1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2016 Intel Corporation
13 #include <sys/queue.h>
15 #include <rte_string_fns.h>
16 #include <rte_memzone.h>
18 #include <rte_malloc.h>
19 #include <rte_ether.h>
20 #include <rte_ethdev_driver.h>
27 #include "i40e_logs.h"
28 #include "base/i40e_prototype.h"
29 #include "base/i40e_type.h"
30 #include "i40e_ethdev.h"
31 #include "i40e_rxtx.h"
33 #define DEFAULT_TX_RS_THRESH 32
34 #define DEFAULT_TX_FREE_THRESH 32
36 #define I40E_TX_MAX_BURST 32
38 #define I40E_DMA_MEM_ALIGN 4096
40 /* Base address of the HW descriptor ring should be 128B aligned. */
41 #define I40E_RING_BASE_ALIGN 128
43 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
45 #ifdef RTE_LIBRTE_IEEE1588
46 #define I40E_TX_IEEE1588_TMST PKT_TX_IEEE1588_TMST
48 #define I40E_TX_IEEE1588_TMST 0
51 #define I40E_TX_CKSUM_OFFLOAD_MASK ( \
55 PKT_TX_OUTER_IP_CKSUM)
57 #define I40E_TX_OFFLOAD_MASK ( \
64 PKT_TX_OUTER_IP_CKSUM | \
68 PKT_TX_TUNNEL_MASK | \
69 I40E_TX_IEEE1588_TMST)
71 #define I40E_TX_OFFLOAD_NOTSUP_MASK \
72 (PKT_TX_OFFLOAD_MASK ^ I40E_TX_OFFLOAD_MASK)
75 i40e_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union i40e_rx_desc *rxdp)
77 if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
78 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
79 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
81 rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
82 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
83 rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1));
87 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
88 if (rte_le_to_cpu_16(rxdp->wb.qword2.ext_status) &
89 (1 << I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT)) {
90 mb->ol_flags |= PKT_RX_QINQ_STRIPPED | PKT_RX_QINQ |
91 PKT_RX_VLAN_STRIPPED | PKT_RX_VLAN;
92 mb->vlan_tci_outer = mb->vlan_tci;
93 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2);
94 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
95 rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_1),
96 rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2));
98 mb->vlan_tci_outer = 0;
101 PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
102 mb->vlan_tci, mb->vlan_tci_outer);
105 /* Translate the rx descriptor status to pkt flags */
106 static inline uint64_t
107 i40e_rxd_status_to_pkt_flags(uint64_t qword)
111 /* Check if RSS_HASH */
112 flags = (((qword >> I40E_RX_DESC_STATUS_FLTSTAT_SHIFT) &
113 I40E_RX_DESC_FLTSTAT_RSS_HASH) ==
114 I40E_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;
116 /* Check if FDIR Match */
117 flags |= (qword & (1 << I40E_RX_DESC_STATUS_FLM_SHIFT) ?
123 static inline uint64_t
124 i40e_rxd_error_to_pkt_flags(uint64_t qword)
127 uint64_t error_bits = (qword >> I40E_RXD_QW1_ERROR_SHIFT);
129 #define I40E_RX_ERR_BITS 0x3f
130 if (likely((error_bits & I40E_RX_ERR_BITS) == 0)) {
131 flags |= (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD);
135 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_IPE_SHIFT)))
136 flags |= PKT_RX_IP_CKSUM_BAD;
138 flags |= PKT_RX_IP_CKSUM_GOOD;
140 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT)))
141 flags |= PKT_RX_L4_CKSUM_BAD;
143 flags |= PKT_RX_L4_CKSUM_GOOD;
145 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT)))
146 flags |= PKT_RX_EIP_CKSUM_BAD;
151 /* Function to check and set the ieee1588 timesync index and get the
154 #ifdef RTE_LIBRTE_IEEE1588
155 static inline uint64_t
156 i40e_get_iee15888_flags(struct rte_mbuf *mb, uint64_t qword)
158 uint64_t pkt_flags = 0;
159 uint16_t tsyn = (qword & (I40E_RXD_QW1_STATUS_TSYNVALID_MASK
160 | I40E_RXD_QW1_STATUS_TSYNINDX_MASK))
161 >> I40E_RX_DESC_STATUS_TSYNINDX_SHIFT;
163 if ((mb->packet_type & RTE_PTYPE_L2_MASK)
164 == RTE_PTYPE_L2_ETHER_TIMESYNC)
165 pkt_flags = PKT_RX_IEEE1588_PTP;
167 pkt_flags |= PKT_RX_IEEE1588_TMST;
168 mb->timesync = tsyn & 0x03;
175 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK 0x03
176 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID 0x01
177 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX 0x02
178 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK 0x03
179 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX 0x01
181 static inline uint64_t
182 i40e_rxd_build_fdir(volatile union i40e_rx_desc *rxdp, struct rte_mbuf *mb)
185 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
186 uint16_t flexbh, flexbl;
188 flexbh = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
189 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT) &
190 I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK;
191 flexbl = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
192 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT) &
193 I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK;
196 if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID) {
198 rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.fd_id);
199 flags |= PKT_RX_FDIR_ID;
200 } else if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX) {
202 rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.flex_bytes_hi);
203 flags |= PKT_RX_FDIR_FLX;
205 if (flexbl == I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX) {
207 rte_le_to_cpu_32(rxdp->wb.qword3.lo_dword.flex_bytes_lo);
208 flags |= PKT_RX_FDIR_FLX;
212 rte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.fd_id);
213 flags |= PKT_RX_FDIR_ID;
219 i40e_parse_tunneling_params(uint64_t ol_flags,
220 union i40e_tx_offload tx_offload,
221 uint32_t *cd_tunneling)
223 /* EIPT: External (outer) IP header type */
224 if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
225 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
226 else if (ol_flags & PKT_TX_OUTER_IPV4)
227 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
228 else if (ol_flags & PKT_TX_OUTER_IPV6)
229 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
231 /* EIPLEN: External (outer) IP header length, in DWords */
232 *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
233 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT;
235 /* L4TUNT: L4 Tunneling Type */
236 switch (ol_flags & PKT_TX_TUNNEL_MASK) {
237 case PKT_TX_TUNNEL_IPIP:
238 /* for non UDP / GRE tunneling, set to 00b */
240 case PKT_TX_TUNNEL_VXLAN:
241 case PKT_TX_TUNNEL_GENEVE:
242 *cd_tunneling |= I40E_TXD_CTX_UDP_TUNNELING;
244 case PKT_TX_TUNNEL_GRE:
245 *cd_tunneling |= I40E_TXD_CTX_GRE_TUNNELING;
248 PMD_TX_LOG(ERR, "Tunnel type not supported");
252 /* L4TUNLEN: L4 Tunneling Length, in Words
254 * We depend on app to set rte_mbuf.l2_len correctly.
255 * For IP in GRE it should be set to the length of the GRE
257 * for MAC in GRE or MAC in UDP it should be set to the length
258 * of the GRE or UDP headers plus the inner MAC up to including
259 * its last Ethertype.
261 *cd_tunneling |= (tx_offload.l2_len >> 1) <<
262 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
266 i40e_txd_enable_checksum(uint64_t ol_flags,
269 union i40e_tx_offload tx_offload)
272 if (ol_flags & PKT_TX_TUNNEL_MASK)
273 *td_offset |= (tx_offload.outer_l2_len >> 1)
274 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
276 *td_offset |= (tx_offload.l2_len >> 1)
277 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
279 /* Enable L3 checksum offloads */
280 if (ol_flags & PKT_TX_IP_CKSUM) {
281 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
282 *td_offset |= (tx_offload.l3_len >> 2)
283 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
284 } else if (ol_flags & PKT_TX_IPV4) {
285 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
286 *td_offset |= (tx_offload.l3_len >> 2)
287 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
288 } else if (ol_flags & PKT_TX_IPV6) {
289 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
290 *td_offset |= (tx_offload.l3_len >> 2)
291 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
294 if (ol_flags & PKT_TX_TCP_SEG) {
295 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
296 *td_offset |= (tx_offload.l4_len >> 2)
297 << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
301 /* Enable L4 checksum offloads */
302 switch (ol_flags & PKT_TX_L4_MASK) {
303 case PKT_TX_TCP_CKSUM:
304 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
305 *td_offset |= (sizeof(struct rte_tcp_hdr) >> 2) <<
306 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
308 case PKT_TX_SCTP_CKSUM:
309 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
310 *td_offset |= (sizeof(struct rte_sctp_hdr) >> 2) <<
311 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
313 case PKT_TX_UDP_CKSUM:
314 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
315 *td_offset |= (sizeof(struct rte_udp_hdr) >> 2) <<
316 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
323 /* Construct the tx flags */
324 static inline uint64_t
325 i40e_build_ctob(uint32_t td_cmd,
330 return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
331 ((uint64_t)td_cmd << I40E_TXD_QW1_CMD_SHIFT) |
332 ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
333 ((uint64_t)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
334 ((uint64_t)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT));
338 i40e_xmit_cleanup(struct i40e_tx_queue *txq)
340 struct i40e_tx_entry *sw_ring = txq->sw_ring;
341 volatile struct i40e_tx_desc *txd = txq->tx_ring;
342 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
343 uint16_t nb_tx_desc = txq->nb_tx_desc;
344 uint16_t desc_to_clean_to;
345 uint16_t nb_tx_to_clean;
347 desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
348 if (desc_to_clean_to >= nb_tx_desc)
349 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
351 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
352 if ((txd[desc_to_clean_to].cmd_type_offset_bsz &
353 rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
354 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE)) {
355 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
356 "(port=%d queue=%d)", desc_to_clean_to,
357 txq->port_id, txq->queue_id);
361 if (last_desc_cleaned > desc_to_clean_to)
362 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
365 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
368 txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
370 txq->last_desc_cleaned = desc_to_clean_to;
371 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
377 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
378 check_rx_burst_bulk_alloc_preconditions(struct i40e_rx_queue *rxq)
380 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct i40e_rx_queue *rxq)
385 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
386 if (!(rxq->rx_free_thresh >= RTE_PMD_I40E_RX_MAX_BURST)) {
387 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
388 "rxq->rx_free_thresh=%d, "
389 "RTE_PMD_I40E_RX_MAX_BURST=%d",
390 rxq->rx_free_thresh, RTE_PMD_I40E_RX_MAX_BURST);
392 } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
393 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
394 "rxq->rx_free_thresh=%d, "
395 "rxq->nb_rx_desc=%d",
396 rxq->rx_free_thresh, rxq->nb_rx_desc);
398 } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
399 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
400 "rxq->nb_rx_desc=%d, "
401 "rxq->rx_free_thresh=%d",
402 rxq->nb_rx_desc, rxq->rx_free_thresh);
412 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
413 #define I40E_LOOK_AHEAD 8
414 #if (I40E_LOOK_AHEAD != 8)
415 #error "PMD I40E: I40E_LOOK_AHEAD must be 8\n"
418 i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq)
420 volatile union i40e_rx_desc *rxdp;
421 struct i40e_rx_entry *rxep;
426 int32_t s[I40E_LOOK_AHEAD], nb_dd;
427 int32_t i, j, nb_rx = 0;
429 uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
431 rxdp = &rxq->rx_ring[rxq->rx_tail];
432 rxep = &rxq->sw_ring[rxq->rx_tail];
434 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
435 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
436 I40E_RXD_QW1_STATUS_SHIFT;
438 /* Make sure there is at least 1 packet to receive */
439 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
443 * Scan LOOK_AHEAD descriptors at a time to determine which
444 * descriptors reference packets that are ready to be received.
446 for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; i+=I40E_LOOK_AHEAD,
447 rxdp += I40E_LOOK_AHEAD, rxep += I40E_LOOK_AHEAD) {
448 /* Read desc statuses backwards to avoid race condition */
449 for (j = I40E_LOOK_AHEAD - 1; j >= 0; j--) {
450 qword1 = rte_le_to_cpu_64(\
451 rxdp[j].wb.qword1.status_error_len);
452 s[j] = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
453 I40E_RXD_QW1_STATUS_SHIFT;
458 /* Compute how many status bits were set */
459 for (j = 0, nb_dd = 0; j < I40E_LOOK_AHEAD; j++)
460 nb_dd += s[j] & (1 << I40E_RX_DESC_STATUS_DD_SHIFT);
464 /* Translate descriptor info to mbuf parameters */
465 for (j = 0; j < nb_dd; j++) {
467 qword1 = rte_le_to_cpu_64(\
468 rxdp[j].wb.qword1.status_error_len);
469 pkt_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
470 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
471 mb->data_len = pkt_len;
472 mb->pkt_len = pkt_len;
474 i40e_rxd_to_vlan_tci(mb, &rxdp[j]);
475 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
476 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
478 ptype_tbl[(uint8_t)((qword1 &
479 I40E_RXD_QW1_PTYPE_MASK) >>
480 I40E_RXD_QW1_PTYPE_SHIFT)];
481 if (pkt_flags & PKT_RX_RSS_HASH)
482 mb->hash.rss = rte_le_to_cpu_32(\
483 rxdp[j].wb.qword0.hi_dword.rss);
484 if (pkt_flags & PKT_RX_FDIR)
485 pkt_flags |= i40e_rxd_build_fdir(&rxdp[j], mb);
487 #ifdef RTE_LIBRTE_IEEE1588
488 pkt_flags |= i40e_get_iee15888_flags(mb, qword1);
490 mb->ol_flags |= pkt_flags;
494 for (j = 0; j < I40E_LOOK_AHEAD; j++)
495 rxq->rx_stage[i + j] = rxep[j].mbuf;
497 if (nb_dd != I40E_LOOK_AHEAD)
501 /* Clear software ring entries */
502 for (i = 0; i < nb_rx; i++)
503 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
508 static inline uint16_t
509 i40e_rx_fill_from_stage(struct i40e_rx_queue *rxq,
510 struct rte_mbuf **rx_pkts,
514 struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
516 nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
518 for (i = 0; i < nb_pkts; i++)
519 rx_pkts[i] = stage[i];
521 rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
522 rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
528 i40e_rx_alloc_bufs(struct i40e_rx_queue *rxq)
530 volatile union i40e_rx_desc *rxdp;
531 struct i40e_rx_entry *rxep;
533 uint16_t alloc_idx, i;
537 /* Allocate buffers in bulk */
538 alloc_idx = (uint16_t)(rxq->rx_free_trigger -
539 (rxq->rx_free_thresh - 1));
540 rxep = &(rxq->sw_ring[alloc_idx]);
541 diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
542 rxq->rx_free_thresh);
543 if (unlikely(diag != 0)) {
544 PMD_DRV_LOG(ERR, "Failed to get mbufs in bulk");
548 rxdp = &rxq->rx_ring[alloc_idx];
549 for (i = 0; i < rxq->rx_free_thresh; i++) {
550 if (likely(i < (rxq->rx_free_thresh - 1)))
551 /* Prefetch next mbuf */
552 rte_prefetch0(rxep[i + 1].mbuf);
555 rte_mbuf_refcnt_set(mb, 1);
557 mb->data_off = RTE_PKTMBUF_HEADROOM;
559 mb->port = rxq->port_id;
560 dma_addr = rte_cpu_to_le_64(\
561 rte_mbuf_data_iova_default(mb));
562 rxdp[i].read.hdr_addr = 0;
563 rxdp[i].read.pkt_addr = dma_addr;
566 /* Update rx tail regsiter */
567 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger);
569 rxq->rx_free_trigger =
570 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
571 if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
572 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
577 static inline uint16_t
578 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
580 struct i40e_rx_queue *rxq = (struct i40e_rx_queue *)rx_queue;
581 struct rte_eth_dev *dev;
587 if (rxq->rx_nb_avail)
588 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
590 nb_rx = (uint16_t)i40e_rx_scan_hw_ring(rxq);
591 rxq->rx_next_avail = 0;
592 rxq->rx_nb_avail = nb_rx;
593 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
595 if (rxq->rx_tail > rxq->rx_free_trigger) {
596 if (i40e_rx_alloc_bufs(rxq) != 0) {
599 dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
600 dev->data->rx_mbuf_alloc_failed +=
603 rxq->rx_nb_avail = 0;
604 rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
605 for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
606 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
612 if (rxq->rx_tail >= rxq->nb_rx_desc)
615 if (rxq->rx_nb_avail)
616 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
622 i40e_recv_pkts_bulk_alloc(void *rx_queue,
623 struct rte_mbuf **rx_pkts,
626 uint16_t nb_rx = 0, n, count;
628 if (unlikely(nb_pkts == 0))
631 if (likely(nb_pkts <= RTE_PMD_I40E_RX_MAX_BURST))
632 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
635 n = RTE_MIN(nb_pkts, RTE_PMD_I40E_RX_MAX_BURST);
636 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
637 nb_rx = (uint16_t)(nb_rx + count);
638 nb_pkts = (uint16_t)(nb_pkts - count);
647 i40e_recv_pkts_bulk_alloc(void __rte_unused *rx_queue,
648 struct rte_mbuf __rte_unused **rx_pkts,
649 uint16_t __rte_unused nb_pkts)
653 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
656 i40e_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
658 struct i40e_rx_queue *rxq;
659 volatile union i40e_rx_desc *rx_ring;
660 volatile union i40e_rx_desc *rxdp;
661 union i40e_rx_desc rxd;
662 struct i40e_rx_entry *sw_ring;
663 struct i40e_rx_entry *rxe;
664 struct rte_eth_dev *dev;
665 struct rte_mbuf *rxm;
666 struct rte_mbuf *nmb;
670 uint16_t rx_packet_len;
671 uint16_t rx_id, nb_hold;
679 rx_id = rxq->rx_tail;
680 rx_ring = rxq->rx_ring;
681 sw_ring = rxq->sw_ring;
682 ptype_tbl = rxq->vsi->adapter->ptype_tbl;
684 while (nb_rx < nb_pkts) {
685 rxdp = &rx_ring[rx_id];
686 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
687 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
688 >> I40E_RXD_QW1_STATUS_SHIFT;
690 /* Check the DD bit first */
691 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
694 nmb = rte_mbuf_raw_alloc(rxq->mp);
695 if (unlikely(!nmb)) {
696 dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
697 dev->data->rx_mbuf_alloc_failed++;
703 rxe = &sw_ring[rx_id];
705 if (unlikely(rx_id == rxq->nb_rx_desc))
708 /* Prefetch next mbuf */
709 rte_prefetch0(sw_ring[rx_id].mbuf);
712 * When next RX descriptor is on a cache line boundary,
713 * prefetch the next 4 RX descriptors and next 8 pointers
716 if ((rx_id & 0x3) == 0) {
717 rte_prefetch0(&rx_ring[rx_id]);
718 rte_prefetch0(&sw_ring[rx_id]);
723 rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
724 rxdp->read.hdr_addr = 0;
725 rxdp->read.pkt_addr = dma_addr;
727 rx_packet_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
728 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
730 rxm->data_off = RTE_PKTMBUF_HEADROOM;
731 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
734 rxm->pkt_len = rx_packet_len;
735 rxm->data_len = rx_packet_len;
736 rxm->port = rxq->port_id;
738 i40e_rxd_to_vlan_tci(rxm, &rxd);
739 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
740 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
742 ptype_tbl[(uint8_t)((qword1 &
743 I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT)];
744 if (pkt_flags & PKT_RX_RSS_HASH)
746 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
747 if (pkt_flags & PKT_RX_FDIR)
748 pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
750 #ifdef RTE_LIBRTE_IEEE1588
751 pkt_flags |= i40e_get_iee15888_flags(rxm, qword1);
753 rxm->ol_flags |= pkt_flags;
755 rx_pkts[nb_rx++] = rxm;
757 rxq->rx_tail = rx_id;
760 * If the number of free RX descriptors is greater than the RX free
761 * threshold of the queue, advance the receive tail register of queue.
762 * Update that register with the value of the last processed RX
763 * descriptor minus 1.
765 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
766 if (nb_hold > rxq->rx_free_thresh) {
767 rx_id = (uint16_t) ((rx_id == 0) ?
768 (rxq->nb_rx_desc - 1) : (rx_id - 1));
769 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
772 rxq->nb_rx_hold = nb_hold;
778 i40e_recv_scattered_pkts(void *rx_queue,
779 struct rte_mbuf **rx_pkts,
782 struct i40e_rx_queue *rxq = rx_queue;
783 volatile union i40e_rx_desc *rx_ring = rxq->rx_ring;
784 volatile union i40e_rx_desc *rxdp;
785 union i40e_rx_desc rxd;
786 struct i40e_rx_entry *sw_ring = rxq->sw_ring;
787 struct i40e_rx_entry *rxe;
788 struct rte_mbuf *first_seg = rxq->pkt_first_seg;
789 struct rte_mbuf *last_seg = rxq->pkt_last_seg;
790 struct rte_mbuf *nmb, *rxm;
791 uint16_t rx_id = rxq->rx_tail;
792 uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
793 struct rte_eth_dev *dev;
798 uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
800 while (nb_rx < nb_pkts) {
801 rxdp = &rx_ring[rx_id];
802 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
803 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
804 I40E_RXD_QW1_STATUS_SHIFT;
806 /* Check the DD bit */
807 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
810 nmb = rte_mbuf_raw_alloc(rxq->mp);
811 if (unlikely(!nmb)) {
812 dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
813 dev->data->rx_mbuf_alloc_failed++;
819 rxe = &sw_ring[rx_id];
821 if (rx_id == rxq->nb_rx_desc)
824 /* Prefetch next mbuf */
825 rte_prefetch0(sw_ring[rx_id].mbuf);
828 * When next RX descriptor is on a cache line boundary,
829 * prefetch the next 4 RX descriptors and next 8 pointers
832 if ((rx_id & 0x3) == 0) {
833 rte_prefetch0(&rx_ring[rx_id]);
834 rte_prefetch0(&sw_ring[rx_id]);
840 rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
842 /* Set data buffer address and data length of the mbuf */
843 rxdp->read.hdr_addr = 0;
844 rxdp->read.pkt_addr = dma_addr;
845 rx_packet_len = (qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
846 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
847 rxm->data_len = rx_packet_len;
848 rxm->data_off = RTE_PKTMBUF_HEADROOM;
851 * If this is the first buffer of the received packet, set the
852 * pointer to the first mbuf of the packet and initialize its
853 * context. Otherwise, update the total length and the number
854 * of segments of the current scattered packet, and update the
855 * pointer to the last mbuf of the current packet.
859 first_seg->nb_segs = 1;
860 first_seg->pkt_len = rx_packet_len;
863 (uint16_t)(first_seg->pkt_len +
865 first_seg->nb_segs++;
866 last_seg->next = rxm;
870 * If this is not the last buffer of the received packet,
871 * update the pointer to the last mbuf of the current scattered
872 * packet and continue to parse the RX ring.
874 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT))) {
880 * This is the last buffer of the received packet. If the CRC
881 * is not stripped by the hardware:
882 * - Subtract the CRC length from the total packet length.
883 * - If the last buffer only contains the whole CRC or a part
884 * of it, free the mbuf associated to the last buffer. If part
885 * of the CRC is also contained in the previous mbuf, subtract
886 * the length of that CRC part from the data length of the
890 if (unlikely(rxq->crc_len > 0)) {
891 first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
892 if (rx_packet_len <= RTE_ETHER_CRC_LEN) {
893 rte_pktmbuf_free_seg(rxm);
894 first_seg->nb_segs--;
896 (uint16_t)(last_seg->data_len -
897 (RTE_ETHER_CRC_LEN - rx_packet_len));
898 last_seg->next = NULL;
900 rxm->data_len = (uint16_t)(rx_packet_len -
904 first_seg->port = rxq->port_id;
905 first_seg->ol_flags = 0;
906 i40e_rxd_to_vlan_tci(first_seg, &rxd);
907 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
908 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
909 first_seg->packet_type =
910 ptype_tbl[(uint8_t)((qword1 &
911 I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT)];
912 if (pkt_flags & PKT_RX_RSS_HASH)
913 first_seg->hash.rss =
914 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
915 if (pkt_flags & PKT_RX_FDIR)
916 pkt_flags |= i40e_rxd_build_fdir(&rxd, first_seg);
918 #ifdef RTE_LIBRTE_IEEE1588
919 pkt_flags |= i40e_get_iee15888_flags(first_seg, qword1);
921 first_seg->ol_flags |= pkt_flags;
923 /* Prefetch data of first segment, if configured to do so. */
924 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
925 first_seg->data_off));
926 rx_pkts[nb_rx++] = first_seg;
930 /* Record index of the next RX descriptor to probe. */
931 rxq->rx_tail = rx_id;
932 rxq->pkt_first_seg = first_seg;
933 rxq->pkt_last_seg = last_seg;
936 * If the number of free RX descriptors is greater than the RX free
937 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
938 * register. Update the RDT with the value of the last processed RX
939 * descriptor minus 1, to guarantee that the RDT register is never
940 * equal to the RDH register, which creates a "full" ring situtation
941 * from the hardware point of view.
943 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
944 if (nb_hold > rxq->rx_free_thresh) {
945 rx_id = (uint16_t)(rx_id == 0 ?
946 (rxq->nb_rx_desc - 1) : (rx_id - 1));
947 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
950 rxq->nb_rx_hold = nb_hold;
955 /* Check if the context descriptor is needed for TX offloading */
956 static inline uint16_t
957 i40e_calc_context_desc(uint64_t flags)
959 static uint64_t mask = PKT_TX_OUTER_IP_CKSUM |
964 #ifdef RTE_LIBRTE_IEEE1588
965 mask |= PKT_TX_IEEE1588_TMST;
968 return (flags & mask) ? 1 : 0;
971 /* set i40e TSO context descriptor */
972 static inline uint64_t
973 i40e_set_tso_ctx(struct rte_mbuf *mbuf, union i40e_tx_offload tx_offload)
975 uint64_t ctx_desc = 0;
976 uint32_t cd_cmd, hdr_len, cd_tso_len;
978 if (!tx_offload.l4_len) {
979 PMD_DRV_LOG(DEBUG, "L4 length set to 0");
983 hdr_len = tx_offload.l2_len + tx_offload.l3_len + tx_offload.l4_len;
984 hdr_len += (mbuf->ol_flags & PKT_TX_TUNNEL_MASK) ?
985 tx_offload.outer_l2_len + tx_offload.outer_l3_len : 0;
987 cd_cmd = I40E_TX_CTX_DESC_TSO;
988 cd_tso_len = mbuf->pkt_len - hdr_len;
989 ctx_desc |= ((uint64_t)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
990 ((uint64_t)cd_tso_len <<
991 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
992 ((uint64_t)mbuf->tso_segsz <<
993 I40E_TXD_CTX_QW1_MSS_SHIFT);
999 i40e_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1001 struct i40e_tx_queue *txq;
1002 struct i40e_tx_entry *sw_ring;
1003 struct i40e_tx_entry *txe, *txn;
1004 volatile struct i40e_tx_desc *txd;
1005 volatile struct i40e_tx_desc *txr;
1006 struct rte_mbuf *tx_pkt;
1007 struct rte_mbuf *m_seg;
1008 uint32_t cd_tunneling_params;
1019 uint64_t buf_dma_addr;
1020 union i40e_tx_offload tx_offload = {0};
1023 sw_ring = txq->sw_ring;
1025 tx_id = txq->tx_tail;
1026 txe = &sw_ring[tx_id];
1028 /* Check if the descriptor ring needs to be cleaned. */
1029 if (txq->nb_tx_free < txq->tx_free_thresh)
1030 i40e_xmit_cleanup(txq);
1032 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1037 tx_pkt = *tx_pkts++;
1038 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
1040 ol_flags = tx_pkt->ol_flags;
1041 tx_offload.l2_len = tx_pkt->l2_len;
1042 tx_offload.l3_len = tx_pkt->l3_len;
1043 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
1044 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
1045 tx_offload.l4_len = tx_pkt->l4_len;
1046 tx_offload.tso_segsz = tx_pkt->tso_segsz;
1048 /* Calculate the number of context descriptors needed. */
1049 nb_ctx = i40e_calc_context_desc(ol_flags);
1052 * The number of descriptors that must be allocated for
1053 * a packet equals to the number of the segments of that
1054 * packet plus 1 context descriptor if needed.
1056 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
1057 tx_last = (uint16_t)(tx_id + nb_used - 1);
1060 if (tx_last >= txq->nb_tx_desc)
1061 tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
1063 if (nb_used > txq->nb_tx_free) {
1064 if (i40e_xmit_cleanup(txq) != 0) {
1069 if (unlikely(nb_used > txq->tx_rs_thresh)) {
1070 while (nb_used > txq->nb_tx_free) {
1071 if (i40e_xmit_cleanup(txq) != 0) {
1080 /* Descriptor based VLAN insertion */
1081 if (ol_flags & (PKT_TX_VLAN_PKT | PKT_TX_QINQ_PKT)) {
1082 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1083 td_tag = tx_pkt->vlan_tci;
1086 /* Always enable CRC offload insertion */
1087 td_cmd |= I40E_TX_DESC_CMD_ICRC;
1089 /* Fill in tunneling parameters if necessary */
1090 cd_tunneling_params = 0;
1091 if (ol_flags & PKT_TX_TUNNEL_MASK)
1092 i40e_parse_tunneling_params(ol_flags, tx_offload,
1093 &cd_tunneling_params);
1094 /* Enable checksum offloading */
1095 if (ol_flags & I40E_TX_CKSUM_OFFLOAD_MASK)
1096 i40e_txd_enable_checksum(ol_flags, &td_cmd,
1097 &td_offset, tx_offload);
1100 /* Setup TX context descriptor if required */
1101 volatile struct i40e_tx_context_desc *ctx_txd =
1102 (volatile struct i40e_tx_context_desc *)\
1104 uint16_t cd_l2tag2 = 0;
1105 uint64_t cd_type_cmd_tso_mss =
1106 I40E_TX_DESC_DTYPE_CONTEXT;
1108 txn = &sw_ring[txe->next_id];
1109 RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
1110 if (txe->mbuf != NULL) {
1111 rte_pktmbuf_free_seg(txe->mbuf);
1115 /* TSO enabled means no timestamp */
1116 if (ol_flags & PKT_TX_TCP_SEG)
1117 cd_type_cmd_tso_mss |=
1118 i40e_set_tso_ctx(tx_pkt, tx_offload);
1120 #ifdef RTE_LIBRTE_IEEE1588
1121 if (ol_flags & PKT_TX_IEEE1588_TMST)
1122 cd_type_cmd_tso_mss |=
1123 ((uint64_t)I40E_TX_CTX_DESC_TSYN <<
1124 I40E_TXD_CTX_QW1_CMD_SHIFT);
1128 ctx_txd->tunneling_params =
1129 rte_cpu_to_le_32(cd_tunneling_params);
1130 if (ol_flags & PKT_TX_QINQ_PKT) {
1131 cd_l2tag2 = tx_pkt->vlan_tci_outer;
1132 cd_type_cmd_tso_mss |=
1133 ((uint64_t)I40E_TX_CTX_DESC_IL2TAG2 <<
1134 I40E_TXD_CTX_QW1_CMD_SHIFT);
1136 ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
1137 ctx_txd->type_cmd_tso_mss =
1138 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
1140 PMD_TX_LOG(DEBUG, "mbuf: %p, TCD[%u]:\n"
1141 "tunneling_params: %#x;\n"
1144 "type_cmd_tso_mss: %#"PRIx64";\n",
1146 ctx_txd->tunneling_params,
1149 ctx_txd->type_cmd_tso_mss);
1151 txe->last_id = tx_last;
1152 tx_id = txe->next_id;
1159 txn = &sw_ring[txe->next_id];
1162 rte_pktmbuf_free_seg(txe->mbuf);
1165 /* Setup TX Descriptor */
1166 slen = m_seg->data_len;
1167 buf_dma_addr = rte_mbuf_data_iova(m_seg);
1169 PMD_TX_LOG(DEBUG, "mbuf: %p, TDD[%u]:\n"
1170 "buf_dma_addr: %#"PRIx64";\n"
1175 tx_pkt, tx_id, buf_dma_addr,
1176 td_cmd, td_offset, slen, td_tag);
1178 txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
1179 txd->cmd_type_offset_bsz = i40e_build_ctob(td_cmd,
1180 td_offset, slen, td_tag);
1181 txe->last_id = tx_last;
1182 tx_id = txe->next_id;
1184 m_seg = m_seg->next;
1185 } while (m_seg != NULL);
1187 /* The last packet data descriptor needs End Of Packet (EOP) */
1188 td_cmd |= I40E_TX_DESC_CMD_EOP;
1189 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
1190 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
1192 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
1193 PMD_TX_FREE_LOG(DEBUG,
1194 "Setting RS bit on TXD id="
1195 "%4u (port=%d queue=%d)",
1196 tx_last, txq->port_id, txq->queue_id);
1198 td_cmd |= I40E_TX_DESC_CMD_RS;
1200 /* Update txq RS bit counters */
1201 txq->nb_tx_used = 0;
1204 txd->cmd_type_offset_bsz |=
1205 rte_cpu_to_le_64(((uint64_t)td_cmd) <<
1206 I40E_TXD_QW1_CMD_SHIFT);
1210 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
1211 (unsigned) txq->port_id, (unsigned) txq->queue_id,
1212 (unsigned) tx_id, (unsigned) nb_tx);
1214 I40E_PCI_REG_WRITE(txq->qtx_tail, tx_id);
1215 txq->tx_tail = tx_id;
1220 static __rte_always_inline int
1221 i40e_tx_free_bufs(struct i40e_tx_queue *txq)
1223 struct i40e_tx_entry *txep;
1226 if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
1227 rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
1228 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
1231 txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
1233 for (i = 0; i < txq->tx_rs_thresh; i++)
1234 rte_prefetch0((txep + i)->mbuf);
1236 if (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE) {
1237 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1238 rte_mempool_put(txep->mbuf->pool, txep->mbuf);
1242 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1243 rte_pktmbuf_free_seg(txep->mbuf);
1248 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
1249 txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
1250 if (txq->tx_next_dd >= txq->nb_tx_desc)
1251 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1253 return txq->tx_rs_thresh;
1256 /* Populate 4 descriptors with data from 4 mbufs */
1258 tx4(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1263 for (i = 0; i < 4; i++, txdp++, pkts++) {
1264 dma_addr = rte_mbuf_data_iova(*pkts);
1265 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1266 txdp->cmd_type_offset_bsz =
1267 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1268 (*pkts)->data_len, 0);
1272 /* Populate 1 descriptor with data from 1 mbuf */
1274 tx1(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1278 dma_addr = rte_mbuf_data_iova(*pkts);
1279 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1280 txdp->cmd_type_offset_bsz =
1281 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1282 (*pkts)->data_len, 0);
1285 /* Fill hardware descriptor ring with mbuf data */
1287 i40e_tx_fill_hw_ring(struct i40e_tx_queue *txq,
1288 struct rte_mbuf **pkts,
1291 volatile struct i40e_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
1292 struct i40e_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
1293 const int N_PER_LOOP = 4;
1294 const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
1295 int mainpart, leftover;
1298 mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
1299 leftover = (nb_pkts & ((uint32_t) N_PER_LOOP_MASK));
1300 for (i = 0; i < mainpart; i += N_PER_LOOP) {
1301 for (j = 0; j < N_PER_LOOP; ++j) {
1302 (txep + i + j)->mbuf = *(pkts + i + j);
1304 tx4(txdp + i, pkts + i);
1306 if (unlikely(leftover > 0)) {
1307 for (i = 0; i < leftover; ++i) {
1308 (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
1309 tx1(txdp + mainpart + i, pkts + mainpart + i);
1314 static inline uint16_t
1315 tx_xmit_pkts(struct i40e_tx_queue *txq,
1316 struct rte_mbuf **tx_pkts,
1319 volatile struct i40e_tx_desc *txr = txq->tx_ring;
1323 * Begin scanning the H/W ring for done descriptors when the number
1324 * of available descriptors drops below tx_free_thresh. For each done
1325 * descriptor, free the associated buffer.
1327 if (txq->nb_tx_free < txq->tx_free_thresh)
1328 i40e_tx_free_bufs(txq);
1330 /* Use available descriptor only */
1331 nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
1332 if (unlikely(!nb_pkts))
1335 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
1336 if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
1337 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
1338 i40e_tx_fill_hw_ring(txq, tx_pkts, n);
1339 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1340 rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1341 I40E_TXD_QW1_CMD_SHIFT);
1342 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1346 /* Fill hardware descriptor ring with mbuf data */
1347 i40e_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
1348 txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
1350 /* Determin if RS bit needs to be set */
1351 if (txq->tx_tail > txq->tx_next_rs) {
1352 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1353 rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1354 I40E_TXD_QW1_CMD_SHIFT);
1356 (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
1357 if (txq->tx_next_rs >= txq->nb_tx_desc)
1358 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1361 if (txq->tx_tail >= txq->nb_tx_desc)
1364 /* Update the tx tail register */
1365 I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
1371 i40e_xmit_pkts_simple(void *tx_queue,
1372 struct rte_mbuf **tx_pkts,
1377 if (likely(nb_pkts <= I40E_TX_MAX_BURST))
1378 return tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1382 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
1385 ret = tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1386 &tx_pkts[nb_tx], num);
1387 nb_tx = (uint16_t)(nb_tx + ret);
1388 nb_pkts = (uint16_t)(nb_pkts - ret);
1397 i40e_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
1401 struct i40e_tx_queue *txq = (struct i40e_tx_queue *)tx_queue;
1406 num = (uint16_t)RTE_MIN(nb_pkts, txq->tx_rs_thresh);
1407 ret = i40e_xmit_fixed_burst_vec(tx_queue, &tx_pkts[nb_tx],
1418 /*********************************************************************
1422 **********************************************************************/
1424 i40e_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
1431 for (i = 0; i < nb_pkts; i++) {
1433 ol_flags = m->ol_flags;
1435 /* Check for m->nb_segs to not exceed the limits. */
1436 if (!(ol_flags & PKT_TX_TCP_SEG)) {
1437 if (m->nb_segs > I40E_TX_MAX_MTU_SEG ||
1438 m->pkt_len > I40E_FRAME_SIZE_MAX) {
1442 } else if (m->nb_segs > I40E_TX_MAX_SEG ||
1443 m->tso_segsz < I40E_MIN_TSO_MSS ||
1444 m->tso_segsz > I40E_MAX_TSO_MSS ||
1445 m->pkt_len > I40E_TSO_FRAME_SIZE_MAX) {
1446 /* MSS outside the range (256B - 9674B) are considered
1453 if (ol_flags & I40E_TX_OFFLOAD_NOTSUP_MASK) {
1454 rte_errno = ENOTSUP;
1458 /* check the size of packet */
1459 if (m->pkt_len < I40E_TX_MIN_PKT_LEN) {
1464 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
1465 ret = rte_validate_tx_offload(m);
1471 ret = rte_net_intel_cksum_prepare(m);
1481 * Find the VSI the queue belongs to. 'queue_idx' is the queue index
1482 * application used, which assume having sequential ones. But from driver's
1483 * perspective, it's different. For example, q0 belongs to FDIR VSI, q1-q64
1484 * to MAIN VSI, , q65-96 to SRIOV VSIs, q97-128 to VMDQ VSIs. For application
1485 * running on host, q1-64 and q97-128 can be used, total 96 queues. They can
1486 * use queue_idx from 0 to 95 to access queues, while real queue would be
1487 * different. This function will do a queue mapping to find VSI the queue
1490 static struct i40e_vsi*
1491 i40e_pf_get_vsi_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1493 /* the queue in MAIN VSI range */
1494 if (queue_idx < pf->main_vsi->nb_qps)
1495 return pf->main_vsi;
1497 queue_idx -= pf->main_vsi->nb_qps;
1499 /* queue_idx is greater than VMDQ VSIs range */
1500 if (queue_idx > pf->nb_cfg_vmdq_vsi * pf->vmdq_nb_qps - 1) {
1501 PMD_INIT_LOG(ERR, "queue_idx out of range. VMDQ configured?");
1505 return pf->vmdq[queue_idx / pf->vmdq_nb_qps].vsi;
1509 i40e_get_queue_offset_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1511 /* the queue in MAIN VSI range */
1512 if (queue_idx < pf->main_vsi->nb_qps)
1515 /* It's VMDQ queues */
1516 queue_idx -= pf->main_vsi->nb_qps;
1518 if (pf->nb_cfg_vmdq_vsi)
1519 return queue_idx % pf->vmdq_nb_qps;
1521 PMD_INIT_LOG(ERR, "Fail to get queue offset");
1522 return (uint16_t)(-1);
1527 i40e_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1529 struct i40e_rx_queue *rxq;
1531 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1533 PMD_INIT_FUNC_TRACE();
1535 rxq = dev->data->rx_queues[rx_queue_id];
1537 err = i40e_alloc_rx_queue_mbufs(rxq);
1539 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1543 /* Init the RX tail regieter. */
1544 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1546 err = i40e_switch_rx_queue(hw, rxq->reg_idx, TRUE);
1548 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1551 i40e_rx_queue_release_mbufs(rxq);
1552 i40e_reset_rx_queue(rxq);
1555 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1561 i40e_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1563 struct i40e_rx_queue *rxq;
1565 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1567 rxq = dev->data->rx_queues[rx_queue_id];
1570 * rx_queue_id is queue id application refers to, while
1571 * rxq->reg_idx is the real queue index.
1573 err = i40e_switch_rx_queue(hw, rxq->reg_idx, FALSE);
1575 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1579 i40e_rx_queue_release_mbufs(rxq);
1580 i40e_reset_rx_queue(rxq);
1581 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1587 i40e_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1590 struct i40e_tx_queue *txq;
1591 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1593 PMD_INIT_FUNC_TRACE();
1595 txq = dev->data->tx_queues[tx_queue_id];
1598 * tx_queue_id is queue id application refers to, while
1599 * rxq->reg_idx is the real queue index.
1601 err = i40e_switch_tx_queue(hw, txq->reg_idx, TRUE);
1603 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1607 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1613 i40e_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1615 struct i40e_tx_queue *txq;
1617 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1619 txq = dev->data->tx_queues[tx_queue_id];
1622 * tx_queue_id is queue id application refers to, while
1623 * txq->reg_idx is the real queue index.
1625 err = i40e_switch_tx_queue(hw, txq->reg_idx, FALSE);
1627 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u of",
1632 i40e_tx_queue_release_mbufs(txq);
1633 i40e_reset_tx_queue(txq);
1634 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1640 i40e_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1642 static const uint32_t ptypes[] = {
1643 /* refers to i40e_rxd_pkt_type_mapping() */
1645 RTE_PTYPE_L2_ETHER_TIMESYNC,
1646 RTE_PTYPE_L2_ETHER_LLDP,
1647 RTE_PTYPE_L2_ETHER_ARP,
1648 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1649 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
1652 RTE_PTYPE_L4_NONFRAG,
1656 RTE_PTYPE_TUNNEL_GRENAT,
1657 RTE_PTYPE_TUNNEL_IP,
1658 RTE_PTYPE_INNER_L2_ETHER,
1659 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1660 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
1661 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
1662 RTE_PTYPE_INNER_L4_FRAG,
1663 RTE_PTYPE_INNER_L4_ICMP,
1664 RTE_PTYPE_INNER_L4_NONFRAG,
1665 RTE_PTYPE_INNER_L4_SCTP,
1666 RTE_PTYPE_INNER_L4_TCP,
1667 RTE_PTYPE_INNER_L4_UDP,
1671 if (dev->rx_pkt_burst == i40e_recv_pkts ||
1672 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1673 dev->rx_pkt_burst == i40e_recv_pkts_bulk_alloc ||
1675 dev->rx_pkt_burst == i40e_recv_scattered_pkts ||
1676 dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
1677 dev->rx_pkt_burst == i40e_recv_pkts_vec ||
1678 dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec_avx2 ||
1679 dev->rx_pkt_burst == i40e_recv_pkts_vec_avx2)
1685 i40e_dev_first_queue(uint16_t idx, void **queues, int num)
1689 for (i = 0; i < num; i++) {
1690 if (i != idx && queues[i])
1698 i40e_dev_rx_queue_setup_runtime(struct rte_eth_dev *dev,
1699 struct i40e_rx_queue *rxq)
1701 struct i40e_adapter *ad =
1702 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1703 int use_def_burst_func =
1704 check_rx_burst_bulk_alloc_preconditions(rxq);
1706 (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
1707 RTE_PKTMBUF_HEADROOM);
1708 int use_scattered_rx =
1709 (rxq->max_pkt_len > buf_size);
1711 if (i40e_rx_queue_init(rxq) != I40E_SUCCESS) {
1713 "Failed to do RX queue initialization");
1717 if (i40e_dev_first_queue(rxq->queue_id,
1718 dev->data->rx_queues,
1719 dev->data->nb_rx_queues)) {
1721 * If it is the first queue to setup,
1722 * set all flags to default and call
1723 * i40e_set_rx_function.
1725 ad->rx_bulk_alloc_allowed = true;
1726 ad->rx_vec_allowed = true;
1727 dev->data->scattered_rx = use_scattered_rx;
1728 if (use_def_burst_func)
1729 ad->rx_bulk_alloc_allowed = false;
1730 i40e_set_rx_function(dev);
1732 } else if (ad->rx_vec_allowed && !rte_is_power_of_2(rxq->nb_rx_desc)) {
1733 PMD_DRV_LOG(ERR, "Vector mode is allowed, but descriptor"
1734 " number %d of queue %d isn't power of 2",
1735 rxq->nb_rx_desc, rxq->queue_id);
1739 /* check bulk alloc conflict */
1740 if (ad->rx_bulk_alloc_allowed && use_def_burst_func) {
1741 PMD_DRV_LOG(ERR, "Can't use default burst.");
1744 /* check scatterred conflict */
1745 if (!dev->data->scattered_rx && use_scattered_rx) {
1746 PMD_DRV_LOG(ERR, "Scattered rx is required.");
1749 /* check vector conflict */
1750 if (ad->rx_vec_allowed && i40e_rxq_vec_setup(rxq)) {
1751 PMD_DRV_LOG(ERR, "Failed vector rx setup.");
1759 i40e_dev_rx_queue_setup(struct rte_eth_dev *dev,
1762 unsigned int socket_id,
1763 const struct rte_eth_rxconf *rx_conf,
1764 struct rte_mempool *mp)
1766 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1767 struct i40e_adapter *ad =
1768 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1769 struct i40e_vsi *vsi;
1770 struct i40e_pf *pf = NULL;
1771 struct i40e_vf *vf = NULL;
1772 struct i40e_rx_queue *rxq;
1773 const struct rte_memzone *rz;
1776 uint16_t reg_idx, base, bsf, tc_mapping;
1777 int q_offset, use_def_burst_func = 1;
1780 offloads = rx_conf->offloads | dev->data->dev_conf.rxmode.offloads;
1782 if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
1783 vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1787 reg_idx = queue_idx;
1789 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1790 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
1793 q_offset = i40e_get_queue_offset_by_qindex(pf, queue_idx);
1796 reg_idx = vsi->base_queue + q_offset;
1799 if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
1800 (nb_desc > I40E_MAX_RING_DESC) ||
1801 (nb_desc < I40E_MIN_RING_DESC)) {
1802 PMD_DRV_LOG(ERR, "Number (%u) of receive descriptors is "
1803 "invalid", nb_desc);
1807 /* Free memory if needed */
1808 if (dev->data->rx_queues[queue_idx]) {
1809 i40e_dev_rx_queue_release(dev->data->rx_queues[queue_idx]);
1810 dev->data->rx_queues[queue_idx] = NULL;
1813 /* Allocate the rx queue data structure */
1814 rxq = rte_zmalloc_socket("i40e rx queue",
1815 sizeof(struct i40e_rx_queue),
1816 RTE_CACHE_LINE_SIZE,
1819 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
1820 "rx queue data structure");
1824 rxq->nb_rx_desc = nb_desc;
1825 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1826 rxq->queue_id = queue_idx;
1827 rxq->reg_idx = reg_idx;
1828 rxq->port_id = dev->data->port_id;
1829 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
1830 rxq->crc_len = RTE_ETHER_CRC_LEN;
1833 rxq->drop_en = rx_conf->rx_drop_en;
1835 rxq->rx_deferred_start = rx_conf->rx_deferred_start;
1836 rxq->offloads = offloads;
1838 /* Allocate the maximun number of RX ring hardware descriptor. */
1839 len = I40E_MAX_RING_DESC;
1842 * Allocating a little more memory because vectorized/bulk_alloc Rx
1843 * functions doesn't check boundaries each time.
1845 len += RTE_PMD_I40E_RX_MAX_BURST;
1847 ring_size = RTE_ALIGN(len * sizeof(union i40e_rx_desc),
1848 I40E_DMA_MEM_ALIGN);
1850 rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1851 ring_size, I40E_RING_BASE_ALIGN, socket_id);
1853 i40e_dev_rx_queue_release(rxq);
1854 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX");
1858 /* Zero all the descriptors in the ring. */
1859 memset(rz->addr, 0, ring_size);
1861 rxq->rx_ring_phys_addr = rz->iova;
1862 rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
1864 len = (uint16_t)(nb_desc + RTE_PMD_I40E_RX_MAX_BURST);
1866 /* Allocate the software ring. */
1868 rte_zmalloc_socket("i40e rx sw ring",
1869 sizeof(struct i40e_rx_entry) * len,
1870 RTE_CACHE_LINE_SIZE,
1872 if (!rxq->sw_ring) {
1873 i40e_dev_rx_queue_release(rxq);
1874 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW ring");
1878 i40e_reset_rx_queue(rxq);
1881 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1882 if (!(vsi->enabled_tc & (1 << i)))
1884 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
1885 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
1886 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
1887 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
1888 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
1890 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
1894 if (dev->data->dev_started) {
1895 if (i40e_dev_rx_queue_setup_runtime(dev, rxq)) {
1896 i40e_dev_rx_queue_release(rxq);
1900 use_def_burst_func =
1901 check_rx_burst_bulk_alloc_preconditions(rxq);
1902 if (!use_def_burst_func) {
1903 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1905 "Rx Burst Bulk Alloc Preconditions are "
1906 "satisfied. Rx Burst Bulk Alloc function will be "
1907 "used on port=%d, queue=%d.",
1908 rxq->port_id, rxq->queue_id);
1909 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
1912 "Rx Burst Bulk Alloc Preconditions are "
1913 "not satisfied, Scattered Rx is requested, "
1914 "or RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC is "
1915 "not enabled on port=%d, queue=%d.",
1916 rxq->port_id, rxq->queue_id);
1917 ad->rx_bulk_alloc_allowed = false;
1921 dev->data->rx_queues[queue_idx] = rxq;
1926 i40e_dev_rx_queue_release(void *rxq)
1928 struct i40e_rx_queue *q = (struct i40e_rx_queue *)rxq;
1931 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
1935 i40e_rx_queue_release_mbufs(q);
1936 rte_free(q->sw_ring);
1941 i40e_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1943 #define I40E_RXQ_SCAN_INTERVAL 4
1944 volatile union i40e_rx_desc *rxdp;
1945 struct i40e_rx_queue *rxq;
1948 rxq = dev->data->rx_queues[rx_queue_id];
1949 rxdp = &(rxq->rx_ring[rxq->rx_tail]);
1950 while ((desc < rxq->nb_rx_desc) &&
1951 ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1952 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
1953 (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
1955 * Check the DD bit of a rx descriptor of each 4 in a group,
1956 * to avoid checking too frequently and downgrading performance
1959 desc += I40E_RXQ_SCAN_INTERVAL;
1960 rxdp += I40E_RXQ_SCAN_INTERVAL;
1961 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
1962 rxdp = &(rxq->rx_ring[rxq->rx_tail +
1963 desc - rxq->nb_rx_desc]);
1970 i40e_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
1972 volatile union i40e_rx_desc *rxdp;
1973 struct i40e_rx_queue *rxq = rx_queue;
1977 if (unlikely(offset >= rxq->nb_rx_desc)) {
1978 PMD_DRV_LOG(ERR, "Invalid RX descriptor id %u", offset);
1982 desc = rxq->rx_tail + offset;
1983 if (desc >= rxq->nb_rx_desc)
1984 desc -= rxq->nb_rx_desc;
1986 rxdp = &(rxq->rx_ring[desc]);
1988 ret = !!(((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1989 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
1990 (1 << I40E_RX_DESC_STATUS_DD_SHIFT));
1996 i40e_dev_rx_descriptor_status(void *rx_queue, uint16_t offset)
1998 struct i40e_rx_queue *rxq = rx_queue;
1999 volatile uint64_t *status;
2003 if (unlikely(offset >= rxq->nb_rx_desc))
2006 if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
2007 return RTE_ETH_RX_DESC_UNAVAIL;
2009 desc = rxq->rx_tail + offset;
2010 if (desc >= rxq->nb_rx_desc)
2011 desc -= rxq->nb_rx_desc;
2013 status = &rxq->rx_ring[desc].wb.qword1.status_error_len;
2014 mask = rte_le_to_cpu_64((1ULL << I40E_RX_DESC_STATUS_DD_SHIFT)
2015 << I40E_RXD_QW1_STATUS_SHIFT);
2017 return RTE_ETH_RX_DESC_DONE;
2019 return RTE_ETH_RX_DESC_AVAIL;
2023 i40e_dev_tx_descriptor_status(void *tx_queue, uint16_t offset)
2025 struct i40e_tx_queue *txq = tx_queue;
2026 volatile uint64_t *status;
2027 uint64_t mask, expect;
2030 if (unlikely(offset >= txq->nb_tx_desc))
2033 desc = txq->tx_tail + offset;
2034 /* go to next desc that has the RS bit */
2035 desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) *
2037 if (desc >= txq->nb_tx_desc) {
2038 desc -= txq->nb_tx_desc;
2039 if (desc >= txq->nb_tx_desc)
2040 desc -= txq->nb_tx_desc;
2043 status = &txq->tx_ring[desc].cmd_type_offset_bsz;
2044 mask = rte_le_to_cpu_64(I40E_TXD_QW1_DTYPE_MASK);
2045 expect = rte_cpu_to_le_64(
2046 I40E_TX_DESC_DTYPE_DESC_DONE << I40E_TXD_QW1_DTYPE_SHIFT);
2047 if ((*status & mask) == expect)
2048 return RTE_ETH_TX_DESC_DONE;
2050 return RTE_ETH_TX_DESC_FULL;
2054 i40e_dev_tx_queue_setup_runtime(struct rte_eth_dev *dev,
2055 struct i40e_tx_queue *txq)
2057 struct i40e_adapter *ad =
2058 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2060 if (i40e_tx_queue_init(txq) != I40E_SUCCESS) {
2062 "Failed to do TX queue initialization");
2066 if (i40e_dev_first_queue(txq->queue_id,
2067 dev->data->tx_queues,
2068 dev->data->nb_tx_queues)) {
2070 * If it is the first queue to setup,
2071 * set all flags and call
2072 * i40e_set_tx_function.
2074 i40e_set_tx_function_flag(dev, txq);
2075 i40e_set_tx_function(dev);
2079 /* check vector conflict */
2080 if (ad->tx_vec_allowed) {
2081 if (txq->tx_rs_thresh > RTE_I40E_TX_MAX_FREE_BUF_SZ ||
2082 i40e_txq_vec_setup(txq)) {
2083 PMD_DRV_LOG(ERR, "Failed vector tx setup.");
2087 /* check simple tx conflict */
2088 if (ad->tx_simple_allowed) {
2089 if ((txq->offloads & ~DEV_TX_OFFLOAD_MBUF_FAST_FREE) != 0 ||
2090 txq->tx_rs_thresh < RTE_PMD_I40E_TX_MAX_BURST) {
2091 PMD_DRV_LOG(ERR, "No-simple tx is required.");
2100 i40e_dev_tx_queue_setup(struct rte_eth_dev *dev,
2103 unsigned int socket_id,
2104 const struct rte_eth_txconf *tx_conf)
2106 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2107 struct i40e_vsi *vsi;
2108 struct i40e_pf *pf = NULL;
2109 struct i40e_vf *vf = NULL;
2110 struct i40e_tx_queue *txq;
2111 const struct rte_memzone *tz;
2113 uint16_t tx_rs_thresh, tx_free_thresh;
2114 uint16_t reg_idx, i, base, bsf, tc_mapping;
2118 offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
2120 if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
2121 vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2125 reg_idx = queue_idx;
2127 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2128 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
2131 q_offset = i40e_get_queue_offset_by_qindex(pf, queue_idx);
2134 reg_idx = vsi->base_queue + q_offset;
2137 if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
2138 (nb_desc > I40E_MAX_RING_DESC) ||
2139 (nb_desc < I40E_MIN_RING_DESC)) {
2140 PMD_DRV_LOG(ERR, "Number (%u) of transmit descriptors is "
2141 "invalid", nb_desc);
2146 * The following two parameters control the setting of the RS bit on
2147 * transmit descriptors. TX descriptors will have their RS bit set
2148 * after txq->tx_rs_thresh descriptors have been used. The TX
2149 * descriptor ring will be cleaned after txq->tx_free_thresh
2150 * descriptors are used or if the number of descriptors required to
2151 * transmit a packet is greater than the number of free TX descriptors.
2153 * The following constraints must be satisfied:
2154 * - tx_rs_thresh must be greater than 0.
2155 * - tx_rs_thresh must be less than the size of the ring minus 2.
2156 * - tx_rs_thresh must be less than or equal to tx_free_thresh.
2157 * - tx_rs_thresh must be a divisor of the ring size.
2158 * - tx_free_thresh must be greater than 0.
2159 * - tx_free_thresh must be less than the size of the ring minus 3.
2160 * - tx_free_thresh + tx_rs_thresh must not exceed nb_desc.
2162 * One descriptor in the TX ring is used as a sentinel to avoid a H/W
2163 * race condition, hence the maximum threshold constraints. When set
2164 * to zero use default values.
2166 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
2167 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
2168 /* force tx_rs_thresh to adapt an aggresive tx_free_thresh */
2169 tx_rs_thresh = (DEFAULT_TX_RS_THRESH + tx_free_thresh > nb_desc) ?
2170 nb_desc - tx_free_thresh : DEFAULT_TX_RS_THRESH;
2171 if (tx_conf->tx_rs_thresh > 0)
2172 tx_rs_thresh = tx_conf->tx_rs_thresh;
2173 if (tx_rs_thresh + tx_free_thresh > nb_desc) {
2174 PMD_INIT_LOG(ERR, "tx_rs_thresh + tx_free_thresh must not "
2175 "exceed nb_desc. (tx_rs_thresh=%u "
2176 "tx_free_thresh=%u nb_desc=%u port=%d queue=%d)",
2177 (unsigned int)tx_rs_thresh,
2178 (unsigned int)tx_free_thresh,
2179 (unsigned int)nb_desc,
2180 (int)dev->data->port_id,
2182 return I40E_ERR_PARAM;
2184 if (tx_rs_thresh >= (nb_desc - 2)) {
2185 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
2186 "number of TX descriptors minus 2. "
2187 "(tx_rs_thresh=%u port=%d queue=%d)",
2188 (unsigned int)tx_rs_thresh,
2189 (int)dev->data->port_id,
2191 return I40E_ERR_PARAM;
2193 if (tx_free_thresh >= (nb_desc - 3)) {
2194 PMD_INIT_LOG(ERR, "tx_free_thresh must be less than the "
2195 "number of TX descriptors minus 3. "
2196 "(tx_free_thresh=%u port=%d queue=%d)",
2197 (unsigned int)tx_free_thresh,
2198 (int)dev->data->port_id,
2200 return I40E_ERR_PARAM;
2202 if (tx_rs_thresh > tx_free_thresh) {
2203 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
2204 "equal to tx_free_thresh. (tx_free_thresh=%u"
2205 " tx_rs_thresh=%u port=%d queue=%d)",
2206 (unsigned int)tx_free_thresh,
2207 (unsigned int)tx_rs_thresh,
2208 (int)dev->data->port_id,
2210 return I40E_ERR_PARAM;
2212 if ((nb_desc % tx_rs_thresh) != 0) {
2213 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
2214 "number of TX descriptors. (tx_rs_thresh=%u"
2215 " port=%d queue=%d)",
2216 (unsigned int)tx_rs_thresh,
2217 (int)dev->data->port_id,
2219 return I40E_ERR_PARAM;
2221 if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
2222 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
2223 "tx_rs_thresh is greater than 1. "
2224 "(tx_rs_thresh=%u port=%d queue=%d)",
2225 (unsigned int)tx_rs_thresh,
2226 (int)dev->data->port_id,
2228 return I40E_ERR_PARAM;
2231 /* Free memory if needed. */
2232 if (dev->data->tx_queues[queue_idx]) {
2233 i40e_dev_tx_queue_release(dev->data->tx_queues[queue_idx]);
2234 dev->data->tx_queues[queue_idx] = NULL;
2237 /* Allocate the TX queue data structure. */
2238 txq = rte_zmalloc_socket("i40e tx queue",
2239 sizeof(struct i40e_tx_queue),
2240 RTE_CACHE_LINE_SIZE,
2243 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2244 "tx queue structure");
2248 /* Allocate TX hardware ring descriptors. */
2249 ring_size = sizeof(struct i40e_tx_desc) * I40E_MAX_RING_DESC;
2250 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2251 tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
2252 ring_size, I40E_RING_BASE_ALIGN, socket_id);
2254 i40e_dev_tx_queue_release(txq);
2255 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX");
2259 txq->nb_tx_desc = nb_desc;
2260 txq->tx_rs_thresh = tx_rs_thresh;
2261 txq->tx_free_thresh = tx_free_thresh;
2262 txq->pthresh = tx_conf->tx_thresh.pthresh;
2263 txq->hthresh = tx_conf->tx_thresh.hthresh;
2264 txq->wthresh = tx_conf->tx_thresh.wthresh;
2265 txq->queue_id = queue_idx;
2266 txq->reg_idx = reg_idx;
2267 txq->port_id = dev->data->port_id;
2268 txq->offloads = offloads;
2270 txq->tx_deferred_start = tx_conf->tx_deferred_start;
2272 txq->tx_ring_phys_addr = tz->iova;
2273 txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2275 /* Allocate software ring */
2277 rte_zmalloc_socket("i40e tx sw ring",
2278 sizeof(struct i40e_tx_entry) * nb_desc,
2279 RTE_CACHE_LINE_SIZE,
2281 if (!txq->sw_ring) {
2282 i40e_dev_tx_queue_release(txq);
2283 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW TX ring");
2287 i40e_reset_tx_queue(txq);
2290 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2291 if (!(vsi->enabled_tc & (1 << i)))
2293 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
2294 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
2295 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
2296 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
2297 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
2299 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
2303 if (dev->data->dev_started) {
2304 if (i40e_dev_tx_queue_setup_runtime(dev, txq)) {
2305 i40e_dev_tx_queue_release(txq);
2310 * Use a simple TX queue without offloads or
2311 * multi segs if possible
2313 i40e_set_tx_function_flag(dev, txq);
2315 dev->data->tx_queues[queue_idx] = txq;
2321 i40e_dev_tx_queue_release(void *txq)
2323 struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
2326 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
2330 i40e_tx_queue_release_mbufs(q);
2331 rte_free(q->sw_ring);
2335 const struct rte_memzone *
2336 i40e_memzone_reserve(const char *name, uint32_t len, int socket_id)
2338 const struct rte_memzone *mz;
2340 mz = rte_memzone_lookup(name);
2344 mz = rte_memzone_reserve_aligned(name, len, socket_id,
2345 RTE_MEMZONE_IOVA_CONTIG, I40E_RING_BASE_ALIGN);
2350 i40e_rx_queue_release_mbufs(struct i40e_rx_queue *rxq)
2354 /* SSE Vector driver has a different way of releasing mbufs. */
2355 if (rxq->rx_using_sse) {
2356 i40e_rx_queue_release_mbufs_vec(rxq);
2360 if (!rxq->sw_ring) {
2361 PMD_DRV_LOG(DEBUG, "Pointer to sw_ring is NULL");
2365 for (i = 0; i < rxq->nb_rx_desc; i++) {
2366 if (rxq->sw_ring[i].mbuf) {
2367 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2368 rxq->sw_ring[i].mbuf = NULL;
2371 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2372 if (rxq->rx_nb_avail == 0)
2374 for (i = 0; i < rxq->rx_nb_avail; i++) {
2375 struct rte_mbuf *mbuf;
2377 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
2378 rte_pktmbuf_free_seg(mbuf);
2380 rxq->rx_nb_avail = 0;
2381 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2385 i40e_reset_rx_queue(struct i40e_rx_queue *rxq)
2391 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
2395 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2396 if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
2397 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_I40E_RX_MAX_BURST);
2399 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2400 len = rxq->nb_rx_desc;
2402 for (i = 0; i < len * sizeof(union i40e_rx_desc); i++)
2403 ((volatile char *)rxq->rx_ring)[i] = 0;
2405 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2406 for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; ++i)
2407 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2409 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2410 rxq->rx_nb_avail = 0;
2411 rxq->rx_next_avail = 0;
2412 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2413 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2415 rxq->nb_rx_hold = 0;
2416 rxq->pkt_first_seg = NULL;
2417 rxq->pkt_last_seg = NULL;
2419 rxq->rxrearm_start = 0;
2420 rxq->rxrearm_nb = 0;
2424 i40e_tx_queue_release_mbufs(struct i40e_tx_queue *txq)
2426 struct rte_eth_dev *dev;
2429 if (!txq || !txq->sw_ring) {
2430 PMD_DRV_LOG(DEBUG, "Pointer to txq or sw_ring is NULL");
2434 dev = &rte_eth_devices[txq->port_id];
2437 * vPMD tx will not set sw_ring's mbuf to NULL after free,
2438 * so need to free remains more carefully.
2440 if (dev->tx_pkt_burst == i40e_xmit_pkts_vec_avx2 ||
2441 dev->tx_pkt_burst == i40e_xmit_pkts_vec) {
2442 i = txq->tx_next_dd - txq->tx_rs_thresh + 1;
2443 if (txq->tx_tail < i) {
2444 for (; i < txq->nb_tx_desc; i++) {
2445 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2446 txq->sw_ring[i].mbuf = NULL;
2450 for (; i < txq->tx_tail; i++) {
2451 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2452 txq->sw_ring[i].mbuf = NULL;
2455 for (i = 0; i < txq->nb_tx_desc; i++) {
2456 if (txq->sw_ring[i].mbuf) {
2457 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2458 txq->sw_ring[i].mbuf = NULL;
2465 i40e_reset_tx_queue(struct i40e_tx_queue *txq)
2467 struct i40e_tx_entry *txe;
2468 uint16_t i, prev, size;
2471 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
2476 size = sizeof(struct i40e_tx_desc) * txq->nb_tx_desc;
2477 for (i = 0; i < size; i++)
2478 ((volatile char *)txq->tx_ring)[i] = 0;
2480 prev = (uint16_t)(txq->nb_tx_desc - 1);
2481 for (i = 0; i < txq->nb_tx_desc; i++) {
2482 volatile struct i40e_tx_desc *txd = &txq->tx_ring[i];
2484 txd->cmd_type_offset_bsz =
2485 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE);
2488 txe[prev].next_id = i;
2492 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2493 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2496 txq->nb_tx_used = 0;
2498 txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
2499 txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
2502 /* Init the TX queue in hardware */
2504 i40e_tx_queue_init(struct i40e_tx_queue *txq)
2506 enum i40e_status_code err = I40E_SUCCESS;
2507 struct i40e_vsi *vsi = txq->vsi;
2508 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2509 uint16_t pf_q = txq->reg_idx;
2510 struct i40e_hmc_obj_txq tx_ctx;
2513 /* clear the context structure first */
2514 memset(&tx_ctx, 0, sizeof(tx_ctx));
2515 tx_ctx.new_context = 1;
2516 tx_ctx.base = txq->tx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2517 tx_ctx.qlen = txq->nb_tx_desc;
2519 #ifdef RTE_LIBRTE_IEEE1588
2520 tx_ctx.timesync_ena = 1;
2522 tx_ctx.rdylist = rte_le_to_cpu_16(vsi->info.qs_handle[txq->dcb_tc]);
2523 if (vsi->type == I40E_VSI_FDIR)
2524 tx_ctx.fd_ena = TRUE;
2526 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2527 if (err != I40E_SUCCESS) {
2528 PMD_DRV_LOG(ERR, "Failure of clean lan tx queue context");
2532 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2533 if (err != I40E_SUCCESS) {
2534 PMD_DRV_LOG(ERR, "Failure of set lan tx queue context");
2538 /* Now associate this queue with this PCI function */
2539 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
2540 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2541 I40E_QTX_CTL_PF_INDX_MASK);
2542 I40E_WRITE_REG(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2543 I40E_WRITE_FLUSH(hw);
2545 txq->qtx_tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2551 i40e_alloc_rx_queue_mbufs(struct i40e_rx_queue *rxq)
2553 struct i40e_rx_entry *rxe = rxq->sw_ring;
2557 for (i = 0; i < rxq->nb_rx_desc; i++) {
2558 volatile union i40e_rx_desc *rxd;
2559 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mp);
2561 if (unlikely(!mbuf)) {
2562 PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
2566 rte_mbuf_refcnt_set(mbuf, 1);
2568 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2570 mbuf->port = rxq->port_id;
2573 rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
2575 rxd = &rxq->rx_ring[i];
2576 rxd->read.pkt_addr = dma_addr;
2577 rxd->read.hdr_addr = 0;
2578 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2579 rxd->read.rsvd1 = 0;
2580 rxd->read.rsvd2 = 0;
2581 #endif /* RTE_LIBRTE_I40E_16BYTE_RX_DESC */
2590 * Calculate the buffer length, and check the jumbo frame
2591 * and maximum packet length.
2594 i40e_rx_queue_config(struct i40e_rx_queue *rxq)
2596 struct i40e_pf *pf = I40E_VSI_TO_PF(rxq->vsi);
2597 struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2598 struct rte_eth_dev_data *data = pf->dev_data;
2599 uint16_t buf_size, len;
2601 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2602 RTE_PKTMBUF_HEADROOM);
2604 switch (pf->flags & (I40E_FLAG_HEADER_SPLIT_DISABLED |
2605 I40E_FLAG_HEADER_SPLIT_ENABLED)) {
2606 case I40E_FLAG_HEADER_SPLIT_ENABLED: /* Not supported */
2607 rxq->rx_hdr_len = RTE_ALIGN(I40E_RXBUF_SZ_1024,
2608 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2609 rxq->rx_buf_len = RTE_ALIGN(I40E_RXBUF_SZ_2048,
2610 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2611 rxq->hs_mode = i40e_header_split_enabled;
2613 case I40E_FLAG_HEADER_SPLIT_DISABLED:
2615 rxq->rx_hdr_len = 0;
2616 rxq->rx_buf_len = RTE_ALIGN_FLOOR(buf_size,
2617 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2618 rxq->hs_mode = i40e_header_split_none;
2622 len = hw->func_caps.rx_buf_chain_len * rxq->rx_buf_len;
2623 rxq->max_pkt_len = RTE_MIN(len, data->dev_conf.rxmode.max_rx_pkt_len);
2624 if (data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
2625 if (rxq->max_pkt_len <= RTE_ETHER_MAX_LEN ||
2626 rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
2627 PMD_DRV_LOG(ERR, "maximum packet length must "
2628 "be larger than %u and smaller than %u,"
2629 "as jumbo frame is enabled",
2630 (uint32_t)RTE_ETHER_MAX_LEN,
2631 (uint32_t)I40E_FRAME_SIZE_MAX);
2632 return I40E_ERR_CONFIG;
2635 if (rxq->max_pkt_len < RTE_ETHER_MIN_LEN ||
2636 rxq->max_pkt_len > RTE_ETHER_MAX_LEN) {
2637 PMD_DRV_LOG(ERR, "maximum packet length must be "
2638 "larger than %u and smaller than %u, "
2639 "as jumbo frame is disabled",
2640 (uint32_t)RTE_ETHER_MIN_LEN,
2641 (uint32_t)RTE_ETHER_MAX_LEN);
2642 return I40E_ERR_CONFIG;
2649 /* Init the RX queue in hardware */
2651 i40e_rx_queue_init(struct i40e_rx_queue *rxq)
2653 int err = I40E_SUCCESS;
2654 struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2655 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(rxq->vsi);
2656 uint16_t pf_q = rxq->reg_idx;
2658 struct i40e_hmc_obj_rxq rx_ctx;
2660 err = i40e_rx_queue_config(rxq);
2662 PMD_DRV_LOG(ERR, "Failed to config RX queue");
2666 /* Clear the context structure first */
2667 memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
2668 rx_ctx.dbuff = rxq->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2669 rx_ctx.hbuff = rxq->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2671 rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2672 rx_ctx.qlen = rxq->nb_rx_desc;
2673 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2676 rx_ctx.dtype = rxq->hs_mode;
2678 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_ALL;
2680 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
2681 rx_ctx.rxmax = rxq->max_pkt_len;
2682 rx_ctx.tphrdesc_ena = 1;
2683 rx_ctx.tphwdesc_ena = 1;
2684 rx_ctx.tphdata_ena = 1;
2685 rx_ctx.tphhead_ena = 1;
2686 rx_ctx.lrxqthresh = 2;
2687 rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
2689 /* showiv indicates if inner VLAN is stripped inside of tunnel
2690 * packet. When set it to 1, vlan information is stripped from
2691 * the inner header, but the hardware does not put it in the
2692 * descriptor. So set it zero by default.
2697 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2698 if (err != I40E_SUCCESS) {
2699 PMD_DRV_LOG(ERR, "Failed to clear LAN RX queue context");
2702 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2703 if (err != I40E_SUCCESS) {
2704 PMD_DRV_LOG(ERR, "Failed to set LAN RX queue context");
2708 rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2710 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2711 RTE_PKTMBUF_HEADROOM);
2713 /* Check if scattered RX needs to be used. */
2714 if (rxq->max_pkt_len > buf_size)
2715 dev_data->scattered_rx = 1;
2717 /* Init the RX tail regieter. */
2718 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
2724 i40e_dev_clear_queues(struct rte_eth_dev *dev)
2728 PMD_INIT_FUNC_TRACE();
2730 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2731 if (!dev->data->tx_queues[i])
2733 i40e_tx_queue_release_mbufs(dev->data->tx_queues[i]);
2734 i40e_reset_tx_queue(dev->data->tx_queues[i]);
2737 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2738 if (!dev->data->rx_queues[i])
2740 i40e_rx_queue_release_mbufs(dev->data->rx_queues[i]);
2741 i40e_reset_rx_queue(dev->data->rx_queues[i]);
2746 i40e_dev_free_queues(struct rte_eth_dev *dev)
2750 PMD_INIT_FUNC_TRACE();
2752 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2753 if (!dev->data->rx_queues[i])
2755 i40e_dev_rx_queue_release(dev->data->rx_queues[i]);
2756 dev->data->rx_queues[i] = NULL;
2759 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2760 if (!dev->data->tx_queues[i])
2762 i40e_dev_tx_queue_release(dev->data->tx_queues[i]);
2763 dev->data->tx_queues[i] = NULL;
2767 #define I40E_FDIR_NUM_TX_DESC I40E_MIN_RING_DESC
2768 #define I40E_FDIR_NUM_RX_DESC I40E_MIN_RING_DESC
2770 enum i40e_status_code
2771 i40e_fdir_setup_tx_resources(struct i40e_pf *pf)
2773 struct i40e_tx_queue *txq;
2774 const struct rte_memzone *tz = NULL;
2776 struct rte_eth_dev *dev;
2779 PMD_DRV_LOG(ERR, "PF is not available");
2780 return I40E_ERR_BAD_PTR;
2783 dev = pf->adapter->eth_dev;
2785 /* Allocate the TX queue data structure. */
2786 txq = rte_zmalloc_socket("i40e fdir tx queue",
2787 sizeof(struct i40e_tx_queue),
2788 RTE_CACHE_LINE_SIZE,
2791 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2792 "tx queue structure.");
2793 return I40E_ERR_NO_MEMORY;
2796 /* Allocate TX hardware ring descriptors. */
2797 ring_size = sizeof(struct i40e_tx_desc) * I40E_FDIR_NUM_TX_DESC;
2798 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2800 tz = rte_eth_dma_zone_reserve(dev, "fdir_tx_ring",
2801 I40E_FDIR_QUEUE_ID, ring_size,
2802 I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
2804 i40e_dev_tx_queue_release(txq);
2805 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX.");
2806 return I40E_ERR_NO_MEMORY;
2809 txq->nb_tx_desc = I40E_FDIR_NUM_TX_DESC;
2810 txq->queue_id = I40E_FDIR_QUEUE_ID;
2811 txq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2812 txq->vsi = pf->fdir.fdir_vsi;
2814 txq->tx_ring_phys_addr = tz->iova;
2815 txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2817 * don't need to allocate software ring and reset for the fdir
2818 * program queue just set the queue has been configured.
2823 return I40E_SUCCESS;
2826 enum i40e_status_code
2827 i40e_fdir_setup_rx_resources(struct i40e_pf *pf)
2829 struct i40e_rx_queue *rxq;
2830 const struct rte_memzone *rz = NULL;
2832 struct rte_eth_dev *dev;
2835 PMD_DRV_LOG(ERR, "PF is not available");
2836 return I40E_ERR_BAD_PTR;
2839 dev = pf->adapter->eth_dev;
2841 /* Allocate the RX queue data structure. */
2842 rxq = rte_zmalloc_socket("i40e fdir rx queue",
2843 sizeof(struct i40e_rx_queue),
2844 RTE_CACHE_LINE_SIZE,
2847 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2848 "rx queue structure.");
2849 return I40E_ERR_NO_MEMORY;
2852 /* Allocate RX hardware ring descriptors. */
2853 ring_size = sizeof(union i40e_rx_desc) * I40E_FDIR_NUM_RX_DESC;
2854 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2856 rz = rte_eth_dma_zone_reserve(dev, "fdir_rx_ring",
2857 I40E_FDIR_QUEUE_ID, ring_size,
2858 I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
2860 i40e_dev_rx_queue_release(rxq);
2861 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX.");
2862 return I40E_ERR_NO_MEMORY;
2865 rxq->nb_rx_desc = I40E_FDIR_NUM_RX_DESC;
2866 rxq->queue_id = I40E_FDIR_QUEUE_ID;
2867 rxq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2868 rxq->vsi = pf->fdir.fdir_vsi;
2870 rxq->rx_ring_phys_addr = rz->iova;
2871 memset(rz->addr, 0, I40E_FDIR_NUM_RX_DESC * sizeof(union i40e_rx_desc));
2872 rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
2875 * Don't need to allocate software ring and reset for the fdir
2876 * rx queue, just set the queue has been configured.
2881 return I40E_SUCCESS;
2885 i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2886 struct rte_eth_rxq_info *qinfo)
2888 struct i40e_rx_queue *rxq;
2890 rxq = dev->data->rx_queues[queue_id];
2892 qinfo->mp = rxq->mp;
2893 qinfo->scattered_rx = dev->data->scattered_rx;
2894 qinfo->nb_desc = rxq->nb_rx_desc;
2896 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2897 qinfo->conf.rx_drop_en = rxq->drop_en;
2898 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2899 qinfo->conf.offloads = rxq->offloads;
2903 i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2904 struct rte_eth_txq_info *qinfo)
2906 struct i40e_tx_queue *txq;
2908 txq = dev->data->tx_queues[queue_id];
2910 qinfo->nb_desc = txq->nb_tx_desc;
2912 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2913 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2914 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2916 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2917 qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
2918 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2919 qinfo->conf.offloads = txq->offloads;
2922 static eth_rx_burst_t
2923 i40e_get_latest_rx_vec(bool scatter)
2925 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
2926 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2))
2927 return scatter ? i40e_recv_scattered_pkts_vec_avx2 :
2928 i40e_recv_pkts_vec_avx2;
2930 return scatter ? i40e_recv_scattered_pkts_vec :
2934 static eth_rx_burst_t
2935 i40e_get_recommend_rx_vec(bool scatter)
2937 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
2939 * since AVX frequency can be different to base frequency, limit
2940 * use of AVX2 version to later plaforms, not all those that could
2941 * theoretically run it.
2943 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F))
2944 return scatter ? i40e_recv_scattered_pkts_vec_avx2 :
2945 i40e_recv_pkts_vec_avx2;
2947 return scatter ? i40e_recv_scattered_pkts_vec :
2951 void __attribute__((cold))
2952 i40e_set_rx_function(struct rte_eth_dev *dev)
2954 struct i40e_adapter *ad =
2955 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2956 uint16_t rx_using_sse, i;
2957 /* In order to allow Vector Rx there are a few configuration
2958 * conditions to be met and Rx Bulk Allocation should be allowed.
2960 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2961 if (i40e_rx_vec_dev_conf_condition_check(dev) ||
2962 !ad->rx_bulk_alloc_allowed) {
2963 PMD_INIT_LOG(DEBUG, "Port[%d] doesn't meet"
2964 " Vector Rx preconditions",
2965 dev->data->port_id);
2967 ad->rx_vec_allowed = false;
2969 if (ad->rx_vec_allowed) {
2970 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2971 struct i40e_rx_queue *rxq =
2972 dev->data->rx_queues[i];
2974 if (rxq && i40e_rxq_vec_setup(rxq)) {
2975 ad->rx_vec_allowed = false;
2982 if (ad->rx_vec_allowed) {
2984 PMD_INIT_LOG(DEBUG, "Vector Rx path will be used on port=%d.",
2985 dev->data->port_id);
2986 if (ad->use_latest_vec)
2988 i40e_get_latest_rx_vec(dev->data->scattered_rx);
2991 i40e_get_recommend_rx_vec(dev->data->scattered_rx);
2992 } else if (!dev->data->scattered_rx && ad->rx_bulk_alloc_allowed) {
2993 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
2994 "satisfied. Rx Burst Bulk Alloc function "
2995 "will be used on port=%d.",
2996 dev->data->port_id);
2998 dev->rx_pkt_burst = i40e_recv_pkts_bulk_alloc;
3000 /* Simple Rx Path. */
3001 PMD_INIT_LOG(DEBUG, "Simple Rx path will be used on port=%d.",
3002 dev->data->port_id);
3003 dev->rx_pkt_burst = dev->data->scattered_rx ?
3004 i40e_recv_scattered_pkts :
3008 /* Propagate information about RX function choice through all queues. */
3009 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3011 (dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
3012 dev->rx_pkt_burst == i40e_recv_pkts_vec ||
3013 dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec_avx2 ||
3014 dev->rx_pkt_burst == i40e_recv_pkts_vec_avx2);
3016 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3017 struct i40e_rx_queue *rxq = dev->data->rx_queues[i];
3020 rxq->rx_using_sse = rx_using_sse;
3025 void __attribute__((cold))
3026 i40e_set_tx_function_flag(struct rte_eth_dev *dev, struct i40e_tx_queue *txq)
3028 struct i40e_adapter *ad =
3029 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3031 /* Use a simple Tx queue if possible (only fast free is allowed) */
3032 ad->tx_simple_allowed =
3034 (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE) &&
3035 txq->tx_rs_thresh >= RTE_PMD_I40E_TX_MAX_BURST);
3036 ad->tx_vec_allowed = (ad->tx_simple_allowed &&
3037 txq->tx_rs_thresh <= RTE_I40E_TX_MAX_FREE_BUF_SZ);
3039 if (ad->tx_vec_allowed)
3040 PMD_INIT_LOG(DEBUG, "Vector Tx can be enabled on Tx queue %u.",
3042 else if (ad->tx_simple_allowed)
3043 PMD_INIT_LOG(DEBUG, "Simple Tx can be enabled on Tx queue %u.",
3047 "Neither simple nor vector Tx enabled on Tx queue %u\n",
3051 static eth_tx_burst_t
3052 i40e_get_latest_tx_vec(void)
3054 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
3055 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2))
3056 return i40e_xmit_pkts_vec_avx2;
3058 return i40e_xmit_pkts_vec;
3061 static eth_tx_burst_t
3062 i40e_get_recommend_tx_vec(void)
3064 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
3066 * since AVX frequency can be different to base frequency, limit
3067 * use of AVX2 version to later plaforms, not all those that could
3068 * theoretically run it.
3070 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F))
3071 return i40e_xmit_pkts_vec_avx2;
3073 return i40e_xmit_pkts_vec;
3076 void __attribute__((cold))
3077 i40e_set_tx_function(struct rte_eth_dev *dev)
3079 struct i40e_adapter *ad =
3080 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3083 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3084 if (ad->tx_vec_allowed) {
3085 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3086 struct i40e_tx_queue *txq =
3087 dev->data->tx_queues[i];
3089 if (txq && i40e_txq_vec_setup(txq)) {
3090 ad->tx_vec_allowed = false;
3097 if (ad->tx_simple_allowed) {
3098 if (ad->tx_vec_allowed) {
3099 PMD_INIT_LOG(DEBUG, "Vector tx finally be used.");
3100 if (ad->use_latest_vec)
3102 i40e_get_latest_tx_vec();
3105 i40e_get_recommend_tx_vec();
3107 PMD_INIT_LOG(DEBUG, "Simple tx finally be used.");
3108 dev->tx_pkt_burst = i40e_xmit_pkts_simple;
3110 dev->tx_pkt_prepare = NULL;
3112 PMD_INIT_LOG(DEBUG, "Xmit tx finally be used.");
3113 dev->tx_pkt_burst = i40e_xmit_pkts;
3114 dev->tx_pkt_prepare = i40e_prep_pkts;
3118 void __attribute__((cold))
3119 i40e_set_default_ptype_table(struct rte_eth_dev *dev)
3121 struct i40e_adapter *ad =
3122 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3125 for (i = 0; i < I40E_MAX_PKT_TYPE; i++)
3126 ad->ptype_tbl[i] = i40e_get_default_pkt_type(i);
3129 void __attribute__((cold))
3130 i40e_set_default_pctype_table(struct rte_eth_dev *dev)
3132 struct i40e_adapter *ad =
3133 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3134 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3137 for (i = 0; i < I40E_FLOW_TYPE_MAX; i++)
3138 ad->pctypes_tbl[i] = 0ULL;
3139 ad->flow_types_mask = 0ULL;
3140 ad->pctypes_mask = 0ULL;
3142 ad->pctypes_tbl[RTE_ETH_FLOW_FRAG_IPV4] =
3143 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4);
3144 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
3145 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP);
3146 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
3147 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP);
3148 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
3149 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP);
3150 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
3151 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER);
3152 ad->pctypes_tbl[RTE_ETH_FLOW_FRAG_IPV6] =
3153 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6);
3154 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
3155 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP);
3156 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
3157 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP);
3158 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
3159 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP);
3160 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
3161 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER);
3162 ad->pctypes_tbl[RTE_ETH_FLOW_L2_PAYLOAD] =
3163 (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD);
3165 if (hw->mac.type == I40E_MAC_X722 ||
3166 hw->mac.type == I40E_MAC_X722_VF) {
3167 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_UDP] |=
3168 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP);
3169 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_UDP] |=
3170 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
3171 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_TCP] |=
3172 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
3173 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_UDP] |=
3174 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP);
3175 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_UDP] |=
3176 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
3177 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_TCP] |=
3178 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
3181 for (i = 0; i < I40E_FLOW_TYPE_MAX; i++) {
3182 if (ad->pctypes_tbl[i])
3183 ad->flow_types_mask |= (1ULL << i);
3184 ad->pctypes_mask |= ad->pctypes_tbl[i];
3188 #ifndef RTE_LIBRTE_I40E_INC_VECTOR
3189 /* Stubs needed for linkage when CONFIG_RTE_LIBRTE_I40E_INC_VECTOR is set to 'n' */
3191 i40e_rx_vec_dev_conf_condition_check(struct rte_eth_dev __rte_unused *dev)
3198 void __rte_unused *rx_queue,
3199 struct rte_mbuf __rte_unused **rx_pkts,
3200 uint16_t __rte_unused nb_pkts)
3206 i40e_recv_scattered_pkts_vec(
3207 void __rte_unused *rx_queue,
3208 struct rte_mbuf __rte_unused **rx_pkts,
3209 uint16_t __rte_unused nb_pkts)
3215 i40e_rxq_vec_setup(struct i40e_rx_queue __rte_unused *rxq)
3221 i40e_txq_vec_setup(struct i40e_tx_queue __rte_unused *txq)
3227 i40e_rx_queue_release_mbufs_vec(struct i40e_rx_queue __rte_unused*rxq)
3233 i40e_xmit_fixed_burst_vec(void __rte_unused * tx_queue,
3234 struct rte_mbuf __rte_unused **tx_pkts,
3235 uint16_t __rte_unused nb_pkts)
3239 #endif /* ifndef RTE_LIBRTE_I40E_INC_VECTOR */
3241 #ifndef CC_AVX2_SUPPORT
3243 i40e_recv_pkts_vec_avx2(void __rte_unused *rx_queue,
3244 struct rte_mbuf __rte_unused **rx_pkts,
3245 uint16_t __rte_unused nb_pkts)
3251 i40e_recv_scattered_pkts_vec_avx2(void __rte_unused *rx_queue,
3252 struct rte_mbuf __rte_unused **rx_pkts,
3253 uint16_t __rte_unused nb_pkts)
3259 i40e_xmit_pkts_vec_avx2(void __rte_unused * tx_queue,
3260 struct rte_mbuf __rte_unused **tx_pkts,
3261 uint16_t __rte_unused nb_pkts)
3265 #endif /* ifndef CC_AVX2_SUPPORT */