1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2016 Intel Corporation
13 #include <sys/queue.h>
15 #include <rte_string_fns.h>
16 #include <rte_memzone.h>
18 #include <rte_malloc.h>
19 #include <rte_ether.h>
20 #include <ethdev_driver.h>
28 #include "i40e_logs.h"
29 #include "base/i40e_prototype.h"
30 #include "base/i40e_type.h"
31 #include "i40e_ethdev.h"
32 #include "i40e_rxtx.h"
34 #define DEFAULT_TX_RS_THRESH 32
35 #define DEFAULT_TX_FREE_THRESH 32
37 #define I40E_TX_MAX_BURST 32
39 #define I40E_DMA_MEM_ALIGN 4096
41 /* Base address of the HW descriptor ring should be 128B aligned. */
42 #define I40E_RING_BASE_ALIGN 128
44 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
46 #ifdef RTE_LIBRTE_IEEE1588
47 #define I40E_TX_IEEE1588_TMST PKT_TX_IEEE1588_TMST
49 #define I40E_TX_IEEE1588_TMST 0
52 #define I40E_TX_CKSUM_OFFLOAD_MASK ( \
56 PKT_TX_OUTER_IP_CKSUM)
58 #define I40E_TX_OFFLOAD_MASK ( \
65 PKT_TX_OUTER_IP_CKSUM | \
69 PKT_TX_TUNNEL_MASK | \
70 I40E_TX_IEEE1588_TMST)
72 #define I40E_TX_OFFLOAD_NOTSUP_MASK \
73 (PKT_TX_OFFLOAD_MASK ^ I40E_TX_OFFLOAD_MASK)
75 #define I40E_TX_OFFLOAD_SIMPLE_SUP_MASK ( \
81 #define I40E_TX_OFFLOAD_SIMPLE_NOTSUP_MASK \
82 (PKT_TX_OFFLOAD_MASK ^ I40E_TX_OFFLOAD_SIMPLE_SUP_MASK)
85 i40e_monitor_callback(const uint64_t value,
86 const uint64_t arg[RTE_POWER_MONITOR_OPAQUE_SZ] __rte_unused)
88 const uint64_t m = rte_cpu_to_le_64(1 << I40E_RX_DESC_STATUS_DD_SHIFT);
90 * we expect the DD bit to be set to 1 if this descriptor was already
93 return (value & m) == m ? -1 : 0;
97 i40e_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc)
99 struct i40e_rx_queue *rxq = rx_queue;
100 volatile union i40e_rx_desc *rxdp;
104 rxdp = &rxq->rx_ring[desc];
105 /* watch for changes in status bit */
106 pmc->addr = &rxdp->wb.qword1.status_error_len;
108 /* comparison callback */
109 pmc->fn = i40e_monitor_callback;
111 /* registers are 64-bit */
112 pmc->size = sizeof(uint64_t);
118 i40e_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union i40e_rx_desc *rxdp)
120 if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
121 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
122 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
124 rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
125 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
126 rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1));
130 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
131 if (rte_le_to_cpu_16(rxdp->wb.qword2.ext_status) &
132 (1 << I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT)) {
133 mb->ol_flags |= PKT_RX_QINQ_STRIPPED | PKT_RX_QINQ |
134 PKT_RX_VLAN_STRIPPED | PKT_RX_VLAN;
135 mb->vlan_tci_outer = mb->vlan_tci;
136 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2);
137 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
138 rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_1),
139 rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2));
141 mb->vlan_tci_outer = 0;
144 PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
145 mb->vlan_tci, mb->vlan_tci_outer);
148 /* Translate the rx descriptor status to pkt flags */
149 static inline uint64_t
150 i40e_rxd_status_to_pkt_flags(uint64_t qword)
154 /* Check if RSS_HASH */
155 flags = (((qword >> I40E_RX_DESC_STATUS_FLTSTAT_SHIFT) &
156 I40E_RX_DESC_FLTSTAT_RSS_HASH) ==
157 I40E_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;
159 /* Check if FDIR Match */
160 flags |= (qword & (1 << I40E_RX_DESC_STATUS_FLM_SHIFT) ?
166 static inline uint64_t
167 i40e_rxd_error_to_pkt_flags(uint64_t qword)
170 uint64_t error_bits = (qword >> I40E_RXD_QW1_ERROR_SHIFT);
172 #define I40E_RX_ERR_BITS 0x3f
173 if (likely((error_bits & I40E_RX_ERR_BITS) == 0)) {
174 flags |= (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD);
178 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_IPE_SHIFT)))
179 flags |= PKT_RX_IP_CKSUM_BAD;
181 flags |= PKT_RX_IP_CKSUM_GOOD;
183 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT)))
184 flags |= PKT_RX_L4_CKSUM_BAD;
186 flags |= PKT_RX_L4_CKSUM_GOOD;
188 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT)))
189 flags |= PKT_RX_OUTER_IP_CKSUM_BAD;
194 /* Function to check and set the ieee1588 timesync index and get the
197 #ifdef RTE_LIBRTE_IEEE1588
198 static inline uint64_t
199 i40e_get_iee15888_flags(struct rte_mbuf *mb, uint64_t qword)
201 uint64_t pkt_flags = 0;
202 uint16_t tsyn = (qword & (I40E_RXD_QW1_STATUS_TSYNVALID_MASK
203 | I40E_RXD_QW1_STATUS_TSYNINDX_MASK))
204 >> I40E_RX_DESC_STATUS_TSYNINDX_SHIFT;
206 if ((mb->packet_type & RTE_PTYPE_L2_MASK)
207 == RTE_PTYPE_L2_ETHER_TIMESYNC)
208 pkt_flags = PKT_RX_IEEE1588_PTP;
210 pkt_flags |= PKT_RX_IEEE1588_TMST;
211 mb->timesync = tsyn & 0x03;
218 static inline uint64_t
219 i40e_rxd_build_fdir(volatile union i40e_rx_desc *rxdp, struct rte_mbuf *mb)
222 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
223 uint16_t flexbh, flexbl;
225 flexbh = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
226 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT) &
227 I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK;
228 flexbl = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
229 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT) &
230 I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK;
233 if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID) {
235 rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.fd_id);
236 flags |= PKT_RX_FDIR_ID;
237 } else if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX) {
239 rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.flex_bytes_hi);
240 flags |= PKT_RX_FDIR_FLX;
242 if (flexbl == I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX) {
244 rte_le_to_cpu_32(rxdp->wb.qword3.lo_dword.flex_bytes_lo);
245 flags |= PKT_RX_FDIR_FLX;
249 rte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.fd_id);
250 flags |= PKT_RX_FDIR_ID;
256 i40e_parse_tunneling_params(uint64_t ol_flags,
257 union i40e_tx_offload tx_offload,
258 uint32_t *cd_tunneling)
260 /* EIPT: External (outer) IP header type */
261 if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
262 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
263 else if (ol_flags & PKT_TX_OUTER_IPV4)
264 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
265 else if (ol_flags & PKT_TX_OUTER_IPV6)
266 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
268 /* EIPLEN: External (outer) IP header length, in DWords */
269 *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
270 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT;
272 /* L4TUNT: L4 Tunneling Type */
273 switch (ol_flags & PKT_TX_TUNNEL_MASK) {
274 case PKT_TX_TUNNEL_IPIP:
275 /* for non UDP / GRE tunneling, set to 00b */
277 case PKT_TX_TUNNEL_VXLAN:
278 case PKT_TX_TUNNEL_GENEVE:
279 *cd_tunneling |= I40E_TXD_CTX_UDP_TUNNELING;
281 case PKT_TX_TUNNEL_GRE:
282 *cd_tunneling |= I40E_TXD_CTX_GRE_TUNNELING;
285 PMD_TX_LOG(ERR, "Tunnel type not supported");
289 /* L4TUNLEN: L4 Tunneling Length, in Words
291 * We depend on app to set rte_mbuf.l2_len correctly.
292 * For IP in GRE it should be set to the length of the GRE
294 * for MAC in GRE or MAC in UDP it should be set to the length
295 * of the GRE or UDP headers plus the inner MAC up to including
296 * its last Ethertype.
298 *cd_tunneling |= (tx_offload.l2_len >> 1) <<
299 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
303 i40e_txd_enable_checksum(uint64_t ol_flags,
306 union i40e_tx_offload tx_offload)
309 if (ol_flags & PKT_TX_TUNNEL_MASK)
310 *td_offset |= (tx_offload.outer_l2_len >> 1)
311 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
313 *td_offset |= (tx_offload.l2_len >> 1)
314 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
316 /* Enable L3 checksum offloads */
317 if (ol_flags & PKT_TX_IP_CKSUM) {
318 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
319 *td_offset |= (tx_offload.l3_len >> 2)
320 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
321 } else if (ol_flags & PKT_TX_IPV4) {
322 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
323 *td_offset |= (tx_offload.l3_len >> 2)
324 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
325 } else if (ol_flags & PKT_TX_IPV6) {
326 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
327 *td_offset |= (tx_offload.l3_len >> 2)
328 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
331 if (ol_flags & PKT_TX_TCP_SEG) {
332 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
333 *td_offset |= (tx_offload.l4_len >> 2)
334 << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
338 /* Enable L4 checksum offloads */
339 switch (ol_flags & PKT_TX_L4_MASK) {
340 case PKT_TX_TCP_CKSUM:
341 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
342 *td_offset |= (sizeof(struct rte_tcp_hdr) >> 2) <<
343 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
345 case PKT_TX_SCTP_CKSUM:
346 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
347 *td_offset |= (sizeof(struct rte_sctp_hdr) >> 2) <<
348 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
350 case PKT_TX_UDP_CKSUM:
351 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
352 *td_offset |= (sizeof(struct rte_udp_hdr) >> 2) <<
353 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
360 /* Construct the tx flags */
361 static inline uint64_t
362 i40e_build_ctob(uint32_t td_cmd,
367 return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
368 ((uint64_t)td_cmd << I40E_TXD_QW1_CMD_SHIFT) |
369 ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
370 ((uint64_t)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
371 ((uint64_t)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT));
375 i40e_xmit_cleanup(struct i40e_tx_queue *txq)
377 struct i40e_tx_entry *sw_ring = txq->sw_ring;
378 volatile struct i40e_tx_desc *txd = txq->tx_ring;
379 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
380 uint16_t nb_tx_desc = txq->nb_tx_desc;
381 uint16_t desc_to_clean_to;
382 uint16_t nb_tx_to_clean;
384 desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
385 if (desc_to_clean_to >= nb_tx_desc)
386 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
388 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
389 if ((txd[desc_to_clean_to].cmd_type_offset_bsz &
390 rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
391 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE)) {
392 PMD_TX_LOG(DEBUG, "TX descriptor %4u is not done "
393 "(port=%d queue=%d)", desc_to_clean_to,
394 txq->port_id, txq->queue_id);
398 if (last_desc_cleaned > desc_to_clean_to)
399 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
402 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
405 txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
407 txq->last_desc_cleaned = desc_to_clean_to;
408 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
414 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
415 check_rx_burst_bulk_alloc_preconditions(struct i40e_rx_queue *rxq)
417 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct i40e_rx_queue *rxq)
422 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
423 if (!(rxq->rx_free_thresh >= RTE_PMD_I40E_RX_MAX_BURST)) {
424 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
425 "rxq->rx_free_thresh=%d, "
426 "RTE_PMD_I40E_RX_MAX_BURST=%d",
427 rxq->rx_free_thresh, RTE_PMD_I40E_RX_MAX_BURST);
429 } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
430 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
431 "rxq->rx_free_thresh=%d, "
432 "rxq->nb_rx_desc=%d",
433 rxq->rx_free_thresh, rxq->nb_rx_desc);
435 } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
436 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
437 "rxq->nb_rx_desc=%d, "
438 "rxq->rx_free_thresh=%d",
439 rxq->nb_rx_desc, rxq->rx_free_thresh);
449 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
450 #define I40E_LOOK_AHEAD 8
451 #if (I40E_LOOK_AHEAD != 8)
452 #error "PMD I40E: I40E_LOOK_AHEAD must be 8\n"
455 i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq)
457 volatile union i40e_rx_desc *rxdp;
458 struct i40e_rx_entry *rxep;
463 int32_t s[I40E_LOOK_AHEAD], var, nb_dd;
464 int32_t i, j, nb_rx = 0;
466 uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
468 rxdp = &rxq->rx_ring[rxq->rx_tail];
469 rxep = &rxq->sw_ring[rxq->rx_tail];
471 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
472 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
473 I40E_RXD_QW1_STATUS_SHIFT;
475 /* Make sure there is at least 1 packet to receive */
476 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
480 * Scan LOOK_AHEAD descriptors at a time to determine which
481 * descriptors reference packets that are ready to be received.
483 for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; i+=I40E_LOOK_AHEAD,
484 rxdp += I40E_LOOK_AHEAD, rxep += I40E_LOOK_AHEAD) {
485 /* Read desc statuses backwards to avoid race condition */
486 for (j = I40E_LOOK_AHEAD - 1; j >= 0; j--) {
487 qword1 = rte_le_to_cpu_64(\
488 rxdp[j].wb.qword1.status_error_len);
489 s[j] = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
490 I40E_RXD_QW1_STATUS_SHIFT;
493 /* This barrier is to order loads of different words in the descriptor */
494 rte_atomic_thread_fence(__ATOMIC_ACQUIRE);
496 /* Compute how many status bits were set */
497 for (j = 0, nb_dd = 0; j < I40E_LOOK_AHEAD; j++) {
498 var = s[j] & (1 << I40E_RX_DESC_STATUS_DD_SHIFT);
500 /* For Arm platforms, only compute continuous status bits */
512 /* Translate descriptor info to mbuf parameters */
513 for (j = 0; j < nb_dd; j++) {
515 qword1 = rte_le_to_cpu_64(\
516 rxdp[j].wb.qword1.status_error_len);
517 pkt_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
518 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
519 mb->data_len = pkt_len;
520 mb->pkt_len = pkt_len;
522 i40e_rxd_to_vlan_tci(mb, &rxdp[j]);
523 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
524 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
526 ptype_tbl[(uint8_t)((qword1 &
527 I40E_RXD_QW1_PTYPE_MASK) >>
528 I40E_RXD_QW1_PTYPE_SHIFT)];
529 if (pkt_flags & PKT_RX_RSS_HASH)
530 mb->hash.rss = rte_le_to_cpu_32(\
531 rxdp[j].wb.qword0.hi_dword.rss);
532 if (pkt_flags & PKT_RX_FDIR)
533 pkt_flags |= i40e_rxd_build_fdir(&rxdp[j], mb);
535 #ifdef RTE_LIBRTE_IEEE1588
536 pkt_flags |= i40e_get_iee15888_flags(mb, qword1);
538 mb->ol_flags |= pkt_flags;
542 for (j = 0; j < I40E_LOOK_AHEAD; j++)
543 rxq->rx_stage[i + j] = rxep[j].mbuf;
545 if (nb_dd != I40E_LOOK_AHEAD)
549 /* Clear software ring entries */
550 for (i = 0; i < nb_rx; i++)
551 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
556 static inline uint16_t
557 i40e_rx_fill_from_stage(struct i40e_rx_queue *rxq,
558 struct rte_mbuf **rx_pkts,
562 struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
564 nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
566 for (i = 0; i < nb_pkts; i++)
567 rx_pkts[i] = stage[i];
569 rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
570 rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
576 i40e_rx_alloc_bufs(struct i40e_rx_queue *rxq)
578 volatile union i40e_rx_desc *rxdp;
579 struct i40e_rx_entry *rxep;
581 uint16_t alloc_idx, i;
585 /* Allocate buffers in bulk */
586 alloc_idx = (uint16_t)(rxq->rx_free_trigger -
587 (rxq->rx_free_thresh - 1));
588 rxep = &(rxq->sw_ring[alloc_idx]);
589 diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
590 rxq->rx_free_thresh);
591 if (unlikely(diag != 0)) {
592 PMD_DRV_LOG(ERR, "Failed to get mbufs in bulk");
596 rxdp = &rxq->rx_ring[alloc_idx];
597 for (i = 0; i < rxq->rx_free_thresh; i++) {
598 if (likely(i < (rxq->rx_free_thresh - 1)))
599 /* Prefetch next mbuf */
600 rte_prefetch0(rxep[i + 1].mbuf);
603 rte_mbuf_refcnt_set(mb, 1);
605 mb->data_off = RTE_PKTMBUF_HEADROOM;
607 mb->port = rxq->port_id;
608 dma_addr = rte_cpu_to_le_64(\
609 rte_mbuf_data_iova_default(mb));
610 rxdp[i].read.hdr_addr = 0;
611 rxdp[i].read.pkt_addr = dma_addr;
614 /* Update rx tail regsiter */
615 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger);
617 rxq->rx_free_trigger =
618 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
619 if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
620 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
625 static inline uint16_t
626 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
628 struct i40e_rx_queue *rxq = (struct i40e_rx_queue *)rx_queue;
629 struct rte_eth_dev *dev;
635 if (rxq->rx_nb_avail)
636 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
638 nb_rx = (uint16_t)i40e_rx_scan_hw_ring(rxq);
639 rxq->rx_next_avail = 0;
640 rxq->rx_nb_avail = nb_rx;
641 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
643 if (rxq->rx_tail > rxq->rx_free_trigger) {
644 if (i40e_rx_alloc_bufs(rxq) != 0) {
647 dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
648 dev->data->rx_mbuf_alloc_failed +=
651 rxq->rx_nb_avail = 0;
652 rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
653 for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
654 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
660 if (rxq->rx_tail >= rxq->nb_rx_desc)
663 if (rxq->rx_nb_avail)
664 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
670 i40e_recv_pkts_bulk_alloc(void *rx_queue,
671 struct rte_mbuf **rx_pkts,
674 uint16_t nb_rx = 0, n, count;
676 if (unlikely(nb_pkts == 0))
679 if (likely(nb_pkts <= RTE_PMD_I40E_RX_MAX_BURST))
680 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
683 n = RTE_MIN(nb_pkts, RTE_PMD_I40E_RX_MAX_BURST);
684 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
685 nb_rx = (uint16_t)(nb_rx + count);
686 nb_pkts = (uint16_t)(nb_pkts - count);
695 i40e_recv_pkts_bulk_alloc(void __rte_unused *rx_queue,
696 struct rte_mbuf __rte_unused **rx_pkts,
697 uint16_t __rte_unused nb_pkts)
701 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
704 i40e_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
706 struct i40e_rx_queue *rxq;
707 volatile union i40e_rx_desc *rx_ring;
708 volatile union i40e_rx_desc *rxdp;
709 union i40e_rx_desc rxd;
710 struct i40e_rx_entry *sw_ring;
711 struct i40e_rx_entry *rxe;
712 struct rte_eth_dev *dev;
713 struct rte_mbuf *rxm;
714 struct rte_mbuf *nmb;
718 uint16_t rx_packet_len;
719 uint16_t rx_id, nb_hold;
727 rx_id = rxq->rx_tail;
728 rx_ring = rxq->rx_ring;
729 sw_ring = rxq->sw_ring;
730 ptype_tbl = rxq->vsi->adapter->ptype_tbl;
732 while (nb_rx < nb_pkts) {
733 rxdp = &rx_ring[rx_id];
734 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
735 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
736 >> I40E_RXD_QW1_STATUS_SHIFT;
738 /* Check the DD bit first */
739 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
742 nmb = rte_mbuf_raw_alloc(rxq->mp);
743 if (unlikely(!nmb)) {
744 dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
745 dev->data->rx_mbuf_alloc_failed++;
751 rxe = &sw_ring[rx_id];
753 if (unlikely(rx_id == rxq->nb_rx_desc))
756 /* Prefetch next mbuf */
757 rte_prefetch0(sw_ring[rx_id].mbuf);
760 * When next RX descriptor is on a cache line boundary,
761 * prefetch the next 4 RX descriptors and next 8 pointers
764 if ((rx_id & 0x3) == 0) {
765 rte_prefetch0(&rx_ring[rx_id]);
766 rte_prefetch0(&sw_ring[rx_id]);
771 rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
772 rxdp->read.hdr_addr = 0;
773 rxdp->read.pkt_addr = dma_addr;
775 rx_packet_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
776 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
778 rxm->data_off = RTE_PKTMBUF_HEADROOM;
779 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
782 rxm->pkt_len = rx_packet_len;
783 rxm->data_len = rx_packet_len;
784 rxm->port = rxq->port_id;
786 i40e_rxd_to_vlan_tci(rxm, &rxd);
787 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
788 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
790 ptype_tbl[(uint8_t)((qword1 &
791 I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT)];
792 if (pkt_flags & PKT_RX_RSS_HASH)
794 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
795 if (pkt_flags & PKT_RX_FDIR)
796 pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
798 #ifdef RTE_LIBRTE_IEEE1588
799 pkt_flags |= i40e_get_iee15888_flags(rxm, qword1);
801 rxm->ol_flags |= pkt_flags;
803 rx_pkts[nb_rx++] = rxm;
805 rxq->rx_tail = rx_id;
808 * If the number of free RX descriptors is greater than the RX free
809 * threshold of the queue, advance the receive tail register of queue.
810 * Update that register with the value of the last processed RX
811 * descriptor minus 1.
813 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
814 if (nb_hold > rxq->rx_free_thresh) {
815 rx_id = (uint16_t) ((rx_id == 0) ?
816 (rxq->nb_rx_desc - 1) : (rx_id - 1));
817 I40E_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
820 rxq->nb_rx_hold = nb_hold;
826 i40e_recv_scattered_pkts(void *rx_queue,
827 struct rte_mbuf **rx_pkts,
830 struct i40e_rx_queue *rxq = rx_queue;
831 volatile union i40e_rx_desc *rx_ring = rxq->rx_ring;
832 volatile union i40e_rx_desc *rxdp;
833 union i40e_rx_desc rxd;
834 struct i40e_rx_entry *sw_ring = rxq->sw_ring;
835 struct i40e_rx_entry *rxe;
836 struct rte_mbuf *first_seg = rxq->pkt_first_seg;
837 struct rte_mbuf *last_seg = rxq->pkt_last_seg;
838 struct rte_mbuf *nmb, *rxm;
839 uint16_t rx_id = rxq->rx_tail;
840 uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
841 struct rte_eth_dev *dev;
846 uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
848 while (nb_rx < nb_pkts) {
849 rxdp = &rx_ring[rx_id];
850 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
851 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
852 I40E_RXD_QW1_STATUS_SHIFT;
854 /* Check the DD bit */
855 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
858 nmb = rte_mbuf_raw_alloc(rxq->mp);
859 if (unlikely(!nmb)) {
860 dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
861 dev->data->rx_mbuf_alloc_failed++;
867 rxe = &sw_ring[rx_id];
869 if (rx_id == rxq->nb_rx_desc)
872 /* Prefetch next mbuf */
873 rte_prefetch0(sw_ring[rx_id].mbuf);
876 * When next RX descriptor is on a cache line boundary,
877 * prefetch the next 4 RX descriptors and next 8 pointers
880 if ((rx_id & 0x3) == 0) {
881 rte_prefetch0(&rx_ring[rx_id]);
882 rte_prefetch0(&sw_ring[rx_id]);
888 rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
890 /* Set data buffer address and data length of the mbuf */
891 rxdp->read.hdr_addr = 0;
892 rxdp->read.pkt_addr = dma_addr;
893 rx_packet_len = (qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
894 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
895 rxm->data_len = rx_packet_len;
896 rxm->data_off = RTE_PKTMBUF_HEADROOM;
899 * If this is the first buffer of the received packet, set the
900 * pointer to the first mbuf of the packet and initialize its
901 * context. Otherwise, update the total length and the number
902 * of segments of the current scattered packet, and update the
903 * pointer to the last mbuf of the current packet.
907 first_seg->nb_segs = 1;
908 first_seg->pkt_len = rx_packet_len;
911 (uint16_t)(first_seg->pkt_len +
913 first_seg->nb_segs++;
914 last_seg->next = rxm;
918 * If this is not the last buffer of the received packet,
919 * update the pointer to the last mbuf of the current scattered
920 * packet and continue to parse the RX ring.
922 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT))) {
928 * This is the last buffer of the received packet. If the CRC
929 * is not stripped by the hardware:
930 * - Subtract the CRC length from the total packet length.
931 * - If the last buffer only contains the whole CRC or a part
932 * of it, free the mbuf associated to the last buffer. If part
933 * of the CRC is also contained in the previous mbuf, subtract
934 * the length of that CRC part from the data length of the
938 if (unlikely(rxq->crc_len > 0)) {
939 first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
940 if (rx_packet_len <= RTE_ETHER_CRC_LEN) {
941 rte_pktmbuf_free_seg(rxm);
942 first_seg->nb_segs--;
944 (uint16_t)(last_seg->data_len -
945 (RTE_ETHER_CRC_LEN - rx_packet_len));
946 last_seg->next = NULL;
948 rxm->data_len = (uint16_t)(rx_packet_len -
952 first_seg->port = rxq->port_id;
953 first_seg->ol_flags = 0;
954 i40e_rxd_to_vlan_tci(first_seg, &rxd);
955 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
956 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
957 first_seg->packet_type =
958 ptype_tbl[(uint8_t)((qword1 &
959 I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT)];
960 if (pkt_flags & PKT_RX_RSS_HASH)
961 first_seg->hash.rss =
962 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
963 if (pkt_flags & PKT_RX_FDIR)
964 pkt_flags |= i40e_rxd_build_fdir(&rxd, first_seg);
966 #ifdef RTE_LIBRTE_IEEE1588
967 pkt_flags |= i40e_get_iee15888_flags(first_seg, qword1);
969 first_seg->ol_flags |= pkt_flags;
971 /* Prefetch data of first segment, if configured to do so. */
972 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
973 first_seg->data_off));
974 rx_pkts[nb_rx++] = first_seg;
978 /* Record index of the next RX descriptor to probe. */
979 rxq->rx_tail = rx_id;
980 rxq->pkt_first_seg = first_seg;
981 rxq->pkt_last_seg = last_seg;
984 * If the number of free RX descriptors is greater than the RX free
985 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
986 * register. Update the RDT with the value of the last processed RX
987 * descriptor minus 1, to guarantee that the RDT register is never
988 * equal to the RDH register, which creates a "full" ring situtation
989 * from the hardware point of view.
991 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
992 if (nb_hold > rxq->rx_free_thresh) {
993 rx_id = (uint16_t)(rx_id == 0 ?
994 (rxq->nb_rx_desc - 1) : (rx_id - 1));
995 I40E_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
998 rxq->nb_rx_hold = nb_hold;
1003 /* Check if the context descriptor is needed for TX offloading */
1004 static inline uint16_t
1005 i40e_calc_context_desc(uint64_t flags)
1007 static uint64_t mask = PKT_TX_OUTER_IP_CKSUM |
1012 #ifdef RTE_LIBRTE_IEEE1588
1013 mask |= PKT_TX_IEEE1588_TMST;
1016 return (flags & mask) ? 1 : 0;
1019 /* set i40e TSO context descriptor */
1020 static inline uint64_t
1021 i40e_set_tso_ctx(struct rte_mbuf *mbuf, union i40e_tx_offload tx_offload)
1023 uint64_t ctx_desc = 0;
1024 uint32_t cd_cmd, hdr_len, cd_tso_len;
1026 if (!tx_offload.l4_len) {
1027 PMD_DRV_LOG(DEBUG, "L4 length set to 0");
1031 hdr_len = tx_offload.l2_len + tx_offload.l3_len + tx_offload.l4_len;
1032 hdr_len += (mbuf->ol_flags & PKT_TX_TUNNEL_MASK) ?
1033 tx_offload.outer_l2_len + tx_offload.outer_l3_len : 0;
1035 cd_cmd = I40E_TX_CTX_DESC_TSO;
1036 cd_tso_len = mbuf->pkt_len - hdr_len;
1037 ctx_desc |= ((uint64_t)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
1038 ((uint64_t)cd_tso_len <<
1039 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1040 ((uint64_t)mbuf->tso_segsz <<
1041 I40E_TXD_CTX_QW1_MSS_SHIFT);
1046 /* HW requires that Tx buffer size ranges from 1B up to (16K-1)B. */
1047 #define I40E_MAX_DATA_PER_TXD \
1048 (I40E_TXD_QW1_TX_BUF_SZ_MASK >> I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
1049 /* Calculate the number of TX descriptors needed for each pkt */
1050 static inline uint16_t
1051 i40e_calc_pkt_desc(struct rte_mbuf *tx_pkt)
1053 struct rte_mbuf *txd = tx_pkt;
1056 while (txd != NULL) {
1057 count += DIV_ROUND_UP(txd->data_len, I40E_MAX_DATA_PER_TXD);
1065 i40e_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1067 struct i40e_tx_queue *txq;
1068 struct i40e_tx_entry *sw_ring;
1069 struct i40e_tx_entry *txe, *txn;
1070 volatile struct i40e_tx_desc *txd;
1071 volatile struct i40e_tx_desc *txr;
1072 struct rte_mbuf *tx_pkt;
1073 struct rte_mbuf *m_seg;
1074 uint32_t cd_tunneling_params;
1085 uint64_t buf_dma_addr;
1086 union i40e_tx_offload tx_offload = {0};
1089 sw_ring = txq->sw_ring;
1091 tx_id = txq->tx_tail;
1092 txe = &sw_ring[tx_id];
1094 /* Check if the descriptor ring needs to be cleaned. */
1095 if (txq->nb_tx_free < txq->tx_free_thresh)
1096 (void)i40e_xmit_cleanup(txq);
1098 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1103 tx_pkt = *tx_pkts++;
1104 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
1106 ol_flags = tx_pkt->ol_flags;
1107 tx_offload.l2_len = tx_pkt->l2_len;
1108 tx_offload.l3_len = tx_pkt->l3_len;
1109 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
1110 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
1111 tx_offload.l4_len = tx_pkt->l4_len;
1112 tx_offload.tso_segsz = tx_pkt->tso_segsz;
1114 /* Calculate the number of context descriptors needed. */
1115 nb_ctx = i40e_calc_context_desc(ol_flags);
1118 * The number of descriptors that must be allocated for
1119 * a packet equals to the number of the segments of that
1120 * packet plus 1 context descriptor if needed.
1121 * Recalculate the needed tx descs when TSO enabled in case
1122 * the mbuf data size exceeds max data size that hw allows
1125 if (ol_flags & PKT_TX_TCP_SEG)
1126 nb_used = (uint16_t)(i40e_calc_pkt_desc(tx_pkt) +
1129 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
1130 tx_last = (uint16_t)(tx_id + nb_used - 1);
1133 if (tx_last >= txq->nb_tx_desc)
1134 tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
1136 if (nb_used > txq->nb_tx_free) {
1137 if (i40e_xmit_cleanup(txq) != 0) {
1142 if (unlikely(nb_used > txq->tx_rs_thresh)) {
1143 while (nb_used > txq->nb_tx_free) {
1144 if (i40e_xmit_cleanup(txq) != 0) {
1153 /* Descriptor based VLAN insertion */
1154 if (ol_flags & (PKT_TX_VLAN | PKT_TX_QINQ)) {
1155 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1156 td_tag = tx_pkt->vlan_tci;
1159 /* Always enable CRC offload insertion */
1160 td_cmd |= I40E_TX_DESC_CMD_ICRC;
1162 /* Fill in tunneling parameters if necessary */
1163 cd_tunneling_params = 0;
1164 if (ol_flags & PKT_TX_TUNNEL_MASK)
1165 i40e_parse_tunneling_params(ol_flags, tx_offload,
1166 &cd_tunneling_params);
1167 /* Enable checksum offloading */
1168 if (ol_flags & I40E_TX_CKSUM_OFFLOAD_MASK)
1169 i40e_txd_enable_checksum(ol_flags, &td_cmd,
1170 &td_offset, tx_offload);
1173 /* Setup TX context descriptor if required */
1174 volatile struct i40e_tx_context_desc *ctx_txd =
1175 (volatile struct i40e_tx_context_desc *)\
1177 uint16_t cd_l2tag2 = 0;
1178 uint64_t cd_type_cmd_tso_mss =
1179 I40E_TX_DESC_DTYPE_CONTEXT;
1181 txn = &sw_ring[txe->next_id];
1182 RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
1183 if (txe->mbuf != NULL) {
1184 rte_pktmbuf_free_seg(txe->mbuf);
1188 /* TSO enabled means no timestamp */
1189 if (ol_flags & PKT_TX_TCP_SEG)
1190 cd_type_cmd_tso_mss |=
1191 i40e_set_tso_ctx(tx_pkt, tx_offload);
1193 #ifdef RTE_LIBRTE_IEEE1588
1194 if (ol_flags & PKT_TX_IEEE1588_TMST)
1195 cd_type_cmd_tso_mss |=
1196 ((uint64_t)I40E_TX_CTX_DESC_TSYN <<
1197 I40E_TXD_CTX_QW1_CMD_SHIFT);
1201 ctx_txd->tunneling_params =
1202 rte_cpu_to_le_32(cd_tunneling_params);
1203 if (ol_flags & PKT_TX_QINQ) {
1204 cd_l2tag2 = tx_pkt->vlan_tci_outer;
1205 cd_type_cmd_tso_mss |=
1206 ((uint64_t)I40E_TX_CTX_DESC_IL2TAG2 <<
1207 I40E_TXD_CTX_QW1_CMD_SHIFT);
1209 ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
1210 ctx_txd->type_cmd_tso_mss =
1211 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
1213 PMD_TX_LOG(DEBUG, "mbuf: %p, TCD[%u]:\n"
1214 "tunneling_params: %#x;\n"
1217 "type_cmd_tso_mss: %#"PRIx64";\n",
1219 ctx_txd->tunneling_params,
1222 ctx_txd->type_cmd_tso_mss);
1224 txe->last_id = tx_last;
1225 tx_id = txe->next_id;
1232 txn = &sw_ring[txe->next_id];
1235 rte_pktmbuf_free_seg(txe->mbuf);
1238 /* Setup TX Descriptor */
1239 slen = m_seg->data_len;
1240 buf_dma_addr = rte_mbuf_data_iova(m_seg);
1242 while ((ol_flags & PKT_TX_TCP_SEG) &&
1243 unlikely(slen > I40E_MAX_DATA_PER_TXD)) {
1245 rte_cpu_to_le_64(buf_dma_addr);
1246 txd->cmd_type_offset_bsz =
1247 i40e_build_ctob(td_cmd,
1248 td_offset, I40E_MAX_DATA_PER_TXD,
1251 buf_dma_addr += I40E_MAX_DATA_PER_TXD;
1252 slen -= I40E_MAX_DATA_PER_TXD;
1254 txe->last_id = tx_last;
1255 tx_id = txe->next_id;
1258 txn = &sw_ring[txe->next_id];
1260 PMD_TX_LOG(DEBUG, "mbuf: %p, TDD[%u]:\n"
1261 "buf_dma_addr: %#"PRIx64";\n"
1266 tx_pkt, tx_id, buf_dma_addr,
1267 td_cmd, td_offset, slen, td_tag);
1269 txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
1270 txd->cmd_type_offset_bsz = i40e_build_ctob(td_cmd,
1271 td_offset, slen, td_tag);
1272 txe->last_id = tx_last;
1273 tx_id = txe->next_id;
1275 m_seg = m_seg->next;
1276 } while (m_seg != NULL);
1278 /* The last packet data descriptor needs End Of Packet (EOP) */
1279 td_cmd |= I40E_TX_DESC_CMD_EOP;
1280 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
1281 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
1283 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
1285 "Setting RS bit on TXD id="
1286 "%4u (port=%d queue=%d)",
1287 tx_last, txq->port_id, txq->queue_id);
1289 td_cmd |= I40E_TX_DESC_CMD_RS;
1291 /* Update txq RS bit counters */
1292 txq->nb_tx_used = 0;
1295 txd->cmd_type_offset_bsz |=
1296 rte_cpu_to_le_64(((uint64_t)td_cmd) <<
1297 I40E_TXD_QW1_CMD_SHIFT);
1301 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
1302 (unsigned) txq->port_id, (unsigned) txq->queue_id,
1303 (unsigned) tx_id, (unsigned) nb_tx);
1306 I40E_PCI_REG_WC_WRITE_RELAXED(txq->qtx_tail, tx_id);
1307 txq->tx_tail = tx_id;
1312 static __rte_always_inline int
1313 i40e_tx_free_bufs(struct i40e_tx_queue *txq)
1315 struct i40e_tx_entry *txep;
1316 uint16_t tx_rs_thresh = txq->tx_rs_thresh;
1317 uint16_t i = 0, j = 0;
1318 struct rte_mbuf *free[RTE_I40E_TX_MAX_FREE_BUF_SZ];
1319 const uint16_t k = RTE_ALIGN_FLOOR(tx_rs_thresh, RTE_I40E_TX_MAX_FREE_BUF_SZ);
1320 const uint16_t m = tx_rs_thresh % RTE_I40E_TX_MAX_FREE_BUF_SZ;
1322 if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
1323 rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
1324 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
1327 txep = &txq->sw_ring[txq->tx_next_dd - (tx_rs_thresh - 1)];
1329 for (i = 0; i < tx_rs_thresh; i++)
1330 rte_prefetch0((txep + i)->mbuf);
1332 if (txq->offloads & RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE) {
1334 for (j = 0; j != k; j += RTE_I40E_TX_MAX_FREE_BUF_SZ) {
1335 for (i = 0; i < RTE_I40E_TX_MAX_FREE_BUF_SZ; ++i, ++txep) {
1336 free[i] = txep->mbuf;
1339 rte_mempool_put_bulk(free[0]->pool, (void **)free,
1340 RTE_I40E_TX_MAX_FREE_BUF_SZ);
1345 for (i = 0; i < m; ++i, ++txep) {
1346 free[i] = txep->mbuf;
1349 rte_mempool_put_bulk(free[0]->pool, (void **)free, m);
1352 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1353 rte_pktmbuf_free_seg(txep->mbuf);
1358 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
1359 txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
1360 if (txq->tx_next_dd >= txq->nb_tx_desc)
1361 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1363 return txq->tx_rs_thresh;
1366 /* Populate 4 descriptors with data from 4 mbufs */
1368 tx4(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1373 for (i = 0; i < 4; i++, txdp++, pkts++) {
1374 dma_addr = rte_mbuf_data_iova(*pkts);
1375 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1376 txdp->cmd_type_offset_bsz =
1377 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1378 (*pkts)->data_len, 0);
1382 /* Populate 1 descriptor with data from 1 mbuf */
1384 tx1(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1388 dma_addr = rte_mbuf_data_iova(*pkts);
1389 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1390 txdp->cmd_type_offset_bsz =
1391 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1392 (*pkts)->data_len, 0);
1395 /* Fill hardware descriptor ring with mbuf data */
1397 i40e_tx_fill_hw_ring(struct i40e_tx_queue *txq,
1398 struct rte_mbuf **pkts,
1401 volatile struct i40e_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
1402 struct i40e_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
1403 const int N_PER_LOOP = 4;
1404 const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
1405 int mainpart, leftover;
1408 mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
1409 leftover = (nb_pkts & ((uint32_t) N_PER_LOOP_MASK));
1410 for (i = 0; i < mainpart; i += N_PER_LOOP) {
1411 for (j = 0; j < N_PER_LOOP; ++j) {
1412 (txep + i + j)->mbuf = *(pkts + i + j);
1414 tx4(txdp + i, pkts + i);
1416 if (unlikely(leftover > 0)) {
1417 for (i = 0; i < leftover; ++i) {
1418 (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
1419 tx1(txdp + mainpart + i, pkts + mainpart + i);
1424 static inline uint16_t
1425 tx_xmit_pkts(struct i40e_tx_queue *txq,
1426 struct rte_mbuf **tx_pkts,
1429 volatile struct i40e_tx_desc *txr = txq->tx_ring;
1433 * Begin scanning the H/W ring for done descriptors when the number
1434 * of available descriptors drops below tx_free_thresh. For each done
1435 * descriptor, free the associated buffer.
1437 if (txq->nb_tx_free < txq->tx_free_thresh)
1438 i40e_tx_free_bufs(txq);
1440 /* Use available descriptor only */
1441 nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
1442 if (unlikely(!nb_pkts))
1445 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
1446 if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
1447 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
1448 i40e_tx_fill_hw_ring(txq, tx_pkts, n);
1449 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1450 rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1451 I40E_TXD_QW1_CMD_SHIFT);
1452 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1456 /* Fill hardware descriptor ring with mbuf data */
1457 i40e_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
1458 txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
1460 /* Determin if RS bit needs to be set */
1461 if (txq->tx_tail > txq->tx_next_rs) {
1462 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1463 rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1464 I40E_TXD_QW1_CMD_SHIFT);
1466 (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
1467 if (txq->tx_next_rs >= txq->nb_tx_desc)
1468 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1471 if (txq->tx_tail >= txq->nb_tx_desc)
1474 /* Update the tx tail register */
1475 I40E_PCI_REG_WC_WRITE(txq->qtx_tail, txq->tx_tail);
1481 i40e_xmit_pkts_simple(void *tx_queue,
1482 struct rte_mbuf **tx_pkts,
1487 if (likely(nb_pkts <= I40E_TX_MAX_BURST))
1488 return tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1492 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
1495 ret = tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1496 &tx_pkts[nb_tx], num);
1497 nb_tx = (uint16_t)(nb_tx + ret);
1498 nb_pkts = (uint16_t)(nb_pkts - ret);
1507 i40e_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
1511 struct i40e_tx_queue *txq = (struct i40e_tx_queue *)tx_queue;
1516 num = (uint16_t)RTE_MIN(nb_pkts, txq->tx_rs_thresh);
1517 ret = i40e_xmit_fixed_burst_vec(tx_queue, &tx_pkts[nb_tx],
1528 /*********************************************************************
1530 * TX simple prep functions
1532 **********************************************************************/
1534 i40e_simple_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
1541 for (i = 0; i < nb_pkts; i++) {
1543 ol_flags = m->ol_flags;
1545 if (m->nb_segs != 1) {
1550 if (ol_flags & I40E_TX_OFFLOAD_SIMPLE_NOTSUP_MASK) {
1551 rte_errno = ENOTSUP;
1555 /* check the size of packet */
1556 if (m->pkt_len < I40E_TX_MIN_PKT_LEN ||
1557 m->pkt_len > I40E_FRAME_SIZE_MAX) {
1565 /*********************************************************************
1569 **********************************************************************/
1571 i40e_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
1578 for (i = 0; i < nb_pkts; i++) {
1580 ol_flags = m->ol_flags;
1582 /* Check for m->nb_segs to not exceed the limits. */
1583 if (!(ol_flags & PKT_TX_TCP_SEG)) {
1584 if (m->nb_segs > I40E_TX_MAX_MTU_SEG ||
1585 m->pkt_len > I40E_FRAME_SIZE_MAX) {
1589 } else if (m->nb_segs > I40E_TX_MAX_SEG ||
1590 m->tso_segsz < I40E_MIN_TSO_MSS ||
1591 m->tso_segsz > I40E_MAX_TSO_MSS ||
1592 m->pkt_len > I40E_TSO_FRAME_SIZE_MAX) {
1593 /* MSS outside the range (256B - 9674B) are considered
1600 if (ol_flags & I40E_TX_OFFLOAD_NOTSUP_MASK) {
1601 rte_errno = ENOTSUP;
1605 /* check the size of packet */
1606 if (m->pkt_len < I40E_TX_MIN_PKT_LEN) {
1611 #ifdef RTE_ETHDEV_DEBUG_TX
1612 ret = rte_validate_tx_offload(m);
1618 ret = rte_net_intel_cksum_prepare(m);
1628 * Find the VSI the queue belongs to. 'queue_idx' is the queue index
1629 * application used, which assume having sequential ones. But from driver's
1630 * perspective, it's different. For example, q0 belongs to FDIR VSI, q1-q64
1631 * to MAIN VSI, , q65-96 to SRIOV VSIs, q97-128 to VMDQ VSIs. For application
1632 * running on host, q1-64 and q97-128 can be used, total 96 queues. They can
1633 * use queue_idx from 0 to 95 to access queues, while real queue would be
1634 * different. This function will do a queue mapping to find VSI the queue
1637 static struct i40e_vsi*
1638 i40e_pf_get_vsi_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1640 /* the queue in MAIN VSI range */
1641 if (queue_idx < pf->main_vsi->nb_qps)
1642 return pf->main_vsi;
1644 queue_idx -= pf->main_vsi->nb_qps;
1646 /* queue_idx is greater than VMDQ VSIs range */
1647 if (queue_idx > pf->nb_cfg_vmdq_vsi * pf->vmdq_nb_qps - 1) {
1648 PMD_INIT_LOG(ERR, "queue_idx out of range. VMDQ configured?");
1652 return pf->vmdq[queue_idx / pf->vmdq_nb_qps].vsi;
1656 i40e_get_queue_offset_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1658 /* the queue in MAIN VSI range */
1659 if (queue_idx < pf->main_vsi->nb_qps)
1662 /* It's VMDQ queues */
1663 queue_idx -= pf->main_vsi->nb_qps;
1665 if (pf->nb_cfg_vmdq_vsi)
1666 return queue_idx % pf->vmdq_nb_qps;
1668 PMD_INIT_LOG(ERR, "Fail to get queue offset");
1669 return (uint16_t)(-1);
1674 i40e_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1676 struct i40e_rx_queue *rxq;
1678 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1680 PMD_INIT_FUNC_TRACE();
1682 rxq = dev->data->rx_queues[rx_queue_id];
1683 if (!rxq || !rxq->q_set) {
1684 PMD_DRV_LOG(ERR, "RX queue %u not available or setup",
1689 if (rxq->rx_deferred_start)
1690 PMD_DRV_LOG(WARNING, "RX queue %u is deferrd start",
1693 err = i40e_alloc_rx_queue_mbufs(rxq);
1695 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1699 /* Init the RX tail regieter. */
1700 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1702 err = i40e_switch_rx_queue(hw, rxq->reg_idx, TRUE);
1704 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1707 i40e_rx_queue_release_mbufs(rxq);
1708 i40e_reset_rx_queue(rxq);
1711 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1717 i40e_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1719 struct i40e_rx_queue *rxq;
1721 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1723 rxq = dev->data->rx_queues[rx_queue_id];
1724 if (!rxq || !rxq->q_set) {
1725 PMD_DRV_LOG(ERR, "RX queue %u not available or setup",
1731 * rx_queue_id is queue id application refers to, while
1732 * rxq->reg_idx is the real queue index.
1734 err = i40e_switch_rx_queue(hw, rxq->reg_idx, FALSE);
1736 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1740 i40e_rx_queue_release_mbufs(rxq);
1741 i40e_reset_rx_queue(rxq);
1742 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1748 i40e_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1751 struct i40e_tx_queue *txq;
1752 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1754 PMD_INIT_FUNC_TRACE();
1756 txq = dev->data->tx_queues[tx_queue_id];
1757 if (!txq || !txq->q_set) {
1758 PMD_DRV_LOG(ERR, "TX queue %u is not available or setup",
1763 if (txq->tx_deferred_start)
1764 PMD_DRV_LOG(WARNING, "TX queue %u is deferrd start",
1768 * tx_queue_id is queue id application refers to, while
1769 * rxq->reg_idx is the real queue index.
1771 err = i40e_switch_tx_queue(hw, txq->reg_idx, TRUE);
1773 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1777 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1783 i40e_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1785 struct i40e_tx_queue *txq;
1787 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1789 txq = dev->data->tx_queues[tx_queue_id];
1790 if (!txq || !txq->q_set) {
1791 PMD_DRV_LOG(ERR, "TX queue %u is not available or setup",
1797 * tx_queue_id is queue id application refers to, while
1798 * txq->reg_idx is the real queue index.
1800 err = i40e_switch_tx_queue(hw, txq->reg_idx, FALSE);
1802 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u of",
1807 i40e_tx_queue_release_mbufs(txq);
1808 i40e_reset_tx_queue(txq);
1809 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1815 i40e_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1817 static const uint32_t ptypes[] = {
1818 /* refers to i40e_rxd_pkt_type_mapping() */
1820 RTE_PTYPE_L2_ETHER_TIMESYNC,
1821 RTE_PTYPE_L2_ETHER_LLDP,
1822 RTE_PTYPE_L2_ETHER_ARP,
1823 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1824 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
1827 RTE_PTYPE_L4_NONFRAG,
1831 RTE_PTYPE_TUNNEL_GRENAT,
1832 RTE_PTYPE_TUNNEL_IP,
1833 RTE_PTYPE_INNER_L2_ETHER,
1834 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1835 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
1836 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
1837 RTE_PTYPE_INNER_L4_FRAG,
1838 RTE_PTYPE_INNER_L4_ICMP,
1839 RTE_PTYPE_INNER_L4_NONFRAG,
1840 RTE_PTYPE_INNER_L4_SCTP,
1841 RTE_PTYPE_INNER_L4_TCP,
1842 RTE_PTYPE_INNER_L4_UDP,
1846 if (dev->rx_pkt_burst == i40e_recv_pkts ||
1847 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1848 dev->rx_pkt_burst == i40e_recv_pkts_bulk_alloc ||
1850 dev->rx_pkt_burst == i40e_recv_scattered_pkts ||
1851 dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
1852 dev->rx_pkt_burst == i40e_recv_pkts_vec ||
1853 #ifdef CC_AVX512_SUPPORT
1854 dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec_avx512 ||
1855 dev->rx_pkt_burst == i40e_recv_pkts_vec_avx512 ||
1857 dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec_avx2 ||
1858 dev->rx_pkt_burst == i40e_recv_pkts_vec_avx2)
1864 i40e_dev_first_queue(uint16_t idx, void **queues, int num)
1868 for (i = 0; i < num; i++) {
1869 if (i != idx && queues[i])
1877 i40e_dev_rx_queue_setup_runtime(struct rte_eth_dev *dev,
1878 struct i40e_rx_queue *rxq)
1880 struct i40e_adapter *ad =
1881 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1882 int use_def_burst_func =
1883 check_rx_burst_bulk_alloc_preconditions(rxq);
1885 (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
1886 RTE_PKTMBUF_HEADROOM);
1887 int use_scattered_rx =
1888 (rxq->max_pkt_len > buf_size);
1890 if (i40e_rx_queue_init(rxq) != I40E_SUCCESS) {
1892 "Failed to do RX queue initialization");
1896 if (i40e_dev_first_queue(rxq->queue_id,
1897 dev->data->rx_queues,
1898 dev->data->nb_rx_queues)) {
1900 * If it is the first queue to setup,
1901 * set all flags to default and call
1902 * i40e_set_rx_function.
1904 ad->rx_bulk_alloc_allowed = true;
1905 ad->rx_vec_allowed = true;
1906 dev->data->scattered_rx = use_scattered_rx;
1907 if (use_def_burst_func)
1908 ad->rx_bulk_alloc_allowed = false;
1909 i40e_set_rx_function(dev);
1911 } else if (ad->rx_vec_allowed && !rte_is_power_of_2(rxq->nb_rx_desc)) {
1912 PMD_DRV_LOG(ERR, "Vector mode is allowed, but descriptor"
1913 " number %d of queue %d isn't power of 2",
1914 rxq->nb_rx_desc, rxq->queue_id);
1918 /* check bulk alloc conflict */
1919 if (ad->rx_bulk_alloc_allowed && use_def_burst_func) {
1920 PMD_DRV_LOG(ERR, "Can't use default burst.");
1923 /* check scatterred conflict */
1924 if (!dev->data->scattered_rx && use_scattered_rx) {
1925 PMD_DRV_LOG(ERR, "Scattered rx is required.");
1928 /* check vector conflict */
1929 if (ad->rx_vec_allowed && i40e_rxq_vec_setup(rxq)) {
1930 PMD_DRV_LOG(ERR, "Failed vector rx setup.");
1938 i40e_dev_rx_queue_setup(struct rte_eth_dev *dev,
1941 unsigned int socket_id,
1942 const struct rte_eth_rxconf *rx_conf,
1943 struct rte_mempool *mp)
1945 struct i40e_adapter *ad =
1946 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1947 struct i40e_vsi *vsi;
1948 struct i40e_pf *pf = NULL;
1949 struct i40e_rx_queue *rxq;
1950 const struct rte_memzone *rz;
1953 uint16_t reg_idx, base, bsf, tc_mapping;
1954 int q_offset, use_def_burst_func = 1;
1957 offloads = rx_conf->offloads | dev->data->dev_conf.rxmode.offloads;
1959 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1960 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
1963 q_offset = i40e_get_queue_offset_by_qindex(pf, queue_idx);
1966 reg_idx = vsi->base_queue + q_offset;
1968 if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
1969 (nb_desc > I40E_MAX_RING_DESC) ||
1970 (nb_desc < I40E_MIN_RING_DESC)) {
1971 PMD_DRV_LOG(ERR, "Number (%u) of receive descriptors is "
1972 "invalid", nb_desc);
1976 /* Free memory if needed */
1977 if (dev->data->rx_queues[queue_idx]) {
1978 i40e_rx_queue_release(dev->data->rx_queues[queue_idx]);
1979 dev->data->rx_queues[queue_idx] = NULL;
1982 /* Allocate the rx queue data structure */
1983 rxq = rte_zmalloc_socket("i40e rx queue",
1984 sizeof(struct i40e_rx_queue),
1985 RTE_CACHE_LINE_SIZE,
1988 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
1989 "rx queue data structure");
1993 rxq->nb_rx_desc = nb_desc;
1994 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1995 rxq->queue_id = queue_idx;
1996 rxq->reg_idx = reg_idx;
1997 rxq->port_id = dev->data->port_id;
1998 if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_KEEP_CRC)
1999 rxq->crc_len = RTE_ETHER_CRC_LEN;
2002 rxq->drop_en = rx_conf->rx_drop_en;
2004 rxq->rx_deferred_start = rx_conf->rx_deferred_start;
2005 rxq->offloads = offloads;
2007 /* Allocate the maximun number of RX ring hardware descriptor. */
2008 len = I40E_MAX_RING_DESC;
2011 * Allocating a little more memory because vectorized/bulk_alloc Rx
2012 * functions doesn't check boundaries each time.
2014 len += RTE_PMD_I40E_RX_MAX_BURST;
2016 ring_size = RTE_ALIGN(len * sizeof(union i40e_rx_desc),
2017 I40E_DMA_MEM_ALIGN);
2019 rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
2020 ring_size, I40E_RING_BASE_ALIGN, socket_id);
2022 i40e_rx_queue_release(rxq);
2023 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX");
2028 /* Zero all the descriptors in the ring. */
2029 memset(rz->addr, 0, ring_size);
2031 rxq->rx_ring_phys_addr = rz->iova;
2032 rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
2034 len = (uint16_t)(nb_desc + RTE_PMD_I40E_RX_MAX_BURST);
2036 /* Allocate the software ring. */
2038 rte_zmalloc_socket("i40e rx sw ring",
2039 sizeof(struct i40e_rx_entry) * len,
2040 RTE_CACHE_LINE_SIZE,
2042 if (!rxq->sw_ring) {
2043 i40e_rx_queue_release(rxq);
2044 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW ring");
2048 i40e_reset_rx_queue(rxq);
2051 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2052 if (!(vsi->enabled_tc & (1 << i)))
2054 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
2055 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
2056 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
2057 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
2058 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
2060 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
2064 if (dev->data->dev_started) {
2065 if (i40e_dev_rx_queue_setup_runtime(dev, rxq)) {
2066 i40e_rx_queue_release(rxq);
2070 use_def_burst_func =
2071 check_rx_burst_bulk_alloc_preconditions(rxq);
2072 if (!use_def_burst_func) {
2073 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2075 "Rx Burst Bulk Alloc Preconditions are "
2076 "satisfied. Rx Burst Bulk Alloc function will be "
2077 "used on port=%d, queue=%d.",
2078 rxq->port_id, rxq->queue_id);
2079 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2082 "Rx Burst Bulk Alloc Preconditions are "
2083 "not satisfied, Scattered Rx is requested, "
2084 "or RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC is "
2085 "not enabled on port=%d, queue=%d.",
2086 rxq->port_id, rxq->queue_id);
2087 ad->rx_bulk_alloc_allowed = false;
2091 dev->data->rx_queues[queue_idx] = rxq;
2096 i40e_dev_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
2098 i40e_rx_queue_release(dev->data->rx_queues[qid]);
2102 i40e_dev_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
2104 i40e_tx_queue_release(dev->data->tx_queues[qid]);
2108 i40e_rx_queue_release(void *rxq)
2110 struct i40e_rx_queue *q = (struct i40e_rx_queue *)rxq;
2113 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
2117 i40e_rx_queue_release_mbufs(q);
2118 rte_free(q->sw_ring);
2119 rte_memzone_free(q->mz);
2124 i40e_dev_rx_queue_count(void *rx_queue)
2126 #define I40E_RXQ_SCAN_INTERVAL 4
2127 volatile union i40e_rx_desc *rxdp;
2128 struct i40e_rx_queue *rxq;
2132 rxdp = &(rxq->rx_ring[rxq->rx_tail]);
2133 while ((desc < rxq->nb_rx_desc) &&
2134 ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
2135 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
2136 (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
2138 * Check the DD bit of a rx descriptor of each 4 in a group,
2139 * to avoid checking too frequently and downgrading performance
2142 desc += I40E_RXQ_SCAN_INTERVAL;
2143 rxdp += I40E_RXQ_SCAN_INTERVAL;
2144 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
2145 rxdp = &(rxq->rx_ring[rxq->rx_tail +
2146 desc - rxq->nb_rx_desc]);
2153 i40e_dev_rx_descriptor_status(void *rx_queue, uint16_t offset)
2155 struct i40e_rx_queue *rxq = rx_queue;
2156 volatile uint64_t *status;
2160 if (unlikely(offset >= rxq->nb_rx_desc))
2163 if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
2164 return RTE_ETH_RX_DESC_UNAVAIL;
2166 desc = rxq->rx_tail + offset;
2167 if (desc >= rxq->nb_rx_desc)
2168 desc -= rxq->nb_rx_desc;
2170 status = &rxq->rx_ring[desc].wb.qword1.status_error_len;
2171 mask = rte_le_to_cpu_64((1ULL << I40E_RX_DESC_STATUS_DD_SHIFT)
2172 << I40E_RXD_QW1_STATUS_SHIFT);
2174 return RTE_ETH_RX_DESC_DONE;
2176 return RTE_ETH_RX_DESC_AVAIL;
2180 i40e_dev_tx_descriptor_status(void *tx_queue, uint16_t offset)
2182 struct i40e_tx_queue *txq = tx_queue;
2183 volatile uint64_t *status;
2184 uint64_t mask, expect;
2187 if (unlikely(offset >= txq->nb_tx_desc))
2190 desc = txq->tx_tail + offset;
2191 /* go to next desc that has the RS bit */
2192 desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) *
2194 if (desc >= txq->nb_tx_desc) {
2195 desc -= txq->nb_tx_desc;
2196 if (desc >= txq->nb_tx_desc)
2197 desc -= txq->nb_tx_desc;
2200 status = &txq->tx_ring[desc].cmd_type_offset_bsz;
2201 mask = rte_le_to_cpu_64(I40E_TXD_QW1_DTYPE_MASK);
2202 expect = rte_cpu_to_le_64(
2203 I40E_TX_DESC_DTYPE_DESC_DONE << I40E_TXD_QW1_DTYPE_SHIFT);
2204 if ((*status & mask) == expect)
2205 return RTE_ETH_TX_DESC_DONE;
2207 return RTE_ETH_TX_DESC_FULL;
2211 i40e_dev_tx_queue_setup_runtime(struct rte_eth_dev *dev,
2212 struct i40e_tx_queue *txq)
2214 struct i40e_adapter *ad =
2215 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2217 if (i40e_tx_queue_init(txq) != I40E_SUCCESS) {
2219 "Failed to do TX queue initialization");
2223 if (i40e_dev_first_queue(txq->queue_id,
2224 dev->data->tx_queues,
2225 dev->data->nb_tx_queues)) {
2227 * If it is the first queue to setup,
2228 * set all flags and call
2229 * i40e_set_tx_function.
2231 i40e_set_tx_function_flag(dev, txq);
2232 i40e_set_tx_function(dev);
2236 /* check vector conflict */
2237 if (ad->tx_vec_allowed) {
2238 if (txq->tx_rs_thresh > RTE_I40E_TX_MAX_FREE_BUF_SZ ||
2239 i40e_txq_vec_setup(txq)) {
2240 PMD_DRV_LOG(ERR, "Failed vector tx setup.");
2244 /* check simple tx conflict */
2245 if (ad->tx_simple_allowed) {
2246 if ((txq->offloads & ~RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE) != 0 ||
2247 txq->tx_rs_thresh < RTE_PMD_I40E_TX_MAX_BURST) {
2248 PMD_DRV_LOG(ERR, "No-simple tx is required.");
2257 i40e_dev_tx_queue_setup(struct rte_eth_dev *dev,
2260 unsigned int socket_id,
2261 const struct rte_eth_txconf *tx_conf)
2263 struct i40e_vsi *vsi;
2264 struct i40e_pf *pf = NULL;
2265 struct i40e_tx_queue *txq;
2266 const struct rte_memzone *tz;
2268 uint16_t tx_rs_thresh, tx_free_thresh;
2269 uint16_t reg_idx, i, base, bsf, tc_mapping;
2273 offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
2275 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2276 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
2279 q_offset = i40e_get_queue_offset_by_qindex(pf, queue_idx);
2282 reg_idx = vsi->base_queue + q_offset;
2284 if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
2285 (nb_desc > I40E_MAX_RING_DESC) ||
2286 (nb_desc < I40E_MIN_RING_DESC)) {
2287 PMD_DRV_LOG(ERR, "Number (%u) of transmit descriptors is "
2288 "invalid", nb_desc);
2293 * The following two parameters control the setting of the RS bit on
2294 * transmit descriptors. TX descriptors will have their RS bit set
2295 * after txq->tx_rs_thresh descriptors have been used. The TX
2296 * descriptor ring will be cleaned after txq->tx_free_thresh
2297 * descriptors are used or if the number of descriptors required to
2298 * transmit a packet is greater than the number of free TX descriptors.
2300 * The following constraints must be satisfied:
2301 * - tx_rs_thresh must be greater than 0.
2302 * - tx_rs_thresh must be less than the size of the ring minus 2.
2303 * - tx_rs_thresh must be less than or equal to tx_free_thresh.
2304 * - tx_rs_thresh must be a divisor of the ring size.
2305 * - tx_free_thresh must be greater than 0.
2306 * - tx_free_thresh must be less than the size of the ring minus 3.
2307 * - tx_free_thresh + tx_rs_thresh must not exceed nb_desc.
2309 * One descriptor in the TX ring is used as a sentinel to avoid a H/W
2310 * race condition, hence the maximum threshold constraints. When set
2311 * to zero use default values.
2313 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
2314 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
2315 /* force tx_rs_thresh to adapt an aggresive tx_free_thresh */
2316 tx_rs_thresh = (DEFAULT_TX_RS_THRESH + tx_free_thresh > nb_desc) ?
2317 nb_desc - tx_free_thresh : DEFAULT_TX_RS_THRESH;
2318 if (tx_conf->tx_rs_thresh > 0)
2319 tx_rs_thresh = tx_conf->tx_rs_thresh;
2320 if (tx_rs_thresh + tx_free_thresh > nb_desc) {
2321 PMD_INIT_LOG(ERR, "tx_rs_thresh + tx_free_thresh must not "
2322 "exceed nb_desc. (tx_rs_thresh=%u "
2323 "tx_free_thresh=%u nb_desc=%u port=%d queue=%d)",
2324 (unsigned int)tx_rs_thresh,
2325 (unsigned int)tx_free_thresh,
2326 (unsigned int)nb_desc,
2327 (int)dev->data->port_id,
2329 return I40E_ERR_PARAM;
2331 if (tx_rs_thresh >= (nb_desc - 2)) {
2332 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
2333 "number of TX descriptors minus 2. "
2334 "(tx_rs_thresh=%u port=%d queue=%d)",
2335 (unsigned int)tx_rs_thresh,
2336 (int)dev->data->port_id,
2338 return I40E_ERR_PARAM;
2340 if (tx_free_thresh >= (nb_desc - 3)) {
2341 PMD_INIT_LOG(ERR, "tx_free_thresh must be less than the "
2342 "number of TX descriptors minus 3. "
2343 "(tx_free_thresh=%u port=%d queue=%d)",
2344 (unsigned int)tx_free_thresh,
2345 (int)dev->data->port_id,
2347 return I40E_ERR_PARAM;
2349 if (tx_rs_thresh > tx_free_thresh) {
2350 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
2351 "equal to tx_free_thresh. (tx_free_thresh=%u"
2352 " tx_rs_thresh=%u port=%d queue=%d)",
2353 (unsigned int)tx_free_thresh,
2354 (unsigned int)tx_rs_thresh,
2355 (int)dev->data->port_id,
2357 return I40E_ERR_PARAM;
2359 if ((nb_desc % tx_rs_thresh) != 0) {
2360 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
2361 "number of TX descriptors. (tx_rs_thresh=%u"
2362 " port=%d queue=%d)",
2363 (unsigned int)tx_rs_thresh,
2364 (int)dev->data->port_id,
2366 return I40E_ERR_PARAM;
2368 if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
2369 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
2370 "tx_rs_thresh is greater than 1. "
2371 "(tx_rs_thresh=%u port=%d queue=%d)",
2372 (unsigned int)tx_rs_thresh,
2373 (int)dev->data->port_id,
2375 return I40E_ERR_PARAM;
2378 /* Free memory if needed. */
2379 if (dev->data->tx_queues[queue_idx]) {
2380 i40e_tx_queue_release(dev->data->tx_queues[queue_idx]);
2381 dev->data->tx_queues[queue_idx] = NULL;
2384 /* Allocate the TX queue data structure. */
2385 txq = rte_zmalloc_socket("i40e tx queue",
2386 sizeof(struct i40e_tx_queue),
2387 RTE_CACHE_LINE_SIZE,
2390 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2391 "tx queue structure");
2395 /* Allocate TX hardware ring descriptors. */
2396 ring_size = sizeof(struct i40e_tx_desc) * I40E_MAX_RING_DESC;
2397 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2398 tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
2399 ring_size, I40E_RING_BASE_ALIGN, socket_id);
2401 i40e_tx_queue_release(txq);
2402 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX");
2407 txq->nb_tx_desc = nb_desc;
2408 txq->tx_rs_thresh = tx_rs_thresh;
2409 txq->tx_free_thresh = tx_free_thresh;
2410 txq->pthresh = tx_conf->tx_thresh.pthresh;
2411 txq->hthresh = tx_conf->tx_thresh.hthresh;
2412 txq->wthresh = tx_conf->tx_thresh.wthresh;
2413 txq->queue_id = queue_idx;
2414 txq->reg_idx = reg_idx;
2415 txq->port_id = dev->data->port_id;
2416 txq->offloads = offloads;
2418 txq->tx_deferred_start = tx_conf->tx_deferred_start;
2420 txq->tx_ring_phys_addr = tz->iova;
2421 txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2423 /* Allocate software ring */
2425 rte_zmalloc_socket("i40e tx sw ring",
2426 sizeof(struct i40e_tx_entry) * nb_desc,
2427 RTE_CACHE_LINE_SIZE,
2429 if (!txq->sw_ring) {
2430 i40e_tx_queue_release(txq);
2431 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW TX ring");
2435 i40e_reset_tx_queue(txq);
2438 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2439 if (!(vsi->enabled_tc & (1 << i)))
2441 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
2442 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
2443 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
2444 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
2445 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
2447 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
2451 if (dev->data->dev_started) {
2452 if (i40e_dev_tx_queue_setup_runtime(dev, txq)) {
2453 i40e_tx_queue_release(txq);
2458 * Use a simple TX queue without offloads or
2459 * multi segs if possible
2461 i40e_set_tx_function_flag(dev, txq);
2463 dev->data->tx_queues[queue_idx] = txq;
2469 i40e_tx_queue_release(void *txq)
2471 struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
2474 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
2478 i40e_tx_queue_release_mbufs(q);
2479 rte_free(q->sw_ring);
2480 rte_memzone_free(q->mz);
2484 const struct rte_memzone *
2485 i40e_memzone_reserve(const char *name, uint32_t len, int socket_id)
2487 const struct rte_memzone *mz;
2489 mz = rte_memzone_lookup(name);
2493 mz = rte_memzone_reserve_aligned(name, len, socket_id,
2494 RTE_MEMZONE_IOVA_CONTIG, I40E_RING_BASE_ALIGN);
2499 i40e_rx_queue_release_mbufs(struct i40e_rx_queue *rxq)
2503 /* SSE Vector driver has a different way of releasing mbufs. */
2504 if (rxq->rx_using_sse) {
2505 i40e_rx_queue_release_mbufs_vec(rxq);
2509 if (!rxq->sw_ring) {
2510 PMD_DRV_LOG(DEBUG, "Pointer to sw_ring is NULL");
2514 for (i = 0; i < rxq->nb_rx_desc; i++) {
2515 if (rxq->sw_ring[i].mbuf) {
2516 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2517 rxq->sw_ring[i].mbuf = NULL;
2520 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2521 if (rxq->rx_nb_avail == 0)
2523 for (i = 0; i < rxq->rx_nb_avail; i++) {
2524 struct rte_mbuf *mbuf;
2526 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
2527 rte_pktmbuf_free_seg(mbuf);
2529 rxq->rx_nb_avail = 0;
2530 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2534 i40e_reset_rx_queue(struct i40e_rx_queue *rxq)
2540 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
2544 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2545 if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
2546 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_I40E_RX_MAX_BURST);
2548 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2549 len = rxq->nb_rx_desc;
2551 for (i = 0; i < len * sizeof(union i40e_rx_desc); i++)
2552 ((volatile char *)rxq->rx_ring)[i] = 0;
2554 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2555 for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; ++i)
2556 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2558 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2559 rxq->rx_nb_avail = 0;
2560 rxq->rx_next_avail = 0;
2561 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2562 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2564 rxq->nb_rx_hold = 0;
2566 if (rxq->pkt_first_seg != NULL)
2567 rte_pktmbuf_free(rxq->pkt_first_seg);
2569 rxq->pkt_first_seg = NULL;
2570 rxq->pkt_last_seg = NULL;
2572 rxq->rxrearm_start = 0;
2573 rxq->rxrearm_nb = 0;
2577 i40e_tx_queue_release_mbufs(struct i40e_tx_queue *txq)
2579 struct rte_eth_dev *dev;
2582 if (!txq || !txq->sw_ring) {
2583 PMD_DRV_LOG(DEBUG, "Pointer to txq or sw_ring is NULL");
2587 dev = &rte_eth_devices[txq->port_id];
2590 * vPMD tx will not set sw_ring's mbuf to NULL after free,
2591 * so need to free remains more carefully.
2593 #ifdef CC_AVX512_SUPPORT
2594 if (dev->tx_pkt_burst == i40e_xmit_pkts_vec_avx512) {
2595 struct i40e_vec_tx_entry *swr = (void *)txq->sw_ring;
2597 i = txq->tx_next_dd - txq->tx_rs_thresh + 1;
2598 if (txq->tx_tail < i) {
2599 for (; i < txq->nb_tx_desc; i++) {
2600 rte_pktmbuf_free_seg(swr[i].mbuf);
2605 for (; i < txq->tx_tail; i++) {
2606 rte_pktmbuf_free_seg(swr[i].mbuf);
2612 if (dev->tx_pkt_burst == i40e_xmit_pkts_vec_avx2 ||
2613 dev->tx_pkt_burst == i40e_xmit_pkts_vec) {
2614 i = txq->tx_next_dd - txq->tx_rs_thresh + 1;
2615 if (txq->tx_tail < i) {
2616 for (; i < txq->nb_tx_desc; i++) {
2617 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2618 txq->sw_ring[i].mbuf = NULL;
2622 for (; i < txq->tx_tail; i++) {
2623 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2624 txq->sw_ring[i].mbuf = NULL;
2627 for (i = 0; i < txq->nb_tx_desc; i++) {
2628 if (txq->sw_ring[i].mbuf) {
2629 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2630 txq->sw_ring[i].mbuf = NULL;
2637 i40e_tx_done_cleanup_full(struct i40e_tx_queue *txq,
2640 struct i40e_tx_entry *swr_ring = txq->sw_ring;
2641 uint16_t i, tx_last, tx_id;
2642 uint16_t nb_tx_free_last;
2643 uint16_t nb_tx_to_clean;
2646 /* Start free mbuf from the next of tx_tail */
2647 tx_last = txq->tx_tail;
2648 tx_id = swr_ring[tx_last].next_id;
2650 if (txq->nb_tx_free == 0 && i40e_xmit_cleanup(txq))
2653 nb_tx_to_clean = txq->nb_tx_free;
2654 nb_tx_free_last = txq->nb_tx_free;
2656 free_cnt = txq->nb_tx_desc;
2658 /* Loop through swr_ring to count the amount of
2659 * freeable mubfs and packets.
2661 for (pkt_cnt = 0; pkt_cnt < free_cnt; ) {
2662 for (i = 0; i < nb_tx_to_clean &&
2663 pkt_cnt < free_cnt &&
2664 tx_id != tx_last; i++) {
2665 if (swr_ring[tx_id].mbuf != NULL) {
2666 rte_pktmbuf_free_seg(swr_ring[tx_id].mbuf);
2667 swr_ring[tx_id].mbuf = NULL;
2670 * last segment in the packet,
2671 * increment packet count
2673 pkt_cnt += (swr_ring[tx_id].last_id == tx_id);
2676 tx_id = swr_ring[tx_id].next_id;
2679 if (txq->tx_rs_thresh > txq->nb_tx_desc -
2680 txq->nb_tx_free || tx_id == tx_last)
2683 if (pkt_cnt < free_cnt) {
2684 if (i40e_xmit_cleanup(txq))
2687 nb_tx_to_clean = txq->nb_tx_free - nb_tx_free_last;
2688 nb_tx_free_last = txq->nb_tx_free;
2692 return (int)pkt_cnt;
2696 i40e_tx_done_cleanup_simple(struct i40e_tx_queue *txq,
2701 if (free_cnt == 0 || free_cnt > txq->nb_tx_desc)
2702 free_cnt = txq->nb_tx_desc;
2704 cnt = free_cnt - free_cnt % txq->tx_rs_thresh;
2706 for (i = 0; i < cnt; i += n) {
2707 if (txq->nb_tx_desc - txq->nb_tx_free < txq->tx_rs_thresh)
2710 n = i40e_tx_free_bufs(txq);
2720 i40e_tx_done_cleanup_vec(struct i40e_tx_queue *txq __rte_unused,
2721 uint32_t free_cnt __rte_unused)
2726 i40e_tx_done_cleanup(void *txq, uint32_t free_cnt)
2728 struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
2729 struct rte_eth_dev *dev = &rte_eth_devices[q->port_id];
2730 struct i40e_adapter *ad =
2731 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2733 if (ad->tx_simple_allowed) {
2734 if (ad->tx_vec_allowed)
2735 return i40e_tx_done_cleanup_vec(q, free_cnt);
2737 return i40e_tx_done_cleanup_simple(q, free_cnt);
2739 return i40e_tx_done_cleanup_full(q, free_cnt);
2744 i40e_reset_tx_queue(struct i40e_tx_queue *txq)
2746 struct i40e_tx_entry *txe;
2747 uint16_t i, prev, size;
2750 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
2755 size = sizeof(struct i40e_tx_desc) * txq->nb_tx_desc;
2756 for (i = 0; i < size; i++)
2757 ((volatile char *)txq->tx_ring)[i] = 0;
2759 prev = (uint16_t)(txq->nb_tx_desc - 1);
2760 for (i = 0; i < txq->nb_tx_desc; i++) {
2761 volatile struct i40e_tx_desc *txd = &txq->tx_ring[i];
2763 txd->cmd_type_offset_bsz =
2764 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE);
2767 txe[prev].next_id = i;
2771 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2772 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2775 txq->nb_tx_used = 0;
2777 txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
2778 txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
2781 /* Init the TX queue in hardware */
2783 i40e_tx_queue_init(struct i40e_tx_queue *txq)
2785 enum i40e_status_code err = I40E_SUCCESS;
2786 struct i40e_vsi *vsi = txq->vsi;
2787 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2788 uint16_t pf_q = txq->reg_idx;
2789 struct i40e_hmc_obj_txq tx_ctx;
2792 /* clear the context structure first */
2793 memset(&tx_ctx, 0, sizeof(tx_ctx));
2794 tx_ctx.new_context = 1;
2795 tx_ctx.base = txq->tx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2796 tx_ctx.qlen = txq->nb_tx_desc;
2798 #ifdef RTE_LIBRTE_IEEE1588
2799 tx_ctx.timesync_ena = 1;
2801 tx_ctx.rdylist = rte_le_to_cpu_16(vsi->info.qs_handle[txq->dcb_tc]);
2802 if (vsi->type == I40E_VSI_FDIR)
2803 tx_ctx.fd_ena = TRUE;
2805 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2806 if (err != I40E_SUCCESS) {
2807 PMD_DRV_LOG(ERR, "Failure of clean lan tx queue context");
2811 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2812 if (err != I40E_SUCCESS) {
2813 PMD_DRV_LOG(ERR, "Failure of set lan tx queue context");
2817 /* Now associate this queue with this PCI function */
2818 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
2819 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2820 I40E_QTX_CTL_PF_INDX_MASK);
2821 I40E_WRITE_REG(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2822 I40E_WRITE_FLUSH(hw);
2824 txq->qtx_tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2830 i40e_alloc_rx_queue_mbufs(struct i40e_rx_queue *rxq)
2832 struct i40e_rx_entry *rxe = rxq->sw_ring;
2836 for (i = 0; i < rxq->nb_rx_desc; i++) {
2837 volatile union i40e_rx_desc *rxd;
2838 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mp);
2840 if (unlikely(!mbuf)) {
2841 PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
2845 rte_mbuf_refcnt_set(mbuf, 1);
2847 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2849 mbuf->port = rxq->port_id;
2852 rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
2854 rxd = &rxq->rx_ring[i];
2855 rxd->read.pkt_addr = dma_addr;
2856 rxd->read.hdr_addr = 0;
2857 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2858 rxd->read.rsvd1 = 0;
2859 rxd->read.rsvd2 = 0;
2860 #endif /* RTE_LIBRTE_I40E_16BYTE_RX_DESC */
2869 * Calculate the buffer length, and check the jumbo frame
2870 * and maximum packet length.
2873 i40e_rx_queue_config(struct i40e_rx_queue *rxq)
2875 struct i40e_pf *pf = I40E_VSI_TO_PF(rxq->vsi);
2876 struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2877 struct rte_eth_dev_data *data = pf->dev_data;
2880 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2881 RTE_PKTMBUF_HEADROOM);
2883 switch (pf->flags & (I40E_FLAG_HEADER_SPLIT_DISABLED |
2884 I40E_FLAG_HEADER_SPLIT_ENABLED)) {
2885 case I40E_FLAG_HEADER_SPLIT_ENABLED: /* Not supported */
2886 rxq->rx_hdr_len = RTE_ALIGN(I40E_RXBUF_SZ_1024,
2887 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2888 rxq->rx_buf_len = RTE_ALIGN(I40E_RXBUF_SZ_2048,
2889 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2890 rxq->hs_mode = i40e_header_split_enabled;
2892 case I40E_FLAG_HEADER_SPLIT_DISABLED:
2894 rxq->rx_hdr_len = 0;
2895 rxq->rx_buf_len = RTE_ALIGN_FLOOR(buf_size,
2896 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2897 rxq->hs_mode = i40e_header_split_none;
2902 RTE_MIN(hw->func_caps.rx_buf_chain_len * rxq->rx_buf_len,
2903 data->mtu + I40E_ETH_OVERHEAD);
2904 if (rxq->max_pkt_len < RTE_ETHER_MIN_LEN ||
2905 rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
2906 PMD_DRV_LOG(ERR, "maximum packet length must be "
2907 "larger than %u and smaller than %u",
2908 (uint32_t)RTE_ETHER_MIN_LEN,
2909 (uint32_t)I40E_FRAME_SIZE_MAX);
2910 return I40E_ERR_CONFIG;
2916 /* Init the RX queue in hardware */
2918 i40e_rx_queue_init(struct i40e_rx_queue *rxq)
2920 int err = I40E_SUCCESS;
2921 struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2922 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(rxq->vsi);
2923 uint16_t pf_q = rxq->reg_idx;
2925 struct i40e_hmc_obj_rxq rx_ctx;
2927 err = i40e_rx_queue_config(rxq);
2929 PMD_DRV_LOG(ERR, "Failed to config RX queue");
2933 /* Clear the context structure first */
2934 memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
2935 rx_ctx.dbuff = rxq->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2936 rx_ctx.hbuff = rxq->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2938 rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2939 rx_ctx.qlen = rxq->nb_rx_desc;
2940 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2943 rx_ctx.dtype = rxq->hs_mode;
2945 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_ALL;
2947 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
2948 rx_ctx.rxmax = rxq->max_pkt_len;
2949 rx_ctx.tphrdesc_ena = 1;
2950 rx_ctx.tphwdesc_ena = 1;
2951 rx_ctx.tphdata_ena = 1;
2952 rx_ctx.tphhead_ena = 1;
2953 rx_ctx.lrxqthresh = 2;
2954 rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
2956 /* showiv indicates if inner VLAN is stripped inside of tunnel
2957 * packet. When set it to 1, vlan information is stripped from
2958 * the inner header, but the hardware does not put it in the
2959 * descriptor. So set it zero by default.
2964 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2965 if (err != I40E_SUCCESS) {
2966 PMD_DRV_LOG(ERR, "Failed to clear LAN RX queue context");
2969 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2970 if (err != I40E_SUCCESS) {
2971 PMD_DRV_LOG(ERR, "Failed to set LAN RX queue context");
2975 rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2977 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2978 RTE_PKTMBUF_HEADROOM);
2980 /* Check if scattered RX needs to be used. */
2981 if (rxq->max_pkt_len > buf_size)
2982 dev_data->scattered_rx = 1;
2984 /* Init the RX tail regieter. */
2985 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
2991 i40e_dev_clear_queues(struct rte_eth_dev *dev)
2995 PMD_INIT_FUNC_TRACE();
2997 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2998 if (!dev->data->tx_queues[i])
3000 i40e_tx_queue_release_mbufs(dev->data->tx_queues[i]);
3001 i40e_reset_tx_queue(dev->data->tx_queues[i]);
3004 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3005 if (!dev->data->rx_queues[i])
3007 i40e_rx_queue_release_mbufs(dev->data->rx_queues[i]);
3008 i40e_reset_rx_queue(dev->data->rx_queues[i]);
3013 i40e_dev_free_queues(struct rte_eth_dev *dev)
3017 PMD_INIT_FUNC_TRACE();
3019 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3020 if (!dev->data->rx_queues[i])
3022 i40e_rx_queue_release(dev->data->rx_queues[i]);
3023 dev->data->rx_queues[i] = NULL;
3026 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3027 if (!dev->data->tx_queues[i])
3029 i40e_tx_queue_release(dev->data->tx_queues[i]);
3030 dev->data->tx_queues[i] = NULL;
3034 enum i40e_status_code
3035 i40e_fdir_setup_tx_resources(struct i40e_pf *pf)
3037 struct i40e_tx_queue *txq;
3038 const struct rte_memzone *tz = NULL;
3039 struct rte_eth_dev *dev;
3043 PMD_DRV_LOG(ERR, "PF is not available");
3044 return I40E_ERR_BAD_PTR;
3047 dev = &rte_eth_devices[pf->dev_data->port_id];
3049 /* Allocate the TX queue data structure. */
3050 txq = rte_zmalloc_socket("i40e fdir tx queue",
3051 sizeof(struct i40e_tx_queue),
3052 RTE_CACHE_LINE_SIZE,
3055 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3056 "tx queue structure.");
3057 return I40E_ERR_NO_MEMORY;
3060 /* Allocate TX hardware ring descriptors. */
3061 ring_size = sizeof(struct i40e_tx_desc) * I40E_FDIR_NUM_TX_DESC;
3062 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
3064 tz = rte_eth_dma_zone_reserve(dev, "fdir_tx_ring",
3065 I40E_FDIR_QUEUE_ID, ring_size,
3066 I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
3068 i40e_tx_queue_release(txq);
3069 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX.");
3070 return I40E_ERR_NO_MEMORY;
3074 txq->nb_tx_desc = I40E_FDIR_NUM_TX_DESC;
3075 txq->queue_id = I40E_FDIR_QUEUE_ID;
3076 txq->reg_idx = pf->fdir.fdir_vsi->base_queue;
3077 txq->vsi = pf->fdir.fdir_vsi;
3079 txq->tx_ring_phys_addr = tz->iova;
3080 txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
3083 * don't need to allocate software ring and reset for the fdir
3084 * program queue just set the queue has been configured.
3088 pf->fdir.txq_available_buf_count = I40E_FDIR_PRG_PKT_CNT;
3090 return I40E_SUCCESS;
3093 enum i40e_status_code
3094 i40e_fdir_setup_rx_resources(struct i40e_pf *pf)
3096 struct i40e_rx_queue *rxq;
3097 const struct rte_memzone *rz = NULL;
3099 struct rte_eth_dev *dev;
3102 PMD_DRV_LOG(ERR, "PF is not available");
3103 return I40E_ERR_BAD_PTR;
3106 dev = &rte_eth_devices[pf->dev_data->port_id];
3108 /* Allocate the RX queue data structure. */
3109 rxq = rte_zmalloc_socket("i40e fdir rx queue",
3110 sizeof(struct i40e_rx_queue),
3111 RTE_CACHE_LINE_SIZE,
3114 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3115 "rx queue structure.");
3116 return I40E_ERR_NO_MEMORY;
3119 /* Allocate RX hardware ring descriptors. */
3120 ring_size = sizeof(union i40e_rx_desc) * I40E_FDIR_NUM_RX_DESC;
3121 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
3123 rz = rte_eth_dma_zone_reserve(dev, "fdir_rx_ring",
3124 I40E_FDIR_QUEUE_ID, ring_size,
3125 I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
3127 i40e_rx_queue_release(rxq);
3128 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX.");
3129 return I40E_ERR_NO_MEMORY;
3133 rxq->nb_rx_desc = I40E_FDIR_NUM_RX_DESC;
3134 rxq->queue_id = I40E_FDIR_QUEUE_ID;
3135 rxq->reg_idx = pf->fdir.fdir_vsi->base_queue;
3136 rxq->vsi = pf->fdir.fdir_vsi;
3138 rxq->rx_ring_phys_addr = rz->iova;
3139 memset(rz->addr, 0, I40E_FDIR_NUM_RX_DESC * sizeof(union i40e_rx_desc));
3140 rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
3143 * Don't need to allocate software ring and reset for the fdir
3144 * rx queue, just set the queue has been configured.
3149 return I40E_SUCCESS;
3153 i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
3154 struct rte_eth_rxq_info *qinfo)
3156 struct i40e_rx_queue *rxq;
3158 rxq = dev->data->rx_queues[queue_id];
3160 qinfo->mp = rxq->mp;
3161 qinfo->scattered_rx = dev->data->scattered_rx;
3162 qinfo->nb_desc = rxq->nb_rx_desc;
3164 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
3165 qinfo->conf.rx_drop_en = rxq->drop_en;
3166 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
3167 qinfo->conf.offloads = rxq->offloads;
3171 i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
3172 struct rte_eth_txq_info *qinfo)
3174 struct i40e_tx_queue *txq;
3176 txq = dev->data->tx_queues[queue_id];
3178 qinfo->nb_desc = txq->nb_tx_desc;
3180 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
3181 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
3182 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
3184 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
3185 qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
3186 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
3187 qinfo->conf.offloads = txq->offloads;
3192 get_avx_supported(bool request_avx512)
3194 if (request_avx512) {
3195 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512 &&
3196 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 &&
3197 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1)
3198 #ifdef CC_AVX512_SUPPORT
3202 "AVX512 is not supported in build env");
3206 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256 &&
3207 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 &&
3208 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1)
3209 #ifdef CC_AVX2_SUPPORT
3213 "AVX2 is not supported in build env");
3220 #endif /* RTE_ARCH_X86 */
3224 i40e_set_rx_function(struct rte_eth_dev *dev)
3226 struct i40e_adapter *ad =
3227 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3228 uint16_t rx_using_sse, i;
3229 /* In order to allow Vector Rx there are a few configuration
3230 * conditions to be met and Rx Bulk Allocation should be allowed.
3232 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3234 ad->rx_use_avx512 = false;
3235 ad->rx_use_avx2 = false;
3237 if (i40e_rx_vec_dev_conf_condition_check(dev) ||
3238 !ad->rx_bulk_alloc_allowed) {
3239 PMD_INIT_LOG(DEBUG, "Port[%d] doesn't meet"
3240 " Vector Rx preconditions",
3241 dev->data->port_id);
3243 ad->rx_vec_allowed = false;
3245 if (ad->rx_vec_allowed) {
3246 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3247 struct i40e_rx_queue *rxq =
3248 dev->data->rx_queues[i];
3250 if (rxq && i40e_rxq_vec_setup(rxq)) {
3251 ad->rx_vec_allowed = false;
3256 ad->rx_use_avx512 = get_avx_supported(1);
3258 if (!ad->rx_use_avx512)
3259 ad->rx_use_avx2 = get_avx_supported(0);
3264 if (ad->rx_vec_allowed &&
3265 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
3267 if (dev->data->scattered_rx) {
3268 if (ad->rx_use_avx512) {
3269 #ifdef CC_AVX512_SUPPORT
3271 "Using AVX512 Vector Scattered Rx (port %d).",
3272 dev->data->port_id);
3274 i40e_recv_scattered_pkts_vec_avx512;
3278 "Using %sVector Scattered Rx (port %d).",
3279 ad->rx_use_avx2 ? "avx2 " : "",
3280 dev->data->port_id);
3281 dev->rx_pkt_burst = ad->rx_use_avx2 ?
3282 i40e_recv_scattered_pkts_vec_avx2 :
3283 i40e_recv_scattered_pkts_vec;
3286 if (ad->rx_use_avx512) {
3287 #ifdef CC_AVX512_SUPPORT
3289 "Using AVX512 Vector Rx (port %d).",
3290 dev->data->port_id);
3292 i40e_recv_pkts_vec_avx512;
3296 "Using %sVector Rx (port %d).",
3297 ad->rx_use_avx2 ? "avx2 " : "",
3298 dev->data->port_id);
3299 dev->rx_pkt_burst = ad->rx_use_avx2 ?
3300 i40e_recv_pkts_vec_avx2 :
3304 #else /* RTE_ARCH_X86 */
3305 if (dev->data->scattered_rx) {
3307 "Using Vector Scattered Rx (port %d).",
3308 dev->data->port_id);
3309 dev->rx_pkt_burst = i40e_recv_scattered_pkts_vec;
3311 PMD_INIT_LOG(DEBUG, "Using Vector Rx (port %d).",
3312 dev->data->port_id);
3313 dev->rx_pkt_burst = i40e_recv_pkts_vec;
3315 #endif /* RTE_ARCH_X86 */
3316 } else if (!dev->data->scattered_rx && ad->rx_bulk_alloc_allowed) {
3317 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
3318 "satisfied. Rx Burst Bulk Alloc function "
3319 "will be used on port=%d.",
3320 dev->data->port_id);
3322 dev->rx_pkt_burst = i40e_recv_pkts_bulk_alloc;
3324 /* Simple Rx Path. */
3325 PMD_INIT_LOG(DEBUG, "Simple Rx path will be used on port=%d.",
3326 dev->data->port_id);
3327 dev->rx_pkt_burst = dev->data->scattered_rx ?
3328 i40e_recv_scattered_pkts :
3332 /* Propagate information about RX function choice through all queues. */
3333 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3335 (dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
3336 dev->rx_pkt_burst == i40e_recv_pkts_vec ||
3337 #ifdef CC_AVX512_SUPPORT
3338 dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec_avx512 ||
3339 dev->rx_pkt_burst == i40e_recv_pkts_vec_avx512 ||
3341 dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec_avx2 ||
3342 dev->rx_pkt_burst == i40e_recv_pkts_vec_avx2);
3344 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3345 struct i40e_rx_queue *rxq = dev->data->rx_queues[i];
3348 rxq->rx_using_sse = rx_using_sse;
3353 static const struct {
3354 eth_rx_burst_t pkt_burst;
3356 } i40e_rx_burst_infos[] = {
3357 { i40e_recv_scattered_pkts, "Scalar Scattered" },
3358 { i40e_recv_pkts_bulk_alloc, "Scalar Bulk Alloc" },
3359 { i40e_recv_pkts, "Scalar" },
3361 #ifdef CC_AVX512_SUPPORT
3362 { i40e_recv_scattered_pkts_vec_avx512, "Vector AVX512 Scattered" },
3363 { i40e_recv_pkts_vec_avx512, "Vector AVX512" },
3365 { i40e_recv_scattered_pkts_vec_avx2, "Vector AVX2 Scattered" },
3366 { i40e_recv_pkts_vec_avx2, "Vector AVX2" },
3367 { i40e_recv_scattered_pkts_vec, "Vector SSE Scattered" },
3368 { i40e_recv_pkts_vec, "Vector SSE" },
3369 #elif defined(RTE_ARCH_ARM64)
3370 { i40e_recv_scattered_pkts_vec, "Vector Neon Scattered" },
3371 { i40e_recv_pkts_vec, "Vector Neon" },
3372 #elif defined(RTE_ARCH_PPC_64)
3373 { i40e_recv_scattered_pkts_vec, "Vector AltiVec Scattered" },
3374 { i40e_recv_pkts_vec, "Vector AltiVec" },
3379 i40e_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
3380 struct rte_eth_burst_mode *mode)
3382 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
3386 for (i = 0; i < RTE_DIM(i40e_rx_burst_infos); ++i) {
3387 if (pkt_burst == i40e_rx_burst_infos[i].pkt_burst) {
3388 snprintf(mode->info, sizeof(mode->info), "%s",
3389 i40e_rx_burst_infos[i].info);
3399 i40e_set_tx_function_flag(struct rte_eth_dev *dev, struct i40e_tx_queue *txq)
3401 struct i40e_adapter *ad =
3402 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3404 /* Use a simple Tx queue if possible (only fast free is allowed) */
3405 ad->tx_simple_allowed =
3407 (txq->offloads & RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE) &&
3408 txq->tx_rs_thresh >= RTE_PMD_I40E_TX_MAX_BURST);
3409 ad->tx_vec_allowed = (ad->tx_simple_allowed &&
3410 txq->tx_rs_thresh <= RTE_I40E_TX_MAX_FREE_BUF_SZ);
3412 if (ad->tx_vec_allowed)
3413 PMD_INIT_LOG(DEBUG, "Vector Tx can be enabled on Tx queue %u.",
3415 else if (ad->tx_simple_allowed)
3416 PMD_INIT_LOG(DEBUG, "Simple Tx can be enabled on Tx queue %u.",
3420 "Neither simple nor vector Tx enabled on Tx queue %u\n",
3425 i40e_set_tx_function(struct rte_eth_dev *dev)
3427 struct i40e_adapter *ad =
3428 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3431 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3433 ad->tx_use_avx2 = false;
3434 ad->tx_use_avx512 = false;
3436 if (ad->tx_vec_allowed) {
3437 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3438 struct i40e_tx_queue *txq =
3439 dev->data->tx_queues[i];
3441 if (txq && i40e_txq_vec_setup(txq)) {
3442 ad->tx_vec_allowed = false;
3447 ad->tx_use_avx512 = get_avx_supported(1);
3449 if (!ad->tx_use_avx512)
3450 ad->tx_use_avx2 = get_avx_supported(0);
3455 if (ad->tx_simple_allowed) {
3456 if (ad->tx_vec_allowed &&
3457 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
3459 if (ad->tx_use_avx512) {
3460 #ifdef CC_AVX512_SUPPORT
3461 PMD_DRV_LOG(NOTICE, "Using AVX512 Vector Tx (port %d).",
3462 dev->data->port_id);
3463 dev->tx_pkt_burst = i40e_xmit_pkts_vec_avx512;
3466 PMD_INIT_LOG(DEBUG, "Using %sVector Tx (port %d).",
3467 ad->tx_use_avx2 ? "avx2 " : "",
3468 dev->data->port_id);
3469 dev->tx_pkt_burst = ad->tx_use_avx2 ?
3470 i40e_xmit_pkts_vec_avx2 :
3473 #else /* RTE_ARCH_X86 */
3474 PMD_INIT_LOG(DEBUG, "Using Vector Tx (port %d).",
3475 dev->data->port_id);
3476 dev->tx_pkt_burst = i40e_xmit_pkts_vec;
3477 #endif /* RTE_ARCH_X86 */
3479 PMD_INIT_LOG(DEBUG, "Simple tx finally be used.");
3480 dev->tx_pkt_burst = i40e_xmit_pkts_simple;
3482 dev->tx_pkt_prepare = i40e_simple_prep_pkts;
3484 PMD_INIT_LOG(DEBUG, "Xmit tx finally be used.");
3485 dev->tx_pkt_burst = i40e_xmit_pkts;
3486 dev->tx_pkt_prepare = i40e_prep_pkts;
3490 static const struct {
3491 eth_tx_burst_t pkt_burst;
3493 } i40e_tx_burst_infos[] = {
3494 { i40e_xmit_pkts_simple, "Scalar Simple" },
3495 { i40e_xmit_pkts, "Scalar" },
3497 #ifdef CC_AVX512_SUPPORT
3498 { i40e_xmit_pkts_vec_avx512, "Vector AVX512" },
3500 { i40e_xmit_pkts_vec_avx2, "Vector AVX2" },
3501 { i40e_xmit_pkts_vec, "Vector SSE" },
3502 #elif defined(RTE_ARCH_ARM64)
3503 { i40e_xmit_pkts_vec, "Vector Neon" },
3504 #elif defined(RTE_ARCH_PPC_64)
3505 { i40e_xmit_pkts_vec, "Vector AltiVec" },
3510 i40e_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
3511 struct rte_eth_burst_mode *mode)
3513 eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
3517 for (i = 0; i < RTE_DIM(i40e_tx_burst_infos); ++i) {
3518 if (pkt_burst == i40e_tx_burst_infos[i].pkt_burst) {
3519 snprintf(mode->info, sizeof(mode->info), "%s",
3520 i40e_tx_burst_infos[i].info);
3530 i40e_set_default_ptype_table(struct rte_eth_dev *dev)
3532 struct i40e_adapter *ad =
3533 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3536 for (i = 0; i < I40E_MAX_PKT_TYPE; i++)
3537 ad->ptype_tbl[i] = i40e_get_default_pkt_type(i);
3541 i40e_set_default_pctype_table(struct rte_eth_dev *dev)
3543 struct i40e_adapter *ad =
3544 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3545 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3548 for (i = 0; i < I40E_FLOW_TYPE_MAX; i++)
3549 ad->pctypes_tbl[i] = 0ULL;
3550 ad->flow_types_mask = 0ULL;
3551 ad->pctypes_mask = 0ULL;
3553 ad->pctypes_tbl[RTE_ETH_FLOW_FRAG_IPV4] =
3554 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4);
3555 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
3556 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP);
3557 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
3558 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP);
3559 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
3560 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP);
3561 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
3562 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER);
3563 ad->pctypes_tbl[RTE_ETH_FLOW_FRAG_IPV6] =
3564 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6);
3565 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
3566 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP);
3567 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
3568 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP);
3569 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
3570 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP);
3571 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
3572 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER);
3573 ad->pctypes_tbl[RTE_ETH_FLOW_L2_PAYLOAD] =
3574 (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD);
3576 if (hw->mac.type == I40E_MAC_X722 ||
3577 hw->mac.type == I40E_MAC_X722_VF) {
3578 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_UDP] |=
3579 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP);
3580 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_UDP] |=
3581 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
3582 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_TCP] |=
3583 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
3584 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_UDP] |=
3585 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP);
3586 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_UDP] |=
3587 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
3588 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_TCP] |=
3589 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
3592 for (i = 0; i < I40E_FLOW_TYPE_MAX; i++) {
3593 if (ad->pctypes_tbl[i])
3594 ad->flow_types_mask |= (1ULL << i);
3595 ad->pctypes_mask |= ad->pctypes_tbl[i];
3599 #ifndef CC_AVX2_SUPPORT
3601 i40e_recv_pkts_vec_avx2(void __rte_unused *rx_queue,
3602 struct rte_mbuf __rte_unused **rx_pkts,
3603 uint16_t __rte_unused nb_pkts)
3609 i40e_recv_scattered_pkts_vec_avx2(void __rte_unused *rx_queue,
3610 struct rte_mbuf __rte_unused **rx_pkts,
3611 uint16_t __rte_unused nb_pkts)
3617 i40e_xmit_pkts_vec_avx2(void __rte_unused * tx_queue,
3618 struct rte_mbuf __rte_unused **tx_pkts,
3619 uint16_t __rte_unused nb_pkts)
3623 #endif /* ifndef CC_AVX2_SUPPORT */