drivers/net/i40e/i40e_rxtx.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <stdlib.h>
  36 #include <string.h>
  37 #include <errno.h>
  38 #include <stdint.h>
  39 #include <stdarg.h>
  40 #include <unistd.h>
  41 #include <inttypes.h>
  42 #include <sys/queue.h>
  43
  44 #include <rte_string_fns.h>
  45 #include <rte_memzone.h>
  46 #include <rte_mbuf.h>
  47 #include <rte_malloc.h>
  48 #include <rte_ether.h>
  49 #include <rte_ethdev.h>
  50 #include <rte_tcp.h>
  51 #include <rte_sctp.h>
  52 #include <rte_udp.h>
  53 #include <rte_ip.h>
  54 #include <rte_net.h>
  55
  56 #include "i40e_logs.h"
  57 #include "base/i40e_prototype.h"
  58 #include "base/i40e_type.h"
  59 #include "i40e_ethdev.h"
  60 #include "i40e_rxtx.h"
  61
  62 #define DEFAULT_TX_RS_THRESH   32
  63 #define DEFAULT_TX_FREE_THRESH 32
  64 #define I40E_MAX_PKT_TYPE      256
  65
  66 #define I40E_TX_MAX_BURST  32
  67
  68 #define I40E_DMA_MEM_ALIGN 4096
  69
  70 /* Base address of the HW descriptor ring should be 128B aligned. */
  71 #define I40E_RING_BASE_ALIGN    128
  72
  73 #define I40E_SIMPLE_FLAGS ((uint32_t)ETH_TXQ_FLAGS_NOMULTSEGS | \
  74                                         ETH_TXQ_FLAGS_NOOFFLOADS)
  75
  76 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
  77
  78 #ifdef RTE_LIBRTE_IEEE1588
  79 #define I40E_TX_IEEE1588_TMST PKT_TX_IEEE1588_TMST
  80 #else
  81 #define I40E_TX_IEEE1588_TMST 0
  82 #endif
  83
  84 #define I40E_TX_CKSUM_OFFLOAD_MASK (             \
  85                 PKT_TX_IP_CKSUM |                \
  86                 PKT_TX_L4_MASK |                 \
  87                 PKT_TX_TCP_SEG |                 \
  88                 PKT_TX_OUTER_IP_CKSUM)
  89
  90 #define I40E_TX_OFFLOAD_MASK (  \
  91                 PKT_TX_IP_CKSUM |       \
  92                 PKT_TX_L4_MASK |        \
  93                 PKT_TX_OUTER_IP_CKSUM | \
  94                 PKT_TX_TCP_SEG |        \
  95                 PKT_TX_QINQ_PKT |       \
  96                 PKT_TX_VLAN_PKT |       \
  97                 PKT_TX_TUNNEL_MASK |    \
  98                 I40E_TX_IEEE1588_TMST)
  99
 100 #define I40E_TX_OFFLOAD_NOTSUP_MASK \
 101                 (PKT_TX_OFFLOAD_MASK ^ I40E_TX_OFFLOAD_MASK)
 102
 103 static uint16_t i40e_xmit_pkts_simple(void *tx_queue,
 104                                       struct rte_mbuf **tx_pkts,
 105                                       uint16_t nb_pkts);
 106
 107 static inline void
 108 i40e_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union i40e_rx_desc *rxdp)
 109 {
 110         if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
 111                 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
 112                 mb->ol_flags |= PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
 113                 mb->vlan_tci =
 114                         rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
 115                 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
 116                            rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1));
 117         } else {
 118                 mb->vlan_tci = 0;
 119         }
 120 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
 121         if (rte_le_to_cpu_16(rxdp->wb.qword2.ext_status) &
 122                 (1 << I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT)) {
 123                 mb->ol_flags |= PKT_RX_QINQ_STRIPPED;
 124                 mb->vlan_tci_outer = mb->vlan_tci;
 125                 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2);
 126                 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
 127                            rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_1),
 128                            rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2));
 129         } else {
 130                 mb->vlan_tci_outer = 0;
 131         }
 132 #endif
 133         PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
 134                    mb->vlan_tci, mb->vlan_tci_outer);
 135 }
 136
 137 /* Translate the rx descriptor status to pkt flags */
 138 static inline uint64_t
 139 i40e_rxd_status_to_pkt_flags(uint64_t qword)
 140 {
 141         uint64_t flags;
 142
 143         /* Check if RSS_HASH */
 144         flags = (((qword >> I40E_RX_DESC_STATUS_FLTSTAT_SHIFT) &
 145                                         I40E_RX_DESC_FLTSTAT_RSS_HASH) ==
 146                         I40E_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;
 147
 148         /* Check if FDIR Match */
 149         flags |= (qword & (1 << I40E_RX_DESC_STATUS_FLM_SHIFT) ?
 150                                                         PKT_RX_FDIR : 0);
 151
 152         return flags;
 153 }
 154
 155 static inline uint64_t
 156 i40e_rxd_error_to_pkt_flags(uint64_t qword)
 157 {
 158         uint64_t flags = 0;
 159         uint64_t error_bits = (qword >> I40E_RXD_QW1_ERROR_SHIFT);
 160
 161 #define I40E_RX_ERR_BITS 0x3f
 162         if (likely((error_bits & I40E_RX_ERR_BITS) == 0)) {
 163                 flags |= (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD);
 164                 return flags;
 165         }
 166
 167         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_IPE_SHIFT)))
 168                 flags |= PKT_RX_IP_CKSUM_BAD;
 169         else
 170                 flags |= PKT_RX_IP_CKSUM_GOOD;
 171
 172         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT)))
 173                 flags |= PKT_RX_L4_CKSUM_BAD;
 174         else
 175                 flags |= PKT_RX_L4_CKSUM_GOOD;
 176
 177         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT)))
 178                 flags |= PKT_RX_EIP_CKSUM_BAD;
 179
 180         return flags;
 181 }
 182
 183 /* Function to check and set the ieee1588 timesync index and get the
 184  * appropriate flags.
 185  */
 186 #ifdef RTE_LIBRTE_IEEE1588
 187 static inline uint64_t
 188 i40e_get_iee15888_flags(struct rte_mbuf *mb, uint64_t qword)
 189 {
 190         uint64_t pkt_flags = 0;
 191         uint16_t tsyn = (qword & (I40E_RXD_QW1_STATUS_TSYNVALID_MASK
 192                                   | I40E_RXD_QW1_STATUS_TSYNINDX_MASK))
 193                                     >> I40E_RX_DESC_STATUS_TSYNINDX_SHIFT;
 194
 195         if ((mb->packet_type & RTE_PTYPE_L2_MASK)
 196                         == RTE_PTYPE_L2_ETHER_TIMESYNC)
 197                 pkt_flags = PKT_RX_IEEE1588_PTP;
 198         if (tsyn & 0x04) {
 199                 pkt_flags |= PKT_RX_IEEE1588_TMST;
 200                 mb->timesync = tsyn & 0x03;
 201         }
 202
 203         return pkt_flags;
 204 }
 205 #endif
 206
 207 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK   0x03
 208 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID  0x01
 209 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX   0x02
 210 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK   0x03
 211 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX   0x01
 212
 213 static inline uint64_t
 214 i40e_rxd_build_fdir(volatile union i40e_rx_desc *rxdp, struct rte_mbuf *mb)
 215 {
 216         uint64_t flags = 0;
 217 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
 218         uint16_t flexbh, flexbl;
 219
 220         flexbh = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
 221                 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT) &
 222                 I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK;
 223         flexbl = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
 224                 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT) &
 225                 I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK;
 226
 227
 228         if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID) {
 229                 mb->hash.fdir.hi =
 230                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.fd_id);
 231                 flags |= PKT_RX_FDIR_ID;
 232         } else if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX) {
 233                 mb->hash.fdir.hi =
 234                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.flex_bytes_hi);
 235                 flags |= PKT_RX_FDIR_FLX;
 236         }
 237         if (flexbl == I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX) {
 238                 mb->hash.fdir.lo =
 239                         rte_le_to_cpu_32(rxdp->wb.qword3.lo_dword.flex_bytes_lo);
 240                 flags |= PKT_RX_FDIR_FLX;
 241         }
 242 #else
 243         mb->hash.fdir.hi =
 244                 rte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.fd_id);
 245         flags |= PKT_RX_FDIR_ID;
 246 #endif
 247         return flags;
 248 }
 249
 250 static inline void
 251 i40e_parse_tunneling_params(uint64_t ol_flags,
 252                             union i40e_tx_offload tx_offload,
 253                             uint32_t *cd_tunneling)
 254 {
 255         /* EIPT: External (outer) IP header type */
 256         if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
 257                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
 258         else if (ol_flags & PKT_TX_OUTER_IPV4)
 259                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
 260         else if (ol_flags & PKT_TX_OUTER_IPV6)
 261                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
 262
 263         /* EIPLEN: External (outer) IP header length, in DWords */
 264         *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
 265                 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT;
 266
 267         /* L4TUNT: L4 Tunneling Type */
 268         switch (ol_flags & PKT_TX_TUNNEL_MASK) {
 269         case PKT_TX_TUNNEL_IPIP:
 270                 /* for non UDP / GRE tunneling, set to 00b */
 271                 break;
 272         case PKT_TX_TUNNEL_VXLAN:
 273         case PKT_TX_TUNNEL_GENEVE:
 274                 *cd_tunneling |= I40E_TXD_CTX_UDP_TUNNELING;
 275                 break;
 276         case PKT_TX_TUNNEL_GRE:
 277                 *cd_tunneling |= I40E_TXD_CTX_GRE_TUNNELING;
 278                 break;
 279         default:
 280                 PMD_TX_LOG(ERR, "Tunnel type not supported");
 281                 return;
 282         }
 283
 284         /* L4TUNLEN: L4 Tunneling Length, in Words
 285          *
 286          * We depend on app to set rte_mbuf.l2_len correctly.
 287          * For IP in GRE it should be set to the length of the GRE
 288          * header;
 289          * for MAC in GRE or MAC in UDP it should be set to the length
 290          * of the GRE or UDP headers plus the inner MAC up to including
 291          * its last Ethertype.
 292          */
 293         *cd_tunneling |= (tx_offload.l2_len >> 1) <<
 294                 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
 295 }
 296
 297 static inline void
 298 i40e_txd_enable_checksum(uint64_t ol_flags,
 299                         uint32_t *td_cmd,
 300                         uint32_t *td_offset,
 301                         union i40e_tx_offload tx_offload)
 302 {
 303         /* Set MACLEN */
 304         if (ol_flags & PKT_TX_TUNNEL_MASK)
 305                 *td_offset |= (tx_offload.outer_l2_len >> 1)
 306                                 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
 307         else
 308                 *td_offset |= (tx_offload.l2_len >> 1)
 309                         << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
 310
 311         /* Enable L3 checksum offloads */
 312         if (ol_flags & PKT_TX_IP_CKSUM) {
 313                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
 314                 *td_offset |= (tx_offload.l3_len >> 2)
 315                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 316         } else if (ol_flags & PKT_TX_IPV4) {
 317                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
 318                 *td_offset |= (tx_offload.l3_len >> 2)
 319                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 320         } else if (ol_flags & PKT_TX_IPV6) {
 321                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
 322                 *td_offset |= (tx_offload.l3_len >> 2)
 323                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 324         }
 325
 326         if (ol_flags & PKT_TX_TCP_SEG) {
 327                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
 328                 *td_offset |= (tx_offload.l4_len >> 2)
 329                         << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 330                 return;
 331         }
 332
 333         /* Enable L4 checksum offloads */
 334         switch (ol_flags & PKT_TX_L4_MASK) {
 335         case PKT_TX_TCP_CKSUM:
 336                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
 337                 *td_offset |= (sizeof(struct tcp_hdr) >> 2) <<
 338                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 339                 break;
 340         case PKT_TX_SCTP_CKSUM:
 341                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
 342                 *td_offset |= (sizeof(struct sctp_hdr) >> 2) <<
 343                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 344                 break;
 345         case PKT_TX_UDP_CKSUM:
 346                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
 347                 *td_offset |= (sizeof(struct udp_hdr) >> 2) <<
 348                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 349                 break;
 350         default:
 351                 break;
 352         }
 353 }
 354
 355 /* Construct the tx flags */
 356 static inline uint64_t
 357 i40e_build_ctob(uint32_t td_cmd,
 358                 uint32_t td_offset,
 359                 unsigned int size,
 360                 uint32_t td_tag)
 361 {
 362         return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
 363                         ((uint64_t)td_cmd  << I40E_TXD_QW1_CMD_SHIFT) |
 364                         ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
 365                         ((uint64_t)size  << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
 366                         ((uint64_t)td_tag  << I40E_TXD_QW1_L2TAG1_SHIFT));
 367 }
 368
 369 static inline int
 370 i40e_xmit_cleanup(struct i40e_tx_queue *txq)
 371 {
 372         struct i40e_tx_entry *sw_ring = txq->sw_ring;
 373         volatile struct i40e_tx_desc *txd = txq->tx_ring;
 374         uint16_t last_desc_cleaned = txq->last_desc_cleaned;
 375         uint16_t nb_tx_desc = txq->nb_tx_desc;
 376         uint16_t desc_to_clean_to;
 377         uint16_t nb_tx_to_clean;
 378
 379         desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
 380         if (desc_to_clean_to >= nb_tx_desc)
 381                 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
 382
 383         desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
 384         if ((txd[desc_to_clean_to].cmd_type_offset_bsz &
 385                         rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
 386                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE)) {
 387                 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
 388                         "(port=%d queue=%d)", desc_to_clean_to,
 389                                 txq->port_id, txq->queue_id);
 390                 return -1;
 391         }
 392
 393         if (last_desc_cleaned > desc_to_clean_to)
 394                 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
 395                                                         desc_to_clean_to);
 396         else
 397                 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
 398                                         last_desc_cleaned);
 399
 400         txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
 401
 402         txq->last_desc_cleaned = desc_to_clean_to;
 403         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
 404
 405         return 0;
 406 }
 407
 408 static inline int
 409 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 410 check_rx_burst_bulk_alloc_preconditions(struct i40e_rx_queue *rxq)
 411 #else
 412 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct i40e_rx_queue *rxq)
 413 #endif
 414 {
 415         int ret = 0;
 416
 417 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 418         if (!(rxq->rx_free_thresh >= RTE_PMD_I40E_RX_MAX_BURST)) {
 419                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 420                              "rxq->rx_free_thresh=%d, "
 421                              "RTE_PMD_I40E_RX_MAX_BURST=%d",
 422                              rxq->rx_free_thresh, RTE_PMD_I40E_RX_MAX_BURST);
 423                 ret = -EINVAL;
 424         } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
 425                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 426                              "rxq->rx_free_thresh=%d, "
 427                              "rxq->nb_rx_desc=%d",
 428                              rxq->rx_free_thresh, rxq->nb_rx_desc);
 429                 ret = -EINVAL;
 430         } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
 431                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 432                              "rxq->nb_rx_desc=%d, "
 433                              "rxq->rx_free_thresh=%d",
 434                              rxq->nb_rx_desc, rxq->rx_free_thresh);
 435                 ret = -EINVAL;
 436         }
 437 #else
 438         ret = -EINVAL;
 439 #endif
 440
 441         return ret;
 442 }
 443
 444 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 445 #define I40E_LOOK_AHEAD 8
 446 #if (I40E_LOOK_AHEAD != 8)
 447 #error "PMD I40E: I40E_LOOK_AHEAD must be 8\n"
 448 #endif
 449 static inline int
 450 i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq)
 451 {
 452         volatile union i40e_rx_desc *rxdp;
 453         struct i40e_rx_entry *rxep;
 454         struct rte_mbuf *mb;
 455         uint16_t pkt_len;
 456         uint64_t qword1;
 457         uint32_t rx_status;
 458         int32_t s[I40E_LOOK_AHEAD], nb_dd;
 459         int32_t i, j, nb_rx = 0;
 460         uint64_t pkt_flags;
 461
 462         rxdp = &rxq->rx_ring[rxq->rx_tail];
 463         rxep = &rxq->sw_ring[rxq->rx_tail];
 464
 465         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 466         rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 467                                 I40E_RXD_QW1_STATUS_SHIFT;
 468
 469         /* Make sure there is at least 1 packet to receive */
 470         if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 471                 return 0;
 472
 473         /**
 474          * Scan LOOK_AHEAD descriptors at a time to determine which
 475          * descriptors reference packets that are ready to be received.
 476          */
 477         for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; i+=I40E_LOOK_AHEAD,
 478                         rxdp += I40E_LOOK_AHEAD, rxep += I40E_LOOK_AHEAD) {
 479                 /* Read desc statuses backwards to avoid race condition */
 480                 for (j = I40E_LOOK_AHEAD - 1; j >= 0; j--) {
 481                         qword1 = rte_le_to_cpu_64(\
 482                                 rxdp[j].wb.qword1.status_error_len);
 483                         s[j] = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 484                                         I40E_RXD_QW1_STATUS_SHIFT;
 485                 }
 486
 487                 rte_smp_rmb();
 488
 489                 /* Compute how many status bits were set */
 490                 for (j = 0, nb_dd = 0; j < I40E_LOOK_AHEAD; j++)
 491                         nb_dd += s[j] & (1 << I40E_RX_DESC_STATUS_DD_SHIFT);
 492
 493                 nb_rx += nb_dd;
 494
 495                 /* Translate descriptor info to mbuf parameters */
 496                 for (j = 0; j < nb_dd; j++) {
 497                         mb = rxep[j].mbuf;
 498                         qword1 = rte_le_to_cpu_64(\
 499                                 rxdp[j].wb.qword1.status_error_len);
 500                         pkt_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 501                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
 502                         mb->data_len = pkt_len;
 503                         mb->pkt_len = pkt_len;
 504                         mb->ol_flags = 0;
 505                         i40e_rxd_to_vlan_tci(mb, &rxdp[j]);
 506                         pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
 507                         pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
 508                         mb->packet_type =
 509                                 i40e_rxd_pkt_type_mapping((uint8_t)((qword1 &
 510                                                 I40E_RXD_QW1_PTYPE_MASK) >>
 511                                                 I40E_RXD_QW1_PTYPE_SHIFT));
 512                         if (pkt_flags & PKT_RX_RSS_HASH)
 513                                 mb->hash.rss = rte_le_to_cpu_32(\
 514                                         rxdp[j].wb.qword0.hi_dword.rss);
 515                         if (pkt_flags & PKT_RX_FDIR)
 516                                 pkt_flags |= i40e_rxd_build_fdir(&rxdp[j], mb);
 517
 518 #ifdef RTE_LIBRTE_IEEE1588
 519                         pkt_flags |= i40e_get_iee15888_flags(mb, qword1);
 520 #endif
 521                         mb->ol_flags |= pkt_flags;
 522
 523                 }
 524
 525                 for (j = 0; j < I40E_LOOK_AHEAD; j++)
 526                         rxq->rx_stage[i + j] = rxep[j].mbuf;
 527
 528                 if (nb_dd != I40E_LOOK_AHEAD)
 529                         break;
 530         }
 531
 532         /* Clear software ring entries */
 533         for (i = 0; i < nb_rx; i++)
 534                 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
 535
 536         return nb_rx;
 537 }
 538
 539 static inline uint16_t
 540 i40e_rx_fill_from_stage(struct i40e_rx_queue *rxq,
 541                         struct rte_mbuf **rx_pkts,
 542                         uint16_t nb_pkts)
 543 {
 544         uint16_t i;
 545         struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
 546
 547         nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
 548
 549         for (i = 0; i < nb_pkts; i++)
 550                 rx_pkts[i] = stage[i];
 551
 552         rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
 553         rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
 554
 555         return nb_pkts;
 556 }
 557
 558 static inline int
 559 i40e_rx_alloc_bufs(struct i40e_rx_queue *rxq)
 560 {
 561         volatile union i40e_rx_desc *rxdp;
 562         struct i40e_rx_entry *rxep;
 563         struct rte_mbuf *mb;
 564         uint16_t alloc_idx, i;
 565         uint64_t dma_addr;
 566         int diag;
 567
 568         /* Allocate buffers in bulk */
 569         alloc_idx = (uint16_t)(rxq->rx_free_trigger -
 570                                 (rxq->rx_free_thresh - 1));
 571         rxep = &(rxq->sw_ring[alloc_idx]);
 572         diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
 573                                         rxq->rx_free_thresh);
 574         if (unlikely(diag != 0)) {
 575                 PMD_DRV_LOG(ERR, "Failed to get mbufs in bulk");
 576                 return -ENOMEM;
 577         }
 578
 579         rxdp = &rxq->rx_ring[alloc_idx];
 580         for (i = 0; i < rxq->rx_free_thresh; i++) {
 581                 if (likely(i < (rxq->rx_free_thresh - 1)))
 582                         /* Prefetch next mbuf */
 583                         rte_prefetch0(rxep[i + 1].mbuf);
 584
 585                 mb = rxep[i].mbuf;
 586                 rte_mbuf_refcnt_set(mb, 1);
 587                 mb->next = NULL;
 588                 mb->data_off = RTE_PKTMBUF_HEADROOM;
 589                 mb->nb_segs = 1;
 590                 mb->port = rxq->port_id;
 591                 dma_addr = rte_cpu_to_le_64(\
 592                         rte_mbuf_data_dma_addr_default(mb));
 593                 rxdp[i].read.hdr_addr = 0;
 594                 rxdp[i].read.pkt_addr = dma_addr;
 595         }
 596
 597         /* Update rx tail regsiter */
 598         rte_wmb();
 599         I40E_PCI_REG_WRITE_RELAXED(rxq->qrx_tail, rxq->rx_free_trigger);
 600
 601         rxq->rx_free_trigger =
 602                 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
 603         if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
 604                 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
 605
 606         return 0;
 607 }
 608
 609 static inline uint16_t
 610 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 611 {
 612         struct i40e_rx_queue *rxq = (struct i40e_rx_queue *)rx_queue;
 613         uint16_t nb_rx = 0;
 614
 615         if (!nb_pkts)
 616                 return 0;
 617
 618         if (rxq->rx_nb_avail)
 619                 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
 620
 621         nb_rx = (uint16_t)i40e_rx_scan_hw_ring(rxq);
 622         rxq->rx_next_avail = 0;
 623         rxq->rx_nb_avail = nb_rx;
 624         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
 625
 626         if (rxq->rx_tail > rxq->rx_free_trigger) {
 627                 if (i40e_rx_alloc_bufs(rxq) != 0) {
 628                         uint16_t i, j;
 629
 630                         PMD_RX_LOG(DEBUG, "Rx mbuf alloc failed for "
 631                                    "port_id=%u, queue_id=%u",
 632                                    rxq->port_id, rxq->queue_id);
 633                         rxq->rx_nb_avail = 0;
 634                         rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
 635                         for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
 636                                 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
 637
 638                         return 0;
 639                 }
 640         }
 641
 642         if (rxq->rx_tail >= rxq->nb_rx_desc)
 643                 rxq->rx_tail = 0;
 644
 645         if (rxq->rx_nb_avail)
 646                 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
 647
 648         return 0;
 649 }
 650
 651 static uint16_t
 652 i40e_recv_pkts_bulk_alloc(void *rx_queue,
 653                           struct rte_mbuf **rx_pkts,
 654                           uint16_t nb_pkts)
 655 {
 656         uint16_t nb_rx = 0, n, count;
 657
 658         if (unlikely(nb_pkts == 0))
 659                 return 0;
 660
 661         if (likely(nb_pkts <= RTE_PMD_I40E_RX_MAX_BURST))
 662                 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
 663
 664         while (nb_pkts) {
 665                 n = RTE_MIN(nb_pkts, RTE_PMD_I40E_RX_MAX_BURST);
 666                 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
 667                 nb_rx = (uint16_t)(nb_rx + count);
 668                 nb_pkts = (uint16_t)(nb_pkts - count);
 669                 if (count < n)
 670                         break;
 671         }
 672
 673         return nb_rx;
 674 }
 675 #else
 676 static uint16_t
 677 i40e_recv_pkts_bulk_alloc(void __rte_unused *rx_queue,
 678                           struct rte_mbuf __rte_unused **rx_pkts,
 679                           uint16_t __rte_unused nb_pkts)
 680 {
 681         return 0;
 682 }
 683 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
 684
 685 uint16_t
 686 i40e_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 687 {
 688         struct i40e_rx_queue *rxq;
 689         volatile union i40e_rx_desc *rx_ring;
 690         volatile union i40e_rx_desc *rxdp;
 691         union i40e_rx_desc rxd;
 692         struct i40e_rx_entry *sw_ring;
 693         struct i40e_rx_entry *rxe;
 694         struct rte_mbuf *rxm;
 695         struct rte_mbuf *nmb;
 696         uint16_t nb_rx;
 697         uint32_t rx_status;
 698         uint64_t qword1;
 699         uint16_t rx_packet_len;
 700         uint16_t rx_id, nb_hold;
 701         uint64_t dma_addr;
 702         uint64_t pkt_flags;
 703
 704         nb_rx = 0;
 705         nb_hold = 0;
 706         rxq = rx_queue;
 707         rx_id = rxq->rx_tail;
 708         rx_ring = rxq->rx_ring;
 709         sw_ring = rxq->sw_ring;
 710
 711         while (nb_rx < nb_pkts) {
 712                 rxdp = &rx_ring[rx_id];
 713                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 714                 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
 715                                 >> I40E_RXD_QW1_STATUS_SHIFT;
 716
 717                 /* Check the DD bit first */
 718                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 719                         break;
 720
 721                 nmb = rte_mbuf_raw_alloc(rxq->mp);
 722                 if (unlikely(!nmb))
 723                         break;
 724                 rxd = *rxdp;
 725
 726                 nb_hold++;
 727                 rxe = &sw_ring[rx_id];
 728                 rx_id++;
 729                 if (unlikely(rx_id == rxq->nb_rx_desc))
 730                         rx_id = 0;
 731
 732                 /* Prefetch next mbuf */
 733                 rte_prefetch0(sw_ring[rx_id].mbuf);
 734
 735                 /**
 736                  * When next RX descriptor is on a cache line boundary,
 737                  * prefetch the next 4 RX descriptors and next 8 pointers
 738                  * to mbufs.
 739                  */
 740                 if ((rx_id & 0x3) == 0) {
 741                         rte_prefetch0(&rx_ring[rx_id]);
 742                         rte_prefetch0(&sw_ring[rx_id]);
 743                 }
 744                 rxm = rxe->mbuf;
 745                 rxe->mbuf = nmb;
 746                 dma_addr =
 747                         rte_cpu_to_le_64(rte_mbuf_data_dma_addr_default(nmb));
 748                 rxdp->read.hdr_addr = 0;
 749                 rxdp->read.pkt_addr = dma_addr;
 750
 751                 rx_packet_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 752                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
 753
 754                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
 755                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
 756                 rxm->nb_segs = 1;
 757                 rxm->next = NULL;
 758                 rxm->pkt_len = rx_packet_len;
 759                 rxm->data_len = rx_packet_len;
 760                 rxm->port = rxq->port_id;
 761                 rxm->ol_flags = 0;
 762                 i40e_rxd_to_vlan_tci(rxm, &rxd);
 763                 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
 764                 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
 765                 rxm->packet_type =
 766                         i40e_rxd_pkt_type_mapping((uint8_t)((qword1 &
 767                         I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT));
 768                 if (pkt_flags & PKT_RX_RSS_HASH)
 769                         rxm->hash.rss =
 770                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
 771                 if (pkt_flags & PKT_RX_FDIR)
 772                         pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
 773
 774 #ifdef RTE_LIBRTE_IEEE1588
 775                 pkt_flags |= i40e_get_iee15888_flags(rxm, qword1);
 776 #endif
 777                 rxm->ol_flags |= pkt_flags;
 778
 779                 rx_pkts[nb_rx++] = rxm;
 780         }
 781         rxq->rx_tail = rx_id;
 782
 783         /**
 784          * If the number of free RX descriptors is greater than the RX free
 785          * threshold of the queue, advance the receive tail register of queue.
 786          * Update that register with the value of the last processed RX
 787          * descriptor minus 1.
 788          */
 789         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
 790         if (nb_hold > rxq->rx_free_thresh) {
 791                 rx_id = (uint16_t) ((rx_id == 0) ?
 792                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
 793                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
 794                 nb_hold = 0;
 795         }
 796         rxq->nb_rx_hold = nb_hold;
 797
 798         return nb_rx;
 799 }
 800
 801 uint16_t
 802 i40e_recv_scattered_pkts(void *rx_queue,
 803                          struct rte_mbuf **rx_pkts,
 804                          uint16_t nb_pkts)
 805 {
 806         struct i40e_rx_queue *rxq = rx_queue;
 807         volatile union i40e_rx_desc *rx_ring = rxq->rx_ring;
 808         volatile union i40e_rx_desc *rxdp;
 809         union i40e_rx_desc rxd;
 810         struct i40e_rx_entry *sw_ring = rxq->sw_ring;
 811         struct i40e_rx_entry *rxe;
 812         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
 813         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
 814         struct rte_mbuf *nmb, *rxm;
 815         uint16_t rx_id = rxq->rx_tail;
 816         uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
 817         uint32_t rx_status;
 818         uint64_t qword1;
 819         uint64_t dma_addr;
 820         uint64_t pkt_flags;
 821
 822         while (nb_rx < nb_pkts) {
 823                 rxdp = &rx_ring[rx_id];
 824                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 825                 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 826                                         I40E_RXD_QW1_STATUS_SHIFT;
 827
 828                 /* Check the DD bit */
 829                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 830                         break;
 831
 832                 nmb = rte_mbuf_raw_alloc(rxq->mp);
 833                 if (unlikely(!nmb))
 834                         break;
 835                 rxd = *rxdp;
 836                 nb_hold++;
 837                 rxe = &sw_ring[rx_id];
 838                 rx_id++;
 839                 if (rx_id == rxq->nb_rx_desc)
 840                         rx_id = 0;
 841
 842                 /* Prefetch next mbuf */
 843                 rte_prefetch0(sw_ring[rx_id].mbuf);
 844
 845                 /**
 846                  * When next RX descriptor is on a cache line boundary,
 847                  * prefetch the next 4 RX descriptors and next 8 pointers
 848                  * to mbufs.
 849                  */
 850                 if ((rx_id & 0x3) == 0) {
 851                         rte_prefetch0(&rx_ring[rx_id]);
 852                         rte_prefetch0(&sw_ring[rx_id]);
 853                 }
 854
 855                 rxm = rxe->mbuf;
 856                 rxe->mbuf = nmb;
 857                 dma_addr =
 858                         rte_cpu_to_le_64(rte_mbuf_data_dma_addr_default(nmb));
 859
 860                 /* Set data buffer address and data length of the mbuf */
 861                 rxdp->read.hdr_addr = 0;
 862                 rxdp->read.pkt_addr = dma_addr;
 863                 rx_packet_len = (qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 864                                         I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
 865                 rxm->data_len = rx_packet_len;
 866                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
 867
 868                 /**
 869                  * If this is the first buffer of the received packet, set the
 870                  * pointer to the first mbuf of the packet and initialize its
 871                  * context. Otherwise, update the total length and the number
 872                  * of segments of the current scattered packet, and update the
 873                  * pointer to the last mbuf of the current packet.
 874                  */
 875                 if (!first_seg) {
 876                         first_seg = rxm;
 877                         first_seg->nb_segs = 1;
 878                         first_seg->pkt_len = rx_packet_len;
 879                 } else {
 880                         first_seg->pkt_len =
 881                                 (uint16_t)(first_seg->pkt_len +
 882                                                 rx_packet_len);
 883                         first_seg->nb_segs++;
 884                         last_seg->next = rxm;
 885                 }
 886
 887                 /**
 888                  * If this is not the last buffer of the received packet,
 889                  * update the pointer to the last mbuf of the current scattered
 890                  * packet and continue to parse the RX ring.
 891                  */
 892                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT))) {
 893                         last_seg = rxm;
 894                         continue;
 895                 }
 896
 897                 /**
 898                  * This is the last buffer of the received packet. If the CRC
 899                  * is not stripped by the hardware:
 900                  *  - Subtract the CRC length from the total packet length.
 901                  *  - If the last buffer only contains the whole CRC or a part
 902                  *  of it, free the mbuf associated to the last buffer. If part
 903                  *  of the CRC is also contained in the previous mbuf, subtract
 904                  *  the length of that CRC part from the data length of the
 905                  *  previous mbuf.
 906                  */
 907                 rxm->next = NULL;
 908                 if (unlikely(rxq->crc_len > 0)) {
 909                         first_seg->pkt_len -= ETHER_CRC_LEN;
 910                         if (rx_packet_len <= ETHER_CRC_LEN) {
 911                                 rte_pktmbuf_free_seg(rxm);
 912                                 first_seg->nb_segs--;
 913                                 last_seg->data_len =
 914                                         (uint16_t)(last_seg->data_len -
 915                                         (ETHER_CRC_LEN - rx_packet_len));
 916                                 last_seg->next = NULL;
 917                         } else
 918                                 rxm->data_len = (uint16_t)(rx_packet_len -
 919                                                                 ETHER_CRC_LEN);
 920                 }
 921
 922                 first_seg->port = rxq->port_id;
 923                 first_seg->ol_flags = 0;
 924                 i40e_rxd_to_vlan_tci(first_seg, &rxd);
 925                 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
 926                 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
 927                 first_seg->packet_type =
 928                         i40e_rxd_pkt_type_mapping((uint8_t)((qword1 &
 929                         I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT));
 930                 if (pkt_flags & PKT_RX_RSS_HASH)
 931                         first_seg->hash.rss =
 932                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
 933                 if (pkt_flags & PKT_RX_FDIR)
 934                         pkt_flags |= i40e_rxd_build_fdir(&rxd, first_seg);
 935
 936 #ifdef RTE_LIBRTE_IEEE1588
 937                 pkt_flags |= i40e_get_iee15888_flags(first_seg, qword1);
 938 #endif
 939                 first_seg->ol_flags |= pkt_flags;
 940
 941                 /* Prefetch data of first segment, if configured to do so. */
 942                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
 943                         first_seg->data_off));
 944                 rx_pkts[nb_rx++] = first_seg;
 945                 first_seg = NULL;
 946         }
 947
 948         /* Record index of the next RX descriptor to probe. */
 949         rxq->rx_tail = rx_id;
 950         rxq->pkt_first_seg = first_seg;
 951         rxq->pkt_last_seg = last_seg;
 952
 953         /**
 954          * If the number of free RX descriptors is greater than the RX free
 955          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
 956          * register. Update the RDT with the value of the last processed RX
 957          * descriptor minus 1, to guarantee that the RDT register is never
 958          * equal to the RDH register, which creates a "full" ring situtation
 959          * from the hardware point of view.
 960          */
 961         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
 962         if (nb_hold > rxq->rx_free_thresh) {
 963                 rx_id = (uint16_t)(rx_id == 0 ?
 964                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
 965                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
 966                 nb_hold = 0;
 967         }
 968         rxq->nb_rx_hold = nb_hold;
 969
 970         return nb_rx;
 971 }
 972
 973 /* Check if the context descriptor is needed for TX offloading */
 974 static inline uint16_t
 975 i40e_calc_context_desc(uint64_t flags)
 976 {
 977         static uint64_t mask = PKT_TX_OUTER_IP_CKSUM |
 978                 PKT_TX_TCP_SEG |
 979                 PKT_TX_QINQ_PKT |
 980                 PKT_TX_TUNNEL_MASK;
 981
 982 #ifdef RTE_LIBRTE_IEEE1588
 983         mask |= PKT_TX_IEEE1588_TMST;
 984 #endif
 985
 986         return (flags & mask) ? 1 : 0;
 987 }
 988
 989 /* set i40e TSO context descriptor */
 990 static inline uint64_t
 991 i40e_set_tso_ctx(struct rte_mbuf *mbuf, union i40e_tx_offload tx_offload)
 992 {
 993         uint64_t ctx_desc = 0;
 994         uint32_t cd_cmd, hdr_len, cd_tso_len;
 995
 996         if (!tx_offload.l4_len) {
 997                 PMD_DRV_LOG(DEBUG, "L4 length set to 0");
 998                 return ctx_desc;
 999         }
1000
1001         /**
1002          * in case of non tunneling packet, the outer_l2_len and
1003          * outer_l3_len must be 0.
1004          */
1005         hdr_len = tx_offload.outer_l2_len +
1006                 tx_offload.outer_l3_len +
1007                 tx_offload.l2_len +
1008                 tx_offload.l3_len +
1009                 tx_offload.l4_len;
1010
1011         cd_cmd = I40E_TX_CTX_DESC_TSO;
1012         cd_tso_len = mbuf->pkt_len - hdr_len;
1013         ctx_desc |= ((uint64_t)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
1014                 ((uint64_t)cd_tso_len <<
1015                  I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1016                 ((uint64_t)mbuf->tso_segsz <<
1017                  I40E_TXD_CTX_QW1_MSS_SHIFT);
1018
1019         return ctx_desc;
1020 }
1021
1022 uint16_t
1023 i40e_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1024 {
1025         struct i40e_tx_queue *txq;
1026         struct i40e_tx_entry *sw_ring;
1027         struct i40e_tx_entry *txe, *txn;
1028         volatile struct i40e_tx_desc *txd;
1029         volatile struct i40e_tx_desc *txr;
1030         struct rte_mbuf *tx_pkt;
1031         struct rte_mbuf *m_seg;
1032         uint32_t cd_tunneling_params;
1033         uint16_t tx_id;
1034         uint16_t nb_tx;
1035         uint32_t td_cmd;
1036         uint32_t td_offset;
1037         uint32_t td_tag;
1038         uint64_t ol_flags;
1039         uint16_t nb_used;
1040         uint16_t nb_ctx;
1041         uint16_t tx_last;
1042         uint16_t slen;
1043         uint64_t buf_dma_addr;
1044         union i40e_tx_offload tx_offload = {0};
1045
1046         txq = tx_queue;
1047         sw_ring = txq->sw_ring;
1048         txr = txq->tx_ring;
1049         tx_id = txq->tx_tail;
1050         txe = &sw_ring[tx_id];
1051
1052         /* Check if the descriptor ring needs to be cleaned. */
1053         if (txq->nb_tx_free < txq->tx_free_thresh)
1054                 i40e_xmit_cleanup(txq);
1055
1056         for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1057                 td_cmd = 0;
1058                 td_tag = 0;
1059                 td_offset = 0;
1060
1061                 tx_pkt = *tx_pkts++;
1062                 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
1063
1064                 ol_flags = tx_pkt->ol_flags;
1065                 tx_offload.l2_len = tx_pkt->l2_len;
1066                 tx_offload.l3_len = tx_pkt->l3_len;
1067                 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
1068                 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
1069                 tx_offload.l4_len = tx_pkt->l4_len;
1070                 tx_offload.tso_segsz = tx_pkt->tso_segsz;
1071
1072                 /* Calculate the number of context descriptors needed. */
1073                 nb_ctx = i40e_calc_context_desc(ol_flags);
1074
1075                 /**
1076                  * The number of descriptors that must be allocated for
1077                  * a packet equals to the number of the segments of that
1078                  * packet plus 1 context descriptor if needed.
1079                  */
1080                 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
1081                 tx_last = (uint16_t)(tx_id + nb_used - 1);
1082
1083                 /* Circular ring */
1084                 if (tx_last >= txq->nb_tx_desc)
1085                         tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
1086
1087                 if (nb_used > txq->nb_tx_free) {
1088                         if (i40e_xmit_cleanup(txq) != 0) {
1089                                 if (nb_tx == 0)
1090                                         return 0;
1091                                 goto end_of_tx;
1092                         }
1093                         if (unlikely(nb_used > txq->tx_rs_thresh)) {
1094                                 while (nb_used > txq->nb_tx_free) {
1095                                         if (i40e_xmit_cleanup(txq) != 0) {
1096                                                 if (nb_tx == 0)
1097                                                         return 0;
1098                                                 goto end_of_tx;
1099                                         }
1100                                 }
1101                         }
1102                 }
1103
1104                 /* Descriptor based VLAN insertion */
1105                 if (ol_flags & (PKT_TX_VLAN_PKT | PKT_TX_QINQ_PKT)) {
1106                         td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1107                         td_tag = tx_pkt->vlan_tci;
1108                 }
1109
1110                 /* Always enable CRC offload insertion */
1111                 td_cmd |= I40E_TX_DESC_CMD_ICRC;
1112
1113                 /* Fill in tunneling parameters if necessary */
1114                 cd_tunneling_params = 0;
1115                 if (ol_flags & PKT_TX_TUNNEL_MASK)
1116                         i40e_parse_tunneling_params(ol_flags, tx_offload,
1117                                                     &cd_tunneling_params);
1118                 /* Enable checksum offloading */
1119                 if (ol_flags & I40E_TX_CKSUM_OFFLOAD_MASK)
1120                         i40e_txd_enable_checksum(ol_flags, &td_cmd,
1121                                                  &td_offset, tx_offload);
1122
1123                 if (nb_ctx) {
1124                         /* Setup TX context descriptor if required */
1125                         volatile struct i40e_tx_context_desc *ctx_txd =
1126                                 (volatile struct i40e_tx_context_desc *)\
1127                                                         &txr[tx_id];
1128                         uint16_t cd_l2tag2 = 0;
1129                         uint64_t cd_type_cmd_tso_mss =
1130                                 I40E_TX_DESC_DTYPE_CONTEXT;
1131
1132                         txn = &sw_ring[txe->next_id];
1133                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
1134                         if (txe->mbuf != NULL) {
1135                                 rte_pktmbuf_free_seg(txe->mbuf);
1136                                 txe->mbuf = NULL;
1137                         }
1138
1139                         /* TSO enabled means no timestamp */
1140                         if (ol_flags & PKT_TX_TCP_SEG)
1141                                 cd_type_cmd_tso_mss |=
1142                                         i40e_set_tso_ctx(tx_pkt, tx_offload);
1143                         else {
1144 #ifdef RTE_LIBRTE_IEEE1588
1145                                 if (ol_flags & PKT_TX_IEEE1588_TMST)
1146                                         cd_type_cmd_tso_mss |=
1147                                                 ((uint64_t)I40E_TX_CTX_DESC_TSYN <<
1148                                                  I40E_TXD_CTX_QW1_CMD_SHIFT);
1149 #endif
1150                         }
1151
1152                         ctx_txd->tunneling_params =
1153                                 rte_cpu_to_le_32(cd_tunneling_params);
1154                         if (ol_flags & PKT_TX_QINQ_PKT) {
1155                                 cd_l2tag2 = tx_pkt->vlan_tci_outer;
1156                                 cd_type_cmd_tso_mss |=
1157                                         ((uint64_t)I40E_TX_CTX_DESC_IL2TAG2 <<
1158                                                 I40E_TXD_CTX_QW1_CMD_SHIFT);
1159                         }
1160                         ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
1161                         ctx_txd->type_cmd_tso_mss =
1162                                 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
1163
1164                         PMD_TX_LOG(DEBUG, "mbuf: %p, TCD[%u]:\n"
1165                                 "tunneling_params: %#x;\n"
1166                                 "l2tag2: %#hx;\n"
1167                                 "rsvd: %#hx;\n"
1168                                 "type_cmd_tso_mss: %#"PRIx64";\n",
1169                                 tx_pkt, tx_id,
1170                                 ctx_txd->tunneling_params,
1171                                 ctx_txd->l2tag2,
1172                                 ctx_txd->rsvd,
1173                                 ctx_txd->type_cmd_tso_mss);
1174
1175                         txe->last_id = tx_last;
1176                         tx_id = txe->next_id;
1177                         txe = txn;
1178                 }
1179
1180                 m_seg = tx_pkt;
1181                 do {
1182                         txd = &txr[tx_id];
1183                         txn = &sw_ring[txe->next_id];
1184
1185                         if (txe->mbuf)
1186                                 rte_pktmbuf_free_seg(txe->mbuf);
1187                         txe->mbuf = m_seg;
1188
1189                         /* Setup TX Descriptor */
1190                         slen = m_seg->data_len;
1191                         buf_dma_addr = rte_mbuf_data_dma_addr(m_seg);
1192
1193                         PMD_TX_LOG(DEBUG, "mbuf: %p, TDD[%u]:\n"
1194                                 "buf_dma_addr: %#"PRIx64";\n"
1195                                 "td_cmd: %#x;\n"
1196                                 "td_offset: %#x;\n"
1197                                 "td_len: %u;\n"
1198                                 "td_tag: %#x;\n",
1199                                 tx_pkt, tx_id, buf_dma_addr,
1200                                 td_cmd, td_offset, slen, td_tag);
1201
1202                         txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
1203                         txd->cmd_type_offset_bsz = i40e_build_ctob(td_cmd,
1204                                                 td_offset, slen, td_tag);
1205                         txe->last_id = tx_last;
1206                         tx_id = txe->next_id;
1207                         txe = txn;
1208                         m_seg = m_seg->next;
1209                 } while (m_seg != NULL);
1210
1211                 /* The last packet data descriptor needs End Of Packet (EOP) */
1212                 td_cmd |= I40E_TX_DESC_CMD_EOP;
1213                 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
1214                 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
1215
1216                 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
1217                         PMD_TX_FREE_LOG(DEBUG,
1218                                         "Setting RS bit on TXD id="
1219                                         "%4u (port=%d queue=%d)",
1220                                         tx_last, txq->port_id, txq->queue_id);
1221
1222                         td_cmd |= I40E_TX_DESC_CMD_RS;
1223
1224                         /* Update txq RS bit counters */
1225                         txq->nb_tx_used = 0;
1226                 }
1227
1228                 txd->cmd_type_offset_bsz |=
1229                         rte_cpu_to_le_64(((uint64_t)td_cmd) <<
1230                                         I40E_TXD_QW1_CMD_SHIFT);
1231         }
1232
1233 end_of_tx:
1234         rte_wmb();
1235
1236         PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
1237                    (unsigned) txq->port_id, (unsigned) txq->queue_id,
1238                    (unsigned) tx_id, (unsigned) nb_tx);
1239
1240         I40E_PCI_REG_WRITE_RELAXED(txq->qtx_tail, tx_id);
1241         txq->tx_tail = tx_id;
1242
1243         return nb_tx;
1244 }
1245
1246 static inline int __attribute__((always_inline))
1247 i40e_tx_free_bufs(struct i40e_tx_queue *txq)
1248 {
1249         struct i40e_tx_entry *txep;
1250         uint16_t i;
1251
1252         if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
1253                         rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
1254                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
1255                 return 0;
1256
1257         txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
1258
1259         for (i = 0; i < txq->tx_rs_thresh; i++)
1260                 rte_prefetch0((txep + i)->mbuf);
1261
1262         if (txq->txq_flags & (uint32_t)ETH_TXQ_FLAGS_NOREFCOUNT) {
1263                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1264                         rte_mempool_put(txep->mbuf->pool, txep->mbuf);
1265                         txep->mbuf = NULL;
1266                 }
1267         } else {
1268                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1269                         rte_pktmbuf_free_seg(txep->mbuf);
1270                         txep->mbuf = NULL;
1271                 }
1272         }
1273
1274         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
1275         txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
1276         if (txq->tx_next_dd >= txq->nb_tx_desc)
1277                 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1278
1279         return txq->tx_rs_thresh;
1280 }
1281
1282 /* Populate 4 descriptors with data from 4 mbufs */
1283 static inline void
1284 tx4(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1285 {
1286         uint64_t dma_addr;
1287         uint32_t i;
1288
1289         for (i = 0; i < 4; i++, txdp++, pkts++) {
1290                 dma_addr = rte_mbuf_data_dma_addr(*pkts);
1291                 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1292                 txdp->cmd_type_offset_bsz =
1293                         i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1294                                         (*pkts)->data_len, 0);
1295         }
1296 }
1297
1298 /* Populate 1 descriptor with data from 1 mbuf */
1299 static inline void
1300 tx1(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1301 {
1302         uint64_t dma_addr;
1303
1304         dma_addr = rte_mbuf_data_dma_addr(*pkts);
1305         txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1306         txdp->cmd_type_offset_bsz =
1307                 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1308                                 (*pkts)->data_len, 0);
1309 }
1310
1311 /* Fill hardware descriptor ring with mbuf data */
1312 static inline void
1313 i40e_tx_fill_hw_ring(struct i40e_tx_queue *txq,
1314                      struct rte_mbuf **pkts,
1315                      uint16_t nb_pkts)
1316 {
1317         volatile struct i40e_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
1318         struct i40e_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
1319         const int N_PER_LOOP = 4;
1320         const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
1321         int mainpart, leftover;
1322         int i, j;
1323
1324         mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
1325         leftover = (nb_pkts & ((uint32_t)  N_PER_LOOP_MASK));
1326         for (i = 0; i < mainpart; i += N_PER_LOOP) {
1327                 for (j = 0; j < N_PER_LOOP; ++j) {
1328                         (txep + i + j)->mbuf = *(pkts + i + j);
1329                 }
1330                 tx4(txdp + i, pkts + i);
1331         }
1332         if (unlikely(leftover > 0)) {
1333                 for (i = 0; i < leftover; ++i) {
1334                         (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
1335                         tx1(txdp + mainpart + i, pkts + mainpart + i);
1336                 }
1337         }
1338 }
1339
1340 static inline uint16_t
1341 tx_xmit_pkts(struct i40e_tx_queue *txq,
1342              struct rte_mbuf **tx_pkts,
1343              uint16_t nb_pkts)
1344 {
1345         volatile struct i40e_tx_desc *txr = txq->tx_ring;
1346         uint16_t n = 0;
1347
1348         /**
1349          * Begin scanning the H/W ring for done descriptors when the number
1350          * of available descriptors drops below tx_free_thresh. For each done
1351          * descriptor, free the associated buffer.
1352          */
1353         if (txq->nb_tx_free < txq->tx_free_thresh)
1354                 i40e_tx_free_bufs(txq);
1355
1356         /* Use available descriptor only */
1357         nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
1358         if (unlikely(!nb_pkts))
1359                 return 0;
1360
1361         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
1362         if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
1363                 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
1364                 i40e_tx_fill_hw_ring(txq, tx_pkts, n);
1365                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1366                         rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1367                                                 I40E_TXD_QW1_CMD_SHIFT);
1368                 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1369                 txq->tx_tail = 0;
1370         }
1371
1372         /* Fill hardware descriptor ring with mbuf data */
1373         i40e_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
1374         txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
1375
1376         /* Determin if RS bit needs to be set */
1377         if (txq->tx_tail > txq->tx_next_rs) {
1378                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1379                         rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1380                                                 I40E_TXD_QW1_CMD_SHIFT);
1381                 txq->tx_next_rs =
1382                         (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
1383                 if (txq->tx_next_rs >= txq->nb_tx_desc)
1384                         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1385         }
1386
1387         if (txq->tx_tail >= txq->nb_tx_desc)
1388                 txq->tx_tail = 0;
1389
1390         /* Update the tx tail register */
1391         rte_wmb();
1392         I40E_PCI_REG_WRITE_RELAXED(txq->qtx_tail, txq->tx_tail);
1393
1394         return nb_pkts;
1395 }
1396
1397 static uint16_t
1398 i40e_xmit_pkts_simple(void *tx_queue,
1399                       struct rte_mbuf **tx_pkts,
1400                       uint16_t nb_pkts)
1401 {
1402         uint16_t nb_tx = 0;
1403
1404         if (likely(nb_pkts <= I40E_TX_MAX_BURST))
1405                 return tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1406                                                 tx_pkts, nb_pkts);
1407
1408         while (nb_pkts) {
1409                 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
1410                                                 I40E_TX_MAX_BURST);
1411
1412                 ret = tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1413                                                 &tx_pkts[nb_tx], num);
1414                 nb_tx = (uint16_t)(nb_tx + ret);
1415                 nb_pkts = (uint16_t)(nb_pkts - ret);
1416                 if (ret < num)
1417                         break;
1418         }
1419
1420         return nb_tx;
1421 }
1422
1423 static uint16_t
1424 i40e_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
1425                    uint16_t nb_pkts)
1426 {
1427         uint16_t nb_tx = 0;
1428         struct i40e_tx_queue *txq = (struct i40e_tx_queue *)tx_queue;
1429
1430         while (nb_pkts) {
1431                 uint16_t ret, num;
1432
1433                 num = (uint16_t)RTE_MIN(nb_pkts, txq->tx_rs_thresh);
1434                 ret = i40e_xmit_fixed_burst_vec(tx_queue, &tx_pkts[nb_tx],
1435                                                 num);
1436                 nb_tx += ret;
1437                 nb_pkts -= ret;
1438                 if (ret < num)
1439                         break;
1440         }
1441
1442         return nb_tx;
1443 }
1444
1445 /*********************************************************************
1446  *
1447  *  TX prep functions
1448  *
1449  **********************************************************************/
1450 uint16_t
1451 i40e_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
1452                 uint16_t nb_pkts)
1453 {
1454         int i, ret;
1455         uint64_t ol_flags;
1456         struct rte_mbuf *m;
1457
1458         for (i = 0; i < nb_pkts; i++) {
1459                 m = tx_pkts[i];
1460                 ol_flags = m->ol_flags;
1461
1462                 /**
1463                  * m->nb_segs is uint8_t, so nb_segs is always less than
1464                  * I40E_TX_MAX_SEG.
1465                  * We check only a condition for nb_segs > I40E_TX_MAX_MTU_SEG.
1466                  */
1467                 if (!(ol_flags & PKT_TX_TCP_SEG)) {
1468                         if (m->nb_segs > I40E_TX_MAX_MTU_SEG) {
1469                                 rte_errno = -EINVAL;
1470                                 return i;
1471                         }
1472                 } else if ((m->tso_segsz < I40E_MIN_TSO_MSS) ||
1473                                 (m->tso_segsz > I40E_MAX_TSO_MSS)) {
1474                         /* MSS outside the range (256B - 9674B) are considered
1475                          * malicious
1476                          */
1477                         rte_errno = -EINVAL;
1478                         return i;
1479                 }
1480
1481                 if (ol_flags & I40E_TX_OFFLOAD_NOTSUP_MASK) {
1482                         rte_errno = -ENOTSUP;
1483                         return i;
1484                 }
1485
1486 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
1487                 ret = rte_validate_tx_offload(m);
1488                 if (ret != 0) {
1489                         rte_errno = ret;
1490                         return i;
1491                 }
1492 #endif
1493                 ret = rte_net_intel_cksum_prepare(m);
1494                 if (ret != 0) {
1495                         rte_errno = ret;
1496                         return i;
1497                 }
1498         }
1499         return i;
1500 }
1501
1502 /*
1503  * Find the VSI the queue belongs to. 'queue_idx' is the queue index
1504  * application used, which assume having sequential ones. But from driver's
1505  * perspective, it's different. For example, q0 belongs to FDIR VSI, q1-q64
1506  * to MAIN VSI, , q65-96 to SRIOV VSIs, q97-128 to VMDQ VSIs. For application
1507  * running on host, q1-64 and q97-128 can be used, total 96 queues. They can
1508  * use queue_idx from 0 to 95 to access queues, while real queue would be
1509  * different. This function will do a queue mapping to find VSI the queue
1510  * belongs to.
1511  */
1512 static struct i40e_vsi*
1513 i40e_pf_get_vsi_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1514 {
1515         /* the queue in MAIN VSI range */
1516         if (queue_idx < pf->main_vsi->nb_qps)
1517                 return pf->main_vsi;
1518
1519         queue_idx -= pf->main_vsi->nb_qps;
1520
1521         /* queue_idx is greater than VMDQ VSIs range */
1522         if (queue_idx > pf->nb_cfg_vmdq_vsi * pf->vmdq_nb_qps - 1) {
1523                 PMD_INIT_LOG(ERR, "queue_idx out of range. VMDQ configured?");
1524                 return NULL;
1525         }
1526
1527         return pf->vmdq[queue_idx / pf->vmdq_nb_qps].vsi;
1528 }
1529
1530 static uint16_t
1531 i40e_get_queue_offset_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1532 {
1533         /* the queue in MAIN VSI range */
1534         if (queue_idx < pf->main_vsi->nb_qps)
1535                 return queue_idx;
1536
1537         /* It's VMDQ queues */
1538         queue_idx -= pf->main_vsi->nb_qps;
1539
1540         if (pf->nb_cfg_vmdq_vsi)
1541                 return queue_idx % pf->vmdq_nb_qps;
1542         else {
1543                 PMD_INIT_LOG(ERR, "Fail to get queue offset");
1544                 return (uint16_t)(-1);
1545         }
1546 }
1547
1548 int
1549 i40e_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1550 {
1551         struct i40e_rx_queue *rxq;
1552         int err = -1;
1553         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1554
1555         PMD_INIT_FUNC_TRACE();
1556
1557         if (rx_queue_id < dev->data->nb_rx_queues) {
1558                 rxq = dev->data->rx_queues[rx_queue_id];
1559
1560                 err = i40e_alloc_rx_queue_mbufs(rxq);
1561                 if (err) {
1562                         PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1563                         return err;
1564                 }
1565
1566                 rte_wmb();
1567
1568                 /* Init the RX tail regieter. */
1569                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1570
1571                 err = i40e_switch_rx_queue(hw, rxq->reg_idx, TRUE);
1572
1573                 if (err) {
1574                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1575                                     rx_queue_id);
1576
1577                         i40e_rx_queue_release_mbufs(rxq);
1578                         i40e_reset_rx_queue(rxq);
1579                 } else
1580                         dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1581         }
1582
1583         return err;
1584 }
1585
1586 int
1587 i40e_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1588 {
1589         struct i40e_rx_queue *rxq;
1590         int err;
1591         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1592
1593         if (rx_queue_id < dev->data->nb_rx_queues) {
1594                 rxq = dev->data->rx_queues[rx_queue_id];
1595
1596                 /*
1597                 * rx_queue_id is queue id aplication refers to, while
1598                 * rxq->reg_idx is the real queue index.
1599                 */
1600                 err = i40e_switch_rx_queue(hw, rxq->reg_idx, FALSE);
1601
1602                 if (err) {
1603                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1604                                     rx_queue_id);
1605                         return err;
1606                 }
1607                 i40e_rx_queue_release_mbufs(rxq);
1608                 i40e_reset_rx_queue(rxq);
1609                 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1610         }
1611
1612         return 0;
1613 }
1614
1615 int
1616 i40e_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1617 {
1618         int err = -1;
1619         struct i40e_tx_queue *txq;
1620         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1621
1622         PMD_INIT_FUNC_TRACE();
1623
1624         if (tx_queue_id < dev->data->nb_tx_queues) {
1625                 txq = dev->data->tx_queues[tx_queue_id];
1626
1627                 /*
1628                 * tx_queue_id is queue id aplication refers to, while
1629                 * rxq->reg_idx is the real queue index.
1630                 */
1631                 err = i40e_switch_tx_queue(hw, txq->reg_idx, TRUE);
1632                 if (err)
1633                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1634                                     tx_queue_id);
1635                 else
1636                         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1637         }
1638
1639         return err;
1640 }
1641
1642 int
1643 i40e_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1644 {
1645         struct i40e_tx_queue *txq;
1646         int err;
1647         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1648
1649         if (tx_queue_id < dev->data->nb_tx_queues) {
1650                 txq = dev->data->tx_queues[tx_queue_id];
1651
1652                 /*
1653                 * tx_queue_id is queue id aplication refers to, while
1654                 * txq->reg_idx is the real queue index.
1655                 */
1656                 err = i40e_switch_tx_queue(hw, txq->reg_idx, FALSE);
1657
1658                 if (err) {
1659                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u of",
1660                                     tx_queue_id);
1661                         return err;
1662                 }
1663
1664                 i40e_tx_queue_release_mbufs(txq);
1665                 i40e_reset_tx_queue(txq);
1666                 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1667         }
1668
1669         return 0;
1670 }
1671
1672 const uint32_t *
1673 i40e_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1674 {
1675         static const uint32_t ptypes[] = {
1676                 /* refers to i40e_rxd_pkt_type_mapping() */
1677                 RTE_PTYPE_L2_ETHER,
1678                 RTE_PTYPE_L2_ETHER_TIMESYNC,
1679                 RTE_PTYPE_L2_ETHER_LLDP,
1680                 RTE_PTYPE_L2_ETHER_ARP,
1681                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1682                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
1683                 RTE_PTYPE_L4_FRAG,
1684                 RTE_PTYPE_L4_ICMP,
1685                 RTE_PTYPE_L4_NONFRAG,
1686                 RTE_PTYPE_L4_SCTP,
1687                 RTE_PTYPE_L4_TCP,
1688                 RTE_PTYPE_L4_UDP,
1689                 RTE_PTYPE_TUNNEL_GRENAT,
1690                 RTE_PTYPE_TUNNEL_IP,
1691                 RTE_PTYPE_INNER_L2_ETHER,
1692                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1693                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
1694                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
1695                 RTE_PTYPE_INNER_L4_FRAG,
1696                 RTE_PTYPE_INNER_L4_ICMP,
1697                 RTE_PTYPE_INNER_L4_NONFRAG,
1698                 RTE_PTYPE_INNER_L4_SCTP,
1699                 RTE_PTYPE_INNER_L4_TCP,
1700                 RTE_PTYPE_INNER_L4_UDP,
1701                 RTE_PTYPE_UNKNOWN
1702         };
1703
1704         if (dev->rx_pkt_burst == i40e_recv_pkts ||
1705 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1706             dev->rx_pkt_burst == i40e_recv_pkts_bulk_alloc ||
1707 #endif
1708             dev->rx_pkt_burst == i40e_recv_scattered_pkts ||
1709             dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
1710             dev->rx_pkt_burst == i40e_recv_pkts_vec)
1711                 return ptypes;
1712         return NULL;
1713 }
1714
1715 int
1716 i40e_dev_rx_queue_setup(struct rte_eth_dev *dev,
1717                         uint16_t queue_idx,
1718                         uint16_t nb_desc,
1719                         unsigned int socket_id,
1720                         const struct rte_eth_rxconf *rx_conf,
1721                         struct rte_mempool *mp)
1722 {
1723         struct i40e_vsi *vsi;
1724         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1725         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1726         struct i40e_adapter *ad =
1727                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1728         struct i40e_rx_queue *rxq;
1729         const struct rte_memzone *rz;
1730         uint32_t ring_size;
1731         uint16_t len, i;
1732         uint16_t base, bsf, tc_mapping;
1733         int use_def_burst_func = 1;
1734
1735         if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
1736                 struct i40e_vf *vf =
1737                         I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1738                 vsi = &vf->vsi;
1739         } else
1740                 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
1741
1742         if (vsi == NULL) {
1743                 PMD_DRV_LOG(ERR, "VSI not available or queue "
1744                             "index exceeds the maximum");
1745                 return I40E_ERR_PARAM;
1746         }
1747         if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
1748                         (nb_desc > I40E_MAX_RING_DESC) ||
1749                         (nb_desc < I40E_MIN_RING_DESC)) {
1750                 PMD_DRV_LOG(ERR, "Number (%u) of receive descriptors is "
1751                             "invalid", nb_desc);
1752                 return I40E_ERR_PARAM;
1753         }
1754
1755         /* Free memory if needed */
1756         if (dev->data->rx_queues[queue_idx]) {
1757                 i40e_dev_rx_queue_release(dev->data->rx_queues[queue_idx]);
1758                 dev->data->rx_queues[queue_idx] = NULL;
1759         }
1760
1761         /* Allocate the rx queue data structure */
1762         rxq = rte_zmalloc_socket("i40e rx queue",
1763                                  sizeof(struct i40e_rx_queue),
1764                                  RTE_CACHE_LINE_SIZE,
1765                                  socket_id);
1766         if (!rxq) {
1767                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
1768                             "rx queue data structure");
1769                 return -ENOMEM;
1770         }
1771         rxq->mp = mp;
1772         rxq->nb_rx_desc = nb_desc;
1773         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1774         rxq->queue_id = queue_idx;
1775         if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF)
1776                 rxq->reg_idx = queue_idx;
1777         else /* PF device */
1778                 rxq->reg_idx = vsi->base_queue +
1779                         i40e_get_queue_offset_by_qindex(pf, queue_idx);
1780
1781         rxq->port_id = dev->data->port_id;
1782         rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ?
1783                                                         0 : ETHER_CRC_LEN);
1784         rxq->drop_en = rx_conf->rx_drop_en;
1785         rxq->vsi = vsi;
1786         rxq->rx_deferred_start = rx_conf->rx_deferred_start;
1787
1788         /* Allocate the maximun number of RX ring hardware descriptor. */
1789         len = I40E_MAX_RING_DESC;
1790
1791 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1792         /**
1793          * Allocating a little more memory because vectorized/bulk_alloc Rx
1794          * functions doesn't check boundaries each time.
1795          */
1796         len += RTE_PMD_I40E_RX_MAX_BURST;
1797 #endif
1798
1799         ring_size = RTE_ALIGN(len * sizeof(union i40e_rx_desc),
1800                               I40E_DMA_MEM_ALIGN);
1801
1802         rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1803                               ring_size, I40E_RING_BASE_ALIGN, socket_id);
1804         if (!rz) {
1805                 i40e_dev_rx_queue_release(rxq);
1806                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX");
1807                 return -ENOMEM;
1808         }
1809
1810         /* Zero all the descriptors in the ring. */
1811         memset(rz->addr, 0, ring_size);
1812
1813         rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
1814         rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
1815
1816 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1817         len = (uint16_t)(nb_desc + RTE_PMD_I40E_RX_MAX_BURST);
1818 #else
1819         len = nb_desc;
1820 #endif
1821
1822         /* Allocate the software ring. */
1823         rxq->sw_ring =
1824                 rte_zmalloc_socket("i40e rx sw ring",
1825                                    sizeof(struct i40e_rx_entry) * len,
1826                                    RTE_CACHE_LINE_SIZE,
1827                                    socket_id);
1828         if (!rxq->sw_ring) {
1829                 i40e_dev_rx_queue_release(rxq);
1830                 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW ring");
1831                 return -ENOMEM;
1832         }
1833
1834         i40e_reset_rx_queue(rxq);
1835         rxq->q_set = TRUE;
1836         dev->data->rx_queues[queue_idx] = rxq;
1837
1838         use_def_burst_func = check_rx_burst_bulk_alloc_preconditions(rxq);
1839
1840         if (!use_def_burst_func) {
1841 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1842                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1843                              "satisfied. Rx Burst Bulk Alloc function will be "
1844                              "used on port=%d, queue=%d.",
1845                              rxq->port_id, rxq->queue_id);
1846 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
1847         } else {
1848                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1849                              "not satisfied, Scattered Rx is requested, "
1850                              "or RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC is "
1851                              "not enabled on port=%d, queue=%d.",
1852                              rxq->port_id, rxq->queue_id);
1853                 ad->rx_bulk_alloc_allowed = false;
1854         }
1855
1856         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1857                 if (!(vsi->enabled_tc & (1 << i)))
1858                         continue;
1859                 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
1860                 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
1861                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
1862                 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
1863                         I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
1864
1865                 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
1866                         rxq->dcb_tc = i;
1867         }
1868
1869         return 0;
1870 }
1871
1872 void
1873 i40e_dev_rx_queue_release(void *rxq)
1874 {
1875         struct i40e_rx_queue *q = (struct i40e_rx_queue *)rxq;
1876
1877         if (!q) {
1878                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
1879                 return;
1880         }
1881
1882         i40e_rx_queue_release_mbufs(q);
1883         rte_free(q->sw_ring);
1884         rte_free(q);
1885 }
1886
1887 uint32_t
1888 i40e_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1889 {
1890 #define I40E_RXQ_SCAN_INTERVAL 4
1891         volatile union i40e_rx_desc *rxdp;
1892         struct i40e_rx_queue *rxq;
1893         uint16_t desc = 0;
1894
1895         rxq = dev->data->rx_queues[rx_queue_id];
1896         rxdp = &(rxq->rx_ring[rxq->rx_tail]);
1897         while ((desc < rxq->nb_rx_desc) &&
1898                 ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1899                 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
1900                                 (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
1901                 /**
1902                  * Check the DD bit of a rx descriptor of each 4 in a group,
1903                  * to avoid checking too frequently and downgrading performance
1904                  * too much.
1905                  */
1906                 desc += I40E_RXQ_SCAN_INTERVAL;
1907                 rxdp += I40E_RXQ_SCAN_INTERVAL;
1908                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
1909                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
1910                                         desc - rxq->nb_rx_desc]);
1911         }
1912
1913         return desc;
1914 }
1915
1916 int
1917 i40e_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
1918 {
1919         volatile union i40e_rx_desc *rxdp;
1920         struct i40e_rx_queue *rxq = rx_queue;
1921         uint16_t desc;
1922         int ret;
1923
1924         if (unlikely(offset >= rxq->nb_rx_desc)) {
1925                 PMD_DRV_LOG(ERR, "Invalid RX descriptor id %u", offset);
1926                 return 0;
1927         }
1928
1929         desc = rxq->rx_tail + offset;
1930         if (desc >= rxq->nb_rx_desc)
1931                 desc -= rxq->nb_rx_desc;
1932
1933         rxdp = &(rxq->rx_ring[desc]);
1934
1935         ret = !!(((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1936                 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
1937                                 (1 << I40E_RX_DESC_STATUS_DD_SHIFT));
1938
1939         return ret;
1940 }
1941
1942 int
1943 i40e_dev_rx_descriptor_status(void *rx_queue, uint16_t offset)
1944 {
1945         struct i40e_rx_queue *rxq = rx_queue;
1946         volatile uint64_t *status;
1947         uint64_t mask;
1948         uint32_t desc;
1949
1950         if (unlikely(offset >= rxq->nb_rx_desc))
1951                 return -EINVAL;
1952
1953         if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
1954                 return RTE_ETH_RX_DESC_UNAVAIL;
1955
1956         desc = rxq->rx_tail + offset;
1957         if (desc >= rxq->nb_rx_desc)
1958                 desc -= rxq->nb_rx_desc;
1959
1960         status = &rxq->rx_ring[desc].wb.qword1.status_error_len;
1961         mask = rte_le_to_cpu_64((1ULL << I40E_RX_DESC_STATUS_DD_SHIFT)
1962                 << I40E_RXD_QW1_STATUS_SHIFT);
1963         if (*status & mask)
1964                 return RTE_ETH_RX_DESC_DONE;
1965
1966         return RTE_ETH_RX_DESC_AVAIL;
1967 }
1968
1969 int
1970 i40e_dev_tx_descriptor_status(void *tx_queue, uint16_t offset)
1971 {
1972         struct i40e_tx_queue *txq = tx_queue;
1973         volatile uint64_t *status;
1974         uint64_t mask, expect;
1975         uint32_t desc;
1976
1977         if (unlikely(offset >= txq->nb_tx_desc))
1978                 return -EINVAL;
1979
1980         desc = txq->tx_tail + offset;
1981         /* go to next desc that has the RS bit */
1982         desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) *
1983                 txq->tx_rs_thresh;
1984         if (desc >= txq->nb_tx_desc) {
1985                 desc -= txq->nb_tx_desc;
1986                 if (desc >= txq->nb_tx_desc)
1987                         desc -= txq->nb_tx_desc;
1988         }
1989
1990         status = &txq->tx_ring[desc].cmd_type_offset_bsz;
1991         mask = rte_le_to_cpu_64(I40E_TXD_QW1_DTYPE_MASK);
1992         expect = rte_cpu_to_le_64(
1993                 I40E_TX_DESC_DTYPE_DESC_DONE << I40E_TXD_QW1_DTYPE_SHIFT);
1994         if ((*status & mask) == expect)
1995                 return RTE_ETH_TX_DESC_DONE;
1996
1997         return RTE_ETH_TX_DESC_FULL;
1998 }
1999
2000 int
2001 i40e_dev_tx_queue_setup(struct rte_eth_dev *dev,
2002                         uint16_t queue_idx,
2003                         uint16_t nb_desc,
2004                         unsigned int socket_id,
2005                         const struct rte_eth_txconf *tx_conf)
2006 {
2007         struct i40e_vsi *vsi;
2008         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2009         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2010         struct i40e_tx_queue *txq;
2011         const struct rte_memzone *tz;
2012         uint32_t ring_size;
2013         uint16_t tx_rs_thresh, tx_free_thresh;
2014         uint16_t i, base, bsf, tc_mapping;
2015
2016         if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
2017                 struct i40e_vf *vf =
2018                         I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2019                 vsi = &vf->vsi;
2020         } else
2021                 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
2022
2023         if (vsi == NULL) {
2024                 PMD_DRV_LOG(ERR, "VSI is NULL, or queue index (%u) "
2025                             "exceeds the maximum", queue_idx);
2026                 return I40E_ERR_PARAM;
2027         }
2028
2029         if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
2030                         (nb_desc > I40E_MAX_RING_DESC) ||
2031                         (nb_desc < I40E_MIN_RING_DESC)) {
2032                 PMD_DRV_LOG(ERR, "Number (%u) of transmit descriptors is "
2033                             "invalid", nb_desc);
2034                 return I40E_ERR_PARAM;
2035         }
2036
2037         /**
2038          * The following two parameters control the setting of the RS bit on
2039          * transmit descriptors. TX descriptors will have their RS bit set
2040          * after txq->tx_rs_thresh descriptors have been used. The TX
2041          * descriptor ring will be cleaned after txq->tx_free_thresh
2042          * descriptors are used or if the number of descriptors required to
2043          * transmit a packet is greater than the number of free TX descriptors.
2044          *
2045          * The following constraints must be satisfied:
2046          *  - tx_rs_thresh must be greater than 0.
2047          *  - tx_rs_thresh must be less than the size of the ring minus 2.
2048          *  - tx_rs_thresh must be less than or equal to tx_free_thresh.
2049          *  - tx_rs_thresh must be a divisor of the ring size.
2050          *  - tx_free_thresh must be greater than 0.
2051          *  - tx_free_thresh must be less than the size of the ring minus 3.
2052          *
2053          * One descriptor in the TX ring is used as a sentinel to avoid a H/W
2054          * race condition, hence the maximum threshold constraints. When set
2055          * to zero use default values.
2056          */
2057         tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
2058                 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
2059         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
2060                 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
2061         if (tx_rs_thresh >= (nb_desc - 2)) {
2062                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
2063                              "number of TX descriptors minus 2. "
2064                              "(tx_rs_thresh=%u port=%d queue=%d)",
2065                              (unsigned int)tx_rs_thresh,
2066                              (int)dev->data->port_id,
2067                              (int)queue_idx);
2068                 return I40E_ERR_PARAM;
2069         }
2070         if (tx_free_thresh >= (nb_desc - 3)) {
2071                 PMD_INIT_LOG(ERR, "tx_free_thresh must be less than the "
2072                              "number of TX descriptors minus 3. "
2073                              "(tx_free_thresh=%u port=%d queue=%d)",
2074                              (unsigned int)tx_free_thresh,
2075                              (int)dev->data->port_id,
2076                              (int)queue_idx);
2077                 return I40E_ERR_PARAM;
2078         }
2079         if (tx_rs_thresh > tx_free_thresh) {
2080                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
2081                              "equal to tx_free_thresh. (tx_free_thresh=%u"
2082                              " tx_rs_thresh=%u port=%d queue=%d)",
2083                              (unsigned int)tx_free_thresh,
2084                              (unsigned int)tx_rs_thresh,
2085                              (int)dev->data->port_id,
2086                              (int)queue_idx);
2087                 return I40E_ERR_PARAM;
2088         }
2089         if ((nb_desc % tx_rs_thresh) != 0) {
2090                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
2091                              "number of TX descriptors. (tx_rs_thresh=%u"
2092                              " port=%d queue=%d)",
2093                              (unsigned int)tx_rs_thresh,
2094                              (int)dev->data->port_id,
2095                              (int)queue_idx);
2096                 return I40E_ERR_PARAM;
2097         }
2098         if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
2099                 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
2100                              "tx_rs_thresh is greater than 1. "
2101                              "(tx_rs_thresh=%u port=%d queue=%d)",
2102                              (unsigned int)tx_rs_thresh,
2103                              (int)dev->data->port_id,
2104                              (int)queue_idx);
2105                 return I40E_ERR_PARAM;
2106         }
2107
2108         /* Free memory if needed. */
2109         if (dev->data->tx_queues[queue_idx]) {
2110                 i40e_dev_tx_queue_release(dev->data->tx_queues[queue_idx]);
2111                 dev->data->tx_queues[queue_idx] = NULL;
2112         }
2113
2114         /* Allocate the TX queue data structure. */
2115         txq = rte_zmalloc_socket("i40e tx queue",
2116                                   sizeof(struct i40e_tx_queue),
2117                                   RTE_CACHE_LINE_SIZE,
2118                                   socket_id);
2119         if (!txq) {
2120                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2121                             "tx queue structure");
2122                 return -ENOMEM;
2123         }
2124
2125         /* Allocate TX hardware ring descriptors. */
2126         ring_size = sizeof(struct i40e_tx_desc) * I40E_MAX_RING_DESC;
2127         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2128         tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
2129                               ring_size, I40E_RING_BASE_ALIGN, socket_id);
2130         if (!tz) {
2131                 i40e_dev_tx_queue_release(txq);
2132                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX");
2133                 return -ENOMEM;
2134         }
2135
2136         txq->nb_tx_desc = nb_desc;
2137         txq->tx_rs_thresh = tx_rs_thresh;
2138         txq->tx_free_thresh = tx_free_thresh;
2139         txq->pthresh = tx_conf->tx_thresh.pthresh;
2140         txq->hthresh = tx_conf->tx_thresh.hthresh;
2141         txq->wthresh = tx_conf->tx_thresh.wthresh;
2142         txq->queue_id = queue_idx;
2143         if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF)
2144                 txq->reg_idx = queue_idx;
2145         else /* PF device */
2146                 txq->reg_idx = vsi->base_queue +
2147                         i40e_get_queue_offset_by_qindex(pf, queue_idx);
2148
2149         txq->port_id = dev->data->port_id;
2150         txq->txq_flags = tx_conf->txq_flags;
2151         txq->vsi = vsi;
2152         txq->tx_deferred_start = tx_conf->tx_deferred_start;
2153
2154         txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
2155         txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2156
2157         /* Allocate software ring */
2158         txq->sw_ring =
2159                 rte_zmalloc_socket("i40e tx sw ring",
2160                                    sizeof(struct i40e_tx_entry) * nb_desc,
2161                                    RTE_CACHE_LINE_SIZE,
2162                                    socket_id);
2163         if (!txq->sw_ring) {
2164                 i40e_dev_tx_queue_release(txq);
2165                 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW TX ring");
2166                 return -ENOMEM;
2167         }
2168
2169         i40e_reset_tx_queue(txq);
2170         txq->q_set = TRUE;
2171         dev->data->tx_queues[queue_idx] = txq;
2172
2173         /* Use a simple TX queue without offloads or multi segs if possible */
2174         i40e_set_tx_function_flag(dev, txq);
2175
2176         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2177                 if (!(vsi->enabled_tc & (1 << i)))
2178                         continue;
2179                 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
2180                 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
2181                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
2182                 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
2183                         I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
2184
2185                 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
2186                         txq->dcb_tc = i;
2187         }
2188
2189         return 0;
2190 }
2191
2192 void
2193 i40e_dev_tx_queue_release(void *txq)
2194 {
2195         struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
2196
2197         if (!q) {
2198                 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
2199                 return;
2200         }
2201
2202         i40e_tx_queue_release_mbufs(q);
2203         rte_free(q->sw_ring);
2204         rte_free(q);
2205 }
2206
2207 const struct rte_memzone *
2208 i40e_memzone_reserve(const char *name, uint32_t len, int socket_id)
2209 {
2210         const struct rte_memzone *mz;
2211
2212         mz = rte_memzone_lookup(name);
2213         if (mz)
2214                 return mz;
2215
2216         if (rte_xen_dom0_supported())
2217                 mz = rte_memzone_reserve_bounded(name, len,
2218                                 socket_id, 0, I40E_RING_BASE_ALIGN, RTE_PGSIZE_2M);
2219         else
2220                 mz = rte_memzone_reserve_aligned(name, len,
2221                                 socket_id, 0, I40E_RING_BASE_ALIGN);
2222         return mz;
2223 }
2224
2225 void
2226 i40e_rx_queue_release_mbufs(struct i40e_rx_queue *rxq)
2227 {
2228         uint16_t i;
2229
2230         /* SSE Vector driver has a different way of releasing mbufs. */
2231         if (rxq->rx_using_sse) {
2232                 i40e_rx_queue_release_mbufs_vec(rxq);
2233                 return;
2234         }
2235
2236         if (!rxq->sw_ring) {
2237                 PMD_DRV_LOG(DEBUG, "Pointer to sw_ring is NULL");
2238                 return;
2239         }
2240
2241         for (i = 0; i < rxq->nb_rx_desc; i++) {
2242                 if (rxq->sw_ring[i].mbuf) {
2243                         rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2244                         rxq->sw_ring[i].mbuf = NULL;
2245                 }
2246         }
2247 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2248         if (rxq->rx_nb_avail == 0)
2249                 return;
2250         for (i = 0; i < rxq->rx_nb_avail; i++) {
2251                 struct rte_mbuf *mbuf;
2252
2253                 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
2254                 rte_pktmbuf_free_seg(mbuf);
2255         }
2256         rxq->rx_nb_avail = 0;
2257 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2258 }
2259
2260 void
2261 i40e_reset_rx_queue(struct i40e_rx_queue *rxq)
2262 {
2263         unsigned i;
2264         uint16_t len;
2265
2266         if (!rxq) {
2267                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
2268                 return;
2269         }
2270
2271 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2272         if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
2273                 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_I40E_RX_MAX_BURST);
2274         else
2275 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2276                 len = rxq->nb_rx_desc;
2277
2278         for (i = 0; i < len * sizeof(union i40e_rx_desc); i++)
2279                 ((volatile char *)rxq->rx_ring)[i] = 0;
2280
2281         memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2282         for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; ++i)
2283                 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2284
2285 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2286         rxq->rx_nb_avail = 0;
2287         rxq->rx_next_avail = 0;
2288         rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2289 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2290         rxq->rx_tail = 0;
2291         rxq->nb_rx_hold = 0;
2292         rxq->pkt_first_seg = NULL;
2293         rxq->pkt_last_seg = NULL;
2294
2295         rxq->rxrearm_start = 0;
2296         rxq->rxrearm_nb = 0;
2297 }
2298
2299 void
2300 i40e_tx_queue_release_mbufs(struct i40e_tx_queue *txq)
2301 {
2302         uint16_t i;
2303
2304         if (!txq || !txq->sw_ring) {
2305                 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
2306                 return;
2307         }
2308
2309         for (i = 0; i < txq->nb_tx_desc; i++) {
2310                 if (txq->sw_ring[i].mbuf) {
2311                         rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2312                         txq->sw_ring[i].mbuf = NULL;
2313                 }
2314         }
2315 }
2316
2317 void
2318 i40e_reset_tx_queue(struct i40e_tx_queue *txq)
2319 {
2320         struct i40e_tx_entry *txe;
2321         uint16_t i, prev, size;
2322
2323         if (!txq) {
2324                 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
2325                 return;
2326         }
2327
2328         txe = txq->sw_ring;
2329         size = sizeof(struct i40e_tx_desc) * txq->nb_tx_desc;
2330         for (i = 0; i < size; i++)
2331                 ((volatile char *)txq->tx_ring)[i] = 0;
2332
2333         prev = (uint16_t)(txq->nb_tx_desc - 1);
2334         for (i = 0; i < txq->nb_tx_desc; i++) {
2335                 volatile struct i40e_tx_desc *txd = &txq->tx_ring[i];
2336
2337                 txd->cmd_type_offset_bsz =
2338                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE);
2339                 txe[i].mbuf =  NULL;
2340                 txe[i].last_id = i;
2341                 txe[prev].next_id = i;
2342                 prev = i;
2343         }
2344
2345         txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2346         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2347
2348         txq->tx_tail = 0;
2349         txq->nb_tx_used = 0;
2350
2351         txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
2352         txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
2353 }
2354
2355 /* Init the TX queue in hardware */
2356 int
2357 i40e_tx_queue_init(struct i40e_tx_queue *txq)
2358 {
2359         enum i40e_status_code err = I40E_SUCCESS;
2360         struct i40e_vsi *vsi = txq->vsi;
2361         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2362         uint16_t pf_q = txq->reg_idx;
2363         struct i40e_hmc_obj_txq tx_ctx;
2364         uint32_t qtx_ctl;
2365
2366         /* clear the context structure first */
2367         memset(&tx_ctx, 0, sizeof(tx_ctx));
2368         tx_ctx.new_context = 1;
2369         tx_ctx.base = txq->tx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2370         tx_ctx.qlen = txq->nb_tx_desc;
2371
2372 #ifdef RTE_LIBRTE_IEEE1588
2373         tx_ctx.timesync_ena = 1;
2374 #endif
2375         tx_ctx.rdylist = rte_le_to_cpu_16(vsi->info.qs_handle[txq->dcb_tc]);
2376         if (vsi->type == I40E_VSI_FDIR)
2377                 tx_ctx.fd_ena = TRUE;
2378
2379         err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2380         if (err != I40E_SUCCESS) {
2381                 PMD_DRV_LOG(ERR, "Failure of clean lan tx queue context");
2382                 return err;
2383         }
2384
2385         err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2386         if (err != I40E_SUCCESS) {
2387                 PMD_DRV_LOG(ERR, "Failure of set lan tx queue context");
2388                 return err;
2389         }
2390
2391         /* Now associate this queue with this PCI function */
2392         qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
2393         qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2394                                         I40E_QTX_CTL_PF_INDX_MASK);
2395         I40E_WRITE_REG(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2396         I40E_WRITE_FLUSH(hw);
2397
2398         txq->qtx_tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2399
2400         return err;
2401 }
2402
2403 int
2404 i40e_alloc_rx_queue_mbufs(struct i40e_rx_queue *rxq)
2405 {
2406         struct i40e_rx_entry *rxe = rxq->sw_ring;
2407         uint64_t dma_addr;
2408         uint16_t i;
2409
2410         for (i = 0; i < rxq->nb_rx_desc; i++) {
2411                 volatile union i40e_rx_desc *rxd;
2412                 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mp);
2413
2414                 if (unlikely(!mbuf)) {
2415                         PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
2416                         return -ENOMEM;
2417                 }
2418
2419                 rte_mbuf_refcnt_set(mbuf, 1);
2420                 mbuf->next = NULL;
2421                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2422                 mbuf->nb_segs = 1;
2423                 mbuf->port = rxq->port_id;
2424
2425                 dma_addr =
2426                         rte_cpu_to_le_64(rte_mbuf_data_dma_addr_default(mbuf));
2427
2428                 rxd = &rxq->rx_ring[i];
2429                 rxd->read.pkt_addr = dma_addr;
2430                 rxd->read.hdr_addr = 0;
2431 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2432                 rxd->read.rsvd1 = 0;
2433                 rxd->read.rsvd2 = 0;
2434 #endif /* RTE_LIBRTE_I40E_16BYTE_RX_DESC */
2435
2436                 rxe[i].mbuf = mbuf;
2437         }
2438
2439         return 0;
2440 }
2441
2442 /*
2443  * Calculate the buffer length, and check the jumbo frame
2444  * and maximum packet length.
2445  */
2446 static int
2447 i40e_rx_queue_config(struct i40e_rx_queue *rxq)
2448 {
2449         struct i40e_pf *pf = I40E_VSI_TO_PF(rxq->vsi);
2450         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2451         struct rte_eth_dev_data *data = pf->dev_data;
2452         uint16_t buf_size, len;
2453
2454         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2455                 RTE_PKTMBUF_HEADROOM);
2456
2457         switch (pf->flags & (I40E_FLAG_HEADER_SPLIT_DISABLED |
2458                         I40E_FLAG_HEADER_SPLIT_ENABLED)) {
2459         case I40E_FLAG_HEADER_SPLIT_ENABLED: /* Not supported */
2460                 rxq->rx_hdr_len = RTE_ALIGN(I40E_RXBUF_SZ_1024,
2461                                 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2462                 rxq->rx_buf_len = RTE_ALIGN(I40E_RXBUF_SZ_2048,
2463                                 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2464                 rxq->hs_mode = i40e_header_split_enabled;
2465                 break;
2466         case I40E_FLAG_HEADER_SPLIT_DISABLED:
2467         default:
2468                 rxq->rx_hdr_len = 0;
2469                 rxq->rx_buf_len = RTE_ALIGN(buf_size,
2470                         (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2471                 rxq->hs_mode = i40e_header_split_none;
2472                 break;
2473         }
2474
2475         len = hw->func_caps.rx_buf_chain_len * rxq->rx_buf_len;
2476         rxq->max_pkt_len = RTE_MIN(len, data->dev_conf.rxmode.max_rx_pkt_len);
2477         if (data->dev_conf.rxmode.jumbo_frame == 1) {
2478                 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
2479                         rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
2480                         PMD_DRV_LOG(ERR, "maximum packet length must "
2481                                     "be larger than %u and smaller than %u,"
2482                                     "as jumbo frame is enabled",
2483                                     (uint32_t)ETHER_MAX_LEN,
2484                                     (uint32_t)I40E_FRAME_SIZE_MAX);
2485                         return I40E_ERR_CONFIG;
2486                 }
2487         } else {
2488                 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
2489                         rxq->max_pkt_len > ETHER_MAX_LEN) {
2490                         PMD_DRV_LOG(ERR, "maximum packet length must be "
2491                                     "larger than %u and smaller than %u, "
2492                                     "as jumbo frame is disabled",
2493                                     (uint32_t)ETHER_MIN_LEN,
2494                                     (uint32_t)ETHER_MAX_LEN);
2495                         return I40E_ERR_CONFIG;
2496                 }
2497         }
2498
2499         return 0;
2500 }
2501
2502 /* Init the RX queue in hardware */
2503 int
2504 i40e_rx_queue_init(struct i40e_rx_queue *rxq)
2505 {
2506         int err = I40E_SUCCESS;
2507         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2508         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(rxq->vsi);
2509         uint16_t pf_q = rxq->reg_idx;
2510         uint16_t buf_size;
2511         struct i40e_hmc_obj_rxq rx_ctx;
2512
2513         err = i40e_rx_queue_config(rxq);
2514         if (err < 0) {
2515                 PMD_DRV_LOG(ERR, "Failed to config RX queue");
2516                 return err;
2517         }
2518
2519         /* Clear the context structure first */
2520         memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
2521         rx_ctx.dbuff = rxq->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2522         rx_ctx.hbuff = rxq->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2523
2524         rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2525         rx_ctx.qlen = rxq->nb_rx_desc;
2526 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2527         rx_ctx.dsize = 1;
2528 #endif
2529         rx_ctx.dtype = rxq->hs_mode;
2530         if (rxq->hs_mode)
2531                 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_ALL;
2532         else
2533                 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
2534         rx_ctx.rxmax = rxq->max_pkt_len;
2535         rx_ctx.tphrdesc_ena = 1;
2536         rx_ctx.tphwdesc_ena = 1;
2537         rx_ctx.tphdata_ena = 1;
2538         rx_ctx.tphhead_ena = 1;
2539         rx_ctx.lrxqthresh = 2;
2540         rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
2541         rx_ctx.l2tsel = 1;
2542         /* showiv indicates if inner VLAN is stripped inside of tunnel
2543          * packet. When set it to 1, vlan information is stripped from
2544          * the inner header, but the hardware does not put it in the
2545          * descriptor. So set it zero by default.
2546          */
2547         rx_ctx.showiv = 0;
2548         rx_ctx.prefena = 1;
2549
2550         err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2551         if (err != I40E_SUCCESS) {
2552                 PMD_DRV_LOG(ERR, "Failed to clear LAN RX queue context");
2553                 return err;
2554         }
2555         err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2556         if (err != I40E_SUCCESS) {
2557                 PMD_DRV_LOG(ERR, "Failed to set LAN RX queue context");
2558                 return err;
2559         }
2560
2561         rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2562
2563         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2564                 RTE_PKTMBUF_HEADROOM);
2565
2566         /* Check if scattered RX needs to be used. */
2567         if ((rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {
2568                 dev_data->scattered_rx = 1;
2569         }
2570
2571         /* Init the RX tail regieter. */
2572         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
2573
2574         return 0;
2575 }
2576
2577 void
2578 i40e_dev_clear_queues(struct rte_eth_dev *dev)
2579 {
2580         uint16_t i;
2581
2582         PMD_INIT_FUNC_TRACE();
2583
2584         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2585                 if (!dev->data->tx_queues[i])
2586                         continue;
2587                 i40e_tx_queue_release_mbufs(dev->data->tx_queues[i]);
2588                 i40e_reset_tx_queue(dev->data->tx_queues[i]);
2589         }
2590
2591         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2592                 if (!dev->data->rx_queues[i])
2593                         continue;
2594                 i40e_rx_queue_release_mbufs(dev->data->rx_queues[i]);
2595                 i40e_reset_rx_queue(dev->data->rx_queues[i]);
2596         }
2597 }
2598
2599 void
2600 i40e_dev_free_queues(struct rte_eth_dev *dev)
2601 {
2602         uint16_t i;
2603
2604         PMD_INIT_FUNC_TRACE();
2605
2606         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2607                 if (!dev->data->rx_queues[i])
2608                         continue;
2609                 i40e_dev_rx_queue_release(dev->data->rx_queues[i]);
2610                 dev->data->rx_queues[i] = NULL;
2611         }
2612         dev->data->nb_rx_queues = 0;
2613
2614         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2615                 if (!dev->data->tx_queues[i])
2616                         continue;
2617                 i40e_dev_tx_queue_release(dev->data->tx_queues[i]);
2618                 dev->data->tx_queues[i] = NULL;
2619         }
2620         dev->data->nb_tx_queues = 0;
2621 }
2622
2623 #define I40E_FDIR_NUM_TX_DESC  I40E_MIN_RING_DESC
2624 #define I40E_FDIR_NUM_RX_DESC  I40E_MIN_RING_DESC
2625
2626 enum i40e_status_code
2627 i40e_fdir_setup_tx_resources(struct i40e_pf *pf)
2628 {
2629         struct i40e_tx_queue *txq;
2630         const struct rte_memzone *tz = NULL;
2631         uint32_t ring_size;
2632         struct rte_eth_dev *dev;
2633
2634         if (!pf) {
2635                 PMD_DRV_LOG(ERR, "PF is not available");
2636                 return I40E_ERR_BAD_PTR;
2637         }
2638
2639         dev = pf->adapter->eth_dev;
2640
2641         /* Allocate the TX queue data structure. */
2642         txq = rte_zmalloc_socket("i40e fdir tx queue",
2643                                   sizeof(struct i40e_tx_queue),
2644                                   RTE_CACHE_LINE_SIZE,
2645                                   SOCKET_ID_ANY);
2646         if (!txq) {
2647                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2648                                         "tx queue structure.");
2649                 return I40E_ERR_NO_MEMORY;
2650         }
2651
2652         /* Allocate TX hardware ring descriptors. */
2653         ring_size = sizeof(struct i40e_tx_desc) * I40E_FDIR_NUM_TX_DESC;
2654         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2655
2656         tz = rte_eth_dma_zone_reserve(dev, "fdir_tx_ring",
2657                                       I40E_FDIR_QUEUE_ID, ring_size,
2658                                       I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
2659         if (!tz) {
2660                 i40e_dev_tx_queue_release(txq);
2661                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX.");
2662                 return I40E_ERR_NO_MEMORY;
2663         }
2664
2665         txq->nb_tx_desc = I40E_FDIR_NUM_TX_DESC;
2666         txq->queue_id = I40E_FDIR_QUEUE_ID;
2667         txq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2668         txq->vsi = pf->fdir.fdir_vsi;
2669
2670         txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
2671         txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2672         /*
2673          * don't need to allocate software ring and reset for the fdir
2674          * program queue just set the queue has been configured.
2675          */
2676         txq->q_set = TRUE;
2677         pf->fdir.txq = txq;
2678
2679         return I40E_SUCCESS;
2680 }
2681
2682 enum i40e_status_code
2683 i40e_fdir_setup_rx_resources(struct i40e_pf *pf)
2684 {
2685         struct i40e_rx_queue *rxq;
2686         const struct rte_memzone *rz = NULL;
2687         uint32_t ring_size;
2688         struct rte_eth_dev *dev;
2689
2690         if (!pf) {
2691                 PMD_DRV_LOG(ERR, "PF is not available");
2692                 return I40E_ERR_BAD_PTR;
2693         }
2694
2695         dev = pf->adapter->eth_dev;
2696
2697         /* Allocate the RX queue data structure. */
2698         rxq = rte_zmalloc_socket("i40e fdir rx queue",
2699                                   sizeof(struct i40e_rx_queue),
2700                                   RTE_CACHE_LINE_SIZE,
2701                                   SOCKET_ID_ANY);
2702         if (!rxq) {
2703                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2704                                         "rx queue structure.");
2705                 return I40E_ERR_NO_MEMORY;
2706         }
2707
2708         /* Allocate RX hardware ring descriptors. */
2709         ring_size = sizeof(union i40e_rx_desc) * I40E_FDIR_NUM_RX_DESC;
2710         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2711
2712         rz = rte_eth_dma_zone_reserve(dev, "fdir_rx_ring",
2713                                       I40E_FDIR_QUEUE_ID, ring_size,
2714                                       I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
2715         if (!rz) {
2716                 i40e_dev_rx_queue_release(rxq);
2717                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX.");
2718                 return I40E_ERR_NO_MEMORY;
2719         }
2720
2721         rxq->nb_rx_desc = I40E_FDIR_NUM_RX_DESC;
2722         rxq->queue_id = I40E_FDIR_QUEUE_ID;
2723         rxq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2724         rxq->vsi = pf->fdir.fdir_vsi;
2725
2726         rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
2727         rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
2728
2729         /*
2730          * Don't need to allocate software ring and reset for the fdir
2731          * rx queue, just set the queue has been configured.
2732          */
2733         rxq->q_set = TRUE;
2734         pf->fdir.rxq = rxq;
2735
2736         return I40E_SUCCESS;
2737 }
2738
2739 void
2740 i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2741         struct rte_eth_rxq_info *qinfo)
2742 {
2743         struct i40e_rx_queue *rxq;
2744
2745         rxq = dev->data->rx_queues[queue_id];
2746
2747         qinfo->mp = rxq->mp;
2748         qinfo->scattered_rx = dev->data->scattered_rx;
2749         qinfo->nb_desc = rxq->nb_rx_desc;
2750
2751         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2752         qinfo->conf.rx_drop_en = rxq->drop_en;
2753         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2754 }
2755
2756 void
2757 i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2758         struct rte_eth_txq_info *qinfo)
2759 {
2760         struct i40e_tx_queue *txq;
2761
2762         txq = dev->data->tx_queues[queue_id];
2763
2764         qinfo->nb_desc = txq->nb_tx_desc;
2765
2766         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2767         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2768         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2769
2770         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2771         qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
2772         qinfo->conf.txq_flags = txq->txq_flags;
2773         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2774 }
2775
2776 void __attribute__((cold))
2777 i40e_set_rx_function(struct rte_eth_dev *dev)
2778 {
2779         struct i40e_adapter *ad =
2780                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2781         uint16_t rx_using_sse, i;
2782         /* In order to allow Vector Rx there are a few configuration
2783          * conditions to be met and Rx Bulk Allocation should be allowed.
2784          */
2785         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2786                 if (i40e_rx_vec_dev_conf_condition_check(dev) ||
2787                     !ad->rx_bulk_alloc_allowed) {
2788                         PMD_INIT_LOG(DEBUG, "Port[%d] doesn't meet"
2789                                      " Vector Rx preconditions",
2790                                      dev->data->port_id);
2791
2792                         ad->rx_vec_allowed = false;
2793                 }
2794                 if (ad->rx_vec_allowed) {
2795                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2796                                 struct i40e_rx_queue *rxq =
2797                                         dev->data->rx_queues[i];
2798
2799                                 if (rxq && i40e_rxq_vec_setup(rxq)) {
2800                                         ad->rx_vec_allowed = false;
2801                                         break;
2802                                 }
2803                         }
2804                 }
2805         }
2806
2807         if (dev->data->scattered_rx) {
2808                 /* Set the non-LRO scattered callback: there are Vector and
2809                  * single allocation versions.
2810                  */
2811                 if (ad->rx_vec_allowed) {
2812                         PMD_INIT_LOG(DEBUG, "Using Vector Scattered Rx "
2813                                             "callback (port=%d).",
2814                                      dev->data->port_id);
2815
2816                         dev->rx_pkt_burst = i40e_recv_scattered_pkts_vec;
2817                 } else {
2818                         PMD_INIT_LOG(DEBUG, "Using a Scattered with bulk "
2819                                            "allocation callback (port=%d).",
2820                                      dev->data->port_id);
2821                         dev->rx_pkt_burst = i40e_recv_scattered_pkts;
2822                 }
2823         /* If parameters allow we are going to choose between the following
2824          * callbacks:
2825          *    - Vector
2826          *    - Bulk Allocation
2827          *    - Single buffer allocation (the simplest one)
2828          */
2829         } else if (ad->rx_vec_allowed) {
2830                 PMD_INIT_LOG(DEBUG, "Vector rx enabled, please make sure RX "
2831                                     "burst size no less than %d (port=%d).",
2832                              RTE_I40E_DESCS_PER_LOOP,
2833                              dev->data->port_id);
2834
2835                 dev->rx_pkt_burst = i40e_recv_pkts_vec;
2836         } else if (ad->rx_bulk_alloc_allowed) {
2837                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
2838                                     "satisfied. Rx Burst Bulk Alloc function "
2839                                     "will be used on port=%d.",
2840                              dev->data->port_id);
2841
2842                 dev->rx_pkt_burst = i40e_recv_pkts_bulk_alloc;
2843         } else {
2844                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are not "
2845                                     "satisfied, or Scattered Rx is requested "
2846                                     "(port=%d).",
2847                              dev->data->port_id);
2848
2849                 dev->rx_pkt_burst = i40e_recv_pkts;
2850         }
2851
2852         /* Propagate information about RX function choice through all queues. */
2853         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2854                 rx_using_sse =
2855                         (dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
2856                          dev->rx_pkt_burst == i40e_recv_pkts_vec);
2857
2858                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2859                         struct i40e_rx_queue *rxq = dev->data->rx_queues[i];
2860
2861                         if (rxq)
2862                                 rxq->rx_using_sse = rx_using_sse;
2863                 }
2864         }
2865 }
2866
2867 void __attribute__((cold))
2868 i40e_set_tx_function_flag(struct rte_eth_dev *dev, struct i40e_tx_queue *txq)
2869 {
2870         struct i40e_adapter *ad =
2871                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2872
2873         /* Use a simple Tx queue (no offloads, no multi segs) if possible */
2874         if (((txq->txq_flags & I40E_SIMPLE_FLAGS) == I40E_SIMPLE_FLAGS)
2875                         && (txq->tx_rs_thresh >= RTE_PMD_I40E_TX_MAX_BURST)) {
2876                 if (txq->tx_rs_thresh <= RTE_I40E_TX_MAX_FREE_BUF_SZ) {
2877                         PMD_INIT_LOG(DEBUG, "Vector tx"
2878                                      " can be enabled on this txq.");
2879
2880                 } else {
2881                         ad->tx_vec_allowed = false;
2882                 }
2883         } else {
2884                 ad->tx_simple_allowed = false;
2885         }
2886 }
2887
2888 void __attribute__((cold))
2889 i40e_set_tx_function(struct rte_eth_dev *dev)
2890 {
2891         struct i40e_adapter *ad =
2892                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2893         int i;
2894
2895         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2896                 if (ad->tx_vec_allowed) {
2897                         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2898                                 struct i40e_tx_queue *txq =
2899                                         dev->data->tx_queues[i];
2900
2901                                 if (txq && i40e_txq_vec_setup(txq)) {
2902                                         ad->tx_vec_allowed = false;
2903                                         break;
2904                                 }
2905                         }
2906                 }
2907         }
2908
2909         if (ad->tx_simple_allowed) {
2910                 if (ad->tx_vec_allowed) {
2911                         PMD_INIT_LOG(DEBUG, "Vector tx finally be used.");
2912                         dev->tx_pkt_burst = i40e_xmit_pkts_vec;
2913                 } else {
2914                         PMD_INIT_LOG(DEBUG, "Simple tx finally be used.");
2915                         dev->tx_pkt_burst = i40e_xmit_pkts_simple;
2916                 }
2917                 dev->tx_pkt_prepare = NULL;
2918         } else {
2919                 PMD_INIT_LOG(DEBUG, "Xmit tx finally be used.");
2920                 dev->tx_pkt_burst = i40e_xmit_pkts;
2921                 dev->tx_pkt_prepare = i40e_prep_pkts;
2922         }
2923 }
2924
2925 /* Stubs needed for linkage when CONFIG_RTE_I40E_INC_VECTOR is set to 'n' */
2926 int __attribute__((weak))
2927 i40e_rx_vec_dev_conf_condition_check(struct rte_eth_dev __rte_unused *dev)
2928 {
2929         return -1;
2930 }
2931
2932 uint16_t __attribute__((weak))
2933 i40e_recv_pkts_vec(
2934         void __rte_unused *rx_queue,
2935         struct rte_mbuf __rte_unused **rx_pkts,
2936         uint16_t __rte_unused nb_pkts)
2937 {
2938         return 0;
2939 }
2940
2941 uint16_t __attribute__((weak))
2942 i40e_recv_scattered_pkts_vec(
2943         void __rte_unused *rx_queue,
2944         struct rte_mbuf __rte_unused **rx_pkts,
2945         uint16_t __rte_unused nb_pkts)
2946 {
2947         return 0;
2948 }
2949
2950 int __attribute__((weak))
2951 i40e_rxq_vec_setup(struct i40e_rx_queue __rte_unused *rxq)
2952 {
2953         return -1;
2954 }
2955
2956 int __attribute__((weak))
2957 i40e_txq_vec_setup(struct i40e_tx_queue __rte_unused *txq)
2958 {
2959         return -1;
2960 }
2961
2962 void __attribute__((weak))
2963 i40e_rx_queue_release_mbufs_vec(struct i40e_rx_queue __rte_unused*rxq)
2964 {
2965         return;
2966 }
2967
2968 uint16_t __attribute__((weak))
2969 i40e_xmit_fixed_burst_vec(void __rte_unused * tx_queue,
2970                           struct rte_mbuf __rte_unused **tx_pkts,
2971                           uint16_t __rte_unused nb_pkts)
2972 {
2973         return 0;
2974 }