drivers/net/i40e/i40e_rxtx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2016 Intel Corporation
   3  */
   4
   5 #include <stdio.h>
   6 #include <stdlib.h>
   7 #include <string.h>
   8 #include <errno.h>
   9 #include <stdint.h>
  10 #include <stdarg.h>
  11 #include <unistd.h>
  12 #include <inttypes.h>
  13 #include <sys/queue.h>
  14
  15 #include <rte_string_fns.h>
  16 #include <rte_memzone.h>
  17 #include <rte_mbuf.h>
  18 #include <rte_malloc.h>
  19 #include <rte_ether.h>
  20 #include <ethdev_driver.h>
  21 #include <rte_tcp.h>
  22 #include <rte_sctp.h>
  23 #include <rte_udp.h>
  24 #include <rte_ip.h>
  25 #include <rte_net.h>
  26 #include <rte_vect.h>
  27
  28 #include "i40e_logs.h"
  29 #include "base/i40e_prototype.h"
  30 #include "base/i40e_type.h"
  31 #include "i40e_ethdev.h"
  32 #include "i40e_rxtx.h"
  33
  34 #define DEFAULT_TX_RS_THRESH   32
  35 #define DEFAULT_TX_FREE_THRESH 32
  36
  37 #define I40E_TX_MAX_BURST  32
  38
  39 #define I40E_DMA_MEM_ALIGN 4096
  40
  41 /* Base address of the HW descriptor ring should be 128B aligned. */
  42 #define I40E_RING_BASE_ALIGN    128
  43
  44 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
  45
  46 #ifdef RTE_LIBRTE_IEEE1588
  47 #define I40E_TX_IEEE1588_TMST RTE_MBUF_F_TX_IEEE1588_TMST
  48 #else
  49 #define I40E_TX_IEEE1588_TMST 0
  50 #endif
  51
  52 #define I40E_TX_CKSUM_OFFLOAD_MASK (RTE_MBUF_F_TX_IP_CKSUM |             \
  53                 RTE_MBUF_F_TX_L4_MASK |          \
  54                 RTE_MBUF_F_TX_TCP_SEG |          \
  55                 RTE_MBUF_F_TX_OUTER_IP_CKSUM)
  56
  57 #define I40E_TX_OFFLOAD_MASK (RTE_MBUF_F_TX_OUTER_IPV4 |        \
  58                 RTE_MBUF_F_TX_OUTER_IPV6 |      \
  59                 RTE_MBUF_F_TX_IPV4 |            \
  60                 RTE_MBUF_F_TX_IPV6 |            \
  61                 RTE_MBUF_F_TX_IP_CKSUM |       \
  62                 RTE_MBUF_F_TX_L4_MASK |        \
  63                 RTE_MBUF_F_TX_OUTER_IP_CKSUM | \
  64                 RTE_MBUF_F_TX_TCP_SEG |        \
  65                 RTE_MBUF_F_TX_QINQ |       \
  66                 RTE_MBUF_F_TX_VLAN |    \
  67                 RTE_MBUF_F_TX_TUNNEL_MASK |     \
  68                 RTE_MBUF_F_TX_OUTER_UDP_CKSUM | \
  69                 I40E_TX_IEEE1588_TMST)
  70
  71 #define I40E_TX_OFFLOAD_NOTSUP_MASK \
  72                 (RTE_MBUF_F_TX_OFFLOAD_MASK ^ I40E_TX_OFFLOAD_MASK)
  73
  74 #define I40E_TX_OFFLOAD_SIMPLE_SUP_MASK (RTE_MBUF_F_TX_IPV4 | \
  75                 RTE_MBUF_F_TX_IPV6 | \
  76                 RTE_MBUF_F_TX_OUTER_IPV4 | \
  77                 RTE_MBUF_F_TX_OUTER_IPV6)
  78
  79 #define I40E_TX_OFFLOAD_SIMPLE_NOTSUP_MASK \
  80                 (RTE_MBUF_F_TX_OFFLOAD_MASK ^ I40E_TX_OFFLOAD_SIMPLE_SUP_MASK)
  81
  82 static int
  83 i40e_monitor_callback(const uint64_t value,
  84                 const uint64_t arg[RTE_POWER_MONITOR_OPAQUE_SZ] __rte_unused)
  85 {
  86         const uint64_t m = rte_cpu_to_le_64(1 << I40E_RX_DESC_STATUS_DD_SHIFT);
  87         /*
  88          * we expect the DD bit to be set to 1 if this descriptor was already
  89          * written to.
  90          */
  91         return (value & m) == m ? -1 : 0;
  92 }
  93
  94 int
  95 i40e_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc)
  96 {
  97         struct i40e_rx_queue *rxq = rx_queue;
  98         volatile union i40e_rx_desc *rxdp;
  99         uint16_t desc;
 100
 101         desc = rxq->rx_tail;
 102         rxdp = &rxq->rx_ring[desc];
 103         /* watch for changes in status bit */
 104         pmc->addr = &rxdp->wb.qword1.status_error_len;
 105
 106         /* comparison callback */
 107         pmc->fn = i40e_monitor_callback;
 108
 109         /* registers are 64-bit */
 110         pmc->size = sizeof(uint64_t);
 111
 112         return 0;
 113 }
 114
 115 static inline void
 116 i40e_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union i40e_rx_desc *rxdp)
 117 {
 118         if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
 119                 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
 120                 mb->ol_flags |= RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED;
 121                 mb->vlan_tci =
 122                         rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
 123                 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
 124                            rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1));
 125         } else {
 126                 mb->vlan_tci = 0;
 127         }
 128 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
 129         if (rte_le_to_cpu_16(rxdp->wb.qword2.ext_status) &
 130                 (1 << I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT)) {
 131                 mb->ol_flags |= RTE_MBUF_F_RX_QINQ_STRIPPED | RTE_MBUF_F_RX_QINQ |
 132                         RTE_MBUF_F_RX_VLAN_STRIPPED | RTE_MBUF_F_RX_VLAN;
 133                 mb->vlan_tci_outer = mb->vlan_tci;
 134                 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2);
 135                 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
 136                            rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_1),
 137                            rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2));
 138         } else {
 139                 mb->vlan_tci_outer = 0;
 140         }
 141 #endif
 142         PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
 143                    mb->vlan_tci, mb->vlan_tci_outer);
 144 }
 145
 146 /* Translate the rx descriptor status to pkt flags */
 147 static inline uint64_t
 148 i40e_rxd_status_to_pkt_flags(uint64_t qword)
 149 {
 150         uint64_t flags;
 151
 152         /* Check if RSS_HASH */
 153         flags = (((qword >> I40E_RX_DESC_STATUS_FLTSTAT_SHIFT) &
 154                                         I40E_RX_DESC_FLTSTAT_RSS_HASH) ==
 155                         I40E_RX_DESC_FLTSTAT_RSS_HASH) ? RTE_MBUF_F_RX_RSS_HASH : 0;
 156
 157         /* Check if FDIR Match */
 158         flags |= (qword & (1 << I40E_RX_DESC_STATUS_FLM_SHIFT) ?
 159                                                         RTE_MBUF_F_RX_FDIR : 0);
 160
 161         return flags;
 162 }
 163
 164 static inline uint64_t
 165 i40e_rxd_error_to_pkt_flags(uint64_t qword)
 166 {
 167         uint64_t flags = 0;
 168         uint64_t error_bits = (qword >> I40E_RXD_QW1_ERROR_SHIFT);
 169
 170 #define I40E_RX_ERR_BITS 0x3f
 171         if (likely((error_bits & I40E_RX_ERR_BITS) == 0)) {
 172                 flags |= (RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_GOOD);
 173                 return flags;
 174         }
 175
 176         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_IPE_SHIFT)))
 177                 flags |= RTE_MBUF_F_RX_IP_CKSUM_BAD;
 178         else
 179                 flags |= RTE_MBUF_F_RX_IP_CKSUM_GOOD;
 180
 181         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT)))
 182                 flags |= RTE_MBUF_F_RX_L4_CKSUM_BAD;
 183         else
 184                 flags |= RTE_MBUF_F_RX_L4_CKSUM_GOOD;
 185
 186         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT)))
 187                 flags |= RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD;
 188
 189         return flags;
 190 }
 191
 192 /* Function to check and set the ieee1588 timesync index and get the
 193  * appropriate flags.
 194  */
 195 #ifdef RTE_LIBRTE_IEEE1588
 196 static inline uint64_t
 197 i40e_get_iee15888_flags(struct rte_mbuf *mb, uint64_t qword)
 198 {
 199         uint64_t pkt_flags = 0;
 200         uint16_t tsyn = (qword & (I40E_RXD_QW1_STATUS_TSYNVALID_MASK
 201                                   | I40E_RXD_QW1_STATUS_TSYNINDX_MASK))
 202                                     >> I40E_RX_DESC_STATUS_TSYNINDX_SHIFT;
 203
 204         if ((mb->packet_type & RTE_PTYPE_L2_MASK)
 205                         == RTE_PTYPE_L2_ETHER_TIMESYNC)
 206                 pkt_flags = RTE_MBUF_F_RX_IEEE1588_PTP;
 207         if (tsyn & 0x04) {
 208                 pkt_flags |= RTE_MBUF_F_RX_IEEE1588_TMST;
 209                 mb->timesync = tsyn & 0x03;
 210         }
 211
 212         return pkt_flags;
 213 }
 214 #endif
 215
 216 static inline uint64_t
 217 i40e_rxd_build_fdir(volatile union i40e_rx_desc *rxdp, struct rte_mbuf *mb)
 218 {
 219         uint64_t flags = 0;
 220 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
 221         uint16_t flexbh, flexbl;
 222
 223         flexbh = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
 224                 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT) &
 225                 I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK;
 226         flexbl = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
 227                 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT) &
 228                 I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK;
 229
 230
 231         if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID) {
 232                 mb->hash.fdir.hi =
 233                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.fd_id);
 234                 flags |= RTE_MBUF_F_RX_FDIR_ID;
 235         } else if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX) {
 236                 mb->hash.fdir.hi =
 237                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.flex_bytes_hi);
 238                 flags |= RTE_MBUF_F_RX_FDIR_FLX;
 239         }
 240         if (flexbl == I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX) {
 241                 mb->hash.fdir.lo =
 242                         rte_le_to_cpu_32(rxdp->wb.qword3.lo_dword.flex_bytes_lo);
 243                 flags |= RTE_MBUF_F_RX_FDIR_FLX;
 244         }
 245 #else
 246         mb->hash.fdir.hi =
 247                 rte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.fd_id);
 248         flags |= RTE_MBUF_F_RX_FDIR_ID;
 249 #endif
 250         return flags;
 251 }
 252
 253 static inline void
 254 i40e_parse_tunneling_params(uint64_t ol_flags,
 255                             union i40e_tx_offload tx_offload,
 256                             uint32_t *cd_tunneling)
 257 {
 258         /* EIPT: External (outer) IP header type */
 259         if (ol_flags & RTE_MBUF_F_TX_OUTER_IP_CKSUM)
 260                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
 261         else if (ol_flags & RTE_MBUF_F_TX_OUTER_IPV4)
 262                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
 263         else if (ol_flags & RTE_MBUF_F_TX_OUTER_IPV6)
 264                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
 265
 266         /* EIPLEN: External (outer) IP header length, in DWords */
 267         *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
 268                 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT;
 269
 270         /* L4TUNT: L4 Tunneling Type */
 271         switch (ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK) {
 272         case RTE_MBUF_F_TX_TUNNEL_IPIP:
 273                 /* for non UDP / GRE tunneling, set to 00b */
 274                 break;
 275         case RTE_MBUF_F_TX_TUNNEL_VXLAN:
 276         case RTE_MBUF_F_TX_TUNNEL_GENEVE:
 277                 *cd_tunneling |= I40E_TXD_CTX_UDP_TUNNELING;
 278                 break;
 279         case RTE_MBUF_F_TX_TUNNEL_GRE:
 280                 *cd_tunneling |= I40E_TXD_CTX_GRE_TUNNELING;
 281                 break;
 282         default:
 283                 PMD_TX_LOG(ERR, "Tunnel type not supported");
 284                 return;
 285         }
 286
 287         /* L4TUNLEN: L4 Tunneling Length, in Words
 288          *
 289          * We depend on app to set rte_mbuf.l2_len correctly.
 290          * For IP in GRE it should be set to the length of the GRE
 291          * header;
 292          * for MAC in GRE or MAC in UDP it should be set to the length
 293          * of the GRE or UDP headers plus the inner MAC up to including
 294          * its last Ethertype.
 295          */
 296         *cd_tunneling |= (tx_offload.l2_len >> 1) <<
 297                 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
 298 }
 299
 300 static inline void
 301 i40e_txd_enable_checksum(uint64_t ol_flags,
 302                         uint32_t *td_cmd,
 303                         uint32_t *td_offset,
 304                         union i40e_tx_offload tx_offload)
 305 {
 306         /* Set MACLEN */
 307         if (ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK)
 308                 *td_offset |= (tx_offload.outer_l2_len >> 1)
 309                                 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
 310         else
 311                 *td_offset |= (tx_offload.l2_len >> 1)
 312                         << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
 313
 314         /* Enable L3 checksum offloads */
 315         if (ol_flags & RTE_MBUF_F_TX_IP_CKSUM) {
 316                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
 317                 *td_offset |= (tx_offload.l3_len >> 2)
 318                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 319         } else if (ol_flags & RTE_MBUF_F_TX_IPV4) {
 320                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
 321                 *td_offset |= (tx_offload.l3_len >> 2)
 322                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 323         } else if (ol_flags & RTE_MBUF_F_TX_IPV6) {
 324                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
 325                 *td_offset |= (tx_offload.l3_len >> 2)
 326                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 327         }
 328
 329         if (ol_flags & RTE_MBUF_F_TX_TCP_SEG) {
 330                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
 331                 *td_offset |= (tx_offload.l4_len >> 2)
 332                         << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 333                 return;
 334         }
 335
 336         /* Enable L4 checksum offloads */
 337         switch (ol_flags & RTE_MBUF_F_TX_L4_MASK) {
 338         case RTE_MBUF_F_TX_TCP_CKSUM:
 339                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
 340                 *td_offset |= (sizeof(struct rte_tcp_hdr) >> 2) <<
 341                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 342                 break;
 343         case RTE_MBUF_F_TX_SCTP_CKSUM:
 344                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
 345                 *td_offset |= (sizeof(struct rte_sctp_hdr) >> 2) <<
 346                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 347                 break;
 348         case RTE_MBUF_F_TX_UDP_CKSUM:
 349                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
 350                 *td_offset |= (sizeof(struct rte_udp_hdr) >> 2) <<
 351                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 352                 break;
 353         default:
 354                 break;
 355         }
 356 }
 357
 358 /* Construct the tx flags */
 359 static inline uint64_t
 360 i40e_build_ctob(uint32_t td_cmd,
 361                 uint32_t td_offset,
 362                 unsigned int size,
 363                 uint32_t td_tag)
 364 {
 365         return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
 366                         ((uint64_t)td_cmd  << I40E_TXD_QW1_CMD_SHIFT) |
 367                         ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
 368                         ((uint64_t)size  << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
 369                         ((uint64_t)td_tag  << I40E_TXD_QW1_L2TAG1_SHIFT));
 370 }
 371
 372 static inline int
 373 i40e_xmit_cleanup(struct i40e_tx_queue *txq)
 374 {
 375         struct i40e_tx_entry *sw_ring = txq->sw_ring;
 376         volatile struct i40e_tx_desc *txd = txq->tx_ring;
 377         uint16_t last_desc_cleaned = txq->last_desc_cleaned;
 378         uint16_t nb_tx_desc = txq->nb_tx_desc;
 379         uint16_t desc_to_clean_to;
 380         uint16_t nb_tx_to_clean;
 381
 382         desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
 383         if (desc_to_clean_to >= nb_tx_desc)
 384                 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
 385
 386         desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
 387         if ((txd[desc_to_clean_to].cmd_type_offset_bsz &
 388                         rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
 389                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE)) {
 390                 PMD_TX_LOG(DEBUG, "TX descriptor %4u is not done "
 391                            "(port=%d queue=%d)", desc_to_clean_to,
 392                            txq->port_id, txq->queue_id);
 393                 return -1;
 394         }
 395
 396         if (last_desc_cleaned > desc_to_clean_to)
 397                 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
 398                                                         desc_to_clean_to);
 399         else
 400                 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
 401                                         last_desc_cleaned);
 402
 403         txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
 404
 405         txq->last_desc_cleaned = desc_to_clean_to;
 406         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
 407
 408         return 0;
 409 }
 410
 411 static inline int
 412 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 413 check_rx_burst_bulk_alloc_preconditions(struct i40e_rx_queue *rxq)
 414 #else
 415 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct i40e_rx_queue *rxq)
 416 #endif
 417 {
 418         int ret = 0;
 419
 420 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 421         if (!(rxq->rx_free_thresh >= RTE_PMD_I40E_RX_MAX_BURST)) {
 422                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 423                              "rxq->rx_free_thresh=%d, "
 424                              "RTE_PMD_I40E_RX_MAX_BURST=%d",
 425                              rxq->rx_free_thresh, RTE_PMD_I40E_RX_MAX_BURST);
 426                 ret = -EINVAL;
 427         } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
 428                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 429                              "rxq->rx_free_thresh=%d, "
 430                              "rxq->nb_rx_desc=%d",
 431                              rxq->rx_free_thresh, rxq->nb_rx_desc);
 432                 ret = -EINVAL;
 433         } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
 434                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 435                              "rxq->nb_rx_desc=%d, "
 436                              "rxq->rx_free_thresh=%d",
 437                              rxq->nb_rx_desc, rxq->rx_free_thresh);
 438                 ret = -EINVAL;
 439         }
 440 #else
 441         ret = -EINVAL;
 442 #endif
 443
 444         return ret;
 445 }
 446
 447 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 448 #define I40E_LOOK_AHEAD 8
 449 #if (I40E_LOOK_AHEAD != 8)
 450 #error "PMD I40E: I40E_LOOK_AHEAD must be 8\n"
 451 #endif
 452 static inline int
 453 i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq)
 454 {
 455         volatile union i40e_rx_desc *rxdp;
 456         struct i40e_rx_entry *rxep;
 457         struct rte_mbuf *mb;
 458         uint16_t pkt_len;
 459         uint64_t qword1;
 460         uint32_t rx_status;
 461         int32_t s[I40E_LOOK_AHEAD], var, nb_dd;
 462         int32_t i, j, nb_rx = 0;
 463         uint64_t pkt_flags;
 464         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
 465
 466         rxdp = &rxq->rx_ring[rxq->rx_tail];
 467         rxep = &rxq->sw_ring[rxq->rx_tail];
 468
 469         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 470         rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 471                                 I40E_RXD_QW1_STATUS_SHIFT;
 472
 473         /* Make sure there is at least 1 packet to receive */
 474         if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 475                 return 0;
 476
 477         /**
 478          * Scan LOOK_AHEAD descriptors at a time to determine which
 479          * descriptors reference packets that are ready to be received.
 480          */
 481         for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; i+=I40E_LOOK_AHEAD,
 482                         rxdp += I40E_LOOK_AHEAD, rxep += I40E_LOOK_AHEAD) {
 483                 /* Read desc statuses backwards to avoid race condition */
 484                 for (j = I40E_LOOK_AHEAD - 1; j >= 0; j--) {
 485                         qword1 = rte_le_to_cpu_64(\
 486                                 rxdp[j].wb.qword1.status_error_len);
 487                         s[j] = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 488                                         I40E_RXD_QW1_STATUS_SHIFT;
 489                 }
 490
 491                 /* This barrier is to order loads of different words in the descriptor */
 492                 rte_atomic_thread_fence(__ATOMIC_ACQUIRE);
 493
 494                 /* Compute how many status bits were set */
 495                 for (j = 0, nb_dd = 0; j < I40E_LOOK_AHEAD; j++) {
 496                         var = s[j] & (1 << I40E_RX_DESC_STATUS_DD_SHIFT);
 497 #ifdef RTE_ARCH_ARM
 498                         /* For Arm platforms, only compute continuous status bits */
 499                         if (var)
 500                                 nb_dd += 1;
 501                         else
 502                                 break;
 503 #else
 504                         nb_dd += var;
 505 #endif
 506                 }
 507
 508                 nb_rx += nb_dd;
 509
 510                 /* Translate descriptor info to mbuf parameters */
 511                 for (j = 0; j < nb_dd; j++) {
 512                         mb = rxep[j].mbuf;
 513                         qword1 = rte_le_to_cpu_64(\
 514                                 rxdp[j].wb.qword1.status_error_len);
 515                         pkt_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 516                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
 517                         mb->data_len = pkt_len;
 518                         mb->pkt_len = pkt_len;
 519                         mb->ol_flags = 0;
 520                         i40e_rxd_to_vlan_tci(mb, &rxdp[j]);
 521                         pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
 522                         pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
 523                         mb->packet_type =
 524                                 ptype_tbl[(uint8_t)((qword1 &
 525                                 I40E_RXD_QW1_PTYPE_MASK) >>
 526                                 I40E_RXD_QW1_PTYPE_SHIFT)];
 527                         if (pkt_flags & RTE_MBUF_F_RX_RSS_HASH)
 528                                 mb->hash.rss = rte_le_to_cpu_32(\
 529                                         rxdp[j].wb.qword0.hi_dword.rss);
 530                         if (pkt_flags & RTE_MBUF_F_RX_FDIR)
 531                                 pkt_flags |= i40e_rxd_build_fdir(&rxdp[j], mb);
 532
 533 #ifdef RTE_LIBRTE_IEEE1588
 534                         pkt_flags |= i40e_get_iee15888_flags(mb, qword1);
 535 #endif
 536                         mb->ol_flags |= pkt_flags;
 537
 538                 }
 539
 540                 for (j = 0; j < I40E_LOOK_AHEAD; j++)
 541                         rxq->rx_stage[i + j] = rxep[j].mbuf;
 542
 543                 if (nb_dd != I40E_LOOK_AHEAD)
 544                         break;
 545         }
 546
 547         /* Clear software ring entries */
 548         for (i = 0; i < nb_rx; i++)
 549                 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
 550
 551         return nb_rx;
 552 }
 553
 554 static inline uint16_t
 555 i40e_rx_fill_from_stage(struct i40e_rx_queue *rxq,
 556                         struct rte_mbuf **rx_pkts,
 557                         uint16_t nb_pkts)
 558 {
 559         uint16_t i;
 560         struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
 561
 562         nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
 563
 564         for (i = 0; i < nb_pkts; i++)
 565                 rx_pkts[i] = stage[i];
 566
 567         rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
 568         rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
 569
 570         return nb_pkts;
 571 }
 572
 573 static inline int
 574 i40e_rx_alloc_bufs(struct i40e_rx_queue *rxq)
 575 {
 576         volatile union i40e_rx_desc *rxdp;
 577         struct i40e_rx_entry *rxep;
 578         struct rte_mbuf *mb;
 579         uint16_t alloc_idx, i;
 580         uint64_t dma_addr;
 581         int diag;
 582
 583         /* Allocate buffers in bulk */
 584         alloc_idx = (uint16_t)(rxq->rx_free_trigger -
 585                                 (rxq->rx_free_thresh - 1));
 586         rxep = &(rxq->sw_ring[alloc_idx]);
 587         diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
 588                                         rxq->rx_free_thresh);
 589         if (unlikely(diag != 0)) {
 590                 PMD_DRV_LOG(ERR, "Failed to get mbufs in bulk");
 591                 return -ENOMEM;
 592         }
 593
 594         rxdp = &rxq->rx_ring[alloc_idx];
 595         for (i = 0; i < rxq->rx_free_thresh; i++) {
 596                 if (likely(i < (rxq->rx_free_thresh - 1)))
 597                         /* Prefetch next mbuf */
 598                         rte_prefetch0(rxep[i + 1].mbuf);
 599
 600                 mb = rxep[i].mbuf;
 601                 rte_mbuf_refcnt_set(mb, 1);
 602                 mb->next = NULL;
 603                 mb->data_off = RTE_PKTMBUF_HEADROOM;
 604                 mb->nb_segs = 1;
 605                 mb->port = rxq->port_id;
 606                 dma_addr = rte_cpu_to_le_64(\
 607                         rte_mbuf_data_iova_default(mb));
 608                 rxdp[i].read.hdr_addr = 0;
 609                 rxdp[i].read.pkt_addr = dma_addr;
 610         }
 611
 612         /* Update rx tail regsiter */
 613         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger);
 614
 615         rxq->rx_free_trigger =
 616                 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
 617         if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
 618                 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
 619
 620         return 0;
 621 }
 622
 623 static inline uint16_t
 624 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 625 {
 626         struct i40e_rx_queue *rxq = (struct i40e_rx_queue *)rx_queue;
 627         struct rte_eth_dev *dev;
 628         uint16_t nb_rx = 0;
 629
 630         if (!nb_pkts)
 631                 return 0;
 632
 633         if (rxq->rx_nb_avail)
 634                 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
 635
 636         nb_rx = (uint16_t)i40e_rx_scan_hw_ring(rxq);
 637         rxq->rx_next_avail = 0;
 638         rxq->rx_nb_avail = nb_rx;
 639         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
 640
 641         if (rxq->rx_tail > rxq->rx_free_trigger) {
 642                 if (i40e_rx_alloc_bufs(rxq) != 0) {
 643                         uint16_t i, j;
 644
 645                         dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
 646                         dev->data->rx_mbuf_alloc_failed +=
 647                                 rxq->rx_free_thresh;
 648
 649                         rxq->rx_nb_avail = 0;
 650                         rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
 651                         for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
 652                                 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
 653
 654                         return 0;
 655                 }
 656         }
 657
 658         if (rxq->rx_tail >= rxq->nb_rx_desc)
 659                 rxq->rx_tail = 0;
 660
 661         if (rxq->rx_nb_avail)
 662                 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
 663
 664         return 0;
 665 }
 666
 667 static uint16_t
 668 i40e_recv_pkts_bulk_alloc(void *rx_queue,
 669                           struct rte_mbuf **rx_pkts,
 670                           uint16_t nb_pkts)
 671 {
 672         uint16_t nb_rx = 0, n, count;
 673
 674         if (unlikely(nb_pkts == 0))
 675                 return 0;
 676
 677         if (likely(nb_pkts <= RTE_PMD_I40E_RX_MAX_BURST))
 678                 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
 679
 680         while (nb_pkts) {
 681                 n = RTE_MIN(nb_pkts, RTE_PMD_I40E_RX_MAX_BURST);
 682                 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
 683                 nb_rx = (uint16_t)(nb_rx + count);
 684                 nb_pkts = (uint16_t)(nb_pkts - count);
 685                 if (count < n)
 686                         break;
 687         }
 688
 689         return nb_rx;
 690 }
 691 #else
 692 static uint16_t
 693 i40e_recv_pkts_bulk_alloc(void __rte_unused *rx_queue,
 694                           struct rte_mbuf __rte_unused **rx_pkts,
 695                           uint16_t __rte_unused nb_pkts)
 696 {
 697         return 0;
 698 }
 699 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
 700
 701 uint16_t
 702 i40e_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 703 {
 704         struct i40e_rx_queue *rxq;
 705         volatile union i40e_rx_desc *rx_ring;
 706         volatile union i40e_rx_desc *rxdp;
 707         union i40e_rx_desc rxd;
 708         struct i40e_rx_entry *sw_ring;
 709         struct i40e_rx_entry *rxe;
 710         struct rte_eth_dev *dev;
 711         struct rte_mbuf *rxm;
 712         struct rte_mbuf *nmb;
 713         uint16_t nb_rx;
 714         uint32_t rx_status;
 715         uint64_t qword1;
 716         uint16_t rx_packet_len;
 717         uint16_t rx_id, nb_hold;
 718         uint64_t dma_addr;
 719         uint64_t pkt_flags;
 720         uint32_t *ptype_tbl;
 721
 722         nb_rx = 0;
 723         nb_hold = 0;
 724         rxq = rx_queue;
 725         rx_id = rxq->rx_tail;
 726         rx_ring = rxq->rx_ring;
 727         sw_ring = rxq->sw_ring;
 728         ptype_tbl = rxq->vsi->adapter->ptype_tbl;
 729
 730         while (nb_rx < nb_pkts) {
 731                 rxdp = &rx_ring[rx_id];
 732                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 733                 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
 734                                 >> I40E_RXD_QW1_STATUS_SHIFT;
 735
 736                 /* Check the DD bit first */
 737                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 738                         break;
 739
 740                 nmb = rte_mbuf_raw_alloc(rxq->mp);
 741                 if (unlikely(!nmb)) {
 742                         dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
 743                         dev->data->rx_mbuf_alloc_failed++;
 744                         break;
 745                 }
 746
 747                 rxd = *rxdp;
 748                 nb_hold++;
 749                 rxe = &sw_ring[rx_id];
 750                 rx_id++;
 751                 if (unlikely(rx_id == rxq->nb_rx_desc))
 752                         rx_id = 0;
 753
 754                 /* Prefetch next mbuf */
 755                 rte_prefetch0(sw_ring[rx_id].mbuf);
 756
 757                 /**
 758                  * When next RX descriptor is on a cache line boundary,
 759                  * prefetch the next 4 RX descriptors and next 8 pointers
 760                  * to mbufs.
 761                  */
 762                 if ((rx_id & 0x3) == 0) {
 763                         rte_prefetch0(&rx_ring[rx_id]);
 764                         rte_prefetch0(&sw_ring[rx_id]);
 765                 }
 766                 rxm = rxe->mbuf;
 767                 rxe->mbuf = nmb;
 768                 dma_addr =
 769                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
 770                 rxdp->read.hdr_addr = 0;
 771                 rxdp->read.pkt_addr = dma_addr;
 772
 773                 rx_packet_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 774                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
 775
 776                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
 777                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
 778                 rxm->nb_segs = 1;
 779                 rxm->next = NULL;
 780                 rxm->pkt_len = rx_packet_len;
 781                 rxm->data_len = rx_packet_len;
 782                 rxm->port = rxq->port_id;
 783                 rxm->ol_flags = 0;
 784                 i40e_rxd_to_vlan_tci(rxm, &rxd);
 785                 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
 786                 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
 787                 rxm->packet_type =
 788                         ptype_tbl[(uint8_t)((qword1 &
 789                         I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT)];
 790                 if (pkt_flags & RTE_MBUF_F_RX_RSS_HASH)
 791                         rxm->hash.rss =
 792                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
 793                 if (pkt_flags & RTE_MBUF_F_RX_FDIR)
 794                         pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
 795
 796 #ifdef RTE_LIBRTE_IEEE1588
 797                 pkt_flags |= i40e_get_iee15888_flags(rxm, qword1);
 798 #endif
 799                 rxm->ol_flags |= pkt_flags;
 800
 801                 rx_pkts[nb_rx++] = rxm;
 802         }
 803         rxq->rx_tail = rx_id;
 804
 805         /**
 806          * If the number of free RX descriptors is greater than the RX free
 807          * threshold of the queue, advance the receive tail register of queue.
 808          * Update that register with the value of the last processed RX
 809          * descriptor minus 1.
 810          */
 811         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
 812         if (nb_hold > rxq->rx_free_thresh) {
 813                 rx_id = (uint16_t) ((rx_id == 0) ?
 814                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
 815                 I40E_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
 816                 nb_hold = 0;
 817         }
 818         rxq->nb_rx_hold = nb_hold;
 819
 820         return nb_rx;
 821 }
 822
 823 uint16_t
 824 i40e_recv_scattered_pkts(void *rx_queue,
 825                          struct rte_mbuf **rx_pkts,
 826                          uint16_t nb_pkts)
 827 {
 828         struct i40e_rx_queue *rxq = rx_queue;
 829         volatile union i40e_rx_desc *rx_ring = rxq->rx_ring;
 830         volatile union i40e_rx_desc *rxdp;
 831         union i40e_rx_desc rxd;
 832         struct i40e_rx_entry *sw_ring = rxq->sw_ring;
 833         struct i40e_rx_entry *rxe;
 834         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
 835         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
 836         struct rte_mbuf *nmb, *rxm;
 837         uint16_t rx_id = rxq->rx_tail;
 838         uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
 839         struct rte_eth_dev *dev;
 840         uint32_t rx_status;
 841         uint64_t qword1;
 842         uint64_t dma_addr;
 843         uint64_t pkt_flags;
 844         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
 845
 846         while (nb_rx < nb_pkts) {
 847                 rxdp = &rx_ring[rx_id];
 848                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 849                 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 850                                         I40E_RXD_QW1_STATUS_SHIFT;
 851
 852                 /* Check the DD bit */
 853                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 854                         break;
 855
 856                 nmb = rte_mbuf_raw_alloc(rxq->mp);
 857                 if (unlikely(!nmb)) {
 858                         dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
 859                         dev->data->rx_mbuf_alloc_failed++;
 860                         break;
 861                 }
 862
 863                 rxd = *rxdp;
 864                 nb_hold++;
 865                 rxe = &sw_ring[rx_id];
 866                 rx_id++;
 867                 if (rx_id == rxq->nb_rx_desc)
 868                         rx_id = 0;
 869
 870                 /* Prefetch next mbuf */
 871                 rte_prefetch0(sw_ring[rx_id].mbuf);
 872
 873                 /**
 874                  * When next RX descriptor is on a cache line boundary,
 875                  * prefetch the next 4 RX descriptors and next 8 pointers
 876                  * to mbufs.
 877                  */
 878                 if ((rx_id & 0x3) == 0) {
 879                         rte_prefetch0(&rx_ring[rx_id]);
 880                         rte_prefetch0(&sw_ring[rx_id]);
 881                 }
 882
 883                 rxm = rxe->mbuf;
 884                 rxe->mbuf = nmb;
 885                 dma_addr =
 886                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
 887
 888                 /* Set data buffer address and data length of the mbuf */
 889                 rxdp->read.hdr_addr = 0;
 890                 rxdp->read.pkt_addr = dma_addr;
 891                 rx_packet_len = (qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 892                                         I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
 893                 rxm->data_len = rx_packet_len;
 894                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
 895
 896                 /**
 897                  * If this is the first buffer of the received packet, set the
 898                  * pointer to the first mbuf of the packet and initialize its
 899                  * context. Otherwise, update the total length and the number
 900                  * of segments of the current scattered packet, and update the
 901                  * pointer to the last mbuf of the current packet.
 902                  */
 903                 if (!first_seg) {
 904                         first_seg = rxm;
 905                         first_seg->nb_segs = 1;
 906                         first_seg->pkt_len = rx_packet_len;
 907                 } else {
 908                         first_seg->pkt_len =
 909                                 (uint16_t)(first_seg->pkt_len +
 910                                                 rx_packet_len);
 911                         first_seg->nb_segs++;
 912                         last_seg->next = rxm;
 913                 }
 914
 915                 /**
 916                  * If this is not the last buffer of the received packet,
 917                  * update the pointer to the last mbuf of the current scattered
 918                  * packet and continue to parse the RX ring.
 919                  */
 920                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT))) {
 921                         last_seg = rxm;
 922                         continue;
 923                 }
 924
 925                 /**
 926                  * This is the last buffer of the received packet. If the CRC
 927                  * is not stripped by the hardware:
 928                  *  - Subtract the CRC length from the total packet length.
 929                  *  - If the last buffer only contains the whole CRC or a part
 930                  *  of it, free the mbuf associated to the last buffer. If part
 931                  *  of the CRC is also contained in the previous mbuf, subtract
 932                  *  the length of that CRC part from the data length of the
 933                  *  previous mbuf.
 934                  */
 935                 rxm->next = NULL;
 936                 if (unlikely(rxq->crc_len > 0)) {
 937                         first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
 938                         if (rx_packet_len <= RTE_ETHER_CRC_LEN) {
 939                                 rte_pktmbuf_free_seg(rxm);
 940                                 first_seg->nb_segs--;
 941                                 last_seg->data_len =
 942                                         (uint16_t)(last_seg->data_len -
 943                                         (RTE_ETHER_CRC_LEN - rx_packet_len));
 944                                 last_seg->next = NULL;
 945                         } else
 946                                 rxm->data_len = (uint16_t)(rx_packet_len -
 947                                                         RTE_ETHER_CRC_LEN);
 948                 }
 949
 950                 first_seg->port = rxq->port_id;
 951                 first_seg->ol_flags = 0;
 952                 i40e_rxd_to_vlan_tci(first_seg, &rxd);
 953                 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
 954                 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
 955                 first_seg->packet_type =
 956                         ptype_tbl[(uint8_t)((qword1 &
 957                         I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT)];
 958                 if (pkt_flags & RTE_MBUF_F_RX_RSS_HASH)
 959                         first_seg->hash.rss =
 960                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
 961                 if (pkt_flags & RTE_MBUF_F_RX_FDIR)
 962                         pkt_flags |= i40e_rxd_build_fdir(&rxd, first_seg);
 963
 964 #ifdef RTE_LIBRTE_IEEE1588
 965                 pkt_flags |= i40e_get_iee15888_flags(first_seg, qword1);
 966 #endif
 967                 first_seg->ol_flags |= pkt_flags;
 968
 969                 /* Prefetch data of first segment, if configured to do so. */
 970                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
 971                         first_seg->data_off));
 972                 rx_pkts[nb_rx++] = first_seg;
 973                 first_seg = NULL;
 974         }
 975
 976         /* Record index of the next RX descriptor to probe. */
 977         rxq->rx_tail = rx_id;
 978         rxq->pkt_first_seg = first_seg;
 979         rxq->pkt_last_seg = last_seg;
 980
 981         /**
 982          * If the number of free RX descriptors is greater than the RX free
 983          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
 984          * register. Update the RDT with the value of the last processed RX
 985          * descriptor minus 1, to guarantee that the RDT register is never
 986          * equal to the RDH register, which creates a "full" ring situtation
 987          * from the hardware point of view.
 988          */
 989         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
 990         if (nb_hold > rxq->rx_free_thresh) {
 991                 rx_id = (uint16_t)(rx_id == 0 ?
 992                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
 993                 I40E_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
 994                 nb_hold = 0;
 995         }
 996         rxq->nb_rx_hold = nb_hold;
 997
 998         return nb_rx;
 999 }
1000
1001 /* Check if the context descriptor is needed for TX offloading */
1002 static inline uint16_t
1003 i40e_calc_context_desc(uint64_t flags)
1004 {
1005         static uint64_t mask = RTE_MBUF_F_TX_OUTER_IP_CKSUM |
1006                 RTE_MBUF_F_TX_TCP_SEG |
1007                 RTE_MBUF_F_TX_QINQ |
1008                 RTE_MBUF_F_TX_TUNNEL_MASK;
1009
1010 #ifdef RTE_LIBRTE_IEEE1588
1011         mask |= RTE_MBUF_F_TX_IEEE1588_TMST;
1012 #endif
1013
1014         return (flags & mask) ? 1 : 0;
1015 }
1016
1017 /* set i40e TSO context descriptor */
1018 static inline uint64_t
1019 i40e_set_tso_ctx(struct rte_mbuf *mbuf, union i40e_tx_offload tx_offload)
1020 {
1021         uint64_t ctx_desc = 0;
1022         uint32_t cd_cmd, hdr_len, cd_tso_len;
1023
1024         if (!tx_offload.l4_len) {
1025                 PMD_DRV_LOG(DEBUG, "L4 length set to 0");
1026                 return ctx_desc;
1027         }
1028
1029         hdr_len = tx_offload.l2_len + tx_offload.l3_len + tx_offload.l4_len;
1030         hdr_len += (mbuf->ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK) ?
1031                    tx_offload.outer_l2_len + tx_offload.outer_l3_len : 0;
1032
1033         cd_cmd = I40E_TX_CTX_DESC_TSO;
1034         cd_tso_len = mbuf->pkt_len - hdr_len;
1035         ctx_desc |= ((uint64_t)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
1036                 ((uint64_t)cd_tso_len <<
1037                  I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1038                 ((uint64_t)mbuf->tso_segsz <<
1039                  I40E_TXD_CTX_QW1_MSS_SHIFT);
1040
1041         return ctx_desc;
1042 }
1043
1044 /* HW requires that Tx buffer size ranges from 1B up to (16K-1)B. */
1045 #define I40E_MAX_DATA_PER_TXD \
1046         (I40E_TXD_QW1_TX_BUF_SZ_MASK >> I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
1047 /* Calculate the number of TX descriptors needed for each pkt */
1048 static inline uint16_t
1049 i40e_calc_pkt_desc(struct rte_mbuf *tx_pkt)
1050 {
1051         struct rte_mbuf *txd = tx_pkt;
1052         uint16_t count = 0;
1053
1054         while (txd != NULL) {
1055                 count += DIV_ROUND_UP(txd->data_len, I40E_MAX_DATA_PER_TXD);
1056                 txd = txd->next;
1057         }
1058
1059         return count;
1060 }
1061
1062 uint16_t
1063 i40e_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1064 {
1065         struct i40e_tx_queue *txq;
1066         struct i40e_tx_entry *sw_ring;
1067         struct i40e_tx_entry *txe, *txn;
1068         volatile struct i40e_tx_desc *txd;
1069         volatile struct i40e_tx_desc *txr;
1070         struct rte_mbuf *tx_pkt;
1071         struct rte_mbuf *m_seg;
1072         uint32_t cd_tunneling_params;
1073         uint16_t tx_id;
1074         uint16_t nb_tx;
1075         uint32_t td_cmd;
1076         uint32_t td_offset;
1077         uint32_t td_tag;
1078         uint64_t ol_flags;
1079         uint16_t nb_used;
1080         uint16_t nb_ctx;
1081         uint16_t tx_last;
1082         uint16_t slen;
1083         uint64_t buf_dma_addr;
1084         union i40e_tx_offload tx_offload = {0};
1085
1086         txq = tx_queue;
1087         sw_ring = txq->sw_ring;
1088         txr = txq->tx_ring;
1089         tx_id = txq->tx_tail;
1090         txe = &sw_ring[tx_id];
1091
1092         /* Check if the descriptor ring needs to be cleaned. */
1093         if (txq->nb_tx_free < txq->tx_free_thresh)
1094                 (void)i40e_xmit_cleanup(txq);
1095
1096         for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1097                 td_cmd = 0;
1098                 td_tag = 0;
1099                 td_offset = 0;
1100
1101                 tx_pkt = *tx_pkts++;
1102                 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
1103
1104                 ol_flags = tx_pkt->ol_flags;
1105                 tx_offload.l2_len = tx_pkt->l2_len;
1106                 tx_offload.l3_len = tx_pkt->l3_len;
1107                 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
1108                 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
1109                 tx_offload.l4_len = tx_pkt->l4_len;
1110                 tx_offload.tso_segsz = tx_pkt->tso_segsz;
1111
1112                 /* Calculate the number of context descriptors needed. */
1113                 nb_ctx = i40e_calc_context_desc(ol_flags);
1114
1115                 /**
1116                  * The number of descriptors that must be allocated for
1117                  * a packet equals to the number of the segments of that
1118                  * packet plus 1 context descriptor if needed.
1119                  * Recalculate the needed tx descs when TSO enabled in case
1120                  * the mbuf data size exceeds max data size that hw allows
1121                  * per tx desc.
1122                  */
1123                 if (ol_flags & RTE_MBUF_F_TX_TCP_SEG)
1124                         nb_used = (uint16_t)(i40e_calc_pkt_desc(tx_pkt) +
1125                                              nb_ctx);
1126                 else
1127                         nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
1128                 tx_last = (uint16_t)(tx_id + nb_used - 1);
1129
1130                 /* Circular ring */
1131                 if (tx_last >= txq->nb_tx_desc)
1132                         tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
1133
1134                 if (nb_used > txq->nb_tx_free) {
1135                         if (i40e_xmit_cleanup(txq) != 0) {
1136                                 if (nb_tx == 0)
1137                                         return 0;
1138                                 goto end_of_tx;
1139                         }
1140                         if (unlikely(nb_used > txq->tx_rs_thresh)) {
1141                                 while (nb_used > txq->nb_tx_free) {
1142                                         if (i40e_xmit_cleanup(txq) != 0) {
1143                                                 if (nb_tx == 0)
1144                                                         return 0;
1145                                                 goto end_of_tx;
1146                                         }
1147                                 }
1148                         }
1149                 }
1150
1151                 /* Descriptor based VLAN insertion */
1152                 if (ol_flags & (RTE_MBUF_F_TX_VLAN | RTE_MBUF_F_TX_QINQ)) {
1153                         td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1154                         td_tag = tx_pkt->vlan_tci;
1155                 }
1156
1157                 /* Always enable CRC offload insertion */
1158                 td_cmd |= I40E_TX_DESC_CMD_ICRC;
1159
1160                 /* Fill in tunneling parameters if necessary */
1161                 cd_tunneling_params = 0;
1162                 if (ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK)
1163                         i40e_parse_tunneling_params(ol_flags, tx_offload,
1164                                                     &cd_tunneling_params);
1165                 /* Enable checksum offloading */
1166                 if (ol_flags & I40E_TX_CKSUM_OFFLOAD_MASK)
1167                         i40e_txd_enable_checksum(ol_flags, &td_cmd,
1168                                                  &td_offset, tx_offload);
1169
1170                 if (nb_ctx) {
1171                         /* Setup TX context descriptor if required */
1172                         volatile struct i40e_tx_context_desc *ctx_txd =
1173                                 (volatile struct i40e_tx_context_desc *)\
1174                                                         &txr[tx_id];
1175                         uint16_t cd_l2tag2 = 0;
1176                         uint64_t cd_type_cmd_tso_mss =
1177                                 I40E_TX_DESC_DTYPE_CONTEXT;
1178
1179                         txn = &sw_ring[txe->next_id];
1180                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
1181                         if (txe->mbuf != NULL) {
1182                                 rte_pktmbuf_free_seg(txe->mbuf);
1183                                 txe->mbuf = NULL;
1184                         }
1185
1186                         /* TSO enabled means no timestamp */
1187                         if (ol_flags & RTE_MBUF_F_TX_TCP_SEG)
1188                                 cd_type_cmd_tso_mss |=
1189                                         i40e_set_tso_ctx(tx_pkt, tx_offload);
1190                         else {
1191 #ifdef RTE_LIBRTE_IEEE1588
1192                                 if (ol_flags & RTE_MBUF_F_TX_IEEE1588_TMST)
1193                                         cd_type_cmd_tso_mss |=
1194                                                 ((uint64_t)I40E_TX_CTX_DESC_TSYN <<
1195                                                  I40E_TXD_CTX_QW1_CMD_SHIFT);
1196 #endif
1197                         }
1198
1199                         ctx_txd->tunneling_params =
1200                                 rte_cpu_to_le_32(cd_tunneling_params);
1201                         if (ol_flags & RTE_MBUF_F_TX_QINQ) {
1202                                 cd_l2tag2 = tx_pkt->vlan_tci_outer;
1203                                 cd_type_cmd_tso_mss |=
1204                                         ((uint64_t)I40E_TX_CTX_DESC_IL2TAG2 <<
1205                                                 I40E_TXD_CTX_QW1_CMD_SHIFT);
1206                         }
1207                         ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
1208                         ctx_txd->type_cmd_tso_mss =
1209                                 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
1210
1211                         PMD_TX_LOG(DEBUG, "mbuf: %p, TCD[%u]:\n"
1212                                 "tunneling_params: %#x;\n"
1213                                 "l2tag2: %#hx;\n"
1214                                 "rsvd: %#hx;\n"
1215                                 "type_cmd_tso_mss: %#"PRIx64";\n",
1216                                 tx_pkt, tx_id,
1217                                 ctx_txd->tunneling_params,
1218                                 ctx_txd->l2tag2,
1219                                 ctx_txd->rsvd,
1220                                 ctx_txd->type_cmd_tso_mss);
1221
1222                         txe->last_id = tx_last;
1223                         tx_id = txe->next_id;
1224                         txe = txn;
1225                 }
1226
1227                 m_seg = tx_pkt;
1228                 do {
1229                         txd = &txr[tx_id];
1230                         txn = &sw_ring[txe->next_id];
1231
1232                         if (txe->mbuf)
1233                                 rte_pktmbuf_free_seg(txe->mbuf);
1234                         txe->mbuf = m_seg;
1235
1236                         /* Setup TX Descriptor */
1237                         slen = m_seg->data_len;
1238                         buf_dma_addr = rte_mbuf_data_iova(m_seg);
1239
1240                         while ((ol_flags & RTE_MBUF_F_TX_TCP_SEG) &&
1241                                 unlikely(slen > I40E_MAX_DATA_PER_TXD)) {
1242                                 txd->buffer_addr =
1243                                         rte_cpu_to_le_64(buf_dma_addr);
1244                                 txd->cmd_type_offset_bsz =
1245                                         i40e_build_ctob(td_cmd,
1246                                         td_offset, I40E_MAX_DATA_PER_TXD,
1247                                         td_tag);
1248
1249                                 buf_dma_addr += I40E_MAX_DATA_PER_TXD;
1250                                 slen -= I40E_MAX_DATA_PER_TXD;
1251
1252                                 txe->last_id = tx_last;
1253                                 tx_id = txe->next_id;
1254                                 txe = txn;
1255                                 txd = &txr[tx_id];
1256                                 txn = &sw_ring[txe->next_id];
1257                         }
1258                         PMD_TX_LOG(DEBUG, "mbuf: %p, TDD[%u]:\n"
1259                                 "buf_dma_addr: %#"PRIx64";\n"
1260                                 "td_cmd: %#x;\n"
1261                                 "td_offset: %#x;\n"
1262                                 "td_len: %u;\n"
1263                                 "td_tag: %#x;\n",
1264                                 tx_pkt, tx_id, buf_dma_addr,
1265                                 td_cmd, td_offset, slen, td_tag);
1266
1267                         txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
1268                         txd->cmd_type_offset_bsz = i40e_build_ctob(td_cmd,
1269                                                 td_offset, slen, td_tag);
1270                         txe->last_id = tx_last;
1271                         tx_id = txe->next_id;
1272                         txe = txn;
1273                         m_seg = m_seg->next;
1274                 } while (m_seg != NULL);
1275
1276                 /* The last packet data descriptor needs End Of Packet (EOP) */
1277                 td_cmd |= I40E_TX_DESC_CMD_EOP;
1278                 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
1279                 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
1280
1281                 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
1282                         PMD_TX_LOG(DEBUG,
1283                                    "Setting RS bit on TXD id="
1284                                    "%4u (port=%d queue=%d)",
1285                                    tx_last, txq->port_id, txq->queue_id);
1286
1287                         td_cmd |= I40E_TX_DESC_CMD_RS;
1288
1289                         /* Update txq RS bit counters */
1290                         txq->nb_tx_used = 0;
1291                 }
1292
1293                 txd->cmd_type_offset_bsz |=
1294                         rte_cpu_to_le_64(((uint64_t)td_cmd) <<
1295                                         I40E_TXD_QW1_CMD_SHIFT);
1296         }
1297
1298 end_of_tx:
1299         PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
1300                    (unsigned) txq->port_id, (unsigned) txq->queue_id,
1301                    (unsigned) tx_id, (unsigned) nb_tx);
1302
1303         rte_io_wmb();
1304         I40E_PCI_REG_WC_WRITE_RELAXED(txq->qtx_tail, tx_id);
1305         txq->tx_tail = tx_id;
1306
1307         return nb_tx;
1308 }
1309
1310 static __rte_always_inline int
1311 i40e_tx_free_bufs(struct i40e_tx_queue *txq)
1312 {
1313         struct i40e_tx_entry *txep;
1314         uint16_t tx_rs_thresh = txq->tx_rs_thresh;
1315         uint16_t i = 0, j = 0;
1316         struct rte_mbuf *free[RTE_I40E_TX_MAX_FREE_BUF_SZ];
1317         const uint16_t k = RTE_ALIGN_FLOOR(tx_rs_thresh, RTE_I40E_TX_MAX_FREE_BUF_SZ);
1318         const uint16_t m = tx_rs_thresh % RTE_I40E_TX_MAX_FREE_BUF_SZ;
1319
1320         if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
1321                         rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
1322                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
1323                 return 0;
1324
1325         txep = &txq->sw_ring[txq->tx_next_dd - (tx_rs_thresh - 1)];
1326
1327         for (i = 0; i < tx_rs_thresh; i++)
1328                 rte_prefetch0((txep + i)->mbuf);
1329
1330         if (txq->offloads & RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE) {
1331                 if (k) {
1332                         for (j = 0; j != k; j += RTE_I40E_TX_MAX_FREE_BUF_SZ) {
1333                                 for (i = 0; i < RTE_I40E_TX_MAX_FREE_BUF_SZ; ++i, ++txep) {
1334                                         free[i] = txep->mbuf;
1335                                         txep->mbuf = NULL;
1336                                 }
1337                                 rte_mempool_put_bulk(free[0]->pool, (void **)free,
1338                                                 RTE_I40E_TX_MAX_FREE_BUF_SZ);
1339                         }
1340                 }
1341
1342                 if (m) {
1343                         for (i = 0; i < m; ++i, ++txep) {
1344                                 free[i] = txep->mbuf;
1345                                 txep->mbuf = NULL;
1346                         }
1347                         rte_mempool_put_bulk(free[0]->pool, (void **)free, m);
1348                 }
1349         } else {
1350                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1351                         rte_pktmbuf_free_seg(txep->mbuf);
1352                         txep->mbuf = NULL;
1353                 }
1354         }
1355
1356         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
1357         txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
1358         if (txq->tx_next_dd >= txq->nb_tx_desc)
1359                 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1360
1361         return txq->tx_rs_thresh;
1362 }
1363
1364 /* Populate 4 descriptors with data from 4 mbufs */
1365 static inline void
1366 tx4(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1367 {
1368         uint64_t dma_addr;
1369         uint32_t i;
1370
1371         for (i = 0; i < 4; i++, txdp++, pkts++) {
1372                 dma_addr = rte_mbuf_data_iova(*pkts);
1373                 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1374                 txdp->cmd_type_offset_bsz =
1375                         i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1376                                         (*pkts)->data_len, 0);
1377         }
1378 }
1379
1380 /* Populate 1 descriptor with data from 1 mbuf */
1381 static inline void
1382 tx1(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1383 {
1384         uint64_t dma_addr;
1385
1386         dma_addr = rte_mbuf_data_iova(*pkts);
1387         txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1388         txdp->cmd_type_offset_bsz =
1389                 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1390                                 (*pkts)->data_len, 0);
1391 }
1392
1393 /* Fill hardware descriptor ring with mbuf data */
1394 static inline void
1395 i40e_tx_fill_hw_ring(struct i40e_tx_queue *txq,
1396                      struct rte_mbuf **pkts,
1397                      uint16_t nb_pkts)
1398 {
1399         volatile struct i40e_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
1400         struct i40e_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
1401         const int N_PER_LOOP = 4;
1402         const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
1403         int mainpart, leftover;
1404         int i, j;
1405
1406         mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
1407         leftover = (nb_pkts & ((uint32_t)  N_PER_LOOP_MASK));
1408         for (i = 0; i < mainpart; i += N_PER_LOOP) {
1409                 for (j = 0; j < N_PER_LOOP; ++j) {
1410                         (txep + i + j)->mbuf = *(pkts + i + j);
1411                 }
1412                 tx4(txdp + i, pkts + i);
1413         }
1414         if (unlikely(leftover > 0)) {
1415                 for (i = 0; i < leftover; ++i) {
1416                         (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
1417                         tx1(txdp + mainpart + i, pkts + mainpart + i);
1418                 }
1419         }
1420 }
1421
1422 static inline uint16_t
1423 tx_xmit_pkts(struct i40e_tx_queue *txq,
1424              struct rte_mbuf **tx_pkts,
1425              uint16_t nb_pkts)
1426 {
1427         volatile struct i40e_tx_desc *txr = txq->tx_ring;
1428         uint16_t n = 0;
1429
1430         /**
1431          * Begin scanning the H/W ring for done descriptors when the number
1432          * of available descriptors drops below tx_free_thresh. For each done
1433          * descriptor, free the associated buffer.
1434          */
1435         if (txq->nb_tx_free < txq->tx_free_thresh)
1436                 i40e_tx_free_bufs(txq);
1437
1438         /* Use available descriptor only */
1439         nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
1440         if (unlikely(!nb_pkts))
1441                 return 0;
1442
1443         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
1444         if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
1445                 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
1446                 i40e_tx_fill_hw_ring(txq, tx_pkts, n);
1447                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1448                         rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1449                                                 I40E_TXD_QW1_CMD_SHIFT);
1450                 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1451                 txq->tx_tail = 0;
1452         }
1453
1454         /* Fill hardware descriptor ring with mbuf data */
1455         i40e_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
1456         txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
1457
1458         /* Determin if RS bit needs to be set */
1459         if (txq->tx_tail > txq->tx_next_rs) {
1460                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1461                         rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1462                                                 I40E_TXD_QW1_CMD_SHIFT);
1463                 txq->tx_next_rs =
1464                         (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
1465                 if (txq->tx_next_rs >= txq->nb_tx_desc)
1466                         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1467         }
1468
1469         if (txq->tx_tail >= txq->nb_tx_desc)
1470                 txq->tx_tail = 0;
1471
1472         /* Update the tx tail register */
1473         I40E_PCI_REG_WC_WRITE(txq->qtx_tail, txq->tx_tail);
1474
1475         return nb_pkts;
1476 }
1477
1478 static uint16_t
1479 i40e_xmit_pkts_simple(void *tx_queue,
1480                       struct rte_mbuf **tx_pkts,
1481                       uint16_t nb_pkts)
1482 {
1483         uint16_t nb_tx = 0;
1484
1485         if (likely(nb_pkts <= I40E_TX_MAX_BURST))
1486                 return tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1487                                                 tx_pkts, nb_pkts);
1488
1489         while (nb_pkts) {
1490                 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
1491                                                 I40E_TX_MAX_BURST);
1492
1493                 ret = tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1494                                                 &tx_pkts[nb_tx], num);
1495                 nb_tx = (uint16_t)(nb_tx + ret);
1496                 nb_pkts = (uint16_t)(nb_pkts - ret);
1497                 if (ret < num)
1498                         break;
1499         }
1500
1501         return nb_tx;
1502 }
1503
1504 static uint16_t
1505 i40e_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
1506                    uint16_t nb_pkts)
1507 {
1508         uint16_t nb_tx = 0;
1509         struct i40e_tx_queue *txq = (struct i40e_tx_queue *)tx_queue;
1510
1511         while (nb_pkts) {
1512                 uint16_t ret, num;
1513
1514                 num = (uint16_t)RTE_MIN(nb_pkts, txq->tx_rs_thresh);
1515                 ret = i40e_xmit_fixed_burst_vec(tx_queue, &tx_pkts[nb_tx],
1516                                                 num);
1517                 nb_tx += ret;
1518                 nb_pkts -= ret;
1519                 if (ret < num)
1520                         break;
1521         }
1522
1523         return nb_tx;
1524 }
1525
1526 /*********************************************************************
1527  *
1528  *  TX simple prep functions
1529  *
1530  **********************************************************************/
1531 uint16_t
1532 i40e_simple_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
1533                       uint16_t nb_pkts)
1534 {
1535         int i;
1536         uint64_t ol_flags;
1537         struct rte_mbuf *m;
1538
1539         for (i = 0; i < nb_pkts; i++) {
1540                 m = tx_pkts[i];
1541                 ol_flags = m->ol_flags;
1542
1543                 if (m->nb_segs != 1) {
1544                         rte_errno = EINVAL;
1545                         return i;
1546                 }
1547
1548                 if (ol_flags & I40E_TX_OFFLOAD_SIMPLE_NOTSUP_MASK) {
1549                         rte_errno = ENOTSUP;
1550                         return i;
1551                 }
1552
1553                 /* check the size of packet */
1554                 if (m->pkt_len < I40E_TX_MIN_PKT_LEN ||
1555                     m->pkt_len > I40E_FRAME_SIZE_MAX) {
1556                         rte_errno = EINVAL;
1557                         return i;
1558                 }
1559         }
1560         return i;
1561 }
1562
1563 /*********************************************************************
1564  *
1565  *  TX prep functions
1566  *
1567  **********************************************************************/
1568 uint16_t
1569 i40e_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
1570                 uint16_t nb_pkts)
1571 {
1572         int i, ret;
1573         uint64_t ol_flags;
1574         struct rte_mbuf *m;
1575
1576         for (i = 0; i < nb_pkts; i++) {
1577                 m = tx_pkts[i];
1578                 ol_flags = m->ol_flags;
1579
1580                 /* Check for m->nb_segs to not exceed the limits. */
1581                 if (!(ol_flags & RTE_MBUF_F_TX_TCP_SEG)) {
1582                         if (m->nb_segs > I40E_TX_MAX_MTU_SEG ||
1583                             m->pkt_len > I40E_FRAME_SIZE_MAX) {
1584                                 rte_errno = EINVAL;
1585                                 return i;
1586                         }
1587                 } else if (m->nb_segs > I40E_TX_MAX_SEG ||
1588                            m->tso_segsz < I40E_MIN_TSO_MSS ||
1589                            m->tso_segsz > I40E_MAX_TSO_MSS ||
1590                            m->pkt_len > I40E_TSO_FRAME_SIZE_MAX) {
1591                         /* MSS outside the range (256B - 9674B) are considered
1592                          * malicious
1593                          */
1594                         rte_errno = EINVAL;
1595                         return i;
1596                 }
1597
1598                 if (ol_flags & I40E_TX_OFFLOAD_NOTSUP_MASK) {
1599                         rte_errno = ENOTSUP;
1600                         return i;
1601                 }
1602
1603                 /* check the size of packet */
1604                 if (m->pkt_len < I40E_TX_MIN_PKT_LEN) {
1605                         rte_errno = EINVAL;
1606                         return i;
1607                 }
1608
1609 #ifdef RTE_ETHDEV_DEBUG_TX
1610                 ret = rte_validate_tx_offload(m);
1611                 if (ret != 0) {
1612                         rte_errno = -ret;
1613                         return i;
1614                 }
1615 #endif
1616                 ret = rte_net_intel_cksum_prepare(m);
1617                 if (ret != 0) {
1618                         rte_errno = -ret;
1619                         return i;
1620                 }
1621         }
1622         return i;
1623 }
1624
1625 /*
1626  * Find the VSI the queue belongs to. 'queue_idx' is the queue index
1627  * application used, which assume having sequential ones. But from driver's
1628  * perspective, it's different. For example, q0 belongs to FDIR VSI, q1-q64
1629  * to MAIN VSI, , q65-96 to SRIOV VSIs, q97-128 to VMDQ VSIs. For application
1630  * running on host, q1-64 and q97-128 can be used, total 96 queues. They can
1631  * use queue_idx from 0 to 95 to access queues, while real queue would be
1632  * different. This function will do a queue mapping to find VSI the queue
1633  * belongs to.
1634  */
1635 static struct i40e_vsi*
1636 i40e_pf_get_vsi_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1637 {
1638         /* the queue in MAIN VSI range */
1639         if (queue_idx < pf->main_vsi->nb_qps)
1640                 return pf->main_vsi;
1641
1642         queue_idx -= pf->main_vsi->nb_qps;
1643
1644         /* queue_idx is greater than VMDQ VSIs range */
1645         if (queue_idx > pf->nb_cfg_vmdq_vsi * pf->vmdq_nb_qps - 1) {
1646                 PMD_INIT_LOG(ERR, "queue_idx out of range. VMDQ configured?");
1647                 return NULL;
1648         }
1649
1650         return pf->vmdq[queue_idx / pf->vmdq_nb_qps].vsi;
1651 }
1652
1653 static uint16_t
1654 i40e_get_queue_offset_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1655 {
1656         /* the queue in MAIN VSI range */
1657         if (queue_idx < pf->main_vsi->nb_qps)
1658                 return queue_idx;
1659
1660         /* It's VMDQ queues */
1661         queue_idx -= pf->main_vsi->nb_qps;
1662
1663         if (pf->nb_cfg_vmdq_vsi)
1664                 return queue_idx % pf->vmdq_nb_qps;
1665         else {
1666                 PMD_INIT_LOG(ERR, "Fail to get queue offset");
1667                 return (uint16_t)(-1);
1668         }
1669 }
1670
1671 int
1672 i40e_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1673 {
1674         struct i40e_rx_queue *rxq;
1675         int err;
1676         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1677
1678         PMD_INIT_FUNC_TRACE();
1679
1680         rxq = dev->data->rx_queues[rx_queue_id];
1681         if (!rxq || !rxq->q_set) {
1682                 PMD_DRV_LOG(ERR, "RX queue %u not available or setup",
1683                             rx_queue_id);
1684                 return -EINVAL;
1685         }
1686
1687         if (rxq->rx_deferred_start)
1688                 PMD_DRV_LOG(WARNING, "RX queue %u is deferrd start",
1689                             rx_queue_id);
1690
1691         err = i40e_alloc_rx_queue_mbufs(rxq);
1692         if (err) {
1693                 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1694                 return err;
1695         }
1696
1697         /* Init the RX tail regieter. */
1698         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1699
1700         err = i40e_switch_rx_queue(hw, rxq->reg_idx, TRUE);
1701         if (err) {
1702                 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1703                             rx_queue_id);
1704
1705                 i40e_rx_queue_release_mbufs(rxq);
1706                 i40e_reset_rx_queue(rxq);
1707                 return err;
1708         }
1709         dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1710
1711         return 0;
1712 }
1713
1714 int
1715 i40e_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1716 {
1717         struct i40e_rx_queue *rxq;
1718         int err;
1719         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1720
1721         rxq = dev->data->rx_queues[rx_queue_id];
1722         if (!rxq || !rxq->q_set) {
1723                 PMD_DRV_LOG(ERR, "RX queue %u not available or setup",
1724                                 rx_queue_id);
1725                 return -EINVAL;
1726         }
1727
1728         /*
1729          * rx_queue_id is queue id application refers to, while
1730          * rxq->reg_idx is the real queue index.
1731          */
1732         err = i40e_switch_rx_queue(hw, rxq->reg_idx, FALSE);
1733         if (err) {
1734                 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1735                             rx_queue_id);
1736                 return err;
1737         }
1738         i40e_rx_queue_release_mbufs(rxq);
1739         i40e_reset_rx_queue(rxq);
1740         dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1741
1742         return 0;
1743 }
1744
1745 int
1746 i40e_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1747 {
1748         int err;
1749         struct i40e_tx_queue *txq;
1750         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1751
1752         PMD_INIT_FUNC_TRACE();
1753
1754         txq = dev->data->tx_queues[tx_queue_id];
1755         if (!txq || !txq->q_set) {
1756                 PMD_DRV_LOG(ERR, "TX queue %u is not available or setup",
1757                             tx_queue_id);
1758                 return -EINVAL;
1759         }
1760
1761         if (txq->tx_deferred_start)
1762                 PMD_DRV_LOG(WARNING, "TX queue %u is deferrd start",
1763                             tx_queue_id);
1764
1765         /*
1766          * tx_queue_id is queue id application refers to, while
1767          * rxq->reg_idx is the real queue index.
1768          */
1769         err = i40e_switch_tx_queue(hw, txq->reg_idx, TRUE);
1770         if (err) {
1771                 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1772                             tx_queue_id);
1773                 return err;
1774         }
1775         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1776
1777         return 0;
1778 }
1779
1780 int
1781 i40e_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1782 {
1783         struct i40e_tx_queue *txq;
1784         int err;
1785         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1786
1787         txq = dev->data->tx_queues[tx_queue_id];
1788         if (!txq || !txq->q_set) {
1789                 PMD_DRV_LOG(ERR, "TX queue %u is not available or setup",
1790                         tx_queue_id);
1791                 return -EINVAL;
1792         }
1793
1794         /*
1795          * tx_queue_id is queue id application refers to, while
1796          * txq->reg_idx is the real queue index.
1797          */
1798         err = i40e_switch_tx_queue(hw, txq->reg_idx, FALSE);
1799         if (err) {
1800                 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u of",
1801                             tx_queue_id);
1802                 return err;
1803         }
1804
1805         i40e_tx_queue_release_mbufs(txq);
1806         i40e_reset_tx_queue(txq);
1807         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1808
1809         return 0;
1810 }
1811
1812 const uint32_t *
1813 i40e_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1814 {
1815         static const uint32_t ptypes[] = {
1816                 /* refers to i40e_rxd_pkt_type_mapping() */
1817                 RTE_PTYPE_L2_ETHER,
1818                 RTE_PTYPE_L2_ETHER_TIMESYNC,
1819                 RTE_PTYPE_L2_ETHER_LLDP,
1820                 RTE_PTYPE_L2_ETHER_ARP,
1821                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1822                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
1823                 RTE_PTYPE_L4_FRAG,
1824                 RTE_PTYPE_L4_ICMP,
1825                 RTE_PTYPE_L4_NONFRAG,
1826                 RTE_PTYPE_L4_SCTP,
1827                 RTE_PTYPE_L4_TCP,
1828                 RTE_PTYPE_L4_UDP,
1829                 RTE_PTYPE_TUNNEL_GRENAT,
1830                 RTE_PTYPE_TUNNEL_IP,
1831                 RTE_PTYPE_INNER_L2_ETHER,
1832                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1833                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
1834                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
1835                 RTE_PTYPE_INNER_L4_FRAG,
1836                 RTE_PTYPE_INNER_L4_ICMP,
1837                 RTE_PTYPE_INNER_L4_NONFRAG,
1838                 RTE_PTYPE_INNER_L4_SCTP,
1839                 RTE_PTYPE_INNER_L4_TCP,
1840                 RTE_PTYPE_INNER_L4_UDP,
1841                 RTE_PTYPE_UNKNOWN
1842         };
1843
1844         if (dev->rx_pkt_burst == i40e_recv_pkts ||
1845 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1846             dev->rx_pkt_burst == i40e_recv_pkts_bulk_alloc ||
1847 #endif
1848             dev->rx_pkt_burst == i40e_recv_scattered_pkts ||
1849             dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
1850             dev->rx_pkt_burst == i40e_recv_pkts_vec ||
1851 #ifdef CC_AVX512_SUPPORT
1852             dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec_avx512 ||
1853             dev->rx_pkt_burst == i40e_recv_pkts_vec_avx512 ||
1854 #endif
1855             dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec_avx2 ||
1856             dev->rx_pkt_burst == i40e_recv_pkts_vec_avx2)
1857                 return ptypes;
1858         return NULL;
1859 }
1860
1861 static int
1862 i40e_dev_first_queue(uint16_t idx, void **queues, int num)
1863 {
1864         uint16_t i;
1865
1866         for (i = 0; i < num; i++) {
1867                 if (i != idx && queues[i])
1868                         return 0;
1869         }
1870
1871         return 1;
1872 }
1873
1874 static int
1875 i40e_dev_rx_queue_setup_runtime(struct rte_eth_dev *dev,
1876                                 struct i40e_rx_queue *rxq)
1877 {
1878         struct i40e_adapter *ad =
1879                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1880         int use_def_burst_func =
1881                 check_rx_burst_bulk_alloc_preconditions(rxq);
1882         uint16_t buf_size =
1883                 (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
1884                            RTE_PKTMBUF_HEADROOM);
1885         int use_scattered_rx =
1886                 (rxq->max_pkt_len > buf_size);
1887
1888         if (i40e_rx_queue_init(rxq) != I40E_SUCCESS) {
1889                 PMD_DRV_LOG(ERR,
1890                             "Failed to do RX queue initialization");
1891                 return -EINVAL;
1892         }
1893
1894         if (i40e_dev_first_queue(rxq->queue_id,
1895                                  dev->data->rx_queues,
1896                                  dev->data->nb_rx_queues)) {
1897                 /**
1898                  * If it is the first queue to setup,
1899                  * set all flags to default and call
1900                  * i40e_set_rx_function.
1901                  */
1902                 ad->rx_bulk_alloc_allowed = true;
1903                 ad->rx_vec_allowed = true;
1904                 dev->data->scattered_rx = use_scattered_rx;
1905                 if (use_def_burst_func)
1906                         ad->rx_bulk_alloc_allowed = false;
1907                 i40e_set_rx_function(dev);
1908                 return 0;
1909         } else if (ad->rx_vec_allowed && !rte_is_power_of_2(rxq->nb_rx_desc)) {
1910                 PMD_DRV_LOG(ERR, "Vector mode is allowed, but descriptor"
1911                             " number %d of queue %d isn't power of 2",
1912                             rxq->nb_rx_desc, rxq->queue_id);
1913                 return -EINVAL;
1914         }
1915
1916         /* check bulk alloc conflict */
1917         if (ad->rx_bulk_alloc_allowed && use_def_burst_func) {
1918                 PMD_DRV_LOG(ERR, "Can't use default burst.");
1919                 return -EINVAL;
1920         }
1921         /* check scatterred conflict */
1922         if (!dev->data->scattered_rx && use_scattered_rx) {
1923                 PMD_DRV_LOG(ERR, "Scattered rx is required.");
1924                 return -EINVAL;
1925         }
1926         /* check vector conflict */
1927         if (ad->rx_vec_allowed && i40e_rxq_vec_setup(rxq)) {
1928                 PMD_DRV_LOG(ERR, "Failed vector rx setup.");
1929                 return -EINVAL;
1930         }
1931
1932         return 0;
1933 }
1934
1935 int
1936 i40e_dev_rx_queue_setup(struct rte_eth_dev *dev,
1937                         uint16_t queue_idx,
1938                         uint16_t nb_desc,
1939                         unsigned int socket_id,
1940                         const struct rte_eth_rxconf *rx_conf,
1941                         struct rte_mempool *mp)
1942 {
1943         struct i40e_adapter *ad =
1944                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1945         struct i40e_vsi *vsi;
1946         struct i40e_pf *pf = NULL;
1947         struct i40e_rx_queue *rxq;
1948         const struct rte_memzone *rz;
1949         uint32_t ring_size;
1950         uint16_t len, i;
1951         uint16_t reg_idx, base, bsf, tc_mapping;
1952         int q_offset, use_def_burst_func = 1;
1953         uint64_t offloads;
1954
1955         offloads = rx_conf->offloads | dev->data->dev_conf.rxmode.offloads;
1956
1957         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1958         vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
1959         if (!vsi)
1960                 return -EINVAL;
1961         q_offset = i40e_get_queue_offset_by_qindex(pf, queue_idx);
1962         if (q_offset < 0)
1963                 return -EINVAL;
1964         reg_idx = vsi->base_queue + q_offset;
1965
1966         if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
1967             (nb_desc > I40E_MAX_RING_DESC) ||
1968             (nb_desc < I40E_MIN_RING_DESC)) {
1969                 PMD_DRV_LOG(ERR, "Number (%u) of receive descriptors is "
1970                             "invalid", nb_desc);
1971                 return -EINVAL;
1972         }
1973
1974         /* Free memory if needed */
1975         if (dev->data->rx_queues[queue_idx]) {
1976                 i40e_rx_queue_release(dev->data->rx_queues[queue_idx]);
1977                 dev->data->rx_queues[queue_idx] = NULL;
1978         }
1979
1980         /* Allocate the rx queue data structure */
1981         rxq = rte_zmalloc_socket("i40e rx queue",
1982                                  sizeof(struct i40e_rx_queue),
1983                                  RTE_CACHE_LINE_SIZE,
1984                                  socket_id);
1985         if (!rxq) {
1986                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
1987                             "rx queue data structure");
1988                 return -ENOMEM;
1989         }
1990         rxq->mp = mp;
1991         rxq->nb_rx_desc = nb_desc;
1992         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1993         rxq->queue_id = queue_idx;
1994         rxq->reg_idx = reg_idx;
1995         rxq->port_id = dev->data->port_id;
1996         if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_KEEP_CRC)
1997                 rxq->crc_len = RTE_ETHER_CRC_LEN;
1998         else
1999                 rxq->crc_len = 0;
2000         rxq->drop_en = rx_conf->rx_drop_en;
2001         rxq->vsi = vsi;
2002         rxq->rx_deferred_start = rx_conf->rx_deferred_start;
2003         rxq->offloads = offloads;
2004
2005         /* Allocate the maximun number of RX ring hardware descriptor. */
2006         len = I40E_MAX_RING_DESC;
2007
2008         /**
2009          * Allocating a little more memory because vectorized/bulk_alloc Rx
2010          * functions doesn't check boundaries each time.
2011          */
2012         len += RTE_PMD_I40E_RX_MAX_BURST;
2013
2014         ring_size = RTE_ALIGN(len * sizeof(union i40e_rx_desc),
2015                               I40E_DMA_MEM_ALIGN);
2016
2017         rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
2018                               ring_size, I40E_RING_BASE_ALIGN, socket_id);
2019         if (!rz) {
2020                 i40e_rx_queue_release(rxq);
2021                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX");
2022                 return -ENOMEM;
2023         }
2024
2025         rxq->mz = rz;
2026         /* Zero all the descriptors in the ring. */
2027         memset(rz->addr, 0, ring_size);
2028
2029         rxq->rx_ring_phys_addr = rz->iova;
2030         rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
2031
2032         len = (uint16_t)(nb_desc + RTE_PMD_I40E_RX_MAX_BURST);
2033
2034         /* Allocate the software ring. */
2035         rxq->sw_ring =
2036                 rte_zmalloc_socket("i40e rx sw ring",
2037                                    sizeof(struct i40e_rx_entry) * len,
2038                                    RTE_CACHE_LINE_SIZE,
2039                                    socket_id);
2040         if (!rxq->sw_ring) {
2041                 i40e_rx_queue_release(rxq);
2042                 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW ring");
2043                 return -ENOMEM;
2044         }
2045
2046         i40e_reset_rx_queue(rxq);
2047         rxq->q_set = TRUE;
2048
2049         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2050                 if (!(vsi->enabled_tc & (1 << i)))
2051                         continue;
2052                 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
2053                 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
2054                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
2055                 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
2056                         I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
2057
2058                 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
2059                         rxq->dcb_tc = i;
2060         }
2061
2062         if (dev->data->dev_started) {
2063                 if (i40e_dev_rx_queue_setup_runtime(dev, rxq)) {
2064                         i40e_rx_queue_release(rxq);
2065                         return -EINVAL;
2066                 }
2067         } else {
2068                 use_def_burst_func =
2069                         check_rx_burst_bulk_alloc_preconditions(rxq);
2070                 if (!use_def_burst_func) {
2071 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2072                         PMD_INIT_LOG(DEBUG,
2073                           "Rx Burst Bulk Alloc Preconditions are "
2074                           "satisfied. Rx Burst Bulk Alloc function will be "
2075                           "used on port=%d, queue=%d.",
2076                           rxq->port_id, rxq->queue_id);
2077 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2078                 } else {
2079                         PMD_INIT_LOG(DEBUG,
2080                           "Rx Burst Bulk Alloc Preconditions are "
2081                           "not satisfied, Scattered Rx is requested, "
2082                           "or RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC is "
2083                           "not enabled on port=%d, queue=%d.",
2084                           rxq->port_id, rxq->queue_id);
2085                         ad->rx_bulk_alloc_allowed = false;
2086                 }
2087         }
2088
2089         dev->data->rx_queues[queue_idx] = rxq;
2090         return 0;
2091 }
2092
2093 void
2094 i40e_dev_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
2095 {
2096         i40e_rx_queue_release(dev->data->rx_queues[qid]);
2097 }
2098
2099 void
2100 i40e_dev_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
2101 {
2102         i40e_tx_queue_release(dev->data->tx_queues[qid]);
2103 }
2104
2105 void
2106 i40e_rx_queue_release(void *rxq)
2107 {
2108         struct i40e_rx_queue *q = (struct i40e_rx_queue *)rxq;
2109
2110         if (!q) {
2111                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
2112                 return;
2113         }
2114
2115         i40e_rx_queue_release_mbufs(q);
2116         rte_free(q->sw_ring);
2117         rte_memzone_free(q->mz);
2118         rte_free(q);
2119 }
2120
2121 uint32_t
2122 i40e_dev_rx_queue_count(void *rx_queue)
2123 {
2124 #define I40E_RXQ_SCAN_INTERVAL 4
2125         volatile union i40e_rx_desc *rxdp;
2126         struct i40e_rx_queue *rxq;
2127         uint16_t desc = 0;
2128
2129         rxq = rx_queue;
2130         rxdp = &(rxq->rx_ring[rxq->rx_tail]);
2131         while ((desc < rxq->nb_rx_desc) &&
2132                 ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
2133                 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
2134                                 (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
2135                 /**
2136                  * Check the DD bit of a rx descriptor of each 4 in a group,
2137                  * to avoid checking too frequently and downgrading performance
2138                  * too much.
2139                  */
2140                 desc += I40E_RXQ_SCAN_INTERVAL;
2141                 rxdp += I40E_RXQ_SCAN_INTERVAL;
2142                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
2143                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
2144                                         desc - rxq->nb_rx_desc]);
2145         }
2146
2147         return desc;
2148 }
2149
2150 int
2151 i40e_dev_rx_descriptor_status(void *rx_queue, uint16_t offset)
2152 {
2153         struct i40e_rx_queue *rxq = rx_queue;
2154         volatile uint64_t *status;
2155         uint64_t mask;
2156         uint32_t desc;
2157
2158         if (unlikely(offset >= rxq->nb_rx_desc))
2159                 return -EINVAL;
2160
2161         if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
2162                 return RTE_ETH_RX_DESC_UNAVAIL;
2163
2164         desc = rxq->rx_tail + offset;
2165         if (desc >= rxq->nb_rx_desc)
2166                 desc -= rxq->nb_rx_desc;
2167
2168         status = &rxq->rx_ring[desc].wb.qword1.status_error_len;
2169         mask = rte_le_to_cpu_64((1ULL << I40E_RX_DESC_STATUS_DD_SHIFT)
2170                 << I40E_RXD_QW1_STATUS_SHIFT);
2171         if (*status & mask)
2172                 return RTE_ETH_RX_DESC_DONE;
2173
2174         return RTE_ETH_RX_DESC_AVAIL;
2175 }
2176
2177 int
2178 i40e_dev_tx_descriptor_status(void *tx_queue, uint16_t offset)
2179 {
2180         struct i40e_tx_queue *txq = tx_queue;
2181         volatile uint64_t *status;
2182         uint64_t mask, expect;
2183         uint32_t desc;
2184
2185         if (unlikely(offset >= txq->nb_tx_desc))
2186                 return -EINVAL;
2187
2188         desc = txq->tx_tail + offset;
2189         /* go to next desc that has the RS bit */
2190         desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) *
2191                 txq->tx_rs_thresh;
2192         if (desc >= txq->nb_tx_desc) {
2193                 desc -= txq->nb_tx_desc;
2194                 if (desc >= txq->nb_tx_desc)
2195                         desc -= txq->nb_tx_desc;
2196         }
2197
2198         status = &txq->tx_ring[desc].cmd_type_offset_bsz;
2199         mask = rte_le_to_cpu_64(I40E_TXD_QW1_DTYPE_MASK);
2200         expect = rte_cpu_to_le_64(
2201                 I40E_TX_DESC_DTYPE_DESC_DONE << I40E_TXD_QW1_DTYPE_SHIFT);
2202         if ((*status & mask) == expect)
2203                 return RTE_ETH_TX_DESC_DONE;
2204
2205         return RTE_ETH_TX_DESC_FULL;
2206 }
2207
2208 static int
2209 i40e_dev_tx_queue_setup_runtime(struct rte_eth_dev *dev,
2210                                 struct i40e_tx_queue *txq)
2211 {
2212         struct i40e_adapter *ad =
2213                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2214
2215         if (i40e_tx_queue_init(txq) != I40E_SUCCESS) {
2216                 PMD_DRV_LOG(ERR,
2217                             "Failed to do TX queue initialization");
2218                 return -EINVAL;
2219         }
2220
2221         if (i40e_dev_first_queue(txq->queue_id,
2222                                  dev->data->tx_queues,
2223                                  dev->data->nb_tx_queues)) {
2224                 /**
2225                  * If it is the first queue to setup,
2226                  * set all flags and call
2227                  * i40e_set_tx_function.
2228                  */
2229                 i40e_set_tx_function_flag(dev, txq);
2230                 i40e_set_tx_function(dev);
2231                 return 0;
2232         }
2233
2234         /* check vector conflict */
2235         if (ad->tx_vec_allowed) {
2236                 if (txq->tx_rs_thresh > RTE_I40E_TX_MAX_FREE_BUF_SZ ||
2237                     i40e_txq_vec_setup(txq)) {
2238                         PMD_DRV_LOG(ERR, "Failed vector tx setup.");
2239                         return -EINVAL;
2240                 }
2241         }
2242         /* check simple tx conflict */
2243         if (ad->tx_simple_allowed) {
2244                 if ((txq->offloads & ~RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE) != 0 ||
2245                                 txq->tx_rs_thresh < RTE_PMD_I40E_TX_MAX_BURST) {
2246                         PMD_DRV_LOG(ERR, "No-simple tx is required.");
2247                         return -EINVAL;
2248                 }
2249         }
2250
2251         return 0;
2252 }
2253
2254 int
2255 i40e_dev_tx_queue_setup(struct rte_eth_dev *dev,
2256                         uint16_t queue_idx,
2257                         uint16_t nb_desc,
2258                         unsigned int socket_id,
2259                         const struct rte_eth_txconf *tx_conf)
2260 {
2261         struct i40e_vsi *vsi;
2262         struct i40e_pf *pf = NULL;
2263         struct i40e_tx_queue *txq;
2264         const struct rte_memzone *tz;
2265         uint32_t ring_size;
2266         uint16_t tx_rs_thresh, tx_free_thresh;
2267         uint16_t reg_idx, i, base, bsf, tc_mapping;
2268         int q_offset;
2269         uint64_t offloads;
2270
2271         offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
2272
2273         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2274         vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
2275         if (!vsi)
2276                 return -EINVAL;
2277         q_offset = i40e_get_queue_offset_by_qindex(pf, queue_idx);
2278         if (q_offset < 0)
2279                 return -EINVAL;
2280         reg_idx = vsi->base_queue + q_offset;
2281
2282         if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
2283             (nb_desc > I40E_MAX_RING_DESC) ||
2284             (nb_desc < I40E_MIN_RING_DESC)) {
2285                 PMD_DRV_LOG(ERR, "Number (%u) of transmit descriptors is "
2286                             "invalid", nb_desc);
2287                 return -EINVAL;
2288         }
2289
2290         /**
2291          * The following two parameters control the setting of the RS bit on
2292          * transmit descriptors. TX descriptors will have their RS bit set
2293          * after txq->tx_rs_thresh descriptors have been used. The TX
2294          * descriptor ring will be cleaned after txq->tx_free_thresh
2295          * descriptors are used or if the number of descriptors required to
2296          * transmit a packet is greater than the number of free TX descriptors.
2297          *
2298          * The following constraints must be satisfied:
2299          *  - tx_rs_thresh must be greater than 0.
2300          *  - tx_rs_thresh must be less than the size of the ring minus 2.
2301          *  - tx_rs_thresh must be less than or equal to tx_free_thresh.
2302          *  - tx_rs_thresh must be a divisor of the ring size.
2303          *  - tx_free_thresh must be greater than 0.
2304          *  - tx_free_thresh must be less than the size of the ring minus 3.
2305          *  - tx_free_thresh + tx_rs_thresh must not exceed nb_desc.
2306          *
2307          * One descriptor in the TX ring is used as a sentinel to avoid a H/W
2308          * race condition, hence the maximum threshold constraints. When set
2309          * to zero use default values.
2310          */
2311         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
2312                 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
2313         /* force tx_rs_thresh to adapt an aggresive tx_free_thresh */
2314         tx_rs_thresh = (DEFAULT_TX_RS_THRESH + tx_free_thresh > nb_desc) ?
2315                 nb_desc - tx_free_thresh : DEFAULT_TX_RS_THRESH;
2316         if (tx_conf->tx_rs_thresh > 0)
2317                 tx_rs_thresh = tx_conf->tx_rs_thresh;
2318         if (tx_rs_thresh + tx_free_thresh > nb_desc) {
2319                 PMD_INIT_LOG(ERR, "tx_rs_thresh + tx_free_thresh must not "
2320                                 "exceed nb_desc. (tx_rs_thresh=%u "
2321                                 "tx_free_thresh=%u nb_desc=%u port=%d queue=%d)",
2322                                 (unsigned int)tx_rs_thresh,
2323                                 (unsigned int)tx_free_thresh,
2324                                 (unsigned int)nb_desc,
2325                                 (int)dev->data->port_id,
2326                                 (int)queue_idx);
2327                 return I40E_ERR_PARAM;
2328         }
2329         if (tx_rs_thresh >= (nb_desc - 2)) {
2330                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
2331                              "number of TX descriptors minus 2. "
2332                              "(tx_rs_thresh=%u port=%d queue=%d)",
2333                              (unsigned int)tx_rs_thresh,
2334                              (int)dev->data->port_id,
2335                              (int)queue_idx);
2336                 return I40E_ERR_PARAM;
2337         }
2338         if (tx_free_thresh >= (nb_desc - 3)) {
2339                 PMD_INIT_LOG(ERR, "tx_free_thresh must be less than the "
2340                              "number of TX descriptors minus 3. "
2341                              "(tx_free_thresh=%u port=%d queue=%d)",
2342                              (unsigned int)tx_free_thresh,
2343                              (int)dev->data->port_id,
2344                              (int)queue_idx);
2345                 return I40E_ERR_PARAM;
2346         }
2347         if (tx_rs_thresh > tx_free_thresh) {
2348                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
2349                              "equal to tx_free_thresh. (tx_free_thresh=%u"
2350                              " tx_rs_thresh=%u port=%d queue=%d)",
2351                              (unsigned int)tx_free_thresh,
2352                              (unsigned int)tx_rs_thresh,
2353                              (int)dev->data->port_id,
2354                              (int)queue_idx);
2355                 return I40E_ERR_PARAM;
2356         }
2357         if ((nb_desc % tx_rs_thresh) != 0) {
2358                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
2359                              "number of TX descriptors. (tx_rs_thresh=%u"
2360                              " port=%d queue=%d)",
2361                              (unsigned int)tx_rs_thresh,
2362                              (int)dev->data->port_id,
2363                              (int)queue_idx);
2364                 return I40E_ERR_PARAM;
2365         }
2366         if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
2367                 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
2368                              "tx_rs_thresh is greater than 1. "
2369                              "(tx_rs_thresh=%u port=%d queue=%d)",
2370                              (unsigned int)tx_rs_thresh,
2371                              (int)dev->data->port_id,
2372                              (int)queue_idx);
2373                 return I40E_ERR_PARAM;
2374         }
2375
2376         /* Free memory if needed. */
2377         if (dev->data->tx_queues[queue_idx]) {
2378                 i40e_tx_queue_release(dev->data->tx_queues[queue_idx]);
2379                 dev->data->tx_queues[queue_idx] = NULL;
2380         }
2381
2382         /* Allocate the TX queue data structure. */
2383         txq = rte_zmalloc_socket("i40e tx queue",
2384                                   sizeof(struct i40e_tx_queue),
2385                                   RTE_CACHE_LINE_SIZE,
2386                                   socket_id);
2387         if (!txq) {
2388                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2389                             "tx queue structure");
2390                 return -ENOMEM;
2391         }
2392
2393         /* Allocate TX hardware ring descriptors. */
2394         ring_size = sizeof(struct i40e_tx_desc) * I40E_MAX_RING_DESC;
2395         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2396         tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
2397                               ring_size, I40E_RING_BASE_ALIGN, socket_id);
2398         if (!tz) {
2399                 i40e_tx_queue_release(txq);
2400                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX");
2401                 return -ENOMEM;
2402         }
2403
2404         txq->mz = tz;
2405         txq->nb_tx_desc = nb_desc;
2406         txq->tx_rs_thresh = tx_rs_thresh;
2407         txq->tx_free_thresh = tx_free_thresh;
2408         txq->pthresh = tx_conf->tx_thresh.pthresh;
2409         txq->hthresh = tx_conf->tx_thresh.hthresh;
2410         txq->wthresh = tx_conf->tx_thresh.wthresh;
2411         txq->queue_id = queue_idx;
2412         txq->reg_idx = reg_idx;
2413         txq->port_id = dev->data->port_id;
2414         txq->offloads = offloads;
2415         txq->vsi = vsi;
2416         txq->tx_deferred_start = tx_conf->tx_deferred_start;
2417
2418         txq->tx_ring_phys_addr = tz->iova;
2419         txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2420
2421         /* Allocate software ring */
2422         txq->sw_ring =
2423                 rte_zmalloc_socket("i40e tx sw ring",
2424                                    sizeof(struct i40e_tx_entry) * nb_desc,
2425                                    RTE_CACHE_LINE_SIZE,
2426                                    socket_id);
2427         if (!txq->sw_ring) {
2428                 i40e_tx_queue_release(txq);
2429                 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW TX ring");
2430                 return -ENOMEM;
2431         }
2432
2433         i40e_reset_tx_queue(txq);
2434         txq->q_set = TRUE;
2435
2436         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2437                 if (!(vsi->enabled_tc & (1 << i)))
2438                         continue;
2439                 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
2440                 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
2441                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
2442                 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
2443                         I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
2444
2445                 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
2446                         txq->dcb_tc = i;
2447         }
2448
2449         if (dev->data->dev_started) {
2450                 if (i40e_dev_tx_queue_setup_runtime(dev, txq)) {
2451                         i40e_tx_queue_release(txq);
2452                         return -EINVAL;
2453                 }
2454         } else {
2455                 /**
2456                  * Use a simple TX queue without offloads or
2457                  * multi segs if possible
2458                  */
2459                 i40e_set_tx_function_flag(dev, txq);
2460         }
2461         dev->data->tx_queues[queue_idx] = txq;
2462
2463         return 0;
2464 }
2465
2466 void
2467 i40e_tx_queue_release(void *txq)
2468 {
2469         struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
2470
2471         if (!q) {
2472                 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
2473                 return;
2474         }
2475
2476         i40e_tx_queue_release_mbufs(q);
2477         rte_free(q->sw_ring);
2478         rte_memzone_free(q->mz);
2479         rte_free(q);
2480 }
2481
2482 const struct rte_memzone *
2483 i40e_memzone_reserve(const char *name, uint32_t len, int socket_id)
2484 {
2485         const struct rte_memzone *mz;
2486
2487         mz = rte_memzone_lookup(name);
2488         if (mz)
2489                 return mz;
2490
2491         mz = rte_memzone_reserve_aligned(name, len, socket_id,
2492                         RTE_MEMZONE_IOVA_CONTIG, I40E_RING_BASE_ALIGN);
2493         return mz;
2494 }
2495
2496 void
2497 i40e_rx_queue_release_mbufs(struct i40e_rx_queue *rxq)
2498 {
2499         uint16_t i;
2500
2501         /* SSE Vector driver has a different way of releasing mbufs. */
2502         if (rxq->rx_using_sse) {
2503                 i40e_rx_queue_release_mbufs_vec(rxq);
2504                 return;
2505         }
2506
2507         if (!rxq->sw_ring) {
2508                 PMD_DRV_LOG(DEBUG, "Pointer to sw_ring is NULL");
2509                 return;
2510         }
2511
2512         for (i = 0; i < rxq->nb_rx_desc; i++) {
2513                 if (rxq->sw_ring[i].mbuf) {
2514                         rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2515                         rxq->sw_ring[i].mbuf = NULL;
2516                 }
2517         }
2518 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2519         if (rxq->rx_nb_avail == 0)
2520                 return;
2521         for (i = 0; i < rxq->rx_nb_avail; i++) {
2522                 struct rte_mbuf *mbuf;
2523
2524                 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
2525                 rte_pktmbuf_free_seg(mbuf);
2526         }
2527         rxq->rx_nb_avail = 0;
2528 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2529 }
2530
2531 void
2532 i40e_reset_rx_queue(struct i40e_rx_queue *rxq)
2533 {
2534         unsigned i;
2535         uint16_t len;
2536
2537         if (!rxq) {
2538                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
2539                 return;
2540         }
2541
2542 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2543         if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
2544                 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_I40E_RX_MAX_BURST);
2545         else
2546 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2547                 len = rxq->nb_rx_desc;
2548
2549         for (i = 0; i < len * sizeof(union i40e_rx_desc); i++)
2550                 ((volatile char *)rxq->rx_ring)[i] = 0;
2551
2552         memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2553         for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; ++i)
2554                 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2555
2556 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2557         rxq->rx_nb_avail = 0;
2558         rxq->rx_next_avail = 0;
2559         rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2560 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2561         rxq->rx_tail = 0;
2562         rxq->nb_rx_hold = 0;
2563
2564         if (rxq->pkt_first_seg != NULL)
2565                 rte_pktmbuf_free(rxq->pkt_first_seg);
2566
2567         rxq->pkt_first_seg = NULL;
2568         rxq->pkt_last_seg = NULL;
2569
2570         rxq->rxrearm_start = 0;
2571         rxq->rxrearm_nb = 0;
2572 }
2573
2574 void
2575 i40e_tx_queue_release_mbufs(struct i40e_tx_queue *txq)
2576 {
2577         struct rte_eth_dev *dev;
2578         uint16_t i;
2579
2580         if (!txq || !txq->sw_ring) {
2581                 PMD_DRV_LOG(DEBUG, "Pointer to txq or sw_ring is NULL");
2582                 return;
2583         }
2584
2585         dev = &rte_eth_devices[txq->port_id];
2586
2587         /**
2588          *  vPMD tx will not set sw_ring's mbuf to NULL after free,
2589          *  so need to free remains more carefully.
2590          */
2591 #ifdef CC_AVX512_SUPPORT
2592         if (dev->tx_pkt_burst == i40e_xmit_pkts_vec_avx512) {
2593                 struct i40e_vec_tx_entry *swr = (void *)txq->sw_ring;
2594
2595                 i = txq->tx_next_dd - txq->tx_rs_thresh + 1;
2596                 if (txq->tx_tail < i) {
2597                         for (; i < txq->nb_tx_desc; i++) {
2598                                 rte_pktmbuf_free_seg(swr[i].mbuf);
2599                                 swr[i].mbuf = NULL;
2600                         }
2601                         i = 0;
2602                 }
2603                 for (; i < txq->tx_tail; i++) {
2604                         rte_pktmbuf_free_seg(swr[i].mbuf);
2605                         swr[i].mbuf = NULL;
2606                 }
2607                 return;
2608         }
2609 #endif
2610         if (dev->tx_pkt_burst == i40e_xmit_pkts_vec_avx2 ||
2611                         dev->tx_pkt_burst == i40e_xmit_pkts_vec) {
2612                 i = txq->tx_next_dd - txq->tx_rs_thresh + 1;
2613                 if (txq->tx_tail < i) {
2614                         for (; i < txq->nb_tx_desc; i++) {
2615                                 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2616                                 txq->sw_ring[i].mbuf = NULL;
2617                         }
2618                         i = 0;
2619                 }
2620                 for (; i < txq->tx_tail; i++) {
2621                         rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2622                         txq->sw_ring[i].mbuf = NULL;
2623                 }
2624         } else {
2625                 for (i = 0; i < txq->nb_tx_desc; i++) {
2626                         if (txq->sw_ring[i].mbuf) {
2627                                 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2628                                 txq->sw_ring[i].mbuf = NULL;
2629                         }
2630                 }
2631         }
2632 }
2633
2634 static int
2635 i40e_tx_done_cleanup_full(struct i40e_tx_queue *txq,
2636                         uint32_t free_cnt)
2637 {
2638         struct i40e_tx_entry *swr_ring = txq->sw_ring;
2639         uint16_t i, tx_last, tx_id;
2640         uint16_t nb_tx_free_last;
2641         uint16_t nb_tx_to_clean;
2642         uint32_t pkt_cnt;
2643
2644         /* Start free mbuf from the next of tx_tail */
2645         tx_last = txq->tx_tail;
2646         tx_id  = swr_ring[tx_last].next_id;
2647
2648         if (txq->nb_tx_free == 0 && i40e_xmit_cleanup(txq))
2649                 return 0;
2650
2651         nb_tx_to_clean = txq->nb_tx_free;
2652         nb_tx_free_last = txq->nb_tx_free;
2653         if (!free_cnt)
2654                 free_cnt = txq->nb_tx_desc;
2655
2656         /* Loop through swr_ring to count the amount of
2657          * freeable mubfs and packets.
2658          */
2659         for (pkt_cnt = 0; pkt_cnt < free_cnt; ) {
2660                 for (i = 0; i < nb_tx_to_clean &&
2661                         pkt_cnt < free_cnt &&
2662                         tx_id != tx_last; i++) {
2663                         if (swr_ring[tx_id].mbuf != NULL) {
2664                                 rte_pktmbuf_free_seg(swr_ring[tx_id].mbuf);
2665                                 swr_ring[tx_id].mbuf = NULL;
2666
2667                                 /*
2668                                  * last segment in the packet,
2669                                  * increment packet count
2670                                  */
2671                                 pkt_cnt += (swr_ring[tx_id].last_id == tx_id);
2672                         }
2673
2674                         tx_id = swr_ring[tx_id].next_id;
2675                 }
2676
2677                 if (txq->tx_rs_thresh > txq->nb_tx_desc -
2678                         txq->nb_tx_free || tx_id == tx_last)
2679                         break;
2680
2681                 if (pkt_cnt < free_cnt) {
2682                         if (i40e_xmit_cleanup(txq))
2683                                 break;
2684
2685                         nb_tx_to_clean = txq->nb_tx_free - nb_tx_free_last;
2686                         nb_tx_free_last = txq->nb_tx_free;
2687                 }
2688         }
2689
2690         return (int)pkt_cnt;
2691 }
2692
2693 static int
2694 i40e_tx_done_cleanup_simple(struct i40e_tx_queue *txq,
2695                         uint32_t free_cnt)
2696 {
2697         int i, n, cnt;
2698
2699         if (free_cnt == 0 || free_cnt > txq->nb_tx_desc)
2700                 free_cnt = txq->nb_tx_desc;
2701
2702         cnt = free_cnt - free_cnt % txq->tx_rs_thresh;
2703
2704         for (i = 0; i < cnt; i += n) {
2705                 if (txq->nb_tx_desc - txq->nb_tx_free < txq->tx_rs_thresh)
2706                         break;
2707
2708                 n = i40e_tx_free_bufs(txq);
2709
2710                 if (n == 0)
2711                         break;
2712         }
2713
2714         return i;
2715 }
2716
2717 static int
2718 i40e_tx_done_cleanup_vec(struct i40e_tx_queue *txq __rte_unused,
2719                         uint32_t free_cnt __rte_unused)
2720 {
2721         return -ENOTSUP;
2722 }
2723 int
2724 i40e_tx_done_cleanup(void *txq, uint32_t free_cnt)
2725 {
2726         struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
2727         struct rte_eth_dev *dev = &rte_eth_devices[q->port_id];
2728         struct i40e_adapter *ad =
2729                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2730
2731         if (ad->tx_simple_allowed) {
2732                 if (ad->tx_vec_allowed)
2733                         return i40e_tx_done_cleanup_vec(q, free_cnt);
2734                 else
2735                         return i40e_tx_done_cleanup_simple(q, free_cnt);
2736         } else {
2737                 return i40e_tx_done_cleanup_full(q, free_cnt);
2738         }
2739 }
2740
2741 void
2742 i40e_reset_tx_queue(struct i40e_tx_queue *txq)
2743 {
2744         struct i40e_tx_entry *txe;
2745         uint16_t i, prev, size;
2746
2747         if (!txq) {
2748                 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
2749                 return;
2750         }
2751
2752         txe = txq->sw_ring;
2753         size = sizeof(struct i40e_tx_desc) * txq->nb_tx_desc;
2754         for (i = 0; i < size; i++)
2755                 ((volatile char *)txq->tx_ring)[i] = 0;
2756
2757         prev = (uint16_t)(txq->nb_tx_desc - 1);
2758         for (i = 0; i < txq->nb_tx_desc; i++) {
2759                 volatile struct i40e_tx_desc *txd = &txq->tx_ring[i];
2760
2761                 txd->cmd_type_offset_bsz =
2762                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE);
2763                 txe[i].mbuf =  NULL;
2764                 txe[i].last_id = i;
2765                 txe[prev].next_id = i;
2766                 prev = i;
2767         }
2768
2769         txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2770         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2771
2772         txq->tx_tail = 0;
2773         txq->nb_tx_used = 0;
2774
2775         txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
2776         txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
2777 }
2778
2779 /* Init the TX queue in hardware */
2780 int
2781 i40e_tx_queue_init(struct i40e_tx_queue *txq)
2782 {
2783         enum i40e_status_code err = I40E_SUCCESS;
2784         struct i40e_vsi *vsi = txq->vsi;
2785         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2786         uint16_t pf_q = txq->reg_idx;
2787         struct i40e_hmc_obj_txq tx_ctx;
2788         uint32_t qtx_ctl;
2789
2790         /* clear the context structure first */
2791         memset(&tx_ctx, 0, sizeof(tx_ctx));
2792         tx_ctx.new_context = 1;
2793         tx_ctx.base = txq->tx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2794         tx_ctx.qlen = txq->nb_tx_desc;
2795
2796 #ifdef RTE_LIBRTE_IEEE1588
2797         tx_ctx.timesync_ena = 1;
2798 #endif
2799         tx_ctx.rdylist = rte_le_to_cpu_16(vsi->info.qs_handle[txq->dcb_tc]);
2800         if (vsi->type == I40E_VSI_FDIR)
2801                 tx_ctx.fd_ena = TRUE;
2802
2803         err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2804         if (err != I40E_SUCCESS) {
2805                 PMD_DRV_LOG(ERR, "Failure of clean lan tx queue context");
2806                 return err;
2807         }
2808
2809         err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2810         if (err != I40E_SUCCESS) {
2811                 PMD_DRV_LOG(ERR, "Failure of set lan tx queue context");
2812                 return err;
2813         }
2814
2815         /* Now associate this queue with this PCI function */
2816         qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
2817         qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2818                                         I40E_QTX_CTL_PF_INDX_MASK);
2819         I40E_WRITE_REG(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2820         I40E_WRITE_FLUSH(hw);
2821
2822         txq->qtx_tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2823
2824         return err;
2825 }
2826
2827 int
2828 i40e_alloc_rx_queue_mbufs(struct i40e_rx_queue *rxq)
2829 {
2830         struct i40e_rx_entry *rxe = rxq->sw_ring;
2831         uint64_t dma_addr;
2832         uint16_t i;
2833
2834         for (i = 0; i < rxq->nb_rx_desc; i++) {
2835                 volatile union i40e_rx_desc *rxd;
2836                 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mp);
2837
2838                 if (unlikely(!mbuf)) {
2839                         PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
2840                         return -ENOMEM;
2841                 }
2842
2843                 rte_mbuf_refcnt_set(mbuf, 1);
2844                 mbuf->next = NULL;
2845                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2846                 mbuf->nb_segs = 1;
2847                 mbuf->port = rxq->port_id;
2848
2849                 dma_addr =
2850                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
2851
2852                 rxd = &rxq->rx_ring[i];
2853                 rxd->read.pkt_addr = dma_addr;
2854                 rxd->read.hdr_addr = 0;
2855 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2856                 rxd->read.rsvd1 = 0;
2857                 rxd->read.rsvd2 = 0;
2858 #endif /* RTE_LIBRTE_I40E_16BYTE_RX_DESC */
2859
2860                 rxe[i].mbuf = mbuf;
2861         }
2862
2863         return 0;
2864 }
2865
2866 /*
2867  * Calculate the buffer length, and check the jumbo frame
2868  * and maximum packet length.
2869  */
2870 static int
2871 i40e_rx_queue_config(struct i40e_rx_queue *rxq)
2872 {
2873         struct i40e_pf *pf = I40E_VSI_TO_PF(rxq->vsi);
2874         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2875         struct rte_eth_dev_data *data = pf->dev_data;
2876         uint16_t buf_size;
2877
2878         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2879                 RTE_PKTMBUF_HEADROOM);
2880
2881         switch (pf->flags & (I40E_FLAG_HEADER_SPLIT_DISABLED |
2882                         I40E_FLAG_HEADER_SPLIT_ENABLED)) {
2883         case I40E_FLAG_HEADER_SPLIT_ENABLED: /* Not supported */
2884                 rxq->rx_hdr_len = RTE_ALIGN(I40E_RXBUF_SZ_1024,
2885                                 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2886                 rxq->rx_buf_len = RTE_ALIGN(I40E_RXBUF_SZ_2048,
2887                                 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2888                 rxq->hs_mode = i40e_header_split_enabled;
2889                 break;
2890         case I40E_FLAG_HEADER_SPLIT_DISABLED:
2891         default:
2892                 rxq->rx_hdr_len = 0;
2893                 rxq->rx_buf_len = RTE_ALIGN_FLOOR(buf_size,
2894                         (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2895                 rxq->hs_mode = i40e_header_split_none;
2896                 break;
2897         }
2898
2899         rxq->max_pkt_len =
2900                 RTE_MIN(hw->func_caps.rx_buf_chain_len * rxq->rx_buf_len,
2901                                 data->mtu + I40E_ETH_OVERHEAD);
2902         if (rxq->max_pkt_len < RTE_ETHER_MIN_LEN ||
2903                 rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
2904                 PMD_DRV_LOG(ERR, "maximum packet length must be "
2905                             "larger than %u and smaller than %u",
2906                             (uint32_t)RTE_ETHER_MIN_LEN,
2907                             (uint32_t)I40E_FRAME_SIZE_MAX);
2908                 return I40E_ERR_CONFIG;
2909         }
2910
2911         return 0;
2912 }
2913
2914 /* Init the RX queue in hardware */
2915 int
2916 i40e_rx_queue_init(struct i40e_rx_queue *rxq)
2917 {
2918         int err = I40E_SUCCESS;
2919         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2920         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(rxq->vsi);
2921         uint16_t pf_q = rxq->reg_idx;
2922         uint16_t buf_size;
2923         struct i40e_hmc_obj_rxq rx_ctx;
2924
2925         err = i40e_rx_queue_config(rxq);
2926         if (err < 0) {
2927                 PMD_DRV_LOG(ERR, "Failed to config RX queue");
2928                 return err;
2929         }
2930
2931         /* Clear the context structure first */
2932         memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
2933         rx_ctx.dbuff = rxq->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2934         rx_ctx.hbuff = rxq->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2935
2936         rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2937         rx_ctx.qlen = rxq->nb_rx_desc;
2938 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2939         rx_ctx.dsize = 1;
2940 #endif
2941         rx_ctx.dtype = rxq->hs_mode;
2942         if (rxq->hs_mode)
2943                 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_ALL;
2944         else
2945                 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
2946         rx_ctx.rxmax = rxq->max_pkt_len;
2947         rx_ctx.tphrdesc_ena = 1;
2948         rx_ctx.tphwdesc_ena = 1;
2949         rx_ctx.tphdata_ena = 1;
2950         rx_ctx.tphhead_ena = 1;
2951         rx_ctx.lrxqthresh = 2;
2952         rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
2953         rx_ctx.l2tsel = 1;
2954         /* showiv indicates if inner VLAN is stripped inside of tunnel
2955          * packet. When set it to 1, vlan information is stripped from
2956          * the inner header, but the hardware does not put it in the
2957          * descriptor. So set it zero by default.
2958          */
2959         rx_ctx.showiv = 0;
2960         rx_ctx.prefena = 1;
2961
2962         err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2963         if (err != I40E_SUCCESS) {
2964                 PMD_DRV_LOG(ERR, "Failed to clear LAN RX queue context");
2965                 return err;
2966         }
2967         err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2968         if (err != I40E_SUCCESS) {
2969                 PMD_DRV_LOG(ERR, "Failed to set LAN RX queue context");
2970                 return err;
2971         }
2972
2973         rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2974
2975         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2976                 RTE_PKTMBUF_HEADROOM);
2977
2978         /* Check if scattered RX needs to be used. */
2979         if (rxq->max_pkt_len > buf_size)
2980                 dev_data->scattered_rx = 1;
2981
2982         /* Init the RX tail regieter. */
2983         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
2984
2985         return 0;
2986 }
2987
2988 void
2989 i40e_dev_clear_queues(struct rte_eth_dev *dev)
2990 {
2991         uint16_t i;
2992
2993         PMD_INIT_FUNC_TRACE();
2994
2995         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2996                 if (!dev->data->tx_queues[i])
2997                         continue;
2998                 i40e_tx_queue_release_mbufs(dev->data->tx_queues[i]);
2999                 i40e_reset_tx_queue(dev->data->tx_queues[i]);
3000         }
3001
3002         for (i = 0; i < dev->data->nb_rx_queues; i++) {
3003                 if (!dev->data->rx_queues[i])
3004                         continue;
3005                 i40e_rx_queue_release_mbufs(dev->data->rx_queues[i]);
3006                 i40e_reset_rx_queue(dev->data->rx_queues[i]);
3007         }
3008 }
3009
3010 void
3011 i40e_dev_free_queues(struct rte_eth_dev *dev)
3012 {
3013         uint16_t i;
3014
3015         PMD_INIT_FUNC_TRACE();
3016
3017         for (i = 0; i < dev->data->nb_rx_queues; i++) {
3018                 if (!dev->data->rx_queues[i])
3019                         continue;
3020                 i40e_rx_queue_release(dev->data->rx_queues[i]);
3021                 dev->data->rx_queues[i] = NULL;
3022         }
3023
3024         for (i = 0; i < dev->data->nb_tx_queues; i++) {
3025                 if (!dev->data->tx_queues[i])
3026                         continue;
3027                 i40e_tx_queue_release(dev->data->tx_queues[i]);
3028                 dev->data->tx_queues[i] = NULL;
3029         }
3030 }
3031
3032 enum i40e_status_code
3033 i40e_fdir_setup_tx_resources(struct i40e_pf *pf)
3034 {
3035         struct i40e_tx_queue *txq;
3036         const struct rte_memzone *tz = NULL;
3037         struct rte_eth_dev *dev;
3038         uint32_t ring_size;
3039
3040         if (!pf) {
3041                 PMD_DRV_LOG(ERR, "PF is not available");
3042                 return I40E_ERR_BAD_PTR;
3043         }
3044
3045         dev = &rte_eth_devices[pf->dev_data->port_id];
3046
3047         /* Allocate the TX queue data structure. */
3048         txq = rte_zmalloc_socket("i40e fdir tx queue",
3049                                   sizeof(struct i40e_tx_queue),
3050                                   RTE_CACHE_LINE_SIZE,
3051                                   SOCKET_ID_ANY);
3052         if (!txq) {
3053                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3054                                         "tx queue structure.");
3055                 return I40E_ERR_NO_MEMORY;
3056         }
3057
3058         /* Allocate TX hardware ring descriptors. */
3059         ring_size = sizeof(struct i40e_tx_desc) * I40E_FDIR_NUM_TX_DESC;
3060         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
3061
3062         tz = rte_eth_dma_zone_reserve(dev, "fdir_tx_ring",
3063                                       I40E_FDIR_QUEUE_ID, ring_size,
3064                                       I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
3065         if (!tz) {
3066                 i40e_tx_queue_release(txq);
3067                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX.");
3068                 return I40E_ERR_NO_MEMORY;
3069         }
3070
3071         txq->mz = tz;
3072         txq->nb_tx_desc = I40E_FDIR_NUM_TX_DESC;
3073         txq->queue_id = I40E_FDIR_QUEUE_ID;
3074         txq->reg_idx = pf->fdir.fdir_vsi->base_queue;
3075         txq->vsi = pf->fdir.fdir_vsi;
3076
3077         txq->tx_ring_phys_addr = tz->iova;
3078         txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
3079
3080         /*
3081          * don't need to allocate software ring and reset for the fdir
3082          * program queue just set the queue has been configured.
3083          */
3084         txq->q_set = TRUE;
3085         pf->fdir.txq = txq;
3086         pf->fdir.txq_available_buf_count = I40E_FDIR_PRG_PKT_CNT;
3087
3088         return I40E_SUCCESS;
3089 }
3090
3091 enum i40e_status_code
3092 i40e_fdir_setup_rx_resources(struct i40e_pf *pf)
3093 {
3094         struct i40e_rx_queue *rxq;
3095         const struct rte_memzone *rz = NULL;
3096         uint32_t ring_size;
3097         struct rte_eth_dev *dev;
3098
3099         if (!pf) {
3100                 PMD_DRV_LOG(ERR, "PF is not available");
3101                 return I40E_ERR_BAD_PTR;
3102         }
3103
3104         dev = &rte_eth_devices[pf->dev_data->port_id];
3105
3106         /* Allocate the RX queue data structure. */
3107         rxq = rte_zmalloc_socket("i40e fdir rx queue",
3108                                   sizeof(struct i40e_rx_queue),
3109                                   RTE_CACHE_LINE_SIZE,
3110                                   SOCKET_ID_ANY);
3111         if (!rxq) {
3112                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3113                                         "rx queue structure.");
3114                 return I40E_ERR_NO_MEMORY;
3115         }
3116
3117         /* Allocate RX hardware ring descriptors. */
3118         ring_size = sizeof(union i40e_rx_desc) * I40E_FDIR_NUM_RX_DESC;
3119         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
3120
3121         rz = rte_eth_dma_zone_reserve(dev, "fdir_rx_ring",
3122                                       I40E_FDIR_QUEUE_ID, ring_size,
3123                                       I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
3124         if (!rz) {
3125                 i40e_rx_queue_release(rxq);
3126                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX.");
3127                 return I40E_ERR_NO_MEMORY;
3128         }
3129
3130         rxq->mz = rz;
3131         rxq->nb_rx_desc = I40E_FDIR_NUM_RX_DESC;
3132         rxq->queue_id = I40E_FDIR_QUEUE_ID;
3133         rxq->reg_idx = pf->fdir.fdir_vsi->base_queue;
3134         rxq->vsi = pf->fdir.fdir_vsi;
3135
3136         rxq->rx_ring_phys_addr = rz->iova;
3137         memset(rz->addr, 0, I40E_FDIR_NUM_RX_DESC * sizeof(union i40e_rx_desc));
3138         rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
3139
3140         /*
3141          * Don't need to allocate software ring and reset for the fdir
3142          * rx queue, just set the queue has been configured.
3143          */
3144         rxq->q_set = TRUE;
3145         pf->fdir.rxq = rxq;
3146
3147         return I40E_SUCCESS;
3148 }
3149
3150 void
3151 i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
3152         struct rte_eth_rxq_info *qinfo)
3153 {
3154         struct i40e_rx_queue *rxq;
3155
3156         rxq = dev->data->rx_queues[queue_id];
3157
3158         qinfo->mp = rxq->mp;
3159         qinfo->scattered_rx = dev->data->scattered_rx;
3160         qinfo->nb_desc = rxq->nb_rx_desc;
3161
3162         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
3163         qinfo->conf.rx_drop_en = rxq->drop_en;
3164         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
3165         qinfo->conf.offloads = rxq->offloads;
3166 }
3167
3168 void
3169 i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
3170         struct rte_eth_txq_info *qinfo)
3171 {
3172         struct i40e_tx_queue *txq;
3173
3174         txq = dev->data->tx_queues[queue_id];
3175
3176         qinfo->nb_desc = txq->nb_tx_desc;
3177
3178         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
3179         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
3180         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
3181
3182         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
3183         qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
3184         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
3185         qinfo->conf.offloads = txq->offloads;
3186 }
3187
3188 #ifdef RTE_ARCH_X86
3189 static inline bool
3190 get_avx_supported(bool request_avx512)
3191 {
3192         if (request_avx512) {
3193                 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512 &&
3194                 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 &&
3195                 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1)
3196 #ifdef CC_AVX512_SUPPORT
3197                         return true;
3198 #else
3199                 PMD_DRV_LOG(NOTICE,
3200                         "AVX512 is not supported in build env");
3201                 return false;
3202 #endif
3203         } else {
3204                 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256 &&
3205                 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 &&
3206                 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1)
3207 #ifdef CC_AVX2_SUPPORT
3208                         return true;
3209 #else
3210                 PMD_DRV_LOG(NOTICE,
3211                         "AVX2 is not supported in build env");
3212                 return false;
3213 #endif
3214         }
3215
3216         return false;
3217 }
3218 #endif /* RTE_ARCH_X86 */
3219
3220
3221 void __rte_cold
3222 i40e_set_rx_function(struct rte_eth_dev *dev)
3223 {
3224         struct i40e_adapter *ad =
3225                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3226         uint16_t rx_using_sse, i;
3227         /* In order to allow Vector Rx there are a few configuration
3228          * conditions to be met and Rx Bulk Allocation should be allowed.
3229          */
3230         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3231 #ifdef RTE_ARCH_X86
3232                 ad->rx_use_avx512 = false;
3233                 ad->rx_use_avx2 = false;
3234 #endif
3235                 if (i40e_rx_vec_dev_conf_condition_check(dev) ||
3236                     !ad->rx_bulk_alloc_allowed) {
3237                         PMD_INIT_LOG(DEBUG, "Port[%d] doesn't meet"
3238                                      " Vector Rx preconditions",
3239                                      dev->data->port_id);
3240
3241                         ad->rx_vec_allowed = false;
3242                 }
3243                 if (ad->rx_vec_allowed) {
3244                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
3245                                 struct i40e_rx_queue *rxq =
3246                                         dev->data->rx_queues[i];
3247
3248                                 if (rxq && i40e_rxq_vec_setup(rxq)) {
3249                                         ad->rx_vec_allowed = false;
3250                                         break;
3251                                 }
3252                         }
3253 #ifdef RTE_ARCH_X86
3254                         ad->rx_use_avx512 = get_avx_supported(1);
3255
3256                         if (!ad->rx_use_avx512)
3257                                 ad->rx_use_avx2 = get_avx_supported(0);
3258 #endif
3259                 }
3260         }
3261
3262         if (ad->rx_vec_allowed  &&
3263             rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
3264 #ifdef RTE_ARCH_X86
3265                 if (dev->data->scattered_rx) {
3266                         if (ad->rx_use_avx512) {
3267 #ifdef CC_AVX512_SUPPORT
3268                                 PMD_DRV_LOG(NOTICE,
3269                                         "Using AVX512 Vector Scattered Rx (port %d).",
3270                                         dev->data->port_id);
3271                                 dev->rx_pkt_burst =
3272                                         i40e_recv_scattered_pkts_vec_avx512;
3273 #endif
3274                         } else {
3275                                 PMD_INIT_LOG(DEBUG,
3276                                         "Using %sVector Scattered Rx (port %d).",
3277                                         ad->rx_use_avx2 ? "avx2 " : "",
3278                                         dev->data->port_id);
3279                                 dev->rx_pkt_burst = ad->rx_use_avx2 ?
3280                                         i40e_recv_scattered_pkts_vec_avx2 :
3281                                         i40e_recv_scattered_pkts_vec;
3282                         }
3283                 } else {
3284                         if (ad->rx_use_avx512) {
3285 #ifdef CC_AVX512_SUPPORT
3286                                 PMD_DRV_LOG(NOTICE,
3287                                         "Using AVX512 Vector Rx (port %d).",
3288                                         dev->data->port_id);
3289                                 dev->rx_pkt_burst =
3290                                         i40e_recv_pkts_vec_avx512;
3291 #endif
3292                         } else {
3293                                 PMD_INIT_LOG(DEBUG,
3294                                         "Using %sVector Rx (port %d).",
3295                                         ad->rx_use_avx2 ? "avx2 " : "",
3296                                         dev->data->port_id);
3297                                 dev->rx_pkt_burst = ad->rx_use_avx2 ?
3298                                         i40e_recv_pkts_vec_avx2 :
3299                                         i40e_recv_pkts_vec;
3300                         }
3301                 }
3302 #else /* RTE_ARCH_X86 */
3303                 if (dev->data->scattered_rx) {
3304                         PMD_INIT_LOG(DEBUG,
3305                                      "Using Vector Scattered Rx (port %d).",
3306                                      dev->data->port_id);
3307                         dev->rx_pkt_burst = i40e_recv_scattered_pkts_vec;
3308                 } else {
3309                         PMD_INIT_LOG(DEBUG, "Using Vector Rx (port %d).",
3310                                      dev->data->port_id);
3311                         dev->rx_pkt_burst = i40e_recv_pkts_vec;
3312                 }
3313 #endif /* RTE_ARCH_X86 */
3314         } else if (!dev->data->scattered_rx && ad->rx_bulk_alloc_allowed) {
3315                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
3316                                     "satisfied. Rx Burst Bulk Alloc function "
3317                                     "will be used on port=%d.",
3318                              dev->data->port_id);
3319
3320                 dev->rx_pkt_burst = i40e_recv_pkts_bulk_alloc;
3321         } else {
3322                 /* Simple Rx Path. */
3323                 PMD_INIT_LOG(DEBUG, "Simple Rx path will be used on port=%d.",
3324                              dev->data->port_id);
3325                 dev->rx_pkt_burst = dev->data->scattered_rx ?
3326                                         i40e_recv_scattered_pkts :
3327                                         i40e_recv_pkts;
3328         }
3329
3330         /* Propagate information about RX function choice through all queues. */
3331         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3332                 rx_using_sse =
3333                         (dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
3334                          dev->rx_pkt_burst == i40e_recv_pkts_vec ||
3335 #ifdef CC_AVX512_SUPPORT
3336                          dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec_avx512 ||
3337                          dev->rx_pkt_burst == i40e_recv_pkts_vec_avx512 ||
3338 #endif
3339                          dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec_avx2 ||
3340                          dev->rx_pkt_burst == i40e_recv_pkts_vec_avx2);
3341
3342                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3343                         struct i40e_rx_queue *rxq = dev->data->rx_queues[i];
3344
3345                         if (rxq)
3346                                 rxq->rx_using_sse = rx_using_sse;
3347                 }
3348         }
3349 }
3350
3351 static const struct {
3352         eth_rx_burst_t pkt_burst;
3353         const char *info;
3354 } i40e_rx_burst_infos[] = {
3355         { i40e_recv_scattered_pkts,          "Scalar Scattered" },
3356         { i40e_recv_pkts_bulk_alloc,         "Scalar Bulk Alloc" },
3357         { i40e_recv_pkts,                    "Scalar" },
3358 #ifdef RTE_ARCH_X86
3359 #ifdef CC_AVX512_SUPPORT
3360         { i40e_recv_scattered_pkts_vec_avx512, "Vector AVX512 Scattered" },
3361         { i40e_recv_pkts_vec_avx512,           "Vector AVX512" },
3362 #endif
3363         { i40e_recv_scattered_pkts_vec_avx2, "Vector AVX2 Scattered" },
3364         { i40e_recv_pkts_vec_avx2,           "Vector AVX2" },
3365         { i40e_recv_scattered_pkts_vec,      "Vector SSE Scattered" },
3366         { i40e_recv_pkts_vec,                "Vector SSE" },
3367 #elif defined(RTE_ARCH_ARM64)
3368         { i40e_recv_scattered_pkts_vec,      "Vector Neon Scattered" },
3369         { i40e_recv_pkts_vec,                "Vector Neon" },
3370 #elif defined(RTE_ARCH_PPC_64)
3371         { i40e_recv_scattered_pkts_vec,      "Vector AltiVec Scattered" },
3372         { i40e_recv_pkts_vec,                "Vector AltiVec" },
3373 #endif
3374 };
3375
3376 int
3377 i40e_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
3378                        struct rte_eth_burst_mode *mode)
3379 {
3380         eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
3381         int ret = -EINVAL;
3382         unsigned int i;
3383
3384         for (i = 0; i < RTE_DIM(i40e_rx_burst_infos); ++i) {
3385                 if (pkt_burst == i40e_rx_burst_infos[i].pkt_burst) {
3386                         snprintf(mode->info, sizeof(mode->info), "%s",
3387                                  i40e_rx_burst_infos[i].info);
3388                         ret = 0;
3389                         break;
3390                 }
3391         }
3392
3393         return ret;
3394 }
3395
3396 void __rte_cold
3397 i40e_set_tx_function_flag(struct rte_eth_dev *dev, struct i40e_tx_queue *txq)
3398 {
3399         struct i40e_adapter *ad =
3400                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3401
3402         /* Use a simple Tx queue if possible (only fast free is allowed) */
3403         ad->tx_simple_allowed =
3404                 (txq->offloads ==
3405                  (txq->offloads & RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE) &&
3406                  txq->tx_rs_thresh >= RTE_PMD_I40E_TX_MAX_BURST);
3407         ad->tx_vec_allowed = (ad->tx_simple_allowed &&
3408                         txq->tx_rs_thresh <= RTE_I40E_TX_MAX_FREE_BUF_SZ);
3409
3410         if (ad->tx_vec_allowed)
3411                 PMD_INIT_LOG(DEBUG, "Vector Tx can be enabled on Tx queue %u.",
3412                                 txq->queue_id);
3413         else if (ad->tx_simple_allowed)
3414                 PMD_INIT_LOG(DEBUG, "Simple Tx can be enabled on Tx queue %u.",
3415                                 txq->queue_id);
3416         else
3417                 PMD_INIT_LOG(DEBUG,
3418                                 "Neither simple nor vector Tx enabled on Tx queue %u\n",
3419                                 txq->queue_id);
3420 }
3421
3422 void __rte_cold
3423 i40e_set_tx_function(struct rte_eth_dev *dev)
3424 {
3425         struct i40e_adapter *ad =
3426                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3427         int i;
3428
3429         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3430 #ifdef RTE_ARCH_X86
3431                 ad->tx_use_avx2 = false;
3432                 ad->tx_use_avx512 = false;
3433 #endif
3434                 if (ad->tx_vec_allowed) {
3435                         for (i = 0; i < dev->data->nb_tx_queues; i++) {
3436                                 struct i40e_tx_queue *txq =
3437                                         dev->data->tx_queues[i];
3438
3439                                 if (txq && i40e_txq_vec_setup(txq)) {
3440                                         ad->tx_vec_allowed = false;
3441                                         break;
3442                                 }
3443                         }
3444 #ifdef RTE_ARCH_X86
3445                         ad->tx_use_avx512 = get_avx_supported(1);
3446
3447                         if (!ad->tx_use_avx512)
3448                                 ad->tx_use_avx2 = get_avx_supported(0);
3449 #endif
3450                 }
3451         }
3452
3453         if (ad->tx_simple_allowed) {
3454                 if (ad->tx_vec_allowed &&
3455                     rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
3456 #ifdef RTE_ARCH_X86
3457                         if (ad->tx_use_avx512) {
3458 #ifdef CC_AVX512_SUPPORT
3459                                 PMD_DRV_LOG(NOTICE, "Using AVX512 Vector Tx (port %d).",
3460                                             dev->data->port_id);
3461                                 dev->tx_pkt_burst = i40e_xmit_pkts_vec_avx512;
3462 #endif
3463                         } else {
3464                                 PMD_INIT_LOG(DEBUG, "Using %sVector Tx (port %d).",
3465                                              ad->tx_use_avx2 ? "avx2 " : "",
3466                                              dev->data->port_id);
3467                                 dev->tx_pkt_burst = ad->tx_use_avx2 ?
3468                                                     i40e_xmit_pkts_vec_avx2 :
3469                                                     i40e_xmit_pkts_vec;
3470                         }
3471 #else /* RTE_ARCH_X86 */
3472                         PMD_INIT_LOG(DEBUG, "Using Vector Tx (port %d).",
3473                                      dev->data->port_id);
3474                         dev->tx_pkt_burst = i40e_xmit_pkts_vec;
3475 #endif /* RTE_ARCH_X86 */
3476                 } else {
3477                         PMD_INIT_LOG(DEBUG, "Simple tx finally be used.");
3478                         dev->tx_pkt_burst = i40e_xmit_pkts_simple;
3479                 }
3480                 dev->tx_pkt_prepare = i40e_simple_prep_pkts;
3481         } else {
3482                 PMD_INIT_LOG(DEBUG, "Xmit tx finally be used.");
3483                 dev->tx_pkt_burst = i40e_xmit_pkts;
3484                 dev->tx_pkt_prepare = i40e_prep_pkts;
3485         }
3486 }
3487
3488 static const struct {
3489         eth_tx_burst_t pkt_burst;
3490         const char *info;
3491 } i40e_tx_burst_infos[] = {
3492         { i40e_xmit_pkts_simple,   "Scalar Simple" },
3493         { i40e_xmit_pkts,          "Scalar" },
3494 #ifdef RTE_ARCH_X86
3495 #ifdef CC_AVX512_SUPPORT
3496         { i40e_xmit_pkts_vec_avx512, "Vector AVX512" },
3497 #endif
3498         { i40e_xmit_pkts_vec_avx2, "Vector AVX2" },
3499         { i40e_xmit_pkts_vec,      "Vector SSE" },
3500 #elif defined(RTE_ARCH_ARM64)
3501         { i40e_xmit_pkts_vec,      "Vector Neon" },
3502 #elif defined(RTE_ARCH_PPC_64)
3503         { i40e_xmit_pkts_vec,      "Vector AltiVec" },
3504 #endif
3505 };
3506
3507 int
3508 i40e_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
3509                        struct rte_eth_burst_mode *mode)
3510 {
3511         eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
3512         int ret = -EINVAL;
3513         unsigned int i;
3514
3515         for (i = 0; i < RTE_DIM(i40e_tx_burst_infos); ++i) {
3516                 if (pkt_burst == i40e_tx_burst_infos[i].pkt_burst) {
3517                         snprintf(mode->info, sizeof(mode->info), "%s",
3518                                  i40e_tx_burst_infos[i].info);
3519                         ret = 0;
3520                         break;
3521                 }
3522         }
3523
3524         return ret;
3525 }
3526
3527 void __rte_cold
3528 i40e_set_default_ptype_table(struct rte_eth_dev *dev)
3529 {
3530         struct i40e_adapter *ad =
3531                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3532         int i;
3533
3534         for (i = 0; i < I40E_MAX_PKT_TYPE; i++)
3535                 ad->ptype_tbl[i] = i40e_get_default_pkt_type(i);
3536 }
3537
3538 void __rte_cold
3539 i40e_set_default_pctype_table(struct rte_eth_dev *dev)
3540 {
3541         struct i40e_adapter *ad =
3542                         I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3543         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3544         int i;
3545
3546         for (i = 0; i < I40E_FLOW_TYPE_MAX; i++)
3547                 ad->pctypes_tbl[i] = 0ULL;
3548         ad->flow_types_mask = 0ULL;
3549         ad->pctypes_mask = 0ULL;
3550
3551         ad->pctypes_tbl[RTE_ETH_FLOW_FRAG_IPV4] =
3552                                 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4);
3553         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
3554                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP);
3555         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
3556                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP);
3557         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
3558                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP);
3559         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
3560                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER);
3561         ad->pctypes_tbl[RTE_ETH_FLOW_FRAG_IPV6] =
3562                                 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6);
3563         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
3564                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP);
3565         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
3566                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP);
3567         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
3568                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP);
3569         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
3570                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER);
3571         ad->pctypes_tbl[RTE_ETH_FLOW_L2_PAYLOAD] =
3572                                 (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD);
3573
3574         if (hw->mac.type == I40E_MAC_X722 ||
3575                 hw->mac.type == I40E_MAC_X722_VF) {
3576                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_UDP] |=
3577                         (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP);
3578                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_UDP] |=
3579                         (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
3580                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_TCP] |=
3581                         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
3582                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_UDP] |=
3583                         (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP);
3584                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_UDP] |=
3585                         (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
3586                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_TCP] |=
3587                         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
3588         }
3589
3590         for (i = 0; i < I40E_FLOW_TYPE_MAX; i++) {
3591                 if (ad->pctypes_tbl[i])
3592                         ad->flow_types_mask |= (1ULL << i);
3593                 ad->pctypes_mask |= ad->pctypes_tbl[i];
3594         }
3595 }
3596
3597 #ifndef CC_AVX2_SUPPORT
3598 uint16_t
3599 i40e_recv_pkts_vec_avx2(void __rte_unused *rx_queue,
3600                         struct rte_mbuf __rte_unused **rx_pkts,
3601                         uint16_t __rte_unused nb_pkts)
3602 {
3603         return 0;
3604 }
3605
3606 uint16_t
3607 i40e_recv_scattered_pkts_vec_avx2(void __rte_unused *rx_queue,
3608                         struct rte_mbuf __rte_unused **rx_pkts,
3609                         uint16_t __rte_unused nb_pkts)
3610 {
3611         return 0;
3612 }
3613
3614 uint16_t
3615 i40e_xmit_pkts_vec_avx2(void __rte_unused * tx_queue,
3616                           struct rte_mbuf __rte_unused **tx_pkts,
3617                           uint16_t __rte_unused nb_pkts)
3618 {
3619         return 0;
3620 }
3621 #endif /* ifndef CC_AVX2_SUPPORT */