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38 * 32 bits tx flags, high 16 bits for L2TAG1 (VLAN),
39 * low 16 bits for others.
41 #define I40E_TX_FLAG_L2TAG1_SHIFT 16
42 #define I40E_TX_FLAG_L2TAG1_MASK 0xffff0000
43 #define I40E_TX_FLAG_CSUM ((uint32_t)(1 << 0))
44 #define I40E_TX_FLAG_INSERT_VLAN ((uint32_t)(1 << 1))
45 #define I40E_TX_FLAG_TSYN ((uint32_t)(1 << 2))
47 #define RTE_PMD_I40E_RX_MAX_BURST 32
48 #define RTE_PMD_I40E_TX_MAX_BURST 32
50 #define RTE_I40E_VPMD_RX_BURST 32
51 #define RTE_I40E_VPMD_TX_BURST 32
52 #define RTE_I40E_RXQ_REARM_THRESH 32
53 #define RTE_I40E_MAX_RX_BURST RTE_I40E_RXQ_REARM_THRESH
54 #define RTE_I40E_TX_MAX_FREE_BUF_SZ 64
55 #define RTE_I40E_DESCS_PER_LOOP 4
57 #define I40E_RXBUF_SZ_1024 1024
58 #define I40E_RXBUF_SZ_2048 2048
61 #define container_of(ptr, type, member) ({ \
62 typeof(((type *)0)->member)(*__mptr) = (ptr); \
63 (type *)((char *)__mptr - offsetof(type, member)); })
65 #define I40E_TD_CMD (I40E_TX_DESC_CMD_ICRC |\
68 enum i40e_header_split_mode {
69 i40e_header_split_none = 0,
70 i40e_header_split_enabled = 1,
71 i40e_header_split_always = 2,
72 i40e_header_split_reserved
75 #define I40E_HEADER_SPLIT_NONE ((uint8_t)0)
76 #define I40E_HEADER_SPLIT_L2 ((uint8_t)(1 << 0))
77 #define I40E_HEADER_SPLIT_IP ((uint8_t)(1 << 1))
78 #define I40E_HEADER_SPLIT_UDP_TCP ((uint8_t)(1 << 2))
79 #define I40E_HEADER_SPLIT_SCTP ((uint8_t)(1 << 3))
80 #define I40E_HEADER_SPLIT_ALL (I40E_HEADER_SPLIT_L2 | \
81 I40E_HEADER_SPLIT_IP | \
82 I40E_HEADER_SPLIT_UDP_TCP | \
83 I40E_HEADER_SPLIT_SCTP)
85 /* HW desc structure, both 16-byte and 32-byte types are supported */
86 #ifdef RTE_LIBRTE_I40E_16BYTE_RX_DESC
87 #define i40e_rx_desc i40e_16byte_rx_desc
89 #define i40e_rx_desc i40e_32byte_rx_desc
92 struct i40e_rx_entry {
93 struct rte_mbuf *mbuf;
97 * Structure associated with each RX queue.
99 struct i40e_rx_queue {
100 struct rte_mempool *mp; /**< mbuf pool to populate RX ring */
101 volatile union i40e_rx_desc *rx_ring;/**< RX ring virtual address */
102 uint64_t rx_ring_phys_addr; /**< RX ring DMA address */
103 struct i40e_rx_entry *sw_ring; /**< address of RX soft ring */
104 uint16_t nb_rx_desc; /**< number of RX descriptors */
105 uint16_t rx_free_thresh; /**< max free RX desc to hold */
106 uint16_t rx_tail; /**< current value of tail */
107 uint16_t nb_rx_hold; /**< number of held free RX desc */
108 struct rte_mbuf *pkt_first_seg; /**< first segment of current packet */
109 struct rte_mbuf *pkt_last_seg; /**< last segment of current packet */
110 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
111 uint16_t rx_nb_avail; /**< number of staged packets ready */
112 uint16_t rx_next_avail; /**< index of next staged packets */
113 uint16_t rx_free_trigger; /**< triggers rx buffer allocation */
114 struct rte_mbuf fake_mbuf; /**< dummy mbuf */
115 struct rte_mbuf *rx_stage[RTE_PMD_I40E_RX_MAX_BURST * 2];
118 uint16_t rxrearm_nb; /**< number of remaining to be re-armed */
119 uint16_t rxrearm_start; /**< the idx we start the re-arming from */
120 uint64_t mbuf_initializer; /**< value to init mbufs */
122 uint8_t port_id; /**< device port ID */
123 uint8_t crc_len; /**< 0 if CRC stripped, 4 otherwise */
124 uint16_t queue_id; /**< RX queue index */
125 uint16_t reg_idx; /**< RX queue register index */
126 uint8_t drop_en; /**< if not 0, set register bit */
127 volatile uint8_t *qrx_tail; /**< register address of tail */
128 struct i40e_vsi *vsi; /**< the VSI this queue belongs to */
129 uint16_t rx_buf_len; /* The packet buffer size */
130 uint16_t rx_hdr_len; /* The header buffer size */
131 uint16_t max_pkt_len; /* Maximum packet length */
132 uint8_t hs_mode; /* Header Split mode */
133 bool q_set; /**< indicate if rx queue has been configured */
134 bool rx_deferred_start; /**< don't start this queue in dev start */
135 uint16_t rx_using_sse; /**<flag indicate the usage of vPMD for rx */
138 struct i40e_tx_entry {
139 struct rte_mbuf *mbuf;
145 * Structure associated with each TX queue.
147 struct i40e_tx_queue {
148 uint16_t nb_tx_desc; /**< number of TX descriptors */
149 uint64_t tx_ring_phys_addr; /**< TX ring DMA address */
150 volatile struct i40e_tx_desc *tx_ring; /**< TX ring virtual address */
151 struct i40e_tx_entry *sw_ring; /**< virtual address of SW ring */
152 uint16_t tx_tail; /**< current value of tail register */
153 volatile uint8_t *qtx_tail; /**< register address of tail */
154 uint16_t nb_tx_used; /**< number of TX desc used since RS bit set */
155 /**< index to last TX descriptor to have been cleaned */
156 uint16_t last_desc_cleaned;
157 /**< Total number of TX descriptors ready to be allocated. */
159 /**< Start freeing TX buffers if there are less free descriptors than
161 uint16_t tx_free_thresh;
162 /** Number of TX descriptors to use before RS bit is set. */
163 uint16_t tx_rs_thresh;
164 uint8_t pthresh; /**< Prefetch threshold register. */
165 uint8_t hthresh; /**< Host threshold register. */
166 uint8_t wthresh; /**< Write-back threshold reg. */
167 uint8_t port_id; /**< Device port identifier. */
168 uint16_t queue_id; /**< TX queue index. */
171 struct i40e_vsi *vsi; /**< the VSI this queue belongs to */
174 bool q_set; /**< indicate if tx queue has been configured */
175 bool tx_deferred_start; /**< don't start this queue in dev start */
178 /** Offload features */
179 union i40e_tx_offload {
182 uint64_t l2_len:7; /**< L2 (MAC) Header Length. */
183 uint64_t l3_len:9; /**< L3 (IP) Header Length. */
184 uint64_t l4_len:8; /**< L4 Header Length. */
185 uint64_t tso_segsz:16; /**< TCP TSO segment size */
186 uint64_t outer_l2_len:8; /**< outer L2 Header Length */
187 uint64_t outer_l3_len:16; /**< outer L3 Header Length */
191 int i40e_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
192 int i40e_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
193 int i40e_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
194 int i40e_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);
195 int i40e_dev_rx_queue_setup(struct rte_eth_dev *dev,
198 unsigned int socket_id,
199 const struct rte_eth_rxconf *rx_conf,
200 struct rte_mempool *mp);
201 int i40e_dev_tx_queue_setup(struct rte_eth_dev *dev,
204 unsigned int socket_id,
205 const struct rte_eth_txconf *tx_conf);
206 void i40e_dev_rx_queue_release(void *rxq);
207 void i40e_dev_tx_queue_release(void *txq);
208 uint16_t i40e_recv_pkts(void *rx_queue,
209 struct rte_mbuf **rx_pkts,
211 uint16_t i40e_recv_scattered_pkts(void *rx_queue,
212 struct rte_mbuf **rx_pkts,
214 uint16_t i40e_xmit_pkts(void *tx_queue,
215 struct rte_mbuf **tx_pkts,
217 int i40e_tx_queue_init(struct i40e_tx_queue *txq);
218 int i40e_rx_queue_init(struct i40e_rx_queue *rxq);
219 void i40e_free_tx_resources(struct i40e_tx_queue *txq);
220 void i40e_free_rx_resources(struct i40e_rx_queue *rxq);
221 void i40e_dev_clear_queues(struct rte_eth_dev *dev);
222 void i40e_dev_free_queues(struct rte_eth_dev *dev);
223 void i40e_reset_rx_queue(struct i40e_rx_queue *rxq);
224 void i40e_reset_tx_queue(struct i40e_tx_queue *txq);
225 void i40e_tx_queue_release_mbufs(struct i40e_tx_queue *txq);
226 int i40e_alloc_rx_queue_mbufs(struct i40e_rx_queue *rxq);
227 void i40e_rx_queue_release_mbufs(struct i40e_rx_queue *rxq);
229 uint32_t i40e_dev_rx_queue_count(struct rte_eth_dev *dev,
230 uint16_t rx_queue_id);
231 int i40e_dev_rx_descriptor_done(void *rx_queue, uint16_t offset);
233 uint16_t i40e_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
235 uint16_t i40e_recv_scattered_pkts_vec(void *rx_queue,
236 struct rte_mbuf **rx_pkts,
238 int i40e_rx_vec_dev_conf_condition_check(struct rte_eth_dev *dev);
239 int i40e_rxq_vec_setup(struct i40e_rx_queue *rxq);
240 int i40e_txq_vec_setup(struct i40e_tx_queue *txq);
241 void i40e_rx_queue_release_mbufs_vec(struct i40e_rx_queue *rxq);
242 uint16_t i40e_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
244 void i40e_set_rx_function(struct rte_eth_dev *dev);
245 void i40e_set_tx_function_flag(struct rte_eth_dev *dev,
246 struct i40e_tx_queue *txq);
247 void i40e_set_tx_function(struct rte_eth_dev *dev);
249 #endif /* _I40E_RXTX_H_ */