4 * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 * 32 bits tx flags, high 16 bits for L2TAG1 (VLAN),
39 * low 16 bits for others.
41 #define I40E_TX_FLAG_L2TAG1_SHIFT 16
42 #define I40E_TX_FLAG_L2TAG1_MASK 0xffff0000
43 #define I40E_TX_FLAG_CSUM ((uint32_t)(1 << 0))
44 #define I40E_TX_FLAG_INSERT_VLAN ((uint32_t)(1 << 1))
45 #define I40E_TX_FLAG_TSYN ((uint32_t)(1 << 2))
47 #define RTE_PMD_I40E_RX_MAX_BURST 32
48 #define RTE_PMD_I40E_TX_MAX_BURST 32
50 #define RTE_I40E_VPMD_RX_BURST 32
51 #define RTE_I40E_VPMD_TX_BURST 32
52 #define RTE_I40E_RXQ_REARM_THRESH 32
53 #define RTE_I40E_MAX_RX_BURST RTE_I40E_RXQ_REARM_THRESH
54 #define RTE_I40E_TX_MAX_FREE_BUF_SZ 64
55 #define RTE_I40E_DESCS_PER_LOOP 4
57 #define I40E_RXBUF_SZ_1024 1024
58 #define I40E_RXBUF_SZ_2048 2048
60 /* In none-PXE mode QLEN must be whole number of 32 descriptors. */
61 #define I40E_ALIGN_RING_DESC 32
63 #define I40E_MIN_RING_DESC 64
64 #define I40E_MAX_RING_DESC 4096
66 #define I40E_MIN_TSO_MSS 256
67 #define I40E_MAX_TSO_MSS 9674
69 #define I40E_TX_MAX_SEG UINT8_MAX
70 #define I40E_TX_MAX_MTU_SEG 8
73 #define container_of(ptr, type, member) ({ \
74 typeof(((type *)0)->member)(*__mptr) = (ptr); \
75 (type *)((char *)__mptr - offsetof(type, member)); })
77 #define I40E_TD_CMD (I40E_TX_DESC_CMD_ICRC |\
80 enum i40e_header_split_mode {
81 i40e_header_split_none = 0,
82 i40e_header_split_enabled = 1,
83 i40e_header_split_always = 2,
84 i40e_header_split_reserved
87 #define I40E_HEADER_SPLIT_NONE ((uint8_t)0)
88 #define I40E_HEADER_SPLIT_L2 ((uint8_t)(1 << 0))
89 #define I40E_HEADER_SPLIT_IP ((uint8_t)(1 << 1))
90 #define I40E_HEADER_SPLIT_UDP_TCP ((uint8_t)(1 << 2))
91 #define I40E_HEADER_SPLIT_SCTP ((uint8_t)(1 << 3))
92 #define I40E_HEADER_SPLIT_ALL (I40E_HEADER_SPLIT_L2 | \
93 I40E_HEADER_SPLIT_IP | \
94 I40E_HEADER_SPLIT_UDP_TCP | \
95 I40E_HEADER_SPLIT_SCTP)
97 /* HW desc structure, both 16-byte and 32-byte types are supported */
98 #ifdef RTE_LIBRTE_I40E_16BYTE_RX_DESC
99 #define i40e_rx_desc i40e_16byte_rx_desc
101 #define i40e_rx_desc i40e_32byte_rx_desc
104 struct i40e_rx_entry {
105 struct rte_mbuf *mbuf;
109 * Structure associated with each RX queue.
111 struct i40e_rx_queue {
112 struct rte_mempool *mp; /**< mbuf pool to populate RX ring */
113 volatile union i40e_rx_desc *rx_ring;/**< RX ring virtual address */
114 uint64_t rx_ring_phys_addr; /**< RX ring DMA address */
115 struct i40e_rx_entry *sw_ring; /**< address of RX soft ring */
116 uint16_t nb_rx_desc; /**< number of RX descriptors */
117 uint16_t rx_free_thresh; /**< max free RX desc to hold */
118 uint16_t rx_tail; /**< current value of tail */
119 uint16_t nb_rx_hold; /**< number of held free RX desc */
120 struct rte_mbuf *pkt_first_seg; /**< first segment of current packet */
121 struct rte_mbuf *pkt_last_seg; /**< last segment of current packet */
122 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
123 uint16_t rx_nb_avail; /**< number of staged packets ready */
124 uint16_t rx_next_avail; /**< index of next staged packets */
125 uint16_t rx_free_trigger; /**< triggers rx buffer allocation */
126 struct rte_mbuf fake_mbuf; /**< dummy mbuf */
127 struct rte_mbuf *rx_stage[RTE_PMD_I40E_RX_MAX_BURST * 2];
130 uint16_t rxrearm_nb; /**< number of remaining to be re-armed */
131 uint16_t rxrearm_start; /**< the idx we start the re-arming from */
132 uint64_t mbuf_initializer; /**< value to init mbufs */
134 uint8_t port_id; /**< device port ID */
135 uint8_t crc_len; /**< 0 if CRC stripped, 4 otherwise */
136 uint16_t queue_id; /**< RX queue index */
137 uint16_t reg_idx; /**< RX queue register index */
138 uint8_t drop_en; /**< if not 0, set register bit */
139 volatile uint8_t *qrx_tail; /**< register address of tail */
140 struct i40e_vsi *vsi; /**< the VSI this queue belongs to */
141 uint16_t rx_buf_len; /* The packet buffer size */
142 uint16_t rx_hdr_len; /* The header buffer size */
143 uint16_t max_pkt_len; /* Maximum packet length */
144 uint8_t hs_mode; /* Header Split mode */
145 bool q_set; /**< indicate if rx queue has been configured */
146 bool rx_deferred_start; /**< don't start this queue in dev start */
147 uint16_t rx_using_sse; /**<flag indicate the usage of vPMD for rx */
148 uint8_t dcb_tc; /**< Traffic class of rx queue */
151 struct i40e_tx_entry {
152 struct rte_mbuf *mbuf;
158 * Structure associated with each TX queue.
160 struct i40e_tx_queue {
161 uint16_t nb_tx_desc; /**< number of TX descriptors */
162 uint64_t tx_ring_phys_addr; /**< TX ring DMA address */
163 volatile struct i40e_tx_desc *tx_ring; /**< TX ring virtual address */
164 struct i40e_tx_entry *sw_ring; /**< virtual address of SW ring */
165 uint16_t tx_tail; /**< current value of tail register */
166 volatile uint8_t *qtx_tail; /**< register address of tail */
167 uint16_t nb_tx_used; /**< number of TX desc used since RS bit set */
168 /**< index to last TX descriptor to have been cleaned */
169 uint16_t last_desc_cleaned;
170 /**< Total number of TX descriptors ready to be allocated. */
172 /**< Start freeing TX buffers if there are less free descriptors than
174 uint16_t tx_free_thresh;
175 /** Number of TX descriptors to use before RS bit is set. */
176 uint16_t tx_rs_thresh;
177 uint8_t pthresh; /**< Prefetch threshold register. */
178 uint8_t hthresh; /**< Host threshold register. */
179 uint8_t wthresh; /**< Write-back threshold reg. */
180 uint8_t port_id; /**< Device port identifier. */
181 uint16_t queue_id; /**< TX queue index. */
184 struct i40e_vsi *vsi; /**< the VSI this queue belongs to */
187 bool q_set; /**< indicate if tx queue has been configured */
188 bool tx_deferred_start; /**< don't start this queue in dev start */
189 uint8_t dcb_tc; /**< Traffic class of tx queue */
192 /** Offload features */
193 union i40e_tx_offload {
196 uint64_t l2_len:7; /**< L2 (MAC) Header Length. */
197 uint64_t l3_len:9; /**< L3 (IP) Header Length. */
198 uint64_t l4_len:8; /**< L4 Header Length. */
199 uint64_t tso_segsz:16; /**< TCP TSO segment size */
200 uint64_t outer_l2_len:8; /**< outer L2 Header Length */
201 uint64_t outer_l3_len:16; /**< outer L3 Header Length */
205 int i40e_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
206 int i40e_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
207 int i40e_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
208 int i40e_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);
209 const uint32_t *i40e_dev_supported_ptypes_get(struct rte_eth_dev *dev);
210 int i40e_dev_rx_queue_setup(struct rte_eth_dev *dev,
213 unsigned int socket_id,
214 const struct rte_eth_rxconf *rx_conf,
215 struct rte_mempool *mp);
216 int i40e_dev_tx_queue_setup(struct rte_eth_dev *dev,
219 unsigned int socket_id,
220 const struct rte_eth_txconf *tx_conf);
221 void i40e_dev_rx_queue_release(void *rxq);
222 void i40e_dev_tx_queue_release(void *txq);
223 uint16_t i40e_recv_pkts(void *rx_queue,
224 struct rte_mbuf **rx_pkts,
226 uint16_t i40e_recv_scattered_pkts(void *rx_queue,
227 struct rte_mbuf **rx_pkts,
229 uint16_t i40e_xmit_pkts(void *tx_queue,
230 struct rte_mbuf **tx_pkts,
232 uint16_t i40e_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
234 int i40e_tx_queue_init(struct i40e_tx_queue *txq);
235 int i40e_rx_queue_init(struct i40e_rx_queue *rxq);
236 void i40e_free_tx_resources(struct i40e_tx_queue *txq);
237 void i40e_free_rx_resources(struct i40e_rx_queue *rxq);
238 void i40e_dev_clear_queues(struct rte_eth_dev *dev);
239 void i40e_dev_free_queues(struct rte_eth_dev *dev);
240 void i40e_reset_rx_queue(struct i40e_rx_queue *rxq);
241 void i40e_reset_tx_queue(struct i40e_tx_queue *txq);
242 void i40e_tx_queue_release_mbufs(struct i40e_tx_queue *txq);
243 int i40e_alloc_rx_queue_mbufs(struct i40e_rx_queue *rxq);
244 void i40e_rx_queue_release_mbufs(struct i40e_rx_queue *rxq);
246 uint32_t i40e_dev_rx_queue_count(struct rte_eth_dev *dev,
247 uint16_t rx_queue_id);
248 int i40e_dev_rx_descriptor_done(void *rx_queue, uint16_t offset);
250 uint16_t i40e_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
252 uint16_t i40e_recv_scattered_pkts_vec(void *rx_queue,
253 struct rte_mbuf **rx_pkts,
255 int i40e_rx_vec_dev_conf_condition_check(struct rte_eth_dev *dev);
256 int i40e_rxq_vec_setup(struct i40e_rx_queue *rxq);
257 int i40e_txq_vec_setup(struct i40e_tx_queue *txq);
258 void i40e_rx_queue_release_mbufs_vec(struct i40e_rx_queue *rxq);
259 uint16_t i40e_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
261 void i40e_set_rx_function(struct rte_eth_dev *dev);
262 void i40e_set_tx_function_flag(struct rte_eth_dev *dev,
263 struct i40e_tx_queue *txq);
264 void i40e_set_tx_function(struct rte_eth_dev *dev);
266 /* For each value it means, datasheet of hardware can tell more details
268 * @note: fix i40e_dev_supported_ptypes_get() if any change here.
270 static inline uint32_t
271 i40e_rxd_pkt_type_mapping(uint8_t ptype)
273 static const uint32_t type_table[UINT8_MAX + 1] __rte_cache_aligned = {
276 [1] = RTE_PTYPE_L2_ETHER,
277 [2] = RTE_PTYPE_L2_ETHER_TIMESYNC,
278 /* [3] - [5] reserved */
279 [6] = RTE_PTYPE_L2_ETHER_LLDP,
280 /* [7] - [10] reserved */
281 [11] = RTE_PTYPE_L2_ETHER_ARP,
282 /* [12] - [21] reserved */
284 /* Non tunneled IPv4 */
285 [22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
287 [23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
288 RTE_PTYPE_L4_NONFRAG,
289 [24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
292 [26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
294 [27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
296 [28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
300 [29] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
301 RTE_PTYPE_TUNNEL_IP |
302 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
303 RTE_PTYPE_INNER_L4_FRAG,
304 [30] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
305 RTE_PTYPE_TUNNEL_IP |
306 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
307 RTE_PTYPE_INNER_L4_NONFRAG,
308 [31] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
309 RTE_PTYPE_TUNNEL_IP |
310 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
311 RTE_PTYPE_INNER_L4_UDP,
313 [33] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
314 RTE_PTYPE_TUNNEL_IP |
315 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
316 RTE_PTYPE_INNER_L4_TCP,
317 [34] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
318 RTE_PTYPE_TUNNEL_IP |
319 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
320 RTE_PTYPE_INNER_L4_SCTP,
321 [35] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
322 RTE_PTYPE_TUNNEL_IP |
323 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
324 RTE_PTYPE_INNER_L4_ICMP,
327 [36] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
328 RTE_PTYPE_TUNNEL_IP |
329 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
330 RTE_PTYPE_INNER_L4_FRAG,
331 [37] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
332 RTE_PTYPE_TUNNEL_IP |
333 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
334 RTE_PTYPE_INNER_L4_NONFRAG,
335 [38] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
336 RTE_PTYPE_TUNNEL_IP |
337 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
338 RTE_PTYPE_INNER_L4_UDP,
340 [40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
341 RTE_PTYPE_TUNNEL_IP |
342 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
343 RTE_PTYPE_INNER_L4_TCP,
344 [41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
345 RTE_PTYPE_TUNNEL_IP |
346 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
347 RTE_PTYPE_INNER_L4_SCTP,
348 [42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
349 RTE_PTYPE_TUNNEL_IP |
350 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
351 RTE_PTYPE_INNER_L4_ICMP,
353 /* IPv4 --> GRE/Teredo/VXLAN */
354 [43] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
355 RTE_PTYPE_TUNNEL_GRENAT,
357 /* IPv4 --> GRE/Teredo/VXLAN --> IPv4 */
358 [44] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
359 RTE_PTYPE_TUNNEL_GRENAT |
360 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
361 RTE_PTYPE_INNER_L4_FRAG,
362 [45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
363 RTE_PTYPE_TUNNEL_GRENAT |
364 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
365 RTE_PTYPE_INNER_L4_NONFRAG,
366 [46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
367 RTE_PTYPE_TUNNEL_GRENAT |
368 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
369 RTE_PTYPE_INNER_L4_UDP,
371 [48] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
372 RTE_PTYPE_TUNNEL_GRENAT |
373 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
374 RTE_PTYPE_INNER_L4_TCP,
375 [49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
376 RTE_PTYPE_TUNNEL_GRENAT |
377 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
378 RTE_PTYPE_INNER_L4_SCTP,
379 [50] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
380 RTE_PTYPE_TUNNEL_GRENAT |
381 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
382 RTE_PTYPE_INNER_L4_ICMP,
384 /* IPv4 --> GRE/Teredo/VXLAN --> IPv6 */
385 [51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
386 RTE_PTYPE_TUNNEL_GRENAT |
387 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
388 RTE_PTYPE_INNER_L4_FRAG,
389 [52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
390 RTE_PTYPE_TUNNEL_GRENAT |
391 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
392 RTE_PTYPE_INNER_L4_NONFRAG,
393 [53] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
394 RTE_PTYPE_TUNNEL_GRENAT |
395 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
396 RTE_PTYPE_INNER_L4_UDP,
398 [55] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
399 RTE_PTYPE_TUNNEL_GRENAT |
400 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
401 RTE_PTYPE_INNER_L4_TCP,
402 [56] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
403 RTE_PTYPE_TUNNEL_GRENAT |
404 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
405 RTE_PTYPE_INNER_L4_SCTP,
406 [57] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
407 RTE_PTYPE_TUNNEL_GRENAT |
408 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
409 RTE_PTYPE_INNER_L4_ICMP,
411 /* IPv4 --> GRE/Teredo/VXLAN --> MAC */
412 [58] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
413 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
415 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
416 [59] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
417 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
418 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
419 RTE_PTYPE_INNER_L4_FRAG,
420 [60] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
421 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
422 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
423 RTE_PTYPE_INNER_L4_NONFRAG,
424 [61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
425 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
426 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
427 RTE_PTYPE_INNER_L4_UDP,
429 [63] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
430 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
431 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
432 RTE_PTYPE_INNER_L4_TCP,
433 [64] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
434 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
435 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
436 RTE_PTYPE_INNER_L4_SCTP,
437 [65] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
438 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
439 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
440 RTE_PTYPE_INNER_L4_ICMP,
442 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
443 [66] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
444 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
445 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
446 RTE_PTYPE_INNER_L4_FRAG,
447 [67] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
448 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
449 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
450 RTE_PTYPE_INNER_L4_NONFRAG,
451 [68] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
452 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
453 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
454 RTE_PTYPE_INNER_L4_UDP,
456 [70] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
457 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
458 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
459 RTE_PTYPE_INNER_L4_TCP,
460 [71] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
461 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
462 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
463 RTE_PTYPE_INNER_L4_SCTP,
464 [72] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
465 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
466 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
467 RTE_PTYPE_INNER_L4_ICMP,
469 /* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN */
470 [73] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
471 RTE_PTYPE_TUNNEL_GRENAT |
472 RTE_PTYPE_INNER_L2_ETHER_VLAN,
474 /* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv4 */
475 [74] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
476 RTE_PTYPE_TUNNEL_GRENAT |
477 RTE_PTYPE_INNER_L2_ETHER_VLAN |
478 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
479 RTE_PTYPE_INNER_L4_FRAG,
480 [75] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
481 RTE_PTYPE_TUNNEL_GRENAT |
482 RTE_PTYPE_INNER_L2_ETHER_VLAN |
483 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
484 RTE_PTYPE_INNER_L4_NONFRAG,
485 [76] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
486 RTE_PTYPE_TUNNEL_GRENAT |
487 RTE_PTYPE_INNER_L2_ETHER_VLAN |
488 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
489 RTE_PTYPE_INNER_L4_UDP,
491 [78] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
492 RTE_PTYPE_TUNNEL_GRENAT |
493 RTE_PTYPE_INNER_L2_ETHER_VLAN |
494 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
495 RTE_PTYPE_INNER_L4_TCP,
496 [79] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
497 RTE_PTYPE_TUNNEL_GRENAT |
498 RTE_PTYPE_INNER_L2_ETHER_VLAN |
499 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
500 RTE_PTYPE_INNER_L4_SCTP,
501 [80] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
502 RTE_PTYPE_TUNNEL_GRENAT |
503 RTE_PTYPE_INNER_L2_ETHER_VLAN |
504 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
505 RTE_PTYPE_INNER_L4_ICMP,
507 /* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv6 */
508 [81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
509 RTE_PTYPE_TUNNEL_GRENAT |
510 RTE_PTYPE_INNER_L2_ETHER_VLAN |
511 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
512 RTE_PTYPE_INNER_L4_FRAG,
513 [82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
514 RTE_PTYPE_TUNNEL_GRENAT |
515 RTE_PTYPE_INNER_L2_ETHER_VLAN |
516 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
517 RTE_PTYPE_INNER_L4_NONFRAG,
518 [83] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
519 RTE_PTYPE_TUNNEL_GRENAT |
520 RTE_PTYPE_INNER_L2_ETHER_VLAN |
521 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
522 RTE_PTYPE_INNER_L4_UDP,
524 [85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
525 RTE_PTYPE_TUNNEL_GRENAT |
526 RTE_PTYPE_INNER_L2_ETHER_VLAN |
527 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
528 RTE_PTYPE_INNER_L4_TCP,
529 [86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
530 RTE_PTYPE_TUNNEL_GRENAT |
531 RTE_PTYPE_INNER_L2_ETHER_VLAN |
532 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
533 RTE_PTYPE_INNER_L4_SCTP,
534 [87] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
535 RTE_PTYPE_TUNNEL_GRENAT |
536 RTE_PTYPE_INNER_L2_ETHER_VLAN |
537 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
538 RTE_PTYPE_INNER_L4_ICMP,
540 /* Non tunneled IPv6 */
541 [88] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
543 [89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
544 RTE_PTYPE_L4_NONFRAG,
545 [90] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
548 [92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
550 [93] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
552 [94] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
556 [95] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
557 RTE_PTYPE_TUNNEL_IP |
558 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
559 RTE_PTYPE_INNER_L4_FRAG,
560 [96] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
561 RTE_PTYPE_TUNNEL_IP |
562 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
563 RTE_PTYPE_INNER_L4_NONFRAG,
564 [97] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
565 RTE_PTYPE_TUNNEL_IP |
566 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
567 RTE_PTYPE_INNER_L4_UDP,
569 [99] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
570 RTE_PTYPE_TUNNEL_IP |
571 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
572 RTE_PTYPE_INNER_L4_TCP,
573 [100] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
574 RTE_PTYPE_TUNNEL_IP |
575 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
576 RTE_PTYPE_INNER_L4_SCTP,
577 [101] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
578 RTE_PTYPE_TUNNEL_IP |
579 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
580 RTE_PTYPE_INNER_L4_ICMP,
583 [102] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
584 RTE_PTYPE_TUNNEL_IP |
585 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
586 RTE_PTYPE_INNER_L4_FRAG,
587 [103] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
588 RTE_PTYPE_TUNNEL_IP |
589 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
590 RTE_PTYPE_INNER_L4_NONFRAG,
591 [104] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
592 RTE_PTYPE_TUNNEL_IP |
593 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
594 RTE_PTYPE_INNER_L4_UDP,
596 [106] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
597 RTE_PTYPE_TUNNEL_IP |
598 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
599 RTE_PTYPE_INNER_L4_TCP,
600 [107] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
601 RTE_PTYPE_TUNNEL_IP |
602 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
603 RTE_PTYPE_INNER_L4_SCTP,
604 [108] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
605 RTE_PTYPE_TUNNEL_IP |
606 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
607 RTE_PTYPE_INNER_L4_ICMP,
609 /* IPv6 --> GRE/Teredo/VXLAN */
610 [109] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
611 RTE_PTYPE_TUNNEL_GRENAT,
613 /* IPv6 --> GRE/Teredo/VXLAN --> IPv4 */
614 [110] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
615 RTE_PTYPE_TUNNEL_GRENAT |
616 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
617 RTE_PTYPE_INNER_L4_FRAG,
618 [111] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
619 RTE_PTYPE_TUNNEL_GRENAT |
620 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
621 RTE_PTYPE_INNER_L4_NONFRAG,
622 [112] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
623 RTE_PTYPE_TUNNEL_GRENAT |
624 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
625 RTE_PTYPE_INNER_L4_UDP,
627 [114] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
628 RTE_PTYPE_TUNNEL_GRENAT |
629 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
630 RTE_PTYPE_INNER_L4_TCP,
631 [115] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
632 RTE_PTYPE_TUNNEL_GRENAT |
633 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
634 RTE_PTYPE_INNER_L4_SCTP,
635 [116] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
636 RTE_PTYPE_TUNNEL_GRENAT |
637 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
638 RTE_PTYPE_INNER_L4_ICMP,
640 /* IPv6 --> GRE/Teredo/VXLAN --> IPv6 */
641 [117] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
642 RTE_PTYPE_TUNNEL_GRENAT |
643 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
644 RTE_PTYPE_INNER_L4_FRAG,
645 [118] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
646 RTE_PTYPE_TUNNEL_GRENAT |
647 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
648 RTE_PTYPE_INNER_L4_NONFRAG,
649 [119] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
650 RTE_PTYPE_TUNNEL_GRENAT |
651 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
652 RTE_PTYPE_INNER_L4_UDP,
654 [121] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
655 RTE_PTYPE_TUNNEL_GRENAT |
656 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
657 RTE_PTYPE_INNER_L4_TCP,
658 [122] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
659 RTE_PTYPE_TUNNEL_GRENAT |
660 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
661 RTE_PTYPE_INNER_L4_SCTP,
662 [123] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
663 RTE_PTYPE_TUNNEL_GRENAT |
664 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
665 RTE_PTYPE_INNER_L4_ICMP,
667 /* IPv6 --> GRE/Teredo/VXLAN --> MAC */
668 [124] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
669 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
671 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
672 [125] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
673 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
674 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
675 RTE_PTYPE_INNER_L4_FRAG,
676 [126] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
677 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
678 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
679 RTE_PTYPE_INNER_L4_NONFRAG,
680 [127] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
681 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
682 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
683 RTE_PTYPE_INNER_L4_UDP,
685 [129] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
686 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
687 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
688 RTE_PTYPE_INNER_L4_TCP,
689 [130] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
690 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
691 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
692 RTE_PTYPE_INNER_L4_SCTP,
693 [131] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
694 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
695 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
696 RTE_PTYPE_INNER_L4_ICMP,
698 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
699 [132] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
700 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
701 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
702 RTE_PTYPE_INNER_L4_FRAG,
703 [133] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
704 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
705 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
706 RTE_PTYPE_INNER_L4_NONFRAG,
707 [134] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
708 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
709 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
710 RTE_PTYPE_INNER_L4_UDP,
712 [136] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
713 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
714 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
715 RTE_PTYPE_INNER_L4_TCP,
716 [137] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
717 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
718 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
719 RTE_PTYPE_INNER_L4_SCTP,
720 [138] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
721 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
722 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
723 RTE_PTYPE_INNER_L4_ICMP,
725 /* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN */
726 [139] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
727 RTE_PTYPE_TUNNEL_GRENAT |
728 RTE_PTYPE_INNER_L2_ETHER_VLAN,
730 /* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv4 */
731 [140] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
732 RTE_PTYPE_TUNNEL_GRENAT |
733 RTE_PTYPE_INNER_L2_ETHER_VLAN |
734 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
735 RTE_PTYPE_INNER_L4_FRAG,
736 [141] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
737 RTE_PTYPE_TUNNEL_GRENAT |
738 RTE_PTYPE_INNER_L2_ETHER_VLAN |
739 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
740 RTE_PTYPE_INNER_L4_NONFRAG,
741 [142] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
742 RTE_PTYPE_TUNNEL_GRENAT |
743 RTE_PTYPE_INNER_L2_ETHER_VLAN |
744 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
745 RTE_PTYPE_INNER_L4_UDP,
747 [144] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
748 RTE_PTYPE_TUNNEL_GRENAT |
749 RTE_PTYPE_INNER_L2_ETHER_VLAN |
750 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
751 RTE_PTYPE_INNER_L4_TCP,
752 [145] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
753 RTE_PTYPE_TUNNEL_GRENAT |
754 RTE_PTYPE_INNER_L2_ETHER_VLAN |
755 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
756 RTE_PTYPE_INNER_L4_SCTP,
757 [146] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
758 RTE_PTYPE_TUNNEL_GRENAT |
759 RTE_PTYPE_INNER_L2_ETHER_VLAN |
760 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
761 RTE_PTYPE_INNER_L4_ICMP,
763 /* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv6 */
764 [147] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
765 RTE_PTYPE_TUNNEL_GRENAT |
766 RTE_PTYPE_INNER_L2_ETHER_VLAN |
767 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
768 RTE_PTYPE_INNER_L4_FRAG,
769 [148] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
770 RTE_PTYPE_TUNNEL_GRENAT |
771 RTE_PTYPE_INNER_L2_ETHER_VLAN |
772 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
773 RTE_PTYPE_INNER_L4_NONFRAG,
774 [149] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
775 RTE_PTYPE_TUNNEL_GRENAT |
776 RTE_PTYPE_INNER_L2_ETHER_VLAN |
777 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
778 RTE_PTYPE_INNER_L4_UDP,
780 [151] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
781 RTE_PTYPE_TUNNEL_GRENAT |
782 RTE_PTYPE_INNER_L2_ETHER_VLAN |
783 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
784 RTE_PTYPE_INNER_L4_TCP,
785 [152] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
786 RTE_PTYPE_TUNNEL_GRENAT |
787 RTE_PTYPE_INNER_L2_ETHER_VLAN |
788 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
789 RTE_PTYPE_INNER_L4_SCTP,
790 [153] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
791 RTE_PTYPE_TUNNEL_GRENAT |
792 RTE_PTYPE_INNER_L2_ETHER_VLAN |
793 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
794 RTE_PTYPE_INNER_L4_ICMP,
796 /* L2 NSH packet type */
797 [154] = RTE_PTYPE_L2_ETHER_NSH,
798 [155] = RTE_PTYPE_L2_ETHER_NSH | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
800 [156] = RTE_PTYPE_L2_ETHER_NSH | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
801 RTE_PTYPE_L4_NONFRAG,
802 [157] = RTE_PTYPE_L2_ETHER_NSH | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
804 [158] = RTE_PTYPE_L2_ETHER_NSH | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
806 [159] = RTE_PTYPE_L2_ETHER_NSH | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
808 [160] = RTE_PTYPE_L2_ETHER_NSH | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
810 [161] = RTE_PTYPE_L2_ETHER_NSH | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
812 [162] = RTE_PTYPE_L2_ETHER_NSH | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
813 RTE_PTYPE_L4_NONFRAG,
814 [163] = RTE_PTYPE_L2_ETHER_NSH | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
816 [164] = RTE_PTYPE_L2_ETHER_NSH | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
818 [165] = RTE_PTYPE_L2_ETHER_NSH | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
820 [166] = RTE_PTYPE_L2_ETHER_NSH | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
823 /* All others reserved */
826 return type_table[ptype];
829 #endif /* _I40E_RXTX_H_ */