1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2015 Intel Corporation
8 #define RTE_PMD_I40E_RX_MAX_BURST 32
9 #define RTE_PMD_I40E_TX_MAX_BURST 32
11 #define RTE_I40E_VPMD_RX_BURST 32
12 #define RTE_I40E_VPMD_TX_BURST 32
13 #define RTE_I40E_RXQ_REARM_THRESH 32
14 #define RTE_I40E_MAX_RX_BURST RTE_I40E_RXQ_REARM_THRESH
15 #define RTE_I40E_TX_MAX_FREE_BUF_SZ 64
16 #define RTE_I40E_DESCS_PER_LOOP 4
18 #define I40E_RXBUF_SZ_1024 1024
19 #define I40E_RXBUF_SZ_2048 2048
21 /* In none-PXE mode QLEN must be whole number of 32 descriptors. */
22 #define I40E_ALIGN_RING_DESC 32
24 #define I40E_MIN_RING_DESC 64
25 #define I40E_MAX_RING_DESC 4096
27 #define I40E_FDIR_NUM_TX_DESC (I40E_FDIR_PRG_PKT_CNT << 1)
28 #define I40E_FDIR_NUM_RX_DESC (I40E_FDIR_PRG_PKT_CNT << 1)
30 #define I40E_MIN_TSO_MSS 256
31 #define I40E_MAX_TSO_MSS 9674
33 #define I40E_TX_MAX_SEG UINT8_MAX
34 #define I40E_TX_MAX_MTU_SEG 8
36 #define I40E_TX_MIN_PKT_LEN 17
38 /* Shared FDIR masks between scalar / vector drivers */
39 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK 0x03
40 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID 0x01
41 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX 0x02
42 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK 0x03
43 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX 0x01
46 #define container_of(ptr, type, member) ({ \
47 typeof(((type *)0)->member)(*__mptr) = (ptr); \
48 (type *)((char *)__mptr - offsetof(type, member)); })
50 #define I40E_TD_CMD (I40E_TX_DESC_CMD_ICRC |\
53 enum i40e_header_split_mode {
54 i40e_header_split_none = 0,
55 i40e_header_split_enabled = 1,
56 i40e_header_split_always = 2,
57 i40e_header_split_reserved
60 #define I40E_HEADER_SPLIT_NONE ((uint8_t)0)
61 #define I40E_HEADER_SPLIT_L2 ((uint8_t)(1 << 0))
62 #define I40E_HEADER_SPLIT_IP ((uint8_t)(1 << 1))
63 #define I40E_HEADER_SPLIT_UDP_TCP ((uint8_t)(1 << 2))
64 #define I40E_HEADER_SPLIT_SCTP ((uint8_t)(1 << 3))
65 #define I40E_HEADER_SPLIT_ALL (I40E_HEADER_SPLIT_L2 | \
66 I40E_HEADER_SPLIT_IP | \
67 I40E_HEADER_SPLIT_UDP_TCP | \
68 I40E_HEADER_SPLIT_SCTP)
70 /* HW desc structure, both 16-byte and 32-byte types are supported */
71 #ifdef RTE_LIBRTE_I40E_16BYTE_RX_DESC
72 #define i40e_rx_desc i40e_16byte_rx_desc
74 #define i40e_rx_desc i40e_32byte_rx_desc
77 struct i40e_rx_entry {
78 struct rte_mbuf *mbuf;
82 * Structure associated with each RX queue.
84 struct i40e_rx_queue {
85 struct rte_mempool *mp; /**< mbuf pool to populate RX ring */
86 volatile union i40e_rx_desc *rx_ring;/**< RX ring virtual address */
87 uint64_t rx_ring_phys_addr; /**< RX ring DMA address */
88 struct i40e_rx_entry *sw_ring; /**< address of RX soft ring */
89 uint16_t nb_rx_desc; /**< number of RX descriptors */
90 uint16_t rx_free_thresh; /**< max free RX desc to hold */
91 uint16_t rx_tail; /**< current value of tail */
92 uint16_t nb_rx_hold; /**< number of held free RX desc */
93 struct rte_mbuf *pkt_first_seg; /**< first segment of current packet */
94 struct rte_mbuf *pkt_last_seg; /**< last segment of current packet */
95 struct rte_mbuf fake_mbuf; /**< dummy mbuf */
96 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
97 uint16_t rx_nb_avail; /**< number of staged packets ready */
98 uint16_t rx_next_avail; /**< index of next staged packets */
99 uint16_t rx_free_trigger; /**< triggers rx buffer allocation */
100 struct rte_mbuf *rx_stage[RTE_PMD_I40E_RX_MAX_BURST * 2];
103 uint16_t rxrearm_nb; /**< number of remaining to be re-armed */
104 uint16_t rxrearm_start; /**< the idx we start the re-arming from */
105 uint64_t mbuf_initializer; /**< value to init mbufs */
107 uint16_t port_id; /**< device port ID */
108 uint8_t crc_len; /**< 0 if CRC stripped, 4 otherwise */
109 uint8_t fdir_enabled; /**< 0 if FDIR disabled, 1 when enabled */
110 uint16_t queue_id; /**< RX queue index */
111 uint16_t reg_idx; /**< RX queue register index */
112 uint8_t drop_en; /**< if not 0, set register bit */
113 volatile uint8_t *qrx_tail; /**< register address of tail */
114 struct i40e_vsi *vsi; /**< the VSI this queue belongs to */
115 uint16_t rx_buf_len; /* The packet buffer size */
116 uint16_t rx_hdr_len; /* The header buffer size */
117 uint16_t max_pkt_len; /* Maximum packet length */
118 uint8_t hs_mode; /* Header Split mode */
119 bool q_set; /**< indicate if rx queue has been configured */
120 bool rx_deferred_start; /**< don't start this queue in dev start */
121 uint16_t rx_using_sse; /**<flag indicate the usage of vPMD for rx */
122 uint8_t dcb_tc; /**< Traffic class of rx queue */
123 uint64_t offloads; /**< Rx offload flags of DEV_RX_OFFLOAD_* */
126 struct i40e_tx_entry {
127 struct rte_mbuf *mbuf;
133 * Structure associated with each TX queue.
135 struct i40e_tx_queue {
136 uint16_t nb_tx_desc; /**< number of TX descriptors */
137 uint64_t tx_ring_phys_addr; /**< TX ring DMA address */
138 volatile struct i40e_tx_desc *tx_ring; /**< TX ring virtual address */
139 struct i40e_tx_entry *sw_ring; /**< virtual address of SW ring */
140 uint16_t tx_tail; /**< current value of tail register */
141 volatile uint8_t *qtx_tail; /**< register address of tail */
142 uint16_t nb_tx_used; /**< number of TX desc used since RS bit set */
143 /**< index to last TX descriptor to have been cleaned */
144 uint16_t last_desc_cleaned;
145 /**< Total number of TX descriptors ready to be allocated. */
147 /**< Start freeing TX buffers if there are less free descriptors than
149 uint16_t tx_free_thresh;
150 /** Number of TX descriptors to use before RS bit is set. */
151 uint16_t tx_rs_thresh;
152 uint8_t pthresh; /**< Prefetch threshold register. */
153 uint8_t hthresh; /**< Host threshold register. */
154 uint8_t wthresh; /**< Write-back threshold reg. */
155 uint16_t port_id; /**< Device port identifier. */
156 uint16_t queue_id; /**< TX queue index. */
158 struct i40e_vsi *vsi; /**< the VSI this queue belongs to */
161 bool q_set; /**< indicate if tx queue has been configured */
162 bool tx_deferred_start; /**< don't start this queue in dev start */
163 uint8_t dcb_tc; /**< Traffic class of tx queue */
164 uint64_t offloads; /**< Tx offload flags of DEV_RX_OFFLOAD_* */
167 /** Offload features */
168 union i40e_tx_offload {
171 uint64_t l2_len:7; /**< L2 (MAC) Header Length. */
172 uint64_t l3_len:9; /**< L3 (IP) Header Length. */
173 uint64_t l4_len:8; /**< L4 Header Length. */
174 uint64_t tso_segsz:16; /**< TCP TSO segment size */
175 uint64_t outer_l2_len:8; /**< outer L2 Header Length */
176 uint64_t outer_l3_len:16; /**< outer L3 Header Length */
180 int i40e_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
181 int i40e_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
182 int i40e_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
183 int i40e_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);
184 const uint32_t *i40e_dev_supported_ptypes_get(struct rte_eth_dev *dev);
185 int i40e_dev_rx_queue_setup(struct rte_eth_dev *dev,
188 unsigned int socket_id,
189 const struct rte_eth_rxconf *rx_conf,
190 struct rte_mempool *mp);
191 int i40e_dev_tx_queue_setup(struct rte_eth_dev *dev,
194 unsigned int socket_id,
195 const struct rte_eth_txconf *tx_conf);
196 void i40e_dev_rx_queue_release(void *rxq);
197 void i40e_dev_tx_queue_release(void *txq);
198 uint16_t i40e_recv_pkts(void *rx_queue,
199 struct rte_mbuf **rx_pkts,
201 uint16_t i40e_recv_scattered_pkts(void *rx_queue,
202 struct rte_mbuf **rx_pkts,
204 uint16_t i40e_xmit_pkts(void *tx_queue,
205 struct rte_mbuf **tx_pkts,
207 uint16_t i40e_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
209 int i40e_tx_queue_init(struct i40e_tx_queue *txq);
210 int i40e_rx_queue_init(struct i40e_rx_queue *rxq);
211 void i40e_free_tx_resources(struct i40e_tx_queue *txq);
212 void i40e_free_rx_resources(struct i40e_rx_queue *rxq);
213 void i40e_dev_clear_queues(struct rte_eth_dev *dev);
214 void i40e_dev_free_queues(struct rte_eth_dev *dev);
215 void i40e_reset_rx_queue(struct i40e_rx_queue *rxq);
216 void i40e_reset_tx_queue(struct i40e_tx_queue *txq);
217 void i40e_tx_queue_release_mbufs(struct i40e_tx_queue *txq);
218 int i40e_tx_done_cleanup(void *txq, uint32_t free_cnt);
219 int i40e_alloc_rx_queue_mbufs(struct i40e_rx_queue *rxq);
220 void i40e_rx_queue_release_mbufs(struct i40e_rx_queue *rxq);
222 uint32_t i40e_dev_rx_queue_count(struct rte_eth_dev *dev,
223 uint16_t rx_queue_id);
224 int i40e_dev_rx_descriptor_done(void *rx_queue, uint16_t offset);
225 int i40e_dev_rx_descriptor_status(void *rx_queue, uint16_t offset);
226 int i40e_dev_tx_descriptor_status(void *tx_queue, uint16_t offset);
228 uint16_t i40e_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
230 uint16_t i40e_recv_scattered_pkts_vec(void *rx_queue,
231 struct rte_mbuf **rx_pkts,
233 int i40e_rx_vec_dev_conf_condition_check(struct rte_eth_dev *dev);
234 int i40e_rxq_vec_setup(struct i40e_rx_queue *rxq);
235 int i40e_txq_vec_setup(struct i40e_tx_queue *txq);
236 void i40e_rx_queue_release_mbufs_vec(struct i40e_rx_queue *rxq);
237 uint16_t i40e_xmit_fixed_burst_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
239 void i40e_set_rx_function(struct rte_eth_dev *dev);
240 void i40e_set_tx_function_flag(struct rte_eth_dev *dev,
241 struct i40e_tx_queue *txq);
242 void i40e_set_tx_function(struct rte_eth_dev *dev);
243 void i40e_set_default_ptype_table(struct rte_eth_dev *dev);
244 void i40e_set_default_pctype_table(struct rte_eth_dev *dev);
245 uint16_t i40e_recv_pkts_vec_avx2(void *rx_queue, struct rte_mbuf **rx_pkts,
247 uint16_t i40e_recv_scattered_pkts_vec_avx2(void *rx_queue,
248 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
249 uint16_t i40e_xmit_pkts_vec_avx2(void *tx_queue, struct rte_mbuf **tx_pkts,
251 int i40e_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc);
252 uint16_t i40e_recv_pkts_vec_avx512(void *rx_queue,
253 struct rte_mbuf **rx_pkts,
255 uint16_t i40e_recv_scattered_pkts_vec_avx512(void *rx_queue,
256 struct rte_mbuf **rx_pkts,
258 uint16_t i40e_xmit_pkts_vec_avx512(void *tx_queue,
259 struct rte_mbuf **tx_pkts,
262 /* For each value it means, datasheet of hardware can tell more details
264 * @note: fix i40e_dev_supported_ptypes_get() if any change here.
266 static inline uint32_t
267 i40e_get_default_pkt_type(uint8_t ptype)
269 static const uint32_t type_table[UINT8_MAX + 1] __rte_cache_aligned = {
272 [1] = RTE_PTYPE_L2_ETHER,
273 [2] = RTE_PTYPE_L2_ETHER_TIMESYNC,
274 /* [3] - [5] reserved */
275 [6] = RTE_PTYPE_L2_ETHER_LLDP,
276 /* [7] - [10] reserved */
277 [11] = RTE_PTYPE_L2_ETHER_ARP,
278 /* [12] - [21] reserved */
280 /* Non tunneled IPv4 */
281 [22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
283 [23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
284 RTE_PTYPE_L4_NONFRAG,
285 [24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
288 [26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
290 [27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
292 [28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
296 [29] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
297 RTE_PTYPE_TUNNEL_IP |
298 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
299 RTE_PTYPE_INNER_L4_FRAG,
300 [30] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
301 RTE_PTYPE_TUNNEL_IP |
302 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
303 RTE_PTYPE_INNER_L4_NONFRAG,
304 [31] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
305 RTE_PTYPE_TUNNEL_IP |
306 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
307 RTE_PTYPE_INNER_L4_UDP,
309 [33] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
310 RTE_PTYPE_TUNNEL_IP |
311 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
312 RTE_PTYPE_INNER_L4_TCP,
313 [34] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
314 RTE_PTYPE_TUNNEL_IP |
315 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
316 RTE_PTYPE_INNER_L4_SCTP,
317 [35] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
318 RTE_PTYPE_TUNNEL_IP |
319 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
320 RTE_PTYPE_INNER_L4_ICMP,
323 [36] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
324 RTE_PTYPE_TUNNEL_IP |
325 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
326 RTE_PTYPE_INNER_L4_FRAG,
327 [37] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
328 RTE_PTYPE_TUNNEL_IP |
329 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
330 RTE_PTYPE_INNER_L4_NONFRAG,
331 [38] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
332 RTE_PTYPE_TUNNEL_IP |
333 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
334 RTE_PTYPE_INNER_L4_UDP,
336 [40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
337 RTE_PTYPE_TUNNEL_IP |
338 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
339 RTE_PTYPE_INNER_L4_TCP,
340 [41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
341 RTE_PTYPE_TUNNEL_IP |
342 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
343 RTE_PTYPE_INNER_L4_SCTP,
344 [42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
345 RTE_PTYPE_TUNNEL_IP |
346 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
347 RTE_PTYPE_INNER_L4_ICMP,
349 /* IPv4 --> GRE/Teredo/VXLAN */
350 [43] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
351 RTE_PTYPE_TUNNEL_GRENAT,
353 /* IPv4 --> GRE/Teredo/VXLAN --> IPv4 */
354 [44] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
355 RTE_PTYPE_TUNNEL_GRENAT |
356 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
357 RTE_PTYPE_INNER_L4_FRAG,
358 [45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
359 RTE_PTYPE_TUNNEL_GRENAT |
360 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
361 RTE_PTYPE_INNER_L4_NONFRAG,
362 [46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
363 RTE_PTYPE_TUNNEL_GRENAT |
364 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
365 RTE_PTYPE_INNER_L4_UDP,
367 [48] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
368 RTE_PTYPE_TUNNEL_GRENAT |
369 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
370 RTE_PTYPE_INNER_L4_TCP,
371 [49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
372 RTE_PTYPE_TUNNEL_GRENAT |
373 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
374 RTE_PTYPE_INNER_L4_SCTP,
375 [50] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
376 RTE_PTYPE_TUNNEL_GRENAT |
377 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
378 RTE_PTYPE_INNER_L4_ICMP,
380 /* IPv4 --> GRE/Teredo/VXLAN --> IPv6 */
381 [51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
382 RTE_PTYPE_TUNNEL_GRENAT |
383 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
384 RTE_PTYPE_INNER_L4_FRAG,
385 [52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
386 RTE_PTYPE_TUNNEL_GRENAT |
387 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
388 RTE_PTYPE_INNER_L4_NONFRAG,
389 [53] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
390 RTE_PTYPE_TUNNEL_GRENAT |
391 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
392 RTE_PTYPE_INNER_L4_UDP,
394 [55] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
395 RTE_PTYPE_TUNNEL_GRENAT |
396 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
397 RTE_PTYPE_INNER_L4_TCP,
398 [56] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
399 RTE_PTYPE_TUNNEL_GRENAT |
400 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
401 RTE_PTYPE_INNER_L4_SCTP,
402 [57] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
403 RTE_PTYPE_TUNNEL_GRENAT |
404 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
405 RTE_PTYPE_INNER_L4_ICMP,
407 /* IPv4 --> GRE/Teredo/VXLAN --> MAC */
408 [58] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
409 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
411 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
412 [59] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
413 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
414 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
415 RTE_PTYPE_INNER_L4_FRAG,
416 [60] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
417 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
418 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
419 RTE_PTYPE_INNER_L4_NONFRAG,
420 [61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
421 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
422 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
423 RTE_PTYPE_INNER_L4_UDP,
425 [63] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
426 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
427 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
428 RTE_PTYPE_INNER_L4_TCP,
429 [64] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
430 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
431 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
432 RTE_PTYPE_INNER_L4_SCTP,
433 [65] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
434 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
435 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
436 RTE_PTYPE_INNER_L4_ICMP,
438 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
439 [66] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
440 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
441 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
442 RTE_PTYPE_INNER_L4_FRAG,
443 [67] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
444 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
445 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
446 RTE_PTYPE_INNER_L4_NONFRAG,
447 [68] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
448 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
449 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
450 RTE_PTYPE_INNER_L4_UDP,
452 [70] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
453 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
454 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
455 RTE_PTYPE_INNER_L4_TCP,
456 [71] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
457 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
458 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
459 RTE_PTYPE_INNER_L4_SCTP,
460 [72] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
461 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
462 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
463 RTE_PTYPE_INNER_L4_ICMP,
465 /* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN */
466 [73] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
467 RTE_PTYPE_TUNNEL_GRENAT |
468 RTE_PTYPE_INNER_L2_ETHER_VLAN,
470 /* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv4 */
471 [74] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
472 RTE_PTYPE_TUNNEL_GRENAT |
473 RTE_PTYPE_INNER_L2_ETHER_VLAN |
474 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
475 RTE_PTYPE_INNER_L4_FRAG,
476 [75] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
477 RTE_PTYPE_TUNNEL_GRENAT |
478 RTE_PTYPE_INNER_L2_ETHER_VLAN |
479 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
480 RTE_PTYPE_INNER_L4_NONFRAG,
481 [76] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
482 RTE_PTYPE_TUNNEL_GRENAT |
483 RTE_PTYPE_INNER_L2_ETHER_VLAN |
484 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
485 RTE_PTYPE_INNER_L4_UDP,
487 [78] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
488 RTE_PTYPE_TUNNEL_GRENAT |
489 RTE_PTYPE_INNER_L2_ETHER_VLAN |
490 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
491 RTE_PTYPE_INNER_L4_TCP,
492 [79] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
493 RTE_PTYPE_TUNNEL_GRENAT |
494 RTE_PTYPE_INNER_L2_ETHER_VLAN |
495 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
496 RTE_PTYPE_INNER_L4_SCTP,
497 [80] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
498 RTE_PTYPE_TUNNEL_GRENAT |
499 RTE_PTYPE_INNER_L2_ETHER_VLAN |
500 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
501 RTE_PTYPE_INNER_L4_ICMP,
503 /* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv6 */
504 [81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
505 RTE_PTYPE_TUNNEL_GRENAT |
506 RTE_PTYPE_INNER_L2_ETHER_VLAN |
507 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
508 RTE_PTYPE_INNER_L4_FRAG,
509 [82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
510 RTE_PTYPE_TUNNEL_GRENAT |
511 RTE_PTYPE_INNER_L2_ETHER_VLAN |
512 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
513 RTE_PTYPE_INNER_L4_NONFRAG,
514 [83] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
515 RTE_PTYPE_TUNNEL_GRENAT |
516 RTE_PTYPE_INNER_L2_ETHER_VLAN |
517 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
518 RTE_PTYPE_INNER_L4_UDP,
520 [85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
521 RTE_PTYPE_TUNNEL_GRENAT |
522 RTE_PTYPE_INNER_L2_ETHER_VLAN |
523 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
524 RTE_PTYPE_INNER_L4_TCP,
525 [86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
526 RTE_PTYPE_TUNNEL_GRENAT |
527 RTE_PTYPE_INNER_L2_ETHER_VLAN |
528 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
529 RTE_PTYPE_INNER_L4_SCTP,
530 [87] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
531 RTE_PTYPE_TUNNEL_GRENAT |
532 RTE_PTYPE_INNER_L2_ETHER_VLAN |
533 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
534 RTE_PTYPE_INNER_L4_ICMP,
536 /* Non tunneled IPv6 */
537 [88] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
539 [89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
540 RTE_PTYPE_L4_NONFRAG,
541 [90] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
544 [92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
546 [93] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
548 [94] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
552 [95] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
553 RTE_PTYPE_TUNNEL_IP |
554 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
555 RTE_PTYPE_INNER_L4_FRAG,
556 [96] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
557 RTE_PTYPE_TUNNEL_IP |
558 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
559 RTE_PTYPE_INNER_L4_NONFRAG,
560 [97] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
561 RTE_PTYPE_TUNNEL_IP |
562 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
563 RTE_PTYPE_INNER_L4_UDP,
565 [99] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
566 RTE_PTYPE_TUNNEL_IP |
567 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
568 RTE_PTYPE_INNER_L4_TCP,
569 [100] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
570 RTE_PTYPE_TUNNEL_IP |
571 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
572 RTE_PTYPE_INNER_L4_SCTP,
573 [101] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
574 RTE_PTYPE_TUNNEL_IP |
575 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
576 RTE_PTYPE_INNER_L4_ICMP,
579 [102] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
580 RTE_PTYPE_TUNNEL_IP |
581 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
582 RTE_PTYPE_INNER_L4_FRAG,
583 [103] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
584 RTE_PTYPE_TUNNEL_IP |
585 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
586 RTE_PTYPE_INNER_L4_NONFRAG,
587 [104] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
588 RTE_PTYPE_TUNNEL_IP |
589 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
590 RTE_PTYPE_INNER_L4_UDP,
592 [106] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
593 RTE_PTYPE_TUNNEL_IP |
594 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
595 RTE_PTYPE_INNER_L4_TCP,
596 [107] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
597 RTE_PTYPE_TUNNEL_IP |
598 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
599 RTE_PTYPE_INNER_L4_SCTP,
600 [108] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
601 RTE_PTYPE_TUNNEL_IP |
602 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
603 RTE_PTYPE_INNER_L4_ICMP,
605 /* IPv6 --> GRE/Teredo/VXLAN */
606 [109] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
607 RTE_PTYPE_TUNNEL_GRENAT,
609 /* IPv6 --> GRE/Teredo/VXLAN --> IPv4 */
610 [110] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
611 RTE_PTYPE_TUNNEL_GRENAT |
612 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
613 RTE_PTYPE_INNER_L4_FRAG,
614 [111] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
615 RTE_PTYPE_TUNNEL_GRENAT |
616 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
617 RTE_PTYPE_INNER_L4_NONFRAG,
618 [112] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
619 RTE_PTYPE_TUNNEL_GRENAT |
620 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
621 RTE_PTYPE_INNER_L4_UDP,
623 [114] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
624 RTE_PTYPE_TUNNEL_GRENAT |
625 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
626 RTE_PTYPE_INNER_L4_TCP,
627 [115] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
628 RTE_PTYPE_TUNNEL_GRENAT |
629 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
630 RTE_PTYPE_INNER_L4_SCTP,
631 [116] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
632 RTE_PTYPE_TUNNEL_GRENAT |
633 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
634 RTE_PTYPE_INNER_L4_ICMP,
636 /* IPv6 --> GRE/Teredo/VXLAN --> IPv6 */
637 [117] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
638 RTE_PTYPE_TUNNEL_GRENAT |
639 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
640 RTE_PTYPE_INNER_L4_FRAG,
641 [118] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
642 RTE_PTYPE_TUNNEL_GRENAT |
643 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
644 RTE_PTYPE_INNER_L4_NONFRAG,
645 [119] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
646 RTE_PTYPE_TUNNEL_GRENAT |
647 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
648 RTE_PTYPE_INNER_L4_UDP,
650 [121] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
651 RTE_PTYPE_TUNNEL_GRENAT |
652 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
653 RTE_PTYPE_INNER_L4_TCP,
654 [122] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
655 RTE_PTYPE_TUNNEL_GRENAT |
656 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
657 RTE_PTYPE_INNER_L4_SCTP,
658 [123] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
659 RTE_PTYPE_TUNNEL_GRENAT |
660 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
661 RTE_PTYPE_INNER_L4_ICMP,
663 /* IPv6 --> GRE/Teredo/VXLAN --> MAC */
664 [124] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
665 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
667 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
668 [125] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
669 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
670 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
671 RTE_PTYPE_INNER_L4_FRAG,
672 [126] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
673 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
674 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
675 RTE_PTYPE_INNER_L4_NONFRAG,
676 [127] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
677 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
678 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
679 RTE_PTYPE_INNER_L4_UDP,
681 [129] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
682 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
683 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
684 RTE_PTYPE_INNER_L4_TCP,
685 [130] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
686 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
687 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
688 RTE_PTYPE_INNER_L4_SCTP,
689 [131] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
690 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
691 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
692 RTE_PTYPE_INNER_L4_ICMP,
694 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
695 [132] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
696 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
697 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
698 RTE_PTYPE_INNER_L4_FRAG,
699 [133] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
700 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
701 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
702 RTE_PTYPE_INNER_L4_NONFRAG,
703 [134] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
704 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
705 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
706 RTE_PTYPE_INNER_L4_UDP,
708 [136] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
709 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
710 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
711 RTE_PTYPE_INNER_L4_TCP,
712 [137] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
713 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
714 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
715 RTE_PTYPE_INNER_L4_SCTP,
716 [138] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
717 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
718 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
719 RTE_PTYPE_INNER_L4_ICMP,
721 /* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN */
722 [139] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
723 RTE_PTYPE_TUNNEL_GRENAT |
724 RTE_PTYPE_INNER_L2_ETHER_VLAN,
726 /* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv4 */
727 [140] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
728 RTE_PTYPE_TUNNEL_GRENAT |
729 RTE_PTYPE_INNER_L2_ETHER_VLAN |
730 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
731 RTE_PTYPE_INNER_L4_FRAG,
732 [141] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
733 RTE_PTYPE_TUNNEL_GRENAT |
734 RTE_PTYPE_INNER_L2_ETHER_VLAN |
735 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
736 RTE_PTYPE_INNER_L4_NONFRAG,
737 [142] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
738 RTE_PTYPE_TUNNEL_GRENAT |
739 RTE_PTYPE_INNER_L2_ETHER_VLAN |
740 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
741 RTE_PTYPE_INNER_L4_UDP,
743 [144] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
744 RTE_PTYPE_TUNNEL_GRENAT |
745 RTE_PTYPE_INNER_L2_ETHER_VLAN |
746 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
747 RTE_PTYPE_INNER_L4_TCP,
748 [145] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
749 RTE_PTYPE_TUNNEL_GRENAT |
750 RTE_PTYPE_INNER_L2_ETHER_VLAN |
751 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
752 RTE_PTYPE_INNER_L4_SCTP,
753 [146] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
754 RTE_PTYPE_TUNNEL_GRENAT |
755 RTE_PTYPE_INNER_L2_ETHER_VLAN |
756 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
757 RTE_PTYPE_INNER_L4_ICMP,
759 /* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv6 */
760 [147] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
761 RTE_PTYPE_TUNNEL_GRENAT |
762 RTE_PTYPE_INNER_L2_ETHER_VLAN |
763 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
764 RTE_PTYPE_INNER_L4_FRAG,
765 [148] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
766 RTE_PTYPE_TUNNEL_GRENAT |
767 RTE_PTYPE_INNER_L2_ETHER_VLAN |
768 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
769 RTE_PTYPE_INNER_L4_NONFRAG,
770 [149] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
771 RTE_PTYPE_TUNNEL_GRENAT |
772 RTE_PTYPE_INNER_L2_ETHER_VLAN |
773 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
774 RTE_PTYPE_INNER_L4_UDP,
776 [151] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
777 RTE_PTYPE_TUNNEL_GRENAT |
778 RTE_PTYPE_INNER_L2_ETHER_VLAN |
779 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
780 RTE_PTYPE_INNER_L4_TCP,
781 [152] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
782 RTE_PTYPE_TUNNEL_GRENAT |
783 RTE_PTYPE_INNER_L2_ETHER_VLAN |
784 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
785 RTE_PTYPE_INNER_L4_SCTP,
786 [153] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
787 RTE_PTYPE_TUNNEL_GRENAT |
788 RTE_PTYPE_INNER_L2_ETHER_VLAN |
789 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
790 RTE_PTYPE_INNER_L4_ICMP,
792 /* L2 NSH packet type */
793 [154] = RTE_PTYPE_L2_ETHER_NSH,
794 [155] = RTE_PTYPE_L2_ETHER_NSH | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
796 [156] = RTE_PTYPE_L2_ETHER_NSH | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
797 RTE_PTYPE_L4_NONFRAG,
798 [157] = RTE_PTYPE_L2_ETHER_NSH | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
800 [158] = RTE_PTYPE_L2_ETHER_NSH | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
802 [159] = RTE_PTYPE_L2_ETHER_NSH | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
804 [160] = RTE_PTYPE_L2_ETHER_NSH | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
806 [161] = RTE_PTYPE_L2_ETHER_NSH | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
808 [162] = RTE_PTYPE_L2_ETHER_NSH | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
809 RTE_PTYPE_L4_NONFRAG,
810 [163] = RTE_PTYPE_L2_ETHER_NSH | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
812 [164] = RTE_PTYPE_L2_ETHER_NSH | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
814 [165] = RTE_PTYPE_L2_ETHER_NSH | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
816 [166] = RTE_PTYPE_L2_ETHER_NSH | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
819 /* All others reserved */
822 return type_table[ptype];
825 #endif /* _I40E_RXTX_H_ */