drivers/net/i40e/i40e_rxtx_vec.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdint.h>
  35 #include <rte_ethdev.h>
  36 #include <rte_malloc.h>
  37
  38 #include "base/i40e_prototype.h"
  39 #include "base/i40e_type.h"
  40 #include "i40e_ethdev.h"
  41 #include "i40e_rxtx.h"
  42
  43 #include <tmmintrin.h>
  44
  45 #ifndef __INTEL_COMPILER
  46 #pragma GCC diagnostic ignored "-Wcast-qual"
  47 #endif
  48
  49 static inline void
  50 i40e_rxq_rearm(struct i40e_rx_queue *rxq)
  51 {
  52         int i;
  53         uint16_t rx_id;
  54         volatile union i40e_rx_desc *rxdp;
  55         struct i40e_rx_entry *rxep = &rxq->sw_ring[rxq->rxrearm_start];
  56         struct rte_mbuf *mb0, *mb1;
  57         __m128i hdr_room = _mm_set_epi64x(RTE_PKTMBUF_HEADROOM,
  58                         RTE_PKTMBUF_HEADROOM);
  59         __m128i dma_addr0, dma_addr1;
  60
  61         rxdp = rxq->rx_ring + rxq->rxrearm_start;
  62
  63         /* Pull 'n' more MBUFs into the software ring */
  64         if (rte_mempool_get_bulk(rxq->mp,
  65                                  (void *)rxep,
  66                                  RTE_I40E_RXQ_REARM_THRESH) < 0) {
  67                 if (rxq->rxrearm_nb + RTE_I40E_RXQ_REARM_THRESH >=
  68                     rxq->nb_rx_desc) {
  69                         dma_addr0 = _mm_setzero_si128();
  70                         for (i = 0; i < RTE_I40E_DESCS_PER_LOOP; i++) {
  71                                 rxep[i].mbuf = &rxq->fake_mbuf;
  72                                 _mm_store_si128((__m128i *)&rxdp[i].read,
  73                                                 dma_addr0);
  74                         }
  75                 }
  76                 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
  77                         RTE_I40E_RXQ_REARM_THRESH;
  78                 return;
  79         }
  80
  81         /* Initialize the mbufs in vector, process 2 mbufs in one loop */
  82         for (i = 0; i < RTE_I40E_RXQ_REARM_THRESH; i += 2, rxep += 2) {
  83                 __m128i vaddr0, vaddr1;
  84                 uintptr_t p0, p1;
  85
  86                 mb0 = rxep[0].mbuf;
  87                 mb1 = rxep[1].mbuf;
  88
  89                  /* Flush mbuf with pkt template.
  90                  * Data to be rearmed is 6 bytes long.
  91                  * Though, RX will overwrite ol_flags that are coming next
  92                  * anyway. So overwrite whole 8 bytes with one load:
  93                  * 6 bytes of rearm_data plus first 2 bytes of ol_flags.
  94                  */
  95                 p0 = (uintptr_t)&mb0->rearm_data;
  96                 *(uint64_t *)p0 = rxq->mbuf_initializer;
  97                 p1 = (uintptr_t)&mb1->rearm_data;
  98                 *(uint64_t *)p1 = rxq->mbuf_initializer;
  99
 100                 /* load buf_addr(lo 64bit) and buf_physaddr(hi 64bit) */
 101                 vaddr0 = _mm_loadu_si128((__m128i *)&mb0->buf_addr);
 102                 vaddr1 = _mm_loadu_si128((__m128i *)&mb1->buf_addr);
 103
 104                 /* convert pa to dma_addr hdr/data */
 105                 dma_addr0 = _mm_unpackhi_epi64(vaddr0, vaddr0);
 106                 dma_addr1 = _mm_unpackhi_epi64(vaddr1, vaddr1);
 107
 108                 /* add headroom to pa values */
 109                 dma_addr0 = _mm_add_epi64(dma_addr0, hdr_room);
 110                 dma_addr1 = _mm_add_epi64(dma_addr1, hdr_room);
 111
 112                 /* flush desc with pa dma_addr */
 113                 _mm_store_si128((__m128i *)&rxdp++->read, dma_addr0);
 114                 _mm_store_si128((__m128i *)&rxdp++->read, dma_addr1);
 115         }
 116
 117         rxq->rxrearm_start += RTE_I40E_RXQ_REARM_THRESH;
 118         if (rxq->rxrearm_start >= rxq->nb_rx_desc)
 119                 rxq->rxrearm_start = 0;
 120
 121         rxq->rxrearm_nb -= RTE_I40E_RXQ_REARM_THRESH;
 122
 123         rx_id = (uint16_t)((rxq->rxrearm_start == 0) ?
 124                              (rxq->nb_rx_desc - 1) : (rxq->rxrearm_start - 1));
 125
 126         /* Update the tail pointer on the NIC */
 127         I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
 128 }
 129
 130 /* Handling the offload flags (olflags) field takes computation
 131  * time when receiving packets. Therefore we provide a flag to disable
 132  * the processing of the olflags field when they are not needed. This
 133  * gives improved performance, at the cost of losing the offload info
 134  * in the received packet
 135  */
 136 #ifdef RTE_LIBRTE_I40E_RX_OLFLAGS_ENABLE
 137
 138 static inline void
 139 desc_to_olflags_v(__m128i descs[4], struct rte_mbuf **rx_pkts)
 140 {
 141         __m128i vlan0, vlan1, rss;
 142         union {
 143                 uint16_t e[4];
 144                 uint64_t dword;
 145         } vol;
 146
 147         /* mask everything except RSS, flow director and VLAN flags
 148          * bit2 is for VLAN tag, bit11 for flow director indication
 149          * bit13:12 for RSS indication.
 150          */
 151         const __m128i rss_vlan_msk = _mm_set_epi16(
 152                         0x0000, 0x0000, 0x0000, 0x0000,
 153                         0x3804, 0x3804, 0x3804, 0x3804);
 154
 155         /* map rss and vlan type to rss hash and vlan flag */
 156         const __m128i vlan_flags = _mm_set_epi8(0, 0, 0, 0,
 157                         0, 0, 0, 0,
 158                         0, 0, 0, PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED,
 159                         0, 0, 0, 0);
 160
 161         const __m128i rss_flags = _mm_set_epi8(0, 0, 0, 0,
 162                         0, 0, 0, 0,
 163                         PKT_RX_RSS_HASH | PKT_RX_FDIR, PKT_RX_RSS_HASH, 0, 0,
 164                         0, 0, PKT_RX_FDIR, 0);
 165
 166         vlan0 = _mm_unpackhi_epi16(descs[0], descs[1]);
 167         vlan1 = _mm_unpackhi_epi16(descs[2], descs[3]);
 168         vlan0 = _mm_unpacklo_epi32(vlan0, vlan1);
 169
 170         vlan1 = _mm_and_si128(vlan0, rss_vlan_msk);
 171         vlan0 = _mm_shuffle_epi8(vlan_flags, vlan1);
 172
 173         rss = _mm_srli_epi16(vlan1, 11);
 174         rss = _mm_shuffle_epi8(rss_flags, rss);
 175
 176         vlan0 = _mm_or_si128(vlan0, rss);
 177         vol.dword = _mm_cvtsi128_si64(vlan0);
 178
 179         rx_pkts[0]->ol_flags = vol.e[0];
 180         rx_pkts[1]->ol_flags = vol.e[1];
 181         rx_pkts[2]->ol_flags = vol.e[2];
 182         rx_pkts[3]->ol_flags = vol.e[3];
 183 }
 184 #else
 185 #define desc_to_olflags_v(desc, rx_pkts) do {} while (0)
 186 #endif
 187
 188 #define PKTLEN_SHIFT     10
 189
 190 static inline void
 191 desc_to_ptype_v(__m128i descs[4], struct rte_mbuf **rx_pkts)
 192 {
 193         __m128i ptype0 = _mm_unpackhi_epi64(descs[0], descs[1]);
 194         __m128i ptype1 = _mm_unpackhi_epi64(descs[2], descs[3]);
 195
 196         ptype0 = _mm_srli_epi64(ptype0, 30);
 197         ptype1 = _mm_srli_epi64(ptype1, 30);
 198
 199         rx_pkts[0]->packet_type = i40e_rxd_pkt_type_mapping(_mm_extract_epi8(ptype0, 0));
 200         rx_pkts[1]->packet_type = i40e_rxd_pkt_type_mapping(_mm_extract_epi8(ptype0, 8));
 201         rx_pkts[2]->packet_type = i40e_rxd_pkt_type_mapping(_mm_extract_epi8(ptype1, 0));
 202         rx_pkts[3]->packet_type = i40e_rxd_pkt_type_mapping(_mm_extract_epi8(ptype1, 8));
 203 }
 204
 205  /*
 206  * Notice:
 207  * - nb_pkts < RTE_I40E_DESCS_PER_LOOP, just return no packet
 208  * - nb_pkts > RTE_I40E_VPMD_RX_BURST, only scan RTE_I40E_VPMD_RX_BURST
 209  *   numbers of DD bits
 210  */
 211 static inline uint16_t
 212 _recv_raw_pkts_vec(struct i40e_rx_queue *rxq, struct rte_mbuf **rx_pkts,
 213                    uint16_t nb_pkts, uint8_t *split_packet)
 214 {
 215         volatile union i40e_rx_desc *rxdp;
 216         struct i40e_rx_entry *sw_ring;
 217         uint16_t nb_pkts_recd;
 218         int pos;
 219         uint64_t var;
 220         __m128i shuf_msk;
 221
 222         __m128i crc_adjust = _mm_set_epi16(
 223                                 0, 0, 0,    /* ignore non-length fields */
 224                                 -rxq->crc_len, /* sub crc on data_len */
 225                                 0,          /* ignore high-16bits of pkt_len */
 226                                 -rxq->crc_len, /* sub crc on pkt_len */
 227                                 0, 0            /* ignore pkt_type field */
 228                         );
 229         __m128i dd_check, eop_check;
 230
 231         /* nb_pkts shall be less equal than RTE_I40E_MAX_RX_BURST */
 232         nb_pkts = RTE_MIN(nb_pkts, RTE_I40E_MAX_RX_BURST);
 233
 234         /* nb_pkts has to be floor-aligned to RTE_I40E_DESCS_PER_LOOP */
 235         nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, RTE_I40E_DESCS_PER_LOOP);
 236
 237         /* Just the act of getting into the function from the application is
 238          * going to cost about 7 cycles
 239          */
 240         rxdp = rxq->rx_ring + rxq->rx_tail;
 241
 242         rte_prefetch0(rxdp);
 243
 244         /* See if we need to rearm the RX queue - gives the prefetch a bit
 245          * of time to act
 246          */
 247         if (rxq->rxrearm_nb > RTE_I40E_RXQ_REARM_THRESH)
 248                 i40e_rxq_rearm(rxq);
 249
 250         /* Before we start moving massive data around, check to see if
 251          * there is actually a packet available
 252          */
 253         if (!(rxdp->wb.qword1.status_error_len &
 254                         rte_cpu_to_le_32(1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 255                 return 0;
 256
 257         /* 4 packets DD mask */
 258         dd_check = _mm_set_epi64x(0x0000000100000001LL, 0x0000000100000001LL);
 259
 260         /* 4 packets EOP mask */
 261         eop_check = _mm_set_epi64x(0x0000000200000002LL, 0x0000000200000002LL);
 262
 263         /* mask to shuffle from desc. to mbuf */
 264         shuf_msk = _mm_set_epi8(
 265                 7, 6, 5, 4,  /* octet 4~7, 32bits rss */
 266                 3, 2,        /* octet 2~3, low 16 bits vlan_macip */
 267                 15, 14,      /* octet 15~14, 16 bits data_len */
 268                 0xFF, 0xFF,  /* skip high 16 bits pkt_len, zero out */
 269                 15, 14,      /* octet 15~14, low 16 bits pkt_len */
 270                 0xFF, 0xFF,  /* pkt_type set as unknown */
 271                 0xFF, 0xFF  /*pkt_type set as unknown */
 272                 );
 273
 274         /* Cache is empty -> need to scan the buffer rings, but first move
 275          * the next 'n' mbufs into the cache
 276          */
 277         sw_ring = &rxq->sw_ring[rxq->rx_tail];
 278
 279         /* A. load 4 packet in one loop
 280          * [A*. mask out 4 unused dirty field in desc]
 281          * B. copy 4 mbuf point from swring to rx_pkts
 282          * C. calc the number of DD bits among the 4 packets
 283          * [C*. extract the end-of-packet bit, if requested]
 284          * D. fill info. from desc to mbuf
 285          */
 286
 287         for (pos = 0, nb_pkts_recd = 0; pos < nb_pkts;
 288                         pos += RTE_I40E_DESCS_PER_LOOP,
 289                         rxdp += RTE_I40E_DESCS_PER_LOOP) {
 290                 __m128i descs[RTE_I40E_DESCS_PER_LOOP];
 291                 __m128i pkt_mb1, pkt_mb2, pkt_mb3, pkt_mb4;
 292                 __m128i zero, staterr, sterr_tmp1, sterr_tmp2;
 293                 __m128i mbp1, mbp2; /* two mbuf pointer in one XMM reg. */
 294
 295                 /* B.1 load 1 mbuf point */
 296                 mbp1 = _mm_loadu_si128((__m128i *)&sw_ring[pos]);
 297                 /* Read desc statuses backwards to avoid race condition */
 298                 /* A.1 load 4 pkts desc */
 299                 descs[3] = _mm_loadu_si128((__m128i *)(rxdp + 3));
 300
 301                 /* B.2 copy 2 mbuf point into rx_pkts  */
 302                 _mm_storeu_si128((__m128i *)&rx_pkts[pos], mbp1);
 303
 304                 /* B.1 load 1 mbuf point */
 305                 mbp2 = _mm_loadu_si128((__m128i *)&sw_ring[pos+2]);
 306
 307                 descs[2] = _mm_loadu_si128((__m128i *)(rxdp + 2));
 308                 /* B.1 load 2 mbuf point */
 309                 descs[1] = _mm_loadu_si128((__m128i *)(rxdp + 1));
 310                 descs[0] = _mm_loadu_si128((__m128i *)(rxdp));
 311
 312                 /* B.2 copy 2 mbuf point into rx_pkts  */
 313                 _mm_storeu_si128((__m128i *)&rx_pkts[pos+2], mbp2);
 314
 315                 if (split_packet) {
 316                         rte_mbuf_prefetch_part2(rx_pkts[pos]);
 317                         rte_mbuf_prefetch_part2(rx_pkts[pos + 1]);
 318                         rte_mbuf_prefetch_part2(rx_pkts[pos + 2]);
 319                         rte_mbuf_prefetch_part2(rx_pkts[pos + 3]);
 320                 }
 321
 322                 /* avoid compiler reorder optimization */
 323                 rte_compiler_barrier();
 324
 325                 /* pkt 3,4 shift the pktlen field to be 16-bit aligned*/
 326                 const __m128i len3 = _mm_slli_epi32(descs[3], PKTLEN_SHIFT);
 327                 const __m128i len2 = _mm_slli_epi32(descs[2], PKTLEN_SHIFT);
 328
 329                 /* merge the now-aligned packet length fields back in */
 330                 descs[3] = _mm_blend_epi16(descs[3], len3, 0x80);
 331                 descs[2] = _mm_blend_epi16(descs[2], len2, 0x80);
 332
 333                 /* D.1 pkt 3,4 convert format from desc to pktmbuf */
 334                 pkt_mb4 = _mm_shuffle_epi8(descs[3], shuf_msk);
 335                 pkt_mb3 = _mm_shuffle_epi8(descs[2], shuf_msk);
 336
 337                 /* C.1 4=>2 filter staterr info only */
 338                 sterr_tmp2 = _mm_unpackhi_epi32(descs[3], descs[2]);
 339                 /* C.1 4=>2 filter staterr info only */
 340                 sterr_tmp1 = _mm_unpackhi_epi32(descs[1], descs[0]);
 341
 342                 desc_to_olflags_v(descs, &rx_pkts[pos]);
 343
 344                 /* D.2 pkt 3,4 set in_port/nb_seg and remove crc */
 345                 pkt_mb4 = _mm_add_epi16(pkt_mb4, crc_adjust);
 346                 pkt_mb3 = _mm_add_epi16(pkt_mb3, crc_adjust);
 347
 348                 /* pkt 1,2 shift the pktlen field to be 16-bit aligned*/
 349                 const __m128i len1 = _mm_slli_epi32(descs[1], PKTLEN_SHIFT);
 350                 const __m128i len0 = _mm_slli_epi32(descs[0], PKTLEN_SHIFT);
 351
 352                 /* merge the now-aligned packet length fields back in */
 353                 descs[1] = _mm_blend_epi16(descs[1], len1, 0x80);
 354                 descs[0] = _mm_blend_epi16(descs[0], len0, 0x80);
 355
 356                 /* D.1 pkt 1,2 convert format from desc to pktmbuf */
 357                 pkt_mb2 = _mm_shuffle_epi8(descs[1], shuf_msk);
 358                 pkt_mb1 = _mm_shuffle_epi8(descs[0], shuf_msk);
 359
 360                 /* C.2 get 4 pkts staterr value  */
 361                 zero = _mm_xor_si128(dd_check, dd_check);
 362                 staterr = _mm_unpacklo_epi32(sterr_tmp1, sterr_tmp2);
 363
 364                 /* D.3 copy final 3,4 data to rx_pkts */
 365                 _mm_storeu_si128((void *)&rx_pkts[pos+3]->rx_descriptor_fields1,
 366                                  pkt_mb4);
 367                 _mm_storeu_si128((void *)&rx_pkts[pos+2]->rx_descriptor_fields1,
 368                                  pkt_mb3);
 369
 370                 /* D.2 pkt 1,2 set in_port/nb_seg and remove crc */
 371                 pkt_mb2 = _mm_add_epi16(pkt_mb2, crc_adjust);
 372                 pkt_mb1 = _mm_add_epi16(pkt_mb1, crc_adjust);
 373
 374                 /* C* extract and record EOP bit */
 375                 if (split_packet) {
 376                         __m128i eop_shuf_mask = _mm_set_epi8(
 377                                         0xFF, 0xFF, 0xFF, 0xFF,
 378                                         0xFF, 0xFF, 0xFF, 0xFF,
 379                                         0xFF, 0xFF, 0xFF, 0xFF,
 380                                         0x04, 0x0C, 0x00, 0x08
 381                                         );
 382
 383                         /* and with mask to extract bits, flipping 1-0 */
 384                         __m128i eop_bits = _mm_andnot_si128(staterr, eop_check);
 385                         /* the staterr values are not in order, as the count
 386                          * count of dd bits doesn't care. However, for end of
 387                          * packet tracking, we do care, so shuffle. This also
 388                          * compresses the 32-bit values to 8-bit
 389                          */
 390                         eop_bits = _mm_shuffle_epi8(eop_bits, eop_shuf_mask);
 391                         /* store the resulting 32-bit value */
 392                         *(int *)split_packet = _mm_cvtsi128_si32(eop_bits);
 393                         split_packet += RTE_I40E_DESCS_PER_LOOP;
 394
 395                         /* zero-out next pointers */
 396                         rx_pkts[pos]->next = NULL;
 397                         rx_pkts[pos + 1]->next = NULL;
 398                         rx_pkts[pos + 2]->next = NULL;
 399                         rx_pkts[pos + 3]->next = NULL;
 400                 }
 401
 402                 /* C.3 calc available number of desc */
 403                 staterr = _mm_and_si128(staterr, dd_check);
 404                 staterr = _mm_packs_epi32(staterr, zero);
 405
 406                 /* D.3 copy final 1,2 data to rx_pkts */
 407                 _mm_storeu_si128((void *)&rx_pkts[pos+1]->rx_descriptor_fields1,
 408                                  pkt_mb2);
 409                 _mm_storeu_si128((void *)&rx_pkts[pos]->rx_descriptor_fields1,
 410                                  pkt_mb1);
 411                 desc_to_ptype_v(descs, &rx_pkts[pos]);
 412                 /* C.4 calc avaialbe number of desc */
 413                 var = __builtin_popcountll(_mm_cvtsi128_si64(staterr));
 414                 nb_pkts_recd += var;
 415                 if (likely(var != RTE_I40E_DESCS_PER_LOOP))
 416                         break;
 417         }
 418
 419         /* Update our internal tail pointer */
 420         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_pkts_recd);
 421         rxq->rx_tail = (uint16_t)(rxq->rx_tail & (rxq->nb_rx_desc - 1));
 422         rxq->rxrearm_nb = (uint16_t)(rxq->rxrearm_nb + nb_pkts_recd);
 423
 424         return nb_pkts_recd;
 425 }
 426
 427  /*
 428  * Notice:
 429  * - nb_pkts < RTE_I40E_DESCS_PER_LOOP, just return no packet
 430  * - nb_pkts > RTE_I40E_VPMD_RX_BURST, only scan RTE_I40E_VPMD_RX_BURST
 431  *   numbers of DD bits
 432  */
 433 uint16_t
 434 i40e_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
 435                    uint16_t nb_pkts)
 436 {
 437         return _recv_raw_pkts_vec(rx_queue, rx_pkts, nb_pkts, NULL);
 438 }
 439
 440 static inline uint16_t
 441 reassemble_packets(struct i40e_rx_queue *rxq, struct rte_mbuf **rx_bufs,
 442                    uint16_t nb_bufs, uint8_t *split_flags)
 443 {
 444         struct rte_mbuf *pkts[RTE_I40E_VPMD_RX_BURST]; /*finished pkts*/
 445         struct rte_mbuf *start = rxq->pkt_first_seg;
 446         struct rte_mbuf *end =  rxq->pkt_last_seg;
 447         unsigned pkt_idx, buf_idx;
 448
 449         for (buf_idx = 0, pkt_idx = 0; buf_idx < nb_bufs; buf_idx++) {
 450                 if (end != NULL) {
 451                         /* processing a split packet */
 452                         end->next = rx_bufs[buf_idx];
 453                         rx_bufs[buf_idx]->data_len += rxq->crc_len;
 454
 455                         start->nb_segs++;
 456                         start->pkt_len += rx_bufs[buf_idx]->data_len;
 457                         end = end->next;
 458
 459                         if (!split_flags[buf_idx]) {
 460                                 /* it's the last packet of the set */
 461                                 start->hash = end->hash;
 462                                 start->ol_flags = end->ol_flags;
 463                                 /* we need to strip crc for the whole packet */
 464                                 start->pkt_len -= rxq->crc_len;
 465                                 if (end->data_len > rxq->crc_len) {
 466                                         end->data_len -= rxq->crc_len;
 467                                 } else {
 468                                         /* free up last mbuf */
 469                                         struct rte_mbuf *secondlast = start;
 470
 471                                         while (secondlast->next != end)
 472                                                 secondlast = secondlast->next;
 473                                         secondlast->data_len -= (rxq->crc_len -
 474                                                         end->data_len);
 475                                         secondlast->next = NULL;
 476                                         rte_pktmbuf_free_seg(end);
 477                                         end = secondlast;
 478                                 }
 479                                 pkts[pkt_idx++] = start;
 480                                 start = end = NULL;
 481                         }
 482                 } else {
 483                         /* not processing a split packet */
 484                         if (!split_flags[buf_idx]) {
 485                                 /* not a split packet, save and skip */
 486                                 pkts[pkt_idx++] = rx_bufs[buf_idx];
 487                                 continue;
 488                         }
 489                         end = start = rx_bufs[buf_idx];
 490                         rx_bufs[buf_idx]->data_len += rxq->crc_len;
 491                         rx_bufs[buf_idx]->pkt_len += rxq->crc_len;
 492                 }
 493         }
 494
 495         /* save the partial packet for next time */
 496         rxq->pkt_first_seg = start;
 497         rxq->pkt_last_seg = end;
 498         memcpy(rx_bufs, pkts, pkt_idx * (sizeof(*pkts)));
 499         return pkt_idx;
 500 }
 501
 502  /* vPMD receive routine that reassembles scattered packets
 503  * Notice:
 504  * - nb_pkts < RTE_I40E_DESCS_PER_LOOP, just return no packet
 505  * - nb_pkts > RTE_I40E_VPMD_RX_BURST, only scan RTE_I40E_VPMD_RX_BURST
 506  *   numbers of DD bits
 507  */
 508 uint16_t
 509 i40e_recv_scattered_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
 510                              uint16_t nb_pkts)
 511 {
 512
 513         struct i40e_rx_queue *rxq = rx_queue;
 514         uint8_t split_flags[RTE_I40E_VPMD_RX_BURST] = {0};
 515
 516         /* get some new buffers */
 517         uint16_t nb_bufs = _recv_raw_pkts_vec(rxq, rx_pkts, nb_pkts,
 518                         split_flags);
 519         if (nb_bufs == 0)
 520                 return 0;
 521
 522         /* happy day case, full burst + no packets to be joined */
 523         const uint64_t *split_fl64 = (uint64_t *)split_flags;
 524
 525         if (rxq->pkt_first_seg == NULL &&
 526                         split_fl64[0] == 0 && split_fl64[1] == 0 &&
 527                         split_fl64[2] == 0 && split_fl64[3] == 0)
 528                 return nb_bufs;
 529
 530         /* reassemble any packets that need reassembly*/
 531         unsigned i = 0;
 532
 533         if (rxq->pkt_first_seg == NULL) {
 534                 /* find the first split flag, and only reassemble then*/
 535                 while (i < nb_bufs && !split_flags[i])
 536                         i++;
 537                 if (i == nb_bufs)
 538                         return nb_bufs;
 539         }
 540         return i + reassemble_packets(rxq, &rx_pkts[i], nb_bufs - i,
 541                 &split_flags[i]);
 542 }
 543
 544 static inline void
 545 vtx1(volatile struct i40e_tx_desc *txdp,
 546                 struct rte_mbuf *pkt, uint64_t flags)
 547 {
 548         uint64_t high_qw = (I40E_TX_DESC_DTYPE_DATA |
 549                         ((uint64_t)flags  << I40E_TXD_QW1_CMD_SHIFT) |
 550                         ((uint64_t)pkt->data_len << I40E_TXD_QW1_TX_BUF_SZ_SHIFT));
 551
 552         __m128i descriptor = _mm_set_epi64x(high_qw,
 553                                 pkt->buf_physaddr + pkt->data_off);
 554         _mm_store_si128((__m128i *)txdp, descriptor);
 555 }
 556
 557 static inline void
 558 vtx(volatile struct i40e_tx_desc *txdp,
 559                 struct rte_mbuf **pkt, uint16_t nb_pkts,  uint64_t flags)
 560 {
 561         int i;
 562
 563         for (i = 0; i < nb_pkts; ++i, ++txdp, ++pkt)
 564                 vtx1(txdp, *pkt, flags);
 565 }
 566
 567 static inline int __attribute__((always_inline))
 568 i40e_tx_free_bufs(struct i40e_tx_queue *txq)
 569 {
 570         struct i40e_tx_entry *txep;
 571         uint32_t n;
 572         uint32_t i;
 573         int nb_free = 0;
 574         struct rte_mbuf *m, *free[RTE_I40E_TX_MAX_FREE_BUF_SZ];
 575
 576         /* check DD bits on threshold descriptor */
 577         if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
 578                         rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
 579                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
 580                 return 0;
 581
 582         n = txq->tx_rs_thresh;
 583
 584          /* first buffer to free from S/W ring is at index
 585           * tx_next_dd - (tx_rs_thresh-1)
 586           */
 587         txep = &txq->sw_ring[txq->tx_next_dd - (n - 1)];
 588         m = __rte_pktmbuf_prefree_seg(txep[0].mbuf);
 589         if (likely(m != NULL)) {
 590                 free[0] = m;
 591                 nb_free = 1;
 592                 for (i = 1; i < n; i++) {
 593                         m = __rte_pktmbuf_prefree_seg(txep[i].mbuf);
 594                         if (likely(m != NULL)) {
 595                                 if (likely(m->pool == free[0]->pool)) {
 596                                         free[nb_free++] = m;
 597                                 } else {
 598                                         rte_mempool_put_bulk(free[0]->pool,
 599                                                              (void *)free,
 600                                                              nb_free);
 601                                         free[0] = m;
 602                                         nb_free = 1;
 603                                 }
 604                         }
 605                 }
 606                 rte_mempool_put_bulk(free[0]->pool, (void **)free, nb_free);
 607         } else {
 608                 for (i = 1; i < n; i++) {
 609                         m = __rte_pktmbuf_prefree_seg(txep[i].mbuf);
 610                         if (m != NULL)
 611                                 rte_mempool_put(m->pool, m);
 612                 }
 613         }
 614
 615         /* buffers were freed, update counters */
 616         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
 617         txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
 618         if (txq->tx_next_dd >= txq->nb_tx_desc)
 619                 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
 620
 621         return txq->tx_rs_thresh;
 622 }
 623
 624 static inline void __attribute__((always_inline))
 625 tx_backlog_entry(struct i40e_tx_entry *txep,
 626                  struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
 627 {
 628         int i;
 629
 630         for (i = 0; i < (int)nb_pkts; ++i)
 631                 txep[i].mbuf = tx_pkts[i];
 632 }
 633
 634 uint16_t
 635 i40e_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
 636                    uint16_t nb_pkts)
 637 {
 638         struct i40e_tx_queue *txq = (struct i40e_tx_queue *)tx_queue;
 639         volatile struct i40e_tx_desc *txdp;
 640         struct i40e_tx_entry *txep;
 641         uint16_t n, nb_commit, tx_id;
 642         uint64_t flags = I40E_TD_CMD;
 643         uint64_t rs = I40E_TX_DESC_CMD_RS | I40E_TD_CMD;
 644         int i;
 645
 646         /* cross rx_thresh boundary is not allowed */
 647         nb_pkts = RTE_MIN(nb_pkts, txq->tx_rs_thresh);
 648
 649         if (txq->nb_tx_free < txq->tx_free_thresh)
 650                 i40e_tx_free_bufs(txq);
 651
 652         nb_commit = nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
 653         if (unlikely(nb_pkts == 0))
 654                 return 0;
 655
 656         tx_id = txq->tx_tail;
 657         txdp = &txq->tx_ring[tx_id];
 658         txep = &txq->sw_ring[tx_id];
 659
 660         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
 661
 662         n = (uint16_t)(txq->nb_tx_desc - tx_id);
 663         if (nb_commit >= n) {
 664                 tx_backlog_entry(txep, tx_pkts, n);
 665
 666                 for (i = 0; i < n - 1; ++i, ++tx_pkts, ++txdp)
 667                         vtx1(txdp, *tx_pkts, flags);
 668
 669                 vtx1(txdp, *tx_pkts++, rs);
 670
 671                 nb_commit = (uint16_t)(nb_commit - n);
 672
 673                 tx_id = 0;
 674                 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
 675
 676                 /* avoid reach the end of ring */
 677                 txdp = &txq->tx_ring[tx_id];
 678                 txep = &txq->sw_ring[tx_id];
 679         }
 680
 681         tx_backlog_entry(txep, tx_pkts, nb_commit);
 682
 683         vtx(txdp, tx_pkts, nb_commit, flags);
 684
 685         tx_id = (uint16_t)(tx_id + nb_commit);
 686         if (tx_id > txq->tx_next_rs) {
 687                 txq->tx_ring[txq->tx_next_rs].cmd_type_offset_bsz |=
 688                         rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
 689                                                 I40E_TXD_QW1_CMD_SHIFT);
 690                 txq->tx_next_rs =
 691                         (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
 692         }
 693
 694         txq->tx_tail = tx_id;
 695
 696         I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
 697
 698         return nb_pkts;
 699 }
 700
 701 void __attribute__((cold))
 702 i40e_rx_queue_release_mbufs_vec(struct i40e_rx_queue *rxq)
 703 {
 704         const unsigned mask = rxq->nb_rx_desc - 1;
 705         unsigned i;
 706
 707         if (rxq->sw_ring == NULL || rxq->rxrearm_nb >= rxq->nb_rx_desc)
 708                 return;
 709
 710         /* free all mbufs that are valid in the ring */
 711         if (rxq->rxrearm_nb == 0) {
 712                 for (i = 0; i < rxq->nb_rx_desc; i++) {
 713                         if (rxq->sw_ring[i].mbuf != NULL)
 714                                 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
 715                 }
 716         } else {
 717                 for (i = rxq->rx_tail;
 718                      i != rxq->rxrearm_start;
 719                      i = (i + 1) & mask) {
 720                         if (rxq->sw_ring[i].mbuf != NULL)
 721                                 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
 722                 }
 723         }
 724
 725         rxq->rxrearm_nb = rxq->nb_rx_desc;
 726
 727         /* set all entries to NULL */
 728         memset(rxq->sw_ring, 0, sizeof(rxq->sw_ring[0]) * rxq->nb_rx_desc);
 729 }
 730
 731 int __attribute__((cold))
 732 i40e_rxq_vec_setup(struct i40e_rx_queue *rxq)
 733 {
 734         uintptr_t p;
 735         struct rte_mbuf mb_def = { .buf_addr = 0 }; /* zeroed mbuf */
 736
 737         mb_def.nb_segs = 1;
 738         mb_def.data_off = RTE_PKTMBUF_HEADROOM;
 739         mb_def.port = rxq->port_id;
 740         rte_mbuf_refcnt_set(&mb_def, 1);
 741
 742         /* prevent compiler reordering: rearm_data covers previous fields */
 743         rte_compiler_barrier();
 744         p = (uintptr_t)&mb_def.rearm_data;
 745         rxq->mbuf_initializer = *(uint64_t *)p;
 746         return 0;
 747 }
 748
 749 int __attribute__((cold))
 750 i40e_txq_vec_setup(struct i40e_tx_queue __rte_unused *txq)
 751 {
 752         return 0;
 753 }
 754
 755 int __attribute__((cold))
 756 i40e_rx_vec_dev_conf_condition_check(struct rte_eth_dev *dev)
 757 {
 758 #ifndef RTE_LIBRTE_IEEE1588
 759         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
 760         struct rte_fdir_conf *fconf = &dev->data->dev_conf.fdir_conf;
 761
 762         /* need SSE4.1 support */
 763         if (!rte_cpu_get_flag_enabled(RTE_CPUFLAG_SSE4_1))
 764                 return -1;
 765
 766 #ifndef RTE_LIBRTE_I40E_RX_OLFLAGS_ENABLE
 767         /* whithout rx ol_flags, no VP flag report */
 768         if (rxmode->hw_vlan_strip != 0 ||
 769             rxmode->hw_vlan_extend != 0)
 770                 return -1;
 771 #endif
 772
 773         /* no fdir support */
 774         if (fconf->mode != RTE_FDIR_MODE_NONE)
 775                 return -1;
 776
 777          /* - no csum error report support
 778          * - no header split support
 779          */
 780         if (rxmode->hw_ip_checksum == 1 ||
 781             rxmode->header_split == 1)
 782                 return -1;
 783
 784         return 0;
 785 #else
 786         RTE_SET_USED(dev);
 787         return -1;
 788 #endif
 789 }