1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010 - 2015 Intel Corporation
3 * Copyright(c) 2017 IBM Corporation.
7 #include <ethdev_driver.h>
8 #include <rte_malloc.h>
10 #include "base/i40e_prototype.h"
11 #include "base/i40e_type.h"
12 #include "i40e_ethdev.h"
13 #include "i40e_rxtx.h"
14 #include "i40e_rxtx_vec_common.h"
16 #include <rte_altivec.h>
18 #pragma GCC diagnostic ignored "-Wcast-qual"
21 i40e_rxq_rearm(struct i40e_rx_queue *rxq)
25 volatile union i40e_rx_desc *rxdp;
27 struct i40e_rx_entry *rxep = &rxq->sw_ring[rxq->rxrearm_start];
28 struct rte_mbuf *mb0, *mb1;
30 vector unsigned long hdr_room = (vector unsigned long){
32 RTE_PKTMBUF_HEADROOM};
33 vector unsigned long dma_addr0, dma_addr1;
35 rxdp = rxq->rx_ring + rxq->rxrearm_start;
37 /* Pull 'n' more MBUFs into the software ring */
38 if (rte_mempool_get_bulk(rxq->mp,
40 RTE_I40E_RXQ_REARM_THRESH) < 0) {
41 if (rxq->rxrearm_nb + RTE_I40E_RXQ_REARM_THRESH >=
43 dma_addr0 = (vector unsigned long){};
44 for (i = 0; i < RTE_I40E_DESCS_PER_LOOP; i++) {
45 rxep[i].mbuf = &rxq->fake_mbuf;
47 (vector unsigned long *)&rxdp[i].read);
50 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
51 RTE_I40E_RXQ_REARM_THRESH;
55 /* Initialize the mbufs in vector, process 2 mbufs in one loop */
56 for (i = 0; i < RTE_I40E_RXQ_REARM_THRESH; i += 2, rxep += 2) {
57 vector unsigned long vaddr0, vaddr1;
63 /* Flush mbuf with pkt template.
64 * Data to be rearmed is 6 bytes long.
65 * Though, RX will overwrite ol_flags that are coming next
66 * anyway. So overwrite whole 8 bytes with one load:
67 * 6 bytes of rearm_data plus first 2 bytes of ol_flags.
69 p0 = (uintptr_t)&mb0->rearm_data;
70 *(uint64_t *)p0 = rxq->mbuf_initializer;
71 p1 = (uintptr_t)&mb1->rearm_data;
72 *(uint64_t *)p1 = rxq->mbuf_initializer;
74 /* load buf_addr(lo 64bit) and buf_iova(hi 64bit) */
75 vaddr0 = vec_ld(0, (vector unsigned long *)&mb0->buf_addr);
76 vaddr1 = vec_ld(0, (vector unsigned long *)&mb1->buf_addr);
78 /* convert pa to dma_addr hdr/data */
79 dma_addr0 = vec_mergel(vaddr0, vaddr0);
80 dma_addr1 = vec_mergel(vaddr1, vaddr1);
82 /* add headroom to pa values */
83 dma_addr0 = vec_add(dma_addr0, hdr_room);
84 dma_addr1 = vec_add(dma_addr1, hdr_room);
86 /* flush desc with pa dma_addr */
87 vec_st(dma_addr0, 0, (vector unsigned long *)&rxdp++->read);
88 vec_st(dma_addr1, 0, (vector unsigned long *)&rxdp++->read);
91 rxq->rxrearm_start += RTE_I40E_RXQ_REARM_THRESH;
92 if (rxq->rxrearm_start >= rxq->nb_rx_desc)
93 rxq->rxrearm_start = 0;
95 rxq->rxrearm_nb -= RTE_I40E_RXQ_REARM_THRESH;
97 rx_id = (uint16_t)((rxq->rxrearm_start == 0) ?
98 (rxq->nb_rx_desc - 1) : (rxq->rxrearm_start - 1));
100 /* Update the tail pointer on the NIC */
101 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
105 desc_to_olflags_v(vector unsigned long descs[4], struct rte_mbuf **rx_pkts)
107 vector unsigned int vlan0, vlan1, rss, l3_l4e;
109 /* mask everything except RSS, flow director and VLAN flags
110 * bit2 is for VLAN tag, bit11 for flow director indication
111 * bit13:12 for RSS indication.
113 const vector unsigned int rss_vlan_msk = (vector unsigned int){
114 (int32_t)0x1c03804, (int32_t)0x1c03804,
115 (int32_t)0x1c03804, (int32_t)0x1c03804};
117 /* map rss and vlan type to rss hash and vlan flag */
118 const vector unsigned char vlan_flags = (vector unsigned char){
120 PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED, 0, 0, 0,
124 const vector unsigned char rss_flags = (vector unsigned char){
125 0, PKT_RX_FDIR, 0, 0,
126 0, 0, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH | PKT_RX_FDIR,
130 const vector unsigned char l3_l4e_flags = (vector unsigned char){
134 PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD,
135 PKT_RX_OUTER_IP_CKSUM_BAD,
136 PKT_RX_OUTER_IP_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD,
137 PKT_RX_OUTER_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD,
138 PKT_RX_OUTER_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD
139 | PKT_RX_IP_CKSUM_BAD,
140 0, 0, 0, 0, 0, 0, 0, 0};
142 vlan0 = (vector unsigned int)vec_mergel(descs[0], descs[1]);
143 vlan1 = (vector unsigned int)vec_mergel(descs[2], descs[3]);
144 vlan0 = (vector unsigned int)vec_mergeh(vlan0, vlan1);
146 vlan1 = vec_and(vlan0, rss_vlan_msk);
147 vlan0 = (vector unsigned int)vec_perm(vlan_flags,
148 (vector unsigned char){},
149 *(vector unsigned char *)&vlan1);
151 rss = vec_sr(vlan1, (vector unsigned int){11, 11, 11, 11});
152 rss = (vector unsigned int)vec_perm(rss_flags, (vector unsigned char){},
153 *(vector unsigned char *)&rss);
155 l3_l4e = vec_sr(vlan1, (vector unsigned int){22, 22, 22, 22});
156 l3_l4e = (vector unsigned int)vec_perm(l3_l4e_flags,
157 (vector unsigned char){},
158 *(vector unsigned char *)&l3_l4e);
160 vlan0 = vec_or(vlan0, rss);
161 vlan0 = vec_or(vlan0, l3_l4e);
163 rx_pkts[0]->ol_flags = (uint64_t)vlan0[2];
164 rx_pkts[1]->ol_flags = (uint64_t)vlan0[3];
165 rx_pkts[2]->ol_flags = (uint64_t)vlan0[0];
166 rx_pkts[3]->ol_flags = (uint64_t)vlan0[1];
169 #define PKTLEN_SHIFT 10
172 desc_to_ptype_v(vector unsigned long descs[4], struct rte_mbuf **rx_pkts,
175 vector unsigned long ptype0 = vec_mergel(descs[0], descs[1]);
176 vector unsigned long ptype1 = vec_mergel(descs[2], descs[3]);
178 ptype0 = vec_sr(ptype0, (vector unsigned long){30, 30});
179 ptype1 = vec_sr(ptype1, (vector unsigned long){30, 30});
181 rx_pkts[0]->packet_type =
182 ptype_tbl[(*(vector unsigned char *)&ptype0)[0]];
183 rx_pkts[1]->packet_type =
184 ptype_tbl[(*(vector unsigned char *)&ptype0)[8]];
185 rx_pkts[2]->packet_type =
186 ptype_tbl[(*(vector unsigned char *)&ptype1)[0]];
187 rx_pkts[3]->packet_type =
188 ptype_tbl[(*(vector unsigned char *)&ptype1)[8]];
192 * vPMD raw receive routine, only accept(nb_pkts >= RTE_I40E_DESCS_PER_LOOP)
195 * - nb_pkts < RTE_I40E_DESCS_PER_LOOP, just return no packet
196 * - floor align nb_pkts to a RTE_I40E_DESCS_PER_LOOP power-of-two
198 static inline uint16_t
199 _recv_raw_pkts_vec(struct i40e_rx_queue *rxq, struct rte_mbuf **rx_pkts,
200 uint16_t nb_pkts, uint8_t *split_packet)
202 volatile union i40e_rx_desc *rxdp;
203 struct i40e_rx_entry *sw_ring;
204 uint16_t nb_pkts_recd;
207 vector unsigned char shuf_msk;
208 uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
210 vector unsigned short crc_adjust = (vector unsigned short){
211 0, 0, /* ignore pkt_type field */
212 rxq->crc_len, /* sub crc on pkt_len */
213 0, /* ignore high-16bits of pkt_len */
214 rxq->crc_len, /* sub crc on data_len */
215 0, 0, 0 /* ignore non-length fields */
217 vector unsigned long dd_check, eop_check;
219 /* nb_pkts has to be floor-aligned to RTE_I40E_DESCS_PER_LOOP */
220 nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, RTE_I40E_DESCS_PER_LOOP);
222 /* Just the act of getting into the function from the application is
223 * going to cost about 7 cycles
225 rxdp = rxq->rx_ring + rxq->rx_tail;
229 /* See if we need to rearm the RX queue - gives the prefetch a bit
232 if (rxq->rxrearm_nb > RTE_I40E_RXQ_REARM_THRESH)
235 /* Before we start moving massive data around, check to see if
236 * there is actually a packet available
238 if (!(rxdp->wb.qword1.status_error_len &
239 rte_cpu_to_le_32(1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
242 /* 4 packets DD mask */
243 dd_check = (vector unsigned long){0x0000000100000001ULL,
244 0x0000000100000001ULL};
246 /* 4 packets EOP mask */
247 eop_check = (vector unsigned long){0x0000000200000002ULL,
248 0x0000000200000002ULL};
250 /* mask to shuffle from desc. to mbuf */
251 shuf_msk = (vector unsigned char){
252 0xFF, 0xFF, /* pkt_type set as unknown */
253 0xFF, 0xFF, /* pkt_type set as unknown */
254 14, 15, /* octet 15~14, low 16 bits pkt_len */
255 0xFF, 0xFF, /* skip high 16 bits pkt_len, zero out */
256 14, 15, /* octet 15~14, 16 bits data_len */
257 2, 3, /* octet 2~3, low 16 bits vlan_macip */
258 4, 5, 6, 7 /* octet 4~7, 32bits rss */
261 /* Cache is empty -> need to scan the buffer rings, but first move
262 * the next 'n' mbufs into the cache
264 sw_ring = &rxq->sw_ring[rxq->rx_tail];
266 /* A. load 4 packet in one loop
267 * [A*. mask out 4 unused dirty field in desc]
268 * B. copy 4 mbuf point from swring to rx_pkts
269 * C. calc the number of DD bits among the 4 packets
270 * [C*. extract the end-of-packet bit, if requested]
271 * D. fill info. from desc to mbuf
274 for (pos = 0, nb_pkts_recd = 0; pos < nb_pkts;
275 pos += RTE_I40E_DESCS_PER_LOOP,
276 rxdp += RTE_I40E_DESCS_PER_LOOP) {
277 vector unsigned long descs[RTE_I40E_DESCS_PER_LOOP];
278 vector unsigned char pkt_mb1, pkt_mb2, pkt_mb3, pkt_mb4;
279 vector unsigned short staterr, sterr_tmp1, sterr_tmp2;
280 vector unsigned long mbp1, mbp2; /* two mbuf pointer
284 /* B.1 load 2 mbuf point */
285 mbp1 = *(vector unsigned long *)&sw_ring[pos];
286 /* Read desc statuses backwards to avoid race condition */
287 /* A.1 load desc[3] */
288 descs[3] = *(vector unsigned long *)(rxdp + 3);
289 rte_compiler_barrier();
291 /* B.2 copy 2 mbuf point into rx_pkts */
292 *(vector unsigned long *)&rx_pkts[pos] = mbp1;
294 /* B.1 load 2 mbuf point */
295 mbp2 = *(vector unsigned long *)&sw_ring[pos + 2];
297 /* A.1 load desc[2-0] */
298 descs[2] = *(vector unsigned long *)(rxdp + 2);
299 rte_compiler_barrier();
300 descs[1] = *(vector unsigned long *)(rxdp + 1);
301 rte_compiler_barrier();
302 descs[0] = *(vector unsigned long *)(rxdp);
304 /* B.2 copy 2 mbuf point into rx_pkts */
305 *(vector unsigned long *)&rx_pkts[pos + 2] = mbp2;
308 rte_mbuf_prefetch_part2(rx_pkts[pos]);
309 rte_mbuf_prefetch_part2(rx_pkts[pos + 1]);
310 rte_mbuf_prefetch_part2(rx_pkts[pos + 2]);
311 rte_mbuf_prefetch_part2(rx_pkts[pos + 3]);
314 /* avoid compiler reorder optimization */
315 rte_compiler_barrier();
317 /* pkt 3,4 shift the pktlen field to be 16-bit aligned*/
318 const vector unsigned int len3 = vec_sl(
319 vec_ld(0, (vector unsigned int *)&descs[3]),
320 (vector unsigned int){0, 0, 0, PKTLEN_SHIFT});
322 const vector unsigned int len2 = vec_sl(
323 vec_ld(0, (vector unsigned int *)&descs[2]),
324 (vector unsigned int){0, 0, 0, PKTLEN_SHIFT});
326 /* merge the now-aligned packet length fields back in */
327 descs[3] = (vector unsigned long)len3;
328 descs[2] = (vector unsigned long)len2;
330 /* D.1 pkt 3,4 convert format from desc to pktmbuf */
331 pkt_mb4 = vec_perm((vector unsigned char)descs[3],
332 (vector unsigned char){}, shuf_msk);
333 pkt_mb3 = vec_perm((vector unsigned char)descs[2],
334 (vector unsigned char){}, shuf_msk);
336 /* C.1 4=>2 filter staterr info only */
337 sterr_tmp2 = vec_mergel((vector unsigned short)descs[3],
338 (vector unsigned short)descs[2]);
339 /* C.1 4=>2 filter staterr info only */
340 sterr_tmp1 = vec_mergel((vector unsigned short)descs[1],
341 (vector unsigned short)descs[0]);
342 /* D.2 pkt 3,4 set in_port/nb_seg and remove crc */
343 pkt_mb4 = (vector unsigned char)vec_sub(
344 (vector unsigned short)pkt_mb4, crc_adjust);
345 pkt_mb3 = (vector unsigned char)vec_sub(
346 (vector unsigned short)pkt_mb3, crc_adjust);
348 /* pkt 1,2 shift the pktlen field to be 16-bit aligned*/
349 const vector unsigned int len1 = vec_sl(
350 vec_ld(0, (vector unsigned int *)&descs[1]),
351 (vector unsigned int){0, 0, 0, PKTLEN_SHIFT});
352 const vector unsigned int len0 = vec_sl(
353 vec_ld(0, (vector unsigned int *)&descs[0]),
354 (vector unsigned int){0, 0, 0, PKTLEN_SHIFT});
356 /* merge the now-aligned packet length fields back in */
357 descs[1] = (vector unsigned long)len1;
358 descs[0] = (vector unsigned long)len0;
360 /* D.1 pkt 1,2 convert format from desc to pktmbuf */
361 pkt_mb2 = vec_perm((vector unsigned char)descs[1],
362 (vector unsigned char){}, shuf_msk);
363 pkt_mb1 = vec_perm((vector unsigned char)descs[0],
364 (vector unsigned char){}, shuf_msk);
366 /* C.2 get 4 pkts staterr value */
367 staterr = (vector unsigned short)vec_mergeh(
368 sterr_tmp1, sterr_tmp2);
370 /* D.3 copy final 3,4 data to rx_pkts */
372 (vector unsigned char *)&rx_pkts[pos + 3]
373 ->rx_descriptor_fields1
376 (vector unsigned char *)&rx_pkts[pos + 2]
377 ->rx_descriptor_fields1
380 /* D.2 pkt 1,2 set in_port/nb_seg and remove crc */
381 pkt_mb2 = (vector unsigned char)vec_sub(
382 (vector unsigned short)pkt_mb2, crc_adjust);
383 pkt_mb1 = (vector unsigned char)vec_sub(
384 (vector unsigned short)pkt_mb1, crc_adjust);
386 /* C* extract and record EOP bit */
388 vector unsigned char eop_shuf_mask =
389 (vector unsigned char){
390 0xFF, 0xFF, 0xFF, 0xFF,
391 0xFF, 0xFF, 0xFF, 0xFF,
392 0xFF, 0xFF, 0xFF, 0xFF,
393 0x04, 0x0C, 0x00, 0x08
396 /* and with mask to extract bits, flipping 1-0 */
397 vector unsigned char eop_bits = vec_and(
398 (vector unsigned char)vec_nor(staterr, staterr),
399 (vector unsigned char)eop_check);
400 /* the staterr values are not in order, as the count
401 * of dd bits doesn't care. However, for end of
402 * packet tracking, we do care, so shuffle. This also
403 * compresses the 32-bit values to 8-bit
405 eop_bits = vec_perm(eop_bits, (vector unsigned char){},
407 /* store the resulting 32-bit value */
408 *split_packet = (vec_ld(0,
409 (vector unsigned int *)&eop_bits))[0];
410 split_packet += RTE_I40E_DESCS_PER_LOOP;
412 /* zero-out next pointers */
413 rx_pkts[pos]->next = NULL;
414 rx_pkts[pos + 1]->next = NULL;
415 rx_pkts[pos + 2]->next = NULL;
416 rx_pkts[pos + 3]->next = NULL;
419 /* C.3 calc available number of desc */
420 staterr = vec_and(staterr, (vector unsigned short)dd_check);
422 /* D.3 copy final 1,2 data to rx_pkts */
424 (vector unsigned char *)&rx_pkts[pos + 1]
425 ->rx_descriptor_fields1
428 (vector unsigned char *)&rx_pkts[pos]->rx_descriptor_fields1
430 desc_to_ptype_v(descs, &rx_pkts[pos], ptype_tbl);
431 desc_to_olflags_v(descs, &rx_pkts[pos]);
433 /* C.4 calc avaialbe number of desc */
434 var = __builtin_popcountll((vec_ld(0,
435 (vector unsigned long *)&staterr)[0]));
437 if (likely(var != RTE_I40E_DESCS_PER_LOOP))
441 /* Update our internal tail pointer */
442 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_pkts_recd);
443 rxq->rx_tail = (uint16_t)(rxq->rx_tail & (rxq->nb_rx_desc - 1));
444 rxq->rxrearm_nb = (uint16_t)(rxq->rxrearm_nb + nb_pkts_recd);
450 * - nb_pkts < RTE_I40E_DESCS_PER_LOOP, just return no packet
451 * - nb_pkts > RTE_I40E_VPMD_RX_BURST, only scan RTE_I40E_VPMD_RX_BURST
455 i40e_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
458 return _recv_raw_pkts_vec(rx_queue, rx_pkts, nb_pkts, NULL);
462 * vPMD receive routine that reassembles single burst of 32 scattered packets
465 * - nb_pkts < RTE_I40E_DESCS_PER_LOOP, just return no packet
468 i40e_recv_scattered_burst_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
471 struct i40e_rx_queue *rxq = rx_queue;
472 uint8_t split_flags[RTE_I40E_VPMD_RX_BURST] = {0};
474 /* get some new buffers */
475 uint16_t nb_bufs = _recv_raw_pkts_vec(rxq, rx_pkts, nb_pkts,
480 /* happy day case, full burst + no packets to be joined */
481 const uint64_t *split_fl64 = (uint64_t *)split_flags;
483 if (rxq->pkt_first_seg == NULL &&
484 split_fl64[0] == 0 && split_fl64[1] == 0 &&
485 split_fl64[2] == 0 && split_fl64[3] == 0)
488 /* reassemble any packets that need reassembly*/
491 if (!rxq->pkt_first_seg) {
492 /* find the first split flag, and only reassemble then*/
493 while (i < nb_bufs && !split_flags[i])
498 return i + reassemble_packets(rxq, &rx_pkts[i], nb_bufs - i,
503 * vPMD receive routine that reassembles scattered packets.
506 i40e_recv_scattered_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
511 while (nb_pkts > RTE_I40E_VPMD_RX_BURST) {
514 burst = i40e_recv_scattered_burst_vec(rx_queue,
516 RTE_I40E_VPMD_RX_BURST);
519 if (burst < RTE_I40E_VPMD_RX_BURST)
523 return retval + i40e_recv_scattered_burst_vec(rx_queue,
529 vtx1(volatile struct i40e_tx_desc *txdp,
530 struct rte_mbuf *pkt, uint64_t flags)
532 uint64_t high_qw = (I40E_TX_DESC_DTYPE_DATA |
533 ((uint64_t)flags << I40E_TXD_QW1_CMD_SHIFT) |
534 ((uint64_t)pkt->data_len << I40E_TXD_QW1_TX_BUF_SZ_SHIFT));
536 vector unsigned long descriptor = (vector unsigned long){
537 pkt->buf_iova + pkt->data_off, high_qw};
538 *(vector unsigned long *)txdp = descriptor;
542 vtx(volatile struct i40e_tx_desc *txdp,
543 struct rte_mbuf **pkt, uint16_t nb_pkts, uint64_t flags)
547 for (i = 0; i < nb_pkts; ++i, ++txdp, ++pkt)
548 vtx1(txdp, *pkt, flags);
552 i40e_xmit_fixed_burst_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
555 struct i40e_tx_queue *txq = (struct i40e_tx_queue *)tx_queue;
556 volatile struct i40e_tx_desc *txdp;
557 struct i40e_tx_entry *txep;
558 uint16_t n, nb_commit, tx_id;
559 uint64_t flags = I40E_TD_CMD;
560 uint64_t rs = I40E_TX_DESC_CMD_RS | I40E_TD_CMD;
563 /* cross rx_thresh boundary is not allowed */
564 nb_pkts = RTE_MIN(nb_pkts, txq->tx_rs_thresh);
566 if (txq->nb_tx_free < txq->tx_free_thresh)
567 i40e_tx_free_bufs(txq);
569 nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
571 if (unlikely(nb_pkts == 0))
574 tx_id = txq->tx_tail;
575 txdp = &txq->tx_ring[tx_id];
576 txep = &txq->sw_ring[tx_id];
578 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
580 n = (uint16_t)(txq->nb_tx_desc - tx_id);
581 if (nb_commit >= n) {
582 tx_backlog_entry(txep, tx_pkts, n);
584 for (i = 0; i < n - 1; ++i, ++tx_pkts, ++txdp)
585 vtx1(txdp, *tx_pkts, flags);
587 vtx1(txdp, *tx_pkts++, rs);
589 nb_commit = (uint16_t)(nb_commit - n);
592 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
594 /* avoid reach the end of ring */
595 txdp = &txq->tx_ring[tx_id];
596 txep = &txq->sw_ring[tx_id];
599 tx_backlog_entry(txep, tx_pkts, nb_commit);
601 vtx(txdp, tx_pkts, nb_commit, flags);
603 tx_id = (uint16_t)(tx_id + nb_commit);
604 if (tx_id > txq->tx_next_rs) {
605 txq->tx_ring[txq->tx_next_rs].cmd_type_offset_bsz |=
606 rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
607 I40E_TXD_QW1_CMD_SHIFT);
609 (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
612 txq->tx_tail = tx_id;
614 I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
620 i40e_rx_queue_release_mbufs_vec(struct i40e_rx_queue *rxq)
622 _i40e_rx_queue_release_mbufs_vec(rxq);
626 i40e_rxq_vec_setup(struct i40e_rx_queue *rxq)
628 return i40e_rxq_vec_setup_default(rxq);
632 i40e_txq_vec_setup(struct i40e_tx_queue __rte_unused * txq)
638 i40e_rx_vec_dev_conf_condition_check(struct rte_eth_dev *dev)
640 return i40e_rx_vec_dev_conf_condition_check_default(dev);