1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2020 Intel Corporation
6 #include <rte_ethdev_driver.h>
7 #include <rte_malloc.h>
9 #include "base/i40e_prototype.h"
10 #include "base/i40e_type.h"
11 #include "i40e_ethdev.h"
12 #include "i40e_rxtx.h"
13 #include "i40e_rxtx_vec_common.h"
17 #ifndef __INTEL_COMPILER
18 #pragma GCC diagnostic ignored "-Wcast-qual"
21 #define RTE_I40E_DESCS_PER_LOOP_AVX 8
24 i40e_rxq_rearm(struct i40e_rx_queue *rxq)
28 volatile union i40e_rx_desc *rxdp;
29 struct i40e_rx_entry *rxep = &rxq->sw_ring[rxq->rxrearm_start];
30 struct rte_mempool_cache *cache = rte_mempool_default_cache(rxq->mp,
33 rxdp = rxq->rx_ring + rxq->rxrearm_start;
35 /* We need to pull 'n' more MBUFs into the software ring from mempool
36 * We inline the mempool function here, so we can vectorize the copy
37 * from the cache into the shadow ring.
40 if (cache->len < RTE_I40E_RXQ_REARM_THRESH) {
41 /* No. Backfill the cache first, and then fill from it */
42 uint32_t req = RTE_I40E_RXQ_REARM_THRESH + (cache->size -
45 /* How many do we require
46 * i.e. number to fill the cache + the request
48 int ret = rte_mempool_ops_dequeue_bulk(rxq->mp,
49 &cache->objs[cache->len], req);
53 if (rxq->rxrearm_nb + RTE_I40E_RXQ_REARM_THRESH >=
57 dma_addr0 = _mm_setzero_si128();
58 for (i = 0; i < RTE_I40E_DESCS_PER_LOOP; i++) {
59 rxep[i].mbuf = &rxq->fake_mbuf;
61 ((__m128i *)&rxdp[i].read,
65 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
66 RTE_I40E_RXQ_REARM_THRESH;
71 const __m512i iova_offsets = _mm512_set1_epi64
72 (offsetof(struct rte_mbuf, buf_iova));
73 const __m512i headroom = _mm512_set1_epi64(RTE_PKTMBUF_HEADROOM);
75 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
76 /* to shuffle the addresses to correct slots. Values 4-7 will contain
77 * zeros, so use 7 for a zero-value.
79 const __m512i permute_idx = _mm512_set_epi64(7, 7, 3, 1, 7, 7, 2, 0);
81 const __m512i permute_idx = _mm512_set_epi64(7, 3, 6, 2, 5, 1, 4, 0);
84 /* Initialize the mbufs in vector, process 8 mbufs in one loop, taking
85 * from mempool cache and populating both shadow and HW rings
87 for (i = 0; i < RTE_I40E_RXQ_REARM_THRESH / 8; i++) {
88 const __m512i mbuf_ptrs = _mm512_loadu_si512
89 (&cache->objs[cache->len - 8]);
90 _mm512_store_si512(rxep, mbuf_ptrs);
92 /* gather iova of mbuf0-7 into one zmm reg */
93 const __m512i iova_base_addrs = _mm512_i64gather_epi64
94 (_mm512_add_epi64(mbuf_ptrs, iova_offsets),
97 const __m512i iova_addrs = _mm512_add_epi64(iova_base_addrs,
99 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
100 const __m512i iovas0 = _mm512_castsi256_si512
101 (_mm512_extracti64x4_epi64(iova_addrs, 0));
102 const __m512i iovas1 = _mm512_castsi256_si512
103 (_mm512_extracti64x4_epi64(iova_addrs, 1));
105 /* permute leaves desc 2-3 addresses in header address slots 0-1
106 * but these are ignored by driver since header split not
107 * enabled. Similarly for desc 4 & 5.
109 const __m512i desc_rd_0_1 = _mm512_permutexvar_epi64
110 (permute_idx, iovas0);
111 const __m512i desc_rd_2_3 = _mm512_bsrli_epi128(desc_rd_0_1, 8);
113 const __m512i desc_rd_4_5 = _mm512_permutexvar_epi64
114 (permute_idx, iovas1);
115 const __m512i desc_rd_6_7 = _mm512_bsrli_epi128(desc_rd_4_5, 8);
117 _mm512_store_si512((void *)rxdp, desc_rd_0_1);
118 _mm512_store_si512((void *)(rxdp + 2), desc_rd_2_3);
119 _mm512_store_si512((void *)(rxdp + 4), desc_rd_4_5);
120 _mm512_store_si512((void *)(rxdp + 6), desc_rd_6_7);
122 /* permute leaves desc 4-7 addresses in header address slots 0-3
123 * but these are ignored by driver since header split not
126 const __m512i desc_rd_0_3 = _mm512_permutexvar_epi64
127 (permute_idx, iova_addrs);
128 const __m512i desc_rd_4_7 = _mm512_bsrli_epi128(desc_rd_0_3, 8);
130 _mm512_store_si512((void *)rxdp, desc_rd_0_3);
131 _mm512_store_si512((void *)(rxdp + 4), desc_rd_4_7);
133 rxep += 8, rxdp += 8, cache->len -= 8;
136 rxq->rxrearm_start += RTE_I40E_RXQ_REARM_THRESH;
137 if (rxq->rxrearm_start >= rxq->nb_rx_desc)
138 rxq->rxrearm_start = 0;
140 rxq->rxrearm_nb -= RTE_I40E_RXQ_REARM_THRESH;
142 rx_id = (uint16_t)((rxq->rxrearm_start == 0) ?
143 (rxq->nb_rx_desc - 1) : (rxq->rxrearm_start - 1));
145 /* Update the tail pointer on the NIC */
146 I40E_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
149 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
150 /* Handles 32B descriptor FDIR ID processing:
151 * rxdp: receive descriptor ring, required to load 2nd 16B half of each desc
152 * rx_pkts: required to store metadata back to mbufs
153 * pkt_idx: offset into the burst, increments in vector widths
154 * desc_idx: required to select the correct shift at compile time
156 static inline __m256i
157 desc_fdir_processing_32b(volatile union i40e_rx_desc *rxdp,
158 struct rte_mbuf **rx_pkts,
159 const uint32_t pkt_idx,
160 const uint32_t desc_idx)
162 /* 32B desc path: load rxdp.wb.qword2 for EXT_STATUS and FLEXBH_STAT */
163 __m128i *rxdp_desc_0 = (void *)(&rxdp[desc_idx + 0].wb.qword2);
164 __m128i *rxdp_desc_1 = (void *)(&rxdp[desc_idx + 1].wb.qword2);
165 const __m128i desc_qw2_0 = _mm_load_si128(rxdp_desc_0);
166 const __m128i desc_qw2_1 = _mm_load_si128(rxdp_desc_1);
168 /* Mask for FLEXBH_STAT, and the FDIR_ID value to compare against. The
169 * remaining data is set to all 1's to pass through data.
171 const __m256i flexbh_mask = _mm256_set_epi32(-1, -1, -1, 3 << 4,
173 const __m256i flexbh_id = _mm256_set_epi32(-1, -1, -1, 1 << 4,
176 /* Load descriptor, check for FLEXBH bits, generate a mask for both
177 * packets in the register.
179 __m256i desc_qw2_0_1 =
180 _mm256_inserti128_si256(_mm256_castsi128_si256(desc_qw2_0),
182 __m256i desc_tmp_msk = _mm256_and_si256(flexbh_mask, desc_qw2_0_1);
183 __m256i fdir_mask = _mm256_cmpeq_epi32(flexbh_id, desc_tmp_msk);
184 __m256i fdir_data = _mm256_alignr_epi8(desc_qw2_0_1, desc_qw2_0_1, 12);
185 __m256i desc_fdir_data = _mm256_and_si256(fdir_mask, fdir_data);
187 /* Write data out to the mbuf. There is no store to this area of the
188 * mbuf today, so we cannot combine it with another store.
190 const uint32_t idx_0 = pkt_idx + desc_idx;
191 const uint32_t idx_1 = pkt_idx + desc_idx + 1;
193 rx_pkts[idx_0]->hash.fdir.hi = _mm256_extract_epi32(desc_fdir_data, 0);
194 rx_pkts[idx_1]->hash.fdir.hi = _mm256_extract_epi32(desc_fdir_data, 4);
196 /* Create mbuf flags as required for mbuf_flags layout
197 * (That's high lane [1,3,5,7, 0,2,4,6] as u32 lanes).
199 * - Mask away bits not required from the fdir_mask
200 * - Leave the PKT_FDIR_ID bit (1 << 13)
201 * - Position that bit correctly based on packet number
202 * - OR in the resulting bit to mbuf_flags
204 RTE_BUILD_BUG_ON(PKT_RX_FDIR_ID != (1 << 13));
205 __m256i mbuf_flag_mask = _mm256_set_epi32(0, 0, 0, 1 << 13,
207 __m256i desc_flag_bit = _mm256_and_si256(mbuf_flag_mask, fdir_mask);
209 /* For static-inline function, this will be stripped out
210 * as the desc_idx is a hard-coded constant.
214 return _mm256_alignr_epi8(desc_flag_bit, desc_flag_bit, 4);
216 return _mm256_alignr_epi8(desc_flag_bit, desc_flag_bit, 8);
218 return _mm256_alignr_epi8(desc_flag_bit, desc_flag_bit, 12);
220 return desc_flag_bit;
225 /* NOT REACHED, see above switch returns */
226 return _mm256_setzero_si256();
228 #endif /* RTE_LIBRTE_I40E_16BYTE_RX_DESC */
230 #define PKTLEN_SHIFT 10
232 /* Force inline as some compilers will not inline by default. */
233 static __rte_always_inline uint16_t
234 _recv_raw_pkts_vec_avx512(struct i40e_rx_queue *rxq, struct rte_mbuf **rx_pkts,
235 uint16_t nb_pkts, uint8_t *split_packet)
237 const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
238 const __m256i mbuf_init = _mm256_set_epi64x(0, 0,
239 0, rxq->mbuf_initializer);
240 struct i40e_rx_entry *sw_ring = &rxq->sw_ring[rxq->rx_tail];
241 volatile union i40e_rx_desc *rxdp = rxq->rx_ring + rxq->rx_tail;
245 /* nb_pkts has to be floor-aligned to RTE_I40E_DESCS_PER_LOOP_AVX */
246 nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, RTE_I40E_DESCS_PER_LOOP_AVX);
248 /* See if we need to rearm the RX queue - gives the prefetch a bit
251 if (rxq->rxrearm_nb > RTE_I40E_RXQ_REARM_THRESH)
254 /* Before we start moving massive data around, check to see if
255 * there is actually a packet available
257 if (!(rxdp->wb.qword1.status_error_len &
258 rte_cpu_to_le_32(1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
261 /* constants used in processing loop */
262 const __m512i crc_adjust =
264 (0, /* ignore non-length fields */
265 -rxq->crc_len, /* sub crc on data_len */
266 -rxq->crc_len, /* sub crc on pkt_len */
267 0 /* ignore non-length fields */
270 /* 8 packets DD mask, LSB in each 32-bit value */
271 const __m256i dd_check = _mm256_set1_epi32(1);
273 /* 8 packets EOP mask, second-LSB in each 32-bit value */
274 const __m256i eop_check = _mm256_slli_epi32(dd_check,
275 I40E_RX_DESC_STATUS_EOF_SHIFT);
277 /* mask to shuffle from desc. to mbuf (2 descriptors)*/
278 const __m512i shuf_msk =
280 (/* rss hash parsed separately */
281 /* octet 4~7, 32bits rss */
282 7 << 24 | 6 << 16 | 5 << 8 | 4,
283 /* octet 2~3, low 16 bits vlan_macip */
284 /* octet 14~15, 16 bits data_len */
285 3 << 24 | 2 << 16 | 15 << 8 | 14,
286 /* skip hi 16 bits pkt_len, zero out */
287 /* octet 14~15, 16 bits pkt_len */
288 0xFFFF << 16 | 15 << 8 | 14,
289 /* pkt_type set as unknown */
292 /* compile-time check the above crc and shuffle layout is correct.
293 * NOTE: the first field (lowest address) is given last in set_epi
296 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
297 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);
298 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=
299 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);
300 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, vlan_tci) !=
301 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 10);
302 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, hash) !=
303 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 12);
305 /* Status/Error flag masks */
306 /* mask everything except RSS, flow director and VLAN flags
307 * bit2 is for VLAN tag, bit11 for flow director indication
308 * bit13:12 for RSS indication. Bits 3-5 of error
309 * field (bits 22-24) are for IP/L4 checksum errors
311 const __m256i flags_mask = _mm256_set1_epi32
312 ((1 << 2) | (1 << 11) | (3 << 12) | (7 << 22));
314 /* data to be shuffled by result of flag mask. If VLAN bit is set,
315 * (bit 2), then position 4 in this array will be used in the
318 const __m256i vlan_flags_shuf = _mm256_set_epi32
319 (0, 0, PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED, 0,
320 0, 0, PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED, 0);
322 /* data to be shuffled by result of flag mask, shifted down 11.
323 * If RSS/FDIR bits are set, shuffle moves appropriate flags in
326 const __m256i rss_flags_shuf = _mm256_set_epi8
327 (0, 0, 0, 0, 0, 0, 0, 0,
328 PKT_RX_RSS_HASH | PKT_RX_FDIR, PKT_RX_RSS_HASH, 0, 0,
329 0, 0, PKT_RX_FDIR, 0, /* end up 128-bits */
330 0, 0, 0, 0, 0, 0, 0, 0,
331 PKT_RX_RSS_HASH | PKT_RX_FDIR, PKT_RX_RSS_HASH, 0, 0,
332 0, 0, PKT_RX_FDIR, 0);
334 /* data to be shuffled by the result of the flags mask shifted by 22
335 * bits. This gives use the l3_l4 flags.
337 const __m256i l3_l4_flags_shuf = _mm256_set_epi8
338 (0, 0, 0, 0, 0, 0, 0, 0,
339 /* shift right 1 bit to make sure it not exceed 255 */
340 (PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD |
341 PKT_RX_IP_CKSUM_BAD) >> 1,
342 (PKT_RX_IP_CKSUM_GOOD | PKT_RX_EIP_CKSUM_BAD |
343 PKT_RX_L4_CKSUM_BAD) >> 1,
344 (PKT_RX_EIP_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,
345 (PKT_RX_IP_CKSUM_GOOD | PKT_RX_EIP_CKSUM_BAD) >> 1,
346 (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,
347 (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD) >> 1,
348 PKT_RX_IP_CKSUM_BAD >> 1,
349 (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD) >> 1,
350 /* second 128-bits */
351 0, 0, 0, 0, 0, 0, 0, 0,
352 (PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD |
353 PKT_RX_IP_CKSUM_BAD) >> 1,
354 (PKT_RX_IP_CKSUM_GOOD | PKT_RX_EIP_CKSUM_BAD |
355 PKT_RX_L4_CKSUM_BAD) >> 1,
356 (PKT_RX_EIP_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,
357 (PKT_RX_IP_CKSUM_GOOD | PKT_RX_EIP_CKSUM_BAD) >> 1,
358 (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,
359 (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD) >> 1,
360 PKT_RX_IP_CKSUM_BAD >> 1,
361 (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD) >> 1);
363 const __m256i cksum_mask = _mm256_set1_epi32
364 (PKT_RX_IP_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD |
365 PKT_RX_L4_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD |
366 PKT_RX_EIP_CKSUM_BAD);
368 uint16_t i, received;
370 for (i = 0, received = 0; i < nb_pkts;
371 i += RTE_I40E_DESCS_PER_LOOP_AVX,
372 rxdp += RTE_I40E_DESCS_PER_LOOP_AVX) {
373 /* step 1, copy over 8 mbuf pointers to rx_pkts array */
374 _mm256_storeu_si256((void *)&rx_pkts[i],
375 _mm256_loadu_si256((void *)&sw_ring[i]));
376 #ifdef RTE_ARCH_X86_64
377 _mm256_storeu_si256((void *)&rx_pkts[i + 4],
378 _mm256_loadu_si256((void *)&sw_ring[i + 4]));
381 __m512i raw_desc0_3, raw_desc4_7;
382 __m256i raw_desc0_1, raw_desc2_3, raw_desc4_5, raw_desc6_7;
384 /* load in descriptors, in reverse order */
385 const __m128i raw_desc7 =
386 _mm_load_si128((void *)(rxdp + 7));
387 rte_compiler_barrier();
388 const __m128i raw_desc6 =
389 _mm_load_si128((void *)(rxdp + 6));
390 rte_compiler_barrier();
391 const __m128i raw_desc5 =
392 _mm_load_si128((void *)(rxdp + 5));
393 rte_compiler_barrier();
394 const __m128i raw_desc4 =
395 _mm_load_si128((void *)(rxdp + 4));
396 rte_compiler_barrier();
397 const __m128i raw_desc3 =
398 _mm_load_si128((void *)(rxdp + 3));
399 rte_compiler_barrier();
400 const __m128i raw_desc2 =
401 _mm_load_si128((void *)(rxdp + 2));
402 rte_compiler_barrier();
403 const __m128i raw_desc1 =
404 _mm_load_si128((void *)(rxdp + 1));
405 rte_compiler_barrier();
406 const __m128i raw_desc0 =
407 _mm_load_si128((void *)(rxdp + 0));
410 _mm256_inserti128_si256
411 (_mm256_castsi128_si256(raw_desc6),
414 _mm256_inserti128_si256
415 (_mm256_castsi128_si256(raw_desc4),
418 _mm256_inserti128_si256
419 (_mm256_castsi128_si256(raw_desc2),
422 _mm256_inserti128_si256
423 (_mm256_castsi128_si256(raw_desc0),
428 (_mm512_castsi256_si512(raw_desc4_5),
432 (_mm512_castsi256_si512(raw_desc0_1),
438 for (j = 0; j < RTE_I40E_DESCS_PER_LOOP_AVX; j++)
439 rte_mbuf_prefetch_part2(rx_pkts[i + j]);
442 /* convert descriptors 0-7 into mbufs, adjusting length and
443 * re-arranging fields. Then write into the mbuf
445 const __m512i len4_7 = _mm512_slli_epi32
446 (raw_desc4_7, PKTLEN_SHIFT);
447 const __m512i len0_3 = _mm512_slli_epi32
448 (raw_desc0_3, PKTLEN_SHIFT);
449 const __m512i desc4_7 = _mm512_mask_blend_epi16
450 (0x80808080, raw_desc4_7, len4_7);
451 const __m512i desc0_3 = _mm512_mask_blend_epi16
452 (0x80808080, raw_desc0_3, len0_3);
453 __m512i mb4_7 = _mm512_shuffle_epi8(desc4_7, shuf_msk);
454 __m512i mb0_3 = _mm512_shuffle_epi8(desc0_3, shuf_msk);
456 mb4_7 = _mm512_add_epi32(mb4_7, crc_adjust);
457 mb0_3 = _mm512_add_epi32(mb0_3, crc_adjust);
459 /* to get packet types, shift 64-bit values down 30 bits
460 * and so ptype is in lower 8-bits in each
462 const __m512i ptypes4_7 = _mm512_srli_epi64(desc4_7, 30);
463 const __m512i ptypes0_3 = _mm512_srli_epi64(desc0_3, 30);
464 const __m256i ptypes6_7 =
465 _mm512_extracti64x4_epi64(ptypes4_7, 1);
466 const __m256i ptypes4_5 =
467 _mm512_extracti64x4_epi64(ptypes4_7, 0);
468 const __m256i ptypes2_3 =
469 _mm512_extracti64x4_epi64(ptypes0_3, 1);
470 const __m256i ptypes0_1 =
471 _mm512_extracti64x4_epi64(ptypes0_3, 0);
472 const uint8_t ptype7 = _mm256_extract_epi8(ptypes6_7, 24);
473 const uint8_t ptype6 = _mm256_extract_epi8(ptypes6_7, 8);
474 const uint8_t ptype5 = _mm256_extract_epi8(ptypes4_5, 24);
475 const uint8_t ptype4 = _mm256_extract_epi8(ptypes4_5, 8);
476 const uint8_t ptype3 = _mm256_extract_epi8(ptypes2_3, 24);
477 const uint8_t ptype2 = _mm256_extract_epi8(ptypes2_3, 8);
478 const uint8_t ptype1 = _mm256_extract_epi8(ptypes0_1, 24);
479 const uint8_t ptype0 = _mm256_extract_epi8(ptypes0_1, 8);
481 const __m512i ptype4_7 = _mm512_set_epi32
482 (0, 0, 0, ptype_tbl[ptype7],
483 0, 0, 0, ptype_tbl[ptype6],
484 0, 0, 0, ptype_tbl[ptype5],
485 0, 0, 0, ptype_tbl[ptype4]);
486 const __m512i ptype0_3 = _mm512_set_epi32
487 (0, 0, 0, ptype_tbl[ptype3],
488 0, 0, 0, ptype_tbl[ptype2],
489 0, 0, 0, ptype_tbl[ptype1],
490 0, 0, 0, ptype_tbl[ptype0]);
492 mb4_7 = _mm512_mask_blend_epi32(0x1111, mb4_7, ptype4_7);
493 mb0_3 = _mm512_mask_blend_epi32(0x1111, mb0_3, ptype0_3);
495 __m256i mb4_5 = _mm512_extracti64x4_epi64(mb4_7, 0);
496 __m256i mb6_7 = _mm512_extracti64x4_epi64(mb4_7, 1);
497 __m256i mb0_1 = _mm512_extracti64x4_epi64(mb0_3, 0);
498 __m256i mb2_3 = _mm512_extracti64x4_epi64(mb0_3, 1);
501 * use permute/extract to get status content
502 * After the operations, the packets status flags are in the
503 * order (hi->lo): [1, 3, 5, 7, 0, 2, 4, 6]
505 /* merge the status bits into one register */
506 const __m512i status_permute_msk = _mm512_set_epi32
511 const __m512i raw_status0_7 = _mm512_permutex2var_epi32
512 (desc4_7, status_permute_msk, desc0_3);
513 __m256i status0_7 = _mm512_extracti64x4_epi64
516 /* now do flag manipulation */
518 /* get only flag/error bits we want */
519 const __m256i flag_bits =
520 _mm256_and_si256(status0_7, flags_mask);
521 /* set vlan and rss flags */
522 const __m256i vlan_flags =
523 _mm256_shuffle_epi8(vlan_flags_shuf, flag_bits);
524 const __m256i rss_fdir_bits = _mm256_srli_epi32(flag_bits, 11);
525 const __m256i rss_flags = _mm256_shuffle_epi8(rss_flags_shuf,
528 /* l3_l4_error flags, shuffle, then shift to correct adjustment
529 * of flags in flags_shuf, and finally mask out extra bits
531 __m256i l3_l4_flags = _mm256_shuffle_epi8(l3_l4_flags_shuf,
532 _mm256_srli_epi32(flag_bits, 22));
533 l3_l4_flags = _mm256_slli_epi32(l3_l4_flags, 1);
534 l3_l4_flags = _mm256_and_si256(l3_l4_flags, cksum_mask);
537 __m256i mbuf_flags = _mm256_or_si256(l3_l4_flags,
538 _mm256_or_si256(rss_flags, vlan_flags));
540 /* If the rxq has FDIR enabled, read and process the FDIR info
541 * from the descriptor. This can cause more loads/stores, so is
542 * not always performed. Branch over the code when not enabled.
544 if (rxq->fdir_enabled) {
545 #ifdef RTE_LIBRTE_I40E_16BYTE_RX_DESC
546 /* 16B descriptor code path:
547 * RSS and FDIR ID use the same offset in the desc, so
548 * only one can be present at a time. The code below
549 * identifies an FDIR ID match, and zeros the RSS value
550 * in the mbuf on FDIR match to keep mbuf data clean.
552 #define FDIR_BLEND_MASK ((1 << 3) | (1 << 7))
555 * - Take flags, shift bits to null out
556 * - CMPEQ with known FDIR ID, to get 0xFFFF or 0 mask
557 * - Strip bits from mask, leaving 0 or 1 for FDIR ID
558 * - Merge with mbuf_flags
560 /* FLM = 1, FLTSTAT = 0b01, (FLM | FLTSTAT) == 3.
561 * Shift left by 28 to avoid having to mask.
564 _mm256_slli_epi32(rss_fdir_bits, 28);
565 const __m256i fdir_id = _mm256_set1_epi32(3 << 28);
567 /* As above, the fdir_mask to packet mapping is this:
568 * order (hi->lo): [1, 3, 5, 7, 0, 2, 4, 6]
569 * Then OR FDIR flags to mbuf_flags on FDIR ID hit.
571 RTE_BUILD_BUG_ON(PKT_RX_FDIR_ID != (1 << 13));
572 const __m256i pkt_fdir_bit = _mm256_set1_epi32(1 << 13);
573 const __m256i fdir_mask =
574 _mm256_cmpeq_epi32(fdir, fdir_id);
576 _mm256_and_si256(fdir_mask, pkt_fdir_bit);
578 mbuf_flags = _mm256_or_si256(mbuf_flags, fdir_bits);
580 /* Based on FDIR_MASK, clear the RSS or FDIR value.
581 * The FDIR ID value is masked to zero if not a hit,
582 * otherwise the mb0_1 register RSS field is zeroed.
584 const __m256i fdir_zero_mask = _mm256_setzero_si256();
585 __m256i tmp0_1 = _mm256_blend_epi32(fdir_zero_mask,
586 fdir_mask, FDIR_BLEND_MASK);
587 __m256i fdir_mb0_1 = _mm256_and_si256(mb0_1, fdir_mask);
589 mb0_1 = _mm256_andnot_si256(tmp0_1, mb0_1);
591 /* Write to mbuf: no stores to combine with, so just a
592 * scalar store to push data here.
594 rx_pkts[i + 0]->hash.fdir.hi =
595 _mm256_extract_epi32(fdir_mb0_1, 3);
596 rx_pkts[i + 1]->hash.fdir.hi =
597 _mm256_extract_epi32(fdir_mb0_1, 7);
599 /* Same as above, only shift the fdir_mask to align
600 * the packet FDIR mask with the FDIR_ID desc lane.
603 _mm256_alignr_epi8(fdir_mask, fdir_mask, 12);
604 __m256i fdir_mb2_3 = _mm256_and_si256(mb2_3, tmp2_3);
606 tmp2_3 = _mm256_blend_epi32(fdir_zero_mask, tmp2_3,
608 mb2_3 = _mm256_andnot_si256(tmp2_3, mb2_3);
609 rx_pkts[i + 2]->hash.fdir.hi =
610 _mm256_extract_epi32(fdir_mb2_3, 3);
611 rx_pkts[i + 3]->hash.fdir.hi =
612 _mm256_extract_epi32(fdir_mb2_3, 7);
615 _mm256_alignr_epi8(fdir_mask, fdir_mask, 8);
616 __m256i fdir_mb4_5 = _mm256_and_si256(mb4_5, tmp4_5);
618 tmp4_5 = _mm256_blend_epi32(fdir_zero_mask, tmp4_5,
620 mb4_5 = _mm256_andnot_si256(tmp4_5, mb4_5);
621 rx_pkts[i + 4]->hash.fdir.hi =
622 _mm256_extract_epi32(fdir_mb4_5, 3);
623 rx_pkts[i + 5]->hash.fdir.hi =
624 _mm256_extract_epi32(fdir_mb4_5, 7);
627 _mm256_alignr_epi8(fdir_mask, fdir_mask, 4);
628 __m256i fdir_mb6_7 = _mm256_and_si256(mb6_7, tmp6_7);
630 tmp6_7 = _mm256_blend_epi32(fdir_zero_mask, tmp6_7,
632 mb6_7 = _mm256_andnot_si256(tmp6_7, mb6_7);
633 rx_pkts[i + 6]->hash.fdir.hi =
634 _mm256_extract_epi32(fdir_mb6_7, 3);
635 rx_pkts[i + 7]->hash.fdir.hi =
636 _mm256_extract_epi32(fdir_mb6_7, 7);
638 /* End of 16B descriptor handling */
640 /* 32B descriptor FDIR ID mark handling. Returns bits
641 * to be OR-ed into the mbuf olflags.
643 __m256i fdir_add_flags;
646 desc_fdir_processing_32b(rxdp, rx_pkts, i, 0);
648 _mm256_or_si256(mbuf_flags, fdir_add_flags);
651 desc_fdir_processing_32b(rxdp, rx_pkts, i, 2);
653 _mm256_or_si256(mbuf_flags, fdir_add_flags);
656 desc_fdir_processing_32b(rxdp, rx_pkts, i, 4);
658 _mm256_or_si256(mbuf_flags, fdir_add_flags);
661 desc_fdir_processing_32b(rxdp, rx_pkts, i, 6);
663 _mm256_or_si256(mbuf_flags, fdir_add_flags);
664 /* End 32B desc handling */
665 #endif /* RTE_LIBRTE_I40E_16BYTE_RX_DESC */
667 } /* if() on FDIR enabled */
669 /* At this point, we have the 8 sets of flags in the low 16-bits
670 * of each 32-bit value in vlan0.
671 * We want to extract these, and merge them with the mbuf init data
672 * so we can do a single write to the mbuf to set the flags
673 * and all the other initialization fields. Extracting the
674 * appropriate flags means that we have to do a shift and blend for
675 * each mbuf before we do the write. However, we can also
676 * add in the previously computed rx_descriptor fields to
677 * make a single 256-bit write per mbuf
679 /* check the structure matches expectations */
680 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, ol_flags) !=
681 offsetof(struct rte_mbuf, rearm_data) + 8);
682 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, rearm_data) !=
683 RTE_ALIGN(offsetof(struct rte_mbuf, rearm_data), 16));
684 /* build up data and do writes */
685 __m256i rearm0, rearm1, rearm2, rearm3, rearm4, rearm5,
687 rearm6 = _mm256_blend_epi32
688 (mbuf_init, _mm256_slli_si256(mbuf_flags, 8), 0x04);
689 rearm4 = _mm256_blend_epi32
690 (mbuf_init, _mm256_slli_si256(mbuf_flags, 4), 0x04);
691 rearm2 = _mm256_blend_epi32
692 (mbuf_init, mbuf_flags, 0x04);
693 rearm0 = _mm256_blend_epi32
694 (mbuf_init, _mm256_srli_si256(mbuf_flags, 4), 0x04);
695 /* permute to add in the rx_descriptor e.g. rss fields */
696 rearm6 = _mm256_permute2f128_si256(rearm6, mb6_7, 0x20);
697 rearm4 = _mm256_permute2f128_si256(rearm4, mb4_5, 0x20);
698 rearm2 = _mm256_permute2f128_si256(rearm2, mb2_3, 0x20);
699 rearm0 = _mm256_permute2f128_si256(rearm0, mb0_1, 0x20);
702 ((__m256i *)&rx_pkts[i + 6]->rearm_data, rearm6);
704 ((__m256i *)&rx_pkts[i + 4]->rearm_data, rearm4);
706 ((__m256i *)&rx_pkts[i + 2]->rearm_data, rearm2);
708 ((__m256i *)&rx_pkts[i + 0]->rearm_data, rearm0);
710 /* repeat for the odd mbufs */
711 const __m256i odd_flags = _mm256_castsi128_si256
712 (_mm256_extracti128_si256(mbuf_flags, 1));
713 rearm7 = _mm256_blend_epi32
714 (mbuf_init, _mm256_slli_si256(odd_flags, 8), 0x04);
715 rearm5 = _mm256_blend_epi32
716 (mbuf_init, _mm256_slli_si256(odd_flags, 4), 0x04);
717 rearm3 = _mm256_blend_epi32
718 (mbuf_init, odd_flags, 0x04);
719 rearm1 = _mm256_blend_epi32
720 (mbuf_init, _mm256_srli_si256(odd_flags, 4), 0x04);
721 /* since odd mbufs are already in hi 128-bits use blend */
722 rearm7 = _mm256_blend_epi32(rearm7, mb6_7, 0xF0);
723 rearm5 = _mm256_blend_epi32(rearm5, mb4_5, 0xF0);
724 rearm3 = _mm256_blend_epi32(rearm3, mb2_3, 0xF0);
725 rearm1 = _mm256_blend_epi32(rearm1, mb0_1, 0xF0);
726 /* again write to mbufs */
728 ((__m256i *)&rx_pkts[i + 7]->rearm_data, rearm7);
730 ((__m256i *)&rx_pkts[i + 5]->rearm_data, rearm5);
732 ((__m256i *)&rx_pkts[i + 3]->rearm_data, rearm3);
734 ((__m256i *)&rx_pkts[i + 1]->rearm_data, rearm1);
736 /* extract and record EOP bit */
738 const __m128i eop_mask =
740 (1 << I40E_RX_DESC_STATUS_EOF_SHIFT);
741 const __m256i eop_bits256 =
742 _mm256_and_si256(status0_7, eop_check);
743 /* pack status bits into a single 128-bit register */
744 const __m128i eop_bits =
746 (_mm256_castsi256_si128(eop_bits256),
747 _mm256_extractf128_si256(eop_bits256, 1));
748 /* flip bits, and mask out the EOP bit, which is now
749 * a split-packet bit i.e. !EOP, rather than EOP one.
751 __m128i split_bits = _mm_andnot_si128(eop_bits,
753 /* eop bits are out of order, so we need to shuffle them
754 * back into order again. In doing so, only use low 8
755 * bits, which acts like another pack instruction
756 * The original order is (hi->lo): 1,3,5,7,0,2,4,6
757 * [Since we use epi8, the 16-bit positions are
758 * multiplied by 2 in the eop_shuffle value.]
760 __m128i eop_shuffle = _mm_set_epi8
761 (0xFF, 0xFF, 0xFF, 0xFF, /* zero hi 64b */
762 0xFF, 0xFF, 0xFF, 0xFF,
763 8, 0, 10, 2, /* move values to lo 64b */
765 split_bits = _mm_shuffle_epi8(split_bits, eop_shuffle);
766 *(uint64_t *)split_packet =
767 _mm_cvtsi128_si64(split_bits);
768 split_packet += RTE_I40E_DESCS_PER_LOOP_AVX;
771 /* perform dd_check */
772 status0_7 = _mm256_and_si256(status0_7, dd_check);
773 status0_7 = _mm256_packs_epi32
774 (status0_7, _mm256_setzero_si256());
776 uint64_t burst = __builtin_popcountll
778 (_mm256_extracti128_si256
780 burst += __builtin_popcountll(_mm_cvtsi128_si64
781 (_mm256_castsi256_si128(status0_7)));
783 if (burst != RTE_I40E_DESCS_PER_LOOP_AVX)
787 /* update tail pointers */
788 rxq->rx_tail += received;
789 rxq->rx_tail &= (rxq->nb_rx_desc - 1);
790 if ((rxq->rx_tail & 1) == 1 && received > 1) { /* keep avx2 aligned */
794 rxq->rxrearm_nb += received;
800 * - nb_pkts < RTE_I40E_DESCS_PER_LOOP, just return no packet
803 i40e_recv_pkts_vec_avx512(void *rx_queue, struct rte_mbuf **rx_pkts,
806 return _recv_raw_pkts_vec_avx512(rx_queue, rx_pkts, nb_pkts, NULL);
810 * vPMD receive routine that reassembles single burst of 32 scattered packets
812 * - nb_pkts < RTE_I40E_DESCS_PER_LOOP, just return no packet
815 i40e_recv_scattered_burst_vec_avx512(void *rx_queue,
816 struct rte_mbuf **rx_pkts,
819 struct i40e_rx_queue *rxq = rx_queue;
820 uint8_t split_flags[RTE_I40E_VPMD_RX_BURST] = {0};
822 /* get some new buffers */
823 uint16_t nb_bufs = _recv_raw_pkts_vec_avx512(rxq, rx_pkts, nb_pkts,
828 /* happy day case, full burst + no packets to be joined */
829 const uint64_t *split_fl64 = (uint64_t *)split_flags;
831 if (!rxq->pkt_first_seg &&
832 split_fl64[0] == 0 && split_fl64[1] == 0 &&
833 split_fl64[2] == 0 && split_fl64[3] == 0)
836 /* reassemble any packets that need reassembly*/
839 if (!rxq->pkt_first_seg) {
840 /* find the first split flag, and only reassemble then*/
841 while (i < nb_bufs && !split_flags[i])
845 rxq->pkt_first_seg = rx_pkts[i];
847 return i + reassemble_packets(rxq, &rx_pkts[i], nb_bufs - i,
852 * vPMD receive routine that reassembles scattered packets.
853 * Main receive routine that can handle arbitrary burst sizes
855 * - nb_pkts < RTE_I40E_DESCS_PER_LOOP, just return no packet
858 i40e_recv_scattered_pkts_vec_avx512(void *rx_queue,
859 struct rte_mbuf **rx_pkts,
864 while (nb_pkts > RTE_I40E_VPMD_RX_BURST) {
865 uint16_t burst = i40e_recv_scattered_burst_vec_avx512(rx_queue,
866 rx_pkts + retval, RTE_I40E_VPMD_RX_BURST);
869 if (burst < RTE_I40E_VPMD_RX_BURST)
872 return retval + i40e_recv_scattered_burst_vec_avx512(rx_queue,
873 rx_pkts + retval, nb_pkts);
877 vtx1(volatile struct i40e_tx_desc *txdp, struct rte_mbuf *pkt, uint64_t flags)
879 uint64_t high_qw = (I40E_TX_DESC_DTYPE_DATA |
880 ((uint64_t)flags << I40E_TXD_QW1_CMD_SHIFT) |
881 ((uint64_t)pkt->data_len << I40E_TXD_QW1_TX_BUF_SZ_SHIFT));
883 __m128i descriptor = _mm_set_epi64x(high_qw,
884 pkt->buf_iova + pkt->data_off);
885 _mm_store_si128((__m128i *)txdp, descriptor);
889 vtx(volatile struct i40e_tx_desc *txdp,
890 struct rte_mbuf **pkt, uint16_t nb_pkts, uint64_t flags)
892 const uint64_t hi_qw_tmpl = (I40E_TX_DESC_DTYPE_DATA |
893 ((uint64_t)flags << I40E_TXD_QW1_CMD_SHIFT));
895 /* if unaligned on 32-bit boundary, do one to align */
896 if (((uintptr_t)txdp & 0x1F) != 0 && nb_pkts != 0) {
897 vtx1(txdp, *pkt, flags);
898 nb_pkts--, txdp++, pkt++;
901 /* do two at a time while possible, in bursts */
902 for (; nb_pkts > 3; txdp += 4, pkt += 4, nb_pkts -= 4) {
905 ((uint64_t)pkt[3]->data_len <<
906 I40E_TXD_QW1_TX_BUF_SZ_SHIFT);
909 ((uint64_t)pkt[2]->data_len <<
910 I40E_TXD_QW1_TX_BUF_SZ_SHIFT);
913 ((uint64_t)pkt[1]->data_len <<
914 I40E_TXD_QW1_TX_BUF_SZ_SHIFT);
917 ((uint64_t)pkt[0]->data_len <<
918 I40E_TXD_QW1_TX_BUF_SZ_SHIFT);
920 __m256i desc2_3 = _mm256_set_epi64x
921 (hi_qw3, pkt[3]->buf_iova + pkt[3]->data_off,
922 hi_qw2, pkt[2]->buf_iova + pkt[2]->data_off);
923 __m256i desc0_1 = _mm256_set_epi64x
924 (hi_qw1, pkt[1]->buf_iova + pkt[1]->data_off,
925 hi_qw0, pkt[0]->buf_iova + pkt[0]->data_off);
926 _mm256_store_si256((void *)(txdp + 2), desc2_3);
927 _mm256_store_si256((void *)txdp, desc0_1);
930 /* do any last ones */
932 vtx1(txdp, *pkt, flags);
933 txdp++, pkt++, nb_pkts--;
937 static inline uint16_t
938 i40e_xmit_fixed_burst_vec_avx512(void *tx_queue, struct rte_mbuf **tx_pkts,
941 struct i40e_tx_queue *txq = (struct i40e_tx_queue *)tx_queue;
942 volatile struct i40e_tx_desc *txdp;
943 struct i40e_tx_entry *txep;
944 uint16_t n, nb_commit, tx_id;
945 uint64_t flags = I40E_TD_CMD;
946 uint64_t rs = I40E_TX_DESC_CMD_RS | I40E_TD_CMD;
948 /* cross rx_thresh boundary is not allowed */
949 nb_pkts = RTE_MIN(nb_pkts, txq->tx_rs_thresh);
951 if (txq->nb_tx_free < txq->tx_free_thresh)
952 i40e_tx_free_bufs(txq);
954 nb_commit = nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
955 if (unlikely(nb_pkts == 0))
958 tx_id = txq->tx_tail;
959 txdp = &txq->tx_ring[tx_id];
960 txep = &txq->sw_ring[tx_id];
962 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
964 n = (uint16_t)(txq->nb_tx_desc - tx_id);
965 if (nb_commit >= n) {
966 tx_backlog_entry(txep, tx_pkts, n);
968 vtx(txdp, tx_pkts, n - 1, flags);
972 vtx1(txdp, *tx_pkts++, rs);
974 nb_commit = (uint16_t)(nb_commit - n);
977 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
979 /* avoid reach the end of ring */
980 txdp = &txq->tx_ring[tx_id];
981 txep = &txq->sw_ring[tx_id];
984 tx_backlog_entry(txep, tx_pkts, nb_commit);
986 vtx(txdp, tx_pkts, nb_commit, flags);
988 tx_id = (uint16_t)(tx_id + nb_commit);
989 if (tx_id > txq->tx_next_rs) {
990 txq->tx_ring[txq->tx_next_rs].cmd_type_offset_bsz |=
991 rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
992 I40E_TXD_QW1_CMD_SHIFT);
994 (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
997 txq->tx_tail = tx_id;
999 I40E_PCI_REG_WC_WRITE(txq->qtx_tail, txq->tx_tail);
1005 i40e_xmit_pkts_vec_avx512(void *tx_queue, struct rte_mbuf **tx_pkts,
1009 struct i40e_tx_queue *txq = (struct i40e_tx_queue *)tx_queue;
1014 num = (uint16_t)RTE_MIN(nb_pkts, txq->tx_rs_thresh);
1015 ret = i40e_xmit_fixed_burst_vec_avx512
1016 (tx_queue, &tx_pkts[nb_tx], num);