1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2015 Intel Corporation.
3 * Copyright(c) 2016-2018, Linaro Limited.
7 #include <ethdev_driver.h>
8 #include <rte_malloc.h>
11 #include "base/i40e_prototype.h"
12 #include "base/i40e_type.h"
13 #include "i40e_ethdev.h"
14 #include "i40e_rxtx.h"
15 #include "i40e_rxtx_vec_common.h"
18 #pragma GCC diagnostic ignored "-Wcast-qual"
21 i40e_rxq_rearm(struct i40e_rx_queue *rxq)
25 volatile union i40e_rx_desc *rxdp;
26 struct i40e_rx_entry *rxep = &rxq->sw_ring[rxq->rxrearm_start];
27 struct rte_mbuf *mb0, *mb1;
28 uint64x2_t dma_addr0, dma_addr1;
29 uint64x2_t zero = vdupq_n_u64(0);
32 rxdp = rxq->rx_ring + rxq->rxrearm_start;
34 /* Pull 'n' more MBUFs into the software ring */
35 if (unlikely(rte_mempool_get_bulk(rxq->mp,
37 RTE_I40E_RXQ_REARM_THRESH) < 0)) {
38 if (rxq->rxrearm_nb + RTE_I40E_RXQ_REARM_THRESH >=
40 for (i = 0; i < RTE_I40E_DESCS_PER_LOOP; i++) {
41 rxep[i].mbuf = &rxq->fake_mbuf;
42 vst1q_u64((uint64_t *)&rxdp[i].read, zero);
45 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
46 RTE_I40E_RXQ_REARM_THRESH;
50 /* Initialize the mbufs in vector, process 2 mbufs in one loop */
51 for (i = 0; i < RTE_I40E_RXQ_REARM_THRESH; i += 2, rxep += 2) {
55 paddr = mb0->buf_iova + RTE_PKTMBUF_HEADROOM;
56 dma_addr0 = vdupq_n_u64(paddr);
58 /* flush desc with pa dma_addr */
59 vst1q_u64((uint64_t *)&rxdp++->read, dma_addr0);
61 paddr = mb1->buf_iova + RTE_PKTMBUF_HEADROOM;
62 dma_addr1 = vdupq_n_u64(paddr);
63 vst1q_u64((uint64_t *)&rxdp++->read, dma_addr1);
66 rxq->rxrearm_start += RTE_I40E_RXQ_REARM_THRESH;
67 if (rxq->rxrearm_start >= rxq->nb_rx_desc)
68 rxq->rxrearm_start = 0;
70 rxq->rxrearm_nb -= RTE_I40E_RXQ_REARM_THRESH;
72 rx_id = (uint16_t)((rxq->rxrearm_start == 0) ?
73 (rxq->nb_rx_desc - 1) : (rxq->rxrearm_start - 1));
76 /* Update the tail pointer on the NIC */
77 I40E_PCI_REG_WRITE_RELAXED(rxq->qrx_tail, rx_id);
81 desc_to_olflags_v(struct i40e_rx_queue *rxq, uint64x2_t descs[4],
82 struct rte_mbuf **rx_pkts)
84 uint32x4_t vlan0, vlan1, rss, l3_l4e;
85 const uint64x2_t mbuf_init = {rxq->mbuf_initializer, 0};
86 uint64x2_t rearm0, rearm1, rearm2, rearm3;
88 /* mask everything except RSS, flow director and VLAN flags
89 * bit2 is for VLAN tag, bit11 for flow director indication
90 * bit13:12 for RSS indication.
92 const uint32x4_t rss_vlan_msk = {
93 0x1c03804, 0x1c03804, 0x1c03804, 0x1c03804};
95 const uint32x4_t cksum_mask = {
96 RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_IP_CKSUM_BAD |
97 RTE_MBUF_F_RX_L4_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_BAD |
98 RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD,
99 RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_IP_CKSUM_BAD |
100 RTE_MBUF_F_RX_L4_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_BAD |
101 RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD,
102 RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_IP_CKSUM_BAD |
103 RTE_MBUF_F_RX_L4_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_BAD |
104 RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD,
105 RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_IP_CKSUM_BAD |
106 RTE_MBUF_F_RX_L4_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_BAD |
107 RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD};
109 /* map rss and vlan type to rss hash and vlan flag */
110 const uint8x16_t vlan_flags = {
112 RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED, 0, 0, 0,
116 const uint8x16_t rss_flags = {
117 0, RTE_MBUF_F_RX_FDIR, 0, 0,
118 0, 0, RTE_MBUF_F_RX_RSS_HASH, RTE_MBUF_F_RX_RSS_HASH | RTE_MBUF_F_RX_FDIR,
122 const uint8x16_t l3_l4e_flags = {
123 (RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_GOOD) >> 1,
124 RTE_MBUF_F_RX_IP_CKSUM_BAD >> 1,
125 (RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_BAD) >> 1,
126 (RTE_MBUF_F_RX_L4_CKSUM_BAD | RTE_MBUF_F_RX_IP_CKSUM_BAD) >> 1,
127 (RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD) >> 1,
128 (RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD | RTE_MBUF_F_RX_IP_CKSUM_BAD) >> 1,
129 (RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD |
130 RTE_MBUF_F_RX_L4_CKSUM_BAD) >> 1,
131 (RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD | RTE_MBUF_F_RX_L4_CKSUM_BAD |
132 RTE_MBUF_F_RX_IP_CKSUM_BAD) >> 1,
133 0, 0, 0, 0, 0, 0, 0, 0};
135 vlan0 = vzipq_u32(vreinterpretq_u32_u64(descs[0]),
136 vreinterpretq_u32_u64(descs[2])).val[1];
137 vlan1 = vzipq_u32(vreinterpretq_u32_u64(descs[1]),
138 vreinterpretq_u32_u64(descs[3])).val[1];
139 vlan0 = vzipq_u32(vlan0, vlan1).val[0];
141 vlan1 = vandq_u32(vlan0, rss_vlan_msk);
142 vlan0 = vreinterpretq_u32_u8(vqtbl1q_u8(vlan_flags,
143 vreinterpretq_u8_u32(vlan1)));
145 rss = vshrq_n_u32(vlan1, 11);
146 rss = vreinterpretq_u32_u8(vqtbl1q_u8(rss_flags,
147 vreinterpretq_u8_u32(rss)));
149 l3_l4e = vshrq_n_u32(vlan1, 22);
150 l3_l4e = vreinterpretq_u32_u8(vqtbl1q_u8(l3_l4e_flags,
151 vreinterpretq_u8_u32(l3_l4e)));
152 /* then we shift left 1 bit */
153 l3_l4e = vshlq_n_u32(l3_l4e, 1);
154 /* we need to mask out the redundant bits */
155 l3_l4e = vandq_u32(l3_l4e, cksum_mask);
157 vlan0 = vorrq_u32(vlan0, rss);
158 vlan0 = vorrq_u32(vlan0, l3_l4e);
160 rearm0 = vsetq_lane_u64(vgetq_lane_u32(vlan0, 0), mbuf_init, 1);
161 rearm1 = vsetq_lane_u64(vgetq_lane_u32(vlan0, 1), mbuf_init, 1);
162 rearm2 = vsetq_lane_u64(vgetq_lane_u32(vlan0, 2), mbuf_init, 1);
163 rearm3 = vsetq_lane_u64(vgetq_lane_u32(vlan0, 3), mbuf_init, 1);
165 vst1q_u64((uint64_t *)&rx_pkts[0]->rearm_data, rearm0);
166 vst1q_u64((uint64_t *)&rx_pkts[1]->rearm_data, rearm1);
167 vst1q_u64((uint64_t *)&rx_pkts[2]->rearm_data, rearm2);
168 vst1q_u64((uint64_t *)&rx_pkts[3]->rearm_data, rearm3);
171 #define PKTLEN_SHIFT 10
172 #define I40E_UINT16_BIT (CHAR_BIT * sizeof(uint16_t))
175 desc_to_ptype_v(uint64x2_t descs[4], struct rte_mbuf **__rte_restrict rx_pkts,
176 uint32_t *__rte_restrict ptype_tbl)
182 for (i = 0; i < 4; i++) {
183 tmp = vreinterpretq_u8_u64(vshrq_n_u64(descs[i], 30));
184 ptype = vgetq_lane_u8(tmp, 8);
185 rx_pkts[i]->packet_type = ptype_tbl[ptype];
191 * vPMD raw receive routine, only accept(nb_pkts >= RTE_I40E_DESCS_PER_LOOP)
194 * - nb_pkts < RTE_I40E_DESCS_PER_LOOP, just return no packet
195 * - floor align nb_pkts to a RTE_I40E_DESCS_PER_LOOP power-of-two
197 static inline uint16_t
198 _recv_raw_pkts_vec(struct i40e_rx_queue *__rte_restrict rxq,
199 struct rte_mbuf **__rte_restrict rx_pkts,
200 uint16_t nb_pkts, uint8_t *split_packet)
202 volatile union i40e_rx_desc *rxdp;
203 struct i40e_rx_entry *sw_ring;
204 uint16_t nb_pkts_recd;
206 uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
208 /* mask to shuffle from desc. to mbuf */
209 uint8x16_t shuf_msk = {
210 0xFF, 0xFF, /* pkt_type set as unknown */
211 0xFF, 0xFF, /* pkt_type set as unknown */
212 14, 15, /* octet 15~14, low 16 bits pkt_len */
213 0xFF, 0xFF, /* skip high 16 bits pkt_len, zero out */
214 14, 15, /* octet 15~14, 16 bits data_len */
215 2, 3, /* octet 2~3, low 16 bits vlan_macip */
216 4, 5, 6, 7 /* octet 4~7, 32bits rss */
219 uint8x16_t eop_check = {
220 0x02, 0x00, 0x02, 0x00,
221 0x02, 0x00, 0x02, 0x00,
222 0x00, 0x00, 0x00, 0x00,
223 0x00, 0x00, 0x00, 0x00
226 uint16x8_t crc_adjust = {
227 0, 0, /* ignore pkt_type field */
228 rxq->crc_len, /* sub crc on pkt_len */
229 0, /* ignore high-16bits of pkt_len */
230 rxq->crc_len, /* sub crc on data_len */
231 0, 0, 0 /* ignore non-length fields */
234 /* nb_pkts has to be floor-aligned to RTE_I40E_DESCS_PER_LOOP */
235 nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, RTE_I40E_DESCS_PER_LOOP);
237 /* Just the act of getting into the function from the application is
238 * going to cost about 7 cycles
240 rxdp = rxq->rx_ring + rxq->rx_tail;
242 rte_prefetch_non_temporal(rxdp);
244 /* See if we need to rearm the RX queue - gives the prefetch a bit
247 if (rxq->rxrearm_nb > RTE_I40E_RXQ_REARM_THRESH)
250 /* Before we start moving massive data around, check to see if
251 * there is actually a packet available
253 if (!(rxdp->wb.qword1.status_error_len &
254 rte_cpu_to_le_32(1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
257 /* Cache is empty -> need to scan the buffer rings, but first move
258 * the next 'n' mbufs into the cache
260 sw_ring = &rxq->sw_ring[rxq->rx_tail];
262 /* A. load 4 packet in one loop
263 * [A*. mask out 4 unused dirty field in desc]
264 * B. copy 4 mbuf point from swring to rx_pkts
265 * C. calc the number of DD bits among the 4 packets
266 * [C*. extract the end-of-packet bit, if requested]
267 * D. fill info. from desc to mbuf
270 for (pos = 0, nb_pkts_recd = 0; pos < nb_pkts;
271 pos += RTE_I40E_DESCS_PER_LOOP,
272 rxdp += RTE_I40E_DESCS_PER_LOOP) {
273 uint64x2_t descs[RTE_I40E_DESCS_PER_LOOP];
274 uint8x16_t pkt_mb1, pkt_mb2, pkt_mb3, pkt_mb4;
275 uint16x8x2_t sterr_tmp1, sterr_tmp2;
276 uint64x2_t mbp1, mbp2;
281 int32x4_t len_shl = {0, 0, 0, PKTLEN_SHIFT};
283 /* A.1 load desc[3-0] */
284 descs[3] = vld1q_u64((uint64_t *)(rxdp + 3));
285 descs[2] = vld1q_u64((uint64_t *)(rxdp + 2));
286 descs[1] = vld1q_u64((uint64_t *)(rxdp + 1));
287 descs[0] = vld1q_u64((uint64_t *)(rxdp));
289 /* Use acquire fence to order loads of descriptor qwords */
290 rte_atomic_thread_fence(__ATOMIC_ACQUIRE);
291 /* A.2 reload qword0 to make it ordered after qword1 load */
292 descs[3] = vld1q_lane_u64((uint64_t *)(rxdp + 3), descs[3], 0);
293 descs[2] = vld1q_lane_u64((uint64_t *)(rxdp + 2), descs[2], 0);
294 descs[1] = vld1q_lane_u64((uint64_t *)(rxdp + 1), descs[1], 0);
295 descs[0] = vld1q_lane_u64((uint64_t *)(rxdp), descs[0], 0);
297 /* B.1 load 4 mbuf point */
298 mbp1 = vld1q_u64((uint64_t *)&sw_ring[pos]);
299 mbp2 = vld1q_u64((uint64_t *)&sw_ring[pos + 2]);
301 /* B.2 copy 4 mbuf point into rx_pkts */
302 vst1q_u64((uint64_t *)&rx_pkts[pos], mbp1);
303 vst1q_u64((uint64_t *)&rx_pkts[pos + 2], mbp2);
306 rte_mbuf_prefetch_part2(rx_pkts[pos]);
307 rte_mbuf_prefetch_part2(rx_pkts[pos + 1]);
308 rte_mbuf_prefetch_part2(rx_pkts[pos + 2]);
309 rte_mbuf_prefetch_part2(rx_pkts[pos + 3]);
312 /* pkts shift the pktlen field to be 16-bit aligned*/
313 uint32x4_t len3 = vshlq_u32(vreinterpretq_u32_u64(descs[3]),
315 descs[3] = vreinterpretq_u64_u16(vsetq_lane_u16
316 (vgetq_lane_u16(vreinterpretq_u16_u32(len3), 7),
317 vreinterpretq_u16_u64(descs[3]),
319 uint32x4_t len2 = vshlq_u32(vreinterpretq_u32_u64(descs[2]),
321 descs[2] = vreinterpretq_u64_u16(vsetq_lane_u16
322 (vgetq_lane_u16(vreinterpretq_u16_u32(len2), 7),
323 vreinterpretq_u16_u64(descs[2]),
325 uint32x4_t len1 = vshlq_u32(vreinterpretq_u32_u64(descs[1]),
327 descs[1] = vreinterpretq_u64_u16(vsetq_lane_u16
328 (vgetq_lane_u16(vreinterpretq_u16_u32(len1), 7),
329 vreinterpretq_u16_u64(descs[1]),
331 uint32x4_t len0 = vshlq_u32(vreinterpretq_u32_u64(descs[0]),
333 descs[0] = vreinterpretq_u64_u16(vsetq_lane_u16
334 (vgetq_lane_u16(vreinterpretq_u16_u32(len0), 7),
335 vreinterpretq_u16_u64(descs[0]),
338 /* D.1 pkts convert format from desc to pktmbuf */
339 pkt_mb4 = vqtbl1q_u8(vreinterpretq_u8_u64(descs[3]), shuf_msk);
340 pkt_mb3 = vqtbl1q_u8(vreinterpretq_u8_u64(descs[2]), shuf_msk);
341 pkt_mb2 = vqtbl1q_u8(vreinterpretq_u8_u64(descs[1]), shuf_msk);
342 pkt_mb1 = vqtbl1q_u8(vreinterpretq_u8_u64(descs[0]), shuf_msk);
344 /* D.2 pkts set in_port/nb_seg and remove crc */
345 tmp = vsubq_u16(vreinterpretq_u16_u8(pkt_mb4), crc_adjust);
346 pkt_mb4 = vreinterpretq_u8_u16(tmp);
347 tmp = vsubq_u16(vreinterpretq_u16_u8(pkt_mb3), crc_adjust);
348 pkt_mb3 = vreinterpretq_u8_u16(tmp);
349 tmp = vsubq_u16(vreinterpretq_u16_u8(pkt_mb2), crc_adjust);
350 pkt_mb2 = vreinterpretq_u8_u16(tmp);
351 tmp = vsubq_u16(vreinterpretq_u16_u8(pkt_mb1), crc_adjust);
352 pkt_mb1 = vreinterpretq_u8_u16(tmp);
354 /* D.3 copy final data to rx_pkts */
355 vst1q_u8((void *)&rx_pkts[pos + 3]->rx_descriptor_fields1,
357 vst1q_u8((void *)&rx_pkts[pos + 2]->rx_descriptor_fields1,
359 vst1q_u8((void *)&rx_pkts[pos + 1]->rx_descriptor_fields1,
361 vst1q_u8((void *)&rx_pkts[pos]->rx_descriptor_fields1,
364 desc_to_ptype_v(descs, &rx_pkts[pos], ptype_tbl);
366 desc_to_olflags_v(rxq, descs, &rx_pkts[pos]);
368 if (likely(pos + RTE_I40E_DESCS_PER_LOOP < nb_pkts)) {
369 rte_prefetch_non_temporal(rxdp + RTE_I40E_DESCS_PER_LOOP);
372 /* C.1 4=>2 filter staterr info only */
373 sterr_tmp2 = vzipq_u16(vreinterpretq_u16_u64(descs[1]),
374 vreinterpretq_u16_u64(descs[3]));
375 sterr_tmp1 = vzipq_u16(vreinterpretq_u16_u64(descs[0]),
376 vreinterpretq_u16_u64(descs[2]));
378 /* C.2 get 4 pkts staterr value */
379 staterr = vzipq_u16(sterr_tmp1.val[1],
380 sterr_tmp2.val[1]).val[0];
382 /* C* extract and record EOP bit */
384 uint8x16_t eop_shuf_mask = {
385 0x00, 0x02, 0x04, 0x06,
386 0xFF, 0xFF, 0xFF, 0xFF,
387 0xFF, 0xFF, 0xFF, 0xFF,
388 0xFF, 0xFF, 0xFF, 0xFF};
391 /* and with mask to extract bits, flipping 1-0 */
392 eop_bits = vmvnq_u8(vreinterpretq_u8_u16(staterr));
393 eop_bits = vandq_u8(eop_bits, eop_check);
394 /* the staterr values are not in order, as the count
395 * of dd bits doesn't care. However, for end of
396 * packet tracking, we do care, so shuffle. This also
397 * compresses the 32-bit values to 8-bit
399 eop_bits = vqtbl1q_u8(eop_bits, eop_shuf_mask);
401 /* store the resulting 32-bit value */
402 vst1q_lane_u32((uint32_t *)split_packet,
403 vreinterpretq_u32_u8(eop_bits), 0);
404 split_packet += RTE_I40E_DESCS_PER_LOOP;
406 /* zero-out next pointers */
407 rx_pkts[pos]->next = NULL;
408 rx_pkts[pos + 1]->next = NULL;
409 rx_pkts[pos + 2]->next = NULL;
410 rx_pkts[pos + 3]->next = NULL;
413 staterr = vshlq_n_u16(staterr, I40E_UINT16_BIT - 1);
414 staterr = vreinterpretq_u16_s16(
415 vshrq_n_s16(vreinterpretq_s16_u16(staterr),
416 I40E_UINT16_BIT - 1));
417 stat = ~vgetq_lane_u64(vreinterpretq_u64_u16(staterr), 0);
419 /* C.4 calc available number of desc */
420 if (unlikely(stat == 0)) {
421 nb_pkts_recd += RTE_I40E_DESCS_PER_LOOP;
423 nb_pkts_recd += __builtin_ctzl(stat) / I40E_UINT16_BIT;
428 /* Update our internal tail pointer */
429 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_pkts_recd);
430 rxq->rx_tail = (uint16_t)(rxq->rx_tail & (rxq->nb_rx_desc - 1));
431 rxq->rxrearm_nb = (uint16_t)(rxq->rxrearm_nb + nb_pkts_recd);
438 * - nb_pkts < RTE_I40E_DESCS_PER_LOOP, just return no packet
439 * - nb_pkts > RTE_I40E_VPMD_RX_BURST, only scan RTE_I40E_VPMD_RX_BURST
443 i40e_recv_pkts_vec(void *__rte_restrict rx_queue,
444 struct rte_mbuf **__rte_restrict rx_pkts, uint16_t nb_pkts)
446 return _recv_raw_pkts_vec(rx_queue, rx_pkts, nb_pkts, NULL);
450 * vPMD receive routine that reassembles single burst of 32 scattered packets
453 * - nb_pkts < RTE_I40E_DESCS_PER_LOOP, just return no packet
456 i40e_recv_scattered_burst_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
460 struct i40e_rx_queue *rxq = rx_queue;
461 uint8_t split_flags[RTE_I40E_VPMD_RX_BURST] = {0};
463 /* get some new buffers */
464 uint16_t nb_bufs = _recv_raw_pkts_vec(rxq, rx_pkts, nb_pkts,
469 /* happy day case, full burst + no packets to be joined */
470 const uint64_t *split_fl64 = (uint64_t *)split_flags;
472 if (rxq->pkt_first_seg == NULL &&
473 split_fl64[0] == 0 && split_fl64[1] == 0 &&
474 split_fl64[2] == 0 && split_fl64[3] == 0)
477 /* reassemble any packets that need reassembly*/
480 if (rxq->pkt_first_seg == NULL) {
481 /* find the first split flag, and only reassemble then*/
482 while (i < nb_bufs && !split_flags[i])
486 rxq->pkt_first_seg = rx_pkts[i];
488 return i + reassemble_packets(rxq, &rx_pkts[i], nb_bufs - i,
493 * vPMD receive routine that reassembles scattered packets.
496 i40e_recv_scattered_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
501 while (nb_pkts > RTE_I40E_VPMD_RX_BURST) {
504 burst = i40e_recv_scattered_burst_vec(rx_queue,
506 RTE_I40E_VPMD_RX_BURST);
509 if (burst < RTE_I40E_VPMD_RX_BURST)
513 return retval + i40e_recv_scattered_burst_vec(rx_queue,
519 vtx1(volatile struct i40e_tx_desc *txdp,
520 struct rte_mbuf *pkt, uint64_t flags)
522 uint64_t high_qw = (I40E_TX_DESC_DTYPE_DATA |
523 ((uint64_t)flags << I40E_TXD_QW1_CMD_SHIFT) |
524 ((uint64_t)pkt->data_len << I40E_TXD_QW1_TX_BUF_SZ_SHIFT));
526 uint64x2_t descriptor = {pkt->buf_iova + pkt->data_off, high_qw};
527 vst1q_u64((uint64_t *)txdp, descriptor);
531 vtx(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkt,
532 uint16_t nb_pkts, uint64_t flags)
536 for (i = 0; i < nb_pkts; ++i, ++txdp, ++pkt)
537 vtx1(txdp, *pkt, flags);
541 i40e_xmit_fixed_burst_vec(void *__rte_restrict tx_queue,
542 struct rte_mbuf **__rte_restrict tx_pkts, uint16_t nb_pkts)
544 struct i40e_tx_queue *txq = (struct i40e_tx_queue *)tx_queue;
545 volatile struct i40e_tx_desc *txdp;
546 struct i40e_tx_entry *txep;
547 uint16_t n, nb_commit, tx_id;
548 uint64_t flags = I40E_TD_CMD;
549 uint64_t rs = I40E_TX_DESC_CMD_RS | I40E_TD_CMD;
552 /* cross rx_thresh boundary is not allowed */
553 nb_pkts = RTE_MIN(nb_pkts, txq->tx_rs_thresh);
555 if (txq->nb_tx_free < txq->tx_free_thresh)
556 i40e_tx_free_bufs(txq);
558 nb_commit = nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
559 if (unlikely(nb_pkts == 0))
562 tx_id = txq->tx_tail;
563 txdp = &txq->tx_ring[tx_id];
564 txep = &txq->sw_ring[tx_id];
566 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
568 n = (uint16_t)(txq->nb_tx_desc - tx_id);
569 if (nb_commit >= n) {
570 tx_backlog_entry(txep, tx_pkts, n);
572 for (i = 0; i < n - 1; ++i, ++tx_pkts, ++txdp)
573 vtx1(txdp, *tx_pkts, flags);
575 vtx1(txdp, *tx_pkts++, rs);
577 nb_commit = (uint16_t)(nb_commit - n);
580 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
582 /* avoid reach the end of ring */
583 txdp = &txq->tx_ring[tx_id];
584 txep = &txq->sw_ring[tx_id];
587 tx_backlog_entry(txep, tx_pkts, nb_commit);
589 vtx(txdp, tx_pkts, nb_commit, flags);
591 tx_id = (uint16_t)(tx_id + nb_commit);
592 if (tx_id > txq->tx_next_rs) {
593 txq->tx_ring[txq->tx_next_rs].cmd_type_offset_bsz |=
594 rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
595 I40E_TXD_QW1_CMD_SHIFT);
597 (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
600 txq->tx_tail = tx_id;
603 I40E_PCI_REG_WRITE_RELAXED(txq->qtx_tail, tx_id);
609 i40e_rx_queue_release_mbufs_vec(struct i40e_rx_queue *rxq)
611 _i40e_rx_queue_release_mbufs_vec(rxq);
615 i40e_rxq_vec_setup(struct i40e_rx_queue *rxq)
617 return i40e_rxq_vec_setup_default(rxq);
621 i40e_txq_vec_setup(struct i40e_tx_queue __rte_unused *txq)
627 i40e_rx_vec_dev_conf_condition_check(struct rte_eth_dev *dev)
629 return i40e_rx_vec_dev_conf_condition_check_default(dev);