4 * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
5 * Copyright(c) 2016, Linaro Limited
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9 * modification, are permitted provided that the following conditions
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15 * notice, this list of conditions and the following disclaimer in
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20 * from this software without specific prior written permission.
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32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 #include <rte_ethdev.h>
37 #include <rte_malloc.h>
39 #include "base/i40e_prototype.h"
40 #include "base/i40e_type.h"
41 #include "i40e_ethdev.h"
42 #include "i40e_rxtx.h"
43 #include "i40e_rxtx_vec_common.h"
47 #pragma GCC diagnostic ignored "-Wcast-qual"
50 i40e_rxq_rearm(struct i40e_rx_queue *rxq)
54 volatile union i40e_rx_desc *rxdp;
55 struct i40e_rx_entry *rxep = &rxq->sw_ring[rxq->rxrearm_start];
56 struct rte_mbuf *mb0, *mb1;
57 uint64x2_t dma_addr0, dma_addr1;
58 uint64x2_t zero = vdupq_n_u64(0);
61 rxdp = rxq->rx_ring + rxq->rxrearm_start;
63 /* Pull 'n' more MBUFs into the software ring */
64 if (unlikely(rte_mempool_get_bulk(rxq->mp,
66 RTE_I40E_RXQ_REARM_THRESH) < 0)) {
67 if (rxq->rxrearm_nb + RTE_I40E_RXQ_REARM_THRESH >=
69 for (i = 0; i < RTE_I40E_DESCS_PER_LOOP; i++) {
70 rxep[i].mbuf = &rxq->fake_mbuf;
71 vst1q_u64((uint64_t *)&rxdp[i].read, zero);
74 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
75 RTE_I40E_RXQ_REARM_THRESH;
79 /* Initialize the mbufs in vector, process 2 mbufs in one loop */
80 for (i = 0; i < RTE_I40E_RXQ_REARM_THRESH; i += 2, rxep += 2) {
84 paddr = mb0->buf_physaddr + RTE_PKTMBUF_HEADROOM;
85 dma_addr0 = vdupq_n_u64(paddr);
87 /* flush desc with pa dma_addr */
88 vst1q_u64((uint64_t *)&rxdp++->read, dma_addr0);
90 paddr = mb1->buf_physaddr + RTE_PKTMBUF_HEADROOM;
91 dma_addr1 = vdupq_n_u64(paddr);
92 vst1q_u64((uint64_t *)&rxdp++->read, dma_addr1);
95 rxq->rxrearm_start += RTE_I40E_RXQ_REARM_THRESH;
96 if (rxq->rxrearm_start >= rxq->nb_rx_desc)
97 rxq->rxrearm_start = 0;
99 rxq->rxrearm_nb -= RTE_I40E_RXQ_REARM_THRESH;
101 rx_id = (uint16_t)((rxq->rxrearm_start == 0) ?
102 (rxq->nb_rx_desc - 1) : (rxq->rxrearm_start - 1));
104 /* Update the tail pointer on the NIC */
105 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
109 desc_to_olflags_v(struct i40e_rx_queue *rxq, uint64x2_t descs[4],
110 struct rte_mbuf **rx_pkts)
112 uint32x4_t vlan0, vlan1, rss, l3_l4e;
113 const uint64x2_t mbuf_init = {rxq->mbuf_initializer, 0};
114 uint64x2_t rearm0, rearm1, rearm2, rearm3;
116 /* mask everything except RSS, flow director and VLAN flags
117 * bit2 is for VLAN tag, bit11 for flow director indication
118 * bit13:12 for RSS indication.
120 const uint32x4_t rss_vlan_msk = {
121 0x1c03804, 0x1c03804, 0x1c03804, 0x1c03804};
123 const uint32x4_t cksum_mask = {
124 PKT_RX_IP_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD |
125 PKT_RX_L4_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD |
126 PKT_RX_EIP_CKSUM_BAD,
127 PKT_RX_IP_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD |
128 PKT_RX_L4_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD |
129 PKT_RX_EIP_CKSUM_BAD,
130 PKT_RX_IP_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD |
131 PKT_RX_L4_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD |
132 PKT_RX_EIP_CKSUM_BAD,
133 PKT_RX_IP_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD |
134 PKT_RX_L4_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD |
135 PKT_RX_EIP_CKSUM_BAD};
137 /* map rss and vlan type to rss hash and vlan flag */
138 const uint8x16_t vlan_flags = {
140 PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED, 0, 0, 0,
144 const uint8x16_t rss_flags = {
145 0, PKT_RX_FDIR, 0, 0,
146 0, 0, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH | PKT_RX_FDIR,
150 const uint8x16_t l3_l4e_flags = {
151 (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD) >> 1,
152 PKT_RX_IP_CKSUM_BAD >> 1,
153 (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD) >> 1,
154 (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,
155 (PKT_RX_IP_CKSUM_GOOD | PKT_RX_EIP_CKSUM_BAD) >> 1,
156 (PKT_RX_EIP_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,
157 (PKT_RX_IP_CKSUM_GOOD | PKT_RX_EIP_CKSUM_BAD |
158 PKT_RX_L4_CKSUM_BAD) >> 1,
159 (PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD |
160 PKT_RX_IP_CKSUM_BAD) >> 1,
161 0, 0, 0, 0, 0, 0, 0, 0};
163 vlan0 = vzipq_u32(vreinterpretq_u32_u64(descs[0]),
164 vreinterpretq_u32_u64(descs[2])).val[1];
165 vlan1 = vzipq_u32(vreinterpretq_u32_u64(descs[1]),
166 vreinterpretq_u32_u64(descs[3])).val[1];
167 vlan0 = vzipq_u32(vlan0, vlan1).val[0];
169 vlan1 = vandq_u32(vlan0, rss_vlan_msk);
170 vlan0 = vreinterpretq_u32_u8(vqtbl1q_u8(vlan_flags,
171 vreinterpretq_u8_u32(vlan1)));
173 rss = vshrq_n_u32(vlan1, 11);
174 rss = vreinterpretq_u32_u8(vqtbl1q_u8(rss_flags,
175 vreinterpretq_u8_u32(rss)));
177 l3_l4e = vshrq_n_u32(vlan1, 22);
178 l3_l4e = vreinterpretq_u32_u8(vqtbl1q_u8(l3_l4e_flags,
179 vreinterpretq_u8_u32(l3_l4e)));
180 /* then we shift left 1 bit */
181 l3_l4e = vshlq_n_u32(l3_l4e, 1);
182 /* we need to mask out the reduntant bits */
183 l3_l4e = vandq_u32(l3_l4e, cksum_mask);
185 vlan0 = vorrq_u32(vlan0, rss);
186 vlan0 = vorrq_u32(vlan0, l3_l4e);
188 rearm0 = vsetq_lane_u64(vgetq_lane_u32(vlan0, 0), mbuf_init, 1);
189 rearm1 = vsetq_lane_u64(vgetq_lane_u32(vlan0, 1), mbuf_init, 1);
190 rearm2 = vsetq_lane_u64(vgetq_lane_u32(vlan0, 2), mbuf_init, 1);
191 rearm3 = vsetq_lane_u64(vgetq_lane_u32(vlan0, 3), mbuf_init, 1);
193 vst1q_u64((uint64_t *)&rx_pkts[0]->rearm_data, rearm0);
194 vst1q_u64((uint64_t *)&rx_pkts[1]->rearm_data, rearm1);
195 vst1q_u64((uint64_t *)&rx_pkts[2]->rearm_data, rearm2);
196 vst1q_u64((uint64_t *)&rx_pkts[3]->rearm_data, rearm3);
199 #define PKTLEN_SHIFT 10
201 #define I40E_VPMD_DESC_DD_MASK 0x0001000100010001ULL
204 desc_to_ptype_v(uint64x2_t descs[4], struct rte_mbuf **rx_pkts,
211 for (i = 0; i < 4; i++) {
212 tmp = vreinterpretq_u8_u64(vshrq_n_u64(descs[i], 30));
213 ptype = vgetq_lane_u8(tmp, 8);
214 rx_pkts[i]->packet_type = ptype_tbl[ptype];
221 * - nb_pkts < RTE_I40E_DESCS_PER_LOOP, just return no packet
222 * - nb_pkts > RTE_I40E_VPMD_RX_BURST, only scan RTE_I40E_VPMD_RX_BURST
225 static inline uint16_t
226 _recv_raw_pkts_vec(struct i40e_rx_queue *rxq, struct rte_mbuf **rx_pkts,
227 uint16_t nb_pkts, uint8_t *split_packet)
229 volatile union i40e_rx_desc *rxdp;
230 struct i40e_rx_entry *sw_ring;
231 uint16_t nb_pkts_recd;
234 uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
236 /* mask to shuffle from desc. to mbuf */
237 uint8x16_t shuf_msk = {
238 0xFF, 0xFF, /* pkt_type set as unknown */
239 0xFF, 0xFF, /* pkt_type set as unknown */
240 14, 15, /* octet 15~14, low 16 bits pkt_len */
241 0xFF, 0xFF, /* skip high 16 bits pkt_len, zero out */
242 14, 15, /* octet 15~14, 16 bits data_len */
243 2, 3, /* octet 2~3, low 16 bits vlan_macip */
244 4, 5, 6, 7 /* octet 4~7, 32bits rss */
247 uint8x16_t eop_check = {
248 0x02, 0x00, 0x02, 0x00,
249 0x02, 0x00, 0x02, 0x00,
250 0x00, 0x00, 0x00, 0x00,
251 0x00, 0x00, 0x00, 0x00
254 uint16x8_t crc_adjust = {
255 0, 0, /* ignore pkt_type field */
256 rxq->crc_len, /* sub crc on pkt_len */
257 0, /* ignore high-16bits of pkt_len */
258 rxq->crc_len, /* sub crc on data_len */
259 0, 0, 0 /* ignore non-length fields */
262 /* nb_pkts shall be less equal than RTE_I40E_MAX_RX_BURST */
263 nb_pkts = RTE_MIN(nb_pkts, RTE_I40E_MAX_RX_BURST);
265 /* nb_pkts has to be floor-aligned to RTE_I40E_DESCS_PER_LOOP */
266 nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, RTE_I40E_DESCS_PER_LOOP);
268 /* Just the act of getting into the function from the application is
269 * going to cost about 7 cycles
271 rxdp = rxq->rx_ring + rxq->rx_tail;
273 rte_prefetch_non_temporal(rxdp);
275 /* See if we need to rearm the RX queue - gives the prefetch a bit
278 if (rxq->rxrearm_nb > RTE_I40E_RXQ_REARM_THRESH)
281 /* Before we start moving massive data around, check to see if
282 * there is actually a packet available
284 if (!(rxdp->wb.qword1.status_error_len &
285 rte_cpu_to_le_32(1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
288 /* Cache is empty -> need to scan the buffer rings, but first move
289 * the next 'n' mbufs into the cache
291 sw_ring = &rxq->sw_ring[rxq->rx_tail];
293 /* A. load 4 packet in one loop
294 * [A*. mask out 4 unused dirty field in desc]
295 * B. copy 4 mbuf point from swring to rx_pkts
296 * C. calc the number of DD bits among the 4 packets
297 * [C*. extract the end-of-packet bit, if requested]
298 * D. fill info. from desc to mbuf
301 for (pos = 0, nb_pkts_recd = 0; pos < nb_pkts;
302 pos += RTE_I40E_DESCS_PER_LOOP,
303 rxdp += RTE_I40E_DESCS_PER_LOOP) {
304 uint64x2_t descs[RTE_I40E_DESCS_PER_LOOP];
305 uint8x16_t pkt_mb1, pkt_mb2, pkt_mb3, pkt_mb4;
306 uint16x8x2_t sterr_tmp1, sterr_tmp2;
307 uint64x2_t mbp1, mbp2;
312 int32x4_t len_shl = {0, 0, 0, PKTLEN_SHIFT};
314 /* B.1 load 1 mbuf point */
315 mbp1 = vld1q_u64((uint64_t *)&sw_ring[pos]);
316 /* Read desc statuses backwards to avoid race condition */
317 /* A.1 load 4 pkts desc */
318 descs[3] = vld1q_u64((uint64_t *)(rxdp + 3));
321 /* B.2 copy 2 mbuf point into rx_pkts */
322 vst1q_u64((uint64_t *)&rx_pkts[pos], mbp1);
324 /* B.1 load 1 mbuf point */
325 mbp2 = vld1q_u64((uint64_t *)&sw_ring[pos + 2]);
327 descs[2] = vld1q_u64((uint64_t *)(rxdp + 2));
328 /* B.1 load 2 mbuf point */
329 descs[1] = vld1q_u64((uint64_t *)(rxdp + 1));
330 descs[0] = vld1q_u64((uint64_t *)(rxdp));
332 /* B.2 copy 2 mbuf point into rx_pkts */
333 vst1q_u64((uint64_t *)&rx_pkts[pos + 2], mbp2);
336 rte_mbuf_prefetch_part2(rx_pkts[pos]);
337 rte_mbuf_prefetch_part2(rx_pkts[pos + 1]);
338 rte_mbuf_prefetch_part2(rx_pkts[pos + 2]);
339 rte_mbuf_prefetch_part2(rx_pkts[pos + 3]);
342 /* avoid compiler reorder optimization */
343 rte_compiler_barrier();
345 /* pkt 3,4 shift the pktlen field to be 16-bit aligned*/
346 uint32x4_t len3 = vshlq_u32(vreinterpretq_u32_u64(descs[3]),
348 descs[3] = vreinterpretq_u64_u32(len3);
349 uint32x4_t len2 = vshlq_u32(vreinterpretq_u32_u64(descs[2]),
351 descs[2] = vreinterpretq_u64_u32(len2);
353 /* D.1 pkt 3,4 convert format from desc to pktmbuf */
354 pkt_mb4 = vqtbl1q_u8(vreinterpretq_u8_u64(descs[3]), shuf_msk);
355 pkt_mb3 = vqtbl1q_u8(vreinterpretq_u8_u64(descs[2]), shuf_msk);
357 /* C.1 4=>2 filter staterr info only */
358 sterr_tmp2 = vzipq_u16(vreinterpretq_u16_u64(descs[1]),
359 vreinterpretq_u16_u64(descs[3]));
360 /* C.1 4=>2 filter staterr info only */
361 sterr_tmp1 = vzipq_u16(vreinterpretq_u16_u64(descs[0]),
362 vreinterpretq_u16_u64(descs[2]));
364 /* C.2 get 4 pkts staterr value */
365 staterr = vzipq_u16(sterr_tmp1.val[1],
366 sterr_tmp2.val[1]).val[0];
367 stat = vgetq_lane_u64(vreinterpretq_u64_u16(staterr), 0);
369 desc_to_olflags_v(rxq, descs, &rx_pkts[pos]);
371 /* D.2 pkt 3,4 set in_port/nb_seg and remove crc */
372 tmp = vsubq_u16(vreinterpretq_u16_u8(pkt_mb4), crc_adjust);
373 pkt_mb4 = vreinterpretq_u8_u16(tmp);
374 tmp = vsubq_u16(vreinterpretq_u16_u8(pkt_mb3), crc_adjust);
375 pkt_mb3 = vreinterpretq_u8_u16(tmp);
377 /* pkt 1,2 shift the pktlen field to be 16-bit aligned*/
378 uint32x4_t len1 = vshlq_u32(vreinterpretq_u32_u64(descs[1]),
380 descs[1] = vreinterpretq_u64_u32(len1);
381 uint32x4_t len0 = vshlq_u32(vreinterpretq_u32_u64(descs[0]),
383 descs[0] = vreinterpretq_u64_u32(len0);
385 /* D.1 pkt 1,2 convert format from desc to pktmbuf */
386 pkt_mb2 = vqtbl1q_u8(vreinterpretq_u8_u64(descs[1]), shuf_msk);
387 pkt_mb1 = vqtbl1q_u8(vreinterpretq_u8_u64(descs[0]), shuf_msk);
389 /* D.3 copy final 3,4 data to rx_pkts */
390 vst1q_u8((void *)&rx_pkts[pos + 3]->rx_descriptor_fields1,
392 vst1q_u8((void *)&rx_pkts[pos + 2]->rx_descriptor_fields1,
395 /* D.2 pkt 1,2 set in_port/nb_seg and remove crc */
396 tmp = vsubq_u16(vreinterpretq_u16_u8(pkt_mb2), crc_adjust);
397 pkt_mb2 = vreinterpretq_u8_u16(tmp);
398 tmp = vsubq_u16(vreinterpretq_u16_u8(pkt_mb1), crc_adjust);
399 pkt_mb1 = vreinterpretq_u8_u16(tmp);
401 /* C* extract and record EOP bit */
403 uint8x16_t eop_shuf_mask = {
404 0x00, 0x02, 0x04, 0x06,
405 0xFF, 0xFF, 0xFF, 0xFF,
406 0xFF, 0xFF, 0xFF, 0xFF,
407 0xFF, 0xFF, 0xFF, 0xFF};
410 /* and with mask to extract bits, flipping 1-0 */
411 eop_bits = vmvnq_u8(vreinterpretq_u8_u16(staterr));
412 eop_bits = vandq_u8(eop_bits, eop_check);
413 /* the staterr values are not in order, as the count
414 * count of dd bits doesn't care. However, for end of
415 * packet tracking, we do care, so shuffle. This also
416 * compresses the 32-bit values to 8-bit
418 eop_bits = vqtbl1q_u8(eop_bits, eop_shuf_mask);
420 /* store the resulting 32-bit value */
421 vst1q_lane_u32((uint32_t *)split_packet,
422 vreinterpretq_u32_u8(eop_bits), 0);
423 split_packet += RTE_I40E_DESCS_PER_LOOP;
425 /* zero-out next pointers */
426 rx_pkts[pos]->next = NULL;
427 rx_pkts[pos + 1]->next = NULL;
428 rx_pkts[pos + 2]->next = NULL;
429 rx_pkts[pos + 3]->next = NULL;
432 rte_prefetch_non_temporal(rxdp + RTE_I40E_DESCS_PER_LOOP);
434 /* D.3 copy final 1,2 data to rx_pkts */
435 vst1q_u8((void *)&rx_pkts[pos + 1]->rx_descriptor_fields1,
437 vst1q_u8((void *)&rx_pkts[pos]->rx_descriptor_fields1,
439 desc_to_ptype_v(descs, &rx_pkts[pos], ptype_tbl);
440 /* C.4 calc avaialbe number of desc */
441 var = __builtin_popcountll(stat & I40E_VPMD_DESC_DD_MASK);
443 if (likely(var != RTE_I40E_DESCS_PER_LOOP))
447 /* Update our internal tail pointer */
448 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_pkts_recd);
449 rxq->rx_tail = (uint16_t)(rxq->rx_tail & (rxq->nb_rx_desc - 1));
450 rxq->rxrearm_nb = (uint16_t)(rxq->rxrearm_nb + nb_pkts_recd);
457 * - nb_pkts < RTE_I40E_DESCS_PER_LOOP, just return no packet
458 * - nb_pkts > RTE_I40E_VPMD_RX_BURST, only scan RTE_I40E_VPMD_RX_BURST
462 i40e_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
465 return _recv_raw_pkts_vec(rx_queue, rx_pkts, nb_pkts, NULL);
468 /* vPMD receive routine that reassembles scattered packets
470 * - nb_pkts < RTE_I40E_DESCS_PER_LOOP, just return no packet
471 * - nb_pkts > RTE_I40E_VPMD_RX_BURST, only scan RTE_I40E_VPMD_RX_BURST
475 i40e_recv_scattered_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
479 struct i40e_rx_queue *rxq = rx_queue;
480 uint8_t split_flags[RTE_I40E_VPMD_RX_BURST] = {0};
482 /* get some new buffers */
483 uint16_t nb_bufs = _recv_raw_pkts_vec(rxq, rx_pkts, nb_pkts,
488 /* happy day case, full burst + no packets to be joined */
489 const uint64_t *split_fl64 = (uint64_t *)split_flags;
491 if (rxq->pkt_first_seg == NULL &&
492 split_fl64[0] == 0 && split_fl64[1] == 0 &&
493 split_fl64[2] == 0 && split_fl64[3] == 0)
496 /* reassemble any packets that need reassembly*/
499 if (rxq->pkt_first_seg == NULL) {
500 /* find the first split flag, and only reassemble then*/
501 while (i < nb_bufs && !split_flags[i])
506 return i + reassemble_packets(rxq, &rx_pkts[i], nb_bufs - i,
511 vtx1(volatile struct i40e_tx_desc *txdp,
512 struct rte_mbuf *pkt, uint64_t flags)
514 uint64_t high_qw = (I40E_TX_DESC_DTYPE_DATA |
515 ((uint64_t)flags << I40E_TXD_QW1_CMD_SHIFT) |
516 ((uint64_t)pkt->data_len << I40E_TXD_QW1_TX_BUF_SZ_SHIFT));
518 uint64x2_t descriptor = {pkt->buf_physaddr + pkt->data_off, high_qw};
519 vst1q_u64((uint64_t *)txdp, descriptor);
523 vtx(volatile struct i40e_tx_desc *txdp,
524 struct rte_mbuf **pkt, uint16_t nb_pkts, uint64_t flags)
528 for (i = 0; i < nb_pkts; ++i, ++txdp, ++pkt)
529 vtx1(txdp, *pkt, flags);
533 i40e_xmit_fixed_burst_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
536 struct i40e_tx_queue *txq = (struct i40e_tx_queue *)tx_queue;
537 volatile struct i40e_tx_desc *txdp;
538 struct i40e_tx_entry *txep;
539 uint16_t n, nb_commit, tx_id;
540 uint64_t flags = I40E_TD_CMD;
541 uint64_t rs = I40E_TX_DESC_CMD_RS | I40E_TD_CMD;
544 /* cross rx_thresh boundary is not allowed */
545 nb_pkts = RTE_MIN(nb_pkts, txq->tx_rs_thresh);
547 if (txq->nb_tx_free < txq->tx_free_thresh)
548 i40e_tx_free_bufs(txq);
550 nb_commit = nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
551 if (unlikely(nb_pkts == 0))
554 tx_id = txq->tx_tail;
555 txdp = &txq->tx_ring[tx_id];
556 txep = &txq->sw_ring[tx_id];
558 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
560 n = (uint16_t)(txq->nb_tx_desc - tx_id);
561 if (nb_commit >= n) {
562 tx_backlog_entry(txep, tx_pkts, n);
564 for (i = 0; i < n - 1; ++i, ++tx_pkts, ++txdp)
565 vtx1(txdp, *tx_pkts, flags);
567 vtx1(txdp, *tx_pkts++, rs);
569 nb_commit = (uint16_t)(nb_commit - n);
572 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
574 /* avoid reach the end of ring */
575 txdp = &txq->tx_ring[tx_id];
576 txep = &txq->sw_ring[tx_id];
579 tx_backlog_entry(txep, tx_pkts, nb_commit);
581 vtx(txdp, tx_pkts, nb_commit, flags);
583 tx_id = (uint16_t)(tx_id + nb_commit);
584 if (tx_id > txq->tx_next_rs) {
585 txq->tx_ring[txq->tx_next_rs].cmd_type_offset_bsz |=
586 rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
587 I40E_TXD_QW1_CMD_SHIFT);
589 (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
592 txq->tx_tail = tx_id;
594 I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
599 void __attribute__((cold))
600 i40e_rx_queue_release_mbufs_vec(struct i40e_rx_queue *rxq)
602 _i40e_rx_queue_release_mbufs_vec(rxq);
605 int __attribute__((cold))
606 i40e_rxq_vec_setup(struct i40e_rx_queue *rxq)
608 return i40e_rxq_vec_setup_default(rxq);
611 int __attribute__((cold))
612 i40e_txq_vec_setup(struct i40e_tx_queue __rte_unused *txq)
617 int __attribute__((cold))
618 i40e_rx_vec_dev_conf_condition_check(struct rte_eth_dev *dev)
620 return i40e_rx_vec_dev_conf_condition_check_default(dev);