4 * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
5 * Copyright(c) 2016, Linaro Limited
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15 * notice, this list of conditions and the following disclaimer in
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32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 #include <rte_ethdev.h>
37 #include <rte_malloc.h>
39 #include "base/i40e_prototype.h"
40 #include "base/i40e_type.h"
41 #include "i40e_ethdev.h"
42 #include "i40e_rxtx.h"
43 #include "i40e_rxtx_vec_common.h"
47 #pragma GCC diagnostic ignored "-Wcast-qual"
50 i40e_rxq_rearm(struct i40e_rx_queue *rxq)
54 volatile union i40e_rx_desc *rxdp;
55 struct i40e_rx_entry *rxep = &rxq->sw_ring[rxq->rxrearm_start];
56 struct rte_mbuf *mb0, *mb1;
57 uint64x2_t dma_addr0, dma_addr1;
58 uint64x2_t zero = vdupq_n_u64(0);
62 rxdp = rxq->rx_ring + rxq->rxrearm_start;
64 /* Pull 'n' more MBUFs into the software ring */
65 if (unlikely(rte_mempool_get_bulk(rxq->mp,
67 RTE_I40E_RXQ_REARM_THRESH) < 0)) {
68 if (rxq->rxrearm_nb + RTE_I40E_RXQ_REARM_THRESH >=
70 for (i = 0; i < RTE_I40E_DESCS_PER_LOOP; i++) {
71 rxep[i].mbuf = &rxq->fake_mbuf;
72 vst1q_u64((uint64_t *)&rxdp[i].read, zero);
75 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
76 RTE_I40E_RXQ_REARM_THRESH;
80 p = vld1_u8((uint8_t *)&rxq->mbuf_initializer);
82 /* Initialize the mbufs in vector, process 2 mbufs in one loop */
83 for (i = 0; i < RTE_I40E_RXQ_REARM_THRESH; i += 2, rxep += 2) {
87 /* Flush mbuf with pkt template.
88 * Data to be rearmed is 6 bytes long.
89 * Though, RX will overwrite ol_flags that are coming next
90 * anyway. So overwrite whole 8 bytes with one load:
91 * 6 bytes of rearm_data plus first 2 bytes of ol_flags.
93 vst1_u8((uint8_t *)&mb0->rearm_data, p);
94 paddr = mb0->buf_physaddr + RTE_PKTMBUF_HEADROOM;
95 dma_addr0 = vdupq_n_u64(paddr);
97 /* flush desc with pa dma_addr */
98 vst1q_u64((uint64_t *)&rxdp++->read, dma_addr0);
100 vst1_u8((uint8_t *)&mb1->rearm_data, p);
101 paddr = mb1->buf_physaddr + RTE_PKTMBUF_HEADROOM;
102 dma_addr1 = vdupq_n_u64(paddr);
103 vst1q_u64((uint64_t *)&rxdp++->read, dma_addr1);
106 rxq->rxrearm_start += RTE_I40E_RXQ_REARM_THRESH;
107 if (rxq->rxrearm_start >= rxq->nb_rx_desc)
108 rxq->rxrearm_start = 0;
110 rxq->rxrearm_nb -= RTE_I40E_RXQ_REARM_THRESH;
112 rx_id = (uint16_t)((rxq->rxrearm_start == 0) ?
113 (rxq->nb_rx_desc - 1) : (rxq->rxrearm_start - 1));
115 /* Update the tail pointer on the NIC */
116 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
120 desc_to_olflags_v(uint64x2_t descs[4], struct rte_mbuf **rx_pkts)
122 uint32x4_t vlan0, vlan1, rss, l3_l4e;
124 /* mask everything except RSS, flow director and VLAN flags
125 * bit2 is for VLAN tag, bit11 for flow director indication
126 * bit13:12 for RSS indication.
128 const uint32x4_t rss_vlan_msk = {
129 0x1c03804, 0x1c03804, 0x1c03804, 0x1c03804};
131 /* map rss and vlan type to rss hash and vlan flag */
132 const uint8x16_t vlan_flags = {
134 PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED, 0, 0, 0,
138 const uint8x16_t rss_flags = {
139 0, PKT_RX_FDIR, 0, 0,
140 0, 0, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH | PKT_RX_FDIR,
144 const uint8x16_t l3_l4e_flags = {
148 PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD,
149 PKT_RX_EIP_CKSUM_BAD,
150 PKT_RX_EIP_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD,
151 PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD,
152 PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD,
153 0, 0, 0, 0, 0, 0, 0, 0};
155 vlan0 = vzipq_u32(vreinterpretq_u32_u64(descs[0]),
156 vreinterpretq_u32_u64(descs[2])).val[1];
157 vlan1 = vzipq_u32(vreinterpretq_u32_u64(descs[1]),
158 vreinterpretq_u32_u64(descs[3])).val[1];
159 vlan0 = vzipq_u32(vlan0, vlan1).val[0];
161 vlan1 = vandq_u32(vlan0, rss_vlan_msk);
162 vlan0 = vreinterpretq_u32_u8(vqtbl1q_u8(vlan_flags,
163 vreinterpretq_u8_u32(vlan1)));
165 rss = vshrq_n_u32(vlan1, 11);
166 rss = vreinterpretq_u32_u8(vqtbl1q_u8(rss_flags,
167 vreinterpretq_u8_u32(rss)));
169 l3_l4e = vshrq_n_u32(vlan1, 22);
170 l3_l4e = vreinterpretq_u32_u8(vqtbl1q_u8(l3_l4e_flags,
171 vreinterpretq_u8_u32(l3_l4e)));
174 vlan0 = vorrq_u32(vlan0, rss);
175 vlan0 = vorrq_u32(vlan0, l3_l4e);
177 rx_pkts[0]->ol_flags = vgetq_lane_u32(vlan0, 0);
178 rx_pkts[1]->ol_flags = vgetq_lane_u32(vlan0, 1);
179 rx_pkts[2]->ol_flags = vgetq_lane_u32(vlan0, 2);
180 rx_pkts[3]->ol_flags = vgetq_lane_u32(vlan0, 3);
183 #define PKTLEN_SHIFT 10
185 #define I40E_VPMD_DESC_DD_MASK 0x0001000100010001ULL
188 desc_to_ptype_v(uint64x2_t descs[4], struct rte_mbuf **rx_pkts)
194 for (i = 0; i < 4; i++) {
195 tmp = vreinterpretq_u8_u64(vshrq_n_u64(descs[i], 30));
196 ptype = vgetq_lane_u8(tmp, 8);
197 rx_pkts[i]->packet_type = i40e_rxd_pkt_type_mapping(ptype);
204 * - nb_pkts < RTE_I40E_DESCS_PER_LOOP, just return no packet
205 * - nb_pkts > RTE_I40E_VPMD_RX_BURST, only scan RTE_I40E_VPMD_RX_BURST
208 static inline uint16_t
209 _recv_raw_pkts_vec(struct i40e_rx_queue *rxq, struct rte_mbuf **rx_pkts,
210 uint16_t nb_pkts, uint8_t *split_packet)
212 volatile union i40e_rx_desc *rxdp;
213 struct i40e_rx_entry *sw_ring;
214 uint16_t nb_pkts_recd;
218 /* mask to shuffle from desc. to mbuf */
219 uint8x16_t shuf_msk = {
220 0xFF, 0xFF, /* pkt_type set as unknown */
221 0xFF, 0xFF, /* pkt_type set as unknown */
222 14, 15, /* octet 15~14, low 16 bits pkt_len */
223 0xFF, 0xFF, /* skip high 16 bits pkt_len, zero out */
224 14, 15, /* octet 15~14, 16 bits data_len */
225 2, 3, /* octet 2~3, low 16 bits vlan_macip */
226 4, 5, 6, 7 /* octet 4~7, 32bits rss */
229 uint8x16_t eop_check = {
230 0x02, 0x00, 0x02, 0x00,
231 0x02, 0x00, 0x02, 0x00,
232 0x00, 0x00, 0x00, 0x00,
233 0x00, 0x00, 0x00, 0x00
236 uint16x8_t crc_adjust = {
237 0, 0, /* ignore pkt_type field */
238 rxq->crc_len, /* sub crc on pkt_len */
239 0, /* ignore high-16bits of pkt_len */
240 rxq->crc_len, /* sub crc on data_len */
241 0, 0, 0 /* ignore non-length fields */
244 /* nb_pkts shall be less equal than RTE_I40E_MAX_RX_BURST */
245 nb_pkts = RTE_MIN(nb_pkts, RTE_I40E_MAX_RX_BURST);
247 /* nb_pkts has to be floor-aligned to RTE_I40E_DESCS_PER_LOOP */
248 nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, RTE_I40E_DESCS_PER_LOOP);
250 /* Just the act of getting into the function from the application is
251 * going to cost about 7 cycles
253 rxdp = rxq->rx_ring + rxq->rx_tail;
255 rte_prefetch_non_temporal(rxdp);
257 /* See if we need to rearm the RX queue - gives the prefetch a bit
260 if (rxq->rxrearm_nb > RTE_I40E_RXQ_REARM_THRESH)
263 /* Before we start moving massive data around, check to see if
264 * there is actually a packet available
266 if (!(rxdp->wb.qword1.status_error_len &
267 rte_cpu_to_le_32(1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
270 /* Cache is empty -> need to scan the buffer rings, but first move
271 * the next 'n' mbufs into the cache
273 sw_ring = &rxq->sw_ring[rxq->rx_tail];
275 /* A. load 4 packet in one loop
276 * [A*. mask out 4 unused dirty field in desc]
277 * B. copy 4 mbuf point from swring to rx_pkts
278 * C. calc the number of DD bits among the 4 packets
279 * [C*. extract the end-of-packet bit, if requested]
280 * D. fill info. from desc to mbuf
283 for (pos = 0, nb_pkts_recd = 0; pos < nb_pkts;
284 pos += RTE_I40E_DESCS_PER_LOOP,
285 rxdp += RTE_I40E_DESCS_PER_LOOP) {
286 uint64x2_t descs[RTE_I40E_DESCS_PER_LOOP];
287 uint8x16_t pkt_mb1, pkt_mb2, pkt_mb3, pkt_mb4;
288 uint16x8x2_t sterr_tmp1, sterr_tmp2;
289 uint64x2_t mbp1, mbp2;
294 int32x4_t len_shl = {0, 0, 0, PKTLEN_SHIFT};
296 /* B.1 load 1 mbuf point */
297 mbp1 = vld1q_u64((uint64_t *)&sw_ring[pos]);
298 /* Read desc statuses backwards to avoid race condition */
299 /* A.1 load 4 pkts desc */
300 descs[3] = vld1q_u64((uint64_t *)(rxdp + 3));
303 /* B.2 copy 2 mbuf point into rx_pkts */
304 vst1q_u64((uint64_t *)&rx_pkts[pos], mbp1);
306 /* B.1 load 1 mbuf point */
307 mbp2 = vld1q_u64((uint64_t *)&sw_ring[pos + 2]);
309 descs[2] = vld1q_u64((uint64_t *)(rxdp + 2));
310 /* B.1 load 2 mbuf point */
311 descs[1] = vld1q_u64((uint64_t *)(rxdp + 1));
312 descs[0] = vld1q_u64((uint64_t *)(rxdp));
314 /* B.2 copy 2 mbuf point into rx_pkts */
315 vst1q_u64((uint64_t *)&rx_pkts[pos + 2], mbp2);
318 rte_mbuf_prefetch_part2(rx_pkts[pos]);
319 rte_mbuf_prefetch_part2(rx_pkts[pos + 1]);
320 rte_mbuf_prefetch_part2(rx_pkts[pos + 2]);
321 rte_mbuf_prefetch_part2(rx_pkts[pos + 3]);
324 /* avoid compiler reorder optimization */
325 rte_compiler_barrier();
327 /* pkt 3,4 shift the pktlen field to be 16-bit aligned*/
328 uint32x4_t len3 = vshlq_u32(vreinterpretq_u32_u64(descs[3]),
330 descs[3] = vreinterpretq_u64_u32(len3);
331 uint32x4_t len2 = vshlq_u32(vreinterpretq_u32_u64(descs[2]),
333 descs[2] = vreinterpretq_u64_u32(len2);
335 /* D.1 pkt 3,4 convert format from desc to pktmbuf */
336 pkt_mb4 = vqtbl1q_u8(vreinterpretq_u8_u64(descs[3]), shuf_msk);
337 pkt_mb3 = vqtbl1q_u8(vreinterpretq_u8_u64(descs[2]), shuf_msk);
339 /* C.1 4=>2 filter staterr info only */
340 sterr_tmp2 = vzipq_u16(vreinterpretq_u16_u64(descs[1]),
341 vreinterpretq_u16_u64(descs[3]));
342 /* C.1 4=>2 filter staterr info only */
343 sterr_tmp1 = vzipq_u16(vreinterpretq_u16_u64(descs[0]),
344 vreinterpretq_u16_u64(descs[2]));
346 /* C.2 get 4 pkts staterr value */
347 staterr = vzipq_u16(sterr_tmp1.val[1],
348 sterr_tmp2.val[1]).val[0];
349 stat = vgetq_lane_u64(vreinterpretq_u64_u16(staterr), 0);
351 desc_to_olflags_v(descs, &rx_pkts[pos]);
353 /* D.2 pkt 3,4 set in_port/nb_seg and remove crc */
354 tmp = vsubq_u16(vreinterpretq_u16_u8(pkt_mb4), crc_adjust);
355 pkt_mb4 = vreinterpretq_u8_u16(tmp);
356 tmp = vsubq_u16(vreinterpretq_u16_u8(pkt_mb3), crc_adjust);
357 pkt_mb3 = vreinterpretq_u8_u16(tmp);
359 /* pkt 1,2 shift the pktlen field to be 16-bit aligned*/
360 uint32x4_t len1 = vshlq_u32(vreinterpretq_u32_u64(descs[1]),
362 descs[1] = vreinterpretq_u64_u32(len1);
363 uint32x4_t len0 = vshlq_u32(vreinterpretq_u32_u64(descs[0]),
365 descs[0] = vreinterpretq_u64_u32(len0);
367 /* D.1 pkt 1,2 convert format from desc to pktmbuf */
368 pkt_mb2 = vqtbl1q_u8(vreinterpretq_u8_u64(descs[1]), shuf_msk);
369 pkt_mb1 = vqtbl1q_u8(vreinterpretq_u8_u64(descs[0]), shuf_msk);
371 /* D.3 copy final 3,4 data to rx_pkts */
372 vst1q_u8((void *)&rx_pkts[pos + 3]->rx_descriptor_fields1,
374 vst1q_u8((void *)&rx_pkts[pos + 2]->rx_descriptor_fields1,
377 /* D.2 pkt 1,2 set in_port/nb_seg and remove crc */
378 tmp = vsubq_u16(vreinterpretq_u16_u8(pkt_mb2), crc_adjust);
379 pkt_mb2 = vreinterpretq_u8_u16(tmp);
380 tmp = vsubq_u16(vreinterpretq_u16_u8(pkt_mb1), crc_adjust);
381 pkt_mb1 = vreinterpretq_u8_u16(tmp);
383 /* C* extract and record EOP bit */
385 uint8x16_t eop_shuf_mask = {
386 0x00, 0x02, 0x04, 0x06,
387 0xFF, 0xFF, 0xFF, 0xFF,
388 0xFF, 0xFF, 0xFF, 0xFF,
389 0xFF, 0xFF, 0xFF, 0xFF};
392 /* and with mask to extract bits, flipping 1-0 */
393 eop_bits = vmvnq_u8(vreinterpretq_u8_u16(staterr));
394 eop_bits = vandq_u8(eop_bits, eop_check);
395 /* the staterr values are not in order, as the count
396 * count of dd bits doesn't care. However, for end of
397 * packet tracking, we do care, so shuffle. This also
398 * compresses the 32-bit values to 8-bit
400 eop_bits = vqtbl1q_u8(eop_bits, eop_shuf_mask);
402 /* store the resulting 32-bit value */
403 vst1q_lane_u32((uint32_t *)split_packet,
404 vreinterpretq_u32_u8(eop_bits), 0);
405 split_packet += RTE_I40E_DESCS_PER_LOOP;
407 /* zero-out next pointers */
408 rx_pkts[pos]->next = NULL;
409 rx_pkts[pos + 1]->next = NULL;
410 rx_pkts[pos + 2]->next = NULL;
411 rx_pkts[pos + 3]->next = NULL;
414 rte_prefetch_non_temporal(rxdp + RTE_I40E_DESCS_PER_LOOP);
416 /* D.3 copy final 1,2 data to rx_pkts */
417 vst1q_u8((void *)&rx_pkts[pos + 1]->rx_descriptor_fields1,
419 vst1q_u8((void *)&rx_pkts[pos]->rx_descriptor_fields1,
421 desc_to_ptype_v(descs, &rx_pkts[pos]);
422 /* C.4 calc avaialbe number of desc */
423 var = __builtin_popcountll(stat & I40E_VPMD_DESC_DD_MASK);
425 if (likely(var != RTE_I40E_DESCS_PER_LOOP))
429 /* Update our internal tail pointer */
430 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_pkts_recd);
431 rxq->rx_tail = (uint16_t)(rxq->rx_tail & (rxq->nb_rx_desc - 1));
432 rxq->rxrearm_nb = (uint16_t)(rxq->rxrearm_nb + nb_pkts_recd);
439 * - nb_pkts < RTE_I40E_DESCS_PER_LOOP, just return no packet
440 * - nb_pkts > RTE_I40E_VPMD_RX_BURST, only scan RTE_I40E_VPMD_RX_BURST
444 i40e_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
447 return _recv_raw_pkts_vec(rx_queue, rx_pkts, nb_pkts, NULL);
450 /* vPMD receive routine that reassembles scattered packets
452 * - nb_pkts < RTE_I40E_DESCS_PER_LOOP, just return no packet
453 * - nb_pkts > RTE_I40E_VPMD_RX_BURST, only scan RTE_I40E_VPMD_RX_BURST
457 i40e_recv_scattered_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
461 struct i40e_rx_queue *rxq = rx_queue;
462 uint8_t split_flags[RTE_I40E_VPMD_RX_BURST] = {0};
464 /* get some new buffers */
465 uint16_t nb_bufs = _recv_raw_pkts_vec(rxq, rx_pkts, nb_pkts,
470 /* happy day case, full burst + no packets to be joined */
471 const uint64_t *split_fl64 = (uint64_t *)split_flags;
473 if (rxq->pkt_first_seg == NULL &&
474 split_fl64[0] == 0 && split_fl64[1] == 0 &&
475 split_fl64[2] == 0 && split_fl64[3] == 0)
478 /* reassemble any packets that need reassembly*/
481 if (rxq->pkt_first_seg == NULL) {
482 /* find the first split flag, and only reassemble then*/
483 while (i < nb_bufs && !split_flags[i])
488 return i + reassemble_packets(rxq, &rx_pkts[i], nb_bufs - i,
493 vtx1(volatile struct i40e_tx_desc *txdp,
494 struct rte_mbuf *pkt, uint64_t flags)
496 uint64_t high_qw = (I40E_TX_DESC_DTYPE_DATA |
497 ((uint64_t)flags << I40E_TXD_QW1_CMD_SHIFT) |
498 ((uint64_t)pkt->data_len << I40E_TXD_QW1_TX_BUF_SZ_SHIFT));
500 uint64x2_t descriptor = {pkt->buf_physaddr + pkt->data_off, high_qw};
501 vst1q_u64((uint64_t *)txdp, descriptor);
505 vtx(volatile struct i40e_tx_desc *txdp,
506 struct rte_mbuf **pkt, uint16_t nb_pkts, uint64_t flags)
510 for (i = 0; i < nb_pkts; ++i, ++txdp, ++pkt)
511 vtx1(txdp, *pkt, flags);
515 i40e_xmit_fixed_burst_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
518 struct i40e_tx_queue *txq = (struct i40e_tx_queue *)tx_queue;
519 volatile struct i40e_tx_desc *txdp;
520 struct i40e_tx_entry *txep;
521 uint16_t n, nb_commit, tx_id;
522 uint64_t flags = I40E_TD_CMD;
523 uint64_t rs = I40E_TX_DESC_CMD_RS | I40E_TD_CMD;
526 /* cross rx_thresh boundary is not allowed */
527 nb_pkts = RTE_MIN(nb_pkts, txq->tx_rs_thresh);
529 if (txq->nb_tx_free < txq->tx_free_thresh)
530 i40e_tx_free_bufs(txq);
532 nb_commit = nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
533 if (unlikely(nb_pkts == 0))
536 tx_id = txq->tx_tail;
537 txdp = &txq->tx_ring[tx_id];
538 txep = &txq->sw_ring[tx_id];
540 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
542 n = (uint16_t)(txq->nb_tx_desc - tx_id);
543 if (nb_commit >= n) {
544 tx_backlog_entry(txep, tx_pkts, n);
546 for (i = 0; i < n - 1; ++i, ++tx_pkts, ++txdp)
547 vtx1(txdp, *tx_pkts, flags);
549 vtx1(txdp, *tx_pkts++, rs);
551 nb_commit = (uint16_t)(nb_commit - n);
554 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
556 /* avoid reach the end of ring */
557 txdp = &txq->tx_ring[tx_id];
558 txep = &txq->sw_ring[tx_id];
561 tx_backlog_entry(txep, tx_pkts, nb_commit);
563 vtx(txdp, tx_pkts, nb_commit, flags);
565 tx_id = (uint16_t)(tx_id + nb_commit);
566 if (tx_id > txq->tx_next_rs) {
567 txq->tx_ring[txq->tx_next_rs].cmd_type_offset_bsz |=
568 rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
569 I40E_TXD_QW1_CMD_SHIFT);
571 (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
574 txq->tx_tail = tx_id;
576 I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
581 void __attribute__((cold))
582 i40e_rx_queue_release_mbufs_vec(struct i40e_rx_queue *rxq)
584 _i40e_rx_queue_release_mbufs_vec(rxq);
587 int __attribute__((cold))
588 i40e_rxq_vec_setup(struct i40e_rx_queue *rxq)
590 return i40e_rxq_vec_setup_default(rxq);
593 int __attribute__((cold))
594 i40e_txq_vec_setup(struct i40e_tx_queue __rte_unused *txq)
599 int __attribute__((cold))
600 i40e_rx_vec_dev_conf_condition_check(struct rte_eth_dev *dev)
602 return i40e_rx_vec_dev_conf_condition_check_default(dev);