4 * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
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35 #include <rte_ethdev.h>
36 #include <rte_malloc.h>
38 #include "base/i40e_prototype.h"
39 #include "base/i40e_type.h"
40 #include "i40e_ethdev.h"
41 #include "i40e_rxtx.h"
42 #include "i40e_rxtx_vec_common.h"
44 #include <tmmintrin.h>
46 #ifndef __INTEL_COMPILER
47 #pragma GCC diagnostic ignored "-Wcast-qual"
51 i40e_rxq_rearm(struct i40e_rx_queue *rxq)
55 volatile union i40e_rx_desc *rxdp;
56 struct i40e_rx_entry *rxep = &rxq->sw_ring[rxq->rxrearm_start];
57 struct rte_mbuf *mb0, *mb1;
58 __m128i hdr_room = _mm_set_epi64x(RTE_PKTMBUF_HEADROOM,
59 RTE_PKTMBUF_HEADROOM);
60 __m128i dma_addr0, dma_addr1;
62 rxdp = rxq->rx_ring + rxq->rxrearm_start;
64 /* Pull 'n' more MBUFs into the software ring */
65 if (rte_mempool_get_bulk(rxq->mp,
67 RTE_I40E_RXQ_REARM_THRESH) < 0) {
68 if (rxq->rxrearm_nb + RTE_I40E_RXQ_REARM_THRESH >=
70 dma_addr0 = _mm_setzero_si128();
71 for (i = 0; i < RTE_I40E_DESCS_PER_LOOP; i++) {
72 rxep[i].mbuf = &rxq->fake_mbuf;
73 _mm_store_si128((__m128i *)&rxdp[i].read,
77 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
78 RTE_I40E_RXQ_REARM_THRESH;
82 /* Initialize the mbufs in vector, process 2 mbufs in one loop */
83 for (i = 0; i < RTE_I40E_RXQ_REARM_THRESH; i += 2, rxep += 2) {
84 __m128i vaddr0, vaddr1;
89 /* load buf_addr(lo 64bit) and buf_physaddr(hi 64bit) */
90 vaddr0 = _mm_loadu_si128((__m128i *)&mb0->buf_addr);
91 vaddr1 = _mm_loadu_si128((__m128i *)&mb1->buf_addr);
93 /* convert pa to dma_addr hdr/data */
94 dma_addr0 = _mm_unpackhi_epi64(vaddr0, vaddr0);
95 dma_addr1 = _mm_unpackhi_epi64(vaddr1, vaddr1);
97 /* add headroom to pa values */
98 dma_addr0 = _mm_add_epi64(dma_addr0, hdr_room);
99 dma_addr1 = _mm_add_epi64(dma_addr1, hdr_room);
101 /* flush desc with pa dma_addr */
102 _mm_store_si128((__m128i *)&rxdp++->read, dma_addr0);
103 _mm_store_si128((__m128i *)&rxdp++->read, dma_addr1);
106 rxq->rxrearm_start += RTE_I40E_RXQ_REARM_THRESH;
107 if (rxq->rxrearm_start >= rxq->nb_rx_desc)
108 rxq->rxrearm_start = 0;
110 rxq->rxrearm_nb -= RTE_I40E_RXQ_REARM_THRESH;
112 rx_id = (uint16_t)((rxq->rxrearm_start == 0) ?
113 (rxq->nb_rx_desc - 1) : (rxq->rxrearm_start - 1));
115 /* Update the tail pointer on the NIC */
116 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
120 desc_to_olflags_v(struct i40e_rx_queue *rxq, __m128i descs[4] __rte_unused,
121 struct rte_mbuf **rx_pkts)
123 const __m128i mbuf_init = _mm_set_epi64x(0, rxq->mbuf_initializer);
124 __m128i rearm0, rearm1, rearm2, rearm3;
126 /* Handling the offload flags (olflags) field takes computation
127 * time when receiving packets. Therefore we provide a flag to disable
128 * the processing of the olflags field when they are not needed. This
129 * gives improved performance, at the cost of losing the offload info
130 * in the received packet
132 #ifdef RTE_LIBRTE_I40E_RX_OLFLAGS_ENABLE
134 __m128i vlan0, vlan1, rss, l3_l4e;
136 /* mask everything except RSS, flow director and VLAN flags
137 * bit2 is for VLAN tag, bit11 for flow director indication
138 * bit13:12 for RSS indication.
140 const __m128i rss_vlan_msk = _mm_set_epi32(
141 0x1c03804, 0x1c03804, 0x1c03804, 0x1c03804);
143 const __m128i cksum_mask = _mm_set_epi32(
144 PKT_RX_IP_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD |
145 PKT_RX_L4_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD |
146 PKT_RX_EIP_CKSUM_BAD,
147 PKT_RX_IP_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD |
148 PKT_RX_L4_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD |
149 PKT_RX_EIP_CKSUM_BAD,
150 PKT_RX_IP_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD |
151 PKT_RX_L4_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD |
152 PKT_RX_EIP_CKSUM_BAD,
153 PKT_RX_IP_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD |
154 PKT_RX_L4_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD |
155 PKT_RX_EIP_CKSUM_BAD);
157 /* map rss and vlan type to rss hash and vlan flag */
158 const __m128i vlan_flags = _mm_set_epi8(0, 0, 0, 0,
160 0, 0, 0, PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED,
163 const __m128i rss_flags = _mm_set_epi8(0, 0, 0, 0,
165 PKT_RX_RSS_HASH | PKT_RX_FDIR, PKT_RX_RSS_HASH, 0, 0,
166 0, 0, PKT_RX_FDIR, 0);
168 const __m128i l3_l4e_flags = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0,
169 /* shift right 1 bit to make sure it not exceed 255 */
170 (PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD |
171 PKT_RX_IP_CKSUM_BAD) >> 1,
172 (PKT_RX_IP_CKSUM_GOOD | PKT_RX_EIP_CKSUM_BAD |
173 PKT_RX_L4_CKSUM_BAD) >> 1,
174 (PKT_RX_EIP_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,
175 (PKT_RX_IP_CKSUM_GOOD | PKT_RX_EIP_CKSUM_BAD) >> 1,
176 (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,
177 (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD) >> 1,
178 PKT_RX_IP_CKSUM_BAD >> 1,
179 (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD) >> 1);
181 vlan0 = _mm_unpackhi_epi32(descs[0], descs[1]);
182 vlan1 = _mm_unpackhi_epi32(descs[2], descs[3]);
183 vlan0 = _mm_unpacklo_epi64(vlan0, vlan1);
185 vlan1 = _mm_and_si128(vlan0, rss_vlan_msk);
186 vlan0 = _mm_shuffle_epi8(vlan_flags, vlan1);
188 rss = _mm_srli_epi32(vlan1, 11);
189 rss = _mm_shuffle_epi8(rss_flags, rss);
191 l3_l4e = _mm_srli_epi32(vlan1, 22);
192 l3_l4e = _mm_shuffle_epi8(l3_l4e_flags, l3_l4e);
193 /* then we shift left 1 bit */
194 l3_l4e = _mm_slli_epi32(l3_l4e, 1);
195 /* we need to mask out the reduntant bits */
196 l3_l4e = _mm_and_si128(l3_l4e, cksum_mask);
198 vlan0 = _mm_or_si128(vlan0, rss);
199 vlan0 = _mm_or_si128(vlan0, l3_l4e);
202 * At this point, we have the 4 sets of flags in the low 16-bits
203 * of each 32-bit value in vlan0.
204 * We want to extract these, and merge them with the mbuf init data
205 * so we can do a single 16-byte write to the mbuf to set the flags
206 * and all the other initialization fields. Extracting the
207 * appropriate flags means that we have to do a shift and blend for
208 * each mbuf before we do the write.
210 rearm0 = _mm_blend_epi16(mbuf_init, _mm_slli_si128(vlan0, 8), 0x10);
211 rearm1 = _mm_blend_epi16(mbuf_init, _mm_slli_si128(vlan0, 4), 0x10);
212 rearm2 = _mm_blend_epi16(mbuf_init, vlan0, 0x10);
213 rearm3 = _mm_blend_epi16(mbuf_init, _mm_srli_si128(vlan0, 4), 0x10);
215 rearm0 = rearm1 = rearm2 = rearm3 = mbuf_init;
217 _mm_store_si128((__m128i *)&rx_pkts[0]->rearm_data, rearm0);
218 _mm_store_si128((__m128i *)&rx_pkts[1]->rearm_data, rearm1);
219 _mm_store_si128((__m128i *)&rx_pkts[2]->rearm_data, rearm2);
220 _mm_store_si128((__m128i *)&rx_pkts[3]->rearm_data, rearm3);
223 #define PKTLEN_SHIFT 10
226 desc_to_ptype_v(__m128i descs[4], struct rte_mbuf **rx_pkts)
228 __m128i ptype0 = _mm_unpackhi_epi64(descs[0], descs[1]);
229 __m128i ptype1 = _mm_unpackhi_epi64(descs[2], descs[3]);
231 ptype0 = _mm_srli_epi64(ptype0, 30);
232 ptype1 = _mm_srli_epi64(ptype1, 30);
234 rx_pkts[0]->packet_type = i40e_rxd_pkt_type_mapping(_mm_extract_epi8(ptype0, 0));
235 rx_pkts[1]->packet_type = i40e_rxd_pkt_type_mapping(_mm_extract_epi8(ptype0, 8));
236 rx_pkts[2]->packet_type = i40e_rxd_pkt_type_mapping(_mm_extract_epi8(ptype1, 0));
237 rx_pkts[3]->packet_type = i40e_rxd_pkt_type_mapping(_mm_extract_epi8(ptype1, 8));
242 * - nb_pkts < RTE_I40E_DESCS_PER_LOOP, just return no packet
243 * - nb_pkts > RTE_I40E_VPMD_RX_BURST, only scan RTE_I40E_VPMD_RX_BURST
246 static inline uint16_t
247 _recv_raw_pkts_vec(struct i40e_rx_queue *rxq, struct rte_mbuf **rx_pkts,
248 uint16_t nb_pkts, uint8_t *split_packet)
250 volatile union i40e_rx_desc *rxdp;
251 struct i40e_rx_entry *sw_ring;
252 uint16_t nb_pkts_recd;
257 __m128i crc_adjust = _mm_set_epi16(
258 0, 0, 0, /* ignore non-length fields */
259 -rxq->crc_len, /* sub crc on data_len */
260 0, /* ignore high-16bits of pkt_len */
261 -rxq->crc_len, /* sub crc on pkt_len */
262 0, 0 /* ignore pkt_type field */
264 __m128i dd_check, eop_check;
266 /* nb_pkts shall be less equal than RTE_I40E_MAX_RX_BURST */
267 nb_pkts = RTE_MIN(nb_pkts, RTE_I40E_MAX_RX_BURST);
269 /* nb_pkts has to be floor-aligned to RTE_I40E_DESCS_PER_LOOP */
270 nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, RTE_I40E_DESCS_PER_LOOP);
272 /* Just the act of getting into the function from the application is
273 * going to cost about 7 cycles
275 rxdp = rxq->rx_ring + rxq->rx_tail;
279 /* See if we need to rearm the RX queue - gives the prefetch a bit
282 if (rxq->rxrearm_nb > RTE_I40E_RXQ_REARM_THRESH)
285 /* Before we start moving massive data around, check to see if
286 * there is actually a packet available
288 if (!(rxdp->wb.qword1.status_error_len &
289 rte_cpu_to_le_32(1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
292 /* 4 packets DD mask */
293 dd_check = _mm_set_epi64x(0x0000000100000001LL, 0x0000000100000001LL);
295 /* 4 packets EOP mask */
296 eop_check = _mm_set_epi64x(0x0000000200000002LL, 0x0000000200000002LL);
298 /* mask to shuffle from desc. to mbuf */
299 shuf_msk = _mm_set_epi8(
300 7, 6, 5, 4, /* octet 4~7, 32bits rss */
301 3, 2, /* octet 2~3, low 16 bits vlan_macip */
302 15, 14, /* octet 15~14, 16 bits data_len */
303 0xFF, 0xFF, /* skip high 16 bits pkt_len, zero out */
304 15, 14, /* octet 15~14, low 16 bits pkt_len */
305 0xFF, 0xFF, /* pkt_type set as unknown */
306 0xFF, 0xFF /*pkt_type set as unknown */
309 /* Cache is empty -> need to scan the buffer rings, but first move
310 * the next 'n' mbufs into the cache
312 sw_ring = &rxq->sw_ring[rxq->rx_tail];
314 /* A. load 4 packet in one loop
315 * [A*. mask out 4 unused dirty field in desc]
316 * B. copy 4 mbuf point from swring to rx_pkts
317 * C. calc the number of DD bits among the 4 packets
318 * [C*. extract the end-of-packet bit, if requested]
319 * D. fill info. from desc to mbuf
322 for (pos = 0, nb_pkts_recd = 0; pos < nb_pkts;
323 pos += RTE_I40E_DESCS_PER_LOOP,
324 rxdp += RTE_I40E_DESCS_PER_LOOP) {
325 __m128i descs[RTE_I40E_DESCS_PER_LOOP];
326 __m128i pkt_mb1, pkt_mb2, pkt_mb3, pkt_mb4;
327 __m128i zero, staterr, sterr_tmp1, sterr_tmp2;
328 __m128i mbp1, mbp2; /* two mbuf pointer in one XMM reg. */
330 /* B.1 load 1 mbuf point */
331 mbp1 = _mm_loadu_si128((__m128i *)&sw_ring[pos]);
332 /* Read desc statuses backwards to avoid race condition */
333 /* A.1 load 4 pkts desc */
334 descs[3] = _mm_loadu_si128((__m128i *)(rxdp + 3));
335 rte_compiler_barrier();
337 /* B.2 copy 2 mbuf point into rx_pkts */
338 _mm_storeu_si128((__m128i *)&rx_pkts[pos], mbp1);
340 /* B.1 load 1 mbuf point */
341 mbp2 = _mm_loadu_si128((__m128i *)&sw_ring[pos+2]);
343 descs[2] = _mm_loadu_si128((__m128i *)(rxdp + 2));
344 rte_compiler_barrier();
345 /* B.1 load 2 mbuf point */
346 descs[1] = _mm_loadu_si128((__m128i *)(rxdp + 1));
347 rte_compiler_barrier();
348 descs[0] = _mm_loadu_si128((__m128i *)(rxdp));
350 /* B.2 copy 2 mbuf point into rx_pkts */
351 _mm_storeu_si128((__m128i *)&rx_pkts[pos+2], mbp2);
354 rte_mbuf_prefetch_part2(rx_pkts[pos]);
355 rte_mbuf_prefetch_part2(rx_pkts[pos + 1]);
356 rte_mbuf_prefetch_part2(rx_pkts[pos + 2]);
357 rte_mbuf_prefetch_part2(rx_pkts[pos + 3]);
360 /* avoid compiler reorder optimization */
361 rte_compiler_barrier();
363 /* pkt 3,4 shift the pktlen field to be 16-bit aligned*/
364 const __m128i len3 = _mm_slli_epi32(descs[3], PKTLEN_SHIFT);
365 const __m128i len2 = _mm_slli_epi32(descs[2], PKTLEN_SHIFT);
367 /* merge the now-aligned packet length fields back in */
368 descs[3] = _mm_blend_epi16(descs[3], len3, 0x80);
369 descs[2] = _mm_blend_epi16(descs[2], len2, 0x80);
371 /* D.1 pkt 3,4 convert format from desc to pktmbuf */
372 pkt_mb4 = _mm_shuffle_epi8(descs[3], shuf_msk);
373 pkt_mb3 = _mm_shuffle_epi8(descs[2], shuf_msk);
375 /* C.1 4=>2 filter staterr info only */
376 sterr_tmp2 = _mm_unpackhi_epi32(descs[3], descs[2]);
377 /* C.1 4=>2 filter staterr info only */
378 sterr_tmp1 = _mm_unpackhi_epi32(descs[1], descs[0]);
380 desc_to_olflags_v(rxq, descs, &rx_pkts[pos]);
382 /* D.2 pkt 3,4 set in_port/nb_seg and remove crc */
383 pkt_mb4 = _mm_add_epi16(pkt_mb4, crc_adjust);
384 pkt_mb3 = _mm_add_epi16(pkt_mb3, crc_adjust);
386 /* pkt 1,2 shift the pktlen field to be 16-bit aligned*/
387 const __m128i len1 = _mm_slli_epi32(descs[1], PKTLEN_SHIFT);
388 const __m128i len0 = _mm_slli_epi32(descs[0], PKTLEN_SHIFT);
390 /* merge the now-aligned packet length fields back in */
391 descs[1] = _mm_blend_epi16(descs[1], len1, 0x80);
392 descs[0] = _mm_blend_epi16(descs[0], len0, 0x80);
394 /* D.1 pkt 1,2 convert format from desc to pktmbuf */
395 pkt_mb2 = _mm_shuffle_epi8(descs[1], shuf_msk);
396 pkt_mb1 = _mm_shuffle_epi8(descs[0], shuf_msk);
398 /* C.2 get 4 pkts staterr value */
399 zero = _mm_xor_si128(dd_check, dd_check);
400 staterr = _mm_unpacklo_epi32(sterr_tmp1, sterr_tmp2);
402 /* D.3 copy final 3,4 data to rx_pkts */
403 _mm_storeu_si128((void *)&rx_pkts[pos+3]->rx_descriptor_fields1,
405 _mm_storeu_si128((void *)&rx_pkts[pos+2]->rx_descriptor_fields1,
408 /* D.2 pkt 1,2 set in_port/nb_seg and remove crc */
409 pkt_mb2 = _mm_add_epi16(pkt_mb2, crc_adjust);
410 pkt_mb1 = _mm_add_epi16(pkt_mb1, crc_adjust);
412 /* C* extract and record EOP bit */
414 __m128i eop_shuf_mask = _mm_set_epi8(
415 0xFF, 0xFF, 0xFF, 0xFF,
416 0xFF, 0xFF, 0xFF, 0xFF,
417 0xFF, 0xFF, 0xFF, 0xFF,
418 0x04, 0x0C, 0x00, 0x08
421 /* and with mask to extract bits, flipping 1-0 */
422 __m128i eop_bits = _mm_andnot_si128(staterr, eop_check);
423 /* the staterr values are not in order, as the count
424 * count of dd bits doesn't care. However, for end of
425 * packet tracking, we do care, so shuffle. This also
426 * compresses the 32-bit values to 8-bit
428 eop_bits = _mm_shuffle_epi8(eop_bits, eop_shuf_mask);
429 /* store the resulting 32-bit value */
430 *(int *)split_packet = _mm_cvtsi128_si32(eop_bits);
431 split_packet += RTE_I40E_DESCS_PER_LOOP;
434 /* C.3 calc available number of desc */
435 staterr = _mm_and_si128(staterr, dd_check);
436 staterr = _mm_packs_epi32(staterr, zero);
438 /* D.3 copy final 1,2 data to rx_pkts */
439 _mm_storeu_si128((void *)&rx_pkts[pos+1]->rx_descriptor_fields1,
441 _mm_storeu_si128((void *)&rx_pkts[pos]->rx_descriptor_fields1,
443 desc_to_ptype_v(descs, &rx_pkts[pos]);
444 /* C.4 calc avaialbe number of desc */
445 var = __builtin_popcountll(_mm_cvtsi128_si64(staterr));
447 if (likely(var != RTE_I40E_DESCS_PER_LOOP))
451 /* Update our internal tail pointer */
452 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_pkts_recd);
453 rxq->rx_tail = (uint16_t)(rxq->rx_tail & (rxq->nb_rx_desc - 1));
454 rxq->rxrearm_nb = (uint16_t)(rxq->rxrearm_nb + nb_pkts_recd);
461 * - nb_pkts < RTE_I40E_DESCS_PER_LOOP, just return no packet
462 * - nb_pkts > RTE_I40E_VPMD_RX_BURST, only scan RTE_I40E_VPMD_RX_BURST
466 i40e_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
469 return _recv_raw_pkts_vec(rx_queue, rx_pkts, nb_pkts, NULL);
472 /* vPMD receive routine that reassembles scattered packets
474 * - nb_pkts < RTE_I40E_DESCS_PER_LOOP, just return no packet
475 * - nb_pkts > RTE_I40E_VPMD_RX_BURST, only scan RTE_I40E_VPMD_RX_BURST
479 i40e_recv_scattered_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
483 struct i40e_rx_queue *rxq = rx_queue;
484 uint8_t split_flags[RTE_I40E_VPMD_RX_BURST] = {0};
486 /* get some new buffers */
487 uint16_t nb_bufs = _recv_raw_pkts_vec(rxq, rx_pkts, nb_pkts,
492 /* happy day case, full burst + no packets to be joined */
493 const uint64_t *split_fl64 = (uint64_t *)split_flags;
495 if (rxq->pkt_first_seg == NULL &&
496 split_fl64[0] == 0 && split_fl64[1] == 0 &&
497 split_fl64[2] == 0 && split_fl64[3] == 0)
500 /* reassemble any packets that need reassembly*/
503 if (rxq->pkt_first_seg == NULL) {
504 /* find the first split flag, and only reassemble then*/
505 while (i < nb_bufs && !split_flags[i])
510 return i + reassemble_packets(rxq, &rx_pkts[i], nb_bufs - i,
515 vtx1(volatile struct i40e_tx_desc *txdp,
516 struct rte_mbuf *pkt, uint64_t flags)
518 uint64_t high_qw = (I40E_TX_DESC_DTYPE_DATA |
519 ((uint64_t)flags << I40E_TXD_QW1_CMD_SHIFT) |
520 ((uint64_t)pkt->data_len << I40E_TXD_QW1_TX_BUF_SZ_SHIFT));
522 __m128i descriptor = _mm_set_epi64x(high_qw,
523 pkt->buf_physaddr + pkt->data_off);
524 _mm_store_si128((__m128i *)txdp, descriptor);
528 vtx(volatile struct i40e_tx_desc *txdp,
529 struct rte_mbuf **pkt, uint16_t nb_pkts, uint64_t flags)
533 for (i = 0; i < nb_pkts; ++i, ++txdp, ++pkt)
534 vtx1(txdp, *pkt, flags);
538 i40e_xmit_fixed_burst_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
541 struct i40e_tx_queue *txq = (struct i40e_tx_queue *)tx_queue;
542 volatile struct i40e_tx_desc *txdp;
543 struct i40e_tx_entry *txep;
544 uint16_t n, nb_commit, tx_id;
545 uint64_t flags = I40E_TD_CMD;
546 uint64_t rs = I40E_TX_DESC_CMD_RS | I40E_TD_CMD;
549 /* cross rx_thresh boundary is not allowed */
550 nb_pkts = RTE_MIN(nb_pkts, txq->tx_rs_thresh);
552 if (txq->nb_tx_free < txq->tx_free_thresh)
553 i40e_tx_free_bufs(txq);
555 nb_commit = nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
556 if (unlikely(nb_pkts == 0))
559 tx_id = txq->tx_tail;
560 txdp = &txq->tx_ring[tx_id];
561 txep = &txq->sw_ring[tx_id];
563 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
565 n = (uint16_t)(txq->nb_tx_desc - tx_id);
566 if (nb_commit >= n) {
567 tx_backlog_entry(txep, tx_pkts, n);
569 for (i = 0; i < n - 1; ++i, ++tx_pkts, ++txdp)
570 vtx1(txdp, *tx_pkts, flags);
572 vtx1(txdp, *tx_pkts++, rs);
574 nb_commit = (uint16_t)(nb_commit - n);
577 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
579 /* avoid reach the end of ring */
580 txdp = &txq->tx_ring[tx_id];
581 txep = &txq->sw_ring[tx_id];
584 tx_backlog_entry(txep, tx_pkts, nb_commit);
586 vtx(txdp, tx_pkts, nb_commit, flags);
588 tx_id = (uint16_t)(tx_id + nb_commit);
589 if (tx_id > txq->tx_next_rs) {
590 txq->tx_ring[txq->tx_next_rs].cmd_type_offset_bsz |=
591 rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
592 I40E_TXD_QW1_CMD_SHIFT);
594 (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
597 txq->tx_tail = tx_id;
599 I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
604 void __attribute__((cold))
605 i40e_rx_queue_release_mbufs_vec(struct i40e_rx_queue *rxq)
607 _i40e_rx_queue_release_mbufs_vec(rxq);
610 int __attribute__((cold))
611 i40e_rxq_vec_setup(struct i40e_rx_queue *rxq)
613 return i40e_rxq_vec_setup_default(rxq);
616 int __attribute__((cold))
617 i40e_txq_vec_setup(struct i40e_tx_queue __rte_unused *txq)
622 int __attribute__((cold))
623 i40e_rx_vec_dev_conf_condition_check(struct rte_eth_dev *dev)
625 #ifndef RTE_LIBRTE_IEEE1588
626 /* need SSE4.1 support */
627 if (!rte_cpu_get_flag_enabled(RTE_CPUFLAG_SSE4_1))
631 return i40e_rx_vec_dev_conf_condition_check_default(dev);