drivers/net/i40e/i40e_rxtx_vec_sse.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdint.h>
  35 #include <rte_ethdev.h>
  36 #include <rte_malloc.h>
  37
  38 #include "base/i40e_prototype.h"
  39 #include "base/i40e_type.h"
  40 #include "i40e_ethdev.h"
  41 #include "i40e_rxtx.h"
  42 #include "i40e_rxtx_vec_common.h"
  43
  44 #include <tmmintrin.h>
  45
  46 #ifndef __INTEL_COMPILER
  47 #pragma GCC diagnostic ignored "-Wcast-qual"
  48 #endif
  49
  50 static inline void
  51 i40e_rxq_rearm(struct i40e_rx_queue *rxq)
  52 {
  53         int i;
  54         uint16_t rx_id;
  55         volatile union i40e_rx_desc *rxdp;
  56         struct i40e_rx_entry *rxep = &rxq->sw_ring[rxq->rxrearm_start];
  57         struct rte_mbuf *mb0, *mb1;
  58         __m128i hdr_room = _mm_set_epi64x(RTE_PKTMBUF_HEADROOM,
  59                         RTE_PKTMBUF_HEADROOM);
  60         __m128i dma_addr0, dma_addr1;
  61
  62         rxdp = rxq->rx_ring + rxq->rxrearm_start;
  63
  64         /* Pull 'n' more MBUFs into the software ring */
  65         if (rte_mempool_get_bulk(rxq->mp,
  66                                  (void *)rxep,
  67                                  RTE_I40E_RXQ_REARM_THRESH) < 0) {
  68                 if (rxq->rxrearm_nb + RTE_I40E_RXQ_REARM_THRESH >=
  69                     rxq->nb_rx_desc) {
  70                         dma_addr0 = _mm_setzero_si128();
  71                         for (i = 0; i < RTE_I40E_DESCS_PER_LOOP; i++) {
  72                                 rxep[i].mbuf = &rxq->fake_mbuf;
  73                                 _mm_store_si128((__m128i *)&rxdp[i].read,
  74                                                 dma_addr0);
  75                         }
  76                 }
  77                 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
  78                         RTE_I40E_RXQ_REARM_THRESH;
  79                 return;
  80         }
  81
  82         /* Initialize the mbufs in vector, process 2 mbufs in one loop */
  83         for (i = 0; i < RTE_I40E_RXQ_REARM_THRESH; i += 2, rxep += 2) {
  84                 __m128i vaddr0, vaddr1;
  85
  86                 mb0 = rxep[0].mbuf;
  87                 mb1 = rxep[1].mbuf;
  88
  89                 /* load buf_addr(lo 64bit) and buf_physaddr(hi 64bit) */
  90                 vaddr0 = _mm_loadu_si128((__m128i *)&mb0->buf_addr);
  91                 vaddr1 = _mm_loadu_si128((__m128i *)&mb1->buf_addr);
  92
  93                 /* convert pa to dma_addr hdr/data */
  94                 dma_addr0 = _mm_unpackhi_epi64(vaddr0, vaddr0);
  95                 dma_addr1 = _mm_unpackhi_epi64(vaddr1, vaddr1);
  96
  97                 /* add headroom to pa values */
  98                 dma_addr0 = _mm_add_epi64(dma_addr0, hdr_room);
  99                 dma_addr1 = _mm_add_epi64(dma_addr1, hdr_room);
 100
 101                 /* flush desc with pa dma_addr */
 102                 _mm_store_si128((__m128i *)&rxdp++->read, dma_addr0);
 103                 _mm_store_si128((__m128i *)&rxdp++->read, dma_addr1);
 104         }
 105
 106         rxq->rxrearm_start += RTE_I40E_RXQ_REARM_THRESH;
 107         if (rxq->rxrearm_start >= rxq->nb_rx_desc)
 108                 rxq->rxrearm_start = 0;
 109
 110         rxq->rxrearm_nb -= RTE_I40E_RXQ_REARM_THRESH;
 111
 112         rx_id = (uint16_t)((rxq->rxrearm_start == 0) ?
 113                              (rxq->nb_rx_desc - 1) : (rxq->rxrearm_start - 1));
 114
 115         /* Update the tail pointer on the NIC */
 116         I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
 117 }
 118
 119 static inline void
 120 desc_to_olflags_v(struct i40e_rx_queue *rxq, __m128i descs[4] __rte_unused,
 121         struct rte_mbuf **rx_pkts)
 122 {
 123         const __m128i mbuf_init = _mm_set_epi64x(0, rxq->mbuf_initializer);
 124         __m128i rearm0, rearm1, rearm2, rearm3;
 125
 126         __m128i vlan0, vlan1, rss, l3_l4e;
 127
 128         /* mask everything except RSS, flow director and VLAN flags
 129          * bit2 is for VLAN tag, bit11 for flow director indication
 130          * bit13:12 for RSS indication.
 131          */
 132         const __m128i rss_vlan_msk = _mm_set_epi32(
 133                         0x1c03804, 0x1c03804, 0x1c03804, 0x1c03804);
 134
 135         const __m128i cksum_mask = _mm_set_epi32(
 136                         PKT_RX_IP_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD |
 137                         PKT_RX_L4_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD |
 138                         PKT_RX_EIP_CKSUM_BAD,
 139                         PKT_RX_IP_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD |
 140                         PKT_RX_L4_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD |
 141                         PKT_RX_EIP_CKSUM_BAD,
 142                         PKT_RX_IP_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD |
 143                         PKT_RX_L4_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD |
 144                         PKT_RX_EIP_CKSUM_BAD,
 145                         PKT_RX_IP_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD |
 146                         PKT_RX_L4_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD |
 147                         PKT_RX_EIP_CKSUM_BAD);
 148
 149         /* map rss and vlan type to rss hash and vlan flag */
 150         const __m128i vlan_flags = _mm_set_epi8(0, 0, 0, 0,
 151                         0, 0, 0, 0,
 152                         0, 0, 0, PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED,
 153                         0, 0, 0, 0);
 154
 155         const __m128i rss_flags = _mm_set_epi8(0, 0, 0, 0,
 156                         0, 0, 0, 0,
 157                         PKT_RX_RSS_HASH | PKT_RX_FDIR, PKT_RX_RSS_HASH, 0, 0,
 158                         0, 0, PKT_RX_FDIR, 0);
 159
 160         const __m128i l3_l4e_flags = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0,
 161                         /* shift right 1 bit to make sure it not exceed 255 */
 162                         (PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD |
 163                          PKT_RX_IP_CKSUM_BAD) >> 1,
 164                         (PKT_RX_IP_CKSUM_GOOD | PKT_RX_EIP_CKSUM_BAD |
 165                          PKT_RX_L4_CKSUM_BAD) >> 1,
 166                         (PKT_RX_EIP_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,
 167                         (PKT_RX_IP_CKSUM_GOOD | PKT_RX_EIP_CKSUM_BAD) >> 1,
 168                         (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,
 169                         (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD) >> 1,
 170                         PKT_RX_IP_CKSUM_BAD >> 1,
 171                         (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD) >> 1);
 172
 173         vlan0 = _mm_unpackhi_epi32(descs[0], descs[1]);
 174         vlan1 = _mm_unpackhi_epi32(descs[2], descs[3]);
 175         vlan0 = _mm_unpacklo_epi64(vlan0, vlan1);
 176
 177         vlan1 = _mm_and_si128(vlan0, rss_vlan_msk);
 178         vlan0 = _mm_shuffle_epi8(vlan_flags, vlan1);
 179
 180         rss = _mm_srli_epi32(vlan1, 11);
 181         rss = _mm_shuffle_epi8(rss_flags, rss);
 182
 183         l3_l4e = _mm_srli_epi32(vlan1, 22);
 184         l3_l4e = _mm_shuffle_epi8(l3_l4e_flags, l3_l4e);
 185         /* then we shift left 1 bit */
 186         l3_l4e = _mm_slli_epi32(l3_l4e, 1);
 187         /* we need to mask out the reduntant bits */
 188         l3_l4e = _mm_and_si128(l3_l4e, cksum_mask);
 189
 190         vlan0 = _mm_or_si128(vlan0, rss);
 191         vlan0 = _mm_or_si128(vlan0, l3_l4e);
 192
 193         /*
 194          * At this point, we have the 4 sets of flags in the low 16-bits
 195          * of each 32-bit value in vlan0.
 196          * We want to extract these, and merge them with the mbuf init data
 197          * so we can do a single 16-byte write to the mbuf to set the flags
 198          * and all the other initialization fields. Extracting the
 199          * appropriate flags means that we have to do a shift and blend for
 200          * each mbuf before we do the write.
 201          */
 202         rearm0 = _mm_blend_epi16(mbuf_init, _mm_slli_si128(vlan0, 8), 0x10);
 203         rearm1 = _mm_blend_epi16(mbuf_init, _mm_slli_si128(vlan0, 4), 0x10);
 204         rearm2 = _mm_blend_epi16(mbuf_init, vlan0, 0x10);
 205         rearm3 = _mm_blend_epi16(mbuf_init, _mm_srli_si128(vlan0, 4), 0x10);
 206         _mm_store_si128((__m128i *)&rx_pkts[0]->rearm_data, rearm0);
 207         _mm_store_si128((__m128i *)&rx_pkts[1]->rearm_data, rearm1);
 208         _mm_store_si128((__m128i *)&rx_pkts[2]->rearm_data, rearm2);
 209         _mm_store_si128((__m128i *)&rx_pkts[3]->rearm_data, rearm3);
 210 }
 211
 212 #define PKTLEN_SHIFT     10
 213
 214 static inline void
 215 desc_to_ptype_v(__m128i descs[4], struct rte_mbuf **rx_pkts)
 216 {
 217         __m128i ptype0 = _mm_unpackhi_epi64(descs[0], descs[1]);
 218         __m128i ptype1 = _mm_unpackhi_epi64(descs[2], descs[3]);
 219
 220         ptype0 = _mm_srli_epi64(ptype0, 30);
 221         ptype1 = _mm_srli_epi64(ptype1, 30);
 222
 223         rx_pkts[0]->packet_type = i40e_rxd_pkt_type_mapping(_mm_extract_epi8(ptype0, 0));
 224         rx_pkts[1]->packet_type = i40e_rxd_pkt_type_mapping(_mm_extract_epi8(ptype0, 8));
 225         rx_pkts[2]->packet_type = i40e_rxd_pkt_type_mapping(_mm_extract_epi8(ptype1, 0));
 226         rx_pkts[3]->packet_type = i40e_rxd_pkt_type_mapping(_mm_extract_epi8(ptype1, 8));
 227 }
 228
 229  /*
 230  * Notice:
 231  * - nb_pkts < RTE_I40E_DESCS_PER_LOOP, just return no packet
 232  * - nb_pkts > RTE_I40E_VPMD_RX_BURST, only scan RTE_I40E_VPMD_RX_BURST
 233  *   numbers of DD bits
 234  */
 235 static inline uint16_t
 236 _recv_raw_pkts_vec(struct i40e_rx_queue *rxq, struct rte_mbuf **rx_pkts,
 237                    uint16_t nb_pkts, uint8_t *split_packet)
 238 {
 239         volatile union i40e_rx_desc *rxdp;
 240         struct i40e_rx_entry *sw_ring;
 241         uint16_t nb_pkts_recd;
 242         int pos;
 243         uint64_t var;
 244         __m128i shuf_msk;
 245
 246         __m128i crc_adjust = _mm_set_epi16(
 247                                 0, 0, 0,    /* ignore non-length fields */
 248                                 -rxq->crc_len, /* sub crc on data_len */
 249                                 0,          /* ignore high-16bits of pkt_len */
 250                                 -rxq->crc_len, /* sub crc on pkt_len */
 251                                 0, 0            /* ignore pkt_type field */
 252                         );
 253         __m128i dd_check, eop_check;
 254
 255         /* nb_pkts shall be less equal than RTE_I40E_MAX_RX_BURST */
 256         nb_pkts = RTE_MIN(nb_pkts, RTE_I40E_MAX_RX_BURST);
 257
 258         /* nb_pkts has to be floor-aligned to RTE_I40E_DESCS_PER_LOOP */
 259         nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, RTE_I40E_DESCS_PER_LOOP);
 260
 261         /* Just the act of getting into the function from the application is
 262          * going to cost about 7 cycles
 263          */
 264         rxdp = rxq->rx_ring + rxq->rx_tail;
 265
 266         rte_prefetch0(rxdp);
 267
 268         /* See if we need to rearm the RX queue - gives the prefetch a bit
 269          * of time to act
 270          */
 271         if (rxq->rxrearm_nb > RTE_I40E_RXQ_REARM_THRESH)
 272                 i40e_rxq_rearm(rxq);
 273
 274         /* Before we start moving massive data around, check to see if
 275          * there is actually a packet available
 276          */
 277         if (!(rxdp->wb.qword1.status_error_len &
 278                         rte_cpu_to_le_32(1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 279                 return 0;
 280
 281         /* 4 packets DD mask */
 282         dd_check = _mm_set_epi64x(0x0000000100000001LL, 0x0000000100000001LL);
 283
 284         /* 4 packets EOP mask */
 285         eop_check = _mm_set_epi64x(0x0000000200000002LL, 0x0000000200000002LL);
 286
 287         /* mask to shuffle from desc. to mbuf */
 288         shuf_msk = _mm_set_epi8(
 289                 7, 6, 5, 4,  /* octet 4~7, 32bits rss */
 290                 3, 2,        /* octet 2~3, low 16 bits vlan_macip */
 291                 15, 14,      /* octet 15~14, 16 bits data_len */
 292                 0xFF, 0xFF,  /* skip high 16 bits pkt_len, zero out */
 293                 15, 14,      /* octet 15~14, low 16 bits pkt_len */
 294                 0xFF, 0xFF,  /* pkt_type set as unknown */
 295                 0xFF, 0xFF  /*pkt_type set as unknown */
 296                 );
 297
 298         /* Cache is empty -> need to scan the buffer rings, but first move
 299          * the next 'n' mbufs into the cache
 300          */
 301         sw_ring = &rxq->sw_ring[rxq->rx_tail];
 302
 303         /* A. load 4 packet in one loop
 304          * [A*. mask out 4 unused dirty field in desc]
 305          * B. copy 4 mbuf point from swring to rx_pkts
 306          * C. calc the number of DD bits among the 4 packets
 307          * [C*. extract the end-of-packet bit, if requested]
 308          * D. fill info. from desc to mbuf
 309          */
 310
 311         for (pos = 0, nb_pkts_recd = 0; pos < nb_pkts;
 312                         pos += RTE_I40E_DESCS_PER_LOOP,
 313                         rxdp += RTE_I40E_DESCS_PER_LOOP) {
 314                 __m128i descs[RTE_I40E_DESCS_PER_LOOP];
 315                 __m128i pkt_mb1, pkt_mb2, pkt_mb3, pkt_mb4;
 316                 __m128i zero, staterr, sterr_tmp1, sterr_tmp2;
 317                 __m128i mbp1, mbp2; /* two mbuf pointer in one XMM reg. */
 318
 319                 /* B.1 load 1 mbuf point */
 320                 mbp1 = _mm_loadu_si128((__m128i *)&sw_ring[pos]);
 321                 /* Read desc statuses backwards to avoid race condition */
 322                 /* A.1 load 4 pkts desc */
 323                 descs[3] = _mm_loadu_si128((__m128i *)(rxdp + 3));
 324                 rte_compiler_barrier();
 325
 326                 /* B.2 copy 2 mbuf point into rx_pkts  */
 327                 _mm_storeu_si128((__m128i *)&rx_pkts[pos], mbp1);
 328
 329                 /* B.1 load 1 mbuf point */
 330                 mbp2 = _mm_loadu_si128((__m128i *)&sw_ring[pos+2]);
 331
 332                 descs[2] = _mm_loadu_si128((__m128i *)(rxdp + 2));
 333                 rte_compiler_barrier();
 334                 /* B.1 load 2 mbuf point */
 335                 descs[1] = _mm_loadu_si128((__m128i *)(rxdp + 1));
 336                 rte_compiler_barrier();
 337                 descs[0] = _mm_loadu_si128((__m128i *)(rxdp));
 338
 339                 /* B.2 copy 2 mbuf point into rx_pkts  */
 340                 _mm_storeu_si128((__m128i *)&rx_pkts[pos+2], mbp2);
 341
 342                 if (split_packet) {
 343                         rte_mbuf_prefetch_part2(rx_pkts[pos]);
 344                         rte_mbuf_prefetch_part2(rx_pkts[pos + 1]);
 345                         rte_mbuf_prefetch_part2(rx_pkts[pos + 2]);
 346                         rte_mbuf_prefetch_part2(rx_pkts[pos + 3]);
 347                 }
 348
 349                 /* avoid compiler reorder optimization */
 350                 rte_compiler_barrier();
 351
 352                 /* pkt 3,4 shift the pktlen field to be 16-bit aligned*/
 353                 const __m128i len3 = _mm_slli_epi32(descs[3], PKTLEN_SHIFT);
 354                 const __m128i len2 = _mm_slli_epi32(descs[2], PKTLEN_SHIFT);
 355
 356                 /* merge the now-aligned packet length fields back in */
 357                 descs[3] = _mm_blend_epi16(descs[3], len3, 0x80);
 358                 descs[2] = _mm_blend_epi16(descs[2], len2, 0x80);
 359
 360                 /* D.1 pkt 3,4 convert format from desc to pktmbuf */
 361                 pkt_mb4 = _mm_shuffle_epi8(descs[3], shuf_msk);
 362                 pkt_mb3 = _mm_shuffle_epi8(descs[2], shuf_msk);
 363
 364                 /* C.1 4=>2 filter staterr info only */
 365                 sterr_tmp2 = _mm_unpackhi_epi32(descs[3], descs[2]);
 366                 /* C.1 4=>2 filter staterr info only */
 367                 sterr_tmp1 = _mm_unpackhi_epi32(descs[1], descs[0]);
 368
 369                 desc_to_olflags_v(rxq, descs, &rx_pkts[pos]);
 370
 371                 /* D.2 pkt 3,4 set in_port/nb_seg and remove crc */
 372                 pkt_mb4 = _mm_add_epi16(pkt_mb4, crc_adjust);
 373                 pkt_mb3 = _mm_add_epi16(pkt_mb3, crc_adjust);
 374
 375                 /* pkt 1,2 shift the pktlen field to be 16-bit aligned*/
 376                 const __m128i len1 = _mm_slli_epi32(descs[1], PKTLEN_SHIFT);
 377                 const __m128i len0 = _mm_slli_epi32(descs[0], PKTLEN_SHIFT);
 378
 379                 /* merge the now-aligned packet length fields back in */
 380                 descs[1] = _mm_blend_epi16(descs[1], len1, 0x80);
 381                 descs[0] = _mm_blend_epi16(descs[0], len0, 0x80);
 382
 383                 /* D.1 pkt 1,2 convert format from desc to pktmbuf */
 384                 pkt_mb2 = _mm_shuffle_epi8(descs[1], shuf_msk);
 385                 pkt_mb1 = _mm_shuffle_epi8(descs[0], shuf_msk);
 386
 387                 /* C.2 get 4 pkts staterr value  */
 388                 zero = _mm_xor_si128(dd_check, dd_check);
 389                 staterr = _mm_unpacklo_epi32(sterr_tmp1, sterr_tmp2);
 390
 391                 /* D.3 copy final 3,4 data to rx_pkts */
 392                 _mm_storeu_si128((void *)&rx_pkts[pos+3]->rx_descriptor_fields1,
 393                                  pkt_mb4);
 394                 _mm_storeu_si128((void *)&rx_pkts[pos+2]->rx_descriptor_fields1,
 395                                  pkt_mb3);
 396
 397                 /* D.2 pkt 1,2 set in_port/nb_seg and remove crc */
 398                 pkt_mb2 = _mm_add_epi16(pkt_mb2, crc_adjust);
 399                 pkt_mb1 = _mm_add_epi16(pkt_mb1, crc_adjust);
 400
 401                 /* C* extract and record EOP bit */
 402                 if (split_packet) {
 403                         __m128i eop_shuf_mask = _mm_set_epi8(
 404                                         0xFF, 0xFF, 0xFF, 0xFF,
 405                                         0xFF, 0xFF, 0xFF, 0xFF,
 406                                         0xFF, 0xFF, 0xFF, 0xFF,
 407                                         0x04, 0x0C, 0x00, 0x08
 408                                         );
 409
 410                         /* and with mask to extract bits, flipping 1-0 */
 411                         __m128i eop_bits = _mm_andnot_si128(staterr, eop_check);
 412                         /* the staterr values are not in order, as the count
 413                          * count of dd bits doesn't care. However, for end of
 414                          * packet tracking, we do care, so shuffle. This also
 415                          * compresses the 32-bit values to 8-bit
 416                          */
 417                         eop_bits = _mm_shuffle_epi8(eop_bits, eop_shuf_mask);
 418                         /* store the resulting 32-bit value */
 419                         *(int *)split_packet = _mm_cvtsi128_si32(eop_bits);
 420                         split_packet += RTE_I40E_DESCS_PER_LOOP;
 421                 }
 422
 423                 /* C.3 calc available number of desc */
 424                 staterr = _mm_and_si128(staterr, dd_check);
 425                 staterr = _mm_packs_epi32(staterr, zero);
 426
 427                 /* D.3 copy final 1,2 data to rx_pkts */
 428                 _mm_storeu_si128((void *)&rx_pkts[pos+1]->rx_descriptor_fields1,
 429                                  pkt_mb2);
 430                 _mm_storeu_si128((void *)&rx_pkts[pos]->rx_descriptor_fields1,
 431                                  pkt_mb1);
 432                 desc_to_ptype_v(descs, &rx_pkts[pos]);
 433                 /* C.4 calc avaialbe number of desc */
 434                 var = __builtin_popcountll(_mm_cvtsi128_si64(staterr));
 435                 nb_pkts_recd += var;
 436                 if (likely(var != RTE_I40E_DESCS_PER_LOOP))
 437                         break;
 438         }
 439
 440         /* Update our internal tail pointer */
 441         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_pkts_recd);
 442         rxq->rx_tail = (uint16_t)(rxq->rx_tail & (rxq->nb_rx_desc - 1));
 443         rxq->rxrearm_nb = (uint16_t)(rxq->rxrearm_nb + nb_pkts_recd);
 444
 445         return nb_pkts_recd;
 446 }
 447
 448  /*
 449  * Notice:
 450  * - nb_pkts < RTE_I40E_DESCS_PER_LOOP, just return no packet
 451  * - nb_pkts > RTE_I40E_VPMD_RX_BURST, only scan RTE_I40E_VPMD_RX_BURST
 452  *   numbers of DD bits
 453  */
 454 uint16_t
 455 i40e_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
 456                    uint16_t nb_pkts)
 457 {
 458         return _recv_raw_pkts_vec(rx_queue, rx_pkts, nb_pkts, NULL);
 459 }
 460
 461  /* vPMD receive routine that reassembles scattered packets
 462  * Notice:
 463  * - nb_pkts < RTE_I40E_DESCS_PER_LOOP, just return no packet
 464  * - nb_pkts > RTE_I40E_VPMD_RX_BURST, only scan RTE_I40E_VPMD_RX_BURST
 465  *   numbers of DD bits
 466  */
 467 uint16_t
 468 i40e_recv_scattered_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
 469                              uint16_t nb_pkts)
 470 {
 471
 472         struct i40e_rx_queue *rxq = rx_queue;
 473         uint8_t split_flags[RTE_I40E_VPMD_RX_BURST] = {0};
 474
 475         /* get some new buffers */
 476         uint16_t nb_bufs = _recv_raw_pkts_vec(rxq, rx_pkts, nb_pkts,
 477                         split_flags);
 478         if (nb_bufs == 0)
 479                 return 0;
 480
 481         /* happy day case, full burst + no packets to be joined */
 482         const uint64_t *split_fl64 = (uint64_t *)split_flags;
 483
 484         if (rxq->pkt_first_seg == NULL &&
 485                         split_fl64[0] == 0 && split_fl64[1] == 0 &&
 486                         split_fl64[2] == 0 && split_fl64[3] == 0)
 487                 return nb_bufs;
 488
 489         /* reassemble any packets that need reassembly*/
 490         unsigned i = 0;
 491
 492         if (rxq->pkt_first_seg == NULL) {
 493                 /* find the first split flag, and only reassemble then*/
 494                 while (i < nb_bufs && !split_flags[i])
 495                         i++;
 496                 if (i == nb_bufs)
 497                         return nb_bufs;
 498         }
 499         return i + reassemble_packets(rxq, &rx_pkts[i], nb_bufs - i,
 500                 &split_flags[i]);
 501 }
 502
 503 static inline void
 504 vtx1(volatile struct i40e_tx_desc *txdp,
 505                 struct rte_mbuf *pkt, uint64_t flags)
 506 {
 507         uint64_t high_qw = (I40E_TX_DESC_DTYPE_DATA |
 508                         ((uint64_t)flags  << I40E_TXD_QW1_CMD_SHIFT) |
 509                         ((uint64_t)pkt->data_len << I40E_TXD_QW1_TX_BUF_SZ_SHIFT));
 510
 511         __m128i descriptor = _mm_set_epi64x(high_qw,
 512                                 pkt->buf_physaddr + pkt->data_off);
 513         _mm_store_si128((__m128i *)txdp, descriptor);
 514 }
 515
 516 static inline void
 517 vtx(volatile struct i40e_tx_desc *txdp,
 518                 struct rte_mbuf **pkt, uint16_t nb_pkts,  uint64_t flags)
 519 {
 520         int i;
 521
 522         for (i = 0; i < nb_pkts; ++i, ++txdp, ++pkt)
 523                 vtx1(txdp, *pkt, flags);
 524 }
 525
 526 uint16_t
 527 i40e_xmit_fixed_burst_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
 528                           uint16_t nb_pkts)
 529 {
 530         struct i40e_tx_queue *txq = (struct i40e_tx_queue *)tx_queue;
 531         volatile struct i40e_tx_desc *txdp;
 532         struct i40e_tx_entry *txep;
 533         uint16_t n, nb_commit, tx_id;
 534         uint64_t flags = I40E_TD_CMD;
 535         uint64_t rs = I40E_TX_DESC_CMD_RS | I40E_TD_CMD;
 536         int i;
 537
 538         /* cross rx_thresh boundary is not allowed */
 539         nb_pkts = RTE_MIN(nb_pkts, txq->tx_rs_thresh);
 540
 541         if (txq->nb_tx_free < txq->tx_free_thresh)
 542                 i40e_tx_free_bufs(txq);
 543
 544         nb_commit = nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
 545         if (unlikely(nb_pkts == 0))
 546                 return 0;
 547
 548         tx_id = txq->tx_tail;
 549         txdp = &txq->tx_ring[tx_id];
 550         txep = &txq->sw_ring[tx_id];
 551
 552         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
 553
 554         n = (uint16_t)(txq->nb_tx_desc - tx_id);
 555         if (nb_commit >= n) {
 556                 tx_backlog_entry(txep, tx_pkts, n);
 557
 558                 for (i = 0; i < n - 1; ++i, ++tx_pkts, ++txdp)
 559                         vtx1(txdp, *tx_pkts, flags);
 560
 561                 vtx1(txdp, *tx_pkts++, rs);
 562
 563                 nb_commit = (uint16_t)(nb_commit - n);
 564
 565                 tx_id = 0;
 566                 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
 567
 568                 /* avoid reach the end of ring */
 569                 txdp = &txq->tx_ring[tx_id];
 570                 txep = &txq->sw_ring[tx_id];
 571         }
 572
 573         tx_backlog_entry(txep, tx_pkts, nb_commit);
 574
 575         vtx(txdp, tx_pkts, nb_commit, flags);
 576
 577         tx_id = (uint16_t)(tx_id + nb_commit);
 578         if (tx_id > txq->tx_next_rs) {
 579                 txq->tx_ring[txq->tx_next_rs].cmd_type_offset_bsz |=
 580                         rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
 581                                                 I40E_TXD_QW1_CMD_SHIFT);
 582                 txq->tx_next_rs =
 583                         (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
 584         }
 585
 586         txq->tx_tail = tx_id;
 587
 588         I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
 589
 590         return nb_pkts;
 591 }
 592
 593 void __attribute__((cold))
 594 i40e_rx_queue_release_mbufs_vec(struct i40e_rx_queue *rxq)
 595 {
 596         _i40e_rx_queue_release_mbufs_vec(rxq);
 597 }
 598
 599 int __attribute__((cold))
 600 i40e_rxq_vec_setup(struct i40e_rx_queue *rxq)
 601 {
 602         return i40e_rxq_vec_setup_default(rxq);
 603 }
 604
 605 int __attribute__((cold))
 606 i40e_txq_vec_setup(struct i40e_tx_queue __rte_unused *txq)
 607 {
 608         return 0;
 609 }
 610
 611 int __attribute__((cold))
 612 i40e_rx_vec_dev_conf_condition_check(struct rte_eth_dev *dev)
 613 {
 614 #ifndef RTE_LIBRTE_IEEE1588
 615         /* need SSE4.1 support */
 616         if (!rte_cpu_get_flag_enabled(RTE_CPUFLAG_SSE4_1))
 617                 return -1;
 618 #endif
 619
 620         return i40e_rx_vec_dev_conf_condition_check_default(dev);
 621 }