1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2017 Intel Corporation
5 #include <rte_string_fns.h>
6 #include <rte_malloc.h>
9 #include "base/i40e_prototype.h"
10 #include "base/i40e_dcb.h"
11 #include "i40e_ethdev.h"
13 #include "i40e_rxtx.h"
14 #include "rte_pmd_i40e.h"
17 rte_pmd_i40e_ping_vfs(uint16_t port, uint16_t vf)
19 struct rte_eth_dev *dev;
22 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
24 dev = &rte_eth_devices[port];
26 if (!is_i40e_supported(dev))
29 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
31 if (vf >= pf->vf_num || !pf->vfs) {
32 PMD_DRV_LOG(ERR, "Invalid argument.");
36 i40e_notify_vf_link_status(dev, &pf->vfs[vf]);
42 rte_pmd_i40e_set_vf_mac_anti_spoof(uint16_t port, uint16_t vf_id, uint8_t on)
44 struct rte_eth_dev *dev;
48 struct i40e_vsi_context ctxt;
51 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
53 dev = &rte_eth_devices[port];
55 if (!is_i40e_supported(dev))
58 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
60 if (vf_id >= pf->vf_num || !pf->vfs) {
61 PMD_DRV_LOG(ERR, "Invalid argument.");
65 vsi = pf->vfs[vf_id].vsi;
67 PMD_DRV_LOG(ERR, "Invalid VSI.");
71 /* Check if it has been already on or off */
72 if (vsi->info.valid_sections &
73 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SECURITY_VALID)) {
75 if ((vsi->info.sec_flags &
76 I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK) ==
77 I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK)
78 return 0; /* already on */
80 if ((vsi->info.sec_flags &
81 I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK) == 0)
82 return 0; /* already off */
86 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID);
88 vsi->info.sec_flags |= I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK;
90 vsi->info.sec_flags &= ~I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK;
92 memset(&ctxt, 0, sizeof(ctxt));
93 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
94 ctxt.seid = vsi->seid;
96 hw = I40E_VSI_TO_HW(vsi);
97 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
98 if (ret != I40E_SUCCESS) {
100 PMD_DRV_LOG(ERR, "Failed to update VSI params");
107 i40e_add_rm_all_vlan_filter(struct i40e_vsi *vsi, uint8_t add)
111 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
112 struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
115 for (j = 0; j < I40E_VFTA_SIZE; j++) {
119 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
120 if (!(vsi->vfta[j] & (1 << k)))
123 vlan_id = j * I40E_UINT32_BIT_SIZE + k;
127 vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
129 ret = i40e_aq_add_vlan(hw, vsi->seid,
130 &vlan_data, 1, NULL);
132 ret = i40e_aq_remove_vlan(hw, vsi->seid,
133 &vlan_data, 1, NULL);
134 if (ret != I40E_SUCCESS) {
136 "Failed to add/rm vlan filter");
146 rte_pmd_i40e_set_vf_vlan_anti_spoof(uint16_t port, uint16_t vf_id, uint8_t on)
148 struct rte_eth_dev *dev;
150 struct i40e_vsi *vsi;
152 struct i40e_vsi_context ctxt;
155 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
157 dev = &rte_eth_devices[port];
159 if (!is_i40e_supported(dev))
162 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
164 if (vf_id >= pf->vf_num || !pf->vfs) {
165 PMD_DRV_LOG(ERR, "Invalid argument.");
169 vsi = pf->vfs[vf_id].vsi;
171 PMD_DRV_LOG(ERR, "Invalid VSI.");
175 /* Check if it has been already on or off */
176 if (vsi->vlan_anti_spoof_on == on)
177 return 0; /* already on or off */
179 vsi->vlan_anti_spoof_on = on;
180 if (!vsi->vlan_filter_on) {
181 ret = i40e_add_rm_all_vlan_filter(vsi, on);
183 PMD_DRV_LOG(ERR, "Failed to add/remove VLAN filters.");
188 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID);
190 vsi->info.sec_flags |= I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK;
192 vsi->info.sec_flags &= ~I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK;
194 memset(&ctxt, 0, sizeof(ctxt));
195 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
196 ctxt.seid = vsi->seid;
198 hw = I40E_VSI_TO_HW(vsi);
199 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
200 if (ret != I40E_SUCCESS) {
202 PMD_DRV_LOG(ERR, "Failed to update VSI params");
209 i40e_vsi_rm_mac_filter(struct i40e_vsi *vsi)
211 struct i40e_mac_filter *f;
212 struct i40e_macvlan_filter *mv_f;
214 enum rte_mac_filter_type filter_type;
215 int ret = I40E_SUCCESS;
218 /* remove all the MACs */
219 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
220 vlan_num = vsi->vlan_num;
221 filter_type = f->mac_info.filter_type;
222 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
223 filter_type == RTE_MACVLAN_HASH_MATCH) {
225 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
226 return I40E_ERR_PARAM;
228 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
229 filter_type == RTE_MAC_HASH_MATCH)
232 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
234 PMD_DRV_LOG(ERR, "failed to allocate memory");
235 return I40E_ERR_NO_MEMORY;
238 for (i = 0; i < vlan_num; i++) {
239 mv_f[i].filter_type = filter_type;
240 rte_memcpy(&mv_f[i].macaddr,
241 &f->mac_info.mac_addr,
244 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
245 filter_type == RTE_MACVLAN_HASH_MATCH) {
246 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
247 &f->mac_info.mac_addr);
248 if (ret != I40E_SUCCESS) {
254 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
255 if (ret != I40E_SUCCESS) {
268 i40e_vsi_restore_mac_filter(struct i40e_vsi *vsi)
270 struct i40e_mac_filter *f;
271 struct i40e_macvlan_filter *mv_f;
273 int ret = I40E_SUCCESS;
276 /* restore all the MACs */
277 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
278 if ((f->mac_info.filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
279 (f->mac_info.filter_type == RTE_MACVLAN_HASH_MATCH)) {
281 * If vlan_num is 0, that's the first time to add mac,
282 * set mask for vlan_id 0.
284 if (vsi->vlan_num == 0) {
285 i40e_set_vlan_filter(vsi, 0, 1);
288 vlan_num = vsi->vlan_num;
289 } else if ((f->mac_info.filter_type == RTE_MAC_PERFECT_MATCH) ||
290 (f->mac_info.filter_type == RTE_MAC_HASH_MATCH))
293 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
295 PMD_DRV_LOG(ERR, "failed to allocate memory");
296 return I40E_ERR_NO_MEMORY;
299 for (i = 0; i < vlan_num; i++) {
300 mv_f[i].filter_type = f->mac_info.filter_type;
301 rte_memcpy(&mv_f[i].macaddr,
302 &f->mac_info.mac_addr,
306 if (f->mac_info.filter_type == RTE_MACVLAN_PERFECT_MATCH ||
307 f->mac_info.filter_type == RTE_MACVLAN_HASH_MATCH) {
308 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
309 &f->mac_info.mac_addr);
310 if (ret != I40E_SUCCESS) {
316 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
317 if (ret != I40E_SUCCESS) {
330 i40e_vsi_set_tx_loopback(struct i40e_vsi *vsi, uint8_t on)
332 struct i40e_vsi_context ctxt;
339 hw = I40E_VSI_TO_HW(vsi);
341 /* Use the FW API if FW >= v5.0 */
342 if (hw->aq.fw_maj_ver < 5 && hw->mac.type != I40E_MAC_X722) {
343 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
347 /* Check if it has been already on or off */
348 if (vsi->info.valid_sections &
349 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID)) {
351 if ((vsi->info.switch_id &
352 I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB) ==
353 I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB)
354 return 0; /* already on */
356 if ((vsi->info.switch_id &
357 I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB) == 0)
358 return 0; /* already off */
362 /* remove all the MAC and VLAN first */
363 ret = i40e_vsi_rm_mac_filter(vsi);
365 PMD_INIT_LOG(ERR, "Failed to remove MAC filters.");
368 if (vsi->vlan_anti_spoof_on || vsi->vlan_filter_on) {
369 ret = i40e_add_rm_all_vlan_filter(vsi, 0);
371 PMD_INIT_LOG(ERR, "Failed to remove VLAN filters.");
376 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
378 vsi->info.switch_id |= I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB;
380 vsi->info.switch_id &= ~I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB;
382 memset(&ctxt, 0, sizeof(ctxt));
383 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
384 ctxt.seid = vsi->seid;
386 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
387 if (ret != I40E_SUCCESS) {
388 PMD_DRV_LOG(ERR, "Failed to update VSI params");
392 /* add all the MAC and VLAN back */
393 ret = i40e_vsi_restore_mac_filter(vsi);
396 if (vsi->vlan_anti_spoof_on || vsi->vlan_filter_on) {
397 ret = i40e_add_rm_all_vlan_filter(vsi, 1);
406 rte_pmd_i40e_set_tx_loopback(uint16_t port, uint8_t on)
408 struct rte_eth_dev *dev;
410 struct i40e_pf_vf *vf;
411 struct i40e_vsi *vsi;
415 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
417 dev = &rte_eth_devices[port];
419 if (!is_i40e_supported(dev))
422 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
424 /* setup PF TX loopback */
426 ret = i40e_vsi_set_tx_loopback(vsi, on);
430 /* setup TX loopback for all the VFs */
432 /* if no VF, do nothing. */
436 for (vf_id = 0; vf_id < pf->vf_num; vf_id++) {
437 vf = &pf->vfs[vf_id];
440 ret = i40e_vsi_set_tx_loopback(vsi, on);
449 rte_pmd_i40e_set_vf_unicast_promisc(uint16_t port, uint16_t vf_id, uint8_t on)
451 struct rte_eth_dev *dev;
453 struct i40e_vsi *vsi;
457 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
459 dev = &rte_eth_devices[port];
461 if (!is_i40e_supported(dev))
464 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
466 if (vf_id >= pf->vf_num || !pf->vfs) {
467 PMD_DRV_LOG(ERR, "Invalid argument.");
471 vsi = pf->vfs[vf_id].vsi;
473 PMD_DRV_LOG(ERR, "Invalid VSI.");
477 hw = I40E_VSI_TO_HW(vsi);
479 ret = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
481 if (ret != I40E_SUCCESS) {
483 PMD_DRV_LOG(ERR, "Failed to set unicast promiscuous mode");
490 rte_pmd_i40e_set_vf_multicast_promisc(uint16_t port, uint16_t vf_id, uint8_t on)
492 struct rte_eth_dev *dev;
494 struct i40e_vsi *vsi;
498 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
500 dev = &rte_eth_devices[port];
502 if (!is_i40e_supported(dev))
505 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
507 if (vf_id >= pf->vf_num || !pf->vfs) {
508 PMD_DRV_LOG(ERR, "Invalid argument.");
512 vsi = pf->vfs[vf_id].vsi;
514 PMD_DRV_LOG(ERR, "Invalid VSI.");
518 hw = I40E_VSI_TO_HW(vsi);
520 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
522 if (ret != I40E_SUCCESS) {
524 PMD_DRV_LOG(ERR, "Failed to set multicast promiscuous mode");
531 rte_pmd_i40e_set_vf_mac_addr(uint16_t port, uint16_t vf_id,
532 struct rte_ether_addr *mac_addr)
534 struct i40e_mac_filter *f;
535 struct rte_eth_dev *dev;
536 struct i40e_pf_vf *vf;
537 struct i40e_vsi *vsi;
541 if (i40e_validate_mac_addr((u8 *)mac_addr) != I40E_SUCCESS)
544 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
546 dev = &rte_eth_devices[port];
548 if (!is_i40e_supported(dev))
551 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
553 if (vf_id >= pf->vf_num || !pf->vfs)
556 vf = &pf->vfs[vf_id];
559 PMD_DRV_LOG(ERR, "Invalid VSI.");
563 rte_ether_addr_copy(mac_addr, &vf->mac_addr);
565 /* Remove all existing mac */
566 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
567 if (i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr)
569 PMD_DRV_LOG(WARNING, "Delete MAC failed");
574 static const struct rte_ether_addr null_mac_addr;
577 rte_pmd_i40e_remove_vf_mac_addr(uint16_t port, uint16_t vf_id,
578 struct rte_ether_addr *mac_addr)
580 struct rte_eth_dev *dev;
581 struct i40e_pf_vf *vf;
582 struct i40e_vsi *vsi;
586 if (i40e_validate_mac_addr((u8 *)mac_addr) != I40E_SUCCESS)
589 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
591 dev = &rte_eth_devices[port];
593 if (!is_i40e_supported(dev))
596 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
598 if (vf_id >= pf->vf_num || !pf->vfs)
601 vf = &pf->vfs[vf_id];
604 PMD_DRV_LOG(ERR, "Invalid VSI.");
608 if (rte_is_same_ether_addr(mac_addr, &vf->mac_addr))
609 /* Reset the mac with NULL address */
610 rte_ether_addr_copy(&null_mac_addr, &vf->mac_addr);
613 ret = i40e_vsi_delete_mac(vsi, mac_addr);
614 if (ret != I40E_SUCCESS)
619 /* Set vlan strip on/off for specific VF from host */
621 rte_pmd_i40e_set_vf_vlan_stripq(uint16_t port, uint16_t vf_id, uint8_t on)
623 struct rte_eth_dev *dev;
625 struct i40e_vsi *vsi;
628 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
630 dev = &rte_eth_devices[port];
632 if (!is_i40e_supported(dev))
635 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
637 if (vf_id >= pf->vf_num || !pf->vfs) {
638 PMD_DRV_LOG(ERR, "Invalid argument.");
642 vsi = pf->vfs[vf_id].vsi;
647 ret = i40e_vsi_config_vlan_stripping(vsi, !!on);
648 if (ret != I40E_SUCCESS) {
650 PMD_DRV_LOG(ERR, "Failed to set VLAN stripping!");
656 int rte_pmd_i40e_set_vf_vlan_insert(uint16_t port, uint16_t vf_id,
659 struct rte_eth_dev *dev;
662 struct i40e_vsi *vsi;
663 struct i40e_vsi_context ctxt;
666 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
668 if (vlan_id > RTE_ETHER_MAX_VLAN_ID) {
669 PMD_DRV_LOG(ERR, "Invalid VLAN ID.");
673 dev = &rte_eth_devices[port];
675 if (!is_i40e_supported(dev))
678 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
679 hw = I40E_PF_TO_HW(pf);
682 * return -ENODEV if SRIOV not enabled, VF number not configured
683 * or no queue assigned.
685 if (!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 ||
689 if (vf_id >= pf->vf_num || !pf->vfs) {
690 PMD_DRV_LOG(ERR, "Invalid VF ID.");
694 vsi = pf->vfs[vf_id].vsi;
696 PMD_DRV_LOG(ERR, "Invalid VSI.");
700 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
701 vsi->info.pvid = vlan_id;
703 vsi->info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID;
705 vsi->info.port_vlan_flags &= ~I40E_AQ_VSI_PVLAN_INSERT_PVID;
707 memset(&ctxt, 0, sizeof(ctxt));
708 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
709 ctxt.seid = vsi->seid;
711 hw = I40E_VSI_TO_HW(vsi);
712 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
713 if (ret != I40E_SUCCESS) {
715 PMD_DRV_LOG(ERR, "Failed to update VSI params");
721 int rte_pmd_i40e_set_vf_broadcast(uint16_t port, uint16_t vf_id,
724 struct rte_eth_dev *dev;
726 struct i40e_vsi *vsi;
728 struct i40e_mac_filter_info filter;
729 struct rte_ether_addr broadcast = {
730 .addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} };
733 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
736 PMD_DRV_LOG(ERR, "on should be 0 or 1.");
740 dev = &rte_eth_devices[port];
742 if (!is_i40e_supported(dev))
745 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
746 hw = I40E_PF_TO_HW(pf);
748 if (vf_id >= pf->vf_num || !pf->vfs) {
749 PMD_DRV_LOG(ERR, "Invalid VF ID.");
754 * return -ENODEV if SRIOV not enabled, VF number not configured
755 * or no queue assigned.
757 if (!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 ||
758 pf->vf_nb_qps == 0) {
759 PMD_DRV_LOG(ERR, "SRIOV is not enabled or no queue.");
763 vsi = pf->vfs[vf_id].vsi;
765 PMD_DRV_LOG(ERR, "Invalid VSI.");
770 rte_memcpy(&filter.mac_addr, &broadcast, RTE_ETHER_ADDR_LEN);
771 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
772 ret = i40e_vsi_add_mac(vsi, &filter);
774 ret = i40e_vsi_delete_mac(vsi, &broadcast);
777 if (ret != I40E_SUCCESS && ret != I40E_ERR_PARAM) {
779 PMD_DRV_LOG(ERR, "Failed to set VSI broadcast");
787 int rte_pmd_i40e_set_vf_vlan_tag(uint16_t port, uint16_t vf_id, uint8_t on)
789 struct rte_eth_dev *dev;
792 struct i40e_vsi *vsi;
793 struct i40e_vsi_context ctxt;
796 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
799 PMD_DRV_LOG(ERR, "on should be 0 or 1.");
803 dev = &rte_eth_devices[port];
805 if (!is_i40e_supported(dev))
808 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
809 hw = I40E_PF_TO_HW(pf);
812 * return -ENODEV if SRIOV not enabled, VF number not configured
813 * or no queue assigned.
815 if (!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 ||
816 pf->vf_nb_qps == 0) {
817 PMD_DRV_LOG(ERR, "SRIOV is not enabled or no queue.");
821 if (vf_id >= pf->vf_num || !pf->vfs) {
822 PMD_DRV_LOG(ERR, "Invalid VF ID.");
826 vsi = pf->vfs[vf_id].vsi;
828 PMD_DRV_LOG(ERR, "Invalid VSI.");
832 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
834 vsi->info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
835 vsi->info.port_vlan_flags &= ~I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
837 vsi->info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
838 vsi->info.port_vlan_flags &= ~I40E_AQ_VSI_PVLAN_MODE_TAGGED;
841 memset(&ctxt, 0, sizeof(ctxt));
842 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
843 ctxt.seid = vsi->seid;
845 hw = I40E_VSI_TO_HW(vsi);
846 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
847 if (ret != I40E_SUCCESS) {
849 PMD_DRV_LOG(ERR, "Failed to update VSI params");
856 i40e_vlan_filter_count(struct i40e_vsi *vsi)
862 for (j = 0; j < I40E_VFTA_SIZE; j++) {
866 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
867 if (!(vsi->vfta[j] & (1 << k)))
870 vlan_id = j * I40E_UINT32_BIT_SIZE + k;
881 int rte_pmd_i40e_set_vf_vlan_filter(uint16_t port, uint16_t vlan_id,
882 uint64_t vf_mask, uint8_t on)
884 struct rte_eth_dev *dev;
887 struct i40e_vsi *vsi;
889 int ret = I40E_SUCCESS;
891 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
893 dev = &rte_eth_devices[port];
895 if (!is_i40e_supported(dev))
898 if (vlan_id > RTE_ETHER_MAX_VLAN_ID || !vlan_id) {
899 PMD_DRV_LOG(ERR, "Invalid VLAN ID.");
904 PMD_DRV_LOG(ERR, "No VF.");
909 PMD_DRV_LOG(ERR, "on is should be 0 or 1.");
913 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
914 hw = I40E_PF_TO_HW(pf);
917 * return -ENODEV if SRIOV not enabled, VF number not configured
918 * or no queue assigned.
920 if (!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 ||
921 pf->vf_nb_qps == 0) {
922 PMD_DRV_LOG(ERR, "SRIOV is not enabled or no queue.");
926 for (vf_idx = 0; vf_idx < pf->vf_num && ret == I40E_SUCCESS; vf_idx++) {
927 if (vf_mask & ((uint64_t)(1ULL << vf_idx))) {
928 vsi = pf->vfs[vf_idx].vsi;
930 if (!vsi->vlan_filter_on) {
931 vsi->vlan_filter_on = true;
932 i40e_aq_set_vsi_vlan_promisc(hw,
936 if (!vsi->vlan_anti_spoof_on)
937 i40e_add_rm_all_vlan_filter(
940 ret = i40e_vsi_add_vlan(vsi, vlan_id);
942 ret = i40e_vsi_delete_vlan(vsi, vlan_id);
944 if (!i40e_vlan_filter_count(vsi)) {
945 vsi->vlan_filter_on = false;
946 i40e_aq_set_vsi_vlan_promisc(hw,
955 if (ret != I40E_SUCCESS) {
957 PMD_DRV_LOG(ERR, "Failed to set VF VLAN filter, on = %d", on);
964 rte_pmd_i40e_get_vf_stats(uint16_t port,
966 struct rte_eth_stats *stats)
968 struct rte_eth_dev *dev;
970 struct i40e_vsi *vsi;
972 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
974 dev = &rte_eth_devices[port];
976 if (!is_i40e_supported(dev))
979 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
981 if (vf_id >= pf->vf_num || !pf->vfs) {
982 PMD_DRV_LOG(ERR, "Invalid VF ID.");
986 vsi = pf->vfs[vf_id].vsi;
988 PMD_DRV_LOG(ERR, "Invalid VSI.");
992 i40e_update_vsi_stats(vsi);
994 stats->ipackets = vsi->eth_stats.rx_unicast +
995 vsi->eth_stats.rx_multicast +
996 vsi->eth_stats.rx_broadcast;
997 stats->opackets = vsi->eth_stats.tx_unicast +
998 vsi->eth_stats.tx_multicast +
999 vsi->eth_stats.tx_broadcast;
1000 stats->ibytes = vsi->eth_stats.rx_bytes;
1001 stats->obytes = vsi->eth_stats.tx_bytes;
1002 stats->ierrors = vsi->eth_stats.rx_discards;
1003 stats->oerrors = vsi->eth_stats.tx_errors + vsi->eth_stats.tx_discards;
1009 rte_pmd_i40e_reset_vf_stats(uint16_t port,
1012 struct rte_eth_dev *dev;
1014 struct i40e_vsi *vsi;
1016 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
1018 dev = &rte_eth_devices[port];
1020 if (!is_i40e_supported(dev))
1023 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1025 if (vf_id >= pf->vf_num || !pf->vfs) {
1026 PMD_DRV_LOG(ERR, "Invalid VF ID.");
1030 vsi = pf->vfs[vf_id].vsi;
1032 PMD_DRV_LOG(ERR, "Invalid VSI.");
1036 vsi->offset_loaded = false;
1037 i40e_update_vsi_stats(vsi);
1043 rte_pmd_i40e_set_vf_max_bw(uint16_t port, uint16_t vf_id, uint32_t bw)
1045 struct rte_eth_dev *dev;
1047 struct i40e_vsi *vsi;
1052 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
1054 dev = &rte_eth_devices[port];
1056 if (!is_i40e_supported(dev))
1059 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1061 if (vf_id >= pf->vf_num || !pf->vfs) {
1062 PMD_DRV_LOG(ERR, "Invalid VF ID.");
1066 vsi = pf->vfs[vf_id].vsi;
1068 PMD_DRV_LOG(ERR, "Invalid VSI.");
1072 if (bw > I40E_QOS_BW_MAX) {
1073 PMD_DRV_LOG(ERR, "Bandwidth should not be larger than %dMbps.",
1078 if (bw % I40E_QOS_BW_GRANULARITY) {
1079 PMD_DRV_LOG(ERR, "Bandwidth should be the multiple of %dMbps.",
1080 I40E_QOS_BW_GRANULARITY);
1084 bw /= I40E_QOS_BW_GRANULARITY;
1086 hw = I40E_VSI_TO_HW(vsi);
1089 if (bw == vsi->bw_info.bw_limit) {
1091 "No change for VF max bandwidth. Nothing to do.");
1096 * VF bandwidth limitation and TC bandwidth limitation cannot be
1097 * enabled in parallel, quit if TC bandwidth limitation is enabled.
1099 * If bw is 0, means disable bandwidth limitation. Then no need to
1100 * check TC bandwidth limitation.
1103 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1104 if ((vsi->enabled_tc & BIT_ULL(i)) &&
1105 vsi->bw_info.bw_ets_credits[i])
1108 if (i != I40E_MAX_TRAFFIC_CLASS) {
1110 "TC max bandwidth has been set on this VF,"
1111 " please disable it first.");
1116 ret = i40e_aq_config_vsi_bw_limit(hw, vsi->seid, (uint16_t)bw, 0, NULL);
1119 "Failed to set VF %d bandwidth, err(%d).",
1124 /* Store the configuration. */
1125 vsi->bw_info.bw_limit = (uint16_t)bw;
1126 vsi->bw_info.bw_max = 0;
1132 rte_pmd_i40e_set_vf_tc_bw_alloc(uint16_t port, uint16_t vf_id,
1133 uint8_t tc_num, uint8_t *bw_weight)
1135 struct rte_eth_dev *dev;
1137 struct i40e_vsi *vsi;
1139 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw;
1143 bool b_change = false;
1145 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
1147 dev = &rte_eth_devices[port];
1149 if (!is_i40e_supported(dev))
1152 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1154 if (vf_id >= pf->vf_num || !pf->vfs) {
1155 PMD_DRV_LOG(ERR, "Invalid VF ID.");
1159 vsi = pf->vfs[vf_id].vsi;
1161 PMD_DRV_LOG(ERR, "Invalid VSI.");
1165 if (tc_num > I40E_MAX_TRAFFIC_CLASS) {
1166 PMD_DRV_LOG(ERR, "TCs should be no more than %d.",
1167 I40E_MAX_TRAFFIC_CLASS);
1172 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1173 if (vsi->enabled_tc & BIT_ULL(i))
1176 if (sum != tc_num) {
1178 "Weight should be set for all %d enabled TCs.",
1184 for (i = 0; i < tc_num; i++) {
1185 if (!bw_weight[i]) {
1187 "The weight should be 1 at least.");
1190 sum += bw_weight[i];
1194 "The summary of the TC weight should be 100.");
1199 * Create the configuration for all the TCs.
1201 memset(&tc_bw, 0, sizeof(tc_bw));
1202 tc_bw.tc_valid_bits = vsi->enabled_tc;
1204 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1205 if (vsi->enabled_tc & BIT_ULL(i)) {
1207 vsi->bw_info.bw_ets_share_credits[i])
1210 tc_bw.tc_bw_credits[i] = bw_weight[j];
1218 "No change for TC allocated bandwidth."
1223 hw = I40E_VSI_TO_HW(vsi);
1225 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw, NULL);
1228 "Failed to set VF %d TC bandwidth weight, err(%d).",
1233 /* Store the configuration. */
1235 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1236 if (vsi->enabled_tc & BIT_ULL(i)) {
1237 vsi->bw_info.bw_ets_share_credits[i] = bw_weight[j];
1246 rte_pmd_i40e_set_vf_tc_max_bw(uint16_t port, uint16_t vf_id,
1247 uint8_t tc_no, uint32_t bw)
1249 struct rte_eth_dev *dev;
1251 struct i40e_vsi *vsi;
1253 struct i40e_aqc_configure_vsi_ets_sla_bw_data tc_bw;
1257 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
1259 dev = &rte_eth_devices[port];
1261 if (!is_i40e_supported(dev))
1264 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1266 if (vf_id >= pf->vf_num || !pf->vfs) {
1267 PMD_DRV_LOG(ERR, "Invalid VF ID.");
1271 vsi = pf->vfs[vf_id].vsi;
1273 PMD_DRV_LOG(ERR, "Invalid VSI.");
1277 if (bw > I40E_QOS_BW_MAX) {
1278 PMD_DRV_LOG(ERR, "Bandwidth should not be larger than %dMbps.",
1283 if (bw % I40E_QOS_BW_GRANULARITY) {
1284 PMD_DRV_LOG(ERR, "Bandwidth should be the multiple of %dMbps.",
1285 I40E_QOS_BW_GRANULARITY);
1289 bw /= I40E_QOS_BW_GRANULARITY;
1291 if (tc_no >= I40E_MAX_TRAFFIC_CLASS) {
1292 PMD_DRV_LOG(ERR, "TC No. should be less than %d.",
1293 I40E_MAX_TRAFFIC_CLASS);
1297 hw = I40E_VSI_TO_HW(vsi);
1299 if (!(vsi->enabled_tc & BIT_ULL(tc_no))) {
1300 PMD_DRV_LOG(ERR, "VF %d TC %d isn't enabled.",
1306 if (bw == vsi->bw_info.bw_ets_credits[tc_no]) {
1308 "No change for TC max bandwidth. Nothing to do.");
1313 * VF bandwidth limitation and TC bandwidth limitation cannot be
1314 * enabled in parallel, disable VF bandwidth limitation if it's
1316 * If bw is 0, means disable bandwidth limitation. Then no need to
1317 * care about VF bandwidth limitation configuration.
1319 if (bw && vsi->bw_info.bw_limit) {
1320 ret = i40e_aq_config_vsi_bw_limit(hw, vsi->seid, 0, 0, NULL);
1323 "Failed to disable VF(%d)"
1324 " bandwidth limitation, err(%d).",
1330 "VF max bandwidth is disabled according"
1331 " to TC max bandwidth setting.");
1335 * Get all the TCs' info to create a whole picture.
1336 * Because the incremental change isn't permitted.
1338 memset(&tc_bw, 0, sizeof(tc_bw));
1339 tc_bw.tc_valid_bits = vsi->enabled_tc;
1340 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1341 if (vsi->enabled_tc & BIT_ULL(i)) {
1342 tc_bw.tc_bw_credits[i] =
1344 vsi->bw_info.bw_ets_credits[i]);
1347 tc_bw.tc_bw_credits[tc_no] = rte_cpu_to_le_16((uint16_t)bw);
1349 ret = i40e_aq_config_vsi_ets_sla_bw_limit(hw, vsi->seid, &tc_bw, NULL);
1352 "Failed to set VF %d TC %d max bandwidth, err(%d).",
1357 /* Store the configuration. */
1358 vsi->bw_info.bw_ets_credits[tc_no] = (uint16_t)bw;
1364 rte_pmd_i40e_set_tc_strict_prio(uint16_t port, uint8_t tc_map)
1366 struct rte_eth_dev *dev;
1368 struct i40e_vsi *vsi;
1369 struct i40e_veb *veb;
1371 struct i40e_aqc_configure_switching_comp_ets_data ets_data;
1375 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
1377 dev = &rte_eth_devices[port];
1379 if (!is_i40e_supported(dev))
1382 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1386 PMD_DRV_LOG(ERR, "Invalid VSI.");
1392 PMD_DRV_LOG(ERR, "Invalid VEB.");
1396 if ((tc_map & veb->enabled_tc) != tc_map) {
1398 "TC bitmap isn't the subset of enabled TCs 0x%x.",
1403 if (tc_map == veb->strict_prio_tc) {
1404 PMD_DRV_LOG(INFO, "No change for TC bitmap. Nothing to do.");
1408 hw = I40E_VSI_TO_HW(vsi);
1410 /* Disable DCBx if it's the first time to set strict priority. */
1411 if (!veb->strict_prio_tc) {
1412 ret = i40e_aq_stop_lldp(hw, true, true, NULL);
1415 "Failed to disable DCBx as it's already"
1419 "DCBx is disabled according to strict"
1420 " priority setting.");
1423 memset(&ets_data, 0, sizeof(ets_data));
1424 ets_data.tc_valid_bits = veb->enabled_tc;
1425 ets_data.seepage = I40E_AQ_ETS_SEEPAGE_EN_MASK;
1426 ets_data.tc_strict_priority_flags = tc_map;
1427 /* Get all TCs' bandwidth. */
1428 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1429 if (veb->enabled_tc & BIT_ULL(i)) {
1430 /* For rubust, if bandwidth is 0, use 1 instead. */
1431 if (veb->bw_info.bw_ets_share_credits[i])
1432 ets_data.tc_bw_share_credits[i] =
1433 veb->bw_info.bw_ets_share_credits[i];
1435 ets_data.tc_bw_share_credits[i] =
1436 I40E_QOS_BW_WEIGHT_MIN;
1440 if (!veb->strict_prio_tc)
1441 ret = i40e_aq_config_switch_comp_ets(
1442 hw, veb->uplink_seid,
1443 &ets_data, i40e_aqc_opc_enable_switching_comp_ets,
1446 ret = i40e_aq_config_switch_comp_ets(
1447 hw, veb->uplink_seid,
1448 &ets_data, i40e_aqc_opc_modify_switching_comp_ets,
1451 ret = i40e_aq_config_switch_comp_ets(
1452 hw, veb->uplink_seid,
1453 &ets_data, i40e_aqc_opc_disable_switching_comp_ets,
1458 "Failed to set TCs' strict priority mode."
1463 veb->strict_prio_tc = tc_map;
1465 /* Enable DCBx again, if all the TCs' strict priority disabled. */
1467 ret = i40e_aq_start_lldp(hw, true, NULL);
1470 "Failed to enable DCBx, err(%d).", ret);
1475 "DCBx is enabled again according to strict"
1476 " priority setting.");
1482 #define I40E_PROFILE_INFO_SIZE sizeof(struct rte_pmd_i40e_profile_info)
1483 #define I40E_MAX_PROFILE_NUM 16
1486 i40e_generate_profile_info_sec(char *name, struct i40e_ddp_version *version,
1487 uint32_t track_id, uint8_t *profile_info_sec,
1490 struct i40e_profile_section_header *sec = NULL;
1491 struct i40e_profile_info *pinfo;
1493 sec = (struct i40e_profile_section_header *)profile_info_sec;
1495 sec->data_end = sizeof(struct i40e_profile_section_header) +
1496 sizeof(struct i40e_profile_info);
1497 sec->section.type = SECTION_TYPE_INFO;
1498 sec->section.offset = sizeof(struct i40e_profile_section_header);
1499 sec->section.size = sizeof(struct i40e_profile_info);
1500 pinfo = (struct i40e_profile_info *)(profile_info_sec +
1501 sec->section.offset);
1502 pinfo->track_id = track_id;
1503 memcpy(pinfo->name, name, I40E_DDP_NAME_SIZE);
1504 memcpy(&pinfo->version, version, sizeof(struct i40e_ddp_version));
1506 pinfo->op = I40E_DDP_ADD_TRACKID;
1508 pinfo->op = I40E_DDP_REMOVE_TRACKID;
1511 static enum i40e_status_code
1512 i40e_add_rm_profile_info(struct i40e_hw *hw, uint8_t *profile_info_sec)
1514 enum i40e_status_code status = I40E_SUCCESS;
1515 struct i40e_profile_section_header *sec;
1517 uint32_t offset = 0;
1520 sec = (struct i40e_profile_section_header *)profile_info_sec;
1521 track_id = ((struct i40e_profile_info *)(profile_info_sec +
1522 sec->section.offset))->track_id;
1524 status = i40e_aq_write_ddp(hw, (void *)sec, sec->data_end,
1525 track_id, &offset, &info, NULL);
1527 PMD_DRV_LOG(ERR, "Failed to add/remove profile info: "
1528 "offset %d, info %d",
1534 /* Check if the profile info exists */
1536 i40e_check_profile_info(uint16_t port, uint8_t *profile_info_sec)
1538 struct rte_eth_dev *dev = &rte_eth_devices[port];
1539 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1541 struct rte_pmd_i40e_profile_list *p_list;
1542 struct rte_pmd_i40e_profile_info *pinfo, *p;
1545 static const uint32_t group_mask = 0x00ff0000;
1547 pinfo = (struct rte_pmd_i40e_profile_info *)(profile_info_sec +
1548 sizeof(struct i40e_profile_section_header));
1549 if (pinfo->track_id == 0) {
1550 PMD_DRV_LOG(INFO, "Read-only profile.");
1553 buff = rte_zmalloc("pinfo_list",
1554 (I40E_PROFILE_INFO_SIZE * I40E_MAX_PROFILE_NUM + 4),
1557 PMD_DRV_LOG(ERR, "failed to allocate memory");
1561 ret = i40e_aq_get_ddp_list(
1563 (I40E_PROFILE_INFO_SIZE * I40E_MAX_PROFILE_NUM + 4),
1566 PMD_DRV_LOG(ERR, "Failed to get profile info list.");
1570 p_list = (struct rte_pmd_i40e_profile_list *)buff;
1571 for (i = 0; i < p_list->p_count; i++) {
1572 p = &p_list->p_info[i];
1573 if (pinfo->track_id == p->track_id) {
1574 PMD_DRV_LOG(INFO, "Profile exists.");
1579 /* profile with group id 0xff is compatible with any other profile */
1580 if ((pinfo->track_id & group_mask) == group_mask) {
1584 for (i = 0; i < p_list->p_count; i++) {
1585 p = &p_list->p_info[i];
1586 if ((p->track_id & group_mask) == 0) {
1587 PMD_DRV_LOG(INFO, "Profile of the group 0 exists.");
1592 for (i = 0; i < p_list->p_count; i++) {
1593 p = &p_list->p_info[i];
1594 if ((p->track_id & group_mask) == group_mask)
1596 if ((pinfo->track_id & group_mask) !=
1597 (p->track_id & group_mask)) {
1598 PMD_DRV_LOG(INFO, "Profile of different group exists.");
1609 rte_pmd_i40e_process_ddp_package(uint16_t port, uint8_t *buff,
1611 enum rte_pmd_i40e_package_op op)
1613 struct rte_eth_dev *dev;
1615 struct i40e_package_header *pkg_hdr;
1616 struct i40e_generic_seg_header *profile_seg_hdr;
1617 struct i40e_generic_seg_header *metadata_seg_hdr;
1619 uint8_t *profile_info_sec;
1621 enum i40e_status_code status = I40E_SUCCESS;
1622 static const uint32_t type_mask = 0xff000000;
1624 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
1625 op != RTE_PMD_I40E_PKG_OP_WR_ONLY &&
1626 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
1627 PMD_DRV_LOG(ERR, "Operation not supported.");
1631 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
1633 dev = &rte_eth_devices[port];
1635 if (!is_i40e_supported(dev))
1638 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1640 if (size < (sizeof(struct i40e_package_header) +
1641 sizeof(struct i40e_metadata_segment) +
1642 sizeof(uint32_t) * 2)) {
1643 PMD_DRV_LOG(ERR, "Buff is invalid.");
1647 pkg_hdr = (struct i40e_package_header *)buff;
1650 PMD_DRV_LOG(ERR, "Failed to fill the package structure");
1654 if (pkg_hdr->segment_count < 2) {
1655 PMD_DRV_LOG(ERR, "Segment_count should be 2 at least.");
1659 /* Find metadata segment */
1660 metadata_seg_hdr = i40e_find_segment_in_package(SEGMENT_TYPE_METADATA,
1662 if (!metadata_seg_hdr) {
1663 PMD_DRV_LOG(ERR, "Failed to find metadata segment header");
1666 track_id = ((struct i40e_metadata_segment *)metadata_seg_hdr)->track_id;
1667 if (track_id == I40E_DDP_TRACKID_INVALID) {
1668 PMD_DRV_LOG(ERR, "Invalid track_id");
1672 /* force read-only track_id for type 0 */
1673 if ((track_id & type_mask) == 0)
1676 /* Find profile segment */
1677 profile_seg_hdr = i40e_find_segment_in_package(SEGMENT_TYPE_I40E,
1679 if (!profile_seg_hdr) {
1680 PMD_DRV_LOG(ERR, "Failed to find profile segment header");
1684 profile_info_sec = rte_zmalloc(
1685 "i40e_profile_info",
1686 sizeof(struct i40e_profile_section_header) +
1687 sizeof(struct i40e_profile_info),
1689 if (!profile_info_sec) {
1690 PMD_DRV_LOG(ERR, "Failed to allocate memory");
1694 /* Check if the profile already loaded */
1695 i40e_generate_profile_info_sec(
1696 ((struct i40e_profile_segment *)profile_seg_hdr)->name,
1697 &((struct i40e_profile_segment *)profile_seg_hdr)->version,
1698 track_id, profile_info_sec,
1699 op == RTE_PMD_I40E_PKG_OP_WR_ADD);
1700 is_exist = i40e_check_profile_info(port, profile_info_sec);
1702 PMD_DRV_LOG(ERR, "Failed to check profile.");
1703 rte_free(profile_info_sec);
1707 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) {
1710 PMD_DRV_LOG(ERR, "Profile already exists.");
1711 else if (is_exist == 2)
1712 PMD_DRV_LOG(ERR, "Profile of group 0 already exists.");
1713 else if (is_exist == 3)
1714 PMD_DRV_LOG(ERR, "Profile of different group already exists");
1715 i40e_update_customized_info(dev, buff, size, op);
1716 rte_free(profile_info_sec);
1719 } else if (op == RTE_PMD_I40E_PKG_OP_WR_DEL) {
1720 if (is_exist != 1) {
1721 PMD_DRV_LOG(ERR, "Profile does not exist.");
1722 rte_free(profile_info_sec);
1727 if (op == RTE_PMD_I40E_PKG_OP_WR_DEL) {
1728 status = i40e_rollback_profile(
1730 (struct i40e_profile_segment *)profile_seg_hdr,
1733 PMD_DRV_LOG(ERR, "Failed to write profile for delete.");
1734 rte_free(profile_info_sec);
1738 status = i40e_write_profile(
1740 (struct i40e_profile_segment *)profile_seg_hdr,
1743 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
1744 PMD_DRV_LOG(ERR, "Failed to write profile for add.");
1746 PMD_DRV_LOG(ERR, "Failed to write profile.");
1747 rte_free(profile_info_sec);
1752 if (track_id && (op != RTE_PMD_I40E_PKG_OP_WR_ONLY)) {
1753 /* Modify loaded profiles info list */
1754 status = i40e_add_rm_profile_info(hw, profile_info_sec);
1756 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
1757 PMD_DRV_LOG(ERR, "Failed to add profile to info list.");
1759 PMD_DRV_LOG(ERR, "Failed to delete profile from info list.");
1763 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD ||
1764 op == RTE_PMD_I40E_PKG_OP_WR_DEL)
1765 i40e_update_customized_info(dev, buff, size, op);
1767 rte_free(profile_info_sec);
1771 /* Get number of tvl records in the section */
1773 i40e_get_tlv_section_size(struct i40e_profile_section_header *sec)
1775 unsigned int i, nb_rec, nb_tlv = 0;
1776 struct i40e_profile_tlv_section_record *tlv;
1781 /* get number of records in the section */
1782 nb_rec = sec->section.size /
1783 sizeof(struct i40e_profile_tlv_section_record);
1784 for (i = 0; i < nb_rec; ) {
1785 tlv = (struct i40e_profile_tlv_section_record *)&sec[1 + i];
1792 int rte_pmd_i40e_get_ddp_info(uint8_t *pkg_buff, uint32_t pkg_size,
1793 uint8_t *info_buff, uint32_t info_size,
1794 enum rte_pmd_i40e_package_info type)
1797 struct i40e_package_header *pkg_hdr;
1798 struct i40e_generic_seg_header *i40e_seg_hdr;
1799 struct i40e_generic_seg_header *note_seg_hdr;
1800 struct i40e_generic_seg_header *metadata_seg_hdr;
1803 PMD_DRV_LOG(ERR, "Output info buff is invalid.");
1807 if (!pkg_buff || pkg_size < (sizeof(struct i40e_package_header) +
1808 sizeof(struct i40e_metadata_segment) +
1809 sizeof(uint32_t) * 2)) {
1810 PMD_DRV_LOG(ERR, "Package buff is invalid.");
1814 pkg_hdr = (struct i40e_package_header *)pkg_buff;
1815 if (pkg_hdr->segment_count < 2) {
1816 PMD_DRV_LOG(ERR, "Segment_count should be 2 at least.");
1820 /* Find metadata segment */
1821 metadata_seg_hdr = i40e_find_segment_in_package(SEGMENT_TYPE_METADATA,
1824 /* Find global notes segment */
1825 note_seg_hdr = i40e_find_segment_in_package(SEGMENT_TYPE_NOTES,
1828 /* Find i40e profile segment */
1829 i40e_seg_hdr = i40e_find_segment_in_package(SEGMENT_TYPE_I40E, pkg_hdr);
1831 /* get global header info */
1832 if (type == RTE_PMD_I40E_PKG_INFO_GLOBAL_HEADER) {
1833 struct rte_pmd_i40e_profile_info *info =
1834 (struct rte_pmd_i40e_profile_info *)info_buff;
1836 if (info_size < sizeof(struct rte_pmd_i40e_profile_info)) {
1837 PMD_DRV_LOG(ERR, "Output info buff size is invalid.");
1841 if (!metadata_seg_hdr) {
1842 PMD_DRV_LOG(ERR, "Failed to find metadata segment header");
1846 memset(info, 0, sizeof(struct rte_pmd_i40e_profile_info));
1847 info->owner = RTE_PMD_I40E_DDP_OWNER_UNKNOWN;
1849 ((struct i40e_metadata_segment *)metadata_seg_hdr)->track_id;
1852 ((struct i40e_metadata_segment *)metadata_seg_hdr)->name,
1853 I40E_DDP_NAME_SIZE);
1854 memcpy(&info->version,
1855 &((struct i40e_metadata_segment *)metadata_seg_hdr)->version,
1856 sizeof(struct i40e_ddp_version));
1857 return I40E_SUCCESS;
1860 /* get global note size */
1861 if (type == RTE_PMD_I40E_PKG_INFO_GLOBAL_NOTES_SIZE) {
1862 if (info_size < sizeof(uint32_t)) {
1863 PMD_DRV_LOG(ERR, "Invalid information buffer size");
1866 if (note_seg_hdr == NULL)
1869 ret_size = note_seg_hdr->size;
1870 *(uint32_t *)info_buff = ret_size;
1871 return I40E_SUCCESS;
1874 /* get global note */
1875 if (type == RTE_PMD_I40E_PKG_INFO_GLOBAL_NOTES) {
1876 if (note_seg_hdr == NULL)
1878 if (info_size < note_seg_hdr->size) {
1879 PMD_DRV_LOG(ERR, "Information buffer size is too small");
1882 memcpy(info_buff, ¬e_seg_hdr[1], note_seg_hdr->size);
1883 return I40E_SUCCESS;
1886 /* get i40e segment header info */
1887 if (type == RTE_PMD_I40E_PKG_INFO_HEADER) {
1888 struct rte_pmd_i40e_profile_info *info =
1889 (struct rte_pmd_i40e_profile_info *)info_buff;
1891 if (info_size < sizeof(struct rte_pmd_i40e_profile_info)) {
1892 PMD_DRV_LOG(ERR, "Output info buff size is invalid.");
1896 if (!metadata_seg_hdr) {
1897 PMD_DRV_LOG(ERR, "Failed to find metadata segment header");
1901 if (!i40e_seg_hdr) {
1902 PMD_DRV_LOG(ERR, "Failed to find i40e segment header");
1906 memset(info, 0, sizeof(struct rte_pmd_i40e_profile_info));
1907 info->owner = RTE_PMD_I40E_DDP_OWNER_UNKNOWN;
1909 ((struct i40e_metadata_segment *)metadata_seg_hdr)->track_id;
1912 ((struct i40e_profile_segment *)i40e_seg_hdr)->name,
1913 I40E_DDP_NAME_SIZE);
1914 memcpy(&info->version,
1915 &((struct i40e_profile_segment *)i40e_seg_hdr)->version,
1916 sizeof(struct i40e_ddp_version));
1917 return I40E_SUCCESS;
1920 /* get number of devices */
1921 if (type == RTE_PMD_I40E_PKG_INFO_DEVID_NUM) {
1922 if (info_size < sizeof(uint32_t)) {
1923 PMD_DRV_LOG(ERR, "Invalid information buffer size");
1926 *(uint32_t *)info_buff =
1927 ((struct i40e_profile_segment *)i40e_seg_hdr)->device_table_count;
1928 return I40E_SUCCESS;
1931 /* get list of devices */
1932 if (type == RTE_PMD_I40E_PKG_INFO_DEVID_LIST) {
1935 ((struct i40e_profile_segment *)i40e_seg_hdr)->device_table_count;
1936 if (info_size < sizeof(struct rte_pmd_i40e_ddp_device_id) * dev_num) {
1937 PMD_DRV_LOG(ERR, "Invalid information buffer size");
1941 ((struct i40e_profile_segment *)i40e_seg_hdr)->device_table,
1942 sizeof(struct rte_pmd_i40e_ddp_device_id) * dev_num);
1943 return I40E_SUCCESS;
1946 /* get number of protocols */
1947 if (type == RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM) {
1948 struct i40e_profile_section_header *proto;
1950 if (info_size < sizeof(uint32_t)) {
1951 PMD_DRV_LOG(ERR, "Invalid information buffer size");
1954 proto = i40e_find_section_in_profile(SECTION_TYPE_PROTO,
1955 (struct i40e_profile_segment *)i40e_seg_hdr);
1956 *(uint32_t *)info_buff = i40e_get_tlv_section_size(proto);
1957 return I40E_SUCCESS;
1960 /* get list of protocols */
1961 if (type == RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST) {
1962 uint32_t i, j, nb_tlv, nb_rec, nb_proto_info;
1963 struct rte_pmd_i40e_proto_info *pinfo;
1964 struct i40e_profile_section_header *proto;
1965 struct i40e_profile_tlv_section_record *tlv;
1967 pinfo = (struct rte_pmd_i40e_proto_info *)info_buff;
1968 nb_proto_info = info_size /
1969 sizeof(struct rte_pmd_i40e_proto_info);
1970 for (i = 0; i < nb_proto_info; i++) {
1971 pinfo[i].proto_id = RTE_PMD_I40E_PROTO_UNUSED;
1972 memset(pinfo[i].name, 0, RTE_PMD_I40E_DDP_NAME_SIZE);
1974 proto = i40e_find_section_in_profile(SECTION_TYPE_PROTO,
1975 (struct i40e_profile_segment *)i40e_seg_hdr);
1976 nb_tlv = i40e_get_tlv_section_size(proto);
1978 return I40E_SUCCESS;
1979 if (nb_proto_info < nb_tlv) {
1980 PMD_DRV_LOG(ERR, "Invalid information buffer size");
1983 /* get number of records in the section */
1984 nb_rec = proto->section.size /
1985 sizeof(struct i40e_profile_tlv_section_record);
1986 tlv = (struct i40e_profile_tlv_section_record *)&proto[1];
1987 for (i = j = 0; i < nb_rec; j++) {
1988 pinfo[j].proto_id = tlv->data[0];
1989 strlcpy(pinfo[j].name, (const char *)&tlv->data[1],
1990 I40E_DDP_NAME_SIZE);
1992 tlv = &tlv[tlv->len];
1994 return I40E_SUCCESS;
1997 /* get number of packet classification types */
1998 if (type == RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM) {
1999 struct i40e_profile_section_header *pctype;
2001 if (info_size < sizeof(uint32_t)) {
2002 PMD_DRV_LOG(ERR, "Invalid information buffer size");
2005 pctype = i40e_find_section_in_profile(SECTION_TYPE_PCTYPE,
2006 (struct i40e_profile_segment *)i40e_seg_hdr);
2007 *(uint32_t *)info_buff = i40e_get_tlv_section_size(pctype);
2008 return I40E_SUCCESS;
2011 /* get list of packet classification types */
2012 if (type == RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST) {
2013 uint32_t i, j, nb_tlv, nb_rec, nb_proto_info;
2014 struct rte_pmd_i40e_ptype_info *pinfo;
2015 struct i40e_profile_section_header *pctype;
2016 struct i40e_profile_tlv_section_record *tlv;
2018 pinfo = (struct rte_pmd_i40e_ptype_info *)info_buff;
2019 nb_proto_info = info_size /
2020 sizeof(struct rte_pmd_i40e_ptype_info);
2021 for (i = 0; i < nb_proto_info; i++)
2022 memset(&pinfo[i], RTE_PMD_I40E_PROTO_UNUSED,
2023 sizeof(struct rte_pmd_i40e_ptype_info));
2024 pctype = i40e_find_section_in_profile(SECTION_TYPE_PCTYPE,
2025 (struct i40e_profile_segment *)i40e_seg_hdr);
2026 nb_tlv = i40e_get_tlv_section_size(pctype);
2028 return I40E_SUCCESS;
2029 if (nb_proto_info < nb_tlv) {
2030 PMD_DRV_LOG(ERR, "Invalid information buffer size");
2034 /* get number of records in the section */
2035 nb_rec = pctype->section.size /
2036 sizeof(struct i40e_profile_tlv_section_record);
2037 tlv = (struct i40e_profile_tlv_section_record *)&pctype[1];
2038 for (i = j = 0; i < nb_rec; j++) {
2039 memcpy(&pinfo[j], tlv->data,
2040 sizeof(struct rte_pmd_i40e_ptype_info));
2042 tlv = &tlv[tlv->len];
2044 return I40E_SUCCESS;
2047 /* get number of packet types */
2048 if (type == RTE_PMD_I40E_PKG_INFO_PTYPE_NUM) {
2049 struct i40e_profile_section_header *ptype;
2051 if (info_size < sizeof(uint32_t)) {
2052 PMD_DRV_LOG(ERR, "Invalid information buffer size");
2055 ptype = i40e_find_section_in_profile(SECTION_TYPE_PTYPE,
2056 (struct i40e_profile_segment *)i40e_seg_hdr);
2057 *(uint32_t *)info_buff = i40e_get_tlv_section_size(ptype);
2058 return I40E_SUCCESS;
2061 /* get list of packet types */
2062 if (type == RTE_PMD_I40E_PKG_INFO_PTYPE_LIST) {
2063 uint32_t i, j, nb_tlv, nb_rec, nb_proto_info;
2064 struct rte_pmd_i40e_ptype_info *pinfo;
2065 struct i40e_profile_section_header *ptype;
2066 struct i40e_profile_tlv_section_record *tlv;
2068 pinfo = (struct rte_pmd_i40e_ptype_info *)info_buff;
2069 nb_proto_info = info_size /
2070 sizeof(struct rte_pmd_i40e_ptype_info);
2071 for (i = 0; i < nb_proto_info; i++)
2072 memset(&pinfo[i], RTE_PMD_I40E_PROTO_UNUSED,
2073 sizeof(struct rte_pmd_i40e_ptype_info));
2074 ptype = i40e_find_section_in_profile(SECTION_TYPE_PTYPE,
2075 (struct i40e_profile_segment *)i40e_seg_hdr);
2076 nb_tlv = i40e_get_tlv_section_size(ptype);
2078 return I40E_SUCCESS;
2079 if (nb_proto_info < nb_tlv) {
2080 PMD_DRV_LOG(ERR, "Invalid information buffer size");
2083 /* get number of records in the section */
2084 nb_rec = ptype->section.size /
2085 sizeof(struct i40e_profile_tlv_section_record);
2086 for (i = j = 0; i < nb_rec; j++) {
2087 tlv = (struct i40e_profile_tlv_section_record *)
2089 memcpy(&pinfo[j], tlv->data,
2090 sizeof(struct rte_pmd_i40e_ptype_info));
2093 return I40E_SUCCESS;
2096 PMD_DRV_LOG(ERR, "Info type %u is invalid.", type);
2101 rte_pmd_i40e_get_ddp_list(uint16_t port, uint8_t *buff, uint32_t size)
2103 struct rte_eth_dev *dev;
2105 enum i40e_status_code status = I40E_SUCCESS;
2107 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
2109 dev = &rte_eth_devices[port];
2111 if (!is_i40e_supported(dev))
2114 if (size < (I40E_PROFILE_INFO_SIZE * I40E_MAX_PROFILE_NUM + 4))
2117 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2119 status = i40e_aq_get_ddp_list(hw, (void *)buff,
2125 static int check_invalid_pkt_type(uint32_t pkt_type)
2127 uint32_t l2, l3, l4, tnl, il2, il3, il4;
2129 l2 = pkt_type & RTE_PTYPE_L2_MASK;
2130 l3 = pkt_type & RTE_PTYPE_L3_MASK;
2131 l4 = pkt_type & RTE_PTYPE_L4_MASK;
2132 tnl = pkt_type & RTE_PTYPE_TUNNEL_MASK;
2133 il2 = pkt_type & RTE_PTYPE_INNER_L2_MASK;
2134 il3 = pkt_type & RTE_PTYPE_INNER_L3_MASK;
2135 il4 = pkt_type & RTE_PTYPE_INNER_L4_MASK;
2138 l2 != RTE_PTYPE_L2_ETHER &&
2139 l2 != RTE_PTYPE_L2_ETHER_TIMESYNC &&
2140 l2 != RTE_PTYPE_L2_ETHER_ARP &&
2141 l2 != RTE_PTYPE_L2_ETHER_LLDP &&
2142 l2 != RTE_PTYPE_L2_ETHER_NSH &&
2143 l2 != RTE_PTYPE_L2_ETHER_VLAN &&
2144 l2 != RTE_PTYPE_L2_ETHER_QINQ &&
2145 l2 != RTE_PTYPE_L2_ETHER_PPPOE)
2149 l3 != RTE_PTYPE_L3_IPV4 &&
2150 l3 != RTE_PTYPE_L3_IPV4_EXT &&
2151 l3 != RTE_PTYPE_L3_IPV6 &&
2152 l3 != RTE_PTYPE_L3_IPV4_EXT_UNKNOWN &&
2153 l3 != RTE_PTYPE_L3_IPV6_EXT &&
2154 l3 != RTE_PTYPE_L3_IPV6_EXT_UNKNOWN)
2158 l4 != RTE_PTYPE_L4_TCP &&
2159 l4 != RTE_PTYPE_L4_UDP &&
2160 l4 != RTE_PTYPE_L4_FRAG &&
2161 l4 != RTE_PTYPE_L4_SCTP &&
2162 l4 != RTE_PTYPE_L4_ICMP &&
2163 l4 != RTE_PTYPE_L4_NONFRAG)
2167 tnl != RTE_PTYPE_TUNNEL_IP &&
2168 tnl != RTE_PTYPE_TUNNEL_GRENAT &&
2169 tnl != RTE_PTYPE_TUNNEL_VXLAN &&
2170 tnl != RTE_PTYPE_TUNNEL_NVGRE &&
2171 tnl != RTE_PTYPE_TUNNEL_GENEVE &&
2172 tnl != RTE_PTYPE_TUNNEL_GRENAT &&
2173 tnl != RTE_PTYPE_TUNNEL_GTPC &&
2174 tnl != RTE_PTYPE_TUNNEL_GTPU &&
2175 tnl != RTE_PTYPE_TUNNEL_L2TP &&
2176 tnl != RTE_PTYPE_TUNNEL_ESP)
2180 il2 != RTE_PTYPE_INNER_L2_ETHER &&
2181 il2 != RTE_PTYPE_INNER_L2_ETHER_VLAN &&
2182 il2 != RTE_PTYPE_INNER_L2_ETHER_QINQ)
2186 il3 != RTE_PTYPE_INNER_L3_IPV4 &&
2187 il3 != RTE_PTYPE_INNER_L3_IPV4_EXT &&
2188 il3 != RTE_PTYPE_INNER_L3_IPV6 &&
2189 il3 != RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN &&
2190 il3 != RTE_PTYPE_INNER_L3_IPV6_EXT &&
2191 il3 != RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN)
2195 il4 != RTE_PTYPE_INNER_L4_TCP &&
2196 il4 != RTE_PTYPE_INNER_L4_UDP &&
2197 il4 != RTE_PTYPE_INNER_L4_FRAG &&
2198 il4 != RTE_PTYPE_INNER_L4_SCTP &&
2199 il4 != RTE_PTYPE_INNER_L4_ICMP &&
2200 il4 != RTE_PTYPE_INNER_L4_NONFRAG)
2206 static int check_invalid_ptype_mapping(
2207 struct rte_pmd_i40e_ptype_mapping *mapping_table,
2212 for (i = 0; i < count; i++) {
2213 uint16_t ptype = mapping_table[i].hw_ptype;
2214 uint32_t pkt_type = mapping_table[i].sw_ptype;
2216 if (ptype >= I40E_MAX_PKT_TYPE)
2219 if (pkt_type == RTE_PTYPE_UNKNOWN)
2222 if (pkt_type & RTE_PMD_I40E_PTYPE_USER_DEFINE_MASK)
2225 if (check_invalid_pkt_type(pkt_type))
2233 rte_pmd_i40e_ptype_mapping_update(
2235 struct rte_pmd_i40e_ptype_mapping *mapping_items,
2239 struct rte_eth_dev *dev;
2240 struct i40e_adapter *ad;
2243 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
2245 dev = &rte_eth_devices[port];
2247 if (!is_i40e_supported(dev))
2250 if (count > I40E_MAX_PKT_TYPE)
2253 if (check_invalid_ptype_mapping(mapping_items, count))
2256 ad = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2259 for (i = 0; i < I40E_MAX_PKT_TYPE; i++)
2260 ad->ptype_tbl[i] = RTE_PTYPE_UNKNOWN;
2263 for (i = 0; i < count; i++)
2264 ad->ptype_tbl[mapping_items[i].hw_ptype]
2265 = mapping_items[i].sw_ptype;
2270 int rte_pmd_i40e_ptype_mapping_reset(uint16_t port)
2272 struct rte_eth_dev *dev;
2274 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
2276 dev = &rte_eth_devices[port];
2278 if (!is_i40e_supported(dev))
2281 i40e_set_default_ptype_table(dev);
2286 int rte_pmd_i40e_ptype_mapping_get(
2288 struct rte_pmd_i40e_ptype_mapping *mapping_items,
2293 struct rte_eth_dev *dev;
2294 struct i40e_adapter *ad;
2298 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
2300 dev = &rte_eth_devices[port];
2302 if (!is_i40e_supported(dev))
2305 ad = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2307 for (i = 0; i < I40E_MAX_PKT_TYPE; i++) {
2310 if (valid_only && ad->ptype_tbl[i] == RTE_PTYPE_UNKNOWN)
2312 mapping_items[n].hw_ptype = i;
2313 mapping_items[n].sw_ptype = ad->ptype_tbl[i];
2321 int rte_pmd_i40e_ptype_mapping_replace(uint16_t port,
2326 struct rte_eth_dev *dev;
2327 struct i40e_adapter *ad;
2330 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
2332 dev = &rte_eth_devices[port];
2334 if (!is_i40e_supported(dev))
2337 if (!mask && check_invalid_pkt_type(target))
2340 if (check_invalid_pkt_type(pkt_type))
2343 ad = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2345 for (i = 0; i < I40E_MAX_PKT_TYPE; i++) {
2347 if ((target | ad->ptype_tbl[i]) == target &&
2348 (target & ad->ptype_tbl[i]))
2349 ad->ptype_tbl[i] = pkt_type;
2351 if (ad->ptype_tbl[i] == target)
2352 ad->ptype_tbl[i] = pkt_type;
2360 rte_pmd_i40e_add_vf_mac_addr(uint16_t port, uint16_t vf_id,
2361 struct rte_ether_addr *mac_addr)
2363 struct rte_eth_dev *dev;
2364 struct i40e_pf_vf *vf;
2365 struct i40e_vsi *vsi;
2367 struct i40e_mac_filter_info mac_filter;
2370 if (i40e_validate_mac_addr((u8 *)mac_addr) != I40E_SUCCESS)
2373 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
2375 dev = &rte_eth_devices[port];
2377 if (!is_i40e_supported(dev))
2380 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2382 if (vf_id >= pf->vf_num || !pf->vfs)
2385 vf = &pf->vfs[vf_id];
2388 PMD_DRV_LOG(ERR, "Invalid VSI.");
2392 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2393 rte_ether_addr_copy(mac_addr, &mac_filter.mac_addr);
2394 ret = i40e_vsi_add_mac(vsi, &mac_filter);
2395 if (ret != I40E_SUCCESS) {
2396 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
2403 int rte_pmd_i40e_flow_type_mapping_reset(uint16_t port)
2405 struct rte_eth_dev *dev;
2407 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
2409 dev = &rte_eth_devices[port];
2411 if (!is_i40e_supported(dev) &&
2412 !is_i40evf_supported(dev))
2415 i40e_set_default_pctype_table(dev);
2420 int rte_pmd_i40e_flow_type_mapping_get(
2422 struct rte_pmd_i40e_flow_type_mapping *mapping_items)
2424 struct rte_eth_dev *dev;
2425 struct i40e_adapter *ad;
2428 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
2430 dev = &rte_eth_devices[port];
2432 if (!is_i40e_supported(dev) &&
2433 !is_i40evf_supported(dev))
2436 ad = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2438 for (i = 0; i < I40E_FLOW_TYPE_MAX; i++) {
2439 mapping_items[i].flow_type = i;
2440 mapping_items[i].pctype = ad->pctypes_tbl[i];
2447 rte_pmd_i40e_flow_type_mapping_update(
2449 struct rte_pmd_i40e_flow_type_mapping *mapping_items,
2453 struct rte_eth_dev *dev;
2454 struct i40e_adapter *ad;
2457 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
2459 dev = &rte_eth_devices[port];
2461 if (!is_i40e_supported(dev) &&
2462 !is_i40evf_supported(dev))
2465 if (count > I40E_FLOW_TYPE_MAX)
2468 for (i = 0; i < count; i++)
2469 if (mapping_items[i].flow_type >= I40E_FLOW_TYPE_MAX ||
2470 mapping_items[i].flow_type == RTE_ETH_FLOW_UNKNOWN ||
2471 (mapping_items[i].pctype &
2472 (1ULL << I40E_FILTER_PCTYPE_INVALID)))
2475 ad = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2478 for (i = 0; i < I40E_FLOW_TYPE_MAX; i++)
2479 ad->pctypes_tbl[i] = 0ULL;
2480 ad->flow_types_mask = 0ULL;
2483 for (i = 0; i < count; i++) {
2484 ad->pctypes_tbl[mapping_items[i].flow_type] =
2485 mapping_items[i].pctype;
2486 if (mapping_items[i].pctype)
2487 ad->flow_types_mask |=
2488 (1ULL << mapping_items[i].flow_type);
2490 ad->flow_types_mask &=
2491 ~(1ULL << mapping_items[i].flow_type);
2494 for (i = 0, ad->pctypes_mask = 0ULL; i < I40E_FLOW_TYPE_MAX; i++)
2495 ad->pctypes_mask |= ad->pctypes_tbl[i];
2501 rte_pmd_i40e_query_vfid_by_mac(uint16_t port,
2502 const struct rte_ether_addr *vf_mac)
2504 struct rte_eth_dev *dev;
2505 struct rte_ether_addr *mac;
2508 struct i40e_pf_vf *vf;
2511 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
2512 dev = &rte_eth_devices[port];
2514 if (!is_i40e_supported(dev))
2517 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2518 vf_num = pf->vf_num;
2520 for (vf_id = 0; vf_id < vf_num; vf_id++) {
2521 vf = &pf->vfs[vf_id];
2522 mac = &vf->mac_addr;
2524 if (rte_is_same_ether_addr(mac, vf_mac))
2532 i40e_vsi_update_queue_region_mapping(struct i40e_hw *hw,
2536 struct i40e_vsi *vsi = pf->main_vsi;
2537 uint16_t queue_offset, bsf, tc_index;
2538 struct i40e_vsi_context ctxt;
2539 struct i40e_aqc_vsi_properties_data *vsi_info;
2540 struct i40e_queue_regions *region_info =
2542 int32_t ret = -EINVAL;
2544 if (!region_info->queue_region_number) {
2545 PMD_INIT_LOG(ERR, "there is no that region id been set before");
2549 memset(&ctxt, 0, sizeof(struct i40e_vsi_context));
2551 /* Update Queue Pairs Mapping for currently enabled UPs */
2552 ctxt.seid = vsi->seid;
2553 ctxt.pf_num = hw->pf_id;
2555 ctxt.uplink_seid = vsi->uplink_seid;
2556 ctxt.info = vsi->info;
2557 vsi_info = &ctxt.info;
2559 memset(vsi_info->tc_mapping, 0, sizeof(uint16_t) * 8);
2560 memset(vsi_info->queue_mapping, 0, sizeof(uint16_t) * 16);
2562 /* Configure queue region and queue mapping parameters,
2563 * for enabled queue region, allocate queues to this region.
2566 for (i = 0; i < region_info->queue_region_number; i++) {
2567 tc_index = region_info->region[i].region_id;
2568 bsf = rte_bsf32(region_info->region[i].queue_num);
2569 queue_offset = region_info->region[i].queue_start_index;
2570 vsi_info->tc_mapping[tc_index] = rte_cpu_to_le_16(
2571 (queue_offset << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
2572 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
2575 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
2576 vsi_info->mapping_flags |=
2577 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
2578 vsi_info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
2579 vsi_info->valid_sections |=
2580 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
2582 /* Update the VSI after updating the VSI queue-mapping information */
2583 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2585 PMD_DRV_LOG(ERR, "Failed to configure queue region mapping = %d ",
2586 hw->aq.asq_last_status);
2589 /* update the local VSI info with updated queue map */
2590 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
2591 sizeof(vsi->info.tc_mapping));
2592 rte_memcpy(&vsi->info.queue_mapping,
2593 &ctxt.info.queue_mapping,
2594 sizeof(vsi->info.queue_mapping));
2595 vsi->info.mapping_flags = ctxt.info.mapping_flags;
2596 vsi->info.valid_sections = 0;
2603 i40e_queue_region_set_region(struct i40e_pf *pf,
2604 struct rte_pmd_i40e_queue_region_conf *conf_ptr)
2607 struct i40e_vsi *main_vsi = pf->main_vsi;
2608 struct i40e_queue_regions *info = &pf->queue_region;
2609 int32_t ret = -EINVAL;
2611 if (!((rte_is_power_of_2(conf_ptr->queue_num)) &&
2612 conf_ptr->queue_num <= 64)) {
2613 PMD_DRV_LOG(ERR, "The region sizes should be any of the following values: 1, 2, 4, 8, 16, 32, 64 as long as the "
2614 "total number of queues do not exceed the VSI allocation");
2618 if (conf_ptr->region_id > I40E_REGION_MAX_INDEX) {
2619 PMD_DRV_LOG(ERR, "the queue region max index is 7");
2623 if ((conf_ptr->queue_start_index + conf_ptr->queue_num)
2624 > main_vsi->nb_used_qps) {
2625 PMD_DRV_LOG(ERR, "the queue index exceeds the VSI range");
2629 for (i = 0; i < info->queue_region_number; i++)
2630 if (conf_ptr->region_id == info->region[i].region_id)
2633 if (i == info->queue_region_number &&
2634 i <= I40E_REGION_MAX_INDEX) {
2635 info->region[i].region_id = conf_ptr->region_id;
2636 info->region[i].queue_num = conf_ptr->queue_num;
2637 info->region[i].queue_start_index =
2638 conf_ptr->queue_start_index;
2639 info->queue_region_number++;
2641 PMD_DRV_LOG(ERR, "queue region number exceeds maxnum 8 or the queue region id has been set before");
2649 i40e_queue_region_set_flowtype(struct i40e_pf *pf,
2650 struct rte_pmd_i40e_queue_region_conf *rss_region_conf)
2652 int32_t ret = -EINVAL;
2653 struct i40e_queue_regions *info = &pf->queue_region;
2655 uint16_t region_index, flowtype_index;
2657 /* For the pctype or hardware flowtype of packet,
2658 * the specific index for each type has been defined
2659 * in file i40e_type.h as enum i40e_filter_pctype.
2662 if (rss_region_conf->region_id > I40E_PFQF_HREGION_MAX_INDEX) {
2663 PMD_DRV_LOG(ERR, "the queue region max index is 7");
2667 if (rss_region_conf->hw_flowtype >= I40E_FILTER_PCTYPE_MAX) {
2668 PMD_DRV_LOG(ERR, "the hw_flowtype or PCTYPE max index is 63");
2673 for (i = 0; i < info->queue_region_number; i++)
2674 if (rss_region_conf->region_id == info->region[i].region_id)
2677 if (i == info->queue_region_number) {
2678 PMD_DRV_LOG(ERR, "that region id has not been set before");
2684 for (i = 0; i < info->queue_region_number; i++) {
2685 for (j = 0; j < info->region[i].flowtype_num; j++) {
2686 if (rss_region_conf->hw_flowtype ==
2687 info->region[i].hw_flowtype[j]) {
2688 PMD_DRV_LOG(ERR, "that hw_flowtype has been set before");
2694 flowtype_index = info->region[region_index].flowtype_num;
2695 info->region[region_index].hw_flowtype[flowtype_index] =
2696 rss_region_conf->hw_flowtype;
2697 info->region[region_index].flowtype_num++;
2703 i40e_queue_region_pf_flowtype_conf(struct i40e_hw *hw,
2706 uint8_t hw_flowtype;
2707 uint32_t pfqf_hregion;
2708 uint16_t i, j, index;
2709 struct i40e_queue_regions *info = &pf->queue_region;
2711 /* For the pctype or hardware flowtype of packet,
2712 * the specific index for each type has been defined
2713 * in file i40e_type.h as enum i40e_filter_pctype.
2716 for (i = 0; i < info->queue_region_number; i++) {
2717 for (j = 0; j < info->region[i].flowtype_num; j++) {
2718 hw_flowtype = info->region[i].hw_flowtype[j];
2719 index = hw_flowtype >> 3;
2721 i40e_read_rx_ctl(hw, I40E_PFQF_HREGION(index));
2723 if ((hw_flowtype & 0x7) == 0) {
2724 pfqf_hregion |= info->region[i].region_id <<
2725 I40E_PFQF_HREGION_REGION_0_SHIFT;
2726 pfqf_hregion |= 1 <<
2727 I40E_PFQF_HREGION_OVERRIDE_ENA_0_SHIFT;
2728 } else if ((hw_flowtype & 0x7) == 1) {
2729 pfqf_hregion |= info->region[i].region_id <<
2730 I40E_PFQF_HREGION_REGION_1_SHIFT;
2731 pfqf_hregion |= 1 <<
2732 I40E_PFQF_HREGION_OVERRIDE_ENA_1_SHIFT;
2733 } else if ((hw_flowtype & 0x7) == 2) {
2734 pfqf_hregion |= info->region[i].region_id <<
2735 I40E_PFQF_HREGION_REGION_2_SHIFT;
2736 pfqf_hregion |= 1 <<
2737 I40E_PFQF_HREGION_OVERRIDE_ENA_2_SHIFT;
2738 } else if ((hw_flowtype & 0x7) == 3) {
2739 pfqf_hregion |= info->region[i].region_id <<
2740 I40E_PFQF_HREGION_REGION_3_SHIFT;
2741 pfqf_hregion |= 1 <<
2742 I40E_PFQF_HREGION_OVERRIDE_ENA_3_SHIFT;
2743 } else if ((hw_flowtype & 0x7) == 4) {
2744 pfqf_hregion |= info->region[i].region_id <<
2745 I40E_PFQF_HREGION_REGION_4_SHIFT;
2746 pfqf_hregion |= 1 <<
2747 I40E_PFQF_HREGION_OVERRIDE_ENA_4_SHIFT;
2748 } else if ((hw_flowtype & 0x7) == 5) {
2749 pfqf_hregion |= info->region[i].region_id <<
2750 I40E_PFQF_HREGION_REGION_5_SHIFT;
2751 pfqf_hregion |= 1 <<
2752 I40E_PFQF_HREGION_OVERRIDE_ENA_5_SHIFT;
2753 } else if ((hw_flowtype & 0x7) == 6) {
2754 pfqf_hregion |= info->region[i].region_id <<
2755 I40E_PFQF_HREGION_REGION_6_SHIFT;
2756 pfqf_hregion |= 1 <<
2757 I40E_PFQF_HREGION_OVERRIDE_ENA_6_SHIFT;
2759 pfqf_hregion |= info->region[i].region_id <<
2760 I40E_PFQF_HREGION_REGION_7_SHIFT;
2761 pfqf_hregion |= 1 <<
2762 I40E_PFQF_HREGION_OVERRIDE_ENA_7_SHIFT;
2765 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(index),
2772 i40e_queue_region_set_user_priority(struct i40e_pf *pf,
2773 struct rte_pmd_i40e_queue_region_conf *rss_region_conf)
2775 struct i40e_queue_regions *info = &pf->queue_region;
2776 int32_t ret = -EINVAL;
2777 uint16_t i, j, region_index;
2779 if (rss_region_conf->user_priority >= I40E_MAX_USER_PRIORITY) {
2780 PMD_DRV_LOG(ERR, "the queue region max index is 7");
2784 if (rss_region_conf->region_id > I40E_REGION_MAX_INDEX) {
2785 PMD_DRV_LOG(ERR, "the region_id max index is 7");
2789 for (i = 0; i < info->queue_region_number; i++)
2790 if (rss_region_conf->region_id == info->region[i].region_id)
2793 if (i == info->queue_region_number) {
2794 PMD_DRV_LOG(ERR, "that region id has not been set before");
2801 for (i = 0; i < info->queue_region_number; i++) {
2802 for (j = 0; j < info->region[i].user_priority_num; j++) {
2803 if (info->region[i].user_priority[j] ==
2804 rss_region_conf->user_priority) {
2805 PMD_DRV_LOG(ERR, "that user priority has been set before");
2811 j = info->region[region_index].user_priority_num;
2812 info->region[region_index].user_priority[j] =
2813 rss_region_conf->user_priority;
2814 info->region[region_index].user_priority_num++;
2820 i40e_queue_region_dcb_configure(struct i40e_hw *hw,
2823 struct i40e_dcbx_config dcb_cfg_local;
2824 struct i40e_dcbx_config *dcb_cfg;
2825 struct i40e_queue_regions *info = &pf->queue_region;
2826 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
2827 int32_t ret = -EINVAL;
2828 uint16_t i, j, prio_index, region_index;
2829 uint8_t tc_map, tc_bw, bw_lf, dcb_flag = 0;
2831 if (!info->queue_region_number) {
2832 PMD_DRV_LOG(ERR, "No queue region been set before");
2836 for (i = 0; i < info->queue_region_number; i++) {
2837 if (info->region[i].user_priority_num) {
2846 dcb_cfg = &dcb_cfg_local;
2847 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
2849 /* assume each tc has the same bw */
2850 tc_bw = I40E_MAX_PERCENT / info->queue_region_number;
2851 for (i = 0; i < info->queue_region_number; i++)
2852 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
2853 /* to ensure the sum of tcbw is equal to 100 */
2854 bw_lf = I40E_MAX_PERCENT % info->queue_region_number;
2855 for (i = 0; i < bw_lf; i++)
2856 dcb_cfg->etscfg.tcbwtable[i]++;
2858 /* assume each tc has the same Transmission Selection Algorithm */
2859 for (i = 0; i < info->queue_region_number; i++)
2860 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
2862 for (i = 0; i < info->queue_region_number; i++) {
2863 for (j = 0; j < info->region[i].user_priority_num; j++) {
2864 prio_index = info->region[i].user_priority[j];
2865 region_index = info->region[i].region_id;
2866 dcb_cfg->etscfg.prioritytable[prio_index] =
2871 /* FW needs one App to configure HW */
2872 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
2873 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
2874 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
2875 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
2877 tc_map = RTE_LEN2MASK(info->queue_region_number, uint8_t);
2879 dcb_cfg->pfc.willing = 0;
2880 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
2881 dcb_cfg->pfc.pfcenable = tc_map;
2883 /* Copy the new config to the current config */
2884 *old_cfg = *dcb_cfg;
2885 old_cfg->etsrec = old_cfg->etscfg;
2886 ret = i40e_set_dcb_config(hw);
2889 PMD_DRV_LOG(ERR, "Set queue region DCB Config failed, err %s aq_err %s",
2890 i40e_stat_str(hw, ret),
2891 i40e_aq_str(hw, hw->aq.asq_last_status));
2899 i40e_flush_queue_region_all_conf(struct rte_eth_dev *dev,
2900 struct i40e_hw *hw, struct i40e_pf *pf, uint16_t on)
2902 int32_t ret = -EINVAL;
2903 struct i40e_queue_regions *info = &pf->queue_region;
2904 struct i40e_vsi *main_vsi = pf->main_vsi;
2907 i40e_queue_region_pf_flowtype_conf(hw, pf);
2909 ret = i40e_vsi_update_queue_region_mapping(hw, pf);
2910 if (ret != I40E_SUCCESS) {
2911 PMD_DRV_LOG(INFO, "Failed to flush queue region mapping.");
2915 ret = i40e_queue_region_dcb_configure(hw, pf);
2916 if (ret != I40E_SUCCESS) {
2917 PMD_DRV_LOG(INFO, "Failed to flush dcb.");
2924 if (info->queue_region_number) {
2925 info->queue_region_number = 1;
2926 info->region[0].queue_num = main_vsi->nb_used_qps;
2927 info->region[0].queue_start_index = 0;
2929 ret = i40e_vsi_update_queue_region_mapping(hw, pf);
2930 if (ret != I40E_SUCCESS)
2931 PMD_DRV_LOG(INFO, "Failed to flush queue region mapping.");
2933 ret = i40e_dcb_init_configure(dev, TRUE);
2934 if (ret != I40E_SUCCESS) {
2935 PMD_DRV_LOG(INFO, "Failed to flush dcb.");
2936 pf->flags &= ~I40E_FLAG_DCB;
2939 i40e_init_queue_region_conf(dev);
2945 i40e_queue_region_pf_check_rss(struct i40e_pf *pf)
2947 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2950 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
2951 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
2960 i40e_queue_region_get_all_info(struct i40e_pf *pf,
2961 struct i40e_queue_regions *regions_ptr)
2963 struct i40e_queue_regions *info = &pf->queue_region;
2965 rte_memcpy(regions_ptr, info,
2966 sizeof(struct i40e_queue_regions));
2971 int rte_pmd_i40e_rss_queue_region_conf(uint16_t port_id,
2972 enum rte_pmd_i40e_queue_region_op op_type, void *arg)
2974 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
2975 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2976 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2979 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
2981 if (!is_i40e_supported(dev))
2984 if (!(!i40e_queue_region_pf_check_rss(pf)))
2987 /* This queue region feature only support pf by now. It should
2988 * be called after dev_start, and will be clear after dev_stop.
2989 * "RTE_PMD_I40E_RSS_QUEUE_REGION_ALL_FLUSH_ON"
2990 * is just an enable function which server for other configuration,
2991 * it is for all configuration about queue region from up layer,
2992 * at first will only keep in DPDK softwarestored in driver,
2993 * only after "FLUSH_ON", it commit all configuration to HW.
2994 * Because PMD had to set hardware configuration at a time, so
2995 * it will record all up layer command at first.
2996 * "RTE_PMD_I40E_RSS_QUEUE_REGION_ALL_FLUSH_OFF" is
2997 * just clean all configuration about queue region just now,
2998 * and restore all to DPDK i40e driver default
2999 * config when start up.
3003 case RTE_PMD_I40E_RSS_QUEUE_REGION_SET:
3004 ret = i40e_queue_region_set_region(pf,
3005 (struct rte_pmd_i40e_queue_region_conf *)arg);
3007 case RTE_PMD_I40E_RSS_QUEUE_REGION_FLOWTYPE_SET:
3008 ret = i40e_queue_region_set_flowtype(pf,
3009 (struct rte_pmd_i40e_queue_region_conf *)arg);
3011 case RTE_PMD_I40E_RSS_QUEUE_REGION_USER_PRIORITY_SET:
3012 ret = i40e_queue_region_set_user_priority(pf,
3013 (struct rte_pmd_i40e_queue_region_conf *)arg);
3015 case RTE_PMD_I40E_RSS_QUEUE_REGION_ALL_FLUSH_ON:
3016 ret = i40e_flush_queue_region_all_conf(dev, hw, pf, 1);
3018 case RTE_PMD_I40E_RSS_QUEUE_REGION_ALL_FLUSH_OFF:
3019 ret = i40e_flush_queue_region_all_conf(dev, hw, pf, 0);
3021 case RTE_PMD_I40E_RSS_QUEUE_REGION_INFO_GET:
3022 ret = i40e_queue_region_get_all_info(pf,
3023 (struct i40e_queue_regions *)arg);
3026 PMD_DRV_LOG(WARNING, "op type (%d) not supported",
3031 I40E_WRITE_FLUSH(hw);
3036 int rte_pmd_i40e_flow_add_del_packet_template(
3038 const struct rte_pmd_i40e_pkt_template_conf *conf,
3041 struct rte_eth_dev *dev = &rte_eth_devices[port];
3042 struct i40e_fdir_filter_conf filter_conf;
3044 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
3046 if (!is_i40e_supported(dev))
3049 memset(&filter_conf, 0, sizeof(filter_conf));
3050 filter_conf.soft_id = conf->soft_id;
3051 filter_conf.input.flow.raw_flow.pctype = conf->input.pctype;
3052 filter_conf.input.flow.raw_flow.packet = conf->input.packet;
3053 filter_conf.input.flow.raw_flow.length = conf->input.length;
3054 filter_conf.input.flow_ext.pkt_template = true;
3056 filter_conf.action.rx_queue = conf->action.rx_queue;
3057 filter_conf.action.behavior =
3058 (enum i40e_fdir_behavior)conf->action.behavior;
3059 filter_conf.action.report_status =
3060 (enum i40e_fdir_status)conf->action.report_status;
3061 filter_conf.action.flex_off = conf->action.flex_off;
3063 return i40e_flow_add_del_fdir_filter(dev, &filter_conf, add);
3067 rte_pmd_i40e_inset_get(uint16_t port, uint8_t pctype,
3068 struct rte_pmd_i40e_inset *inset,
3069 enum rte_pmd_i40e_inset_type inset_type)
3071 struct rte_eth_dev *dev;
3074 uint32_t mask_reg[2];
3077 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
3079 dev = &rte_eth_devices[port];
3081 if (!is_i40e_supported(dev))
3087 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3088 memset(inset, 0, sizeof(struct rte_pmd_i40e_inset));
3090 switch (inset_type) {
3094 i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
3095 inset_reg <<= I40E_32_BIT_WIDTH;
3097 i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
3098 /* Get field mask */
3100 i40e_read_rx_ctl(hw, I40E_GLQF_HASH_MSK(0, pctype));
3102 i40e_read_rx_ctl(hw, I40E_GLQF_HASH_MSK(1, pctype));
3106 i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
3107 inset_reg <<= I40E_32_BIT_WIDTH;
3109 i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
3111 i40e_read_rx_ctl(hw, I40E_GLQF_FD_MSK(0, pctype));
3113 i40e_read_rx_ctl(hw, I40E_GLQF_FD_MSK(1, pctype));
3115 case INSET_FDIR_FLX:
3117 i40e_read_rx_ctl(hw, I40E_PRTQF_FD_FLXINSET(pctype));
3119 i40e_read_rx_ctl(hw, I40E_PRTQF_FD_MSK(pctype, 0));
3121 i40e_read_rx_ctl(hw, I40E_PRTQF_FD_MSK(pctype, 1));
3124 PMD_DRV_LOG(ERR, "Unsupported input set type.");
3128 inset->inset = inset_reg;
3130 for (i = 0; i < 2; i++) {
3131 inset->mask[i].field_idx = ((mask_reg[i] >> 16) & 0x3F);
3132 inset->mask[i].mask = mask_reg[i] & 0xFFFF;
3139 rte_pmd_i40e_inset_set(uint16_t port, uint8_t pctype,
3140 struct rte_pmd_i40e_inset *inset,
3141 enum rte_pmd_i40e_inset_type inset_type)
3143 struct rte_eth_dev *dev;
3147 uint32_t mask_reg[2];
3150 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
3152 dev = &rte_eth_devices[port];
3154 if (!is_i40e_supported(dev))
3160 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3161 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3163 if (pf->support_multi_driver) {
3164 PMD_DRV_LOG(ERR, "Input set configuration is not supported.");
3168 inset_reg = inset->inset;
3169 for (i = 0; i < 2; i++)
3170 mask_reg[i] = (inset->mask[i].field_idx << 16) |
3171 inset->mask[i].mask;
3173 switch (inset_type) {
3175 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
3176 (uint32_t)(inset_reg & UINT32_MAX));
3177 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
3178 (uint32_t)((inset_reg >>
3179 I40E_32_BIT_WIDTH) & UINT32_MAX));
3180 for (i = 0; i < 2; i++)
3181 i40e_check_write_global_reg(hw,
3182 I40E_GLQF_HASH_MSK(i, pctype),
3186 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
3187 (uint32_t)(inset_reg & UINT32_MAX));
3188 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
3189 (uint32_t)((inset_reg >>
3190 I40E_32_BIT_WIDTH) & UINT32_MAX));
3191 for (i = 0; i < 2; i++)
3192 i40e_check_write_global_reg(hw,
3193 I40E_GLQF_FD_MSK(i, pctype),
3196 case INSET_FDIR_FLX:
3197 i40e_check_write_reg(hw, I40E_PRTQF_FD_FLXINSET(pctype),
3198 (uint32_t)(inset_reg & UINT32_MAX));
3199 for (i = 0; i < 2; i++)
3200 i40e_check_write_reg(hw, I40E_PRTQF_FD_MSK(pctype, i),
3204 PMD_DRV_LOG(ERR, "Unsupported input set type.");
3208 I40E_WRITE_FLUSH(hw);
3213 rte_pmd_i40e_set_switch_dev(uint16_t port_id, struct rte_eth_dev *switch_dev)
3215 struct rte_eth_dev *i40e_dev;
3218 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3220 i40e_dev = &rte_eth_devices[port_id];
3221 if (!is_i40e_supported(i40e_dev))
3224 hw = I40E_DEV_PRIVATE_TO_HW(i40e_dev->data->dev_private);
3228 hw->switch_dev = switch_dev;