1 /*******************************************************************************
3 Copyright (c) 2013 - 2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #ifndef _IAVF_ADMINQ_CMD_H_
35 #define _IAVF_ADMINQ_CMD_H_
37 /* This header file defines the iavf Admin Queue commands and is shared between
38 * iavf Firmware and Software.
40 * This file needs to comply with the Linux Kernel coding style.
44 #define IAVF_FW_API_VERSION_MAJOR 0x0001
45 #define IAVF_FW_API_VERSION_MINOR_X722 0x0005
46 #define IAVF_FW_API_VERSION_MINOR_X710 0x0007
48 #define IAVF_FW_MINOR_VERSION(_h) ((_h)->mac.type == IAVF_MAC_XL710 ? \
49 IAVF_FW_API_VERSION_MINOR_X710 : \
50 IAVF_FW_API_VERSION_MINOR_X722)
52 /* API version 1.7 implements additional link and PHY-specific APIs */
53 #define IAVF_MINOR_VER_GET_LINK_INFO_XL710 0x0007
79 /* Flags sub-structure
80 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 |
81 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE |
84 /* command flags and offsets*/
85 #define IAVF_AQ_FLAG_DD_SHIFT 0
86 #define IAVF_AQ_FLAG_CMP_SHIFT 1
87 #define IAVF_AQ_FLAG_ERR_SHIFT 2
88 #define IAVF_AQ_FLAG_VFE_SHIFT 3
89 #define IAVF_AQ_FLAG_LB_SHIFT 9
90 #define IAVF_AQ_FLAG_RD_SHIFT 10
91 #define IAVF_AQ_FLAG_VFC_SHIFT 11
92 #define IAVF_AQ_FLAG_BUF_SHIFT 12
93 #define IAVF_AQ_FLAG_SI_SHIFT 13
94 #define IAVF_AQ_FLAG_EI_SHIFT 14
95 #define IAVF_AQ_FLAG_FE_SHIFT 15
97 #define IAVF_AQ_FLAG_DD (1 << IAVF_AQ_FLAG_DD_SHIFT) /* 0x1 */
98 #define IAVF_AQ_FLAG_CMP (1 << IAVF_AQ_FLAG_CMP_SHIFT) /* 0x2 */
99 #define IAVF_AQ_FLAG_ERR (1 << IAVF_AQ_FLAG_ERR_SHIFT) /* 0x4 */
100 #define IAVF_AQ_FLAG_VFE (1 << IAVF_AQ_FLAG_VFE_SHIFT) /* 0x8 */
101 #define IAVF_AQ_FLAG_LB (1 << IAVF_AQ_FLAG_LB_SHIFT) /* 0x200 */
102 #define IAVF_AQ_FLAG_RD (1 << IAVF_AQ_FLAG_RD_SHIFT) /* 0x400 */
103 #define IAVF_AQ_FLAG_VFC (1 << IAVF_AQ_FLAG_VFC_SHIFT) /* 0x800 */
104 #define IAVF_AQ_FLAG_BUF (1 << IAVF_AQ_FLAG_BUF_SHIFT) /* 0x1000 */
105 #define IAVF_AQ_FLAG_SI (1 << IAVF_AQ_FLAG_SI_SHIFT) /* 0x2000 */
106 #define IAVF_AQ_FLAG_EI (1 << IAVF_AQ_FLAG_EI_SHIFT) /* 0x4000 */
107 #define IAVF_AQ_FLAG_FE (1 << IAVF_AQ_FLAG_FE_SHIFT) /* 0x8000 */
110 enum iavf_admin_queue_err {
111 IAVF_AQ_RC_OK = 0, /* success */
112 IAVF_AQ_RC_EPERM = 1, /* Operation not permitted */
113 IAVF_AQ_RC_ENOENT = 2, /* No such element */
114 IAVF_AQ_RC_ESRCH = 3, /* Bad opcode */
115 IAVF_AQ_RC_EINTR = 4, /* operation interrupted */
116 IAVF_AQ_RC_EIO = 5, /* I/O error */
117 IAVF_AQ_RC_ENXIO = 6, /* No such resource */
118 IAVF_AQ_RC_E2BIG = 7, /* Arg too long */
119 IAVF_AQ_RC_EAGAIN = 8, /* Try again */
120 IAVF_AQ_RC_ENOMEM = 9, /* Out of memory */
121 IAVF_AQ_RC_EACCES = 10, /* Permission denied */
122 IAVF_AQ_RC_EFAULT = 11, /* Bad address */
123 IAVF_AQ_RC_EBUSY = 12, /* Device or resource busy */
124 IAVF_AQ_RC_EEXIST = 13, /* object already exists */
125 IAVF_AQ_RC_EINVAL = 14, /* Invalid argument */
126 IAVF_AQ_RC_ENOTTY = 15, /* Not a typewriter */
127 IAVF_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */
128 IAVF_AQ_RC_ENOSYS = 17, /* Function not implemented */
129 IAVF_AQ_RC_ERANGE = 18, /* Parameter out of range */
130 IAVF_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */
131 IAVF_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */
132 IAVF_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */
133 IAVF_AQ_RC_EFBIG = 22, /* File too large */
136 /* Admin Queue command opcodes */
137 enum iavf_admin_queue_opc {
139 iavf_aqc_opc_get_version = 0x0001,
140 iavf_aqc_opc_driver_version = 0x0002,
141 iavf_aqc_opc_queue_shutdown = 0x0003,
142 iavf_aqc_opc_set_pf_context = 0x0004,
144 /* resource ownership */
145 iavf_aqc_opc_request_resource = 0x0008,
146 iavf_aqc_opc_release_resource = 0x0009,
148 iavf_aqc_opc_list_func_capabilities = 0x000A,
149 iavf_aqc_opc_list_dev_capabilities = 0x000B,
152 iavf_aqc_opc_set_proxy_config = 0x0104,
153 iavf_aqc_opc_set_ns_proxy_table_entry = 0x0105,
156 iavf_aqc_opc_mac_address_read = 0x0107,
157 iavf_aqc_opc_mac_address_write = 0x0108,
160 iavf_aqc_opc_clear_pxe_mode = 0x0110,
163 iavf_aqc_opc_set_wol_filter = 0x0120,
164 iavf_aqc_opc_get_wake_reason = 0x0121,
165 iavf_aqc_opc_clear_all_wol_filters = 0x025E,
167 /* internal switch commands */
168 iavf_aqc_opc_get_switch_config = 0x0200,
169 iavf_aqc_opc_add_statistics = 0x0201,
170 iavf_aqc_opc_remove_statistics = 0x0202,
171 iavf_aqc_opc_set_port_parameters = 0x0203,
172 iavf_aqc_opc_get_switch_resource_alloc = 0x0204,
173 iavf_aqc_opc_set_switch_config = 0x0205,
174 iavf_aqc_opc_rx_ctl_reg_read = 0x0206,
175 iavf_aqc_opc_rx_ctl_reg_write = 0x0207,
177 iavf_aqc_opc_add_vsi = 0x0210,
178 iavf_aqc_opc_update_vsi_parameters = 0x0211,
179 iavf_aqc_opc_get_vsi_parameters = 0x0212,
181 iavf_aqc_opc_add_pv = 0x0220,
182 iavf_aqc_opc_update_pv_parameters = 0x0221,
183 iavf_aqc_opc_get_pv_parameters = 0x0222,
185 iavf_aqc_opc_add_veb = 0x0230,
186 iavf_aqc_opc_update_veb_parameters = 0x0231,
187 iavf_aqc_opc_get_veb_parameters = 0x0232,
189 iavf_aqc_opc_delete_element = 0x0243,
191 iavf_aqc_opc_add_macvlan = 0x0250,
192 iavf_aqc_opc_remove_macvlan = 0x0251,
193 iavf_aqc_opc_add_vlan = 0x0252,
194 iavf_aqc_opc_remove_vlan = 0x0253,
195 iavf_aqc_opc_set_vsi_promiscuous_modes = 0x0254,
196 iavf_aqc_opc_add_tag = 0x0255,
197 iavf_aqc_opc_remove_tag = 0x0256,
198 iavf_aqc_opc_add_multicast_etag = 0x0257,
199 iavf_aqc_opc_remove_multicast_etag = 0x0258,
200 iavf_aqc_opc_update_tag = 0x0259,
201 iavf_aqc_opc_add_control_packet_filter = 0x025A,
202 iavf_aqc_opc_remove_control_packet_filter = 0x025B,
203 iavf_aqc_opc_add_cloud_filters = 0x025C,
204 iavf_aqc_opc_remove_cloud_filters = 0x025D,
205 iavf_aqc_opc_clear_wol_switch_filters = 0x025E,
206 iavf_aqc_opc_replace_cloud_filters = 0x025F,
208 iavf_aqc_opc_add_mirror_rule = 0x0260,
209 iavf_aqc_opc_delete_mirror_rule = 0x0261,
211 /* Dynamic Device Personalization */
212 iavf_aqc_opc_write_personalization_profile = 0x0270,
213 iavf_aqc_opc_get_personalization_profile_list = 0x0271,
216 iavf_aqc_opc_dcb_ignore_pfc = 0x0301,
217 iavf_aqc_opc_dcb_updated = 0x0302,
218 iavf_aqc_opc_set_dcb_parameters = 0x0303,
221 iavf_aqc_opc_configure_vsi_bw_limit = 0x0400,
222 iavf_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406,
223 iavf_aqc_opc_configure_vsi_tc_bw = 0x0407,
224 iavf_aqc_opc_query_vsi_bw_config = 0x0408,
225 iavf_aqc_opc_query_vsi_ets_sla_config = 0x040A,
226 iavf_aqc_opc_configure_switching_comp_bw_limit = 0x0410,
228 iavf_aqc_opc_enable_switching_comp_ets = 0x0413,
229 iavf_aqc_opc_modify_switching_comp_ets = 0x0414,
230 iavf_aqc_opc_disable_switching_comp_ets = 0x0415,
231 iavf_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416,
232 iavf_aqc_opc_configure_switching_comp_bw_config = 0x0417,
233 iavf_aqc_opc_query_switching_comp_ets_config = 0x0418,
234 iavf_aqc_opc_query_port_ets_config = 0x0419,
235 iavf_aqc_opc_query_switching_comp_bw_config = 0x041A,
236 iavf_aqc_opc_suspend_port_tx = 0x041B,
237 iavf_aqc_opc_resume_port_tx = 0x041C,
238 iavf_aqc_opc_configure_partition_bw = 0x041D,
240 iavf_aqc_opc_query_hmc_resource_profile = 0x0500,
241 iavf_aqc_opc_set_hmc_resource_profile = 0x0501,
246 iavf_aqc_opc_get_phy_abilities = 0x0600,
247 iavf_aqc_opc_set_phy_config = 0x0601,
248 iavf_aqc_opc_set_mac_config = 0x0603,
249 iavf_aqc_opc_set_link_restart_an = 0x0605,
250 iavf_aqc_opc_get_link_status = 0x0607,
251 iavf_aqc_opc_set_phy_int_mask = 0x0613,
252 iavf_aqc_opc_get_local_advt_reg = 0x0614,
253 iavf_aqc_opc_set_local_advt_reg = 0x0615,
254 iavf_aqc_opc_get_partner_advt = 0x0616,
255 iavf_aqc_opc_set_lb_modes = 0x0618,
256 iavf_aqc_opc_get_phy_wol_caps = 0x0621,
257 iavf_aqc_opc_set_phy_debug = 0x0622,
258 iavf_aqc_opc_upload_ext_phy_fm = 0x0625,
259 iavf_aqc_opc_run_phy_activity = 0x0626,
260 iavf_aqc_opc_set_phy_register = 0x0628,
261 iavf_aqc_opc_get_phy_register = 0x0629,
264 iavf_aqc_opc_nvm_read = 0x0701,
265 iavf_aqc_opc_nvm_erase = 0x0702,
266 iavf_aqc_opc_nvm_update = 0x0703,
267 iavf_aqc_opc_nvm_config_read = 0x0704,
268 iavf_aqc_opc_nvm_config_write = 0x0705,
269 iavf_aqc_opc_nvm_progress = 0x0706,
270 iavf_aqc_opc_oem_post_update = 0x0720,
271 iavf_aqc_opc_thermal_sensor = 0x0721,
273 /* virtualization commands */
274 iavf_aqc_opc_send_msg_to_pf = 0x0801,
275 iavf_aqc_opc_send_msg_to_vf = 0x0802,
276 iavf_aqc_opc_send_msg_to_peer = 0x0803,
278 /* alternate structure */
279 iavf_aqc_opc_alternate_write = 0x0900,
280 iavf_aqc_opc_alternate_write_indirect = 0x0901,
281 iavf_aqc_opc_alternate_read = 0x0902,
282 iavf_aqc_opc_alternate_read_indirect = 0x0903,
283 iavf_aqc_opc_alternate_write_done = 0x0904,
284 iavf_aqc_opc_alternate_set_mode = 0x0905,
285 iavf_aqc_opc_alternate_clear_port = 0x0906,
288 iavf_aqc_opc_lldp_get_mib = 0x0A00,
289 iavf_aqc_opc_lldp_update_mib = 0x0A01,
290 iavf_aqc_opc_lldp_add_tlv = 0x0A02,
291 iavf_aqc_opc_lldp_update_tlv = 0x0A03,
292 iavf_aqc_opc_lldp_delete_tlv = 0x0A04,
293 iavf_aqc_opc_lldp_stop = 0x0A05,
294 iavf_aqc_opc_lldp_start = 0x0A06,
295 iavf_aqc_opc_get_cee_dcb_cfg = 0x0A07,
296 iavf_aqc_opc_lldp_set_local_mib = 0x0A08,
297 iavf_aqc_opc_lldp_stop_start_spec_agent = 0x0A09,
299 /* Tunnel commands */
300 iavf_aqc_opc_add_udp_tunnel = 0x0B00,
301 iavf_aqc_opc_del_udp_tunnel = 0x0B01,
302 iavf_aqc_opc_set_rss_key = 0x0B02,
303 iavf_aqc_opc_set_rss_lut = 0x0B03,
304 iavf_aqc_opc_get_rss_key = 0x0B04,
305 iavf_aqc_opc_get_rss_lut = 0x0B05,
308 iavf_aqc_opc_event_lan_overflow = 0x1001,
311 iavf_aqc_opc_oem_parameter_change = 0xFE00,
312 iavf_aqc_opc_oem_device_status_change = 0xFE01,
313 iavf_aqc_opc_oem_ocsd_initialize = 0xFE02,
314 iavf_aqc_opc_oem_ocbb_initialize = 0xFE03,
317 iavf_aqc_opc_debug_read_reg = 0xFF03,
318 iavf_aqc_opc_debug_write_reg = 0xFF04,
319 iavf_aqc_opc_debug_modify_reg = 0xFF07,
320 iavf_aqc_opc_debug_dump_internals = 0xFF08,
323 /* command structures and indirect data structures */
325 /* Structure naming conventions:
326 * - no suffix for direct command descriptor structures
327 * - _data for indirect sent data
328 * - _resp for indirect return data (data which is both will use _data)
329 * - _completion for direct return data
330 * - _element_ for repeated elements (may also be _data or _resp)
332 * Command structures are expected to overlay the params.raw member of the basic
333 * descriptor, and as such cannot exceed 16 bytes in length.
336 /* This macro is used to generate a compilation error if a structure
337 * is not exactly the correct length. It gives a divide by zero error if the
338 * structure is not of the correct size, otherwise it creates an enum that is
341 #define IAVF_CHECK_STRUCT_LEN(n, X) enum iavf_static_assert_enum_##X \
342 { iavf_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) }
344 /* This macro is used extensively to ensure that command structures are 16
345 * bytes in length as they have to map to the raw array of that size.
347 #define IAVF_CHECK_CMD_LENGTH(X) IAVF_CHECK_STRUCT_LEN(16, X)
349 /* internal (0x00XX) commands */
351 /* Get version (direct 0x0001) */
352 struct iavf_aqc_get_version {
361 IAVF_CHECK_CMD_LENGTH(iavf_aqc_get_version);
363 /* Send driver version (indirect 0x0002) */
364 struct iavf_aqc_driver_version {
368 u8 driver_subbuild_ver;
374 IAVF_CHECK_CMD_LENGTH(iavf_aqc_driver_version);
376 /* Queue Shutdown (direct 0x0003) */
377 struct iavf_aqc_queue_shutdown {
378 __le32 driver_unloading;
379 #define IAVF_AQ_DRIVER_UNLOADING 0x1
383 IAVF_CHECK_CMD_LENGTH(iavf_aqc_queue_shutdown);
385 /* Set PF context (0x0004, direct) */
386 struct iavf_aqc_set_pf_context {
391 IAVF_CHECK_CMD_LENGTH(iavf_aqc_set_pf_context);
393 /* Request resource ownership (direct 0x0008)
394 * Release resource ownership (direct 0x0009)
396 #define IAVF_AQ_RESOURCE_NVM 1
397 #define IAVF_AQ_RESOURCE_SDP 2
398 #define IAVF_AQ_RESOURCE_ACCESS_READ 1
399 #define IAVF_AQ_RESOURCE_ACCESS_WRITE 2
400 #define IAVF_AQ_RESOURCE_NVM_READ_TIMEOUT 3000
401 #define IAVF_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000
403 struct iavf_aqc_request_resource {
407 __le32 resource_number;
411 IAVF_CHECK_CMD_LENGTH(iavf_aqc_request_resource);
413 /* Get function capabilities (indirect 0x000A)
414 * Get device capabilities (indirect 0x000B)
416 struct iavf_aqc_list_capabilites {
418 #define IAVF_AQ_LIST_CAP_PF_INDEX_EN 1
426 IAVF_CHECK_CMD_LENGTH(iavf_aqc_list_capabilites);
428 struct iavf_aqc_list_capabilities_element_resp {
440 #define IAVF_AQ_CAP_ID_SWITCH_MODE 0x0001
441 #define IAVF_AQ_CAP_ID_MNG_MODE 0x0002
442 #define IAVF_AQ_CAP_ID_NPAR_ACTIVE 0x0003
443 #define IAVF_AQ_CAP_ID_OS2BMC_CAP 0x0004
444 #define IAVF_AQ_CAP_ID_FUNCTIONS_VALID 0x0005
445 #define IAVF_AQ_CAP_ID_ALTERNATE_RAM 0x0006
446 #define IAVF_AQ_CAP_ID_WOL_AND_PROXY 0x0008
447 #define IAVF_AQ_CAP_ID_SRIOV 0x0012
448 #define IAVF_AQ_CAP_ID_VF 0x0013
449 #define IAVF_AQ_CAP_ID_VMDQ 0x0014
450 #define IAVF_AQ_CAP_ID_8021QBG 0x0015
451 #define IAVF_AQ_CAP_ID_8021QBR 0x0016
452 #define IAVF_AQ_CAP_ID_VSI 0x0017
453 #define IAVF_AQ_CAP_ID_DCB 0x0018
454 #define IAVF_AQ_CAP_ID_FCOE 0x0021
455 #define IAVF_AQ_CAP_ID_ISCSI 0x0022
456 #define IAVF_AQ_CAP_ID_RSS 0x0040
457 #define IAVF_AQ_CAP_ID_RXQ 0x0041
458 #define IAVF_AQ_CAP_ID_TXQ 0x0042
459 #define IAVF_AQ_CAP_ID_MSIX 0x0043
460 #define IAVF_AQ_CAP_ID_VF_MSIX 0x0044
461 #define IAVF_AQ_CAP_ID_FLOW_DIRECTOR 0x0045
462 #define IAVF_AQ_CAP_ID_1588 0x0046
463 #define IAVF_AQ_CAP_ID_IWARP 0x0051
464 #define IAVF_AQ_CAP_ID_LED 0x0061
465 #define IAVF_AQ_CAP_ID_SDP 0x0062
466 #define IAVF_AQ_CAP_ID_MDIO 0x0063
467 #define IAVF_AQ_CAP_ID_WSR_PROT 0x0064
468 #define IAVF_AQ_CAP_ID_NVM_MGMT 0x0080
469 #define IAVF_AQ_CAP_ID_FLEX10 0x00F1
470 #define IAVF_AQ_CAP_ID_CEM 0x00F2
472 /* Set CPPM Configuration (direct 0x0103) */
473 struct iavf_aqc_cppm_configuration {
474 __le16 command_flags;
475 #define IAVF_AQ_CPPM_EN_LTRC 0x0800
476 #define IAVF_AQ_CPPM_EN_DMCTH 0x1000
477 #define IAVF_AQ_CPPM_EN_DMCTLX 0x2000
478 #define IAVF_AQ_CPPM_EN_HPTC 0x4000
479 #define IAVF_AQ_CPPM_EN_DMARC 0x8000
488 IAVF_CHECK_CMD_LENGTH(iavf_aqc_cppm_configuration);
490 /* Set ARP Proxy command / response (indirect 0x0104) */
491 struct iavf_aqc_arp_proxy_data {
492 __le16 command_flags;
493 #define IAVF_AQ_ARP_INIT_IPV4 0x0800
494 #define IAVF_AQ_ARP_UNSUP_CTL 0x1000
495 #define IAVF_AQ_ARP_ENA 0x2000
496 #define IAVF_AQ_ARP_ADD_IPV4 0x4000
497 #define IAVF_AQ_ARP_DEL_IPV4 0x8000
499 __le32 enabled_offloads;
500 #define IAVF_AQ_ARP_DIRECTED_OFFLOAD_ENABLE 0x00000020
501 #define IAVF_AQ_ARP_OFFLOAD_ENABLE 0x00000800
507 IAVF_CHECK_STRUCT_LEN(0x14, iavf_aqc_arp_proxy_data);
509 /* Set NS Proxy Table Entry Command (indirect 0x0105) */
510 struct iavf_aqc_ns_proxy_data {
511 __le16 table_idx_mac_addr_0;
512 __le16 table_idx_mac_addr_1;
513 __le16 table_idx_ipv6_0;
514 __le16 table_idx_ipv6_1;
516 #define IAVF_AQ_NS_PROXY_ADD_0 0x0001
517 #define IAVF_AQ_NS_PROXY_DEL_0 0x0002
518 #define IAVF_AQ_NS_PROXY_ADD_1 0x0004
519 #define IAVF_AQ_NS_PROXY_DEL_1 0x0008
520 #define IAVF_AQ_NS_PROXY_ADD_IPV6_0 0x0010
521 #define IAVF_AQ_NS_PROXY_DEL_IPV6_0 0x0020
522 #define IAVF_AQ_NS_PROXY_ADD_IPV6_1 0x0040
523 #define IAVF_AQ_NS_PROXY_DEL_IPV6_1 0x0080
524 #define IAVF_AQ_NS_PROXY_COMMAND_SEQ 0x0100
525 #define IAVF_AQ_NS_PROXY_INIT_IPV6_TBL 0x0200
526 #define IAVF_AQ_NS_PROXY_INIT_MAC_TBL 0x0400
527 #define IAVF_AQ_NS_PROXY_OFFLOAD_ENABLE 0x0800
528 #define IAVF_AQ_NS_PROXY_DIRECTED_OFFLOAD_ENABLE 0x1000
531 u8 local_mac_addr[6];
532 u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */
536 IAVF_CHECK_STRUCT_LEN(0x3c, iavf_aqc_ns_proxy_data);
538 /* Manage LAA Command (0x0106) - obsolete */
539 struct iavf_aqc_mng_laa {
540 __le16 command_flags;
541 #define IAVF_AQ_LAA_FLAG_WR 0x8000
548 IAVF_CHECK_CMD_LENGTH(iavf_aqc_mng_laa);
550 /* Manage MAC Address Read Command (indirect 0x0107) */
551 struct iavf_aqc_mac_address_read {
552 __le16 command_flags;
553 #define IAVF_AQC_LAN_ADDR_VALID 0x10
554 #define IAVF_AQC_SAN_ADDR_VALID 0x20
555 #define IAVF_AQC_PORT_ADDR_VALID 0x40
556 #define IAVF_AQC_WOL_ADDR_VALID 0x80
557 #define IAVF_AQC_MC_MAG_EN_VALID 0x100
558 #define IAVF_AQC_WOL_PRESERVE_STATUS 0x200
559 #define IAVF_AQC_ADDR_VALID_MASK 0x3F0
565 IAVF_CHECK_CMD_LENGTH(iavf_aqc_mac_address_read);
567 struct iavf_aqc_mac_address_read_data {
574 IAVF_CHECK_STRUCT_LEN(24, iavf_aqc_mac_address_read_data);
576 /* Manage MAC Address Write Command (0x0108) */
577 struct iavf_aqc_mac_address_write {
578 __le16 command_flags;
579 #define IAVF_AQC_MC_MAG_EN 0x0100
580 #define IAVF_AQC_WOL_PRESERVE_ON_PFR 0x0200
581 #define IAVF_AQC_WRITE_TYPE_LAA_ONLY 0x0000
582 #define IAVF_AQC_WRITE_TYPE_LAA_WOL 0x4000
583 #define IAVF_AQC_WRITE_TYPE_PORT 0x8000
584 #define IAVF_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000
585 #define IAVF_AQC_WRITE_TYPE_MASK 0xC000
592 IAVF_CHECK_CMD_LENGTH(iavf_aqc_mac_address_write);
594 /* PXE commands (0x011x) */
596 /* Clear PXE Command and response (direct 0x0110) */
597 struct iavf_aqc_clear_pxe {
602 IAVF_CHECK_CMD_LENGTH(iavf_aqc_clear_pxe);
604 /* Set WoL Filter (0x0120) */
606 struct iavf_aqc_set_wol_filter {
608 #define IAVF_AQC_MAX_NUM_WOL_FILTERS 8
609 #define IAVF_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT 15
610 #define IAVF_AQC_SET_WOL_FILTER_TYPE_MAGIC_MASK (0x1 << \
611 IAVF_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT)
613 #define IAVF_AQC_SET_WOL_FILTER_INDEX_SHIFT 0
614 #define IAVF_AQC_SET_WOL_FILTER_INDEX_MASK (0x7 << \
615 IAVF_AQC_SET_WOL_FILTER_INDEX_SHIFT)
617 #define IAVF_AQC_SET_WOL_FILTER 0x8000
618 #define IAVF_AQC_SET_WOL_FILTER_NO_TCO_WOL 0x4000
619 #define IAVF_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR 0x2000
620 #define IAVF_AQC_SET_WOL_FILTER_ACTION_CLEAR 0
621 #define IAVF_AQC_SET_WOL_FILTER_ACTION_SET 1
623 #define IAVF_AQC_SET_WOL_FILTER_ACTION_VALID 0x8000
624 #define IAVF_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID 0x4000
630 IAVF_CHECK_CMD_LENGTH(iavf_aqc_set_wol_filter);
632 struct iavf_aqc_set_wol_filter_data {
637 IAVF_CHECK_STRUCT_LEN(0x90, iavf_aqc_set_wol_filter_data);
639 /* Get Wake Reason (0x0121) */
641 struct iavf_aqc_get_wake_reason_completion {
644 #define IAVF_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT 0
645 #define IAVF_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_MASK (0xFF << \
646 IAVF_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT)
647 #define IAVF_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT 8
648 #define IAVF_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_MASK (0xFF << \
649 IAVF_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT)
653 IAVF_CHECK_CMD_LENGTH(iavf_aqc_get_wake_reason_completion);
655 /* Switch configuration commands (0x02xx) */
657 /* Used by many indirect commands that only pass an seid and a buffer in the
660 struct iavf_aqc_switch_seid {
667 IAVF_CHECK_CMD_LENGTH(iavf_aqc_switch_seid);
669 /* Get Switch Configuration command (indirect 0x0200)
670 * uses iavf_aqc_switch_seid for the descriptor
672 struct iavf_aqc_get_switch_config_header_resp {
678 IAVF_CHECK_CMD_LENGTH(iavf_aqc_get_switch_config_header_resp);
680 struct iavf_aqc_switch_config_element_resp {
682 #define IAVF_AQ_SW_ELEM_TYPE_MAC 1
683 #define IAVF_AQ_SW_ELEM_TYPE_PF 2
684 #define IAVF_AQ_SW_ELEM_TYPE_VF 3
685 #define IAVF_AQ_SW_ELEM_TYPE_EMP 4
686 #define IAVF_AQ_SW_ELEM_TYPE_BMC 5
687 #define IAVF_AQ_SW_ELEM_TYPE_PV 16
688 #define IAVF_AQ_SW_ELEM_TYPE_VEB 17
689 #define IAVF_AQ_SW_ELEM_TYPE_PA 18
690 #define IAVF_AQ_SW_ELEM_TYPE_VSI 19
692 #define IAVF_AQ_SW_ELEM_REV_1 1
695 __le16 downlink_seid;
698 #define IAVF_AQ_CONN_TYPE_REGULAR 0x1
699 #define IAVF_AQ_CONN_TYPE_DEFAULT 0x2
700 #define IAVF_AQ_CONN_TYPE_CASCADED 0x3
705 IAVF_CHECK_STRUCT_LEN(0x10, iavf_aqc_switch_config_element_resp);
707 /* Get Switch Configuration (indirect 0x0200)
708 * an array of elements are returned in the response buffer
709 * the first in the array is the header, remainder are elements
711 struct iavf_aqc_get_switch_config_resp {
712 struct iavf_aqc_get_switch_config_header_resp header;
713 struct iavf_aqc_switch_config_element_resp element[1];
716 IAVF_CHECK_STRUCT_LEN(0x20, iavf_aqc_get_switch_config_resp);
718 /* Add Statistics (direct 0x0201)
719 * Remove Statistics (direct 0x0202)
721 struct iavf_aqc_add_remove_statistics {
728 IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_remove_statistics);
730 /* Set Port Parameters command (direct 0x0203) */
731 struct iavf_aqc_set_port_parameters {
732 __le16 command_flags;
733 #define IAVF_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1
734 #define IAVF_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */
735 #define IAVF_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4
736 __le16 bad_frame_vsi;
737 #define IAVF_AQ_SET_P_PARAMS_BFRAME_SEID_SHIFT 0x0
738 #define IAVF_AQ_SET_P_PARAMS_BFRAME_SEID_MASK 0x3FF
739 __le16 default_seid; /* reserved for command */
743 IAVF_CHECK_CMD_LENGTH(iavf_aqc_set_port_parameters);
745 /* Get Switch Resource Allocation (indirect 0x0204) */
746 struct iavf_aqc_get_switch_resource_alloc {
747 u8 num_entries; /* reserved for command */
753 IAVF_CHECK_CMD_LENGTH(iavf_aqc_get_switch_resource_alloc);
755 /* expect an array of these structs in the response buffer */
756 struct iavf_aqc_switch_resource_alloc_element_resp {
758 #define IAVF_AQ_RESOURCE_TYPE_VEB 0x0
759 #define IAVF_AQ_RESOURCE_TYPE_VSI 0x1
760 #define IAVF_AQ_RESOURCE_TYPE_MACADDR 0x2
761 #define IAVF_AQ_RESOURCE_TYPE_STAG 0x3
762 #define IAVF_AQ_RESOURCE_TYPE_ETAG 0x4
763 #define IAVF_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5
764 #define IAVF_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6
765 #define IAVF_AQ_RESOURCE_TYPE_VLAN 0x7
766 #define IAVF_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8
767 #define IAVF_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9
768 #define IAVF_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA
769 #define IAVF_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB
770 #define IAVF_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC
771 #define IAVF_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD
772 #define IAVF_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF
773 #define IAVF_AQ_RESOURCE_TYPE_IP_FILTERS 0x10
774 #define IAVF_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11
775 #define IAVF_AQ_RESOURCE_TYPE_VN2_KEYS 0x12
776 #define IAVF_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13
781 __le16 total_unalloced;
785 IAVF_CHECK_STRUCT_LEN(0x10, iavf_aqc_switch_resource_alloc_element_resp);
787 /* Set Switch Configuration (direct 0x0205) */
788 struct iavf_aqc_set_switch_config {
790 /* flags used for both fields below */
791 #define IAVF_AQ_SET_SWITCH_CFG_PROMISC 0x0001
792 #define IAVF_AQ_SET_SWITCH_CFG_L2_FILTER 0x0002
793 #define IAVF_AQ_SET_SWITCH_CFG_HW_ATR_EVICT 0x0004
795 /* The ethertype in switch_tag is dropped on ingress and used
796 * internally by the switch. Set this to zero for the default
797 * of 0x88a8 (802.1ad). Should be zero for firmware API
798 * versions lower than 1.7.
801 /* The ethertypes in first_tag and second_tag are used to
802 * match the outer and inner VLAN tags (respectively) when HW
803 * double VLAN tagging is enabled via the set port parameters
804 * AQ command. Otherwise these are both ignored. Set them to
805 * zero for their defaults of 0x8100 (802.1Q). Should be zero
806 * for firmware API versions lower than 1.7.
813 IAVF_CHECK_CMD_LENGTH(iavf_aqc_set_switch_config);
815 /* Read Receive control registers (direct 0x0206)
816 * Write Receive control registers (direct 0x0207)
817 * used for accessing Rx control registers that can be
818 * slow and need special handling when under high Rx load
820 struct iavf_aqc_rx_ctl_reg_read_write {
827 IAVF_CHECK_CMD_LENGTH(iavf_aqc_rx_ctl_reg_read_write);
829 /* Add VSI (indirect 0x0210)
830 * this indirect command uses struct iavf_aqc_vsi_properties_data
831 * as the indirect buffer (128 bytes)
833 * Update VSI (indirect 0x211)
834 * uses the same data structure as Add VSI
836 * Get VSI (indirect 0x0212)
837 * uses the same completion and data structure as Add VSI
839 struct iavf_aqc_add_get_update_vsi {
842 #define IAVF_AQ_VSI_CONN_TYPE_NORMAL 0x1
843 #define IAVF_AQ_VSI_CONN_TYPE_DEFAULT 0x2
844 #define IAVF_AQ_VSI_CONN_TYPE_CASCADED 0x3
849 #define IAVF_AQ_VSI_TYPE_SHIFT 0x0
850 #define IAVF_AQ_VSI_TYPE_MASK (0x3 << IAVF_AQ_VSI_TYPE_SHIFT)
851 #define IAVF_AQ_VSI_TYPE_VF 0x0
852 #define IAVF_AQ_VSI_TYPE_VMDQ2 0x1
853 #define IAVF_AQ_VSI_TYPE_PF 0x2
854 #define IAVF_AQ_VSI_TYPE_EMP_MNG 0x3
855 #define IAVF_AQ_VSI_FLAG_CASCADED_PV 0x4
860 IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_get_update_vsi);
862 struct iavf_aqc_add_get_update_vsi_completion {
871 IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_get_update_vsi_completion);
873 struct iavf_aqc_vsi_properties_data {
874 /* first 96 byte are written by SW */
875 __le16 valid_sections;
876 #define IAVF_AQ_VSI_PROP_SWITCH_VALID 0x0001
877 #define IAVF_AQ_VSI_PROP_SECURITY_VALID 0x0002
878 #define IAVF_AQ_VSI_PROP_VLAN_VALID 0x0004
879 #define IAVF_AQ_VSI_PROP_CAS_PV_VALID 0x0008
880 #define IAVF_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010
881 #define IAVF_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020
882 #define IAVF_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040
883 #define IAVF_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080
884 #define IAVF_AQ_VSI_PROP_OUTER_UP_VALID 0x0100
885 #define IAVF_AQ_VSI_PROP_SCHED_VALID 0x0200
887 __le16 switch_id; /* 12bit id combined with flags below */
888 #define IAVF_AQ_VSI_SW_ID_SHIFT 0x0000
889 #define IAVF_AQ_VSI_SW_ID_MASK (0xFFF << IAVF_AQ_VSI_SW_ID_SHIFT)
890 #define IAVF_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000
891 #define IAVF_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000
892 #define IAVF_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000
894 /* security section */
896 #define IAVF_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01
897 #define IAVF_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02
898 #define IAVF_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04
901 __le16 pvid; /* VLANS include priority bits */
904 #define IAVF_AQ_VSI_PVLAN_MODE_SHIFT 0x00
905 #define IAVF_AQ_VSI_PVLAN_MODE_MASK (0x03 << \
906 IAVF_AQ_VSI_PVLAN_MODE_SHIFT)
907 #define IAVF_AQ_VSI_PVLAN_MODE_TAGGED 0x01
908 #define IAVF_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02
909 #define IAVF_AQ_VSI_PVLAN_MODE_ALL 0x03
910 #define IAVF_AQ_VSI_PVLAN_INSERT_PVID 0x04
911 #define IAVF_AQ_VSI_PVLAN_EMOD_SHIFT 0x03
912 #define IAVF_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \
913 IAVF_AQ_VSI_PVLAN_EMOD_SHIFT)
914 #define IAVF_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0
915 #define IAVF_AQ_VSI_PVLAN_EMOD_STR_UP 0x08
916 #define IAVF_AQ_VSI_PVLAN_EMOD_STR 0x10
917 #define IAVF_AQ_VSI_PVLAN_EMOD_NOTHING 0x18
918 u8 pvlan_reserved[3];
919 /* ingress egress up sections */
920 __le32 ingress_table; /* bitmap, 3 bits per up */
921 #define IAVF_AQ_VSI_UP_TABLE_UP0_SHIFT 0
922 #define IAVF_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \
923 IAVF_AQ_VSI_UP_TABLE_UP0_SHIFT)
924 #define IAVF_AQ_VSI_UP_TABLE_UP1_SHIFT 3
925 #define IAVF_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \
926 IAVF_AQ_VSI_UP_TABLE_UP1_SHIFT)
927 #define IAVF_AQ_VSI_UP_TABLE_UP2_SHIFT 6
928 #define IAVF_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \
929 IAVF_AQ_VSI_UP_TABLE_UP2_SHIFT)
930 #define IAVF_AQ_VSI_UP_TABLE_UP3_SHIFT 9
931 #define IAVF_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \
932 IAVF_AQ_VSI_UP_TABLE_UP3_SHIFT)
933 #define IAVF_AQ_VSI_UP_TABLE_UP4_SHIFT 12
934 #define IAVF_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \
935 IAVF_AQ_VSI_UP_TABLE_UP4_SHIFT)
936 #define IAVF_AQ_VSI_UP_TABLE_UP5_SHIFT 15
937 #define IAVF_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \
938 IAVF_AQ_VSI_UP_TABLE_UP5_SHIFT)
939 #define IAVF_AQ_VSI_UP_TABLE_UP6_SHIFT 18
940 #define IAVF_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \
941 IAVF_AQ_VSI_UP_TABLE_UP6_SHIFT)
942 #define IAVF_AQ_VSI_UP_TABLE_UP7_SHIFT 21
943 #define IAVF_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \
944 IAVF_AQ_VSI_UP_TABLE_UP7_SHIFT)
945 __le32 egress_table; /* same defines as for ingress table */
946 /* cascaded PV section */
949 #define IAVF_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00
950 #define IAVF_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \
951 IAVF_AQ_VSI_CAS_PV_TAGX_SHIFT)
952 #define IAVF_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00
953 #define IAVF_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01
954 #define IAVF_AQ_VSI_CAS_PV_TAGX_COPY 0x02
955 #define IAVF_AQ_VSI_CAS_PV_INSERT_TAG 0x10
956 #define IAVF_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20
957 #define IAVF_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40
959 /* queue mapping section */
960 __le16 mapping_flags;
961 #define IAVF_AQ_VSI_QUE_MAP_CONTIG 0x0
962 #define IAVF_AQ_VSI_QUE_MAP_NONCONTIG 0x1
963 __le16 queue_mapping[16];
964 #define IAVF_AQ_VSI_QUEUE_SHIFT 0x0
965 #define IAVF_AQ_VSI_QUEUE_MASK (0x7FF << IAVF_AQ_VSI_QUEUE_SHIFT)
966 __le16 tc_mapping[8];
967 #define IAVF_AQ_VSI_TC_QUE_OFFSET_SHIFT 0
968 #define IAVF_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \
969 IAVF_AQ_VSI_TC_QUE_OFFSET_SHIFT)
970 #define IAVF_AQ_VSI_TC_QUE_NUMBER_SHIFT 9
971 #define IAVF_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \
972 IAVF_AQ_VSI_TC_QUE_NUMBER_SHIFT)
973 /* queueing option section */
974 u8 queueing_opt_flags;
975 #define IAVF_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA 0x04
976 #define IAVF_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA 0x08
977 #define IAVF_AQ_VSI_QUE_OPT_TCP_ENA 0x10
978 #define IAVF_AQ_VSI_QUE_OPT_FCOE_ENA 0x20
979 #define IAVF_AQ_VSI_QUE_OPT_RSS_LUT_PF 0x00
980 #define IAVF_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40
981 u8 queueing_opt_reserved[3];
982 /* scheduler section */
985 /* outer up section */
986 __le32 outer_up_table; /* same structure and defines as ingress tbl */
988 /* last 32 bytes are written by FW */
990 #define IAVF_AQ_VSI_QS_HANDLE_INVALID 0xFFFF
991 __le16 stat_counter_idx;
993 u8 resp_reserved[12];
996 IAVF_CHECK_STRUCT_LEN(128, iavf_aqc_vsi_properties_data);
998 /* Add Port Virtualizer (direct 0x0220)
999 * also used for update PV (direct 0x0221) but only flags are used
1000 * (IS_CTRL_PORT only works on add PV)
1002 struct iavf_aqc_add_update_pv {
1003 __le16 command_flags;
1004 #define IAVF_AQC_PV_FLAG_PV_TYPE 0x1
1005 #define IAVF_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2
1006 #define IAVF_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4
1007 #define IAVF_AQC_PV_FLAG_IS_CTRL_PORT 0x8
1009 __le16 connected_seid;
1013 IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_update_pv);
1015 struct iavf_aqc_add_update_pv_completion {
1016 /* reserved for update; for add also encodes error if rc == ENOSPC */
1018 #define IAVF_AQC_PV_ERR_FLAG_NO_PV 0x1
1019 #define IAVF_AQC_PV_ERR_FLAG_NO_SCHED 0x2
1020 #define IAVF_AQC_PV_ERR_FLAG_NO_COUNTER 0x4
1021 #define IAVF_AQC_PV_ERR_FLAG_NO_ENTRY 0x8
1025 IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_update_pv_completion);
1027 /* Get PV Params (direct 0x0222)
1028 * uses iavf_aqc_switch_seid for the descriptor
1031 struct iavf_aqc_get_pv_params_completion {
1033 __le16 default_stag;
1034 __le16 pv_flags; /* same flags as add_pv */
1035 #define IAVF_AQC_GET_PV_PV_TYPE 0x1
1036 #define IAVF_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2
1037 #define IAVF_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4
1039 __le16 default_port_seid;
1042 IAVF_CHECK_CMD_LENGTH(iavf_aqc_get_pv_params_completion);
1044 /* Add VEB (direct 0x0230) */
1045 struct iavf_aqc_add_veb {
1047 __le16 downlink_seid;
1049 #define IAVF_AQC_ADD_VEB_FLOATING 0x1
1050 #define IAVF_AQC_ADD_VEB_PORT_TYPE_SHIFT 1
1051 #define IAVF_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \
1052 IAVF_AQC_ADD_VEB_PORT_TYPE_SHIFT)
1053 #define IAVF_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2
1054 #define IAVF_AQC_ADD_VEB_PORT_TYPE_DATA 0x4
1055 #define IAVF_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8 /* deprecated */
1056 #define IAVF_AQC_ADD_VEB_ENABLE_DISABLE_STATS 0x10
1061 IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_veb);
1063 struct iavf_aqc_add_veb_completion {
1066 /* also encodes error if rc == ENOSPC; codes are the same as add_pv */
1068 #define IAVF_AQC_VEB_ERR_FLAG_NO_VEB 0x1
1069 #define IAVF_AQC_VEB_ERR_FLAG_NO_SCHED 0x2
1070 #define IAVF_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4
1071 #define IAVF_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8
1072 __le16 statistic_index;
1077 IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_veb_completion);
1079 /* Get VEB Parameters (direct 0x0232)
1080 * uses iavf_aqc_switch_seid for the descriptor
1082 struct iavf_aqc_get_veb_parameters_completion {
1085 __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */
1086 __le16 statistic_index;
1092 IAVF_CHECK_CMD_LENGTH(iavf_aqc_get_veb_parameters_completion);
1094 /* Delete Element (direct 0x0243)
1095 * uses the generic iavf_aqc_switch_seid
1098 /* Add MAC-VLAN (indirect 0x0250) */
1100 /* used for the command for most vlan commands */
1101 struct iavf_aqc_macvlan {
1102 __le16 num_addresses;
1104 #define IAVF_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0
1105 #define IAVF_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \
1106 IAVF_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
1107 #define IAVF_AQC_MACVLAN_CMD_SEID_VALID 0x8000
1112 IAVF_CHECK_CMD_LENGTH(iavf_aqc_macvlan);
1114 /* indirect data for command and response */
1115 struct iavf_aqc_add_macvlan_element_data {
1119 #define IAVF_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001
1120 #define IAVF_AQC_MACVLAN_ADD_HASH_MATCH 0x0002
1121 #define IAVF_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004
1122 #define IAVF_AQC_MACVLAN_ADD_TO_QUEUE 0x0008
1123 #define IAVF_AQC_MACVLAN_ADD_USE_SHARED_MAC 0x0010
1124 __le16 queue_number;
1125 #define IAVF_AQC_MACVLAN_CMD_QUEUE_SHIFT 0
1126 #define IAVF_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \
1127 IAVF_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
1128 /* response section */
1130 #define IAVF_AQC_MM_PERFECT_MATCH 0x01
1131 #define IAVF_AQC_MM_HASH_MATCH 0x02
1132 #define IAVF_AQC_MM_ERR_NO_RES 0xFF
1136 struct iavf_aqc_add_remove_macvlan_completion {
1137 __le16 perfect_mac_used;
1138 __le16 perfect_mac_free;
1139 __le16 unicast_hash_free;
1140 __le16 multicast_hash_free;
1145 IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_remove_macvlan_completion);
1147 /* Remove MAC-VLAN (indirect 0x0251)
1148 * uses iavf_aqc_macvlan for the descriptor
1149 * data points to an array of num_addresses of elements
1152 struct iavf_aqc_remove_macvlan_element_data {
1156 #define IAVF_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01
1157 #define IAVF_AQC_MACVLAN_DEL_HASH_MATCH 0x02
1158 #define IAVF_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08
1159 #define IAVF_AQC_MACVLAN_DEL_ALL_VSIS 0x10
1163 #define IAVF_AQC_REMOVE_MACVLAN_SUCCESS 0x0
1164 #define IAVF_AQC_REMOVE_MACVLAN_FAIL 0xFF
1165 u8 reply_reserved[3];
1168 /* Add VLAN (indirect 0x0252)
1169 * Remove VLAN (indirect 0x0253)
1170 * use the generic iavf_aqc_macvlan for the command
1172 struct iavf_aqc_add_remove_vlan_element_data {
1175 /* flags for add VLAN */
1176 #define IAVF_AQC_ADD_VLAN_LOCAL 0x1
1177 #define IAVF_AQC_ADD_PVLAN_TYPE_SHIFT 1
1178 #define IAVF_AQC_ADD_PVLAN_TYPE_MASK (0x3 << IAVF_AQC_ADD_PVLAN_TYPE_SHIFT)
1179 #define IAVF_AQC_ADD_PVLAN_TYPE_REGULAR 0x0
1180 #define IAVF_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2
1181 #define IAVF_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4
1182 #define IAVF_AQC_VLAN_PTYPE_SHIFT 3
1183 #define IAVF_AQC_VLAN_PTYPE_MASK (0x3 << IAVF_AQC_VLAN_PTYPE_SHIFT)
1184 #define IAVF_AQC_VLAN_PTYPE_REGULAR_VSI 0x0
1185 #define IAVF_AQC_VLAN_PTYPE_PROMISC_VSI 0x8
1186 #define IAVF_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10
1187 #define IAVF_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18
1188 /* flags for remove VLAN */
1189 #define IAVF_AQC_REMOVE_VLAN_ALL 0x1
1192 /* flags for add VLAN */
1193 #define IAVF_AQC_ADD_VLAN_SUCCESS 0x0
1194 #define IAVF_AQC_ADD_VLAN_FAIL_REQUEST 0xFE
1195 #define IAVF_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF
1196 /* flags for remove VLAN */
1197 #define IAVF_AQC_REMOVE_VLAN_SUCCESS 0x0
1198 #define IAVF_AQC_REMOVE_VLAN_FAIL 0xFF
1202 struct iavf_aqc_add_remove_vlan_completion {
1210 /* Set VSI Promiscuous Modes (direct 0x0254) */
1211 struct iavf_aqc_set_vsi_promiscuous_modes {
1212 __le16 promiscuous_flags;
1214 /* flags used for both fields above */
1215 #define IAVF_AQC_SET_VSI_PROMISC_UNICAST 0x01
1216 #define IAVF_AQC_SET_VSI_PROMISC_MULTICAST 0x02
1217 #define IAVF_AQC_SET_VSI_PROMISC_BROADCAST 0x04
1218 #define IAVF_AQC_SET_VSI_DEFAULT 0x08
1219 #define IAVF_AQC_SET_VSI_PROMISC_VLAN 0x10
1220 #define IAVF_AQC_SET_VSI_PROMISC_TX 0x8000
1222 #define IAVF_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF
1224 #define IAVF_AQC_SET_VSI_VLAN_MASK 0x0FFF
1225 #define IAVF_AQC_SET_VSI_VLAN_VALID 0x8000
1229 IAVF_CHECK_CMD_LENGTH(iavf_aqc_set_vsi_promiscuous_modes);
1231 /* Add S/E-tag command (direct 0x0255)
1232 * Uses generic iavf_aqc_add_remove_tag_completion for completion
1234 struct iavf_aqc_add_tag {
1236 #define IAVF_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001
1238 #define IAVF_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0
1239 #define IAVF_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1240 IAVF_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT)
1242 __le16 queue_number;
1246 IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_tag);
1248 struct iavf_aqc_add_remove_tag_completion {
1254 IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_remove_tag_completion);
1256 /* Remove S/E-tag command (direct 0x0256)
1257 * Uses generic iavf_aqc_add_remove_tag_completion for completion
1259 struct iavf_aqc_remove_tag {
1261 #define IAVF_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0
1262 #define IAVF_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1263 IAVF_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT)
1268 IAVF_CHECK_CMD_LENGTH(iavf_aqc_remove_tag);
1270 /* Add multicast E-Tag (direct 0x0257)
1271 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields
1272 * and no external data
1274 struct iavf_aqc_add_remove_mcast_etag {
1277 u8 num_unicast_etags;
1279 __le32 addr_high; /* address of array of 2-byte s-tags */
1283 IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_remove_mcast_etag);
1285 struct iavf_aqc_add_remove_mcast_etag_completion {
1287 __le16 mcast_etags_used;
1288 __le16 mcast_etags_free;
1294 IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_remove_mcast_etag_completion);
1296 /* Update S/E-Tag (direct 0x0259) */
1297 struct iavf_aqc_update_tag {
1299 #define IAVF_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0
1300 #define IAVF_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1301 IAVF_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT)
1307 IAVF_CHECK_CMD_LENGTH(iavf_aqc_update_tag);
1309 struct iavf_aqc_update_tag_completion {
1315 IAVF_CHECK_CMD_LENGTH(iavf_aqc_update_tag_completion);
1317 /* Add Control Packet filter (direct 0x025A)
1318 * Remove Control Packet filter (direct 0x025B)
1319 * uses the iavf_aqc_add_oveb_cloud,
1320 * and the generic direct completion structure
1322 struct iavf_aqc_add_remove_control_packet_filter {
1326 #define IAVF_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001
1327 #define IAVF_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002
1328 #define IAVF_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004
1329 #define IAVF_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008
1330 #define IAVF_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000
1332 #define IAVF_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0
1333 #define IAVF_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \
1334 IAVF_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT)
1339 IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_remove_control_packet_filter);
1341 struct iavf_aqc_add_remove_control_packet_filter_completion {
1342 __le16 mac_etype_used;
1344 __le16 mac_etype_free;
1349 IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_remove_control_packet_filter_completion);
1351 /* Add Cloud filters (indirect 0x025C)
1352 * Remove Cloud filters (indirect 0x025D)
1353 * uses the iavf_aqc_add_remove_cloud_filters,
1354 * and the generic indirect completion structure
1356 struct iavf_aqc_add_remove_cloud_filters {
1360 #define IAVF_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0
1361 #define IAVF_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \
1362 IAVF_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT)
1364 #define IAVF_AQC_ADD_REM_CLOUD_CMD_BIG_BUFFER 1
1370 IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_remove_cloud_filters);
1372 struct iavf_aqc_add_remove_cloud_filters_element_data {
1386 #define IAVF_AQC_ADD_CLOUD_FILTER_SHIFT 0
1387 #define IAVF_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \
1388 IAVF_AQC_ADD_CLOUD_FILTER_SHIFT)
1389 /* 0x0000 reserved */
1390 #define IAVF_AQC_ADD_CLOUD_FILTER_OIP 0x0001
1391 /* 0x0002 reserved */
1392 #define IAVF_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003
1393 #define IAVF_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004
1394 /* 0x0005 reserved */
1395 #define IAVF_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006
1396 /* 0x0007 reserved */
1397 /* 0x0008 reserved */
1398 #define IAVF_AQC_ADD_CLOUD_FILTER_OMAC 0x0009
1399 #define IAVF_AQC_ADD_CLOUD_FILTER_IMAC 0x000A
1400 #define IAVF_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B
1401 #define IAVF_AQC_ADD_CLOUD_FILTER_IIP 0x000C
1402 /* 0x0010 to 0x0017 is for custom filters */
1404 #define IAVF_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080
1405 #define IAVF_AQC_ADD_CLOUD_VNK_SHIFT 6
1406 #define IAVF_AQC_ADD_CLOUD_VNK_MASK 0x00C0
1407 #define IAVF_AQC_ADD_CLOUD_FLAGS_IPV4 0
1408 #define IAVF_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100
1410 #define IAVF_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9
1411 #define IAVF_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00
1412 #define IAVF_AQC_ADD_CLOUD_TNL_TYPE_VXLAN 0
1413 #define IAVF_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1
1414 #define IAVF_AQC_ADD_CLOUD_TNL_TYPE_GENEVE 2
1415 #define IAVF_AQC_ADD_CLOUD_TNL_TYPE_IP 3
1416 #define IAVF_AQC_ADD_CLOUD_TNL_TYPE_RESERVED 4
1417 #define IAVF_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE 5
1419 #define IAVF_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_MAC 0x2000
1420 #define IAVF_AQC_ADD_CLOUD_FLAGS_SHARED_INNER_MAC 0x4000
1421 #define IAVF_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_IP 0x8000
1425 __le16 queue_number;
1426 #define IAVF_AQC_ADD_CLOUD_QUEUE_SHIFT 0
1427 #define IAVF_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \
1428 IAVF_AQC_ADD_CLOUD_QUEUE_SHIFT)
1430 /* response section */
1431 u8 allocation_result;
1432 #define IAVF_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0
1433 #define IAVF_AQC_ADD_CLOUD_FILTER_FAIL 0xFF
1434 u8 response_reserved[7];
1437 /* iavf_aqc_add_rm_cloud_filt_elem_ext is used when
1438 * IAVF_AQC_ADD_REM_CLOUD_CMD_BIG_BUFFER flag is set.
1440 struct iavf_aqc_add_rm_cloud_filt_elem_ext {
1441 struct iavf_aqc_add_remove_cloud_filters_element_data element;
1442 u16 general_fields[32];
1443 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X10_WORD0 0
1444 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1 1
1445 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X10_WORD2 2
1446 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0 3
1447 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1 4
1448 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2 5
1449 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0 6
1450 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1 7
1451 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2 8
1452 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0 9
1453 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1 10
1454 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2 11
1455 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X14_WORD0 12
1456 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X14_WORD1 13
1457 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X14_WORD2 14
1458 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X16_WORD0 15
1459 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X16_WORD1 16
1460 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X16_WORD2 17
1461 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X16_WORD3 18
1462 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X16_WORD4 19
1463 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X16_WORD5 20
1464 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X16_WORD6 21
1465 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X16_WORD7 22
1466 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X17_WORD0 23
1467 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X17_WORD1 24
1468 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X17_WORD2 25
1469 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X17_WORD3 26
1470 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X17_WORD4 27
1471 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X17_WORD5 28
1472 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X17_WORD6 29
1473 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X17_WORD7 30
1476 struct iavf_aqc_remove_cloud_filters_completion {
1477 __le16 perfect_ovlan_used;
1478 __le16 perfect_ovlan_free;
1485 IAVF_CHECK_CMD_LENGTH(iavf_aqc_remove_cloud_filters_completion);
1487 /* Replace filter Command 0x025F
1488 * uses the iavf_aqc_replace_cloud_filters,
1489 * and the generic indirect completion structure
1491 struct iavf_filter_data {
1496 struct iavf_aqc_replace_cloud_filters_cmd {
1498 #define IAVF_AQC_REPLACE_L1_FILTER 0x0
1499 #define IAVF_AQC_REPLACE_CLOUD_FILTER 0x1
1500 #define IAVF_AQC_GET_CLOUD_FILTERS 0x2
1501 #define IAVF_AQC_MIRROR_CLOUD_FILTER 0x4
1502 #define IAVF_AQC_HIGH_PRIORITY_CLOUD_FILTER 0x8
1511 struct iavf_aqc_replace_cloud_filters_cmd_buf {
1513 /* Filter type INPUT codes*/
1514 #define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_ENTRIES_MAX 3
1515 #define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED (1 << 7UL)
1517 /* Field Vector offsets */
1518 #define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_FV_MAC_DA 0
1519 #define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_ETH 6
1520 #define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG 7
1521 #define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN 8
1522 #define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_OVLAN 9
1523 #define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN 10
1524 #define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY 11
1525 #define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC 12
1527 #define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IP_DA 14
1529 #define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_FV_OIP_DA 15
1531 #define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN 37
1532 struct iavf_filter_data filters[8];
1535 /* Add Mirror Rule (indirect or direct 0x0260)
1536 * Delete Mirror Rule (indirect or direct 0x0261)
1537 * note: some rule types (4,5) do not use an external buffer.
1538 * take care to set the flags correctly.
1540 struct iavf_aqc_add_delete_mirror_rule {
1543 #define IAVF_AQC_MIRROR_RULE_TYPE_SHIFT 0
1544 #define IAVF_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \
1545 IAVF_AQC_MIRROR_RULE_TYPE_SHIFT)
1546 #define IAVF_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1
1547 #define IAVF_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2
1548 #define IAVF_AQC_MIRROR_RULE_TYPE_VLAN 3
1549 #define IAVF_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4
1550 #define IAVF_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5
1552 __le16 destination; /* VSI for add, rule id for delete */
1553 __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */
1557 IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_delete_mirror_rule);
1559 struct iavf_aqc_add_delete_mirror_rule_completion {
1561 __le16 rule_id; /* only used on add */
1562 __le16 mirror_rules_used;
1563 __le16 mirror_rules_free;
1568 IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_delete_mirror_rule_completion);
1570 /* Dynamic Device Personalization */
1571 struct iavf_aqc_write_personalization_profile {
1574 __le32 profile_track_id;
1579 IAVF_CHECK_CMD_LENGTH(iavf_aqc_write_personalization_profile);
1581 struct iavf_aqc_write_ddp_resp {
1582 __le32 error_offset;
1588 struct iavf_aqc_get_applied_profiles {
1590 #define IAVF_AQC_GET_DDP_GET_CONF 0x1
1591 #define IAVF_AQC_GET_DDP_GET_RDPU_CONF 0x2
1598 IAVF_CHECK_CMD_LENGTH(iavf_aqc_get_applied_profiles);
1602 /* PFC Ignore (direct 0x0301)
1603 * the command and response use the same descriptor structure
1605 struct iavf_aqc_pfc_ignore {
1607 u8 command_flags; /* unused on response */
1608 #define IAVF_AQC_PFC_IGNORE_SET 0x80
1609 #define IAVF_AQC_PFC_IGNORE_CLEAR 0x0
1613 IAVF_CHECK_CMD_LENGTH(iavf_aqc_pfc_ignore);
1615 /* DCB Update (direct 0x0302) uses the iavf_aq_desc structure
1616 * with no parameters
1619 /* TX scheduler 0x04xx */
1621 /* Almost all the indirect commands use
1622 * this generic struct to pass the SEID in param0
1624 struct iavf_aqc_tx_sched_ind {
1631 IAVF_CHECK_CMD_LENGTH(iavf_aqc_tx_sched_ind);
1633 /* Several commands respond with a set of queue set handles */
1634 struct iavf_aqc_qs_handles_resp {
1635 __le16 qs_handles[8];
1638 /* Configure VSI BW limits (direct 0x0400) */
1639 struct iavf_aqc_configure_vsi_bw_limit {
1644 u8 max_credit; /* 0-3, limit = 2^max */
1648 IAVF_CHECK_CMD_LENGTH(iavf_aqc_configure_vsi_bw_limit);
1650 /* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406)
1651 * responds with iavf_aqc_qs_handles_resp
1653 struct iavf_aqc_configure_vsi_ets_sla_bw_data {
1656 __le16 tc_bw_credits[8]; /* FW writesback QS handles here */
1658 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1659 __le16 tc_bw_max[2];
1663 IAVF_CHECK_STRUCT_LEN(0x40, iavf_aqc_configure_vsi_ets_sla_bw_data);
1665 /* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407)
1666 * responds with iavf_aqc_qs_handles_resp
1668 struct iavf_aqc_configure_vsi_tc_bw_data {
1671 u8 tc_bw_credits[8];
1673 __le16 qs_handles[8];
1676 IAVF_CHECK_STRUCT_LEN(0x20, iavf_aqc_configure_vsi_tc_bw_data);
1678 /* Query vsi bw configuration (indirect 0x0408) */
1679 struct iavf_aqc_query_vsi_bw_config_resp {
1681 u8 tc_suspended_bits;
1683 __le16 qs_handles[8];
1685 __le16 port_bw_limit;
1687 u8 max_bw; /* 0-3, limit = 2^max */
1691 IAVF_CHECK_STRUCT_LEN(0x40, iavf_aqc_query_vsi_bw_config_resp);
1693 /* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */
1694 struct iavf_aqc_query_vsi_ets_sla_config_resp {
1697 u8 share_credits[8];
1700 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1701 __le16 tc_bw_max[2];
1704 IAVF_CHECK_STRUCT_LEN(0x20, iavf_aqc_query_vsi_ets_sla_config_resp);
1706 /* Configure Switching Component Bandwidth Limit (direct 0x0410) */
1707 struct iavf_aqc_configure_switching_comp_bw_limit {
1712 u8 max_bw; /* 0-3, limit = 2^max */
1716 IAVF_CHECK_CMD_LENGTH(iavf_aqc_configure_switching_comp_bw_limit);
1718 /* Enable Physical Port ETS (indirect 0x0413)
1719 * Modify Physical Port ETS (indirect 0x0414)
1720 * Disable Physical Port ETS (indirect 0x0415)
1722 struct iavf_aqc_configure_switching_comp_ets_data {
1726 #define IAVF_AQ_ETS_SEEPAGE_EN_MASK 0x1
1727 u8 tc_strict_priority_flags;
1729 u8 tc_bw_share_credits[8];
1733 IAVF_CHECK_STRUCT_LEN(0x80, iavf_aqc_configure_switching_comp_ets_data);
1735 /* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */
1736 struct iavf_aqc_configure_switching_comp_ets_bw_limit_data {
1739 __le16 tc_bw_credit[8];
1741 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1742 __le16 tc_bw_max[2];
1746 IAVF_CHECK_STRUCT_LEN(0x40,
1747 iavf_aqc_configure_switching_comp_ets_bw_limit_data);
1749 /* Configure Switching Component Bandwidth Allocation per Tc
1752 struct iavf_aqc_configure_switching_comp_bw_config_data {
1755 u8 absolute_credits; /* bool */
1756 u8 tc_bw_share_credits[8];
1760 IAVF_CHECK_STRUCT_LEN(0x20, iavf_aqc_configure_switching_comp_bw_config_data);
1762 /* Query Switching Component Configuration (indirect 0x0418) */
1763 struct iavf_aqc_query_switching_comp_ets_config_resp {
1766 __le16 port_bw_limit;
1768 u8 tc_bw_max; /* 0-3, limit = 2^max */
1772 IAVF_CHECK_STRUCT_LEN(0x40, iavf_aqc_query_switching_comp_ets_config_resp);
1774 /* Query PhysicalPort ETS Configuration (indirect 0x0419) */
1775 struct iavf_aqc_query_port_ets_config_resp {
1779 u8 tc_strict_priority_bits;
1781 u8 tc_bw_share_credits[8];
1782 __le16 tc_bw_limits[8];
1784 /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */
1785 __le16 tc_bw_max[2];
1789 IAVF_CHECK_STRUCT_LEN(0x44, iavf_aqc_query_port_ets_config_resp);
1791 /* Query Switching Component Bandwidth Allocation per Traffic Type
1794 struct iavf_aqc_query_switching_comp_bw_config_resp {
1797 u8 absolute_credits_enable; /* bool */
1798 u8 tc_bw_share_credits[8];
1799 __le16 tc_bw_limits[8];
1801 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1802 __le16 tc_bw_max[2];
1805 IAVF_CHECK_STRUCT_LEN(0x20, iavf_aqc_query_switching_comp_bw_config_resp);
1807 /* Suspend/resume port TX traffic
1808 * (direct 0x041B and 0x041C) uses the generic SEID struct
1811 /* Configure partition BW
1814 struct iavf_aqc_configure_partition_bw_data {
1815 __le16 pf_valid_bits;
1816 u8 min_bw[16]; /* guaranteed bandwidth */
1817 u8 max_bw[16]; /* bandwidth limit */
1820 IAVF_CHECK_STRUCT_LEN(0x22, iavf_aqc_configure_partition_bw_data);
1822 /* Get and set the active HMC resource profile and status.
1823 * (direct 0x0500) and (direct 0x0501)
1825 struct iavf_aq_get_set_hmc_resource_profile {
1831 IAVF_CHECK_CMD_LENGTH(iavf_aq_get_set_hmc_resource_profile);
1833 enum iavf_aq_hmc_profile {
1834 /* IAVF_HMC_PROFILE_NO_CHANGE = 0, reserved */
1835 IAVF_HMC_PROFILE_DEFAULT = 1,
1836 IAVF_HMC_PROFILE_FAVOR_VF = 2,
1837 IAVF_HMC_PROFILE_EQUAL = 3,
1840 /* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */
1842 /* set in param0 for get phy abilities to report qualified modules */
1843 #define IAVF_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001
1844 #define IAVF_AQ_PHY_REPORT_INITIAL_VALUES 0x0002
1846 enum iavf_aq_phy_type {
1847 IAVF_PHY_TYPE_SGMII = 0x0,
1848 IAVF_PHY_TYPE_1000BASE_KX = 0x1,
1849 IAVF_PHY_TYPE_10GBASE_KX4 = 0x2,
1850 IAVF_PHY_TYPE_10GBASE_KR = 0x3,
1851 IAVF_PHY_TYPE_40GBASE_KR4 = 0x4,
1852 IAVF_PHY_TYPE_XAUI = 0x5,
1853 IAVF_PHY_TYPE_XFI = 0x6,
1854 IAVF_PHY_TYPE_SFI = 0x7,
1855 IAVF_PHY_TYPE_XLAUI = 0x8,
1856 IAVF_PHY_TYPE_XLPPI = 0x9,
1857 IAVF_PHY_TYPE_40GBASE_CR4_CU = 0xA,
1858 IAVF_PHY_TYPE_10GBASE_CR1_CU = 0xB,
1859 IAVF_PHY_TYPE_10GBASE_AOC = 0xC,
1860 IAVF_PHY_TYPE_40GBASE_AOC = 0xD,
1861 IAVF_PHY_TYPE_UNRECOGNIZED = 0xE,
1862 IAVF_PHY_TYPE_UNSUPPORTED = 0xF,
1863 IAVF_PHY_TYPE_100BASE_TX = 0x11,
1864 IAVF_PHY_TYPE_1000BASE_T = 0x12,
1865 IAVF_PHY_TYPE_10GBASE_T = 0x13,
1866 IAVF_PHY_TYPE_10GBASE_SR = 0x14,
1867 IAVF_PHY_TYPE_10GBASE_LR = 0x15,
1868 IAVF_PHY_TYPE_10GBASE_SFPP_CU = 0x16,
1869 IAVF_PHY_TYPE_10GBASE_CR1 = 0x17,
1870 IAVF_PHY_TYPE_40GBASE_CR4 = 0x18,
1871 IAVF_PHY_TYPE_40GBASE_SR4 = 0x19,
1872 IAVF_PHY_TYPE_40GBASE_LR4 = 0x1A,
1873 IAVF_PHY_TYPE_1000BASE_SX = 0x1B,
1874 IAVF_PHY_TYPE_1000BASE_LX = 0x1C,
1875 IAVF_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D,
1876 IAVF_PHY_TYPE_20GBASE_KR2 = 0x1E,
1877 IAVF_PHY_TYPE_25GBASE_KR = 0x1F,
1878 IAVF_PHY_TYPE_25GBASE_CR = 0x20,
1879 IAVF_PHY_TYPE_25GBASE_SR = 0x21,
1880 IAVF_PHY_TYPE_25GBASE_LR = 0x22,
1881 IAVF_PHY_TYPE_25GBASE_AOC = 0x23,
1882 IAVF_PHY_TYPE_25GBASE_ACC = 0x24,
1884 IAVF_PHY_TYPE_NOT_SUPPORTED_HIGH_TEMP = 0xFD,
1885 IAVF_PHY_TYPE_EMPTY = 0xFE,
1886 IAVF_PHY_TYPE_DEFAULT = 0xFF,
1889 #define IAVF_LINK_SPEED_100MB_SHIFT 0x1
1890 #define IAVF_LINK_SPEED_1000MB_SHIFT 0x2
1891 #define IAVF_LINK_SPEED_10GB_SHIFT 0x3
1892 #define IAVF_LINK_SPEED_40GB_SHIFT 0x4
1893 #define IAVF_LINK_SPEED_20GB_SHIFT 0x5
1894 #define IAVF_LINK_SPEED_25GB_SHIFT 0x6
1896 enum iavf_aq_link_speed {
1897 IAVF_LINK_SPEED_UNKNOWN = 0,
1898 IAVF_LINK_SPEED_100MB = (1 << IAVF_LINK_SPEED_100MB_SHIFT),
1899 IAVF_LINK_SPEED_1GB = (1 << IAVF_LINK_SPEED_1000MB_SHIFT),
1900 IAVF_LINK_SPEED_10GB = (1 << IAVF_LINK_SPEED_10GB_SHIFT),
1901 IAVF_LINK_SPEED_40GB = (1 << IAVF_LINK_SPEED_40GB_SHIFT),
1902 IAVF_LINK_SPEED_20GB = (1 << IAVF_LINK_SPEED_20GB_SHIFT),
1903 IAVF_LINK_SPEED_25GB = (1 << IAVF_LINK_SPEED_25GB_SHIFT),
1906 struct iavf_aqc_module_desc {
1914 IAVF_CHECK_STRUCT_LEN(0x20, iavf_aqc_module_desc);
1916 struct iavf_aq_get_phy_abilities_resp {
1917 __le32 phy_type; /* bitmap using the above enum for offsets */
1918 u8 link_speed; /* bitmap using the above enum bit patterns */
1920 #define IAVF_AQ_PHY_FLAG_PAUSE_TX 0x01
1921 #define IAVF_AQ_PHY_FLAG_PAUSE_RX 0x02
1922 #define IAVF_AQ_PHY_FLAG_LOW_POWER 0x04
1923 #define IAVF_AQ_PHY_LINK_ENABLED 0x08
1924 #define IAVF_AQ_PHY_AN_ENABLED 0x10
1925 #define IAVF_AQ_PHY_FLAG_MODULE_QUAL 0x20
1926 #define IAVF_AQ_PHY_FEC_ABILITY_KR 0x40
1927 #define IAVF_AQ_PHY_FEC_ABILITY_RS 0x80
1928 __le16 eee_capability;
1929 #define IAVF_AQ_EEE_100BASE_TX 0x0002
1930 #define IAVF_AQ_EEE_1000BASE_T 0x0004
1931 #define IAVF_AQ_EEE_10GBASE_T 0x0008
1932 #define IAVF_AQ_EEE_1000BASE_KX 0x0010
1933 #define IAVF_AQ_EEE_10GBASE_KX4 0x0020
1934 #define IAVF_AQ_EEE_10GBASE_KR 0x0040
1937 #define IAVF_AQ_SET_PHY_D3_LPAN_ENA 0x01
1939 #define IAVF_AQ_PHY_TYPE_EXT_25G_KR 0x01
1940 #define IAVF_AQ_PHY_TYPE_EXT_25G_CR 0x02
1941 #define IAVF_AQ_PHY_TYPE_EXT_25G_SR 0x04
1942 #define IAVF_AQ_PHY_TYPE_EXT_25G_LR 0x08
1943 #define IAVF_AQ_PHY_TYPE_EXT_25G_AOC 0x10
1944 #define IAVF_AQ_PHY_TYPE_EXT_25G_ACC 0x20
1945 u8 fec_cfg_curr_mod_ext_info;
1946 #define IAVF_AQ_ENABLE_FEC_KR 0x01
1947 #define IAVF_AQ_ENABLE_FEC_RS 0x02
1948 #define IAVF_AQ_REQUEST_FEC_KR 0x04
1949 #define IAVF_AQ_REQUEST_FEC_RS 0x08
1950 #define IAVF_AQ_ENABLE_FEC_AUTO 0x10
1952 #define IAVF_AQ_MODULE_TYPE_EXT_MASK 0xE0
1953 #define IAVF_AQ_MODULE_TYPE_EXT_SHIFT 5
1958 u8 qualified_module_count;
1959 #define IAVF_AQ_PHY_MAX_QMS 16
1960 struct iavf_aqc_module_desc qualified_module[IAVF_AQ_PHY_MAX_QMS];
1963 IAVF_CHECK_STRUCT_LEN(0x218, iavf_aq_get_phy_abilities_resp);
1965 /* Set PHY Config (direct 0x0601) */
1966 struct iavf_aq_set_phy_config { /* same bits as above in all */
1970 /* bits 0-2 use the values from get_phy_abilities_resp */
1971 #define IAVF_AQ_PHY_ENABLE_LINK 0x08
1972 #define IAVF_AQ_PHY_ENABLE_AN 0x10
1973 #define IAVF_AQ_PHY_ENABLE_ATOMIC_LINK 0x20
1974 __le16 eee_capability;
1979 #define IAVF_AQ_SET_FEC_ABILITY_KR BIT(0)
1980 #define IAVF_AQ_SET_FEC_ABILITY_RS BIT(1)
1981 #define IAVF_AQ_SET_FEC_REQUEST_KR BIT(2)
1982 #define IAVF_AQ_SET_FEC_REQUEST_RS BIT(3)
1983 #define IAVF_AQ_SET_FEC_AUTO BIT(4)
1984 #define IAVF_AQ_PHY_FEC_CONFIG_SHIFT 0x0
1985 #define IAVF_AQ_PHY_FEC_CONFIG_MASK (0x1F << IAVF_AQ_PHY_FEC_CONFIG_SHIFT)
1989 IAVF_CHECK_CMD_LENGTH(iavf_aq_set_phy_config);
1991 /* Set MAC Config command data structure (direct 0x0603) */
1992 struct iavf_aq_set_mac_config {
1993 __le16 max_frame_size;
1995 #define IAVF_AQ_SET_MAC_CONFIG_CRC_EN 0x04
1996 #define IAVF_AQ_SET_MAC_CONFIG_PACING_MASK 0x78
1997 #define IAVF_AQ_SET_MAC_CONFIG_PACING_SHIFT 3
1998 #define IAVF_AQ_SET_MAC_CONFIG_PACING_NONE 0x0
1999 #define IAVF_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF
2000 #define IAVF_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9
2001 #define IAVF_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8
2002 #define IAVF_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7
2003 #define IAVF_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6
2004 #define IAVF_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5
2005 #define IAVF_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4
2006 #define IAVF_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3
2007 #define IAVF_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2
2008 #define IAVF_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1
2009 u8 tx_timer_priority; /* bitmap */
2010 __le16 tx_timer_value;
2011 __le16 fc_refresh_threshold;
2015 IAVF_CHECK_CMD_LENGTH(iavf_aq_set_mac_config);
2017 /* Restart Auto-Negotiation (direct 0x605) */
2018 struct iavf_aqc_set_link_restart_an {
2020 #define IAVF_AQ_PHY_RESTART_AN 0x02
2021 #define IAVF_AQ_PHY_LINK_ENABLE 0x04
2025 IAVF_CHECK_CMD_LENGTH(iavf_aqc_set_link_restart_an);
2027 /* Get Link Status cmd & response data structure (direct 0x0607) */
2028 struct iavf_aqc_get_link_status {
2029 __le16 command_flags; /* only field set on command */
2030 #define IAVF_AQ_LSE_MASK 0x3
2031 #define IAVF_AQ_LSE_NOP 0x0
2032 #define IAVF_AQ_LSE_DISABLE 0x2
2033 #define IAVF_AQ_LSE_ENABLE 0x3
2034 /* only response uses this flag */
2035 #define IAVF_AQ_LSE_IS_ENABLED 0x1
2036 u8 phy_type; /* iavf_aq_phy_type */
2037 u8 link_speed; /* iavf_aq_link_speed */
2039 #define IAVF_AQ_LINK_UP 0x01 /* obsolete */
2040 #define IAVF_AQ_LINK_UP_FUNCTION 0x01
2041 #define IAVF_AQ_LINK_FAULT 0x02
2042 #define IAVF_AQ_LINK_FAULT_TX 0x04
2043 #define IAVF_AQ_LINK_FAULT_RX 0x08
2044 #define IAVF_AQ_LINK_FAULT_REMOTE 0x10
2045 #define IAVF_AQ_LINK_UP_PORT 0x20
2046 #define IAVF_AQ_MEDIA_AVAILABLE 0x40
2047 #define IAVF_AQ_SIGNAL_DETECT 0x80
2049 #define IAVF_AQ_AN_COMPLETED 0x01
2050 #define IAVF_AQ_LP_AN_ABILITY 0x02
2051 #define IAVF_AQ_PD_FAULT 0x04
2052 #define IAVF_AQ_FEC_EN 0x08
2053 #define IAVF_AQ_PHY_LOW_POWER 0x10
2054 #define IAVF_AQ_LINK_PAUSE_TX 0x20
2055 #define IAVF_AQ_LINK_PAUSE_RX 0x40
2056 #define IAVF_AQ_QUALIFIED_MODULE 0x80
2058 #define IAVF_AQ_LINK_PHY_TEMP_ALARM 0x01
2059 #define IAVF_AQ_LINK_XCESSIVE_ERRORS 0x02
2060 #define IAVF_AQ_LINK_TX_SHIFT 0x02
2061 #define IAVF_AQ_LINK_TX_MASK (0x03 << IAVF_AQ_LINK_TX_SHIFT)
2062 #define IAVF_AQ_LINK_TX_ACTIVE 0x00
2063 #define IAVF_AQ_LINK_TX_DRAINED 0x01
2064 #define IAVF_AQ_LINK_TX_FLUSHED 0x03
2065 #define IAVF_AQ_LINK_FORCED_40G 0x10
2066 /* 25G Error Codes */
2067 #define IAVF_AQ_25G_NO_ERR 0X00
2068 #define IAVF_AQ_25G_NOT_PRESENT 0X01
2069 #define IAVF_AQ_25G_NVM_CRC_ERR 0X02
2070 #define IAVF_AQ_25G_SBUS_UCODE_ERR 0X03
2071 #define IAVF_AQ_25G_SERDES_UCODE_ERR 0X04
2072 #define IAVF_AQ_25G_NIMB_UCODE_ERR 0X05
2073 u8 loopback; /* use defines from iavf_aqc_set_lb_mode */
2074 /* Since firmware API 1.7 loopback field keeps power class info as well */
2075 #define IAVF_AQ_LOOPBACK_MASK 0x07
2076 #define IAVF_AQ_PWR_CLASS_SHIFT_LB 6
2077 #define IAVF_AQ_PWR_CLASS_MASK_LB (0x03 << IAVF_AQ_PWR_CLASS_SHIFT_LB)
2078 __le16 max_frame_size;
2080 #define IAVF_AQ_CONFIG_FEC_KR_ENA 0x01
2081 #define IAVF_AQ_CONFIG_FEC_RS_ENA 0x02
2082 #define IAVF_AQ_CONFIG_CRC_ENA 0x04
2083 #define IAVF_AQ_CONFIG_PACING_MASK 0x78
2087 #define IAVF_AQ_LINK_POWER_CLASS_1 0x00
2088 #define IAVF_AQ_LINK_POWER_CLASS_2 0x01
2089 #define IAVF_AQ_LINK_POWER_CLASS_3 0x02
2090 #define IAVF_AQ_LINK_POWER_CLASS_4 0x03
2091 #define IAVF_AQ_PWR_CLASS_MASK 0x03
2101 IAVF_CHECK_CMD_LENGTH(iavf_aqc_get_link_status);
2103 /* Set event mask command (direct 0x613) */
2104 struct iavf_aqc_set_phy_int_mask {
2107 #define IAVF_AQ_EVENT_LINK_UPDOWN 0x0002
2108 #define IAVF_AQ_EVENT_MEDIA_NA 0x0004
2109 #define IAVF_AQ_EVENT_LINK_FAULT 0x0008
2110 #define IAVF_AQ_EVENT_PHY_TEMP_ALARM 0x0010
2111 #define IAVF_AQ_EVENT_EXCESSIVE_ERRORS 0x0020
2112 #define IAVF_AQ_EVENT_SIGNAL_DETECT 0x0040
2113 #define IAVF_AQ_EVENT_AN_COMPLETED 0x0080
2114 #define IAVF_AQ_EVENT_MODULE_QUAL_FAIL 0x0100
2115 #define IAVF_AQ_EVENT_PORT_TX_SUSPENDED 0x0200
2119 IAVF_CHECK_CMD_LENGTH(iavf_aqc_set_phy_int_mask);
2121 /* Get Local AN advt register (direct 0x0614)
2122 * Set Local AN advt register (direct 0x0615)
2123 * Get Link Partner AN advt register (direct 0x0616)
2125 struct iavf_aqc_an_advt_reg {
2126 __le32 local_an_reg0;
2127 __le16 local_an_reg1;
2131 IAVF_CHECK_CMD_LENGTH(iavf_aqc_an_advt_reg);
2133 /* Set Loopback mode (0x0618) */
2134 struct iavf_aqc_set_lb_mode {
2136 #define IAVF_AQ_LB_NONE 0
2137 #define IAVF_AQ_LB_MAC 1
2138 #define IAVF_AQ_LB_SERDES 2
2139 #define IAVF_AQ_LB_PHY_INT 3
2140 #define IAVF_AQ_LB_PHY_EXT 4
2141 #define IAVF_AQ_LB_CPVL_PCS 5
2142 #define IAVF_AQ_LB_CPVL_EXT 6
2143 #define IAVF_AQ_LB_PHY_LOCAL 0x01
2144 #define IAVF_AQ_LB_PHY_REMOTE 0x02
2145 #define IAVF_AQ_LB_MAC_LOCAL 0x04
2147 #define IAVF_AQ_LB_LOCAL 0
2148 #define IAVF_AQ_LB_FAR 0x01
2150 #define IAVF_AQ_LB_SPEED_NONE 0
2151 #define IAVF_AQ_LB_SPEED_1G 1
2152 #define IAVF_AQ_LB_SPEED_10G 2
2153 #define IAVF_AQ_LB_SPEED_40G 3
2154 #define IAVF_AQ_LB_SPEED_20G 4
2159 IAVF_CHECK_CMD_LENGTH(iavf_aqc_set_lb_mode);
2161 /* Set PHY Debug command (0x0622) */
2162 struct iavf_aqc_set_phy_debug {
2164 #define IAVF_AQ_PHY_DEBUG_RESET_INTERNAL 0x02
2165 #define IAVF_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2
2166 #define IAVF_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \
2167 IAVF_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT)
2168 #define IAVF_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00
2169 #define IAVF_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01
2170 #define IAVF_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02
2171 /* Disable link manageability on a single port */
2172 #define IAVF_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10
2173 /* Disable link manageability on all ports needs both bits 4 and 5 */
2174 #define IAVF_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW 0x20
2178 IAVF_CHECK_CMD_LENGTH(iavf_aqc_set_phy_debug);
2180 enum iavf_aq_phy_reg_type {
2181 IAVF_AQC_PHY_REG_INTERNAL = 0x1,
2182 IAVF_AQC_PHY_REG_EXERNAL_BASET = 0x2,
2183 IAVF_AQC_PHY_REG_EXERNAL_MODULE = 0x3
2186 /* Run PHY Activity (0x0626) */
2187 struct iavf_aqc_run_phy_activity {
2196 IAVF_CHECK_CMD_LENGTH(iavf_aqc_run_phy_activity);
2198 /* Set PHY Register command (0x0628) */
2199 /* Get PHY Register command (0x0629) */
2200 struct iavf_aqc_phy_register_access {
2202 #define IAVF_AQ_PHY_REG_ACCESS_INTERNAL 0
2203 #define IAVF_AQ_PHY_REG_ACCESS_EXTERNAL 1
2204 #define IAVF_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE 2
2212 IAVF_CHECK_CMD_LENGTH(iavf_aqc_phy_register_access);
2214 /* NVM Read command (indirect 0x0701)
2215 * NVM Erase commands (direct 0x0702)
2216 * NVM Update commands (indirect 0x0703)
2218 struct iavf_aqc_nvm_update {
2220 #define IAVF_AQ_NVM_LAST_CMD 0x01
2221 #define IAVF_AQ_NVM_FLASH_ONLY 0x80
2222 #define IAVF_AQ_NVM_PRESERVATION_FLAGS_SHIFT 1
2223 #define IAVF_AQ_NVM_PRESERVATION_FLAGS_MASK 0x03
2224 #define IAVF_AQ_NVM_PRESERVATION_FLAGS_SELECTED 0x03
2225 #define IAVF_AQ_NVM_PRESERVATION_FLAGS_ALL 0x01
2233 IAVF_CHECK_CMD_LENGTH(iavf_aqc_nvm_update);
2235 /* NVM Config Read (indirect 0x0704) */
2236 struct iavf_aqc_nvm_config_read {
2238 #define IAVF_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1
2239 #define IAVF_AQ_ANVM_READ_SINGLE_FEATURE 0
2240 #define IAVF_AQ_ANVM_READ_MULTIPLE_FEATURES 1
2241 __le16 element_count;
2242 __le16 element_id; /* Feature/field ID */
2243 __le16 element_id_msw; /* MSWord of field ID */
2244 __le32 address_high;
2248 IAVF_CHECK_CMD_LENGTH(iavf_aqc_nvm_config_read);
2250 /* NVM Config Write (indirect 0x0705) */
2251 struct iavf_aqc_nvm_config_write {
2253 __le16 element_count;
2255 __le32 address_high;
2259 IAVF_CHECK_CMD_LENGTH(iavf_aqc_nvm_config_write);
2261 /* Used for 0x0704 as well as for 0x0705 commands */
2262 #define IAVF_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1
2263 #define IAVF_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK \
2264 (1 << IAVF_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT)
2265 #define IAVF_AQ_ANVM_FEATURE 0
2266 #define IAVF_AQ_ANVM_IMMEDIATE_FIELD (1 << FEATURE_OR_IMMEDIATE_SHIFT)
2267 struct iavf_aqc_nvm_config_data_feature {
2269 #define IAVF_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01
2270 #define IAVF_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08
2271 #define IAVF_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10
2272 __le16 feature_options;
2273 __le16 feature_selection;
2276 IAVF_CHECK_STRUCT_LEN(0x6, iavf_aqc_nvm_config_data_feature);
2278 struct iavf_aqc_nvm_config_data_immediate_field {
2281 __le16 field_options;
2285 IAVF_CHECK_STRUCT_LEN(0xc, iavf_aqc_nvm_config_data_immediate_field);
2287 /* OEM Post Update (indirect 0x0720)
2288 * no command data struct used
2290 struct iavf_aqc_nvm_oem_post_update {
2291 #define IAVF_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA 0x01
2296 IAVF_CHECK_STRUCT_LEN(0x8, iavf_aqc_nvm_oem_post_update);
2298 struct iavf_aqc_nvm_oem_post_update_buffer {
2305 IAVF_CHECK_STRUCT_LEN(0x28, iavf_aqc_nvm_oem_post_update_buffer);
2307 /* Thermal Sensor (indirect 0x0721)
2308 * read or set thermal sensor configs and values
2309 * takes a sensor and command specific data buffer, not detailed here
2311 struct iavf_aqc_thermal_sensor {
2313 #define IAVF_AQ_THERMAL_SENSOR_READ_CONFIG 0
2314 #define IAVF_AQ_THERMAL_SENSOR_SET_CONFIG 1
2315 #define IAVF_AQ_THERMAL_SENSOR_READ_TEMP 2
2321 IAVF_CHECK_CMD_LENGTH(iavf_aqc_thermal_sensor);
2323 /* Send to PF command (indirect 0x0801) id is only used by PF
2324 * Send to VF command (indirect 0x0802) id is only used by PF
2325 * Send to Peer PF command (indirect 0x0803)
2327 struct iavf_aqc_pf_vf_message {
2334 IAVF_CHECK_CMD_LENGTH(iavf_aqc_pf_vf_message);
2336 /* Alternate structure */
2338 /* Direct write (direct 0x0900)
2339 * Direct read (direct 0x0902)
2341 struct iavf_aqc_alternate_write {
2348 IAVF_CHECK_CMD_LENGTH(iavf_aqc_alternate_write);
2350 /* Indirect write (indirect 0x0901)
2351 * Indirect read (indirect 0x0903)
2354 struct iavf_aqc_alternate_ind_write {
2361 IAVF_CHECK_CMD_LENGTH(iavf_aqc_alternate_ind_write);
2363 /* Done alternate write (direct 0x0904)
2366 struct iavf_aqc_alternate_write_done {
2368 #define IAVF_AQ_ALTERNATE_MODE_BIOS_MASK 1
2369 #define IAVF_AQ_ALTERNATE_MODE_BIOS_LEGACY 0
2370 #define IAVF_AQ_ALTERNATE_MODE_BIOS_UEFI 1
2371 #define IAVF_AQ_ALTERNATE_RESET_NEEDED 2
2375 IAVF_CHECK_CMD_LENGTH(iavf_aqc_alternate_write_done);
2377 /* Set OEM mode (direct 0x0905) */
2378 struct iavf_aqc_alternate_set_mode {
2380 #define IAVF_AQ_ALTERNATE_MODE_NONE 0
2381 #define IAVF_AQ_ALTERNATE_MODE_OEM 1
2385 IAVF_CHECK_CMD_LENGTH(iavf_aqc_alternate_set_mode);
2387 /* Clear port Alternate RAM (direct 0x0906) uses iavf_aq_desc */
2389 /* async events 0x10xx */
2391 /* Lan Queue Overflow Event (direct, 0x1001) */
2392 struct iavf_aqc_lan_overflow {
2393 __le32 prtdcb_rupto;
2398 IAVF_CHECK_CMD_LENGTH(iavf_aqc_lan_overflow);
2400 /* Get LLDP MIB (indirect 0x0A00) */
2401 struct iavf_aqc_lldp_get_mib {
2404 #define IAVF_AQ_LLDP_MIB_TYPE_MASK 0x3
2405 #define IAVF_AQ_LLDP_MIB_LOCAL 0x0
2406 #define IAVF_AQ_LLDP_MIB_REMOTE 0x1
2407 #define IAVF_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2
2408 #define IAVF_AQ_LLDP_BRIDGE_TYPE_MASK 0xC
2409 #define IAVF_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2
2410 #define IAVF_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0
2411 #define IAVF_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1
2412 #define IAVF_AQ_LLDP_TX_SHIFT 0x4
2413 #define IAVF_AQ_LLDP_TX_MASK (0x03 << IAVF_AQ_LLDP_TX_SHIFT)
2414 /* TX pause flags use IAVF_AQ_LINK_TX_* above */
2422 IAVF_CHECK_CMD_LENGTH(iavf_aqc_lldp_get_mib);
2424 /* Configure LLDP MIB Change Event (direct 0x0A01)
2425 * also used for the event (with type in the command field)
2427 struct iavf_aqc_lldp_update_mib {
2429 #define IAVF_AQ_LLDP_MIB_UPDATE_ENABLE 0x0
2430 #define IAVF_AQ_LLDP_MIB_UPDATE_DISABLE 0x1
2436 IAVF_CHECK_CMD_LENGTH(iavf_aqc_lldp_update_mib);
2438 /* Add LLDP TLV (indirect 0x0A02)
2439 * Delete LLDP TLV (indirect 0x0A04)
2441 struct iavf_aqc_lldp_add_tlv {
2442 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
2450 IAVF_CHECK_CMD_LENGTH(iavf_aqc_lldp_add_tlv);
2452 /* Update LLDP TLV (indirect 0x0A03) */
2453 struct iavf_aqc_lldp_update_tlv {
2454 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
2463 IAVF_CHECK_CMD_LENGTH(iavf_aqc_lldp_update_tlv);
2465 /* Stop LLDP (direct 0x0A05) */
2466 struct iavf_aqc_lldp_stop {
2468 #define IAVF_AQ_LLDP_AGENT_STOP 0x0
2469 #define IAVF_AQ_LLDP_AGENT_SHUTDOWN 0x1
2473 IAVF_CHECK_CMD_LENGTH(iavf_aqc_lldp_stop);
2475 /* Start LLDP (direct 0x0A06) */
2477 struct iavf_aqc_lldp_start {
2479 #define IAVF_AQ_LLDP_AGENT_START 0x1
2483 IAVF_CHECK_CMD_LENGTH(iavf_aqc_lldp_start);
2485 /* Set DCB (direct 0x0303) */
2486 struct iavf_aqc_set_dcb_parameters {
2488 #define IAVF_AQ_DCB_SET_AGENT 0x1
2489 #define IAVF_DCB_VALID 0x1
2494 IAVF_CHECK_CMD_LENGTH(iavf_aqc_set_dcb_parameters);
2496 /* Get CEE DCBX Oper Config (0x0A07)
2497 * uses the generic descriptor struct
2498 * returns below as indirect response
2501 #define IAVF_AQC_CEE_APP_FCOE_SHIFT 0x0
2502 #define IAVF_AQC_CEE_APP_FCOE_MASK (0x7 << IAVF_AQC_CEE_APP_FCOE_SHIFT)
2503 #define IAVF_AQC_CEE_APP_ISCSI_SHIFT 0x3
2504 #define IAVF_AQC_CEE_APP_ISCSI_MASK (0x7 << IAVF_AQC_CEE_APP_ISCSI_SHIFT)
2505 #define IAVF_AQC_CEE_APP_FIP_SHIFT 0x8
2506 #define IAVF_AQC_CEE_APP_FIP_MASK (0x7 << IAVF_AQC_CEE_APP_FIP_SHIFT)
2508 #define IAVF_AQC_CEE_PG_STATUS_SHIFT 0x0
2509 #define IAVF_AQC_CEE_PG_STATUS_MASK (0x7 << IAVF_AQC_CEE_PG_STATUS_SHIFT)
2510 #define IAVF_AQC_CEE_PFC_STATUS_SHIFT 0x3
2511 #define IAVF_AQC_CEE_PFC_STATUS_MASK (0x7 << IAVF_AQC_CEE_PFC_STATUS_SHIFT)
2512 #define IAVF_AQC_CEE_APP_STATUS_SHIFT 0x8
2513 #define IAVF_AQC_CEE_APP_STATUS_MASK (0x7 << IAVF_AQC_CEE_APP_STATUS_SHIFT)
2514 #define IAVF_AQC_CEE_FCOE_STATUS_SHIFT 0x8
2515 #define IAVF_AQC_CEE_FCOE_STATUS_MASK (0x7 << IAVF_AQC_CEE_FCOE_STATUS_SHIFT)
2516 #define IAVF_AQC_CEE_ISCSI_STATUS_SHIFT 0xB
2517 #define IAVF_AQC_CEE_ISCSI_STATUS_MASK (0x7 << IAVF_AQC_CEE_ISCSI_STATUS_SHIFT)
2518 #define IAVF_AQC_CEE_FIP_STATUS_SHIFT 0x10
2519 #define IAVF_AQC_CEE_FIP_STATUS_MASK (0x7 << IAVF_AQC_CEE_FIP_STATUS_SHIFT)
2521 /* struct iavf_aqc_get_cee_dcb_cfg_v1_resp was originally defined with
2522 * word boundary layout issues, which the Linux compilers silently deal
2523 * with by adding padding, making the actual struct larger than designed.
2524 * However, the FW compiler for the NIC is less lenient and complains
2525 * about the struct. Hence, the struct defined here has an extra byte in
2526 * fields reserved3 and reserved4 to directly acknowledge that padding,
2527 * and the new length is used in the length check macro.
2529 struct iavf_aqc_get_cee_dcb_cfg_v1_resp {
2537 __le16 oper_app_prio;
2542 IAVF_CHECK_STRUCT_LEN(0x18, iavf_aqc_get_cee_dcb_cfg_v1_resp);
2544 struct iavf_aqc_get_cee_dcb_cfg_resp {
2549 __le16 oper_app_prio;
2554 IAVF_CHECK_STRUCT_LEN(0x20, iavf_aqc_get_cee_dcb_cfg_resp);
2556 /* Set Local LLDP MIB (indirect 0x0A08)
2557 * Used to replace the local MIB of a given LLDP agent. e.g. DCBx
2559 struct iavf_aqc_lldp_set_local_mib {
2560 #define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT 0
2561 #define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK (1 << \
2562 SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT)
2563 #define SET_LOCAL_MIB_AC_TYPE_LOCAL_MIB 0x0
2564 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT (1)
2565 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_MASK (1 << \
2566 SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT)
2567 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS 0x1
2572 __le32 address_high;
2576 IAVF_CHECK_CMD_LENGTH(iavf_aqc_lldp_set_local_mib);
2578 struct iavf_aqc_lldp_set_local_mib_resp {
2579 #define SET_LOCAL_MIB_RESP_EVENT_TRIGGERED_MASK 0x01
2584 IAVF_CHECK_STRUCT_LEN(0x10, iavf_aqc_lldp_set_local_mib_resp);
2586 /* Stop/Start LLDP Agent (direct 0x0A09)
2587 * Used for stopping/starting specific LLDP agent. e.g. DCBx
2589 struct iavf_aqc_lldp_stop_start_specific_agent {
2590 #define IAVF_AQC_START_SPECIFIC_AGENT_SHIFT 0
2591 #define IAVF_AQC_START_SPECIFIC_AGENT_MASK \
2592 (1 << IAVF_AQC_START_SPECIFIC_AGENT_SHIFT)
2597 IAVF_CHECK_CMD_LENGTH(iavf_aqc_lldp_stop_start_specific_agent);
2599 /* Add Udp Tunnel command and completion (direct 0x0B00) */
2600 struct iavf_aqc_add_udp_tunnel {
2604 #define IAVF_AQC_TUNNEL_TYPE_VXLAN 0x00
2605 #define IAVF_AQC_TUNNEL_TYPE_NGE 0x01
2606 #define IAVF_AQC_TUNNEL_TYPE_TEREDO 0x10
2607 #define IAVF_AQC_TUNNEL_TYPE_VXLAN_GPE 0x11
2611 IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_udp_tunnel);
2613 struct iavf_aqc_add_udp_tunnel_completion {
2615 u8 filter_entry_index;
2617 #define IAVF_AQC_SINGLE_PF 0x0
2618 #define IAVF_AQC_MULTIPLE_PFS 0x1
2623 IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_udp_tunnel_completion);
2625 /* remove UDP Tunnel command (0x0B01) */
2626 struct iavf_aqc_remove_udp_tunnel {
2628 u8 index; /* 0 to 15 */
2632 IAVF_CHECK_CMD_LENGTH(iavf_aqc_remove_udp_tunnel);
2634 struct iavf_aqc_del_udp_tunnel_completion {
2636 u8 index; /* 0 to 15 */
2638 u8 total_filters_used;
2642 IAVF_CHECK_CMD_LENGTH(iavf_aqc_del_udp_tunnel_completion);
2644 struct iavf_aqc_get_set_rss_key {
2645 #define IAVF_AQC_SET_RSS_KEY_VSI_VALID (0x1 << 15)
2646 #define IAVF_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0
2647 #define IAVF_AQC_SET_RSS_KEY_VSI_ID_MASK (0x3FF << \
2648 IAVF_AQC_SET_RSS_KEY_VSI_ID_SHIFT)
2655 IAVF_CHECK_CMD_LENGTH(iavf_aqc_get_set_rss_key);
2657 struct iavf_aqc_get_set_rss_key_data {
2658 u8 standard_rss_key[0x28];
2659 u8 extended_hash_key[0xc];
2662 IAVF_CHECK_STRUCT_LEN(0x34, iavf_aqc_get_set_rss_key_data);
2664 struct iavf_aqc_get_set_rss_lut {
2665 #define IAVF_AQC_SET_RSS_LUT_VSI_VALID (0x1 << 15)
2666 #define IAVF_AQC_SET_RSS_LUT_VSI_ID_SHIFT 0
2667 #define IAVF_AQC_SET_RSS_LUT_VSI_ID_MASK (0x3FF << \
2668 IAVF_AQC_SET_RSS_LUT_VSI_ID_SHIFT)
2670 #define IAVF_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT 0
2671 #define IAVF_AQC_SET_RSS_LUT_TABLE_TYPE_MASK (0x1 << \
2672 IAVF_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT)
2674 #define IAVF_AQC_SET_RSS_LUT_TABLE_TYPE_VSI 0
2675 #define IAVF_AQC_SET_RSS_LUT_TABLE_TYPE_PF 1
2682 IAVF_CHECK_CMD_LENGTH(iavf_aqc_get_set_rss_lut);
2684 /* tunnel key structure 0x0B10 */
2686 struct iavf_aqc_tunnel_key_structure {
2689 u8 key1_len; /* 0 to 15 */
2690 u8 key2_len; /* 0 to 15 */
2692 #define IAVF_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01
2693 /* response flags */
2694 #define IAVF_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01
2695 #define IAVF_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02
2696 #define IAVF_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03
2697 u8 network_key_index;
2698 #define IAVF_AQC_NETWORK_KEY_INDEX_VXLAN 0x0
2699 #define IAVF_AQC_NETWORK_KEY_INDEX_NGE 0x1
2700 #define IAVF_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2
2701 #define IAVF_AQC_NETWORK_KEY_INDEX_GRE 0x3
2705 IAVF_CHECK_CMD_LENGTH(iavf_aqc_tunnel_key_structure);
2707 /* OEM mode commands (direct 0xFE0x) */
2708 struct iavf_aqc_oem_param_change {
2710 #define IAVF_AQ_OEM_PARAM_TYPE_PF_CTL 0
2711 #define IAVF_AQ_OEM_PARAM_TYPE_BW_CTL 1
2712 #define IAVF_AQ_OEM_PARAM_MAC 2
2713 __le32 param_value1;
2714 __le16 param_value2;
2718 IAVF_CHECK_CMD_LENGTH(iavf_aqc_oem_param_change);
2720 struct iavf_aqc_oem_state_change {
2722 #define IAVF_AQ_OEM_STATE_LINK_DOWN 0x0
2723 #define IAVF_AQ_OEM_STATE_LINK_UP 0x1
2727 IAVF_CHECK_CMD_LENGTH(iavf_aqc_oem_state_change);
2729 /* Initialize OCSD (0xFE02, direct) */
2730 struct iavf_aqc_opc_oem_ocsd_initialize {
2733 __le32 ocsd_memory_block_addr_high;
2734 __le32 ocsd_memory_block_addr_low;
2735 __le32 requested_update_interval;
2738 IAVF_CHECK_CMD_LENGTH(iavf_aqc_opc_oem_ocsd_initialize);
2740 /* Initialize OCBB (0xFE03, direct) */
2741 struct iavf_aqc_opc_oem_ocbb_initialize {
2744 __le32 ocbb_memory_block_addr_high;
2745 __le32 ocbb_memory_block_addr_low;
2749 IAVF_CHECK_CMD_LENGTH(iavf_aqc_opc_oem_ocbb_initialize);
2751 /* debug commands */
2753 /* get device id (0xFF00) uses the generic structure */
2755 /* set test more (0xFF01, internal) */
2757 struct iavf_acq_set_test_mode {
2759 #define IAVF_AQ_TEST_PARTIAL 0
2760 #define IAVF_AQ_TEST_FULL 1
2761 #define IAVF_AQ_TEST_NVM 2
2764 #define IAVF_AQ_TEST_OPEN 0
2765 #define IAVF_AQ_TEST_CLOSE 1
2766 #define IAVF_AQ_TEST_INC 2
2768 __le32 address_high;
2772 IAVF_CHECK_CMD_LENGTH(iavf_acq_set_test_mode);
2774 /* Debug Read Register command (0xFF03)
2775 * Debug Write Register command (0xFF04)
2777 struct iavf_aqc_debug_reg_read_write {
2784 IAVF_CHECK_CMD_LENGTH(iavf_aqc_debug_reg_read_write);
2786 /* Scatter/gather Reg Read (indirect 0xFF05)
2787 * Scatter/gather Reg Write (indirect 0xFF06)
2790 /* iavf_aq_desc is used for the command */
2791 struct iavf_aqc_debug_reg_sg_element_data {
2796 /* Debug Modify register (direct 0xFF07) */
2797 struct iavf_aqc_debug_modify_reg {
2804 IAVF_CHECK_CMD_LENGTH(iavf_aqc_debug_modify_reg);
2806 /* dump internal data (0xFF08, indirect) */
2808 #define IAVF_AQ_CLUSTER_ID_AUX 0
2809 #define IAVF_AQ_CLUSTER_ID_SWITCH_FLU 1
2810 #define IAVF_AQ_CLUSTER_ID_TXSCHED 2
2811 #define IAVF_AQ_CLUSTER_ID_HMC 3
2812 #define IAVF_AQ_CLUSTER_ID_MAC0 4
2813 #define IAVF_AQ_CLUSTER_ID_MAC1 5
2814 #define IAVF_AQ_CLUSTER_ID_MAC2 6
2815 #define IAVF_AQ_CLUSTER_ID_MAC3 7
2816 #define IAVF_AQ_CLUSTER_ID_DCB 8
2817 #define IAVF_AQ_CLUSTER_ID_EMP_MEM 9
2818 #define IAVF_AQ_CLUSTER_ID_PKT_BUF 10
2819 #define IAVF_AQ_CLUSTER_ID_ALTRAM 11
2821 struct iavf_aqc_debug_dump_internals {
2826 __le32 address_high;
2830 IAVF_CHECK_CMD_LENGTH(iavf_aqc_debug_dump_internals);
2832 struct iavf_aqc_debug_modify_internals {
2834 u8 cluster_specific_params[7];
2835 __le32 address_high;
2839 IAVF_CHECK_CMD_LENGTH(iavf_aqc_debug_modify_internals);
2841 #endif /* _IAVF_ADMINQ_CMD_H_ */