1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2013 - 2015 Intel Corporation
8 #include "iavf_status.h"
9 #include "iavf_osdep.h"
10 #include "iavf_register.h"
11 #include "iavf_adminq.h"
12 #include "iavf_devids.h"
14 #define IAVF_RXQ_CTX_DBUFF_SHIFT 7
16 #define UNREFERENCED_XPARAMETER
17 #define UNREFERENCED_1PARAMETER(_p) (_p);
18 #define UNREFERENCED_2PARAMETER(_p, _q) (_p); (_q);
19 #define UNREFERENCED_3PARAMETER(_p, _q, _r) (_p); (_q); (_r);
20 #define UNREFERENCED_4PARAMETER(_p, _q, _r, _s) (_p); (_q); (_r); (_s);
21 #define UNREFERENCED_5PARAMETER(_p, _q, _r, _s, _t) (_p); (_q); (_r); (_s); (_t);
25 #define BIT(a) (1UL << (a))
28 #define BIT_ULL(a) (1ULL << (a))
30 #endif /* LINUX_MACROS */
32 /* IAVF_MASK is a macro used on 32 bit registers */
33 #define IAVF_MASK(mask, shift) (mask << shift)
35 #define IAVF_MAX_PF 16
36 #define IAVF_MAX_PF_VSI 64
37 #define IAVF_MAX_PF_QP 128
38 #define IAVF_MAX_VSI_QP 16
39 #define IAVF_MAX_VF_VSI 3
40 #define IAVF_MAX_CHAINED_RX_BUFFERS 5
42 /* something less than 1 minute */
43 #define IAVF_HEARTBEAT_TIMEOUT (HZ * 50)
46 /* Check whether address is multicast. */
47 #define IAVF_IS_MULTICAST(address) (bool)(((u8 *)(address))[0] & ((u8)0x01))
49 /* Check whether an address is broadcast. */
50 #define IAVF_IS_BROADCAST(address) \
51 ((((u8 *)(address))[0] == ((u8)0xff)) && \
52 (((u8 *)(address))[1] == ((u8)0xff)))
55 /* forward declaration */
57 typedef void (*IAVF_ADMINQ_CALLBACK)(struct iavf_hw *, struct iavf_aq_desc *);
62 /* Data type manipulation macros. */
63 #define IAVF_HI_DWORD(x) ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF))
64 #define IAVF_LO_DWORD(x) ((u32)((x) & 0xFFFFFFFF))
66 #define IAVF_HI_WORD(x) ((u16)(((x) >> 16) & 0xFFFF))
67 #define IAVF_LO_WORD(x) ((u16)((x) & 0xFFFF))
69 #define IAVF_HI_BYTE(x) ((u8)(((x) >> 8) & 0xFF))
70 #define IAVF_LO_BYTE(x) ((u8)((x) & 0xFF))
72 /* Number of Transmit Descriptors must be a multiple of 8. */
73 #define IAVF_REQ_TX_DESCRIPTOR_MULTIPLE 8
74 /* Number of Receive Descriptors must be a multiple of 32 if
75 * the number of descriptors is greater than 32.
77 #define IAVF_REQ_RX_DESCRIPTOR_MULTIPLE 32
79 #define IAVF_DESC_UNUSED(R) \
80 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
81 (R)->next_to_clean - (R)->next_to_use - 1)
83 /* bitfields for Tx queue mapping in QTX_CTL */
84 #define IAVF_QTX_CTL_VF_QUEUE 0x0
85 #define IAVF_QTX_CTL_VM_QUEUE 0x1
86 #define IAVF_QTX_CTL_PF_QUEUE 0x2
88 /* debug masks - set these bits in hw->debug_mask to control output */
89 enum iavf_debug_mask {
90 IAVF_DEBUG_INIT = 0x00000001,
91 IAVF_DEBUG_RELEASE = 0x00000002,
93 IAVF_DEBUG_LINK = 0x00000010,
94 IAVF_DEBUG_PHY = 0x00000020,
95 IAVF_DEBUG_HMC = 0x00000040,
96 IAVF_DEBUG_NVM = 0x00000080,
97 IAVF_DEBUG_LAN = 0x00000100,
98 IAVF_DEBUG_FLOW = 0x00000200,
99 IAVF_DEBUG_DCB = 0x00000400,
100 IAVF_DEBUG_DIAG = 0x00000800,
101 IAVF_DEBUG_FD = 0x00001000,
102 IAVF_DEBUG_PACKAGE = 0x00002000,
104 IAVF_DEBUG_AQ_MESSAGE = 0x01000000,
105 IAVF_DEBUG_AQ_DESCRIPTOR = 0x02000000,
106 IAVF_DEBUG_AQ_DESC_BUFFER = 0x04000000,
107 IAVF_DEBUG_AQ_COMMAND = 0x06000000,
108 IAVF_DEBUG_AQ = 0x0F000000,
110 IAVF_DEBUG_USER = 0xF0000000,
112 IAVF_DEBUG_ALL = 0xFFFFFFFF
116 #define IAVF_PCI_LINK_STATUS 0xB2
117 #define IAVF_PCI_LINK_WIDTH 0x3F0
118 #define IAVF_PCI_LINK_WIDTH_1 0x10
119 #define IAVF_PCI_LINK_WIDTH_2 0x20
120 #define IAVF_PCI_LINK_WIDTH_4 0x40
121 #define IAVF_PCI_LINK_WIDTH_8 0x80
122 #define IAVF_PCI_LINK_SPEED 0xF
123 #define IAVF_PCI_LINK_SPEED_2500 0x1
124 #define IAVF_PCI_LINK_SPEED_5000 0x2
125 #define IAVF_PCI_LINK_SPEED_8000 0x3
127 #define IAVF_MDIO_CLAUSE22_STCODE_MASK IAVF_MASK(1, \
128 IAVF_GLGEN_MSCA_STCODE_SHIFT)
129 #define IAVF_MDIO_CLAUSE22_OPCODE_WRITE_MASK IAVF_MASK(1, \
130 IAVF_GLGEN_MSCA_OPCODE_SHIFT)
131 #define IAVF_MDIO_CLAUSE22_OPCODE_READ_MASK IAVF_MASK(2, \
132 IAVF_GLGEN_MSCA_OPCODE_SHIFT)
134 #define IAVF_MDIO_CLAUSE45_STCODE_MASK IAVF_MASK(0, \
135 IAVF_GLGEN_MSCA_STCODE_SHIFT)
136 #define IAVF_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK IAVF_MASK(0, \
137 IAVF_GLGEN_MSCA_OPCODE_SHIFT)
138 #define IAVF_MDIO_CLAUSE45_OPCODE_WRITE_MASK IAVF_MASK(1, \
139 IAVF_GLGEN_MSCA_OPCODE_SHIFT)
140 #define IAVF_MDIO_CLAUSE45_OPCODE_READ_INC_ADDR_MASK IAVF_MASK(2, \
141 IAVF_GLGEN_MSCA_OPCODE_SHIFT)
142 #define IAVF_MDIO_CLAUSE45_OPCODE_READ_MASK IAVF_MASK(3, \
143 IAVF_GLGEN_MSCA_OPCODE_SHIFT)
145 #define IAVF_PHY_COM_REG_PAGE 0x1E
146 #define IAVF_PHY_LED_LINK_MODE_MASK 0xF0
147 #define IAVF_PHY_LED_MANUAL_ON 0x100
148 #define IAVF_PHY_LED_PROV_REG_1 0xC430
149 #define IAVF_PHY_LED_MODE_MASK 0xFFFF
150 #define IAVF_PHY_LED_MODE_ORIG 0x80000000
153 enum iavf_memset_type {
159 enum iavf_memcpy_type {
160 IAVF_NONDMA_TO_NONDMA = 0,
166 /* These are structs for managing the hardware information and the operations.
167 * The structures of function pointers are filled out at init time when we
168 * know for sure exactly which hardware we're working with. This gives us the
169 * flexibility of using the same main driver code but adapting to slightly
170 * different hardware needs as new parts are developed. For this architecture,
171 * the Firmware and AdminQ are intended to insulate the driver from most of the
172 * future changes, but these structures will also do part of the job.
175 IAVF_MAC_UNKNOWN = 0,
192 IAVF_VSI_TYPE_UNKNOWN
195 enum iavf_queue_type {
196 IAVF_QUEUE_TYPE_RX = 0,
198 IAVF_QUEUE_TYPE_PE_CEQ,
199 IAVF_QUEUE_TYPE_UNKNOWN
202 #define IAVF_HW_CAP_MAX_GPIO 30
203 #define IAVF_HW_CAP_MDIO_PORT_MODE_MDIO 0
204 #define IAVF_HW_CAP_MDIO_PORT_MODE_I2C 1
206 enum iavf_acpi_programming_method {
207 IAVF_ACPI_PROGRAMMING_METHOD_HW_FVL = 0,
208 IAVF_ACPI_PROGRAMMING_METHOD_AQC_FPK = 1
211 #define IAVF_WOL_SUPPORT_MASK 0x1
212 #define IAVF_ACPI_PROGRAMMING_METHOD_MASK 0x2
213 #define IAVF_PROXY_SUPPORT_MASK 0x4
215 /* Capabilities of a PF or a VF or the whole device */
216 struct iavf_hw_capabilities {
217 /* Cloud filter modes:
218 * Mode1: Filter on L4 port only
219 * Mode2: Filter for non-tunneled traffic
220 * Mode3: Filter for tunnel traffic
222 #define IAVF_CLOUD_FILTER_MODE1 0x6
223 #define IAVF_CLOUD_FILTER_MODE2 0x7
224 #define IAVF_CLOUD_FILTER_MODE3 0x8
225 #define IAVF_SWITCH_MODE_MASK 0xF
234 u32 num_msix_vectors_vf;
235 bool apm_wol_support;
236 enum iavf_acpi_programming_method acpi_prog_method;
240 struct iavf_mac_info {
241 enum iavf_mac_type type;
243 u8 perm_addr[ETH_ALEN];
244 u8 san_addr[ETH_ALEN];
245 u8 port_addr[ETH_ALEN];
249 #define IAVF_NVM_EXEC_GET_AQ_RESULT 0x0
250 #define IAVF_NVM_EXEC_FEATURES 0xe
251 #define IAVF_NVM_EXEC_STATUS 0xf
253 /* NVMUpdate features API */
254 #define IAVF_NVMUPD_FEATURES_API_VER_MAJOR 0
255 #define IAVF_NVMUPD_FEATURES_API_VER_MINOR 14
256 #define IAVF_NVMUPD_FEATURES_API_FEATURES_ARRAY_LEN 12
258 #define IAVF_NVMUPD_FEATURE_FLAT_NVM_SUPPORT BIT(0)
260 struct iavf_nvmupd_features {
264 u8 features[IAVF_NVMUPD_FEATURES_API_FEATURES_ARRAY_LEN];
267 #define IAVF_MODULE_SFF_DIAG_CAPAB 0x40
270 iavf_bus_type_unknown = 0,
273 iavf_bus_type_pci_express,
274 iavf_bus_type_reserved
278 enum iavf_bus_speed {
279 iavf_bus_speed_unknown = 0,
280 iavf_bus_speed_33 = 33,
281 iavf_bus_speed_66 = 66,
282 iavf_bus_speed_100 = 100,
283 iavf_bus_speed_120 = 120,
284 iavf_bus_speed_133 = 133,
285 iavf_bus_speed_2500 = 2500,
286 iavf_bus_speed_5000 = 5000,
287 iavf_bus_speed_8000 = 8000,
288 iavf_bus_speed_reserved
292 enum iavf_bus_width {
293 iavf_bus_width_unknown = 0,
294 iavf_bus_width_pcie_x1 = 1,
295 iavf_bus_width_pcie_x2 = 2,
296 iavf_bus_width_pcie_x4 = 4,
297 iavf_bus_width_pcie_x8 = 8,
298 iavf_bus_width_32 = 32,
299 iavf_bus_width_64 = 64,
300 iavf_bus_width_reserved
304 struct iavf_bus_info {
305 enum iavf_bus_speed speed;
306 enum iavf_bus_width width;
307 enum iavf_bus_type type;
315 #define IAVF_MAX_USER_PRIORITY 8
316 #define IAVF_TLV_STATUS_OPER 0x1
317 #define IAVF_TLV_STATUS_SYNC 0x2
318 #define IAVF_TLV_STATUS_ERR 0x4
319 #define IAVF_CEE_OPER_MAX_APPS 3
320 #define IAVF_APP_PROTOID_FCOE 0x8906
321 #define IAVF_APP_PROTOID_ISCSI 0x0cbc
322 #define IAVF_APP_PROTOID_FIP 0x8914
323 #define IAVF_APP_SEL_ETHTYPE 0x1
324 #define IAVF_APP_SEL_TCPIP 0x2
325 #define IAVF_CEE_APP_SEL_ETHTYPE 0x0
326 #define IAVF_CEE_APP_SEL_TCPIP 0x1
328 /* Port hardware description */
333 /* subsystem structs */
334 struct iavf_mac_info mac;
335 struct iavf_bus_info bus;
340 u16 subsystem_device_id;
341 u16 subsystem_vendor_id;
343 bool adapter_stopped;
345 /* capabilities for entire device and PCI func */
346 struct iavf_hw_capabilities dev_caps;
348 /* Admin Queue info */
349 struct iavf_adminq_info aq;
351 /* WoL and proxy support */
352 u16 num_wol_proxy_filters;
353 u16 wol_proxy_vsi_seid;
355 #define IAVF_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE BIT_ULL(0)
356 #define IAVF_HW_FLAG_802_1AD_CAPABLE BIT_ULL(1)
357 #define IAVF_HW_FLAG_AQ_PHY_ACCESS_CAPABLE BIT_ULL(2)
358 #define IAVF_HW_FLAG_NVM_READ_REQUIRES_LOCK BIT_ULL(3)
359 #define IAVF_HW_FLAG_FW_LLDP_STOPPABLE BIT_ULL(4)
362 /* NVMUpdate features */
363 struct iavf_nvmupd_features nvmupd_features;
370 struct iavf_driver_version {
375 u8 driver_string[32];
379 union iavf_16byte_rx_desc {
381 __le64 pkt_addr; /* Packet buffer address */
382 __le64 hdr_addr; /* Header buffer address */
388 __le16 mirroring_status;
394 __le32 rss; /* RSS Hash */
395 __le32 fd_id; /* Flow director filter id */
396 __le32 fcoe_param; /* FCoE DDP Context id */
400 /* ext status/error/pktype/length */
401 __le64 status_error_len;
403 } wb; /* writeback */
406 union iavf_32byte_rx_desc {
408 __le64 pkt_addr; /* Packet buffer address */
409 __le64 hdr_addr; /* Header buffer address */
410 /* bit 0 of hdr_buffer_addr is DD bit */
418 __le16 mirroring_status;
424 __le32 rss; /* RSS Hash */
425 __le32 fcoe_param; /* FCoE DDP Context id */
426 /* Flow director filter id in case of
427 * Programming status desc WB
433 /* status/error/pktype/length */
434 __le64 status_error_len;
437 __le16 ext_status; /* extended status */
444 __le32 flex_bytes_lo;
448 __le32 flex_bytes_hi;
452 } wb; /* writeback */
455 #define IAVF_RXD_QW0_MIRROR_STATUS_SHIFT 8
456 #define IAVF_RXD_QW0_MIRROR_STATUS_MASK (0x3FUL << \
457 IAVF_RXD_QW0_MIRROR_STATUS_SHIFT)
458 #define IAVF_RXD_QW0_FCOEINDX_SHIFT 0
459 #define IAVF_RXD_QW0_FCOEINDX_MASK (0xFFFUL << \
460 IAVF_RXD_QW0_FCOEINDX_SHIFT)
462 enum iavf_rx_desc_status_bits {
463 /* Note: These are predefined bit offsets */
464 IAVF_RX_DESC_STATUS_DD_SHIFT = 0,
465 IAVF_RX_DESC_STATUS_EOF_SHIFT = 1,
466 IAVF_RX_DESC_STATUS_L2TAG1P_SHIFT = 2,
467 IAVF_RX_DESC_STATUS_L3L4P_SHIFT = 3,
468 IAVF_RX_DESC_STATUS_CRCP_SHIFT = 4,
469 IAVF_RX_DESC_STATUS_TSYNINDX_SHIFT = 5, /* 2 BITS */
470 IAVF_RX_DESC_STATUS_TSYNVALID_SHIFT = 7,
471 IAVF_RX_DESC_STATUS_EXT_UDP_0_SHIFT = 8,
473 IAVF_RX_DESC_STATUS_UMBCAST_SHIFT = 9, /* 2 BITS */
474 IAVF_RX_DESC_STATUS_FLM_SHIFT = 11,
475 IAVF_RX_DESC_STATUS_FLTSTAT_SHIFT = 12, /* 2 BITS */
476 IAVF_RX_DESC_STATUS_LPBK_SHIFT = 14,
477 IAVF_RX_DESC_STATUS_IPV6EXADD_SHIFT = 15,
478 IAVF_RX_DESC_STATUS_RESERVED2_SHIFT = 16, /* 2 BITS */
479 IAVF_RX_DESC_STATUS_INT_UDP_0_SHIFT = 18,
480 IAVF_RX_DESC_STATUS_LAST /* this entry must be last!!! */
483 #define IAVF_RXD_QW1_STATUS_SHIFT 0
484 #define IAVF_RXD_QW1_STATUS_MASK ((BIT(IAVF_RX_DESC_STATUS_LAST) - 1) << \
485 IAVF_RXD_QW1_STATUS_SHIFT)
487 #define IAVF_RXD_QW1_STATUS_TSYNINDX_SHIFT IAVF_RX_DESC_STATUS_TSYNINDX_SHIFT
488 #define IAVF_RXD_QW1_STATUS_TSYNINDX_MASK (0x3UL << \
489 IAVF_RXD_QW1_STATUS_TSYNINDX_SHIFT)
491 #define IAVF_RXD_QW1_STATUS_TSYNVALID_SHIFT IAVF_RX_DESC_STATUS_TSYNVALID_SHIFT
492 #define IAVF_RXD_QW1_STATUS_TSYNVALID_MASK BIT_ULL(IAVF_RXD_QW1_STATUS_TSYNVALID_SHIFT)
494 #define IAVF_RXD_QW1_STATUS_UMBCAST_SHIFT IAVF_RX_DESC_STATUS_UMBCAST
495 #define IAVF_RXD_QW1_STATUS_UMBCAST_MASK (0x3UL << \
496 IAVF_RXD_QW1_STATUS_UMBCAST_SHIFT)
498 enum iavf_rx_desc_fltstat_values {
499 IAVF_RX_DESC_FLTSTAT_NO_DATA = 0,
500 IAVF_RX_DESC_FLTSTAT_RSV_FD_ID = 1, /* 16byte desc? FD_ID : RSV */
501 IAVF_RX_DESC_FLTSTAT_RSV = 2,
502 IAVF_RX_DESC_FLTSTAT_RSS_HASH = 3,
505 #define IAVF_RXD_PACKET_TYPE_UNICAST 0
506 #define IAVF_RXD_PACKET_TYPE_MULTICAST 1
507 #define IAVF_RXD_PACKET_TYPE_BROADCAST 2
508 #define IAVF_RXD_PACKET_TYPE_MIRRORED 3
510 #define IAVF_RXD_QW1_ERROR_SHIFT 19
511 #define IAVF_RXD_QW1_ERROR_MASK (0xFFUL << IAVF_RXD_QW1_ERROR_SHIFT)
513 enum iavf_rx_desc_error_bits {
514 /* Note: These are predefined bit offsets */
515 IAVF_RX_DESC_ERROR_RXE_SHIFT = 0,
516 IAVF_RX_DESC_ERROR_RECIPE_SHIFT = 1,
517 IAVF_RX_DESC_ERROR_HBO_SHIFT = 2,
518 IAVF_RX_DESC_ERROR_L3L4E_SHIFT = 3, /* 3 BITS */
519 IAVF_RX_DESC_ERROR_IPE_SHIFT = 3,
520 IAVF_RX_DESC_ERROR_L4E_SHIFT = 4,
521 IAVF_RX_DESC_ERROR_EIPE_SHIFT = 5,
522 IAVF_RX_DESC_ERROR_OVERSIZE_SHIFT = 6,
523 IAVF_RX_DESC_ERROR_PPRS_SHIFT = 7
526 enum iavf_rx_desc_error_l3l4e_fcoe_masks {
527 IAVF_RX_DESC_ERROR_L3L4E_NONE = 0,
528 IAVF_RX_DESC_ERROR_L3L4E_PROT = 1,
529 IAVF_RX_DESC_ERROR_L3L4E_FC = 2,
530 IAVF_RX_DESC_ERROR_L3L4E_DMAC_ERR = 3,
531 IAVF_RX_DESC_ERROR_L3L4E_DMAC_WARN = 4
534 #define IAVF_RXD_QW1_PTYPE_SHIFT 30
535 #define IAVF_RXD_QW1_PTYPE_MASK (0xFFULL << IAVF_RXD_QW1_PTYPE_SHIFT)
537 /* Packet type non-ip values */
538 enum iavf_rx_l2_ptype {
539 IAVF_RX_PTYPE_L2_RESERVED = 0,
540 IAVF_RX_PTYPE_L2_MAC_PAY2 = 1,
541 IAVF_RX_PTYPE_L2_TIMESYNC_PAY2 = 2,
542 IAVF_RX_PTYPE_L2_FIP_PAY2 = 3,
543 IAVF_RX_PTYPE_L2_OUI_PAY2 = 4,
544 IAVF_RX_PTYPE_L2_MACCNTRL_PAY2 = 5,
545 IAVF_RX_PTYPE_L2_LLDP_PAY2 = 6,
546 IAVF_RX_PTYPE_L2_ECP_PAY2 = 7,
547 IAVF_RX_PTYPE_L2_EVB_PAY2 = 8,
548 IAVF_RX_PTYPE_L2_QCN_PAY2 = 9,
549 IAVF_RX_PTYPE_L2_EAPOL_PAY2 = 10,
550 IAVF_RX_PTYPE_L2_ARP = 11,
551 IAVF_RX_PTYPE_L2_FCOE_PAY3 = 12,
552 IAVF_RX_PTYPE_L2_FCOE_FCDATA_PAY3 = 13,
553 IAVF_RX_PTYPE_L2_FCOE_FCRDY_PAY3 = 14,
554 IAVF_RX_PTYPE_L2_FCOE_FCRSP_PAY3 = 15,
555 IAVF_RX_PTYPE_L2_FCOE_FCOTHER_PA = 16,
556 IAVF_RX_PTYPE_L2_FCOE_VFT_PAY3 = 17,
557 IAVF_RX_PTYPE_L2_FCOE_VFT_FCDATA = 18,
558 IAVF_RX_PTYPE_L2_FCOE_VFT_FCRDY = 19,
559 IAVF_RX_PTYPE_L2_FCOE_VFT_FCRSP = 20,
560 IAVF_RX_PTYPE_L2_FCOE_VFT_FCOTHER = 21,
561 IAVF_RX_PTYPE_GRENAT4_MAC_PAY3 = 58,
562 IAVF_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4 = 87,
563 IAVF_RX_PTYPE_GRENAT6_MAC_PAY3 = 124,
564 IAVF_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4 = 153
567 struct iavf_rx_ptype_decoded {
574 u32 tunnel_end_prot:2;
575 u32 tunnel_end_frag:1;
580 enum iavf_rx_ptype_outer_ip {
581 IAVF_RX_PTYPE_OUTER_L2 = 0,
582 IAVF_RX_PTYPE_OUTER_IP = 1
585 enum iavf_rx_ptype_outer_ip_ver {
586 IAVF_RX_PTYPE_OUTER_NONE = 0,
587 IAVF_RX_PTYPE_OUTER_IPV4 = 0,
588 IAVF_RX_PTYPE_OUTER_IPV6 = 1
591 enum iavf_rx_ptype_outer_fragmented {
592 IAVF_RX_PTYPE_NOT_FRAG = 0,
593 IAVF_RX_PTYPE_FRAG = 1
596 enum iavf_rx_ptype_tunnel_type {
597 IAVF_RX_PTYPE_TUNNEL_NONE = 0,
598 IAVF_RX_PTYPE_TUNNEL_IP_IP = 1,
599 IAVF_RX_PTYPE_TUNNEL_IP_GRENAT = 2,
600 IAVF_RX_PTYPE_TUNNEL_IP_GRENAT_MAC = 3,
601 IAVF_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
604 enum iavf_rx_ptype_tunnel_end_prot {
605 IAVF_RX_PTYPE_TUNNEL_END_NONE = 0,
606 IAVF_RX_PTYPE_TUNNEL_END_IPV4 = 1,
607 IAVF_RX_PTYPE_TUNNEL_END_IPV6 = 2,
610 enum iavf_rx_ptype_inner_prot {
611 IAVF_RX_PTYPE_INNER_PROT_NONE = 0,
612 IAVF_RX_PTYPE_INNER_PROT_UDP = 1,
613 IAVF_RX_PTYPE_INNER_PROT_TCP = 2,
614 IAVF_RX_PTYPE_INNER_PROT_SCTP = 3,
615 IAVF_RX_PTYPE_INNER_PROT_ICMP = 4,
616 IAVF_RX_PTYPE_INNER_PROT_TIMESYNC = 5
619 enum iavf_rx_ptype_payload_layer {
620 IAVF_RX_PTYPE_PAYLOAD_LAYER_NONE = 0,
621 IAVF_RX_PTYPE_PAYLOAD_LAYER_PAY2 = 1,
622 IAVF_RX_PTYPE_PAYLOAD_LAYER_PAY3 = 2,
623 IAVF_RX_PTYPE_PAYLOAD_LAYER_PAY4 = 3,
626 #define IAVF_RX_PTYPE_BIT_MASK 0x0FFFFFFF
627 #define IAVF_RX_PTYPE_SHIFT 56
629 #define IAVF_RXD_QW1_LENGTH_PBUF_SHIFT 38
630 #define IAVF_RXD_QW1_LENGTH_PBUF_MASK (0x3FFFULL << \
631 IAVF_RXD_QW1_LENGTH_PBUF_SHIFT)
633 #define IAVF_RXD_QW1_LENGTH_HBUF_SHIFT 52
634 #define IAVF_RXD_QW1_LENGTH_HBUF_MASK (0x7FFULL << \
635 IAVF_RXD_QW1_LENGTH_HBUF_SHIFT)
637 #define IAVF_RXD_QW1_LENGTH_SPH_SHIFT 63
638 #define IAVF_RXD_QW1_LENGTH_SPH_MASK BIT_ULL(IAVF_RXD_QW1_LENGTH_SPH_SHIFT)
640 #define IAVF_RXD_QW1_NEXTP_SHIFT 38
641 #define IAVF_RXD_QW1_NEXTP_MASK (0x1FFFULL << IAVF_RXD_QW1_NEXTP_SHIFT)
643 #define IAVF_RXD_QW2_EXT_STATUS_SHIFT 0
644 #define IAVF_RXD_QW2_EXT_STATUS_MASK (0xFFFFFUL << \
645 IAVF_RXD_QW2_EXT_STATUS_SHIFT)
647 enum iavf_rx_desc_ext_status_bits {
648 /* Note: These are predefined bit offsets */
649 IAVF_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT = 0,
650 IAVF_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT = 1,
651 IAVF_RX_DESC_EXT_STATUS_FLEXBL_SHIFT = 2, /* 2 BITS */
652 IAVF_RX_DESC_EXT_STATUS_FLEXBH_SHIFT = 4, /* 2 BITS */
653 IAVF_RX_DESC_EXT_STATUS_FDLONGB_SHIFT = 9,
654 IAVF_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
655 IAVF_RX_DESC_EXT_STATUS_PELONGB_SHIFT = 11,
658 #define IAVF_RXD_QW2_L2TAG2_SHIFT 0
659 #define IAVF_RXD_QW2_L2TAG2_MASK (0xFFFFUL << IAVF_RXD_QW2_L2TAG2_SHIFT)
661 #define IAVF_RXD_QW2_L2TAG3_SHIFT 16
662 #define IAVF_RXD_QW2_L2TAG3_MASK (0xFFFFUL << IAVF_RXD_QW2_L2TAG3_SHIFT)
664 enum iavf_rx_desc_pe_status_bits {
665 /* Note: These are predefined bit offsets */
666 IAVF_RX_DESC_PE_STATUS_QPID_SHIFT = 0, /* 18 BITS */
667 IAVF_RX_DESC_PE_STATUS_L4PORT_SHIFT = 0, /* 16 BITS */
668 IAVF_RX_DESC_PE_STATUS_IPINDEX_SHIFT = 16, /* 8 BITS */
669 IAVF_RX_DESC_PE_STATUS_QPIDHIT_SHIFT = 24,
670 IAVF_RX_DESC_PE_STATUS_APBVTHIT_SHIFT = 25,
671 IAVF_RX_DESC_PE_STATUS_PORTV_SHIFT = 26,
672 IAVF_RX_DESC_PE_STATUS_URG_SHIFT = 27,
673 IAVF_RX_DESC_PE_STATUS_IPFRAG_SHIFT = 28,
674 IAVF_RX_DESC_PE_STATUS_IPOPT_SHIFT = 29
677 #define IAVF_RX_PROG_STATUS_DESC_LENGTH_SHIFT 38
678 #define IAVF_RX_PROG_STATUS_DESC_LENGTH 0x2000000
680 #define IAVF_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT 2
681 #define IAVF_RX_PROG_STATUS_DESC_QW1_PROGID_MASK (0x7UL << \
682 IAVF_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
684 #define IAVF_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT 0
685 #define IAVF_RX_PROG_STATUS_DESC_QW1_STATUS_MASK (0x7FFFUL << \
686 IAVF_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT)
688 #define IAVF_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT 19
689 #define IAVF_RX_PROG_STATUS_DESC_QW1_ERROR_MASK (0x3FUL << \
690 IAVF_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
692 enum iavf_rx_prog_status_desc_status_bits {
693 /* Note: These are predefined bit offsets */
694 IAVF_RX_PROG_STATUS_DESC_DD_SHIFT = 0,
695 IAVF_RX_PROG_STATUS_DESC_PROG_ID_SHIFT = 2 /* 3 BITS */
698 enum iavf_rx_prog_status_desc_prog_id_masks {
699 IAVF_RX_PROG_STATUS_DESC_FD_FILTER_STATUS = 1,
700 IAVF_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS = 2,
701 IAVF_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS = 4,
704 enum iavf_rx_prog_status_desc_error_bits {
705 /* Note: These are predefined bit offsets */
706 IAVF_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT = 0,
707 IAVF_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT = 1,
708 IAVF_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT = 2,
709 IAVF_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT = 3
712 #define IAVF_TWO_BIT_MASK 0x3
713 #define IAVF_THREE_BIT_MASK 0x7
714 #define IAVF_FOUR_BIT_MASK 0xF
715 #define IAVF_EIGHTEEN_BIT_MASK 0x3FFFF
718 struct iavf_tx_desc {
719 __le64 buffer_addr; /* Address of descriptor's data buf */
720 __le64 cmd_type_offset_bsz;
723 #define IAVF_TXD_QW1_DTYPE_SHIFT 0
724 #define IAVF_TXD_QW1_DTYPE_MASK (0xFUL << IAVF_TXD_QW1_DTYPE_SHIFT)
726 enum iavf_tx_desc_dtype_value {
727 IAVF_TX_DESC_DTYPE_DATA = 0x0,
728 IAVF_TX_DESC_DTYPE_NOP = 0x1, /* same as Context desc */
729 IAVF_TX_DESC_DTYPE_CONTEXT = 0x1,
730 IAVF_TX_DESC_DTYPE_FCOE_CTX = 0x2,
731 IAVF_TX_DESC_DTYPE_FILTER_PROG = 0x8,
732 IAVF_TX_DESC_DTYPE_DDP_CTX = 0x9,
733 IAVF_TX_DESC_DTYPE_FLEX_DATA = 0xB,
734 IAVF_TX_DESC_DTYPE_FLEX_CTX_1 = 0xC,
735 IAVF_TX_DESC_DTYPE_FLEX_CTX_2 = 0xD,
736 IAVF_TX_DESC_DTYPE_DESC_DONE = 0xF
739 #define IAVF_TXD_QW1_CMD_SHIFT 4
740 #define IAVF_TXD_QW1_CMD_MASK (0x3FFUL << IAVF_TXD_QW1_CMD_SHIFT)
742 enum iavf_tx_desc_cmd_bits {
743 IAVF_TX_DESC_CMD_EOP = 0x0001,
744 IAVF_TX_DESC_CMD_RS = 0x0002,
745 IAVF_TX_DESC_CMD_ICRC = 0x0004,
746 IAVF_TX_DESC_CMD_IL2TAG1 = 0x0008,
747 IAVF_TX_DESC_CMD_DUMMY = 0x0010,
748 IAVF_TX_DESC_CMD_IIPT_NONIP = 0x0000, /* 2 BITS */
749 IAVF_TX_DESC_CMD_IIPT_IPV6 = 0x0020, /* 2 BITS */
750 IAVF_TX_DESC_CMD_IIPT_IPV4 = 0x0040, /* 2 BITS */
751 IAVF_TX_DESC_CMD_IIPT_IPV4_CSUM = 0x0060, /* 2 BITS */
752 IAVF_TX_DESC_CMD_FCOET = 0x0080,
753 IAVF_TX_DESC_CMD_L4T_EOFT_UNK = 0x0000, /* 2 BITS */
754 IAVF_TX_DESC_CMD_L4T_EOFT_TCP = 0x0100, /* 2 BITS */
755 IAVF_TX_DESC_CMD_L4T_EOFT_SCTP = 0x0200, /* 2 BITS */
756 IAVF_TX_DESC_CMD_L4T_EOFT_UDP = 0x0300, /* 2 BITS */
757 IAVF_TX_DESC_CMD_L4T_EOFT_EOF_N = 0x0000, /* 2 BITS */
758 IAVF_TX_DESC_CMD_L4T_EOFT_EOF_T = 0x0100, /* 2 BITS */
759 IAVF_TX_DESC_CMD_L4T_EOFT_EOF_NI = 0x0200, /* 2 BITS */
760 IAVF_TX_DESC_CMD_L4T_EOFT_EOF_A = 0x0300, /* 2 BITS */
763 #define IAVF_TXD_QW1_OFFSET_SHIFT 16
764 #define IAVF_TXD_QW1_OFFSET_MASK (0x3FFFFULL << \
765 IAVF_TXD_QW1_OFFSET_SHIFT)
767 enum iavf_tx_desc_length_fields {
768 /* Note: These are predefined bit offsets */
769 IAVF_TX_DESC_LENGTH_MACLEN_SHIFT = 0, /* 7 BITS */
770 IAVF_TX_DESC_LENGTH_IPLEN_SHIFT = 7, /* 7 BITS */
771 IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT = 14 /* 4 BITS */
774 #define IAVF_TXD_QW1_MACLEN_MASK (0x7FUL << IAVF_TX_DESC_LENGTH_MACLEN_SHIFT)
775 #define IAVF_TXD_QW1_IPLEN_MASK (0x7FUL << IAVF_TX_DESC_LENGTH_IPLEN_SHIFT)
776 #define IAVF_TXD_QW1_L4LEN_MASK (0xFUL << IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
777 #define IAVF_TXD_QW1_FCLEN_MASK (0xFUL << IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
779 #define IAVF_TXD_QW1_TX_BUF_SZ_SHIFT 34
780 #define IAVF_TXD_QW1_TX_BUF_SZ_MASK (0x3FFFULL << \
781 IAVF_TXD_QW1_TX_BUF_SZ_SHIFT)
783 #define IAVF_TXD_QW1_L2TAG1_SHIFT 48
784 #define IAVF_TXD_QW1_L2TAG1_MASK (0xFFFFULL << IAVF_TXD_QW1_L2TAG1_SHIFT)
786 /* Context descriptors */
787 struct iavf_tx_context_desc {
788 __le32 tunneling_params;
791 __le64 type_cmd_tso_mss;
794 #define IAVF_TXD_CTX_QW1_DTYPE_SHIFT 0
795 #define IAVF_TXD_CTX_QW1_DTYPE_MASK (0xFUL << IAVF_TXD_CTX_QW1_DTYPE_SHIFT)
797 #define IAVF_TXD_CTX_QW1_CMD_SHIFT 4
798 #define IAVF_TXD_CTX_QW1_CMD_MASK (0xFFFFUL << IAVF_TXD_CTX_QW1_CMD_SHIFT)
800 enum iavf_tx_ctx_desc_cmd_bits {
801 IAVF_TX_CTX_DESC_TSO = 0x01,
802 IAVF_TX_CTX_DESC_TSYN = 0x02,
803 IAVF_TX_CTX_DESC_IL2TAG2 = 0x04,
804 IAVF_TX_CTX_DESC_IL2TAG2_IL2H = 0x08,
805 IAVF_TX_CTX_DESC_SWTCH_NOTAG = 0x00,
806 IAVF_TX_CTX_DESC_SWTCH_UPLINK = 0x10,
807 IAVF_TX_CTX_DESC_SWTCH_LOCAL = 0x20,
808 IAVF_TX_CTX_DESC_SWTCH_VSI = 0x30,
809 IAVF_TX_CTX_DESC_SWPE = 0x40
812 struct iavf_nop_desc {
817 #define IAVF_TXD_NOP_QW1_DTYPE_SHIFT 0
818 #define IAVF_TXD_NOP_QW1_DTYPE_MASK (0xFUL << IAVF_TXD_NOP_QW1_DTYPE_SHIFT)
820 #define IAVF_TXD_NOP_QW1_CMD_SHIFT 4
821 #define IAVF_TXD_NOP_QW1_CMD_MASK (0x7FUL << IAVF_TXD_NOP_QW1_CMD_SHIFT)
823 enum iavf_tx_nop_desc_cmd_bits {
824 /* Note: These are predefined bit offsets */
825 IAVF_TX_NOP_DESC_EOP_SHIFT = 0,
826 IAVF_TX_NOP_DESC_RS_SHIFT = 1,
827 IAVF_TX_NOP_DESC_RSV_SHIFT = 2 /* 5 bits */
830 /* Packet Classifier Types for filters */
831 enum iavf_filter_pctype {
832 /* Note: Values 0-28 are reserved for future use.
833 * Value 29, 30, 32 are not supported on XL710 and X710.
835 IAVF_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP = 29,
836 IAVF_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP = 30,
837 IAVF_FILTER_PCTYPE_NONF_IPV4_UDP = 31,
838 IAVF_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK = 32,
839 IAVF_FILTER_PCTYPE_NONF_IPV4_TCP = 33,
840 IAVF_FILTER_PCTYPE_NONF_IPV4_SCTP = 34,
841 IAVF_FILTER_PCTYPE_NONF_IPV4_OTHER = 35,
842 IAVF_FILTER_PCTYPE_FRAG_IPV4 = 36,
843 /* Note: Values 37-38 are reserved for future use.
844 * Value 39, 40, 42 are not supported on XL710 and X710.
846 IAVF_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP = 39,
847 IAVF_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP = 40,
848 IAVF_FILTER_PCTYPE_NONF_IPV6_UDP = 41,
849 IAVF_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK = 42,
850 IAVF_FILTER_PCTYPE_NONF_IPV6_TCP = 43,
851 IAVF_FILTER_PCTYPE_NONF_IPV6_SCTP = 44,
852 IAVF_FILTER_PCTYPE_NONF_IPV6_OTHER = 45,
853 IAVF_FILTER_PCTYPE_FRAG_IPV6 = 46,
854 /* Note: Value 47 is reserved for future use */
855 IAVF_FILTER_PCTYPE_FCOE_OX = 48,
856 IAVF_FILTER_PCTYPE_FCOE_RX = 49,
857 IAVF_FILTER_PCTYPE_FCOE_OTHER = 50,
858 /* Note: Values 51-62 are reserved for future use */
859 IAVF_FILTER_PCTYPE_L2_PAYLOAD = 63,
862 #define IAVF_TXD_FLTR_QW1_DTYPE_SHIFT 0
863 #define IAVF_TXD_FLTR_QW1_DTYPE_MASK (0xFUL << IAVF_TXD_FLTR_QW1_DTYPE_SHIFT)
865 #define IAVF_TXD_FLTR_QW1_ATR_SHIFT (0xEULL + \
866 IAVF_TXD_FLTR_QW1_CMD_SHIFT)
867 #define IAVF_TXD_FLTR_QW1_ATR_MASK BIT_ULL(IAVF_TXD_FLTR_QW1_ATR_SHIFT)
870 #define IAVF_TXD_CTX_QW1_TSO_LEN_SHIFT 30
871 #define IAVF_TXD_CTX_QW1_TSO_LEN_MASK (0x3FFFFULL << \
872 IAVF_TXD_CTX_QW1_TSO_LEN_SHIFT)
874 #define IAVF_TXD_CTX_QW1_MSS_SHIFT 50
875 #define IAVF_TXD_CTX_QW1_MSS_MASK (0x3FFFULL << \
876 IAVF_TXD_CTX_QW1_MSS_SHIFT)
878 #define IAVF_TXD_CTX_QW1_VSI_SHIFT 50
879 #define IAVF_TXD_CTX_QW1_VSI_MASK (0x1FFULL << IAVF_TXD_CTX_QW1_VSI_SHIFT)
881 #define IAVF_TXD_CTX_QW0_EXT_IP_SHIFT 0
882 #define IAVF_TXD_CTX_QW0_EXT_IP_MASK (0x3ULL << \
883 IAVF_TXD_CTX_QW0_EXT_IP_SHIFT)
885 enum iavf_tx_ctx_desc_eipt_offload {
886 IAVF_TX_CTX_EXT_IP_NONE = 0x0,
887 IAVF_TX_CTX_EXT_IP_IPV6 = 0x1,
888 IAVF_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
889 IAVF_TX_CTX_EXT_IP_IPV4 = 0x3
892 #define IAVF_TXD_CTX_QW0_EXT_IPLEN_SHIFT 2
893 #define IAVF_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
894 IAVF_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
896 #define IAVF_TXD_CTX_QW0_NATT_SHIFT 9
897 #define IAVF_TXD_CTX_QW0_NATT_MASK (0x3ULL << IAVF_TXD_CTX_QW0_NATT_SHIFT)
899 #define IAVF_TXD_CTX_UDP_TUNNELING BIT_ULL(IAVF_TXD_CTX_QW0_NATT_SHIFT)
900 #define IAVF_TXD_CTX_GRE_TUNNELING (0x2ULL << IAVF_TXD_CTX_QW0_NATT_SHIFT)
902 #define IAVF_TXD_CTX_QW0_EIP_NOINC_SHIFT 11
903 #define IAVF_TXD_CTX_QW0_EIP_NOINC_MASK BIT_ULL(IAVF_TXD_CTX_QW0_EIP_NOINC_SHIFT)
905 #define IAVF_TXD_CTX_EIP_NOINC_IPID_CONST IAVF_TXD_CTX_QW0_EIP_NOINC_MASK
907 #define IAVF_TXD_CTX_QW0_NATLEN_SHIFT 12
908 #define IAVF_TXD_CTX_QW0_NATLEN_MASK (0X7FULL << \
909 IAVF_TXD_CTX_QW0_NATLEN_SHIFT)
911 #define IAVF_TXD_CTX_QW0_DECTTL_SHIFT 19
912 #define IAVF_TXD_CTX_QW0_DECTTL_MASK (0xFULL << \
913 IAVF_TXD_CTX_QW0_DECTTL_SHIFT)
915 #define IAVF_TXD_CTX_QW0_L4T_CS_SHIFT 23
916 #define IAVF_TXD_CTX_QW0_L4T_CS_MASK BIT_ULL(IAVF_TXD_CTX_QW0_L4T_CS_SHIFT)
918 /* Statistics collected by each port, VSI, VEB, and S-channel */
919 struct iavf_eth_stats {
920 u64 rx_bytes; /* gorc */
921 u64 rx_unicast; /* uprc */
922 u64 rx_multicast; /* mprc */
923 u64 rx_broadcast; /* bprc */
924 u64 rx_discards; /* rdpc */
925 u64 rx_unknown_protocol; /* rupp */
926 u64 tx_bytes; /* gotc */
927 u64 tx_unicast; /* uptc */
928 u64 tx_multicast; /* mptc */
929 u64 tx_broadcast; /* bptc */
930 u64 tx_discards; /* tdpc */
931 u64 tx_errors; /* tepc */
933 #define IAVF_SR_PCIE_ANALOG_CONFIG_PTR 0x03
934 #define IAVF_SR_PHY_ANALOG_CONFIG_PTR 0x04
935 #define IAVF_SR_OPTION_ROM_PTR 0x05
936 #define IAVF_SR_RO_PCIR_REGS_AUTO_LOAD_PTR 0x06
937 #define IAVF_SR_AUTO_GENERATED_POINTERS_PTR 0x07
938 #define IAVF_SR_PCIR_REGS_AUTO_LOAD_PTR 0x08
939 #define IAVF_SR_EMP_GLOBAL_MODULE_PTR 0x09
940 #define IAVF_SR_RO_PCIE_LCB_PTR 0x0A
941 #define IAVF_SR_EMP_IMAGE_PTR 0x0B
942 #define IAVF_SR_PE_IMAGE_PTR 0x0C
943 #define IAVF_SR_CSR_PROTECTED_LIST_PTR 0x0D
944 #define IAVF_SR_MNG_CONFIG_PTR 0x0E
945 #define IAVF_SR_PBA_FLAGS 0x15
946 #define IAVF_SR_PBA_BLOCK_PTR 0x16
947 #define IAVF_SR_BOOT_CONFIG_PTR 0x17
948 #define IAVF_SR_PERMANENT_SAN_MAC_ADDRESS_PTR 0x28
949 #define IAVF_SR_NVM_MAP_VERSION 0x29
950 #define IAVF_SR_NVM_IMAGE_VERSION 0x2A
951 #define IAVF_SR_NVM_STRUCTURE_VERSION 0x2B
952 #define IAVF_SR_PXE_SETUP_PTR 0x30
953 #define IAVF_SR_PXE_CONFIG_CUST_OPTIONS_PTR 0x31
954 #define IAVF_SR_NVM_ORIGINAL_EETRACK_LO 0x34
955 #define IAVF_SR_NVM_ORIGINAL_EETRACK_HI 0x35
956 #define IAVF_SR_SW_ETHERNET_MAC_ADDRESS_PTR 0x37
957 #define IAVF_SR_POR_REGS_AUTO_LOAD_PTR 0x38
958 #define IAVF_SR_EMPR_REGS_AUTO_LOAD_PTR 0x3A
959 #define IAVF_SR_GLOBR_REGS_AUTO_LOAD_PTR 0x3B
960 #define IAVF_SR_CORER_REGS_AUTO_LOAD_PTR 0x3C
961 #define IAVF_SR_PHY_ACTIVITY_LIST_PTR 0x3D
962 #define IAVF_SR_1ST_FREE_PROVISION_AREA_PTR 0x40
963 #define IAVF_SR_4TH_FREE_PROVISION_AREA_PTR 0x42
964 #define IAVF_SR_3RD_FREE_PROVISION_AREA_PTR 0x44
965 #define IAVF_SR_2ND_FREE_PROVISION_AREA_PTR 0x46
966 #define IAVF_SR_EMP_SR_SETTINGS_PTR 0x48
967 #define IAVF_SR_FEATURE_CONFIGURATION_PTR 0x49
968 #define IAVF_SR_CONFIGURATION_METADATA_PTR 0x4D
969 #define IAVF_SR_IMMEDIATE_VALUES_PTR 0x4E
970 #define IAVF_SR_OCP_CFG_WORD0 0x2B
971 #define IAVF_SR_OCP_ENABLED BIT(15)
972 #define IAVF_SR_BUF_ALIGNMENT 4096
975 struct iavf_lldp_variables {
985 /* Offsets into Alternate Ram */
986 #define IAVF_ALT_STRUCT_FIRST_PF_OFFSET 0 /* in dwords */
987 #define IAVF_ALT_STRUCT_DWORDS_PER_PF 64 /* in dwords */
988 #define IAVF_ALT_STRUCT_OUTER_VLAN_TAG_OFFSET 0xD /* in dwords */
989 #define IAVF_ALT_STRUCT_USER_PRIORITY_OFFSET 0xC /* in dwords */
990 #define IAVF_ALT_STRUCT_MIN_BW_OFFSET 0xE /* in dwords */
991 #define IAVF_ALT_STRUCT_MAX_BW_OFFSET 0xF /* in dwords */
993 /* Alternate Ram Bandwidth Masks */
994 #define IAVF_ALT_BW_VALUE_MASK 0xFF
995 #define IAVF_ALT_BW_RELATIVE_MASK 0x40000000
996 #define IAVF_ALT_BW_VALID_MASK 0x80000000
998 #define IAVF_DDP_TRACKID_RDONLY 0
999 #define IAVF_DDP_TRACKID_INVALID 0xFFFFFFFF
1000 #define SECTION_TYPE_RB_MMIO 0x00001800
1001 #define SECTION_TYPE_RB_AQ 0x00001801
1002 #define SECTION_TYPE_PROTO 0x80000002
1003 #define SECTION_TYPE_PCTYPE 0x80000003
1004 #define SECTION_TYPE_PTYPE 0x80000004
1005 struct iavf_profile_tlv_section_record {
1012 /* Generic AQ section in proflie */
1013 struct iavf_profile_aq_section {
1021 #endif /* _IAVF_TYPE_H_ */