1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2020 Intel Corporation
13 #include <rte_ether.h>
14 #include <ethdev_driver.h>
15 #include <rte_malloc.h>
16 #include <rte_tailq.h>
19 #include "iavf_generic_flow.h"
21 #include "iavf_rxtx.h"
23 #define IAVF_FDIR_MAX_QREGION_SIZE 128
25 #define IAVF_FDIR_IPV6_TC_OFFSET 20
26 #define IAVF_IPV6_TC_MASK (0xFF << IAVF_FDIR_IPV6_TC_OFFSET)
28 #define IAVF_GTPU_EH_DWLINK 0
29 #define IAVF_GTPU_EH_UPLINK 1
31 #define IAVF_FDIR_INSET_ETH (\
34 #define IAVF_FDIR_INSET_ETH_IPV4 (\
35 IAVF_INSET_IPV4_SRC | IAVF_INSET_IPV4_DST | \
36 IAVF_INSET_IPV4_PROTO | IAVF_INSET_IPV4_TOS | \
39 #define IAVF_FDIR_INSET_ETH_IPV4_UDP (\
40 IAVF_INSET_IPV4_SRC | IAVF_INSET_IPV4_DST | \
41 IAVF_INSET_IPV4_TOS | IAVF_INSET_IPV4_TTL | \
42 IAVF_INSET_UDP_SRC_PORT | IAVF_INSET_UDP_DST_PORT)
44 #define IAVF_FDIR_INSET_ETH_IPV4_TCP (\
45 IAVF_INSET_IPV4_SRC | IAVF_INSET_IPV4_DST | \
46 IAVF_INSET_IPV4_TOS | IAVF_INSET_IPV4_TTL | \
47 IAVF_INSET_TCP_SRC_PORT | IAVF_INSET_TCP_DST_PORT)
49 #define IAVF_FDIR_INSET_ETH_IPV4_SCTP (\
50 IAVF_INSET_IPV4_SRC | IAVF_INSET_IPV4_DST | \
51 IAVF_INSET_IPV4_TOS | IAVF_INSET_IPV4_TTL | \
52 IAVF_INSET_SCTP_SRC_PORT | IAVF_INSET_SCTP_DST_PORT)
54 #define IAVF_FDIR_INSET_ETH_IPV6 (\
55 IAVF_INSET_IPV6_SRC | IAVF_INSET_IPV6_DST | \
56 IAVF_INSET_IPV6_NEXT_HDR | IAVF_INSET_IPV6_TC | \
57 IAVF_INSET_IPV6_HOP_LIMIT)
59 #define IAVF_FDIR_INSET_ETH_IPV6_UDP (\
60 IAVF_INSET_IPV6_SRC | IAVF_INSET_IPV6_DST | \
61 IAVF_INSET_IPV6_TC | IAVF_INSET_IPV6_HOP_LIMIT | \
62 IAVF_INSET_UDP_SRC_PORT | IAVF_INSET_UDP_DST_PORT)
64 #define IAVF_FDIR_INSET_ETH_IPV6_TCP (\
65 IAVF_INSET_IPV6_SRC | IAVF_INSET_IPV6_DST | \
66 IAVF_INSET_IPV6_TC | IAVF_INSET_IPV6_HOP_LIMIT | \
67 IAVF_INSET_TCP_SRC_PORT | IAVF_INSET_TCP_DST_PORT)
69 #define IAVF_FDIR_INSET_ETH_IPV6_SCTP (\
70 IAVF_INSET_IPV6_SRC | IAVF_INSET_IPV6_DST | \
71 IAVF_INSET_IPV6_TC | IAVF_INSET_IPV6_HOP_LIMIT | \
72 IAVF_INSET_SCTP_SRC_PORT | IAVF_INSET_SCTP_DST_PORT)
74 #define IAVF_FDIR_INSET_IPV4_GTPU (\
75 IAVF_INSET_IPV4_SRC | IAVF_INSET_IPV4_DST | \
78 #define IAVF_FDIR_INSET_IPV4_GTPU_EH (\
79 IAVF_INSET_IPV4_SRC | IAVF_INSET_IPV4_DST | \
80 IAVF_INSET_GTPU_TEID | IAVF_INSET_GTPU_QFI)
82 #define IAVF_FDIR_INSET_IPV6_GTPU (\
83 IAVF_INSET_IPV6_SRC | IAVF_INSET_IPV6_DST | \
86 #define IAVF_FDIR_INSET_IPV6_GTPU_EH (\
87 IAVF_INSET_IPV6_SRC | IAVF_INSET_IPV6_DST | \
88 IAVF_INSET_GTPU_TEID | IAVF_INSET_GTPU_QFI)
90 #define IAVF_FDIR_INSET_L2TPV3OIP (\
91 IAVF_L2TPV3OIP_SESSION_ID)
93 #define IAVF_FDIR_INSET_ESP (\
96 #define IAVF_FDIR_INSET_AH (\
99 #define IAVF_FDIR_INSET_IPV4_NATT_ESP (\
100 IAVF_INSET_IPV4_SRC | IAVF_INSET_IPV4_DST | \
103 #define IAVF_FDIR_INSET_IPV6_NATT_ESP (\
104 IAVF_INSET_IPV6_SRC | IAVF_INSET_IPV6_DST | \
107 #define IAVF_FDIR_INSET_PFCP (\
108 IAVF_INSET_PFCP_S_FIELD)
110 #define IAVF_FDIR_INSET_ECPRI (\
113 static struct iavf_pattern_match_item iavf_fdir_pattern[] = {
114 {iavf_pattern_ethertype, IAVF_FDIR_INSET_ETH, IAVF_INSET_NONE},
115 {iavf_pattern_eth_ipv4, IAVF_FDIR_INSET_ETH_IPV4, IAVF_INSET_NONE},
116 {iavf_pattern_eth_ipv4_udp, IAVF_FDIR_INSET_ETH_IPV4_UDP, IAVF_INSET_NONE},
117 {iavf_pattern_eth_ipv4_tcp, IAVF_FDIR_INSET_ETH_IPV4_TCP, IAVF_INSET_NONE},
118 {iavf_pattern_eth_ipv4_sctp, IAVF_FDIR_INSET_ETH_IPV4_SCTP, IAVF_INSET_NONE},
119 {iavf_pattern_eth_ipv6, IAVF_FDIR_INSET_ETH_IPV6, IAVF_INSET_NONE},
120 {iavf_pattern_eth_ipv6_udp, IAVF_FDIR_INSET_ETH_IPV6_UDP, IAVF_INSET_NONE},
121 {iavf_pattern_eth_ipv6_tcp, IAVF_FDIR_INSET_ETH_IPV6_TCP, IAVF_INSET_NONE},
122 {iavf_pattern_eth_ipv6_sctp, IAVF_FDIR_INSET_ETH_IPV6_SCTP, IAVF_INSET_NONE},
123 {iavf_pattern_eth_ipv4_gtpu, IAVF_FDIR_INSET_IPV4_GTPU, IAVF_INSET_NONE},
124 {iavf_pattern_eth_ipv4_gtpu_eh, IAVF_FDIR_INSET_IPV4_GTPU_EH, IAVF_INSET_NONE},
125 {iavf_pattern_eth_ipv6_gtpu, IAVF_FDIR_INSET_IPV6_GTPU, IAVF_INSET_NONE},
126 {iavf_pattern_eth_ipv6_gtpu_eh, IAVF_FDIR_INSET_IPV6_GTPU_EH, IAVF_INSET_NONE},
127 {iavf_pattern_eth_ipv4_l2tpv3, IAVF_FDIR_INSET_L2TPV3OIP, IAVF_INSET_NONE},
128 {iavf_pattern_eth_ipv6_l2tpv3, IAVF_FDIR_INSET_L2TPV3OIP, IAVF_INSET_NONE},
129 {iavf_pattern_eth_ipv4_esp, IAVF_FDIR_INSET_ESP, IAVF_INSET_NONE},
130 {iavf_pattern_eth_ipv6_esp, IAVF_FDIR_INSET_ESP, IAVF_INSET_NONE},
131 {iavf_pattern_eth_ipv4_ah, IAVF_FDIR_INSET_AH, IAVF_INSET_NONE},
132 {iavf_pattern_eth_ipv6_ah, IAVF_FDIR_INSET_AH, IAVF_INSET_NONE},
133 {iavf_pattern_eth_ipv4_udp_esp, IAVF_FDIR_INSET_IPV4_NATT_ESP, IAVF_INSET_NONE},
134 {iavf_pattern_eth_ipv6_udp_esp, IAVF_FDIR_INSET_IPV6_NATT_ESP, IAVF_INSET_NONE},
135 {iavf_pattern_eth_ipv4_pfcp, IAVF_FDIR_INSET_PFCP, IAVF_INSET_NONE},
136 {iavf_pattern_eth_ipv6_pfcp, IAVF_FDIR_INSET_PFCP, IAVF_INSET_NONE},
137 {iavf_pattern_eth_ecpri, IAVF_FDIR_INSET_ECPRI, IAVF_INSET_NONE},
138 {iavf_pattern_eth_ipv4_ecpri, IAVF_FDIR_INSET_ECPRI, IAVF_INSET_NONE},
141 static struct iavf_flow_parser iavf_fdir_parser;
144 iavf_fdir_init(struct iavf_adapter *ad)
146 struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(ad);
147 struct iavf_flow_parser *parser;
152 if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_FDIR_PF)
153 parser = &iavf_fdir_parser;
157 return iavf_register_parser(parser, ad);
161 iavf_fdir_uninit(struct iavf_adapter *ad)
163 iavf_unregister_parser(&iavf_fdir_parser, ad);
167 iavf_fdir_create(struct iavf_adapter *ad,
168 struct rte_flow *flow,
170 struct rte_flow_error *error)
172 struct iavf_fdir_conf *filter = meta;
173 struct iavf_fdir_conf *rule;
176 rule = rte_zmalloc("fdir_entry", sizeof(*rule), 0);
178 rte_flow_error_set(error, ENOMEM,
179 RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
180 "Failed to allocate memory for fdir rule");
184 ret = iavf_fdir_add(ad, filter);
186 rte_flow_error_set(error, -ret,
187 RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
188 "Failed to add filter rule.");
192 if (filter->mark_flag == 1)
193 iavf_fdir_rx_proc_enable(ad, 1);
195 rte_memcpy(rule, filter, sizeof(*rule));
206 iavf_fdir_destroy(struct iavf_adapter *ad,
207 struct rte_flow *flow,
208 struct rte_flow_error *error)
210 struct iavf_fdir_conf *filter;
213 filter = (struct iavf_fdir_conf *)flow->rule;
215 ret = iavf_fdir_del(ad, filter);
217 rte_flow_error_set(error, -ret,
218 RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
219 "Failed to delete filter rule.");
223 if (filter->mark_flag == 1)
224 iavf_fdir_rx_proc_enable(ad, 0);
233 iavf_fdir_validation(struct iavf_adapter *ad,
234 __rte_unused struct rte_flow *flow,
236 struct rte_flow_error *error)
238 struct iavf_fdir_conf *filter = meta;
241 ret = iavf_fdir_check(ad, filter);
243 rte_flow_error_set(error, -ret,
244 RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
245 "Failed to validate filter rule.");
252 static struct iavf_flow_engine iavf_fdir_engine = {
253 .init = iavf_fdir_init,
254 .uninit = iavf_fdir_uninit,
255 .create = iavf_fdir_create,
256 .destroy = iavf_fdir_destroy,
257 .validation = iavf_fdir_validation,
258 .type = IAVF_FLOW_ENGINE_FDIR,
262 iavf_fdir_parse_action_qregion(struct iavf_adapter *ad,
263 struct rte_flow_error *error,
264 const struct rte_flow_action *act,
265 struct virtchnl_filter_action *filter_action)
267 struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(ad);
268 const struct rte_flow_action_rss *rss = act->conf;
271 if (act->type != RTE_FLOW_ACTION_TYPE_RSS) {
272 rte_flow_error_set(error, EINVAL,
273 RTE_FLOW_ERROR_TYPE_ACTION, act,
278 if (rss->queue_num <= 1) {
279 rte_flow_error_set(error, EINVAL,
280 RTE_FLOW_ERROR_TYPE_ACTION, act,
281 "Queue region size can't be 0 or 1.");
285 /* check if queue index for queue region is continuous */
286 for (i = 0; i < rss->queue_num - 1; i++) {
287 if (rss->queue[i + 1] != rss->queue[i] + 1) {
288 rte_flow_error_set(error, EINVAL,
289 RTE_FLOW_ERROR_TYPE_ACTION, act,
290 "Discontinuous queue region");
295 if (rss->queue[rss->queue_num - 1] >= ad->eth_dev->data->nb_rx_queues) {
296 rte_flow_error_set(error, EINVAL,
297 RTE_FLOW_ERROR_TYPE_ACTION, act,
298 "Invalid queue region indexes.");
302 if (!(rte_is_power_of_2(rss->queue_num) &&
303 rss->queue_num <= IAVF_FDIR_MAX_QREGION_SIZE)) {
304 rte_flow_error_set(error, EINVAL,
305 RTE_FLOW_ERROR_TYPE_ACTION, act,
306 "The region size should be any of the following values:"
307 "1, 2, 4, 8, 16, 32, 64, 128 as long as the total number "
308 "of queues do not exceed the VSI allocation.");
312 if (rss->queue_num > vf->max_rss_qregion) {
313 rte_flow_error_set(error, EINVAL,
314 RTE_FLOW_ERROR_TYPE_ACTION, act,
315 "The region size cannot be large than the supported max RSS queue region");
319 filter_action->act_conf.queue.index = rss->queue[0];
320 filter_action->act_conf.queue.region = rte_fls_u32(rss->queue_num) - 1;
326 iavf_fdir_parse_action(struct iavf_adapter *ad,
327 const struct rte_flow_action actions[],
328 struct rte_flow_error *error,
329 struct iavf_fdir_conf *filter)
331 const struct rte_flow_action_queue *act_q;
332 const struct rte_flow_action_mark *mark_spec = NULL;
333 uint32_t dest_num = 0;
334 uint32_t mark_num = 0;
338 struct virtchnl_filter_action *filter_action;
340 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
341 switch (actions->type) {
342 case RTE_FLOW_ACTION_TYPE_VOID:
345 case RTE_FLOW_ACTION_TYPE_PASSTHRU:
348 filter_action = &filter->add_fltr.rule_cfg.action_set.actions[number];
350 filter_action->type = VIRTCHNL_ACTION_PASSTHRU;
352 filter->add_fltr.rule_cfg.action_set.count = ++number;
355 case RTE_FLOW_ACTION_TYPE_DROP:
358 filter_action = &filter->add_fltr.rule_cfg.action_set.actions[number];
360 filter_action->type = VIRTCHNL_ACTION_DROP;
362 filter->add_fltr.rule_cfg.action_set.count = ++number;
365 case RTE_FLOW_ACTION_TYPE_QUEUE:
368 act_q = actions->conf;
369 filter_action = &filter->add_fltr.rule_cfg.action_set.actions[number];
371 filter_action->type = VIRTCHNL_ACTION_QUEUE;
372 filter_action->act_conf.queue.index = act_q->index;
374 if (filter_action->act_conf.queue.index >=
375 ad->eth_dev->data->nb_rx_queues) {
376 rte_flow_error_set(error, EINVAL,
377 RTE_FLOW_ERROR_TYPE_ACTION,
378 actions, "Invalid queue for FDIR.");
382 filter->add_fltr.rule_cfg.action_set.count = ++number;
385 case RTE_FLOW_ACTION_TYPE_RSS:
388 filter_action = &filter->add_fltr.rule_cfg.action_set.actions[number];
390 filter_action->type = VIRTCHNL_ACTION_Q_REGION;
392 ret = iavf_fdir_parse_action_qregion(ad,
393 error, actions, filter_action);
397 filter->add_fltr.rule_cfg.action_set.count = ++number;
400 case RTE_FLOW_ACTION_TYPE_MARK:
403 filter->mark_flag = 1;
404 mark_spec = actions->conf;
405 filter_action = &filter->add_fltr.rule_cfg.action_set.actions[number];
407 filter_action->type = VIRTCHNL_ACTION_MARK;
408 filter_action->act_conf.mark_id = mark_spec->id;
410 filter->add_fltr.rule_cfg.action_set.count = ++number;
414 rte_flow_error_set(error, EINVAL,
415 RTE_FLOW_ERROR_TYPE_ACTION, actions,
421 if (number > VIRTCHNL_MAX_NUM_ACTIONS) {
422 rte_flow_error_set(error, EINVAL,
423 RTE_FLOW_ERROR_TYPE_ACTION, actions,
424 "Action numbers exceed the maximum value");
429 rte_flow_error_set(error, EINVAL,
430 RTE_FLOW_ERROR_TYPE_ACTION, actions,
431 "Unsupported action combination");
436 rte_flow_error_set(error, EINVAL,
437 RTE_FLOW_ERROR_TYPE_ACTION, actions,
438 "Too many mark actions");
442 if (dest_num + mark_num == 0) {
443 rte_flow_error_set(error, EINVAL,
444 RTE_FLOW_ERROR_TYPE_ACTION, actions,
449 /* Mark only is equal to mark + passthru. */
451 filter_action = &filter->add_fltr.rule_cfg.action_set.actions[number];
452 filter_action->type = VIRTCHNL_ACTION_PASSTHRU;
453 filter->add_fltr.rule_cfg.action_set.count = ++number;
460 iavf_fdir_refine_input_set(const uint64_t input_set,
461 const uint64_t input_set_mask,
462 struct iavf_fdir_conf *filter)
464 struct virtchnl_proto_hdr *hdr, *hdr_last;
465 struct rte_flow_item_ipv4 ipv4_spec;
466 struct rte_flow_item_ipv6 ipv6_spec;
470 if (input_set & ~input_set_mask)
475 last_layer = filter->add_fltr.rule_cfg.proto_hdrs.count - 1;
476 /* Last layer of TCP/UDP pattern isn't less than 2. */
479 hdr_last = &filter->add_fltr.rule_cfg.proto_hdrs.proto_hdr[last_layer];
480 if (hdr_last->type == VIRTCHNL_PROTO_HDR_TCP)
482 else if (hdr_last->type == VIRTCHNL_PROTO_HDR_UDP)
487 hdr = &filter->add_fltr.rule_cfg.proto_hdrs.proto_hdr[last_layer - 1];
489 case VIRTCHNL_PROTO_HDR_IPV4:
490 VIRTCHNL_ADD_PROTO_HDR_FIELD_BIT(hdr, IPV4, PROT);
491 memset(&ipv4_spec, 0, sizeof(ipv4_spec));
492 ipv4_spec.hdr.next_proto_id = proto_id;
493 rte_memcpy(hdr->buffer, &ipv4_spec.hdr,
494 sizeof(ipv4_spec.hdr));
496 case VIRTCHNL_PROTO_HDR_IPV6:
497 VIRTCHNL_ADD_PROTO_HDR_FIELD_BIT(hdr, IPV6, PROT);
498 memset(&ipv6_spec, 0, sizeof(ipv6_spec));
499 ipv6_spec.hdr.proto = proto_id;
500 rte_memcpy(hdr->buffer, &ipv6_spec.hdr,
501 sizeof(ipv6_spec.hdr));
509 iavf_fdir_parse_pattern(__rte_unused struct iavf_adapter *ad,
510 const struct rte_flow_item pattern[],
511 const uint64_t input_set_mask,
512 struct rte_flow_error *error,
513 struct iavf_fdir_conf *filter)
515 const struct rte_flow_item *item = pattern;
516 enum rte_flow_item_type item_type;
517 enum rte_flow_item_type l3 = RTE_FLOW_ITEM_TYPE_END;
518 const struct rte_flow_item_eth *eth_spec, *eth_mask;
519 const struct rte_flow_item_ipv4 *ipv4_spec, *ipv4_mask;
520 const struct rte_flow_item_ipv6 *ipv6_spec, *ipv6_mask;
521 const struct rte_flow_item_udp *udp_spec, *udp_mask;
522 const struct rte_flow_item_tcp *tcp_spec, *tcp_mask;
523 const struct rte_flow_item_sctp *sctp_spec, *sctp_mask;
524 const struct rte_flow_item_gtp *gtp_spec, *gtp_mask;
525 const struct rte_flow_item_gtp_psc *gtp_psc_spec, *gtp_psc_mask;
526 const struct rte_flow_item_l2tpv3oip *l2tpv3oip_spec, *l2tpv3oip_mask;
527 const struct rte_flow_item_esp *esp_spec, *esp_mask;
528 const struct rte_flow_item_ah *ah_spec, *ah_mask;
529 const struct rte_flow_item_pfcp *pfcp_spec, *pfcp_mask;
530 const struct rte_flow_item_ecpri *ecpri_spec, *ecpri_mask;
531 struct rte_ecpri_common_hdr ecpri_common;
532 uint64_t input_set = IAVF_INSET_NONE;
534 enum rte_flow_item_type next_type;
538 struct virtchnl_proto_hdr *hdr;
540 uint8_t ipv6_addr_mask[16] = {
541 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
542 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF
545 for (item = pattern; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
547 rte_flow_error_set(error, EINVAL,
548 RTE_FLOW_ERROR_TYPE_ITEM, item,
549 "Not support range");
552 item_type = item->type;
555 case RTE_FLOW_ITEM_TYPE_ETH:
556 eth_spec = item->spec;
557 eth_mask = item->mask;
558 next_type = (item + 1)->type;
560 hdr = &filter->add_fltr.rule_cfg.proto_hdrs.proto_hdr[layer];
562 VIRTCHNL_SET_PROTO_HDR_TYPE(hdr, ETH);
564 if (next_type == RTE_FLOW_ITEM_TYPE_END &&
565 (!eth_spec || !eth_mask)) {
566 rte_flow_error_set(error, EINVAL,
567 RTE_FLOW_ERROR_TYPE_ITEM,
568 item, "NULL eth spec/mask.");
572 if (eth_spec && eth_mask) {
573 if (!rte_is_zero_ether_addr(ð_mask->src) ||
574 !rte_is_zero_ether_addr(ð_mask->dst)) {
575 rte_flow_error_set(error, EINVAL,
576 RTE_FLOW_ERROR_TYPE_ITEM, item,
577 "Invalid MAC_addr mask.");
582 if (eth_spec && eth_mask && eth_mask->type) {
583 if (eth_mask->type != RTE_BE16(0xffff)) {
584 rte_flow_error_set(error, EINVAL,
585 RTE_FLOW_ERROR_TYPE_ITEM,
586 item, "Invalid type mask.");
590 ether_type = rte_be_to_cpu_16(eth_spec->type);
591 if (ether_type == RTE_ETHER_TYPE_IPV4 ||
592 ether_type == RTE_ETHER_TYPE_IPV6) {
593 rte_flow_error_set(error, EINVAL,
594 RTE_FLOW_ERROR_TYPE_ITEM,
596 "Unsupported ether_type.");
600 input_set |= IAVF_INSET_ETHERTYPE;
601 VIRTCHNL_ADD_PROTO_HDR_FIELD_BIT(hdr, ETH, ETHERTYPE);
603 rte_memcpy(hdr->buffer,
604 eth_spec, sizeof(struct rte_ether_hdr));
607 filter->add_fltr.rule_cfg.proto_hdrs.count = ++layer;
610 case RTE_FLOW_ITEM_TYPE_IPV4:
611 l3 = RTE_FLOW_ITEM_TYPE_IPV4;
612 ipv4_spec = item->spec;
613 ipv4_mask = item->mask;
615 hdr = &filter->add_fltr.rule_cfg.proto_hdrs.proto_hdr[layer];
617 VIRTCHNL_SET_PROTO_HDR_TYPE(hdr, IPV4);
619 if (ipv4_spec && ipv4_mask) {
620 if (ipv4_mask->hdr.version_ihl ||
621 ipv4_mask->hdr.total_length ||
622 ipv4_mask->hdr.packet_id ||
623 ipv4_mask->hdr.fragment_offset ||
624 ipv4_mask->hdr.hdr_checksum) {
625 rte_flow_error_set(error, EINVAL,
626 RTE_FLOW_ERROR_TYPE_ITEM,
627 item, "Invalid IPv4 mask.");
631 if (ipv4_mask->hdr.type_of_service ==
633 input_set |= IAVF_INSET_IPV4_TOS;
634 VIRTCHNL_ADD_PROTO_HDR_FIELD_BIT(hdr, IPV4, DSCP);
636 if (ipv4_mask->hdr.next_proto_id == UINT8_MAX) {
637 input_set |= IAVF_INSET_IPV4_PROTO;
638 VIRTCHNL_ADD_PROTO_HDR_FIELD_BIT(hdr, IPV4, PROT);
640 if (ipv4_mask->hdr.time_to_live == UINT8_MAX) {
641 input_set |= IAVF_INSET_IPV4_TTL;
642 VIRTCHNL_ADD_PROTO_HDR_FIELD_BIT(hdr, IPV4, TTL);
644 if (ipv4_mask->hdr.src_addr == UINT32_MAX) {
645 input_set |= IAVF_INSET_IPV4_SRC;
646 VIRTCHNL_ADD_PROTO_HDR_FIELD_BIT(hdr, IPV4, SRC);
648 if (ipv4_mask->hdr.dst_addr == UINT32_MAX) {
649 input_set |= IAVF_INSET_IPV4_DST;
650 VIRTCHNL_ADD_PROTO_HDR_FIELD_BIT(hdr, IPV4, DST);
653 rte_memcpy(hdr->buffer,
655 sizeof(ipv4_spec->hdr));
658 filter->add_fltr.rule_cfg.proto_hdrs.count = ++layer;
661 case RTE_FLOW_ITEM_TYPE_IPV6:
662 l3 = RTE_FLOW_ITEM_TYPE_IPV6;
663 ipv6_spec = item->spec;
664 ipv6_mask = item->mask;
666 hdr = &filter->add_fltr.rule_cfg.proto_hdrs.proto_hdr[layer];
668 VIRTCHNL_SET_PROTO_HDR_TYPE(hdr, IPV6);
670 if (ipv6_spec && ipv6_mask) {
671 if (ipv6_mask->hdr.payload_len) {
672 rte_flow_error_set(error, EINVAL,
673 RTE_FLOW_ERROR_TYPE_ITEM,
674 item, "Invalid IPv6 mask");
678 if ((ipv6_mask->hdr.vtc_flow &
679 rte_cpu_to_be_32(IAVF_IPV6_TC_MASK))
680 == rte_cpu_to_be_32(IAVF_IPV6_TC_MASK)) {
681 input_set |= IAVF_INSET_IPV6_TC;
682 VIRTCHNL_ADD_PROTO_HDR_FIELD_BIT(hdr, IPV6, TC);
684 if (ipv6_mask->hdr.proto == UINT8_MAX) {
685 input_set |= IAVF_INSET_IPV6_NEXT_HDR;
686 VIRTCHNL_ADD_PROTO_HDR_FIELD_BIT(hdr, IPV6, PROT);
688 if (ipv6_mask->hdr.hop_limits == UINT8_MAX) {
689 input_set |= IAVF_INSET_IPV6_HOP_LIMIT;
690 VIRTCHNL_ADD_PROTO_HDR_FIELD_BIT(hdr, IPV6, HOP_LIMIT);
692 if (!memcmp(ipv6_mask->hdr.src_addr,
694 RTE_DIM(ipv6_mask->hdr.src_addr))) {
695 input_set |= IAVF_INSET_IPV6_SRC;
696 VIRTCHNL_ADD_PROTO_HDR_FIELD_BIT(hdr, IPV6, SRC);
698 if (!memcmp(ipv6_mask->hdr.dst_addr,
700 RTE_DIM(ipv6_mask->hdr.dst_addr))) {
701 input_set |= IAVF_INSET_IPV6_DST;
702 VIRTCHNL_ADD_PROTO_HDR_FIELD_BIT(hdr, IPV6, DST);
705 rte_memcpy(hdr->buffer,
707 sizeof(ipv6_spec->hdr));
710 filter->add_fltr.rule_cfg.proto_hdrs.count = ++layer;
713 case RTE_FLOW_ITEM_TYPE_UDP:
714 udp_spec = item->spec;
715 udp_mask = item->mask;
717 hdr = &filter->add_fltr.rule_cfg.proto_hdrs.proto_hdr[layer];
719 VIRTCHNL_SET_PROTO_HDR_TYPE(hdr, UDP);
721 if (udp_spec && udp_mask) {
722 if (udp_mask->hdr.dgram_len ||
723 udp_mask->hdr.dgram_cksum) {
724 rte_flow_error_set(error, EINVAL,
725 RTE_FLOW_ERROR_TYPE_ITEM, item,
730 if (udp_mask->hdr.src_port == UINT16_MAX) {
731 input_set |= IAVF_INSET_UDP_SRC_PORT;
732 VIRTCHNL_ADD_PROTO_HDR_FIELD_BIT(hdr, UDP, SRC_PORT);
734 if (udp_mask->hdr.dst_port == UINT16_MAX) {
735 input_set |= IAVF_INSET_UDP_DST_PORT;
736 VIRTCHNL_ADD_PROTO_HDR_FIELD_BIT(hdr, UDP, DST_PORT);
739 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4)
740 rte_memcpy(hdr->buffer,
742 sizeof(udp_spec->hdr));
743 else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6)
744 rte_memcpy(hdr->buffer,
746 sizeof(udp_spec->hdr));
749 filter->add_fltr.rule_cfg.proto_hdrs.count = ++layer;
752 case RTE_FLOW_ITEM_TYPE_TCP:
753 tcp_spec = item->spec;
754 tcp_mask = item->mask;
756 hdr = &filter->add_fltr.rule_cfg.proto_hdrs.proto_hdr[layer];
758 VIRTCHNL_SET_PROTO_HDR_TYPE(hdr, TCP);
760 if (tcp_spec && tcp_mask) {
761 if (tcp_mask->hdr.sent_seq ||
762 tcp_mask->hdr.recv_ack ||
763 tcp_mask->hdr.data_off ||
764 tcp_mask->hdr.tcp_flags ||
765 tcp_mask->hdr.rx_win ||
766 tcp_mask->hdr.cksum ||
767 tcp_mask->hdr.tcp_urp) {
768 rte_flow_error_set(error, EINVAL,
769 RTE_FLOW_ERROR_TYPE_ITEM, item,
774 if (tcp_mask->hdr.src_port == UINT16_MAX) {
775 input_set |= IAVF_INSET_TCP_SRC_PORT;
776 VIRTCHNL_ADD_PROTO_HDR_FIELD_BIT(hdr, TCP, SRC_PORT);
778 if (tcp_mask->hdr.dst_port == UINT16_MAX) {
779 input_set |= IAVF_INSET_TCP_DST_PORT;
780 VIRTCHNL_ADD_PROTO_HDR_FIELD_BIT(hdr, TCP, DST_PORT);
783 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4)
784 rte_memcpy(hdr->buffer,
786 sizeof(tcp_spec->hdr));
787 else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6)
788 rte_memcpy(hdr->buffer,
790 sizeof(tcp_spec->hdr));
793 filter->add_fltr.rule_cfg.proto_hdrs.count = ++layer;
796 case RTE_FLOW_ITEM_TYPE_SCTP:
797 sctp_spec = item->spec;
798 sctp_mask = item->mask;
800 hdr = &filter->add_fltr.rule_cfg.proto_hdrs.proto_hdr[layer];
802 VIRTCHNL_SET_PROTO_HDR_TYPE(hdr, SCTP);
804 if (sctp_spec && sctp_mask) {
805 if (sctp_mask->hdr.cksum) {
806 rte_flow_error_set(error, EINVAL,
807 RTE_FLOW_ERROR_TYPE_ITEM, item,
812 if (sctp_mask->hdr.src_port == UINT16_MAX) {
813 input_set |= IAVF_INSET_SCTP_SRC_PORT;
814 VIRTCHNL_ADD_PROTO_HDR_FIELD_BIT(hdr, SCTP, SRC_PORT);
816 if (sctp_mask->hdr.dst_port == UINT16_MAX) {
817 input_set |= IAVF_INSET_SCTP_DST_PORT;
818 VIRTCHNL_ADD_PROTO_HDR_FIELD_BIT(hdr, SCTP, DST_PORT);
821 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4)
822 rte_memcpy(hdr->buffer,
824 sizeof(sctp_spec->hdr));
825 else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6)
826 rte_memcpy(hdr->buffer,
828 sizeof(sctp_spec->hdr));
831 filter->add_fltr.rule_cfg.proto_hdrs.count = ++layer;
834 case RTE_FLOW_ITEM_TYPE_GTPU:
835 gtp_spec = item->spec;
836 gtp_mask = item->mask;
838 hdr = &filter->add_fltr.rule_cfg.proto_hdrs.proto_hdr[layer];
840 VIRTCHNL_SET_PROTO_HDR_TYPE(hdr, GTPU_IP);
842 if (gtp_spec && gtp_mask) {
843 if (gtp_mask->v_pt_rsv_flags ||
844 gtp_mask->msg_type ||
846 rte_flow_error_set(error, EINVAL,
847 RTE_FLOW_ERROR_TYPE_ITEM,
848 item, "Invalid GTP mask");
852 if (gtp_mask->teid == UINT32_MAX) {
853 input_set |= IAVF_INSET_GTPU_TEID;
854 VIRTCHNL_ADD_PROTO_HDR_FIELD_BIT(hdr, GTPU_IP, TEID);
857 rte_memcpy(hdr->buffer,
858 gtp_spec, sizeof(*gtp_spec));
861 filter->add_fltr.rule_cfg.proto_hdrs.count = ++layer;
864 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
865 gtp_psc_spec = item->spec;
866 gtp_psc_mask = item->mask;
868 hdr = &filter->add_fltr.rule_cfg.proto_hdrs.proto_hdr[layer];
871 VIRTCHNL_SET_PROTO_HDR_TYPE(hdr, GTPU_EH);
872 else if ((gtp_psc_mask->qfi) && !(gtp_psc_mask->pdu_type))
873 VIRTCHNL_SET_PROTO_HDR_TYPE(hdr, GTPU_EH);
874 else if (gtp_psc_spec->pdu_type == IAVF_GTPU_EH_UPLINK)
875 VIRTCHNL_SET_PROTO_HDR_TYPE(hdr, GTPU_EH_PDU_UP);
876 else if (gtp_psc_spec->pdu_type == IAVF_GTPU_EH_DWLINK)
877 VIRTCHNL_SET_PROTO_HDR_TYPE(hdr, GTPU_EH_PDU_DWN);
879 if (gtp_psc_spec && gtp_psc_mask) {
880 if (gtp_psc_mask->qfi == UINT8_MAX) {
881 input_set |= IAVF_INSET_GTPU_QFI;
882 VIRTCHNL_ADD_PROTO_HDR_FIELD_BIT(hdr, GTPU_EH, QFI);
885 rte_memcpy(hdr->buffer, gtp_psc_spec,
886 sizeof(*gtp_psc_spec));
889 filter->add_fltr.rule_cfg.proto_hdrs.count = ++layer;
892 case RTE_FLOW_ITEM_TYPE_L2TPV3OIP:
893 l2tpv3oip_spec = item->spec;
894 l2tpv3oip_mask = item->mask;
896 hdr = &filter->add_fltr.rule_cfg.proto_hdrs.proto_hdr[layer];
898 VIRTCHNL_SET_PROTO_HDR_TYPE(hdr, L2TPV3);
900 if (l2tpv3oip_spec && l2tpv3oip_mask) {
901 if (l2tpv3oip_mask->session_id == UINT32_MAX) {
902 input_set |= IAVF_L2TPV3OIP_SESSION_ID;
903 VIRTCHNL_ADD_PROTO_HDR_FIELD_BIT(hdr, L2TPV3, SESS_ID);
906 rte_memcpy(hdr->buffer, l2tpv3oip_spec,
907 sizeof(*l2tpv3oip_spec));
910 filter->add_fltr.rule_cfg.proto_hdrs.count = ++layer;
913 case RTE_FLOW_ITEM_TYPE_ESP:
914 esp_spec = item->spec;
915 esp_mask = item->mask;
917 hdr = &filter->add_fltr.rule_cfg.proto_hdrs.proto_hdr[layer];
919 VIRTCHNL_SET_PROTO_HDR_TYPE(hdr, ESP);
921 if (esp_spec && esp_mask) {
922 if (esp_mask->hdr.spi == UINT32_MAX) {
923 input_set |= IAVF_INSET_ESP_SPI;
924 VIRTCHNL_ADD_PROTO_HDR_FIELD_BIT(hdr, ESP, SPI);
927 rte_memcpy(hdr->buffer, &esp_spec->hdr,
928 sizeof(esp_spec->hdr));
931 filter->add_fltr.rule_cfg.proto_hdrs.count = ++layer;
934 case RTE_FLOW_ITEM_TYPE_AH:
935 ah_spec = item->spec;
936 ah_mask = item->mask;
938 hdr = &filter->add_fltr.rule_cfg.proto_hdrs.proto_hdr[layer];
940 VIRTCHNL_SET_PROTO_HDR_TYPE(hdr, AH);
942 if (ah_spec && ah_mask) {
943 if (ah_mask->spi == UINT32_MAX) {
944 input_set |= IAVF_INSET_AH_SPI;
945 VIRTCHNL_ADD_PROTO_HDR_FIELD_BIT(hdr, AH, SPI);
948 rte_memcpy(hdr->buffer, ah_spec,
952 filter->add_fltr.rule_cfg.proto_hdrs.count = ++layer;
955 case RTE_FLOW_ITEM_TYPE_PFCP:
956 pfcp_spec = item->spec;
957 pfcp_mask = item->mask;
959 hdr = &filter->add_fltr.rule_cfg.proto_hdrs.proto_hdr[layer];
961 VIRTCHNL_SET_PROTO_HDR_TYPE(hdr, PFCP);
963 if (pfcp_spec && pfcp_mask) {
964 if (pfcp_mask->s_field == UINT8_MAX) {
965 input_set |= IAVF_INSET_PFCP_S_FIELD;
966 VIRTCHNL_ADD_PROTO_HDR_FIELD_BIT(hdr, PFCP, S_FIELD);
969 rte_memcpy(hdr->buffer, pfcp_spec,
973 filter->add_fltr.rule_cfg.proto_hdrs.count = ++layer;
976 case RTE_FLOW_ITEM_TYPE_ECPRI:
977 ecpri_spec = item->spec;
978 ecpri_mask = item->mask;
980 ecpri_common.u32 = rte_be_to_cpu_32(ecpri_spec->hdr.common.u32);
982 hdr = &filter->add_fltr.rule_cfg.proto_hdrs.proto_hdr[layer];
984 VIRTCHNL_SET_PROTO_HDR_TYPE(hdr, ECPRI);
986 if (ecpri_spec && ecpri_mask) {
987 if (ecpri_common.type == RTE_ECPRI_MSG_TYPE_IQ_DATA &&
988 ecpri_mask->hdr.type0.pc_id == UINT16_MAX) {
989 input_set |= IAVF_ECPRI_PC_RTC_ID;
990 VIRTCHNL_ADD_PROTO_HDR_FIELD_BIT(hdr, ECPRI,
994 rte_memcpy(hdr->buffer, ecpri_spec,
995 sizeof(*ecpri_spec));
998 filter->add_fltr.rule_cfg.proto_hdrs.count = ++layer;
1001 case RTE_FLOW_ITEM_TYPE_VOID:
1005 rte_flow_error_set(error, EINVAL,
1006 RTE_FLOW_ERROR_TYPE_ITEM, item,
1007 "Invalid pattern item.");
1012 if (layer > VIRTCHNL_MAX_NUM_PROTO_HDRS) {
1013 rte_flow_error_set(error, EINVAL,
1014 RTE_FLOW_ERROR_TYPE_ITEM, item,
1015 "Protocol header layers exceed the maximum value");
1019 if (!iavf_fdir_refine_input_set(input_set, input_set_mask, filter)) {
1020 rte_flow_error_set(error, EINVAL,
1021 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, pattern,
1022 "Invalid input set");
1026 filter->input_set = input_set;
1032 iavf_fdir_parse(struct iavf_adapter *ad,
1033 struct iavf_pattern_match_item *array,
1035 const struct rte_flow_item pattern[],
1036 const struct rte_flow_action actions[],
1038 struct rte_flow_error *error)
1040 struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(ad);
1041 struct iavf_fdir_conf *filter = &vf->fdir.conf;
1042 struct iavf_pattern_match_item *item = NULL;
1045 memset(filter, 0, sizeof(*filter));
1047 item = iavf_search_pattern_match_item(pattern, array, array_len, error);
1051 ret = iavf_fdir_parse_pattern(ad, pattern, item->input_set_mask,
1056 ret = iavf_fdir_parse_action(ad, actions, error, filter);
1068 static struct iavf_flow_parser iavf_fdir_parser = {
1069 .engine = &iavf_fdir_engine,
1070 .array = iavf_fdir_pattern,
1071 .array_len = RTE_DIM(iavf_fdir_pattern),
1072 .parse_pattern_action = iavf_fdir_parse,
1073 .stage = IAVF_FLOW_STAGE_DISTRIBUTOR,
1076 RTE_INIT(iavf_fdir_engine_register)
1078 iavf_register_flow_engine(&iavf_fdir_engine);