1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2020 Intel Corporation
13 #include <rte_ether.h>
14 #include <rte_ethdev_driver.h>
15 #include <rte_malloc.h>
16 #include <rte_tailq.h>
19 #include "iavf_generic_flow.h"
21 #include "iavf_rxtx.h"
23 #define IAVF_FDIR_MAX_QREGION_SIZE 128
25 #define IAVF_FDIR_IPV6_TC_OFFSET 20
26 #define IAVF_IPV6_TC_MASK (0xFF << IAVF_FDIR_IPV6_TC_OFFSET)
28 #define IAVF_FDIR_INSET_ETH (\
31 #define IAVF_FDIR_INSET_ETH_IPV4 (\
32 IAVF_INSET_IPV4_SRC | IAVF_INSET_IPV4_DST | \
33 IAVF_INSET_IPV4_PROTO | IAVF_INSET_IPV4_TOS | \
36 #define IAVF_FDIR_INSET_ETH_IPV4_UDP (\
37 IAVF_INSET_IPV4_SRC | IAVF_INSET_IPV4_DST | \
38 IAVF_INSET_IPV4_TOS | IAVF_INSET_IPV4_TTL | \
39 IAVF_INSET_UDP_SRC_PORT | IAVF_INSET_UDP_DST_PORT)
41 #define IAVF_FDIR_INSET_ETH_IPV4_TCP (\
42 IAVF_INSET_IPV4_SRC | IAVF_INSET_IPV4_DST | \
43 IAVF_INSET_IPV4_TOS | IAVF_INSET_IPV4_TTL | \
44 IAVF_INSET_TCP_SRC_PORT | IAVF_INSET_TCP_DST_PORT)
46 #define IAVF_FDIR_INSET_ETH_IPV4_SCTP (\
47 IAVF_INSET_IPV4_SRC | IAVF_INSET_IPV4_DST | \
48 IAVF_INSET_IPV4_TOS | IAVF_INSET_IPV4_TTL | \
49 IAVF_INSET_SCTP_SRC_PORT | IAVF_INSET_SCTP_DST_PORT)
51 #define IAVF_FDIR_INSET_ETH_IPV6 (\
52 IAVF_INSET_IPV6_SRC | IAVF_INSET_IPV6_DST | \
53 IAVF_INSET_IPV6_NEXT_HDR | IAVF_INSET_IPV6_TC | \
54 IAVF_INSET_IPV6_HOP_LIMIT)
56 #define IAVF_FDIR_INSET_ETH_IPV6_UDP (\
57 IAVF_INSET_IPV6_SRC | IAVF_INSET_IPV6_DST | \
58 IAVF_INSET_IPV6_TC | IAVF_INSET_IPV6_HOP_LIMIT | \
59 IAVF_INSET_UDP_SRC_PORT | IAVF_INSET_UDP_DST_PORT)
61 #define IAVF_FDIR_INSET_ETH_IPV6_TCP (\
62 IAVF_INSET_IPV6_SRC | IAVF_INSET_IPV6_DST | \
63 IAVF_INSET_IPV6_TC | IAVF_INSET_IPV6_HOP_LIMIT | \
64 IAVF_INSET_TCP_SRC_PORT | IAVF_INSET_TCP_DST_PORT)
66 #define IAVF_FDIR_INSET_ETH_IPV6_SCTP (\
67 IAVF_INSET_IPV6_SRC | IAVF_INSET_IPV6_DST | \
68 IAVF_INSET_IPV6_TC | IAVF_INSET_IPV6_HOP_LIMIT | \
69 IAVF_INSET_SCTP_SRC_PORT | IAVF_INSET_SCTP_DST_PORT)
71 #define IAVF_FDIR_INSET_IPV4_GTPU (\
72 IAVF_INSET_IPV4_SRC | IAVF_INSET_IPV4_DST | \
75 #define IAVF_FDIR_INSET_IPV4_GTPU_EH (\
76 IAVF_INSET_IPV4_SRC | IAVF_INSET_IPV4_DST | \
77 IAVF_INSET_GTPU_TEID | IAVF_INSET_GTPU_QFI)
79 #define IAVF_FDIR_INSET_IPV6_GTPU (\
80 IAVF_INSET_IPV6_SRC | IAVF_INSET_IPV6_DST | \
83 #define IAVF_FDIR_INSET_IPV6_GTPU_EH (\
84 IAVF_INSET_IPV6_SRC | IAVF_INSET_IPV6_DST | \
85 IAVF_INSET_GTPU_TEID | IAVF_INSET_GTPU_QFI)
87 #define IAVF_FDIR_INSET_L2TPV3OIP (\
88 IAVF_L2TPV3OIP_SESSION_ID)
90 #define IAVF_FDIR_INSET_ESP (\
93 #define IAVF_FDIR_INSET_AH (\
96 #define IAVF_FDIR_INSET_IPV4_NATT_ESP (\
97 IAVF_INSET_IPV4_SRC | IAVF_INSET_IPV4_DST | \
100 #define IAVF_FDIR_INSET_IPV6_NATT_ESP (\
101 IAVF_INSET_IPV6_SRC | IAVF_INSET_IPV6_DST | \
104 #define IAVF_FDIR_INSET_PFCP (\
105 IAVF_INSET_PFCP_S_FIELD)
107 #define IAVF_FDIR_INSET_ECPRI (\
110 static struct iavf_pattern_match_item iavf_fdir_pattern[] = {
111 {iavf_pattern_ethertype, IAVF_FDIR_INSET_ETH, IAVF_INSET_NONE},
112 {iavf_pattern_eth_ipv4, IAVF_FDIR_INSET_ETH_IPV4, IAVF_INSET_NONE},
113 {iavf_pattern_eth_ipv4_udp, IAVF_FDIR_INSET_ETH_IPV4_UDP, IAVF_INSET_NONE},
114 {iavf_pattern_eth_ipv4_tcp, IAVF_FDIR_INSET_ETH_IPV4_TCP, IAVF_INSET_NONE},
115 {iavf_pattern_eth_ipv4_sctp, IAVF_FDIR_INSET_ETH_IPV4_SCTP, IAVF_INSET_NONE},
116 {iavf_pattern_eth_ipv6, IAVF_FDIR_INSET_ETH_IPV6, IAVF_INSET_NONE},
117 {iavf_pattern_eth_ipv6_udp, IAVF_FDIR_INSET_ETH_IPV6_UDP, IAVF_INSET_NONE},
118 {iavf_pattern_eth_ipv6_tcp, IAVF_FDIR_INSET_ETH_IPV6_TCP, IAVF_INSET_NONE},
119 {iavf_pattern_eth_ipv6_sctp, IAVF_FDIR_INSET_ETH_IPV6_SCTP, IAVF_INSET_NONE},
120 {iavf_pattern_eth_ipv4_gtpu, IAVF_FDIR_INSET_IPV4_GTPU, IAVF_INSET_NONE},
121 {iavf_pattern_eth_ipv4_gtpu_eh, IAVF_FDIR_INSET_IPV4_GTPU_EH, IAVF_INSET_NONE},
122 {iavf_pattern_eth_ipv6_gtpu, IAVF_FDIR_INSET_IPV6_GTPU, IAVF_INSET_NONE},
123 {iavf_pattern_eth_ipv6_gtpu_eh, IAVF_FDIR_INSET_IPV6_GTPU_EH, IAVF_INSET_NONE},
124 {iavf_pattern_eth_ipv4_l2tpv3, IAVF_FDIR_INSET_L2TPV3OIP, IAVF_INSET_NONE},
125 {iavf_pattern_eth_ipv6_l2tpv3, IAVF_FDIR_INSET_L2TPV3OIP, IAVF_INSET_NONE},
126 {iavf_pattern_eth_ipv4_esp, IAVF_FDIR_INSET_ESP, IAVF_INSET_NONE},
127 {iavf_pattern_eth_ipv6_esp, IAVF_FDIR_INSET_ESP, IAVF_INSET_NONE},
128 {iavf_pattern_eth_ipv4_ah, IAVF_FDIR_INSET_AH, IAVF_INSET_NONE},
129 {iavf_pattern_eth_ipv6_ah, IAVF_FDIR_INSET_AH, IAVF_INSET_NONE},
130 {iavf_pattern_eth_ipv4_udp_esp, IAVF_FDIR_INSET_IPV4_NATT_ESP, IAVF_INSET_NONE},
131 {iavf_pattern_eth_ipv6_udp_esp, IAVF_FDIR_INSET_IPV6_NATT_ESP, IAVF_INSET_NONE},
132 {iavf_pattern_eth_ipv4_pfcp, IAVF_FDIR_INSET_PFCP, IAVF_INSET_NONE},
133 {iavf_pattern_eth_ipv6_pfcp, IAVF_FDIR_INSET_PFCP, IAVF_INSET_NONE},
134 {iavf_pattern_eth_ecpri, IAVF_FDIR_INSET_ECPRI, IAVF_INSET_NONE},
135 {iavf_pattern_eth_ipv4_ecpri, IAVF_FDIR_INSET_ECPRI, IAVF_INSET_NONE},
138 static struct iavf_flow_parser iavf_fdir_parser;
141 iavf_fdir_init(struct iavf_adapter *ad)
143 struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(ad);
144 struct iavf_flow_parser *parser;
149 if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_FDIR_PF)
150 parser = &iavf_fdir_parser;
154 return iavf_register_parser(parser, ad);
158 iavf_fdir_uninit(struct iavf_adapter *ad)
160 iavf_unregister_parser(&iavf_fdir_parser, ad);
164 iavf_fdir_create(struct iavf_adapter *ad,
165 struct rte_flow *flow,
167 struct rte_flow_error *error)
169 struct iavf_fdir_conf *filter = meta;
170 struct iavf_fdir_conf *rule;
173 rule = rte_zmalloc("fdir_entry", sizeof(*rule), 0);
175 rte_flow_error_set(error, ENOMEM,
176 RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
177 "Failed to allocate memory for fdir rule");
181 ret = iavf_fdir_add(ad, filter);
183 rte_flow_error_set(error, -ret,
184 RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
185 "Failed to add filter rule.");
189 if (filter->mark_flag == 1)
190 iavf_fdir_rx_proc_enable(ad, 1);
192 rte_memcpy(rule, filter, sizeof(*rule));
203 iavf_fdir_destroy(struct iavf_adapter *ad,
204 struct rte_flow *flow,
205 struct rte_flow_error *error)
207 struct iavf_fdir_conf *filter;
210 filter = (struct iavf_fdir_conf *)flow->rule;
212 ret = iavf_fdir_del(ad, filter);
214 rte_flow_error_set(error, -ret,
215 RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
216 "Failed to delete filter rule.");
220 if (filter->mark_flag == 1)
221 iavf_fdir_rx_proc_enable(ad, 0);
230 iavf_fdir_validation(struct iavf_adapter *ad,
231 __rte_unused struct rte_flow *flow,
233 struct rte_flow_error *error)
235 struct iavf_fdir_conf *filter = meta;
238 ret = iavf_fdir_check(ad, filter);
240 rte_flow_error_set(error, -ret,
241 RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
242 "Failed to validate filter rule.");
249 static struct iavf_flow_engine iavf_fdir_engine = {
250 .init = iavf_fdir_init,
251 .uninit = iavf_fdir_uninit,
252 .create = iavf_fdir_create,
253 .destroy = iavf_fdir_destroy,
254 .validation = iavf_fdir_validation,
255 .type = IAVF_FLOW_ENGINE_FDIR,
259 iavf_fdir_parse_action_qregion(struct iavf_adapter *ad,
260 struct rte_flow_error *error,
261 const struct rte_flow_action *act,
262 struct virtchnl_filter_action *filter_action)
264 struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(ad);
265 const struct rte_flow_action_rss *rss = act->conf;
268 if (act->type != RTE_FLOW_ACTION_TYPE_RSS) {
269 rte_flow_error_set(error, EINVAL,
270 RTE_FLOW_ERROR_TYPE_ACTION, act,
275 if (rss->queue_num <= 1) {
276 rte_flow_error_set(error, EINVAL,
277 RTE_FLOW_ERROR_TYPE_ACTION, act,
278 "Queue region size can't be 0 or 1.");
282 /* check if queue index for queue region is continuous */
283 for (i = 0; i < rss->queue_num - 1; i++) {
284 if (rss->queue[i + 1] != rss->queue[i] + 1) {
285 rte_flow_error_set(error, EINVAL,
286 RTE_FLOW_ERROR_TYPE_ACTION, act,
287 "Discontinuous queue region");
292 if (rss->queue[rss->queue_num - 1] >= ad->eth_dev->data->nb_rx_queues) {
293 rte_flow_error_set(error, EINVAL,
294 RTE_FLOW_ERROR_TYPE_ACTION, act,
295 "Invalid queue region indexes.");
299 if (!(rte_is_power_of_2(rss->queue_num) &&
300 rss->queue_num <= IAVF_FDIR_MAX_QREGION_SIZE)) {
301 rte_flow_error_set(error, EINVAL,
302 RTE_FLOW_ERROR_TYPE_ACTION, act,
303 "The region size should be any of the following values:"
304 "1, 2, 4, 8, 16, 32, 64, 128 as long as the total number "
305 "of queues do not exceed the VSI allocation.");
309 if (rss->queue_num > vf->max_rss_qregion) {
310 rte_flow_error_set(error, EINVAL,
311 RTE_FLOW_ERROR_TYPE_ACTION, act,
312 "The region size cannot be large than the supported max RSS queue region");
316 filter_action->act_conf.queue.index = rss->queue[0];
317 filter_action->act_conf.queue.region = rte_fls_u32(rss->queue_num) - 1;
323 iavf_fdir_parse_action(struct iavf_adapter *ad,
324 const struct rte_flow_action actions[],
325 struct rte_flow_error *error,
326 struct iavf_fdir_conf *filter)
328 const struct rte_flow_action_queue *act_q;
329 const struct rte_flow_action_mark *mark_spec = NULL;
330 uint32_t dest_num = 0;
331 uint32_t mark_num = 0;
335 struct virtchnl_filter_action *filter_action;
337 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
338 switch (actions->type) {
339 case RTE_FLOW_ACTION_TYPE_VOID:
342 case RTE_FLOW_ACTION_TYPE_PASSTHRU:
345 filter_action = &filter->add_fltr.rule_cfg.action_set.actions[number];
347 filter_action->type = VIRTCHNL_ACTION_PASSTHRU;
349 filter->add_fltr.rule_cfg.action_set.count = ++number;
352 case RTE_FLOW_ACTION_TYPE_DROP:
355 filter_action = &filter->add_fltr.rule_cfg.action_set.actions[number];
357 filter_action->type = VIRTCHNL_ACTION_DROP;
359 filter->add_fltr.rule_cfg.action_set.count = ++number;
362 case RTE_FLOW_ACTION_TYPE_QUEUE:
365 act_q = actions->conf;
366 filter_action = &filter->add_fltr.rule_cfg.action_set.actions[number];
368 filter_action->type = VIRTCHNL_ACTION_QUEUE;
369 filter_action->act_conf.queue.index = act_q->index;
371 if (filter_action->act_conf.queue.index >=
372 ad->eth_dev->data->nb_rx_queues) {
373 rte_flow_error_set(error, EINVAL,
374 RTE_FLOW_ERROR_TYPE_ACTION,
375 actions, "Invalid queue for FDIR.");
379 filter->add_fltr.rule_cfg.action_set.count = ++number;
382 case RTE_FLOW_ACTION_TYPE_RSS:
385 filter_action = &filter->add_fltr.rule_cfg.action_set.actions[number];
387 filter_action->type = VIRTCHNL_ACTION_Q_REGION;
389 ret = iavf_fdir_parse_action_qregion(ad,
390 error, actions, filter_action);
394 filter->add_fltr.rule_cfg.action_set.count = ++number;
397 case RTE_FLOW_ACTION_TYPE_MARK:
400 filter->mark_flag = 1;
401 mark_spec = actions->conf;
402 filter_action = &filter->add_fltr.rule_cfg.action_set.actions[number];
404 filter_action->type = VIRTCHNL_ACTION_MARK;
405 filter_action->act_conf.mark_id = mark_spec->id;
407 filter->add_fltr.rule_cfg.action_set.count = ++number;
411 rte_flow_error_set(error, EINVAL,
412 RTE_FLOW_ERROR_TYPE_ACTION, actions,
418 if (number > VIRTCHNL_MAX_NUM_ACTIONS) {
419 rte_flow_error_set(error, EINVAL,
420 RTE_FLOW_ERROR_TYPE_ACTION, actions,
421 "Action numbers exceed the maximum value");
426 rte_flow_error_set(error, EINVAL,
427 RTE_FLOW_ERROR_TYPE_ACTION, actions,
428 "Unsupported action combination");
433 rte_flow_error_set(error, EINVAL,
434 RTE_FLOW_ERROR_TYPE_ACTION, actions,
435 "Too many mark actions");
439 if (dest_num + mark_num == 0) {
440 rte_flow_error_set(error, EINVAL,
441 RTE_FLOW_ERROR_TYPE_ACTION, actions,
446 /* Mark only is equal to mark + passthru. */
448 filter_action = &filter->add_fltr.rule_cfg.action_set.actions[number];
449 filter_action->type = VIRTCHNL_ACTION_PASSTHRU;
450 filter->add_fltr.rule_cfg.action_set.count = ++number;
457 iavf_fdir_parse_pattern(__rte_unused struct iavf_adapter *ad,
458 const struct rte_flow_item pattern[],
459 struct rte_flow_error *error,
460 struct iavf_fdir_conf *filter)
462 const struct rte_flow_item *item = pattern;
463 enum rte_flow_item_type item_type;
464 enum rte_flow_item_type l3 = RTE_FLOW_ITEM_TYPE_END;
465 const struct rte_flow_item_eth *eth_spec, *eth_mask;
466 const struct rte_flow_item_ipv4 *ipv4_spec, *ipv4_mask;
467 const struct rte_flow_item_ipv6 *ipv6_spec, *ipv6_mask;
468 const struct rte_flow_item_udp *udp_spec, *udp_mask;
469 const struct rte_flow_item_tcp *tcp_spec, *tcp_mask;
470 const struct rte_flow_item_sctp *sctp_spec, *sctp_mask;
471 const struct rte_flow_item_gtp *gtp_spec, *gtp_mask;
472 const struct rte_flow_item_gtp_psc *gtp_psc_spec, *gtp_psc_mask;
473 const struct rte_flow_item_l2tpv3oip *l2tpv3oip_spec, *l2tpv3oip_mask;
474 const struct rte_flow_item_esp *esp_spec, *esp_mask;
475 const struct rte_flow_item_ah *ah_spec, *ah_mask;
476 const struct rte_flow_item_pfcp *pfcp_spec, *pfcp_mask;
477 const struct rte_flow_item_ecpri *ecpri_spec, *ecpri_mask;
478 struct rte_ecpri_common_hdr ecpri_common;
479 uint64_t input_set = IAVF_INSET_NONE;
481 enum rte_flow_item_type next_type;
485 struct virtchnl_proto_hdr *hdr;
487 uint8_t ipv6_addr_mask[16] = {
488 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
489 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF
492 for (item = pattern; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
494 rte_flow_error_set(error, EINVAL,
495 RTE_FLOW_ERROR_TYPE_ITEM, item,
496 "Not support range");
499 item_type = item->type;
502 case RTE_FLOW_ITEM_TYPE_ETH:
503 eth_spec = item->spec;
504 eth_mask = item->mask;
505 next_type = (item + 1)->type;
507 hdr = &filter->add_fltr.rule_cfg.proto_hdrs.proto_hdr[layer];
509 VIRTCHNL_SET_PROTO_HDR_TYPE(hdr, ETH);
511 if (next_type == RTE_FLOW_ITEM_TYPE_END &&
512 (!eth_spec || !eth_mask)) {
513 rte_flow_error_set(error, EINVAL,
514 RTE_FLOW_ERROR_TYPE_ITEM,
515 item, "NULL eth spec/mask.");
519 if (eth_spec && eth_mask) {
520 if (!rte_is_zero_ether_addr(ð_mask->src) ||
521 !rte_is_zero_ether_addr(ð_mask->dst)) {
522 rte_flow_error_set(error, EINVAL,
523 RTE_FLOW_ERROR_TYPE_ITEM, item,
524 "Invalid MAC_addr mask.");
529 if (eth_spec && eth_mask && eth_mask->type) {
530 if (eth_mask->type != RTE_BE16(0xffff)) {
531 rte_flow_error_set(error, EINVAL,
532 RTE_FLOW_ERROR_TYPE_ITEM,
533 item, "Invalid type mask.");
537 ether_type = rte_be_to_cpu_16(eth_spec->type);
538 if (ether_type == RTE_ETHER_TYPE_IPV4 ||
539 ether_type == RTE_ETHER_TYPE_IPV6) {
540 rte_flow_error_set(error, EINVAL,
541 RTE_FLOW_ERROR_TYPE_ITEM,
543 "Unsupported ether_type.");
547 input_set |= IAVF_INSET_ETHERTYPE;
548 VIRTCHNL_ADD_PROTO_HDR_FIELD_BIT(hdr, ETH, ETHERTYPE);
550 rte_memcpy(hdr->buffer,
551 eth_spec, sizeof(struct rte_ether_hdr));
554 filter->add_fltr.rule_cfg.proto_hdrs.count = ++layer;
557 case RTE_FLOW_ITEM_TYPE_IPV4:
558 l3 = RTE_FLOW_ITEM_TYPE_IPV4;
559 ipv4_spec = item->spec;
560 ipv4_mask = item->mask;
562 hdr = &filter->add_fltr.rule_cfg.proto_hdrs.proto_hdr[layer];
564 VIRTCHNL_SET_PROTO_HDR_TYPE(hdr, IPV4);
566 if (ipv4_spec && ipv4_mask) {
567 if (ipv4_mask->hdr.version_ihl ||
568 ipv4_mask->hdr.total_length ||
569 ipv4_mask->hdr.packet_id ||
570 ipv4_mask->hdr.fragment_offset ||
571 ipv4_mask->hdr.hdr_checksum) {
572 rte_flow_error_set(error, EINVAL,
573 RTE_FLOW_ERROR_TYPE_ITEM,
574 item, "Invalid IPv4 mask.");
578 if (ipv4_mask->hdr.type_of_service ==
580 input_set |= IAVF_INSET_IPV4_TOS;
581 VIRTCHNL_ADD_PROTO_HDR_FIELD_BIT(hdr, IPV4, DSCP);
583 if (ipv4_mask->hdr.next_proto_id == UINT8_MAX) {
584 input_set |= IAVF_INSET_IPV4_PROTO;
585 VIRTCHNL_ADD_PROTO_HDR_FIELD_BIT(hdr, IPV4, PROT);
587 if (ipv4_mask->hdr.time_to_live == UINT8_MAX) {
588 input_set |= IAVF_INSET_IPV4_TTL;
589 VIRTCHNL_ADD_PROTO_HDR_FIELD_BIT(hdr, IPV4, TTL);
591 if (ipv4_mask->hdr.src_addr == UINT32_MAX) {
592 input_set |= IAVF_INSET_IPV4_SRC;
593 VIRTCHNL_ADD_PROTO_HDR_FIELD_BIT(hdr, IPV4, SRC);
595 if (ipv4_mask->hdr.dst_addr == UINT32_MAX) {
596 input_set |= IAVF_INSET_IPV4_DST;
597 VIRTCHNL_ADD_PROTO_HDR_FIELD_BIT(hdr, IPV4, DST);
600 rte_memcpy(hdr->buffer,
602 sizeof(ipv4_spec->hdr));
605 filter->add_fltr.rule_cfg.proto_hdrs.count = ++layer;
608 case RTE_FLOW_ITEM_TYPE_IPV6:
609 l3 = RTE_FLOW_ITEM_TYPE_IPV6;
610 ipv6_spec = item->spec;
611 ipv6_mask = item->mask;
613 hdr = &filter->add_fltr.rule_cfg.proto_hdrs.proto_hdr[layer];
615 VIRTCHNL_SET_PROTO_HDR_TYPE(hdr, IPV6);
617 if (ipv6_spec && ipv6_mask) {
618 if (ipv6_mask->hdr.payload_len) {
619 rte_flow_error_set(error, EINVAL,
620 RTE_FLOW_ERROR_TYPE_ITEM,
621 item, "Invalid IPv6 mask");
625 if ((ipv6_mask->hdr.vtc_flow &
626 rte_cpu_to_be_32(IAVF_IPV6_TC_MASK))
627 == rte_cpu_to_be_32(IAVF_IPV6_TC_MASK)) {
628 input_set |= IAVF_INSET_IPV6_TC;
629 VIRTCHNL_ADD_PROTO_HDR_FIELD_BIT(hdr, IPV6, TC);
631 if (ipv6_mask->hdr.proto == UINT8_MAX) {
632 input_set |= IAVF_INSET_IPV6_NEXT_HDR;
633 VIRTCHNL_ADD_PROTO_HDR_FIELD_BIT(hdr, IPV6, PROT);
635 if (ipv6_mask->hdr.hop_limits == UINT8_MAX) {
636 input_set |= IAVF_INSET_IPV6_HOP_LIMIT;
637 VIRTCHNL_ADD_PROTO_HDR_FIELD_BIT(hdr, IPV6, HOP_LIMIT);
639 if (!memcmp(ipv6_mask->hdr.src_addr,
641 RTE_DIM(ipv6_mask->hdr.src_addr))) {
642 input_set |= IAVF_INSET_IPV6_SRC;
643 VIRTCHNL_ADD_PROTO_HDR_FIELD_BIT(hdr, IPV6, SRC);
645 if (!memcmp(ipv6_mask->hdr.dst_addr,
647 RTE_DIM(ipv6_mask->hdr.dst_addr))) {
648 input_set |= IAVF_INSET_IPV6_DST;
649 VIRTCHNL_ADD_PROTO_HDR_FIELD_BIT(hdr, IPV6, DST);
652 rte_memcpy(hdr->buffer,
654 sizeof(ipv6_spec->hdr));
657 filter->add_fltr.rule_cfg.proto_hdrs.count = ++layer;
660 case RTE_FLOW_ITEM_TYPE_UDP:
661 udp_spec = item->spec;
662 udp_mask = item->mask;
664 hdr = &filter->add_fltr.rule_cfg.proto_hdrs.proto_hdr[layer];
666 VIRTCHNL_SET_PROTO_HDR_TYPE(hdr, UDP);
668 if (udp_spec && udp_mask) {
669 if (udp_mask->hdr.dgram_len ||
670 udp_mask->hdr.dgram_cksum) {
671 rte_flow_error_set(error, EINVAL,
672 RTE_FLOW_ERROR_TYPE_ITEM, item,
677 if (udp_mask->hdr.src_port == UINT16_MAX) {
678 input_set |= IAVF_INSET_UDP_SRC_PORT;
679 VIRTCHNL_ADD_PROTO_HDR_FIELD_BIT(hdr, UDP, SRC_PORT);
681 if (udp_mask->hdr.dst_port == UINT16_MAX) {
682 input_set |= IAVF_INSET_UDP_DST_PORT;
683 VIRTCHNL_ADD_PROTO_HDR_FIELD_BIT(hdr, UDP, DST_PORT);
686 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4)
687 rte_memcpy(hdr->buffer,
689 sizeof(udp_spec->hdr));
690 else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6)
691 rte_memcpy(hdr->buffer,
693 sizeof(udp_spec->hdr));
696 filter->add_fltr.rule_cfg.proto_hdrs.count = ++layer;
699 case RTE_FLOW_ITEM_TYPE_TCP:
700 tcp_spec = item->spec;
701 tcp_mask = item->mask;
703 hdr = &filter->add_fltr.rule_cfg.proto_hdrs.proto_hdr[layer];
705 VIRTCHNL_SET_PROTO_HDR_TYPE(hdr, TCP);
707 if (tcp_spec && tcp_mask) {
708 if (tcp_mask->hdr.sent_seq ||
709 tcp_mask->hdr.recv_ack ||
710 tcp_mask->hdr.data_off ||
711 tcp_mask->hdr.tcp_flags ||
712 tcp_mask->hdr.rx_win ||
713 tcp_mask->hdr.cksum ||
714 tcp_mask->hdr.tcp_urp) {
715 rte_flow_error_set(error, EINVAL,
716 RTE_FLOW_ERROR_TYPE_ITEM, item,
721 if (tcp_mask->hdr.src_port == UINT16_MAX) {
722 input_set |= IAVF_INSET_TCP_SRC_PORT;
723 VIRTCHNL_ADD_PROTO_HDR_FIELD_BIT(hdr, TCP, SRC_PORT);
725 if (tcp_mask->hdr.dst_port == UINT16_MAX) {
726 input_set |= IAVF_INSET_TCP_DST_PORT;
727 VIRTCHNL_ADD_PROTO_HDR_FIELD_BIT(hdr, TCP, DST_PORT);
730 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4)
731 rte_memcpy(hdr->buffer,
733 sizeof(tcp_spec->hdr));
734 else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6)
735 rte_memcpy(hdr->buffer,
737 sizeof(tcp_spec->hdr));
740 filter->add_fltr.rule_cfg.proto_hdrs.count = ++layer;
743 case RTE_FLOW_ITEM_TYPE_SCTP:
744 sctp_spec = item->spec;
745 sctp_mask = item->mask;
747 hdr = &filter->add_fltr.rule_cfg.proto_hdrs.proto_hdr[layer];
749 VIRTCHNL_SET_PROTO_HDR_TYPE(hdr, SCTP);
751 if (sctp_spec && sctp_mask) {
752 if (sctp_mask->hdr.cksum) {
753 rte_flow_error_set(error, EINVAL,
754 RTE_FLOW_ERROR_TYPE_ITEM, item,
759 if (sctp_mask->hdr.src_port == UINT16_MAX) {
760 input_set |= IAVF_INSET_SCTP_SRC_PORT;
761 VIRTCHNL_ADD_PROTO_HDR_FIELD_BIT(hdr, SCTP, SRC_PORT);
763 if (sctp_mask->hdr.dst_port == UINT16_MAX) {
764 input_set |= IAVF_INSET_SCTP_DST_PORT;
765 VIRTCHNL_ADD_PROTO_HDR_FIELD_BIT(hdr, SCTP, DST_PORT);
768 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4)
769 rte_memcpy(hdr->buffer,
771 sizeof(sctp_spec->hdr));
772 else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6)
773 rte_memcpy(hdr->buffer,
775 sizeof(sctp_spec->hdr));
778 filter->add_fltr.rule_cfg.proto_hdrs.count = ++layer;
781 case RTE_FLOW_ITEM_TYPE_GTPU:
782 gtp_spec = item->spec;
783 gtp_mask = item->mask;
785 hdr = &filter->add_fltr.rule_cfg.proto_hdrs.proto_hdr[layer];
787 VIRTCHNL_SET_PROTO_HDR_TYPE(hdr, GTPU_IP);
789 if (gtp_spec && gtp_mask) {
790 if (gtp_mask->v_pt_rsv_flags ||
791 gtp_mask->msg_type ||
793 rte_flow_error_set(error, EINVAL,
794 RTE_FLOW_ERROR_TYPE_ITEM,
795 item, "Invalid GTP mask");
799 if (gtp_mask->teid == UINT32_MAX) {
800 input_set |= IAVF_INSET_GTPU_TEID;
801 VIRTCHNL_ADD_PROTO_HDR_FIELD_BIT(hdr, GTPU_IP, TEID);
804 rte_memcpy(hdr->buffer,
805 gtp_spec, sizeof(*gtp_spec));
808 filter->add_fltr.rule_cfg.proto_hdrs.count = ++layer;
811 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
812 gtp_psc_spec = item->spec;
813 gtp_psc_mask = item->mask;
815 hdr = &filter->add_fltr.rule_cfg.proto_hdrs.proto_hdr[layer];
817 VIRTCHNL_SET_PROTO_HDR_TYPE(hdr, GTPU_EH);
819 if (gtp_psc_spec && gtp_psc_mask) {
820 if (gtp_psc_mask->qfi == UINT8_MAX) {
821 input_set |= IAVF_INSET_GTPU_QFI;
822 VIRTCHNL_ADD_PROTO_HDR_FIELD_BIT(hdr, GTPU_EH, QFI);
825 rte_memcpy(hdr->buffer, gtp_psc_spec,
826 sizeof(*gtp_psc_spec));
829 filter->add_fltr.rule_cfg.proto_hdrs.count = ++layer;
832 case RTE_FLOW_ITEM_TYPE_L2TPV3OIP:
833 l2tpv3oip_spec = item->spec;
834 l2tpv3oip_mask = item->mask;
836 hdr = &filter->add_fltr.rule_cfg.proto_hdrs.proto_hdr[layer];
838 VIRTCHNL_SET_PROTO_HDR_TYPE(hdr, L2TPV3);
840 if (l2tpv3oip_spec && l2tpv3oip_mask) {
841 if (l2tpv3oip_mask->session_id == UINT32_MAX) {
842 input_set |= IAVF_L2TPV3OIP_SESSION_ID;
843 VIRTCHNL_ADD_PROTO_HDR_FIELD_BIT(hdr, L2TPV3, SESS_ID);
846 rte_memcpy(hdr->buffer, l2tpv3oip_spec,
847 sizeof(*l2tpv3oip_spec));
850 filter->add_fltr.rule_cfg.proto_hdrs.count = ++layer;
853 case RTE_FLOW_ITEM_TYPE_ESP:
854 esp_spec = item->spec;
855 esp_mask = item->mask;
857 hdr = &filter->add_fltr.rule_cfg.proto_hdrs.proto_hdr[layer];
859 VIRTCHNL_SET_PROTO_HDR_TYPE(hdr, ESP);
861 if (esp_spec && esp_mask) {
862 if (esp_mask->hdr.spi == UINT32_MAX) {
863 input_set |= IAVF_INSET_ESP_SPI;
864 VIRTCHNL_ADD_PROTO_HDR_FIELD_BIT(hdr, ESP, SPI);
867 rte_memcpy(hdr->buffer, &esp_spec->hdr,
868 sizeof(esp_spec->hdr));
871 filter->add_fltr.rule_cfg.proto_hdrs.count = ++layer;
874 case RTE_FLOW_ITEM_TYPE_AH:
875 ah_spec = item->spec;
876 ah_mask = item->mask;
878 hdr = &filter->add_fltr.rule_cfg.proto_hdrs.proto_hdr[layer];
880 VIRTCHNL_SET_PROTO_HDR_TYPE(hdr, AH);
882 if (ah_spec && ah_mask) {
883 if (ah_mask->spi == UINT32_MAX) {
884 input_set |= IAVF_INSET_AH_SPI;
885 VIRTCHNL_ADD_PROTO_HDR_FIELD_BIT(hdr, AH, SPI);
888 rte_memcpy(hdr->buffer, ah_spec,
892 filter->add_fltr.rule_cfg.proto_hdrs.count = ++layer;
895 case RTE_FLOW_ITEM_TYPE_PFCP:
896 pfcp_spec = item->spec;
897 pfcp_mask = item->mask;
899 hdr = &filter->add_fltr.rule_cfg.proto_hdrs.proto_hdr[layer];
901 VIRTCHNL_SET_PROTO_HDR_TYPE(hdr, PFCP);
903 if (pfcp_spec && pfcp_mask) {
904 if (pfcp_mask->s_field == UINT8_MAX) {
905 input_set |= IAVF_INSET_PFCP_S_FIELD;
906 VIRTCHNL_ADD_PROTO_HDR_FIELD_BIT(hdr, PFCP, S_FIELD);
909 rte_memcpy(hdr->buffer, pfcp_spec,
913 filter->add_fltr.rule_cfg.proto_hdrs.count = ++layer;
916 case RTE_FLOW_ITEM_TYPE_ECPRI:
917 ecpri_spec = item->spec;
918 ecpri_mask = item->mask;
920 ecpri_common.u32 = rte_be_to_cpu_32(ecpri_spec->hdr.common.u32);
922 hdr = &filter->add_fltr.rule_cfg.proto_hdrs.proto_hdr[layer];
924 VIRTCHNL_SET_PROTO_HDR_TYPE(hdr, ECPRI);
926 if (ecpri_spec && ecpri_mask) {
927 if (ecpri_common.type == RTE_ECPRI_MSG_TYPE_IQ_DATA &&
928 ecpri_mask->hdr.type0.pc_id == UINT16_MAX) {
929 input_set |= IAVF_ECPRI_PC_RTC_ID;
930 VIRTCHNL_ADD_PROTO_HDR_FIELD_BIT(hdr, ECPRI,
934 rte_memcpy(hdr->buffer, ecpri_spec,
935 sizeof(*ecpri_spec));
938 filter->add_fltr.rule_cfg.proto_hdrs.count = ++layer;
941 case RTE_FLOW_ITEM_TYPE_VOID:
945 rte_flow_error_set(error, EINVAL,
946 RTE_FLOW_ERROR_TYPE_ITEM, item,
947 "Invalid pattern item.");
952 if (layer > VIRTCHNL_MAX_NUM_PROTO_HDRS) {
953 rte_flow_error_set(error, EINVAL,
954 RTE_FLOW_ERROR_TYPE_ITEM, item,
955 "Protocol header layers exceed the maximum value");
959 filter->input_set = input_set;
965 iavf_fdir_parse(struct iavf_adapter *ad,
966 struct iavf_pattern_match_item *array,
968 const struct rte_flow_item pattern[],
969 const struct rte_flow_action actions[],
971 struct rte_flow_error *error)
973 struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(ad);
974 struct iavf_fdir_conf *filter = &vf->fdir.conf;
975 struct iavf_pattern_match_item *item = NULL;
979 memset(filter, 0, sizeof(*filter));
981 item = iavf_search_pattern_match_item(pattern, array, array_len, error);
985 ret = iavf_fdir_parse_pattern(ad, pattern, error, filter);
989 input_set = filter->input_set;
990 if (!input_set || input_set & ~item->input_set_mask) {
991 rte_flow_error_set(error, EINVAL,
992 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, pattern,
993 "Invalid input set");
998 ret = iavf_fdir_parse_action(ad, actions, error, filter);
1010 static struct iavf_flow_parser iavf_fdir_parser = {
1011 .engine = &iavf_fdir_engine,
1012 .array = iavf_fdir_pattern,
1013 .array_len = RTE_DIM(iavf_fdir_pattern),
1014 .parse_pattern_action = iavf_fdir_parse,
1015 .stage = IAVF_FLOW_STAGE_DISTRIBUTOR,
1018 RTE_INIT(iavf_fdir_engine_register)
1020 iavf_register_flow_engine(&iavf_fdir_engine);