1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2017 Intel Corporation
13 #include <sys/queue.h>
15 #include <rte_string_fns.h>
16 #include <rte_memzone.h>
18 #include <rte_malloc.h>
19 #include <rte_ether.h>
20 #include <ethdev_driver.h>
29 #include "iavf_rxtx.h"
30 #include "rte_pmd_iavf.h"
32 /* Offset of mbuf dynamic field for protocol extraction's metadata */
33 int rte_pmd_ifd_dynfield_proto_xtr_metadata_offs = -1;
35 /* Mask of mbuf dynamic flags for protocol extraction's type */
36 uint64_t rte_pmd_ifd_dynflag_proto_xtr_vlan_mask;
37 uint64_t rte_pmd_ifd_dynflag_proto_xtr_ipv4_mask;
38 uint64_t rte_pmd_ifd_dynflag_proto_xtr_ipv6_mask;
39 uint64_t rte_pmd_ifd_dynflag_proto_xtr_ipv6_flow_mask;
40 uint64_t rte_pmd_ifd_dynflag_proto_xtr_tcp_mask;
41 uint64_t rte_pmd_ifd_dynflag_proto_xtr_ip_offset_mask;
44 iavf_proto_xtr_type_to_rxdid(uint8_t flex_type)
46 static uint8_t rxdid_map[] = {
47 [IAVF_PROTO_XTR_NONE] = IAVF_RXDID_COMMS_OVS_1,
48 [IAVF_PROTO_XTR_VLAN] = IAVF_RXDID_COMMS_AUX_VLAN,
49 [IAVF_PROTO_XTR_IPV4] = IAVF_RXDID_COMMS_AUX_IPV4,
50 [IAVF_PROTO_XTR_IPV6] = IAVF_RXDID_COMMS_AUX_IPV6,
51 [IAVF_PROTO_XTR_IPV6_FLOW] = IAVF_RXDID_COMMS_AUX_IPV6_FLOW,
52 [IAVF_PROTO_XTR_TCP] = IAVF_RXDID_COMMS_AUX_TCP,
53 [IAVF_PROTO_XTR_IP_OFFSET] = IAVF_RXDID_COMMS_AUX_IP_OFFSET,
56 return flex_type < RTE_DIM(rxdid_map) ?
57 rxdid_map[flex_type] : IAVF_RXDID_COMMS_OVS_1;
61 iavf_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc)
63 struct iavf_rx_queue *rxq = rx_queue;
64 volatile union iavf_rx_desc *rxdp;
68 rxdp = &rxq->rx_ring[desc];
69 /* watch for changes in status bit */
70 pmc->addr = &rxdp->wb.qword1.status_error_len;
73 * we expect the DD bit to be set to 1 if this descriptor was already
76 pmc->val = rte_cpu_to_le_64(1 << IAVF_RX_DESC_STATUS_DD_SHIFT);
77 pmc->mask = rte_cpu_to_le_64(1 << IAVF_RX_DESC_STATUS_DD_SHIFT);
79 /* registers are 64-bit */
80 pmc->size = sizeof(uint64_t);
86 check_rx_thresh(uint16_t nb_desc, uint16_t thresh)
88 /* The following constraints must be satisfied:
89 * thresh < rxq->nb_rx_desc
91 if (thresh >= nb_desc) {
92 PMD_INIT_LOG(ERR, "rx_free_thresh (%u) must be less than %u",
100 check_tx_thresh(uint16_t nb_desc, uint16_t tx_rs_thresh,
101 uint16_t tx_free_thresh)
103 /* TX descriptors will have their RS bit set after tx_rs_thresh
104 * descriptors have been used. The TX descriptor ring will be cleaned
105 * after tx_free_thresh descriptors are used or if the number of
106 * descriptors required to transmit a packet is greater than the
107 * number of free TX descriptors.
109 * The following constraints must be satisfied:
110 * - tx_rs_thresh must be less than the size of the ring minus 2.
111 * - tx_free_thresh must be less than the size of the ring minus 3.
112 * - tx_rs_thresh must be less than or equal to tx_free_thresh.
113 * - tx_rs_thresh must be a divisor of the ring size.
115 * One descriptor in the TX ring is used as a sentinel to avoid a H/W
116 * race condition, hence the maximum threshold constraints. When set
117 * to zero use default values.
119 if (tx_rs_thresh >= (nb_desc - 2)) {
120 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be less than the "
121 "number of TX descriptors (%u) minus 2",
122 tx_rs_thresh, nb_desc);
125 if (tx_free_thresh >= (nb_desc - 3)) {
126 PMD_INIT_LOG(ERR, "tx_free_thresh (%u) must be less than the "
127 "number of TX descriptors (%u) minus 3.",
128 tx_free_thresh, nb_desc);
131 if (tx_rs_thresh > tx_free_thresh) {
132 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be less than or "
133 "equal to tx_free_thresh (%u).",
134 tx_rs_thresh, tx_free_thresh);
137 if ((nb_desc % tx_rs_thresh) != 0) {
138 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be a divisor of the "
139 "number of TX descriptors (%u).",
140 tx_rs_thresh, nb_desc);
148 check_rx_vec_allow(struct iavf_rx_queue *rxq)
150 if (rxq->rx_free_thresh >= IAVF_VPMD_RX_MAX_BURST &&
151 rxq->nb_rx_desc % rxq->rx_free_thresh == 0) {
152 PMD_INIT_LOG(DEBUG, "Vector Rx can be enabled on this rxq.");
156 PMD_INIT_LOG(DEBUG, "Vector Rx cannot be enabled on this rxq.");
161 check_tx_vec_allow(struct iavf_tx_queue *txq)
163 if (!(txq->offloads & IAVF_TX_NO_VECTOR_FLAGS) &&
164 txq->rs_thresh >= IAVF_VPMD_TX_MAX_BURST &&
165 txq->rs_thresh <= IAVF_VPMD_TX_MAX_FREE_BUF) {
166 PMD_INIT_LOG(DEBUG, "Vector tx can be enabled on this txq.");
169 PMD_INIT_LOG(DEBUG, "Vector Tx cannot be enabled on this txq.");
174 check_rx_bulk_allow(struct iavf_rx_queue *rxq)
178 if (!(rxq->rx_free_thresh >= IAVF_RX_MAX_BURST)) {
179 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
180 "rxq->rx_free_thresh=%d, "
181 "IAVF_RX_MAX_BURST=%d",
182 rxq->rx_free_thresh, IAVF_RX_MAX_BURST);
184 } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
185 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
186 "rxq->nb_rx_desc=%d, "
187 "rxq->rx_free_thresh=%d",
188 rxq->nb_rx_desc, rxq->rx_free_thresh);
195 reset_rx_queue(struct iavf_rx_queue *rxq)
203 len = rxq->nb_rx_desc + IAVF_RX_MAX_BURST;
205 for (i = 0; i < len * sizeof(union iavf_rx_desc); i++)
206 ((volatile char *)rxq->rx_ring)[i] = 0;
208 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
210 for (i = 0; i < IAVF_RX_MAX_BURST; i++)
211 rxq->sw_ring[rxq->nb_rx_desc + i] = &rxq->fake_mbuf;
214 rxq->rx_nb_avail = 0;
215 rxq->rx_next_avail = 0;
216 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
220 rxq->pkt_first_seg = NULL;
221 rxq->pkt_last_seg = NULL;
223 rxq->rxrearm_start = 0;
227 reset_tx_queue(struct iavf_tx_queue *txq)
229 struct iavf_tx_entry *txe;
234 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
239 size = sizeof(struct iavf_tx_desc) * txq->nb_tx_desc;
240 for (i = 0; i < size; i++)
241 ((volatile char *)txq->tx_ring)[i] = 0;
243 prev = (uint16_t)(txq->nb_tx_desc - 1);
244 for (i = 0; i < txq->nb_tx_desc; i++) {
245 txq->tx_ring[i].cmd_type_offset_bsz =
246 rte_cpu_to_le_64(IAVF_TX_DESC_DTYPE_DESC_DONE);
249 txe[prev].next_id = i;
256 txq->last_desc_cleaned = txq->nb_tx_desc - 1;
257 txq->nb_free = txq->nb_tx_desc - 1;
259 txq->next_dd = txq->rs_thresh - 1;
260 txq->next_rs = txq->rs_thresh - 1;
264 alloc_rxq_mbufs(struct iavf_rx_queue *rxq)
266 volatile union iavf_rx_desc *rxd;
267 struct rte_mbuf *mbuf = NULL;
271 for (i = 0; i < rxq->nb_rx_desc; i++) {
272 mbuf = rte_mbuf_raw_alloc(rxq->mp);
273 if (unlikely(!mbuf)) {
274 PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
278 rte_mbuf_refcnt_set(mbuf, 1);
280 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
282 mbuf->port = rxq->port_id;
285 rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
287 rxd = &rxq->rx_ring[i];
288 rxd->read.pkt_addr = dma_addr;
289 rxd->read.hdr_addr = 0;
290 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
295 rxq->sw_ring[i] = mbuf;
302 release_rxq_mbufs(struct iavf_rx_queue *rxq)
309 for (i = 0; i < rxq->nb_rx_desc; i++) {
310 if (rxq->sw_ring[i]) {
311 rte_pktmbuf_free_seg(rxq->sw_ring[i]);
312 rxq->sw_ring[i] = NULL;
317 if (rxq->rx_nb_avail == 0)
319 for (i = 0; i < rxq->rx_nb_avail; i++) {
320 struct rte_mbuf *mbuf;
322 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
323 rte_pktmbuf_free_seg(mbuf);
325 rxq->rx_nb_avail = 0;
329 release_txq_mbufs(struct iavf_tx_queue *txq)
333 if (!txq || !txq->sw_ring) {
334 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
338 for (i = 0; i < txq->nb_tx_desc; i++) {
339 if (txq->sw_ring[i].mbuf) {
340 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
341 txq->sw_ring[i].mbuf = NULL;
346 static const struct iavf_rxq_ops def_rxq_ops = {
347 .release_mbufs = release_rxq_mbufs,
350 static const struct iavf_txq_ops def_txq_ops = {
351 .release_mbufs = release_txq_mbufs,
355 iavf_rxd_to_pkt_fields_by_comms_ovs(__rte_unused struct iavf_rx_queue *rxq,
357 volatile union iavf_rx_flex_desc *rxdp)
359 volatile struct iavf_32b_rx_flex_desc_comms_ovs *desc =
360 (volatile struct iavf_32b_rx_flex_desc_comms_ovs *)rxdp;
361 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
365 if (desc->flow_id != 0xFFFFFFFF) {
366 mb->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
367 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
370 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
371 stat_err = rte_le_to_cpu_16(desc->status_error0);
372 if (likely(stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
373 mb->ol_flags |= PKT_RX_RSS_HASH;
374 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
380 iavf_rxd_to_pkt_fields_by_comms_aux_v1(struct iavf_rx_queue *rxq,
382 volatile union iavf_rx_flex_desc *rxdp)
384 volatile struct iavf_32b_rx_flex_desc_comms *desc =
385 (volatile struct iavf_32b_rx_flex_desc_comms *)rxdp;
388 stat_err = rte_le_to_cpu_16(desc->status_error0);
389 if (likely(stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
390 mb->ol_flags |= PKT_RX_RSS_HASH;
391 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
394 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
395 if (desc->flow_id != 0xFFFFFFFF) {
396 mb->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
397 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
400 if (rxq->xtr_ol_flag) {
401 uint32_t metadata = 0;
403 stat_err = rte_le_to_cpu_16(desc->status_error1);
405 if (stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS1_XTRMD4_VALID_S))
406 metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux0);
408 if (stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS1_XTRMD5_VALID_S))
410 rte_le_to_cpu_16(desc->flex_ts.flex.aux1) << 16;
413 mb->ol_flags |= rxq->xtr_ol_flag;
415 *RTE_PMD_IFD_DYNF_PROTO_XTR_METADATA(mb) = metadata;
422 iavf_rxd_to_pkt_fields_by_comms_aux_v2(struct iavf_rx_queue *rxq,
424 volatile union iavf_rx_flex_desc *rxdp)
426 volatile struct iavf_32b_rx_flex_desc_comms *desc =
427 (volatile struct iavf_32b_rx_flex_desc_comms *)rxdp;
430 stat_err = rte_le_to_cpu_16(desc->status_error0);
431 if (likely(stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
432 mb->ol_flags |= PKT_RX_RSS_HASH;
433 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
436 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
437 if (desc->flow_id != 0xFFFFFFFF) {
438 mb->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
439 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
442 if (rxq->xtr_ol_flag) {
443 uint32_t metadata = 0;
445 if (desc->flex_ts.flex.aux0 != 0xFFFF)
446 metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux0);
447 else if (desc->flex_ts.flex.aux1 != 0xFFFF)
448 metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux1);
451 mb->ol_flags |= rxq->xtr_ol_flag;
453 *RTE_PMD_IFD_DYNF_PROTO_XTR_METADATA(mb) = metadata;
460 iavf_select_rxd_to_pkt_fields_handler(struct iavf_rx_queue *rxq, uint32_t rxdid)
463 case IAVF_RXDID_COMMS_AUX_VLAN:
464 rxq->xtr_ol_flag = rte_pmd_ifd_dynflag_proto_xtr_vlan_mask;
465 rxq->rxd_to_pkt_fields =
466 iavf_rxd_to_pkt_fields_by_comms_aux_v1;
468 case IAVF_RXDID_COMMS_AUX_IPV4:
469 rxq->xtr_ol_flag = rte_pmd_ifd_dynflag_proto_xtr_ipv4_mask;
470 rxq->rxd_to_pkt_fields =
471 iavf_rxd_to_pkt_fields_by_comms_aux_v1;
473 case IAVF_RXDID_COMMS_AUX_IPV6:
474 rxq->xtr_ol_flag = rte_pmd_ifd_dynflag_proto_xtr_ipv6_mask;
475 rxq->rxd_to_pkt_fields =
476 iavf_rxd_to_pkt_fields_by_comms_aux_v1;
478 case IAVF_RXDID_COMMS_AUX_IPV6_FLOW:
480 rte_pmd_ifd_dynflag_proto_xtr_ipv6_flow_mask;
481 rxq->rxd_to_pkt_fields =
482 iavf_rxd_to_pkt_fields_by_comms_aux_v1;
484 case IAVF_RXDID_COMMS_AUX_TCP:
485 rxq->xtr_ol_flag = rte_pmd_ifd_dynflag_proto_xtr_tcp_mask;
486 rxq->rxd_to_pkt_fields =
487 iavf_rxd_to_pkt_fields_by_comms_aux_v1;
489 case IAVF_RXDID_COMMS_AUX_IP_OFFSET:
491 rte_pmd_ifd_dynflag_proto_xtr_ip_offset_mask;
492 rxq->rxd_to_pkt_fields =
493 iavf_rxd_to_pkt_fields_by_comms_aux_v2;
495 case IAVF_RXDID_COMMS_OVS_1:
496 rxq->rxd_to_pkt_fields = iavf_rxd_to_pkt_fields_by_comms_ovs;
499 /* update this according to the RXDID for FLEX_DESC_NONE */
500 rxq->rxd_to_pkt_fields = iavf_rxd_to_pkt_fields_by_comms_ovs;
504 if (!rte_pmd_ifd_dynf_proto_xtr_metadata_avail())
505 rxq->xtr_ol_flag = 0;
509 iavf_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
510 uint16_t nb_desc, unsigned int socket_id,
511 const struct rte_eth_rxconf *rx_conf,
512 struct rte_mempool *mp)
514 struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
515 struct iavf_adapter *ad =
516 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
517 struct iavf_info *vf =
518 IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
519 struct iavf_vsi *vsi = &vf->vsi;
520 struct iavf_rx_queue *rxq;
521 const struct rte_memzone *mz;
525 uint16_t rx_free_thresh;
528 PMD_INIT_FUNC_TRACE();
530 offloads = rx_conf->offloads | dev->data->dev_conf.rxmode.offloads;
532 if (nb_desc % IAVF_ALIGN_RING_DESC != 0 ||
533 nb_desc > IAVF_MAX_RING_DESC ||
534 nb_desc < IAVF_MIN_RING_DESC) {
535 PMD_INIT_LOG(ERR, "Number (%u) of receive descriptors is "
540 /* Check free threshold */
541 rx_free_thresh = (rx_conf->rx_free_thresh == 0) ?
542 IAVF_DEFAULT_RX_FREE_THRESH :
543 rx_conf->rx_free_thresh;
544 if (check_rx_thresh(nb_desc, rx_free_thresh) != 0)
547 /* Free memory if needed */
548 if (dev->data->rx_queues[queue_idx]) {
549 iavf_dev_rx_queue_release(dev->data->rx_queues[queue_idx]);
550 dev->data->rx_queues[queue_idx] = NULL;
553 /* Allocate the rx queue data structure */
554 rxq = rte_zmalloc_socket("iavf rxq",
555 sizeof(struct iavf_rx_queue),
559 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
560 "rx queue data structure");
564 if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC) {
565 proto_xtr = vf->proto_xtr ? vf->proto_xtr[queue_idx] :
567 rxq->rxdid = iavf_proto_xtr_type_to_rxdid(proto_xtr);
568 rxq->proto_xtr = proto_xtr;
570 rxq->rxdid = IAVF_RXDID_LEGACY_1;
571 rxq->proto_xtr = IAVF_PROTO_XTR_NONE;
574 if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_VLAN_V2) {
575 struct virtchnl_vlan_supported_caps *stripping_support =
576 &vf->vlan_v2_caps.offloads.stripping_support;
577 uint32_t stripping_cap;
579 if (stripping_support->outer)
580 stripping_cap = stripping_support->outer;
582 stripping_cap = stripping_support->inner;
584 if (stripping_cap & VIRTCHNL_VLAN_TAG_LOCATION_L2TAG1)
585 rxq->rx_flags = IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG1;
586 else if (stripping_cap & VIRTCHNL_VLAN_TAG_LOCATION_L2TAG2_2)
587 rxq->rx_flags = IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG2_2;
589 rxq->rx_flags = IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG1;
592 iavf_select_rxd_to_pkt_fields_handler(rxq, rxq->rxdid);
595 rxq->nb_rx_desc = nb_desc;
596 rxq->rx_free_thresh = rx_free_thresh;
597 rxq->queue_id = queue_idx;
598 rxq->port_id = dev->data->port_id;
599 rxq->rx_deferred_start = rx_conf->rx_deferred_start;
602 rxq->offloads = offloads;
604 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
605 rxq->crc_len = RTE_ETHER_CRC_LEN;
609 len = rte_pktmbuf_data_room_size(rxq->mp) - RTE_PKTMBUF_HEADROOM;
610 rxq->rx_buf_len = RTE_ALIGN(len, (1 << IAVF_RXQ_CTX_DBUFF_SHIFT));
612 /* Allocate the software ring. */
613 len = nb_desc + IAVF_RX_MAX_BURST;
615 rte_zmalloc_socket("iavf rx sw ring",
616 sizeof(struct rte_mbuf *) * len,
620 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW ring");
625 /* Allocate the maximun number of RX ring hardware descriptor with
626 * a liitle more to support bulk allocate.
628 len = IAVF_MAX_RING_DESC + IAVF_RX_MAX_BURST;
629 ring_size = RTE_ALIGN(len * sizeof(union iavf_rx_desc),
631 mz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
632 ring_size, IAVF_RING_BASE_ALIGN,
635 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for RX");
636 rte_free(rxq->sw_ring);
640 /* Zero all the descriptors in the ring. */
641 memset(mz->addr, 0, ring_size);
642 rxq->rx_ring_phys_addr = mz->iova;
643 rxq->rx_ring = (union iavf_rx_desc *)mz->addr;
648 dev->data->rx_queues[queue_idx] = rxq;
649 rxq->qrx_tail = hw->hw_addr + IAVF_QRX_TAIL1(rxq->queue_id);
650 rxq->ops = &def_rxq_ops;
652 if (check_rx_bulk_allow(rxq) == true) {
653 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
654 "satisfied. Rx Burst Bulk Alloc function will be "
655 "used on port=%d, queue=%d.",
656 rxq->port_id, rxq->queue_id);
658 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
659 "not satisfied, Scattered Rx is requested "
660 "on port=%d, queue=%d.",
661 rxq->port_id, rxq->queue_id);
662 ad->rx_bulk_alloc_allowed = false;
665 if (check_rx_vec_allow(rxq) == false)
666 ad->rx_vec_allowed = false;
672 iavf_dev_tx_queue_setup(struct rte_eth_dev *dev,
675 unsigned int socket_id,
676 const struct rte_eth_txconf *tx_conf)
678 struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
679 struct iavf_info *vf =
680 IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
681 struct iavf_tx_queue *txq;
682 const struct rte_memzone *mz;
684 uint16_t tx_rs_thresh, tx_free_thresh;
687 PMD_INIT_FUNC_TRACE();
689 offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
691 if (nb_desc % IAVF_ALIGN_RING_DESC != 0 ||
692 nb_desc > IAVF_MAX_RING_DESC ||
693 nb_desc < IAVF_MIN_RING_DESC) {
694 PMD_INIT_LOG(ERR, "Number (%u) of transmit descriptors is "
699 tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
700 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
701 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
702 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
703 check_tx_thresh(nb_desc, tx_rs_thresh, tx_rs_thresh);
705 /* Free memory if needed. */
706 if (dev->data->tx_queues[queue_idx]) {
707 iavf_dev_tx_queue_release(dev->data->tx_queues[queue_idx]);
708 dev->data->tx_queues[queue_idx] = NULL;
711 /* Allocate the TX queue data structure. */
712 txq = rte_zmalloc_socket("iavf txq",
713 sizeof(struct iavf_tx_queue),
717 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
718 "tx queue structure");
722 if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_VLAN_V2) {
723 struct virtchnl_vlan_supported_caps *insertion_support =
724 &vf->vlan_v2_caps.offloads.insertion_support;
725 uint32_t insertion_cap;
727 if (insertion_support->outer)
728 insertion_cap = insertion_support->outer;
730 insertion_cap = insertion_support->inner;
732 if (insertion_cap & VIRTCHNL_VLAN_TAG_LOCATION_L2TAG1)
733 txq->vlan_flag = IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG1;
734 else if (insertion_cap & VIRTCHNL_VLAN_TAG_LOCATION_L2TAG2)
735 txq->vlan_flag = IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG2;
737 txq->vlan_flag = IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG1;
740 txq->nb_tx_desc = nb_desc;
741 txq->rs_thresh = tx_rs_thresh;
742 txq->free_thresh = tx_free_thresh;
743 txq->queue_id = queue_idx;
744 txq->port_id = dev->data->port_id;
745 txq->offloads = offloads;
746 txq->tx_deferred_start = tx_conf->tx_deferred_start;
748 /* Allocate software ring */
750 rte_zmalloc_socket("iavf tx sw ring",
751 sizeof(struct iavf_tx_entry) * nb_desc,
755 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW TX ring");
760 /* Allocate TX hardware ring descriptors. */
761 ring_size = sizeof(struct iavf_tx_desc) * IAVF_MAX_RING_DESC;
762 ring_size = RTE_ALIGN(ring_size, IAVF_DMA_MEM_ALIGN);
763 mz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
764 ring_size, IAVF_RING_BASE_ALIGN,
767 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for TX");
768 rte_free(txq->sw_ring);
772 txq->tx_ring_phys_addr = mz->iova;
773 txq->tx_ring = (struct iavf_tx_desc *)mz->addr;
778 dev->data->tx_queues[queue_idx] = txq;
779 txq->qtx_tail = hw->hw_addr + IAVF_QTX_TAIL1(queue_idx);
780 txq->ops = &def_txq_ops;
782 if (check_tx_vec_allow(txq) == false) {
783 struct iavf_adapter *ad =
784 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
785 ad->tx_vec_allowed = false;
792 iavf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
794 struct iavf_adapter *adapter =
795 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
796 struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
797 struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
798 struct iavf_rx_queue *rxq;
801 PMD_DRV_FUNC_TRACE();
803 if (rx_queue_id >= dev->data->nb_rx_queues)
806 rxq = dev->data->rx_queues[rx_queue_id];
808 err = alloc_rxq_mbufs(rxq);
810 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
816 /* Init the RX tail register. */
817 IAVF_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
818 IAVF_WRITE_FLUSH(hw);
820 /* Ready to switch the queue on */
822 err = iavf_switch_queue(adapter, rx_queue_id, true, true);
824 err = iavf_switch_queue_lv(adapter, rx_queue_id, true, true);
827 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
830 dev->data->rx_queue_state[rx_queue_id] =
831 RTE_ETH_QUEUE_STATE_STARTED;
837 iavf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
839 struct iavf_adapter *adapter =
840 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
841 struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
842 struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
843 struct iavf_tx_queue *txq;
846 PMD_DRV_FUNC_TRACE();
848 if (tx_queue_id >= dev->data->nb_tx_queues)
851 txq = dev->data->tx_queues[tx_queue_id];
853 /* Init the RX tail register. */
854 IAVF_PCI_REG_WRITE(txq->qtx_tail, 0);
855 IAVF_WRITE_FLUSH(hw);
857 /* Ready to switch the queue on */
859 err = iavf_switch_queue(adapter, tx_queue_id, false, true);
861 err = iavf_switch_queue_lv(adapter, tx_queue_id, false, true);
864 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
867 dev->data->tx_queue_state[tx_queue_id] =
868 RTE_ETH_QUEUE_STATE_STARTED;
874 iavf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
876 struct iavf_adapter *adapter =
877 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
878 struct iavf_rx_queue *rxq;
881 PMD_DRV_FUNC_TRACE();
883 if (rx_queue_id >= dev->data->nb_rx_queues)
886 err = iavf_switch_queue(adapter, rx_queue_id, true, false);
888 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
893 rxq = dev->data->rx_queues[rx_queue_id];
894 rxq->ops->release_mbufs(rxq);
896 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
902 iavf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
904 struct iavf_adapter *adapter =
905 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
906 struct iavf_tx_queue *txq;
909 PMD_DRV_FUNC_TRACE();
911 if (tx_queue_id >= dev->data->nb_tx_queues)
914 err = iavf_switch_queue(adapter, tx_queue_id, false, false);
916 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u off",
921 txq = dev->data->tx_queues[tx_queue_id];
922 txq->ops->release_mbufs(txq);
924 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
930 iavf_dev_rx_queue_release(void *rxq)
932 struct iavf_rx_queue *q = (struct iavf_rx_queue *)rxq;
937 q->ops->release_mbufs(q);
938 rte_free(q->sw_ring);
939 rte_memzone_free(q->mz);
944 iavf_dev_tx_queue_release(void *txq)
946 struct iavf_tx_queue *q = (struct iavf_tx_queue *)txq;
951 q->ops->release_mbufs(q);
952 rte_free(q->sw_ring);
953 rte_memzone_free(q->mz);
958 iavf_stop_queues(struct rte_eth_dev *dev)
960 struct iavf_adapter *adapter =
961 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
962 struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
963 struct iavf_rx_queue *rxq;
964 struct iavf_tx_queue *txq;
967 /* Stop All queues */
968 if (!vf->lv_enabled) {
969 ret = iavf_disable_queues(adapter);
971 PMD_DRV_LOG(WARNING, "Fail to stop queues");
973 ret = iavf_disable_queues_lv(adapter);
975 PMD_DRV_LOG(WARNING, "Fail to stop queues for large VF");
979 PMD_DRV_LOG(WARNING, "Fail to stop queues");
981 for (i = 0; i < dev->data->nb_tx_queues; i++) {
982 txq = dev->data->tx_queues[i];
985 txq->ops->release_mbufs(txq);
987 dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED;
989 for (i = 0; i < dev->data->nb_rx_queues; i++) {
990 rxq = dev->data->rx_queues[i];
993 rxq->ops->release_mbufs(rxq);
995 dev->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED;
999 #define IAVF_RX_FLEX_ERR0_BITS \
1000 ((1 << IAVF_RX_FLEX_DESC_STATUS0_HBO_S) | \
1001 (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_IPE_S) | \
1002 (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_L4E_S) | \
1003 (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S) | \
1004 (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S) | \
1005 (1 << IAVF_RX_FLEX_DESC_STATUS0_RXE_S))
1008 iavf_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union iavf_rx_desc *rxdp)
1010 if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1011 (1 << IAVF_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
1012 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1014 rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
1021 iavf_flex_rxd_to_vlan_tci(struct rte_mbuf *mb,
1022 volatile union iavf_rx_flex_desc *rxdp,
1025 uint16_t vlan_tci = 0;
1027 if (rx_flags & IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG1 &&
1028 rte_le_to_cpu_64(rxdp->wb.status_error0) &
1029 (1 << IAVF_RX_FLEX_DESC_STATUS0_L2TAG1P_S))
1030 vlan_tci = rte_le_to_cpu_16(rxdp->wb.l2tag1);
1032 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
1033 if (rx_flags & IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG2_2 &&
1034 rte_le_to_cpu_16(rxdp->wb.status_error1) &
1035 (1 << IAVF_RX_FLEX_DESC_STATUS1_L2TAG2P_S))
1036 vlan_tci = rte_le_to_cpu_16(rxdp->wb.l2tag2_2nd);
1040 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1041 mb->vlan_tci = vlan_tci;
1045 /* Translate the rx descriptor status and error fields to pkt flags */
1046 static inline uint64_t
1047 iavf_rxd_to_pkt_flags(uint64_t qword)
1050 uint64_t error_bits = (qword >> IAVF_RXD_QW1_ERROR_SHIFT);
1052 #define IAVF_RX_ERR_BITS 0x3f
1054 /* Check if RSS_HASH */
1055 flags = (((qword >> IAVF_RX_DESC_STATUS_FLTSTAT_SHIFT) &
1056 IAVF_RX_DESC_FLTSTAT_RSS_HASH) ==
1057 IAVF_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;
1059 /* Check if FDIR Match */
1060 flags |= (qword & (1 << IAVF_RX_DESC_STATUS_FLM_SHIFT) ?
1063 if (likely((error_bits & IAVF_RX_ERR_BITS) == 0)) {
1064 flags |= (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD);
1068 if (unlikely(error_bits & (1 << IAVF_RX_DESC_ERROR_IPE_SHIFT)))
1069 flags |= PKT_RX_IP_CKSUM_BAD;
1071 flags |= PKT_RX_IP_CKSUM_GOOD;
1073 if (unlikely(error_bits & (1 << IAVF_RX_DESC_ERROR_L4E_SHIFT)))
1074 flags |= PKT_RX_L4_CKSUM_BAD;
1076 flags |= PKT_RX_L4_CKSUM_GOOD;
1078 /* TODO: Oversize error bit is not processed here */
1083 static inline uint64_t
1084 iavf_rxd_build_fdir(volatile union iavf_rx_desc *rxdp, struct rte_mbuf *mb)
1087 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
1090 flexbh = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
1091 IAVF_RX_DESC_EXT_STATUS_FLEXBH_SHIFT) &
1092 IAVF_RX_DESC_EXT_STATUS_FLEXBH_MASK;
1094 if (flexbh == IAVF_RX_DESC_EXT_STATUS_FLEXBH_FD_ID) {
1096 rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.fd_id);
1097 flags |= PKT_RX_FDIR_ID;
1101 rte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.fd_id);
1102 flags |= PKT_RX_FDIR_ID;
1107 #define IAVF_RX_FLEX_ERR0_BITS \
1108 ((1 << IAVF_RX_FLEX_DESC_STATUS0_HBO_S) | \
1109 (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_IPE_S) | \
1110 (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_L4E_S) | \
1111 (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S) | \
1112 (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S) | \
1113 (1 << IAVF_RX_FLEX_DESC_STATUS0_RXE_S))
1115 /* Rx L3/L4 checksum */
1116 static inline uint64_t
1117 iavf_flex_rxd_error_to_pkt_flags(uint16_t stat_err0)
1121 /* check if HW has decoded the packet and checksum */
1122 if (unlikely(!(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_L3L4P_S))))
1125 if (likely(!(stat_err0 & IAVF_RX_FLEX_ERR0_BITS))) {
1126 flags |= (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD);
1130 if (unlikely(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_IPE_S)))
1131 flags |= PKT_RX_IP_CKSUM_BAD;
1133 flags |= PKT_RX_IP_CKSUM_GOOD;
1135 if (unlikely(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_L4E_S)))
1136 flags |= PKT_RX_L4_CKSUM_BAD;
1138 flags |= PKT_RX_L4_CKSUM_GOOD;
1140 if (unlikely(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S)))
1141 flags |= PKT_RX_OUTER_IP_CKSUM_BAD;
1146 /* If the number of free RX descriptors is greater than the RX free
1147 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1148 * register. Update the RDT with the value of the last processed RX
1149 * descriptor minus 1, to guarantee that the RDT register is never
1150 * equal to the RDH register, which creates a "full" ring situation
1151 * from the hardware point of view.
1154 iavf_update_rx_tail(struct iavf_rx_queue *rxq, uint16_t nb_hold, uint16_t rx_id)
1156 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1158 if (nb_hold > rxq->rx_free_thresh) {
1160 "port_id=%u queue_id=%u rx_tail=%u nb_hold=%u",
1161 rxq->port_id, rxq->queue_id, rx_id, nb_hold);
1162 rx_id = (uint16_t)((rx_id == 0) ?
1163 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1164 IAVF_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
1167 rxq->nb_rx_hold = nb_hold;
1170 /* implement recv_pkts */
1172 iavf_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1174 volatile union iavf_rx_desc *rx_ring;
1175 volatile union iavf_rx_desc *rxdp;
1176 struct iavf_rx_queue *rxq;
1177 union iavf_rx_desc rxd;
1178 struct rte_mbuf *rxe;
1179 struct rte_eth_dev *dev;
1180 struct rte_mbuf *rxm;
1181 struct rte_mbuf *nmb;
1185 uint16_t rx_packet_len;
1186 uint16_t rx_id, nb_hold;
1189 const uint32_t *ptype_tbl;
1194 rx_id = rxq->rx_tail;
1195 rx_ring = rxq->rx_ring;
1196 ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1198 while (nb_rx < nb_pkts) {
1199 rxdp = &rx_ring[rx_id];
1200 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1201 rx_status = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
1202 IAVF_RXD_QW1_STATUS_SHIFT;
1204 /* Check the DD bit first */
1205 if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)))
1207 IAVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
1209 nmb = rte_mbuf_raw_alloc(rxq->mp);
1210 if (unlikely(!nmb)) {
1211 dev = &rte_eth_devices[rxq->port_id];
1212 dev->data->rx_mbuf_alloc_failed++;
1213 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1214 "queue_id=%u", rxq->port_id, rxq->queue_id);
1220 rxe = rxq->sw_ring[rx_id];
1221 rxq->sw_ring[rx_id] = nmb;
1223 if (unlikely(rx_id == rxq->nb_rx_desc))
1226 /* Prefetch next mbuf */
1227 rte_prefetch0(rxq->sw_ring[rx_id]);
1229 /* When next RX descriptor is on a cache line boundary,
1230 * prefetch the next 4 RX descriptors and next 8 pointers
1233 if ((rx_id & 0x3) == 0) {
1234 rte_prefetch0(&rx_ring[rx_id]);
1235 rte_prefetch0(rxq->sw_ring[rx_id]);
1239 rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1240 rxdp->read.hdr_addr = 0;
1241 rxdp->read.pkt_addr = dma_addr;
1243 rx_packet_len = ((qword1 & IAVF_RXD_QW1_LENGTH_PBUF_MASK) >>
1244 IAVF_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
1246 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1247 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
1250 rxm->pkt_len = rx_packet_len;
1251 rxm->data_len = rx_packet_len;
1252 rxm->port = rxq->port_id;
1254 iavf_rxd_to_vlan_tci(rxm, &rxd);
1255 pkt_flags = iavf_rxd_to_pkt_flags(qword1);
1257 ptype_tbl[(uint8_t)((qword1 &
1258 IAVF_RXD_QW1_PTYPE_MASK) >> IAVF_RXD_QW1_PTYPE_SHIFT)];
1260 if (pkt_flags & PKT_RX_RSS_HASH)
1262 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1264 if (pkt_flags & PKT_RX_FDIR)
1265 pkt_flags |= iavf_rxd_build_fdir(&rxd, rxm);
1267 rxm->ol_flags |= pkt_flags;
1269 rx_pkts[nb_rx++] = rxm;
1271 rxq->rx_tail = rx_id;
1273 iavf_update_rx_tail(rxq, nb_hold, rx_id);
1278 /* implement recv_pkts for flexible Rx descriptor */
1280 iavf_recv_pkts_flex_rxd(void *rx_queue,
1281 struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1283 volatile union iavf_rx_desc *rx_ring;
1284 volatile union iavf_rx_flex_desc *rxdp;
1285 struct iavf_rx_queue *rxq;
1286 union iavf_rx_flex_desc rxd;
1287 struct rte_mbuf *rxe;
1288 struct rte_eth_dev *dev;
1289 struct rte_mbuf *rxm;
1290 struct rte_mbuf *nmb;
1292 uint16_t rx_stat_err0;
1293 uint16_t rx_packet_len;
1294 uint16_t rx_id, nb_hold;
1297 const uint32_t *ptype_tbl;
1302 rx_id = rxq->rx_tail;
1303 rx_ring = rxq->rx_ring;
1304 ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1306 while (nb_rx < nb_pkts) {
1307 rxdp = (volatile union iavf_rx_flex_desc *)&rx_ring[rx_id];
1308 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1310 /* Check the DD bit first */
1311 if (!(rx_stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S)))
1313 IAVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
1315 nmb = rte_mbuf_raw_alloc(rxq->mp);
1316 if (unlikely(!nmb)) {
1317 dev = &rte_eth_devices[rxq->port_id];
1318 dev->data->rx_mbuf_alloc_failed++;
1319 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1320 "queue_id=%u", rxq->port_id, rxq->queue_id);
1326 rxe = rxq->sw_ring[rx_id];
1327 rxq->sw_ring[rx_id] = nmb;
1329 if (unlikely(rx_id == rxq->nb_rx_desc))
1332 /* Prefetch next mbuf */
1333 rte_prefetch0(rxq->sw_ring[rx_id]);
1335 /* When next RX descriptor is on a cache line boundary,
1336 * prefetch the next 4 RX descriptors and next 8 pointers
1339 if ((rx_id & 0x3) == 0) {
1340 rte_prefetch0(&rx_ring[rx_id]);
1341 rte_prefetch0(rxq->sw_ring[rx_id]);
1345 rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1346 rxdp->read.hdr_addr = 0;
1347 rxdp->read.pkt_addr = dma_addr;
1349 rx_packet_len = (rte_le_to_cpu_16(rxd.wb.pkt_len) &
1350 IAVF_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
1352 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1353 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
1356 rxm->pkt_len = rx_packet_len;
1357 rxm->data_len = rx_packet_len;
1358 rxm->port = rxq->port_id;
1360 rxm->packet_type = ptype_tbl[IAVF_RX_FLEX_DESC_PTYPE_M &
1361 rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
1362 iavf_flex_rxd_to_vlan_tci(rxm, &rxd, rxq->rx_flags);
1363 rxq->rxd_to_pkt_fields(rxq, rxm, &rxd);
1364 pkt_flags = iavf_flex_rxd_error_to_pkt_flags(rx_stat_err0);
1365 rxm->ol_flags |= pkt_flags;
1367 rx_pkts[nb_rx++] = rxm;
1369 rxq->rx_tail = rx_id;
1371 iavf_update_rx_tail(rxq, nb_hold, rx_id);
1376 /* implement recv_scattered_pkts for flexible Rx descriptor */
1378 iavf_recv_scattered_pkts_flex_rxd(void *rx_queue, struct rte_mbuf **rx_pkts,
1381 struct iavf_rx_queue *rxq = rx_queue;
1382 union iavf_rx_flex_desc rxd;
1383 struct rte_mbuf *rxe;
1384 struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1385 struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1386 struct rte_mbuf *nmb, *rxm;
1387 uint16_t rx_id = rxq->rx_tail;
1388 uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
1389 struct rte_eth_dev *dev;
1390 uint16_t rx_stat_err0;
1394 volatile union iavf_rx_desc *rx_ring = rxq->rx_ring;
1395 volatile union iavf_rx_flex_desc *rxdp;
1396 const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1398 while (nb_rx < nb_pkts) {
1399 rxdp = (volatile union iavf_rx_flex_desc *)&rx_ring[rx_id];
1400 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1402 /* Check the DD bit */
1403 if (!(rx_stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S)))
1405 IAVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
1407 nmb = rte_mbuf_raw_alloc(rxq->mp);
1408 if (unlikely(!nmb)) {
1409 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1410 "queue_id=%u", rxq->port_id, rxq->queue_id);
1411 dev = &rte_eth_devices[rxq->port_id];
1412 dev->data->rx_mbuf_alloc_failed++;
1418 rxe = rxq->sw_ring[rx_id];
1419 rxq->sw_ring[rx_id] = nmb;
1421 if (rx_id == rxq->nb_rx_desc)
1424 /* Prefetch next mbuf */
1425 rte_prefetch0(rxq->sw_ring[rx_id]);
1427 /* When next RX descriptor is on a cache line boundary,
1428 * prefetch the next 4 RX descriptors and next 8 pointers
1431 if ((rx_id & 0x3) == 0) {
1432 rte_prefetch0(&rx_ring[rx_id]);
1433 rte_prefetch0(rxq->sw_ring[rx_id]);
1438 rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1440 /* Set data buffer address and data length of the mbuf */
1441 rxdp->read.hdr_addr = 0;
1442 rxdp->read.pkt_addr = dma_addr;
1443 rx_packet_len = rte_le_to_cpu_16(rxd.wb.pkt_len) &
1444 IAVF_RX_FLX_DESC_PKT_LEN_M;
1445 rxm->data_len = rx_packet_len;
1446 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1448 /* If this is the first buffer of the received packet, set the
1449 * pointer to the first mbuf of the packet and initialize its
1450 * context. Otherwise, update the total length and the number
1451 * of segments of the current scattered packet, and update the
1452 * pointer to the last mbuf of the current packet.
1456 first_seg->nb_segs = 1;
1457 first_seg->pkt_len = rx_packet_len;
1459 first_seg->pkt_len =
1460 (uint16_t)(first_seg->pkt_len +
1462 first_seg->nb_segs++;
1463 last_seg->next = rxm;
1466 /* If this is not the last buffer of the received packet,
1467 * update the pointer to the last mbuf of the current scattered
1468 * packet and continue to parse the RX ring.
1470 if (!(rx_stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_EOF_S))) {
1475 /* This is the last buffer of the received packet. If the CRC
1476 * is not stripped by the hardware:
1477 * - Subtract the CRC length from the total packet length.
1478 * - If the last buffer only contains the whole CRC or a part
1479 * of it, free the mbuf associated to the last buffer. If part
1480 * of the CRC is also contained in the previous mbuf, subtract
1481 * the length of that CRC part from the data length of the
1485 if (unlikely(rxq->crc_len > 0)) {
1486 first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
1487 if (rx_packet_len <= RTE_ETHER_CRC_LEN) {
1488 rte_pktmbuf_free_seg(rxm);
1489 first_seg->nb_segs--;
1490 last_seg->data_len =
1491 (uint16_t)(last_seg->data_len -
1492 (RTE_ETHER_CRC_LEN - rx_packet_len));
1493 last_seg->next = NULL;
1495 rxm->data_len = (uint16_t)(rx_packet_len -
1500 first_seg->port = rxq->port_id;
1501 first_seg->ol_flags = 0;
1502 first_seg->packet_type = ptype_tbl[IAVF_RX_FLEX_DESC_PTYPE_M &
1503 rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
1504 iavf_flex_rxd_to_vlan_tci(first_seg, &rxd, rxq->rx_flags);
1505 rxq->rxd_to_pkt_fields(rxq, first_seg, &rxd);
1506 pkt_flags = iavf_flex_rxd_error_to_pkt_flags(rx_stat_err0);
1508 first_seg->ol_flags |= pkt_flags;
1510 /* Prefetch data of first segment, if configured to do so. */
1511 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1512 first_seg->data_off));
1513 rx_pkts[nb_rx++] = first_seg;
1517 /* Record index of the next RX descriptor to probe. */
1518 rxq->rx_tail = rx_id;
1519 rxq->pkt_first_seg = first_seg;
1520 rxq->pkt_last_seg = last_seg;
1522 iavf_update_rx_tail(rxq, nb_hold, rx_id);
1527 /* implement recv_scattered_pkts */
1529 iavf_recv_scattered_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1532 struct iavf_rx_queue *rxq = rx_queue;
1533 union iavf_rx_desc rxd;
1534 struct rte_mbuf *rxe;
1535 struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1536 struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1537 struct rte_mbuf *nmb, *rxm;
1538 uint16_t rx_id = rxq->rx_tail;
1539 uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
1540 struct rte_eth_dev *dev;
1546 volatile union iavf_rx_desc *rx_ring = rxq->rx_ring;
1547 volatile union iavf_rx_desc *rxdp;
1548 const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1550 while (nb_rx < nb_pkts) {
1551 rxdp = &rx_ring[rx_id];
1552 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1553 rx_status = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
1554 IAVF_RXD_QW1_STATUS_SHIFT;
1556 /* Check the DD bit */
1557 if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)))
1559 IAVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
1561 nmb = rte_mbuf_raw_alloc(rxq->mp);
1562 if (unlikely(!nmb)) {
1563 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1564 "queue_id=%u", rxq->port_id, rxq->queue_id);
1565 dev = &rte_eth_devices[rxq->port_id];
1566 dev->data->rx_mbuf_alloc_failed++;
1572 rxe = rxq->sw_ring[rx_id];
1573 rxq->sw_ring[rx_id] = nmb;
1575 if (rx_id == rxq->nb_rx_desc)
1578 /* Prefetch next mbuf */
1579 rte_prefetch0(rxq->sw_ring[rx_id]);
1581 /* When next RX descriptor is on a cache line boundary,
1582 * prefetch the next 4 RX descriptors and next 8 pointers
1585 if ((rx_id & 0x3) == 0) {
1586 rte_prefetch0(&rx_ring[rx_id]);
1587 rte_prefetch0(rxq->sw_ring[rx_id]);
1592 rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1594 /* Set data buffer address and data length of the mbuf */
1595 rxdp->read.hdr_addr = 0;
1596 rxdp->read.pkt_addr = dma_addr;
1597 rx_packet_len = (qword1 & IAVF_RXD_QW1_LENGTH_PBUF_MASK) >>
1598 IAVF_RXD_QW1_LENGTH_PBUF_SHIFT;
1599 rxm->data_len = rx_packet_len;
1600 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1602 /* If this is the first buffer of the received packet, set the
1603 * pointer to the first mbuf of the packet and initialize its
1604 * context. Otherwise, update the total length and the number
1605 * of segments of the current scattered packet, and update the
1606 * pointer to the last mbuf of the current packet.
1610 first_seg->nb_segs = 1;
1611 first_seg->pkt_len = rx_packet_len;
1613 first_seg->pkt_len =
1614 (uint16_t)(first_seg->pkt_len +
1616 first_seg->nb_segs++;
1617 last_seg->next = rxm;
1620 /* If this is not the last buffer of the received packet,
1621 * update the pointer to the last mbuf of the current scattered
1622 * packet and continue to parse the RX ring.
1624 if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_EOF_SHIFT))) {
1629 /* This is the last buffer of the received packet. If the CRC
1630 * is not stripped by the hardware:
1631 * - Subtract the CRC length from the total packet length.
1632 * - If the last buffer only contains the whole CRC or a part
1633 * of it, free the mbuf associated to the last buffer. If part
1634 * of the CRC is also contained in the previous mbuf, subtract
1635 * the length of that CRC part from the data length of the
1639 if (unlikely(rxq->crc_len > 0)) {
1640 first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
1641 if (rx_packet_len <= RTE_ETHER_CRC_LEN) {
1642 rte_pktmbuf_free_seg(rxm);
1643 first_seg->nb_segs--;
1644 last_seg->data_len =
1645 (uint16_t)(last_seg->data_len -
1646 (RTE_ETHER_CRC_LEN - rx_packet_len));
1647 last_seg->next = NULL;
1649 rxm->data_len = (uint16_t)(rx_packet_len -
1653 first_seg->port = rxq->port_id;
1654 first_seg->ol_flags = 0;
1655 iavf_rxd_to_vlan_tci(first_seg, &rxd);
1656 pkt_flags = iavf_rxd_to_pkt_flags(qword1);
1657 first_seg->packet_type =
1658 ptype_tbl[(uint8_t)((qword1 &
1659 IAVF_RXD_QW1_PTYPE_MASK) >> IAVF_RXD_QW1_PTYPE_SHIFT)];
1661 if (pkt_flags & PKT_RX_RSS_HASH)
1662 first_seg->hash.rss =
1663 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1665 if (pkt_flags & PKT_RX_FDIR)
1666 pkt_flags |= iavf_rxd_build_fdir(&rxd, first_seg);
1668 first_seg->ol_flags |= pkt_flags;
1670 /* Prefetch data of first segment, if configured to do so. */
1671 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1672 first_seg->data_off));
1673 rx_pkts[nb_rx++] = first_seg;
1677 /* Record index of the next RX descriptor to probe. */
1678 rxq->rx_tail = rx_id;
1679 rxq->pkt_first_seg = first_seg;
1680 rxq->pkt_last_seg = last_seg;
1682 iavf_update_rx_tail(rxq, nb_hold, rx_id);
1687 #define IAVF_LOOK_AHEAD 8
1689 iavf_rx_scan_hw_ring_flex_rxd(struct iavf_rx_queue *rxq)
1691 volatile union iavf_rx_flex_desc *rxdp;
1692 struct rte_mbuf **rxep;
1693 struct rte_mbuf *mb;
1696 int32_t s[IAVF_LOOK_AHEAD], nb_dd;
1697 int32_t i, j, nb_rx = 0;
1699 const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1701 rxdp = (volatile union iavf_rx_flex_desc *)&rxq->rx_ring[rxq->rx_tail];
1702 rxep = &rxq->sw_ring[rxq->rx_tail];
1704 stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1706 /* Make sure there is at least 1 packet to receive */
1707 if (!(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S)))
1710 /* Scan LOOK_AHEAD descriptors at a time to determine which
1711 * descriptors reference packets that are ready to be received.
1713 for (i = 0; i < IAVF_RX_MAX_BURST; i += IAVF_LOOK_AHEAD,
1714 rxdp += IAVF_LOOK_AHEAD, rxep += IAVF_LOOK_AHEAD) {
1715 /* Read desc statuses backwards to avoid race condition */
1716 for (j = IAVF_LOOK_AHEAD - 1; j >= 0; j--)
1717 s[j] = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1721 /* Compute how many status bits were set */
1722 for (j = 0, nb_dd = 0; j < IAVF_LOOK_AHEAD; j++)
1723 nb_dd += s[j] & (1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S);
1727 /* Translate descriptor info to mbuf parameters */
1728 for (j = 0; j < nb_dd; j++) {
1729 IAVF_DUMP_RX_DESC(rxq, &rxdp[j],
1731 i * IAVF_LOOK_AHEAD + j);
1734 pkt_len = (rte_le_to_cpu_16(rxdp[j].wb.pkt_len) &
1735 IAVF_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
1736 mb->data_len = pkt_len;
1737 mb->pkt_len = pkt_len;
1740 mb->packet_type = ptype_tbl[IAVF_RX_FLEX_DESC_PTYPE_M &
1741 rte_le_to_cpu_16(rxdp[j].wb.ptype_flex_flags0)];
1742 iavf_flex_rxd_to_vlan_tci(mb, &rxdp[j], rxq->rx_flags);
1743 rxq->rxd_to_pkt_fields(rxq, mb, &rxdp[j]);
1744 stat_err0 = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1745 pkt_flags = iavf_flex_rxd_error_to_pkt_flags(stat_err0);
1747 mb->ol_flags |= pkt_flags;
1750 for (j = 0; j < IAVF_LOOK_AHEAD; j++)
1751 rxq->rx_stage[i + j] = rxep[j];
1753 if (nb_dd != IAVF_LOOK_AHEAD)
1757 /* Clear software ring entries */
1758 for (i = 0; i < nb_rx; i++)
1759 rxq->sw_ring[rxq->rx_tail + i] = NULL;
1765 iavf_rx_scan_hw_ring(struct iavf_rx_queue *rxq)
1767 volatile union iavf_rx_desc *rxdp;
1768 struct rte_mbuf **rxep;
1769 struct rte_mbuf *mb;
1773 int32_t s[IAVF_LOOK_AHEAD], nb_dd;
1774 int32_t i, j, nb_rx = 0;
1776 const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1778 rxdp = &rxq->rx_ring[rxq->rx_tail];
1779 rxep = &rxq->sw_ring[rxq->rx_tail];
1781 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1782 rx_status = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
1783 IAVF_RXD_QW1_STATUS_SHIFT;
1785 /* Make sure there is at least 1 packet to receive */
1786 if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)))
1789 /* Scan LOOK_AHEAD descriptors at a time to determine which
1790 * descriptors reference packets that are ready to be received.
1792 for (i = 0; i < IAVF_RX_MAX_BURST; i += IAVF_LOOK_AHEAD,
1793 rxdp += IAVF_LOOK_AHEAD, rxep += IAVF_LOOK_AHEAD) {
1794 /* Read desc statuses backwards to avoid race condition */
1795 for (j = IAVF_LOOK_AHEAD - 1; j >= 0; j--) {
1796 qword1 = rte_le_to_cpu_64(
1797 rxdp[j].wb.qword1.status_error_len);
1798 s[j] = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
1799 IAVF_RXD_QW1_STATUS_SHIFT;
1804 /* Compute how many status bits were set */
1805 for (j = 0, nb_dd = 0; j < IAVF_LOOK_AHEAD; j++)
1806 nb_dd += s[j] & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT);
1810 /* Translate descriptor info to mbuf parameters */
1811 for (j = 0; j < nb_dd; j++) {
1812 IAVF_DUMP_RX_DESC(rxq, &rxdp[j],
1813 rxq->rx_tail + i * IAVF_LOOK_AHEAD + j);
1816 qword1 = rte_le_to_cpu_64
1817 (rxdp[j].wb.qword1.status_error_len);
1818 pkt_len = ((qword1 & IAVF_RXD_QW1_LENGTH_PBUF_MASK) >>
1819 IAVF_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
1820 mb->data_len = pkt_len;
1821 mb->pkt_len = pkt_len;
1823 iavf_rxd_to_vlan_tci(mb, &rxdp[j]);
1824 pkt_flags = iavf_rxd_to_pkt_flags(qword1);
1826 ptype_tbl[(uint8_t)((qword1 &
1827 IAVF_RXD_QW1_PTYPE_MASK) >>
1828 IAVF_RXD_QW1_PTYPE_SHIFT)];
1830 if (pkt_flags & PKT_RX_RSS_HASH)
1831 mb->hash.rss = rte_le_to_cpu_32(
1832 rxdp[j].wb.qword0.hi_dword.rss);
1834 if (pkt_flags & PKT_RX_FDIR)
1835 pkt_flags |= iavf_rxd_build_fdir(&rxdp[j], mb);
1837 mb->ol_flags |= pkt_flags;
1840 for (j = 0; j < IAVF_LOOK_AHEAD; j++)
1841 rxq->rx_stage[i + j] = rxep[j];
1843 if (nb_dd != IAVF_LOOK_AHEAD)
1847 /* Clear software ring entries */
1848 for (i = 0; i < nb_rx; i++)
1849 rxq->sw_ring[rxq->rx_tail + i] = NULL;
1854 static inline uint16_t
1855 iavf_rx_fill_from_stage(struct iavf_rx_queue *rxq,
1856 struct rte_mbuf **rx_pkts,
1860 struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1862 nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1864 for (i = 0; i < nb_pkts; i++)
1865 rx_pkts[i] = stage[i];
1867 rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1868 rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1874 iavf_rx_alloc_bufs(struct iavf_rx_queue *rxq)
1876 volatile union iavf_rx_desc *rxdp;
1877 struct rte_mbuf **rxep;
1878 struct rte_mbuf *mb;
1879 uint16_t alloc_idx, i;
1883 /* Allocate buffers in bulk */
1884 alloc_idx = (uint16_t)(rxq->rx_free_trigger -
1885 (rxq->rx_free_thresh - 1));
1886 rxep = &rxq->sw_ring[alloc_idx];
1887 diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
1888 rxq->rx_free_thresh);
1889 if (unlikely(diag != 0)) {
1890 PMD_RX_LOG(ERR, "Failed to get mbufs in bulk");
1894 rxdp = &rxq->rx_ring[alloc_idx];
1895 for (i = 0; i < rxq->rx_free_thresh; i++) {
1896 if (likely(i < (rxq->rx_free_thresh - 1)))
1897 /* Prefetch next mbuf */
1898 rte_prefetch0(rxep[i + 1]);
1901 rte_mbuf_refcnt_set(mb, 1);
1903 mb->data_off = RTE_PKTMBUF_HEADROOM;
1905 mb->port = rxq->port_id;
1906 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mb));
1907 rxdp[i].read.hdr_addr = 0;
1908 rxdp[i].read.pkt_addr = dma_addr;
1911 /* Update rx tail register */
1913 IAVF_PCI_REG_WC_WRITE_RELAXED(rxq->qrx_tail, rxq->rx_free_trigger);
1915 rxq->rx_free_trigger =
1916 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
1917 if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1918 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
1923 static inline uint16_t
1924 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1926 struct iavf_rx_queue *rxq = (struct iavf_rx_queue *)rx_queue;
1932 if (rxq->rx_nb_avail)
1933 return iavf_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1935 if (rxq->rxdid >= IAVF_RXDID_FLEX_NIC && rxq->rxdid <= IAVF_RXDID_LAST)
1936 nb_rx = (uint16_t)iavf_rx_scan_hw_ring_flex_rxd(rxq);
1938 nb_rx = (uint16_t)iavf_rx_scan_hw_ring(rxq);
1939 rxq->rx_next_avail = 0;
1940 rxq->rx_nb_avail = nb_rx;
1941 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1943 if (rxq->rx_tail > rxq->rx_free_trigger) {
1944 if (iavf_rx_alloc_bufs(rxq) != 0) {
1947 /* TODO: count rx_mbuf_alloc_failed here */
1949 rxq->rx_nb_avail = 0;
1950 rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1951 for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
1952 rxq->sw_ring[j] = rxq->rx_stage[i];
1958 if (rxq->rx_tail >= rxq->nb_rx_desc)
1961 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u, nb_rx=%u",
1962 rxq->port_id, rxq->queue_id,
1963 rxq->rx_tail, nb_rx);
1965 if (rxq->rx_nb_avail)
1966 return iavf_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1972 iavf_recv_pkts_bulk_alloc(void *rx_queue,
1973 struct rte_mbuf **rx_pkts,
1976 uint16_t nb_rx = 0, n, count;
1978 if (unlikely(nb_pkts == 0))
1981 if (likely(nb_pkts <= IAVF_RX_MAX_BURST))
1982 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1985 n = RTE_MIN(nb_pkts, IAVF_RX_MAX_BURST);
1986 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1987 nb_rx = (uint16_t)(nb_rx + count);
1988 nb_pkts = (uint16_t)(nb_pkts - count);
1997 iavf_xmit_cleanup(struct iavf_tx_queue *txq)
1999 struct iavf_tx_entry *sw_ring = txq->sw_ring;
2000 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
2001 uint16_t nb_tx_desc = txq->nb_tx_desc;
2002 uint16_t desc_to_clean_to;
2003 uint16_t nb_tx_to_clean;
2005 volatile struct iavf_tx_desc *txd = txq->tx_ring;
2007 desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->rs_thresh);
2008 if (desc_to_clean_to >= nb_tx_desc)
2009 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
2011 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
2012 if ((txd[desc_to_clean_to].cmd_type_offset_bsz &
2013 rte_cpu_to_le_64(IAVF_TXD_QW1_DTYPE_MASK)) !=
2014 rte_cpu_to_le_64(IAVF_TX_DESC_DTYPE_DESC_DONE)) {
2015 PMD_TX_LOG(DEBUG, "TX descriptor %4u is not done "
2016 "(port=%d queue=%d)", desc_to_clean_to,
2017 txq->port_id, txq->queue_id);
2021 if (last_desc_cleaned > desc_to_clean_to)
2022 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
2025 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
2028 txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
2030 txq->last_desc_cleaned = desc_to_clean_to;
2031 txq->nb_free = (uint16_t)(txq->nb_free + nb_tx_to_clean);
2036 /* Check if the context descriptor is needed for TX offloading */
2037 static inline uint16_t
2038 iavf_calc_context_desc(uint64_t flags, uint8_t vlan_flag)
2040 if (flags & PKT_TX_TCP_SEG)
2042 if (flags & PKT_TX_VLAN_PKT &&
2043 vlan_flag & IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG2)
2049 iavf_txd_enable_checksum(uint64_t ol_flags,
2051 uint32_t *td_offset,
2052 union iavf_tx_offload tx_offload)
2055 *td_offset |= (tx_offload.l2_len >> 1) <<
2056 IAVF_TX_DESC_LENGTH_MACLEN_SHIFT;
2058 /* Enable L3 checksum offloads */
2059 if (ol_flags & PKT_TX_IP_CKSUM) {
2060 *td_cmd |= IAVF_TX_DESC_CMD_IIPT_IPV4_CSUM;
2061 *td_offset |= (tx_offload.l3_len >> 2) <<
2062 IAVF_TX_DESC_LENGTH_IPLEN_SHIFT;
2063 } else if (ol_flags & PKT_TX_IPV4) {
2064 *td_cmd |= IAVF_TX_DESC_CMD_IIPT_IPV4;
2065 *td_offset |= (tx_offload.l3_len >> 2) <<
2066 IAVF_TX_DESC_LENGTH_IPLEN_SHIFT;
2067 } else if (ol_flags & PKT_TX_IPV6) {
2068 *td_cmd |= IAVF_TX_DESC_CMD_IIPT_IPV6;
2069 *td_offset |= (tx_offload.l3_len >> 2) <<
2070 IAVF_TX_DESC_LENGTH_IPLEN_SHIFT;
2073 if (ol_flags & PKT_TX_TCP_SEG) {
2074 *td_cmd |= IAVF_TX_DESC_CMD_L4T_EOFT_TCP;
2075 *td_offset |= (tx_offload.l4_len >> 2) <<
2076 IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2080 /* Enable L4 checksum offloads */
2081 switch (ol_flags & PKT_TX_L4_MASK) {
2082 case PKT_TX_TCP_CKSUM:
2083 *td_cmd |= IAVF_TX_DESC_CMD_L4T_EOFT_TCP;
2084 *td_offset |= (sizeof(struct rte_tcp_hdr) >> 2) <<
2085 IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2087 case PKT_TX_SCTP_CKSUM:
2088 *td_cmd |= IAVF_TX_DESC_CMD_L4T_EOFT_SCTP;
2089 *td_offset |= (sizeof(struct rte_sctp_hdr) >> 2) <<
2090 IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2092 case PKT_TX_UDP_CKSUM:
2093 *td_cmd |= IAVF_TX_DESC_CMD_L4T_EOFT_UDP;
2094 *td_offset |= (sizeof(struct rte_udp_hdr) >> 2) <<
2095 IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2102 /* set TSO context descriptor
2103 * support IP -> L4 and IP -> IP -> L4
2105 static inline uint64_t
2106 iavf_set_tso_ctx(struct rte_mbuf *mbuf, union iavf_tx_offload tx_offload)
2108 uint64_t ctx_desc = 0;
2109 uint32_t cd_cmd, hdr_len, cd_tso_len;
2111 if (!tx_offload.l4_len) {
2112 PMD_TX_LOG(DEBUG, "L4 length set to 0");
2116 hdr_len = tx_offload.l2_len +
2120 cd_cmd = IAVF_TX_CTX_DESC_TSO;
2121 cd_tso_len = mbuf->pkt_len - hdr_len;
2122 ctx_desc |= ((uint64_t)cd_cmd << IAVF_TXD_CTX_QW1_CMD_SHIFT) |
2123 ((uint64_t)cd_tso_len << IAVF_TXD_CTX_QW1_TSO_LEN_SHIFT) |
2124 ((uint64_t)mbuf->tso_segsz << IAVF_TXD_CTX_QW1_MSS_SHIFT);
2129 /* Construct the tx flags */
2130 static inline uint64_t
2131 iavf_build_ctob(uint32_t td_cmd, uint32_t td_offset, unsigned int size,
2134 return rte_cpu_to_le_64(IAVF_TX_DESC_DTYPE_DATA |
2135 ((uint64_t)td_cmd << IAVF_TXD_QW1_CMD_SHIFT) |
2136 ((uint64_t)td_offset <<
2137 IAVF_TXD_QW1_OFFSET_SHIFT) |
2139 IAVF_TXD_QW1_TX_BUF_SZ_SHIFT) |
2140 ((uint64_t)td_tag <<
2141 IAVF_TXD_QW1_L2TAG1_SHIFT));
2146 iavf_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2148 volatile struct iavf_tx_desc *txd;
2149 volatile struct iavf_tx_desc *txr;
2150 struct iavf_tx_queue *txq;
2151 struct iavf_tx_entry *sw_ring;
2152 struct iavf_tx_entry *txe, *txn;
2153 struct rte_mbuf *tx_pkt;
2154 struct rte_mbuf *m_seg;
2165 uint64_t buf_dma_addr;
2166 uint16_t cd_l2tag2 = 0;
2167 union iavf_tx_offload tx_offload = {0};
2170 sw_ring = txq->sw_ring;
2172 tx_id = txq->tx_tail;
2173 txe = &sw_ring[tx_id];
2175 /* Check if the descriptor ring needs to be cleaned. */
2176 if (txq->nb_free < txq->free_thresh)
2177 (void)iavf_xmit_cleanup(txq);
2179 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
2184 tx_pkt = *tx_pkts++;
2185 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
2187 ol_flags = tx_pkt->ol_flags;
2188 tx_offload.l2_len = tx_pkt->l2_len;
2189 tx_offload.l3_len = tx_pkt->l3_len;
2190 tx_offload.l4_len = tx_pkt->l4_len;
2191 tx_offload.tso_segsz = tx_pkt->tso_segsz;
2192 /* Calculate the number of context descriptors needed. */
2193 nb_ctx = iavf_calc_context_desc(ol_flags, txq->vlan_flag);
2195 /* The number of descriptors that must be allocated for
2196 * a packet equals to the number of the segments of that
2197 * packet plus 1 context descriptor if needed.
2199 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
2200 tx_last = (uint16_t)(tx_id + nb_used - 1);
2203 if (tx_last >= txq->nb_tx_desc)
2204 tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
2206 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u"
2207 " tx_first=%u tx_last=%u",
2208 txq->port_id, txq->queue_id, tx_id, tx_last);
2210 if (nb_used > txq->nb_free) {
2211 if (iavf_xmit_cleanup(txq)) {
2216 if (unlikely(nb_used > txq->rs_thresh)) {
2217 while (nb_used > txq->nb_free) {
2218 if (iavf_xmit_cleanup(txq)) {
2227 /* Descriptor based VLAN insertion */
2228 if (ol_flags & PKT_TX_VLAN_PKT &&
2229 txq->vlan_flag & IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG1) {
2230 td_cmd |= IAVF_TX_DESC_CMD_IL2TAG1;
2231 td_tag = tx_pkt->vlan_tci;
2234 /* According to datasheet, the bit2 is reserved and must be
2239 /* Enable checksum offloading */
2240 if (ol_flags & IAVF_TX_CKSUM_OFFLOAD_MASK)
2241 iavf_txd_enable_checksum(ol_flags, &td_cmd,
2242 &td_offset, tx_offload);
2245 /* Setup TX context descriptor if required */
2246 uint64_t cd_type_cmd_tso_mss =
2247 IAVF_TX_DESC_DTYPE_CONTEXT;
2248 volatile struct iavf_tx_context_desc *ctx_txd =
2249 (volatile struct iavf_tx_context_desc *)
2252 /* clear QW0 or the previous writeback value
2253 * may impact next write
2255 *(volatile uint64_t *)ctx_txd = 0;
2257 txn = &sw_ring[txe->next_id];
2258 RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
2260 rte_pktmbuf_free_seg(txe->mbuf);
2265 if (ol_flags & PKT_TX_TCP_SEG)
2266 cd_type_cmd_tso_mss |=
2267 iavf_set_tso_ctx(tx_pkt, tx_offload);
2269 if (ol_flags & PKT_TX_VLAN_PKT &&
2270 txq->vlan_flag & IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG2) {
2271 cd_type_cmd_tso_mss |= IAVF_TX_CTX_DESC_IL2TAG2
2272 << IAVF_TXD_CTX_QW1_CMD_SHIFT;
2273 cd_l2tag2 = tx_pkt->vlan_tci;
2276 ctx_txd->type_cmd_tso_mss =
2277 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
2278 ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
2280 IAVF_DUMP_TX_DESC(txq, &txr[tx_id], tx_id);
2281 txe->last_id = tx_last;
2282 tx_id = txe->next_id;
2289 txn = &sw_ring[txe->next_id];
2292 rte_pktmbuf_free_seg(txe->mbuf);
2295 /* Setup TX Descriptor */
2296 slen = m_seg->data_len;
2297 buf_dma_addr = rte_mbuf_data_iova(m_seg);
2298 txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
2299 txd->cmd_type_offset_bsz = iavf_build_ctob(td_cmd,
2304 IAVF_DUMP_TX_DESC(txq, txd, tx_id);
2305 txe->last_id = tx_last;
2306 tx_id = txe->next_id;
2308 m_seg = m_seg->next;
2311 /* The last packet data descriptor needs End Of Packet (EOP) */
2312 td_cmd |= IAVF_TX_DESC_CMD_EOP;
2313 txq->nb_used = (uint16_t)(txq->nb_used + nb_used);
2314 txq->nb_free = (uint16_t)(txq->nb_free - nb_used);
2316 if (txq->nb_used >= txq->rs_thresh) {
2317 PMD_TX_LOG(DEBUG, "Setting RS bit on TXD id="
2318 "%4u (port=%d queue=%d)",
2319 tx_last, txq->port_id, txq->queue_id);
2321 td_cmd |= IAVF_TX_DESC_CMD_RS;
2323 /* Update txq RS bit counters */
2327 txd->cmd_type_offset_bsz |=
2328 rte_cpu_to_le_64(((uint64_t)td_cmd) <<
2329 IAVF_TXD_QW1_CMD_SHIFT);
2330 IAVF_DUMP_TX_DESC(txq, txd, tx_id);
2336 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
2337 txq->port_id, txq->queue_id, tx_id, nb_tx);
2339 IAVF_PCI_REG_WC_WRITE_RELAXED(txq->qtx_tail, tx_id);
2340 txq->tx_tail = tx_id;
2345 /* TX prep functions */
2347 iavf_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
2354 for (i = 0; i < nb_pkts; i++) {
2356 ol_flags = m->ol_flags;
2358 /* Check condition for nb_segs > IAVF_TX_MAX_MTU_SEG. */
2359 if (!(ol_flags & PKT_TX_TCP_SEG)) {
2360 if (m->nb_segs > IAVF_TX_MAX_MTU_SEG) {
2364 } else if ((m->tso_segsz < IAVF_MIN_TSO_MSS) ||
2365 (m->tso_segsz > IAVF_MAX_TSO_MSS)) {
2366 /* MSS outside the range are considered malicious */
2371 if (ol_flags & IAVF_TX_OFFLOAD_NOTSUP_MASK) {
2372 rte_errno = ENOTSUP;
2376 #ifdef RTE_ETHDEV_DEBUG_TX
2377 ret = rte_validate_tx_offload(m);
2383 ret = rte_net_intel_cksum_prepare(m);
2393 /* choose rx function*/
2395 iavf_set_rx_function(struct rte_eth_dev *dev)
2397 struct iavf_adapter *adapter =
2398 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2399 struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2402 struct iavf_rx_queue *rxq;
2405 bool use_avx2 = false;
2406 bool use_avx512 = false;
2407 bool use_flex = false;
2409 check_ret = iavf_rx_vec_dev_check(dev);
2410 if (check_ret >= 0 &&
2411 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
2412 if ((rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
2413 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) &&
2414 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256)
2417 #ifdef CC_AVX512_SUPPORT
2418 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 &&
2419 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1 &&
2420 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512)
2424 if (vf->vf_res->vf_cap_flags &
2425 VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC)
2428 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2429 rxq = dev->data->rx_queues[i];
2430 (void)iavf_rxq_vec_setup(rxq);
2433 if (dev->data->scattered_rx) {
2436 "Using %sVector Scattered Rx (port %d).",
2437 use_avx2 ? "avx2 " : "",
2438 dev->data->port_id);
2440 if (check_ret == IAVF_VECTOR_PATH)
2442 "Using AVX512 Vector Scattered Rx (port %d).",
2443 dev->data->port_id);
2446 "Using AVX512 OFFLOAD Vector Scattered Rx (port %d).",
2447 dev->data->port_id);
2450 dev->rx_pkt_burst = use_avx2 ?
2451 iavf_recv_scattered_pkts_vec_avx2_flex_rxd :
2452 iavf_recv_scattered_pkts_vec_flex_rxd;
2453 #ifdef CC_AVX512_SUPPORT
2455 if (check_ret == IAVF_VECTOR_PATH)
2457 iavf_recv_scattered_pkts_vec_avx512_flex_rxd;
2460 iavf_recv_scattered_pkts_vec_avx512_flex_rxd_offload;
2464 dev->rx_pkt_burst = use_avx2 ?
2465 iavf_recv_scattered_pkts_vec_avx2 :
2466 iavf_recv_scattered_pkts_vec;
2467 #ifdef CC_AVX512_SUPPORT
2469 if (check_ret == IAVF_VECTOR_PATH)
2471 iavf_recv_scattered_pkts_vec_avx512;
2474 iavf_recv_scattered_pkts_vec_avx512_offload;
2480 PMD_DRV_LOG(DEBUG, "Using %sVector Rx (port %d).",
2481 use_avx2 ? "avx2 " : "",
2482 dev->data->port_id);
2484 if (check_ret == IAVF_VECTOR_PATH)
2486 "Using AVX512 Vector Rx (port %d).",
2487 dev->data->port_id);
2490 "Using AVX512 OFFLOAD Vector Rx (port %d).",
2491 dev->data->port_id);
2494 dev->rx_pkt_burst = use_avx2 ?
2495 iavf_recv_pkts_vec_avx2_flex_rxd :
2496 iavf_recv_pkts_vec_flex_rxd;
2497 #ifdef CC_AVX512_SUPPORT
2499 if (check_ret == IAVF_VECTOR_PATH)
2501 iavf_recv_pkts_vec_avx512_flex_rxd;
2504 iavf_recv_pkts_vec_avx512_flex_rxd_offload;
2508 dev->rx_pkt_burst = use_avx2 ?
2509 iavf_recv_pkts_vec_avx2 :
2511 #ifdef CC_AVX512_SUPPORT
2513 if (check_ret == IAVF_VECTOR_PATH)
2515 iavf_recv_pkts_vec_avx512;
2518 iavf_recv_pkts_vec_avx512_offload;
2528 if (dev->data->scattered_rx) {
2529 PMD_DRV_LOG(DEBUG, "Using a Scattered Rx callback (port=%d).",
2530 dev->data->port_id);
2531 if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC)
2532 dev->rx_pkt_burst = iavf_recv_scattered_pkts_flex_rxd;
2534 dev->rx_pkt_burst = iavf_recv_scattered_pkts;
2535 } else if (adapter->rx_bulk_alloc_allowed) {
2536 PMD_DRV_LOG(DEBUG, "Using bulk Rx callback (port=%d).",
2537 dev->data->port_id);
2538 dev->rx_pkt_burst = iavf_recv_pkts_bulk_alloc;
2540 PMD_DRV_LOG(DEBUG, "Using Basic Rx callback (port=%d).",
2541 dev->data->port_id);
2542 if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC)
2543 dev->rx_pkt_burst = iavf_recv_pkts_flex_rxd;
2545 dev->rx_pkt_burst = iavf_recv_pkts;
2549 /* choose tx function*/
2551 iavf_set_tx_function(struct rte_eth_dev *dev)
2554 struct iavf_tx_queue *txq;
2557 bool use_sse = false;
2558 bool use_avx2 = false;
2559 bool use_avx512 = false;
2561 check_ret = iavf_tx_vec_dev_check(dev);
2563 if (check_ret >= 0 &&
2564 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
2565 /* SSE and AVX2 not support offload path yet. */
2566 if (check_ret == IAVF_VECTOR_PATH) {
2568 if ((rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
2569 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) &&
2570 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256)
2573 #ifdef CC_AVX512_SUPPORT
2574 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 &&
2575 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1 &&
2576 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512)
2580 if (!use_sse && !use_avx2 && !use_avx512)
2584 PMD_DRV_LOG(DEBUG, "Using %sVector Tx (port %d).",
2585 use_avx2 ? "avx2 " : "",
2586 dev->data->port_id);
2587 dev->tx_pkt_burst = use_avx2 ?
2588 iavf_xmit_pkts_vec_avx2 :
2591 dev->tx_pkt_prepare = NULL;
2592 #ifdef CC_AVX512_SUPPORT
2594 if (check_ret == IAVF_VECTOR_PATH) {
2595 dev->tx_pkt_burst = iavf_xmit_pkts_vec_avx512;
2596 PMD_DRV_LOG(DEBUG, "Using AVX512 Vector Tx (port %d).",
2597 dev->data->port_id);
2599 dev->tx_pkt_burst = iavf_xmit_pkts_vec_avx512_offload;
2600 dev->tx_pkt_prepare = iavf_prep_pkts;
2601 PMD_DRV_LOG(DEBUG, "Using AVX512 OFFLOAD Vector Tx (port %d).",
2602 dev->data->port_id);
2607 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2608 txq = dev->data->tx_queues[i];
2611 #ifdef CC_AVX512_SUPPORT
2613 iavf_txq_vec_setup_avx512(txq);
2615 iavf_txq_vec_setup(txq);
2617 iavf_txq_vec_setup(txq);
2626 PMD_DRV_LOG(DEBUG, "Using Basic Tx callback (port=%d).",
2627 dev->data->port_id);
2628 dev->tx_pkt_burst = iavf_xmit_pkts;
2629 dev->tx_pkt_prepare = iavf_prep_pkts;
2633 iavf_tx_done_cleanup_full(struct iavf_tx_queue *txq,
2636 struct iavf_tx_entry *swr_ring = txq->sw_ring;
2637 uint16_t i, tx_last, tx_id;
2638 uint16_t nb_tx_free_last;
2639 uint16_t nb_tx_to_clean;
2642 /* Start free mbuf from the next of tx_tail */
2643 tx_last = txq->tx_tail;
2644 tx_id = swr_ring[tx_last].next_id;
2646 if (txq->nb_free == 0 && iavf_xmit_cleanup(txq))
2649 nb_tx_to_clean = txq->nb_free;
2650 nb_tx_free_last = txq->nb_free;
2652 free_cnt = txq->nb_tx_desc;
2654 /* Loop through swr_ring to count the amount of
2655 * freeable mubfs and packets.
2657 for (pkt_cnt = 0; pkt_cnt < free_cnt; ) {
2658 for (i = 0; i < nb_tx_to_clean &&
2659 pkt_cnt < free_cnt &&
2660 tx_id != tx_last; i++) {
2661 if (swr_ring[tx_id].mbuf != NULL) {
2662 rte_pktmbuf_free_seg(swr_ring[tx_id].mbuf);
2663 swr_ring[tx_id].mbuf = NULL;
2666 * last segment in the packet,
2667 * increment packet count
2669 pkt_cnt += (swr_ring[tx_id].last_id == tx_id);
2672 tx_id = swr_ring[tx_id].next_id;
2675 if (txq->rs_thresh > txq->nb_tx_desc -
2676 txq->nb_free || tx_id == tx_last)
2679 if (pkt_cnt < free_cnt) {
2680 if (iavf_xmit_cleanup(txq))
2683 nb_tx_to_clean = txq->nb_free - nb_tx_free_last;
2684 nb_tx_free_last = txq->nb_free;
2688 return (int)pkt_cnt;
2692 iavf_dev_tx_done_cleanup(void *txq, uint32_t free_cnt)
2694 struct iavf_tx_queue *q = (struct iavf_tx_queue *)txq;
2696 return iavf_tx_done_cleanup_full(q, free_cnt);
2700 iavf_dev_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2701 struct rte_eth_rxq_info *qinfo)
2703 struct iavf_rx_queue *rxq;
2705 rxq = dev->data->rx_queues[queue_id];
2707 qinfo->mp = rxq->mp;
2708 qinfo->scattered_rx = dev->data->scattered_rx;
2709 qinfo->nb_desc = rxq->nb_rx_desc;
2711 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2712 qinfo->conf.rx_drop_en = true;
2713 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2717 iavf_dev_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2718 struct rte_eth_txq_info *qinfo)
2720 struct iavf_tx_queue *txq;
2722 txq = dev->data->tx_queues[queue_id];
2724 qinfo->nb_desc = txq->nb_tx_desc;
2726 qinfo->conf.tx_free_thresh = txq->free_thresh;
2727 qinfo->conf.tx_rs_thresh = txq->rs_thresh;
2728 qinfo->conf.offloads = txq->offloads;
2729 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2732 /* Get the number of used descriptors of a rx queue */
2734 iavf_dev_rxq_count(struct rte_eth_dev *dev, uint16_t queue_id)
2736 #define IAVF_RXQ_SCAN_INTERVAL 4
2737 volatile union iavf_rx_desc *rxdp;
2738 struct iavf_rx_queue *rxq;
2741 rxq = dev->data->rx_queues[queue_id];
2742 rxdp = &rxq->rx_ring[rxq->rx_tail];
2744 while ((desc < rxq->nb_rx_desc) &&
2745 ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
2746 IAVF_RXD_QW1_STATUS_MASK) >> IAVF_RXD_QW1_STATUS_SHIFT) &
2747 (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)) {
2748 /* Check the DD bit of a rx descriptor of each 4 in a group,
2749 * to avoid checking too frequently and downgrading performance
2752 desc += IAVF_RXQ_SCAN_INTERVAL;
2753 rxdp += IAVF_RXQ_SCAN_INTERVAL;
2754 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
2755 rxdp = &(rxq->rx_ring[rxq->rx_tail +
2756 desc - rxq->nb_rx_desc]);
2763 iavf_dev_rx_desc_status(void *rx_queue, uint16_t offset)
2765 struct iavf_rx_queue *rxq = rx_queue;
2766 volatile uint64_t *status;
2770 if (unlikely(offset >= rxq->nb_rx_desc))
2773 if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
2774 return RTE_ETH_RX_DESC_UNAVAIL;
2776 desc = rxq->rx_tail + offset;
2777 if (desc >= rxq->nb_rx_desc)
2778 desc -= rxq->nb_rx_desc;
2780 status = &rxq->rx_ring[desc].wb.qword1.status_error_len;
2781 mask = rte_le_to_cpu_64((1ULL << IAVF_RX_DESC_STATUS_DD_SHIFT)
2782 << IAVF_RXD_QW1_STATUS_SHIFT);
2784 return RTE_ETH_RX_DESC_DONE;
2786 return RTE_ETH_RX_DESC_AVAIL;
2790 iavf_dev_tx_desc_status(void *tx_queue, uint16_t offset)
2792 struct iavf_tx_queue *txq = tx_queue;
2793 volatile uint64_t *status;
2794 uint64_t mask, expect;
2797 if (unlikely(offset >= txq->nb_tx_desc))
2800 desc = txq->tx_tail + offset;
2801 /* go to next desc that has the RS bit */
2802 desc = ((desc + txq->rs_thresh - 1) / txq->rs_thresh) *
2804 if (desc >= txq->nb_tx_desc) {
2805 desc -= txq->nb_tx_desc;
2806 if (desc >= txq->nb_tx_desc)
2807 desc -= txq->nb_tx_desc;
2810 status = &txq->tx_ring[desc].cmd_type_offset_bsz;
2811 mask = rte_le_to_cpu_64(IAVF_TXD_QW1_DTYPE_MASK);
2812 expect = rte_cpu_to_le_64(
2813 IAVF_TX_DESC_DTYPE_DESC_DONE << IAVF_TXD_QW1_DTYPE_SHIFT);
2814 if ((*status & mask) == expect)
2815 return RTE_ETH_TX_DESC_DONE;
2817 return RTE_ETH_TX_DESC_FULL;
2821 iavf_get_default_ptype_table(void)
2823 static const uint32_t ptype_tbl[IAVF_MAX_PKT_TYPE]
2824 __rte_cache_aligned = {
2827 [1] = RTE_PTYPE_L2_ETHER,
2828 [2] = RTE_PTYPE_L2_ETHER_TIMESYNC,
2829 /* [3] - [5] reserved */
2830 [6] = RTE_PTYPE_L2_ETHER_LLDP,
2831 /* [7] - [10] reserved */
2832 [11] = RTE_PTYPE_L2_ETHER_ARP,
2833 /* [12] - [21] reserved */
2835 /* Non tunneled IPv4 */
2836 [22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2838 [23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2839 RTE_PTYPE_L4_NONFRAG,
2840 [24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2843 [26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2845 [27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2847 [28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2851 [29] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2852 RTE_PTYPE_TUNNEL_IP |
2853 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2854 RTE_PTYPE_INNER_L4_FRAG,
2855 [30] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2856 RTE_PTYPE_TUNNEL_IP |
2857 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2858 RTE_PTYPE_INNER_L4_NONFRAG,
2859 [31] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2860 RTE_PTYPE_TUNNEL_IP |
2861 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2862 RTE_PTYPE_INNER_L4_UDP,
2864 [33] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2865 RTE_PTYPE_TUNNEL_IP |
2866 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2867 RTE_PTYPE_INNER_L4_TCP,
2868 [34] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2869 RTE_PTYPE_TUNNEL_IP |
2870 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2871 RTE_PTYPE_INNER_L4_SCTP,
2872 [35] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2873 RTE_PTYPE_TUNNEL_IP |
2874 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2875 RTE_PTYPE_INNER_L4_ICMP,
2878 [36] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2879 RTE_PTYPE_TUNNEL_IP |
2880 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2881 RTE_PTYPE_INNER_L4_FRAG,
2882 [37] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2883 RTE_PTYPE_TUNNEL_IP |
2884 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2885 RTE_PTYPE_INNER_L4_NONFRAG,
2886 [38] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2887 RTE_PTYPE_TUNNEL_IP |
2888 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2889 RTE_PTYPE_INNER_L4_UDP,
2891 [40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2892 RTE_PTYPE_TUNNEL_IP |
2893 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2894 RTE_PTYPE_INNER_L4_TCP,
2895 [41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2896 RTE_PTYPE_TUNNEL_IP |
2897 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2898 RTE_PTYPE_INNER_L4_SCTP,
2899 [42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2900 RTE_PTYPE_TUNNEL_IP |
2901 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2902 RTE_PTYPE_INNER_L4_ICMP,
2904 /* IPv4 --> GRE/Teredo/VXLAN */
2905 [43] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2906 RTE_PTYPE_TUNNEL_GRENAT,
2908 /* IPv4 --> GRE/Teredo/VXLAN --> IPv4 */
2909 [44] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2910 RTE_PTYPE_TUNNEL_GRENAT |
2911 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2912 RTE_PTYPE_INNER_L4_FRAG,
2913 [45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2914 RTE_PTYPE_TUNNEL_GRENAT |
2915 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2916 RTE_PTYPE_INNER_L4_NONFRAG,
2917 [46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2918 RTE_PTYPE_TUNNEL_GRENAT |
2919 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2920 RTE_PTYPE_INNER_L4_UDP,
2922 [48] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2923 RTE_PTYPE_TUNNEL_GRENAT |
2924 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2925 RTE_PTYPE_INNER_L4_TCP,
2926 [49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2927 RTE_PTYPE_TUNNEL_GRENAT |
2928 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2929 RTE_PTYPE_INNER_L4_SCTP,
2930 [50] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2931 RTE_PTYPE_TUNNEL_GRENAT |
2932 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2933 RTE_PTYPE_INNER_L4_ICMP,
2935 /* IPv4 --> GRE/Teredo/VXLAN --> IPv6 */
2936 [51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2937 RTE_PTYPE_TUNNEL_GRENAT |
2938 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2939 RTE_PTYPE_INNER_L4_FRAG,
2940 [52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2941 RTE_PTYPE_TUNNEL_GRENAT |
2942 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2943 RTE_PTYPE_INNER_L4_NONFRAG,
2944 [53] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2945 RTE_PTYPE_TUNNEL_GRENAT |
2946 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2947 RTE_PTYPE_INNER_L4_UDP,
2949 [55] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2950 RTE_PTYPE_TUNNEL_GRENAT |
2951 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2952 RTE_PTYPE_INNER_L4_TCP,
2953 [56] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2954 RTE_PTYPE_TUNNEL_GRENAT |
2955 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2956 RTE_PTYPE_INNER_L4_SCTP,
2957 [57] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2958 RTE_PTYPE_TUNNEL_GRENAT |
2959 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2960 RTE_PTYPE_INNER_L4_ICMP,
2962 /* IPv4 --> GRE/Teredo/VXLAN --> MAC */
2963 [58] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2964 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
2966 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
2967 [59] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2968 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2969 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2970 RTE_PTYPE_INNER_L4_FRAG,
2971 [60] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2972 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2973 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2974 RTE_PTYPE_INNER_L4_NONFRAG,
2975 [61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2976 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2977 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2978 RTE_PTYPE_INNER_L4_UDP,
2980 [63] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2981 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2982 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2983 RTE_PTYPE_INNER_L4_TCP,
2984 [64] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2985 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2986 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2987 RTE_PTYPE_INNER_L4_SCTP,
2988 [65] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2989 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2990 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2991 RTE_PTYPE_INNER_L4_ICMP,
2993 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
2994 [66] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2995 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2996 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2997 RTE_PTYPE_INNER_L4_FRAG,
2998 [67] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2999 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3000 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3001 RTE_PTYPE_INNER_L4_NONFRAG,
3002 [68] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3003 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3004 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3005 RTE_PTYPE_INNER_L4_UDP,
3007 [70] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3008 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3009 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3010 RTE_PTYPE_INNER_L4_TCP,
3011 [71] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3012 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3013 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3014 RTE_PTYPE_INNER_L4_SCTP,
3015 [72] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3016 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3017 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3018 RTE_PTYPE_INNER_L4_ICMP,
3019 /* [73] - [87] reserved */
3021 /* Non tunneled IPv6 */
3022 [88] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3024 [89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3025 RTE_PTYPE_L4_NONFRAG,
3026 [90] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3029 [92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3031 [93] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3033 [94] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3037 [95] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3038 RTE_PTYPE_TUNNEL_IP |
3039 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3040 RTE_PTYPE_INNER_L4_FRAG,
3041 [96] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3042 RTE_PTYPE_TUNNEL_IP |
3043 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3044 RTE_PTYPE_INNER_L4_NONFRAG,
3045 [97] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3046 RTE_PTYPE_TUNNEL_IP |
3047 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3048 RTE_PTYPE_INNER_L4_UDP,
3050 [99] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3051 RTE_PTYPE_TUNNEL_IP |
3052 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3053 RTE_PTYPE_INNER_L4_TCP,
3054 [100] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3055 RTE_PTYPE_TUNNEL_IP |
3056 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3057 RTE_PTYPE_INNER_L4_SCTP,
3058 [101] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3059 RTE_PTYPE_TUNNEL_IP |
3060 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3061 RTE_PTYPE_INNER_L4_ICMP,
3064 [102] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3065 RTE_PTYPE_TUNNEL_IP |
3066 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3067 RTE_PTYPE_INNER_L4_FRAG,
3068 [103] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3069 RTE_PTYPE_TUNNEL_IP |
3070 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3071 RTE_PTYPE_INNER_L4_NONFRAG,
3072 [104] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3073 RTE_PTYPE_TUNNEL_IP |
3074 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3075 RTE_PTYPE_INNER_L4_UDP,
3076 /* [105] reserved */
3077 [106] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3078 RTE_PTYPE_TUNNEL_IP |
3079 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3080 RTE_PTYPE_INNER_L4_TCP,
3081 [107] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3082 RTE_PTYPE_TUNNEL_IP |
3083 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3084 RTE_PTYPE_INNER_L4_SCTP,
3085 [108] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3086 RTE_PTYPE_TUNNEL_IP |
3087 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3088 RTE_PTYPE_INNER_L4_ICMP,
3090 /* IPv6 --> GRE/Teredo/VXLAN */
3091 [109] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3092 RTE_PTYPE_TUNNEL_GRENAT,
3094 /* IPv6 --> GRE/Teredo/VXLAN --> IPv4 */
3095 [110] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3096 RTE_PTYPE_TUNNEL_GRENAT |
3097 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3098 RTE_PTYPE_INNER_L4_FRAG,
3099 [111] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3100 RTE_PTYPE_TUNNEL_GRENAT |
3101 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3102 RTE_PTYPE_INNER_L4_NONFRAG,
3103 [112] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3104 RTE_PTYPE_TUNNEL_GRENAT |
3105 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3106 RTE_PTYPE_INNER_L4_UDP,
3107 /* [113] reserved */
3108 [114] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3109 RTE_PTYPE_TUNNEL_GRENAT |
3110 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3111 RTE_PTYPE_INNER_L4_TCP,
3112 [115] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3113 RTE_PTYPE_TUNNEL_GRENAT |
3114 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3115 RTE_PTYPE_INNER_L4_SCTP,
3116 [116] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3117 RTE_PTYPE_TUNNEL_GRENAT |
3118 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3119 RTE_PTYPE_INNER_L4_ICMP,
3121 /* IPv6 --> GRE/Teredo/VXLAN --> IPv6 */
3122 [117] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3123 RTE_PTYPE_TUNNEL_GRENAT |
3124 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3125 RTE_PTYPE_INNER_L4_FRAG,
3126 [118] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3127 RTE_PTYPE_TUNNEL_GRENAT |
3128 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3129 RTE_PTYPE_INNER_L4_NONFRAG,
3130 [119] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3131 RTE_PTYPE_TUNNEL_GRENAT |
3132 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3133 RTE_PTYPE_INNER_L4_UDP,
3134 /* [120] reserved */
3135 [121] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3136 RTE_PTYPE_TUNNEL_GRENAT |
3137 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3138 RTE_PTYPE_INNER_L4_TCP,
3139 [122] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3140 RTE_PTYPE_TUNNEL_GRENAT |
3141 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3142 RTE_PTYPE_INNER_L4_SCTP,
3143 [123] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3144 RTE_PTYPE_TUNNEL_GRENAT |
3145 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3146 RTE_PTYPE_INNER_L4_ICMP,
3148 /* IPv6 --> GRE/Teredo/VXLAN --> MAC */
3149 [124] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3150 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
3152 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
3153 [125] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3154 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3155 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3156 RTE_PTYPE_INNER_L4_FRAG,
3157 [126] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3158 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3159 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3160 RTE_PTYPE_INNER_L4_NONFRAG,
3161 [127] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3162 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3163 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3164 RTE_PTYPE_INNER_L4_UDP,
3165 /* [128] reserved */
3166 [129] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3167 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3168 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3169 RTE_PTYPE_INNER_L4_TCP,
3170 [130] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3171 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3172 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3173 RTE_PTYPE_INNER_L4_SCTP,
3174 [131] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3175 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3176 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3177 RTE_PTYPE_INNER_L4_ICMP,
3179 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
3180 [132] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3181 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3182 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3183 RTE_PTYPE_INNER_L4_FRAG,
3184 [133] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3185 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3186 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3187 RTE_PTYPE_INNER_L4_NONFRAG,
3188 [134] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3189 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3190 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3191 RTE_PTYPE_INNER_L4_UDP,
3192 /* [135] reserved */
3193 [136] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3194 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3195 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3196 RTE_PTYPE_INNER_L4_TCP,
3197 [137] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3198 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3199 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3200 RTE_PTYPE_INNER_L4_SCTP,
3201 [138] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3202 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3203 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3204 RTE_PTYPE_INNER_L4_ICMP,
3205 /* [139] - [299] reserved */
3208 [300] = RTE_PTYPE_L2_ETHER_PPPOE,
3209 [301] = RTE_PTYPE_L2_ETHER_PPPOE,
3211 /* PPPoE --> IPv4 */
3212 [302] = RTE_PTYPE_L2_ETHER_PPPOE |
3213 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3215 [303] = RTE_PTYPE_L2_ETHER_PPPOE |
3216 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3217 RTE_PTYPE_L4_NONFRAG,
3218 [304] = RTE_PTYPE_L2_ETHER_PPPOE |
3219 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3221 [305] = RTE_PTYPE_L2_ETHER_PPPOE |
3222 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3224 [306] = RTE_PTYPE_L2_ETHER_PPPOE |
3225 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3227 [307] = RTE_PTYPE_L2_ETHER_PPPOE |
3228 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3231 /* PPPoE --> IPv6 */
3232 [308] = RTE_PTYPE_L2_ETHER_PPPOE |
3233 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3235 [309] = RTE_PTYPE_L2_ETHER_PPPOE |
3236 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3237 RTE_PTYPE_L4_NONFRAG,
3238 [310] = RTE_PTYPE_L2_ETHER_PPPOE |
3239 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3241 [311] = RTE_PTYPE_L2_ETHER_PPPOE |
3242 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3244 [312] = RTE_PTYPE_L2_ETHER_PPPOE |
3245 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3247 [313] = RTE_PTYPE_L2_ETHER_PPPOE |
3248 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3250 /* [314] - [324] reserved */
3252 /* IPv4/IPv6 --> GTPC/GTPU */
3253 [325] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3254 RTE_PTYPE_TUNNEL_GTPC,
3255 [326] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3256 RTE_PTYPE_TUNNEL_GTPC,
3257 [327] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3258 RTE_PTYPE_TUNNEL_GTPC,
3259 [328] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3260 RTE_PTYPE_TUNNEL_GTPC,
3261 [329] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3262 RTE_PTYPE_TUNNEL_GTPU,
3263 [330] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3264 RTE_PTYPE_TUNNEL_GTPU,
3266 /* IPv4 --> GTPU --> IPv4 */
3267 [331] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3268 RTE_PTYPE_TUNNEL_GTPU |
3269 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3270 RTE_PTYPE_INNER_L4_FRAG,
3271 [332] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3272 RTE_PTYPE_TUNNEL_GTPU |
3273 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3274 RTE_PTYPE_INNER_L4_NONFRAG,
3275 [333] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3276 RTE_PTYPE_TUNNEL_GTPU |
3277 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3278 RTE_PTYPE_INNER_L4_UDP,
3279 [334] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3280 RTE_PTYPE_TUNNEL_GTPU |
3281 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3282 RTE_PTYPE_INNER_L4_TCP,
3283 [335] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3284 RTE_PTYPE_TUNNEL_GTPU |
3285 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3286 RTE_PTYPE_INNER_L4_ICMP,
3288 /* IPv6 --> GTPU --> IPv4 */
3289 [336] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3290 RTE_PTYPE_TUNNEL_GTPU |
3291 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3292 RTE_PTYPE_INNER_L4_FRAG,
3293 [337] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3294 RTE_PTYPE_TUNNEL_GTPU |
3295 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3296 RTE_PTYPE_INNER_L4_NONFRAG,
3297 [338] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3298 RTE_PTYPE_TUNNEL_GTPU |
3299 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3300 RTE_PTYPE_INNER_L4_UDP,
3301 [339] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3302 RTE_PTYPE_TUNNEL_GTPU |
3303 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3304 RTE_PTYPE_INNER_L4_TCP,
3305 [340] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3306 RTE_PTYPE_TUNNEL_GTPU |
3307 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3308 RTE_PTYPE_INNER_L4_ICMP,
3310 /* IPv4 --> GTPU --> IPv6 */
3311 [341] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3312 RTE_PTYPE_TUNNEL_GTPU |
3313 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3314 RTE_PTYPE_INNER_L4_FRAG,
3315 [342] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3316 RTE_PTYPE_TUNNEL_GTPU |
3317 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3318 RTE_PTYPE_INNER_L4_NONFRAG,
3319 [343] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3320 RTE_PTYPE_TUNNEL_GTPU |
3321 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3322 RTE_PTYPE_INNER_L4_UDP,
3323 [344] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3324 RTE_PTYPE_TUNNEL_GTPU |
3325 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3326 RTE_PTYPE_INNER_L4_TCP,
3327 [345] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3328 RTE_PTYPE_TUNNEL_GTPU |
3329 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3330 RTE_PTYPE_INNER_L4_ICMP,
3332 /* IPv6 --> GTPU --> IPv6 */
3333 [346] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3334 RTE_PTYPE_TUNNEL_GTPU |
3335 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3336 RTE_PTYPE_INNER_L4_FRAG,
3337 [347] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3338 RTE_PTYPE_TUNNEL_GTPU |
3339 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3340 RTE_PTYPE_INNER_L4_NONFRAG,
3341 [348] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3342 RTE_PTYPE_TUNNEL_GTPU |
3343 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3344 RTE_PTYPE_INNER_L4_UDP,
3345 [349] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3346 RTE_PTYPE_TUNNEL_GTPU |
3347 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3348 RTE_PTYPE_INNER_L4_TCP,
3349 [350] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3350 RTE_PTYPE_TUNNEL_GTPU |
3351 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3352 RTE_PTYPE_INNER_L4_ICMP,
3354 /* IPv4 --> UDP ECPRI */
3355 [372] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3357 [373] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3359 [374] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3361 [375] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3363 [376] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3365 [377] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3367 [378] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3369 [379] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3371 [380] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3373 [381] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3376 /* IPV6 --> UDP ECPRI */
3377 [382] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3379 [383] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3381 [384] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3383 [385] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3385 [386] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3387 [387] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3389 [388] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3391 [389] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3393 [390] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3395 [391] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3397 /* All others reserved */