drivers/net/iavf/iavf_rxtx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2017 Intel Corporation
   3  */
   4
   5 #include <stdio.h>
   6 #include <stdlib.h>
   7 #include <string.h>
   8 #include <errno.h>
   9 #include <stdint.h>
  10 #include <stdarg.h>
  11 #include <unistd.h>
  12 #include <inttypes.h>
  13 #include <sys/queue.h>
  14
  15 #include <rte_string_fns.h>
  16 #include <rte_memzone.h>
  17 #include <rte_mbuf.h>
  18 #include <rte_malloc.h>
  19 #include <rte_ether.h>
  20 #include <rte_ethdev_driver.h>
  21 #include <rte_tcp.h>
  22 #include <rte_sctp.h>
  23 #include <rte_udp.h>
  24 #include <rte_ip.h>
  25 #include <rte_net.h>
  26
  27 #include "iavf.h"
  28 #include "iavf_rxtx.h"
  29
  30 static inline int
  31 check_rx_thresh(uint16_t nb_desc, uint16_t thresh)
  32 {
  33         /* The following constraints must be satisfied:
  34          *   thresh < rxq->nb_rx_desc
  35          */
  36         if (thresh >= nb_desc) {
  37                 PMD_INIT_LOG(ERR, "rx_free_thresh (%u) must be less than %u",
  38                              thresh, nb_desc);
  39                 return -EINVAL;
  40         }
  41         return 0;
  42 }
  43
  44 static inline int
  45 check_tx_thresh(uint16_t nb_desc, uint16_t tx_rs_thresh,
  46                 uint16_t tx_free_thresh)
  47 {
  48         /* TX descriptors will have their RS bit set after tx_rs_thresh
  49          * descriptors have been used. The TX descriptor ring will be cleaned
  50          * after tx_free_thresh descriptors are used or if the number of
  51          * descriptors required to transmit a packet is greater than the
  52          * number of free TX descriptors.
  53          *
  54          * The following constraints must be satisfied:
  55          *  - tx_rs_thresh must be less than the size of the ring minus 2.
  56          *  - tx_free_thresh must be less than the size of the ring minus 3.
  57          *  - tx_rs_thresh must be less than or equal to tx_free_thresh.
  58          *  - tx_rs_thresh must be a divisor of the ring size.
  59          *
  60          * One descriptor in the TX ring is used as a sentinel to avoid a H/W
  61          * race condition, hence the maximum threshold constraints. When set
  62          * to zero use default values.
  63          */
  64         if (tx_rs_thresh >= (nb_desc - 2)) {
  65                 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be less than the "
  66                              "number of TX descriptors (%u) minus 2",
  67                              tx_rs_thresh, nb_desc);
  68                 return -EINVAL;
  69         }
  70         if (tx_free_thresh >= (nb_desc - 3)) {
  71                 PMD_INIT_LOG(ERR, "tx_free_thresh (%u) must be less than the "
  72                              "number of TX descriptors (%u) minus 3.",
  73                              tx_free_thresh, nb_desc);
  74                 return -EINVAL;
  75         }
  76         if (tx_rs_thresh > tx_free_thresh) {
  77                 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be less than or "
  78                              "equal to tx_free_thresh (%u).",
  79                              tx_rs_thresh, tx_free_thresh);
  80                 return -EINVAL;
  81         }
  82         if ((nb_desc % tx_rs_thresh) != 0) {
  83                 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be a divisor of the "
  84                              "number of TX descriptors (%u).",
  85                              tx_rs_thresh, nb_desc);
  86                 return -EINVAL;
  87         }
  88
  89         return 0;
  90 }
  91
  92 static inline bool
  93 check_rx_vec_allow(struct iavf_rx_queue *rxq)
  94 {
  95         if (rxq->rx_free_thresh >= IAVF_VPMD_RX_MAX_BURST &&
  96             rxq->nb_rx_desc % rxq->rx_free_thresh == 0) {
  97                 PMD_INIT_LOG(DEBUG, "Vector Rx can be enabled on this rxq.");
  98                 return true;
  99         }
 100
 101         PMD_INIT_LOG(DEBUG, "Vector Rx cannot be enabled on this rxq.");
 102         return false;
 103 }
 104
 105 static inline bool
 106 check_tx_vec_allow(struct iavf_tx_queue *txq)
 107 {
 108         if (!(txq->offloads & IAVF_NO_VECTOR_FLAGS) &&
 109             txq->rs_thresh >= IAVF_VPMD_TX_MAX_BURST &&
 110             txq->rs_thresh <= IAVF_VPMD_TX_MAX_FREE_BUF) {
 111                 PMD_INIT_LOG(DEBUG, "Vector tx can be enabled on this txq.");
 112                 return true;
 113         }
 114         PMD_INIT_LOG(DEBUG, "Vector Tx cannot be enabled on this txq.");
 115         return false;
 116 }
 117
 118 static inline bool
 119 check_rx_bulk_allow(struct iavf_rx_queue *rxq)
 120 {
 121         int ret = true;
 122
 123         if (!(rxq->rx_free_thresh >= IAVF_RX_MAX_BURST)) {
 124                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 125                              "rxq->rx_free_thresh=%d, "
 126                              "IAVF_RX_MAX_BURST=%d",
 127                              rxq->rx_free_thresh, IAVF_RX_MAX_BURST);
 128                 ret = false;
 129         } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
 130                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 131                              "rxq->nb_rx_desc=%d, "
 132                              "rxq->rx_free_thresh=%d",
 133                              rxq->nb_rx_desc, rxq->rx_free_thresh);
 134                 ret = false;
 135         }
 136         return ret;
 137 }
 138
 139 static inline void
 140 reset_rx_queue(struct iavf_rx_queue *rxq)
 141 {
 142         uint16_t len;
 143         uint32_t i;
 144
 145         if (!rxq)
 146                 return;
 147
 148         len = rxq->nb_rx_desc + IAVF_RX_MAX_BURST;
 149
 150         for (i = 0; i < len * sizeof(union iavf_rx_desc); i++)
 151                 ((volatile char *)rxq->rx_ring)[i] = 0;
 152
 153         memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
 154
 155         for (i = 0; i < IAVF_RX_MAX_BURST; i++)
 156                 rxq->sw_ring[rxq->nb_rx_desc + i] = &rxq->fake_mbuf;
 157
 158         /* for rx bulk */
 159         rxq->rx_nb_avail = 0;
 160         rxq->rx_next_avail = 0;
 161         rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
 162
 163         rxq->rx_tail = 0;
 164         rxq->nb_rx_hold = 0;
 165         rxq->pkt_first_seg = NULL;
 166         rxq->pkt_last_seg = NULL;
 167 }
 168
 169 static inline void
 170 reset_tx_queue(struct iavf_tx_queue *txq)
 171 {
 172         struct iavf_tx_entry *txe;
 173         uint32_t i, size;
 174         uint16_t prev;
 175
 176         if (!txq) {
 177                 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
 178                 return;
 179         }
 180
 181         txe = txq->sw_ring;
 182         size = sizeof(struct iavf_tx_desc) * txq->nb_tx_desc;
 183         for (i = 0; i < size; i++)
 184                 ((volatile char *)txq->tx_ring)[i] = 0;
 185
 186         prev = (uint16_t)(txq->nb_tx_desc - 1);
 187         for (i = 0; i < txq->nb_tx_desc; i++) {
 188                 txq->tx_ring[i].cmd_type_offset_bsz =
 189                         rte_cpu_to_le_64(IAVF_TX_DESC_DTYPE_DESC_DONE);
 190                 txe[i].mbuf =  NULL;
 191                 txe[i].last_id = i;
 192                 txe[prev].next_id = i;
 193                 prev = i;
 194         }
 195
 196         txq->tx_tail = 0;
 197         txq->nb_used = 0;
 198
 199         txq->last_desc_cleaned = txq->nb_tx_desc - 1;
 200         txq->nb_free = txq->nb_tx_desc - 1;
 201
 202         txq->next_dd = txq->rs_thresh - 1;
 203         txq->next_rs = txq->rs_thresh - 1;
 204 }
 205
 206 static int
 207 alloc_rxq_mbufs(struct iavf_rx_queue *rxq)
 208 {
 209         volatile union iavf_rx_desc *rxd;
 210         struct rte_mbuf *mbuf = NULL;
 211         uint64_t dma_addr;
 212         uint16_t i;
 213
 214         for (i = 0; i < rxq->nb_rx_desc; i++) {
 215                 mbuf = rte_mbuf_raw_alloc(rxq->mp);
 216                 if (unlikely(!mbuf)) {
 217                         PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
 218                         return -ENOMEM;
 219                 }
 220
 221                 rte_mbuf_refcnt_set(mbuf, 1);
 222                 mbuf->next = NULL;
 223                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
 224                 mbuf->nb_segs = 1;
 225                 mbuf->port = rxq->port_id;
 226
 227                 dma_addr =
 228                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
 229
 230                 rxd = &rxq->rx_ring[i];
 231                 rxd->read.pkt_addr = dma_addr;
 232                 rxd->read.hdr_addr = 0;
 233 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
 234                 rxd->read.rsvd1 = 0;
 235                 rxd->read.rsvd2 = 0;
 236 #endif
 237
 238                 rxq->sw_ring[i] = mbuf;
 239         }
 240
 241         return 0;
 242 }
 243
 244 static inline void
 245 release_rxq_mbufs(struct iavf_rx_queue *rxq)
 246 {
 247         uint16_t i;
 248
 249         if (!rxq->sw_ring)
 250                 return;
 251
 252         for (i = 0; i < rxq->nb_rx_desc; i++) {
 253                 if (rxq->sw_ring[i]) {
 254                         rte_pktmbuf_free_seg(rxq->sw_ring[i]);
 255                         rxq->sw_ring[i] = NULL;
 256                 }
 257         }
 258
 259         /* for rx bulk */
 260         if (rxq->rx_nb_avail == 0)
 261                 return;
 262         for (i = 0; i < rxq->rx_nb_avail; i++) {
 263                 struct rte_mbuf *mbuf;
 264
 265                 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
 266                 rte_pktmbuf_free_seg(mbuf);
 267         }
 268         rxq->rx_nb_avail = 0;
 269 }
 270
 271 static inline void
 272 release_txq_mbufs(struct iavf_tx_queue *txq)
 273 {
 274         uint16_t i;
 275
 276         if (!txq || !txq->sw_ring) {
 277                 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
 278                 return;
 279         }
 280
 281         for (i = 0; i < txq->nb_tx_desc; i++) {
 282                 if (txq->sw_ring[i].mbuf) {
 283                         rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
 284                         txq->sw_ring[i].mbuf = NULL;
 285                 }
 286         }
 287 }
 288
 289 static const struct iavf_rxq_ops def_rxq_ops = {
 290         .release_mbufs = release_rxq_mbufs,
 291 };
 292
 293 static const struct iavf_txq_ops def_txq_ops = {
 294         .release_mbufs = release_txq_mbufs,
 295 };
 296
 297 int
 298 iavf_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 299                        uint16_t nb_desc, unsigned int socket_id,
 300                        const struct rte_eth_rxconf *rx_conf,
 301                        struct rte_mempool *mp)
 302 {
 303         struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 304         struct iavf_adapter *ad =
 305                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 306         struct iavf_info *vf =
 307                 IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 308         struct iavf_vsi *vsi = &vf->vsi;
 309         struct iavf_rx_queue *rxq;
 310         const struct rte_memzone *mz;
 311         uint32_t ring_size;
 312         uint16_t len;
 313         uint16_t rx_free_thresh;
 314
 315         PMD_INIT_FUNC_TRACE();
 316
 317         if (nb_desc % IAVF_ALIGN_RING_DESC != 0 ||
 318             nb_desc > IAVF_MAX_RING_DESC ||
 319             nb_desc < IAVF_MIN_RING_DESC) {
 320                 PMD_INIT_LOG(ERR, "Number (%u) of receive descriptors is "
 321                              "invalid", nb_desc);
 322                 return -EINVAL;
 323         }
 324
 325         /* Check free threshold */
 326         rx_free_thresh = (rx_conf->rx_free_thresh == 0) ?
 327                          IAVF_DEFAULT_RX_FREE_THRESH :
 328                          rx_conf->rx_free_thresh;
 329         if (check_rx_thresh(nb_desc, rx_free_thresh) != 0)
 330                 return -EINVAL;
 331
 332         /* Free memory if needed */
 333         if (dev->data->rx_queues[queue_idx]) {
 334                 iavf_dev_rx_queue_release(dev->data->rx_queues[queue_idx]);
 335                 dev->data->rx_queues[queue_idx] = NULL;
 336         }
 337
 338         /* Allocate the rx queue data structure */
 339         rxq = rte_zmalloc_socket("iavf rxq",
 340                                  sizeof(struct iavf_rx_queue),
 341                                  RTE_CACHE_LINE_SIZE,
 342                                  socket_id);
 343         if (!rxq) {
 344                 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
 345                              "rx queue data structure");
 346                 return -ENOMEM;
 347         }
 348
 349         if (vf->vf_res->vf_cap_flags &
 350             VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC &&
 351             vf->supported_rxdid & BIT(IAVF_RXDID_COMMS_OVS_1)) {
 352                 rxq->rxdid = IAVF_RXDID_COMMS_OVS_1;
 353         } else {
 354                 rxq->rxdid = IAVF_RXDID_LEGACY_1;
 355         }
 356
 357         rxq->mp = mp;
 358         rxq->nb_rx_desc = nb_desc;
 359         rxq->rx_free_thresh = rx_free_thresh;
 360         rxq->queue_id = queue_idx;
 361         rxq->port_id = dev->data->port_id;
 362         rxq->crc_len = 0; /* crc stripping by default */
 363         rxq->rx_deferred_start = rx_conf->rx_deferred_start;
 364         rxq->rx_hdr_len = 0;
 365         rxq->vsi = vsi;
 366
 367         len = rte_pktmbuf_data_room_size(rxq->mp) - RTE_PKTMBUF_HEADROOM;
 368         rxq->rx_buf_len = RTE_ALIGN(len, (1 << IAVF_RXQ_CTX_DBUFF_SHIFT));
 369
 370         /* Allocate the software ring. */
 371         len = nb_desc + IAVF_RX_MAX_BURST;
 372         rxq->sw_ring =
 373                 rte_zmalloc_socket("iavf rx sw ring",
 374                                    sizeof(struct rte_mbuf *) * len,
 375                                    RTE_CACHE_LINE_SIZE,
 376                                    socket_id);
 377         if (!rxq->sw_ring) {
 378                 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW ring");
 379                 rte_free(rxq);
 380                 return -ENOMEM;
 381         }
 382
 383         /* Allocate the maximun number of RX ring hardware descriptor with
 384          * a liitle more to support bulk allocate.
 385          */
 386         len = IAVF_MAX_RING_DESC + IAVF_RX_MAX_BURST;
 387         ring_size = RTE_ALIGN(len * sizeof(union iavf_rx_desc),
 388                               IAVF_DMA_MEM_ALIGN);
 389         mz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
 390                                       ring_size, IAVF_RING_BASE_ALIGN,
 391                                       socket_id);
 392         if (!mz) {
 393                 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for RX");
 394                 rte_free(rxq->sw_ring);
 395                 rte_free(rxq);
 396                 return -ENOMEM;
 397         }
 398         /* Zero all the descriptors in the ring. */
 399         memset(mz->addr, 0, ring_size);
 400         rxq->rx_ring_phys_addr = mz->iova;
 401         rxq->rx_ring = (union iavf_rx_desc *)mz->addr;
 402
 403         rxq->mz = mz;
 404         reset_rx_queue(rxq);
 405         rxq->q_set = true;
 406         dev->data->rx_queues[queue_idx] = rxq;
 407         rxq->qrx_tail = hw->hw_addr + IAVF_QRX_TAIL1(rxq->queue_id);
 408         rxq->ops = &def_rxq_ops;
 409
 410         if (check_rx_bulk_allow(rxq) == true) {
 411                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
 412                              "satisfied. Rx Burst Bulk Alloc function will be "
 413                              "used on port=%d, queue=%d.",
 414                              rxq->port_id, rxq->queue_id);
 415         } else {
 416                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
 417                              "not satisfied, Scattered Rx is requested "
 418                              "on port=%d, queue=%d.",
 419                              rxq->port_id, rxq->queue_id);
 420                 ad->rx_bulk_alloc_allowed = false;
 421         }
 422
 423         if (check_rx_vec_allow(rxq) == false)
 424                 ad->rx_vec_allowed = false;
 425
 426         return 0;
 427 }
 428
 429 int
 430 iavf_dev_tx_queue_setup(struct rte_eth_dev *dev,
 431                        uint16_t queue_idx,
 432                        uint16_t nb_desc,
 433                        unsigned int socket_id,
 434                        const struct rte_eth_txconf *tx_conf)
 435 {
 436         struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 437         struct iavf_tx_queue *txq;
 438         const struct rte_memzone *mz;
 439         uint32_t ring_size;
 440         uint16_t tx_rs_thresh, tx_free_thresh;
 441         uint64_t offloads;
 442
 443         PMD_INIT_FUNC_TRACE();
 444
 445         offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
 446
 447         if (nb_desc % IAVF_ALIGN_RING_DESC != 0 ||
 448             nb_desc > IAVF_MAX_RING_DESC ||
 449             nb_desc < IAVF_MIN_RING_DESC) {
 450                 PMD_INIT_LOG(ERR, "Number (%u) of transmit descriptors is "
 451                             "invalid", nb_desc);
 452                 return -EINVAL;
 453         }
 454
 455         tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
 456                 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
 457         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
 458                 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
 459         check_tx_thresh(nb_desc, tx_rs_thresh, tx_rs_thresh);
 460
 461         /* Free memory if needed. */
 462         if (dev->data->tx_queues[queue_idx]) {
 463                 iavf_dev_tx_queue_release(dev->data->tx_queues[queue_idx]);
 464                 dev->data->tx_queues[queue_idx] = NULL;
 465         }
 466
 467         /* Allocate the TX queue data structure. */
 468         txq = rte_zmalloc_socket("iavf txq",
 469                                  sizeof(struct iavf_tx_queue),
 470                                  RTE_CACHE_LINE_SIZE,
 471                                  socket_id);
 472         if (!txq) {
 473                 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
 474                              "tx queue structure");
 475                 return -ENOMEM;
 476         }
 477
 478         txq->nb_tx_desc = nb_desc;
 479         txq->rs_thresh = tx_rs_thresh;
 480         txq->free_thresh = tx_free_thresh;
 481         txq->queue_id = queue_idx;
 482         txq->port_id = dev->data->port_id;
 483         txq->offloads = offloads;
 484         txq->tx_deferred_start = tx_conf->tx_deferred_start;
 485
 486         /* Allocate software ring */
 487         txq->sw_ring =
 488                 rte_zmalloc_socket("iavf tx sw ring",
 489                                    sizeof(struct iavf_tx_entry) * nb_desc,
 490                                    RTE_CACHE_LINE_SIZE,
 491                                    socket_id);
 492         if (!txq->sw_ring) {
 493                 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW TX ring");
 494                 rte_free(txq);
 495                 return -ENOMEM;
 496         }
 497
 498         /* Allocate TX hardware ring descriptors. */
 499         ring_size = sizeof(struct iavf_tx_desc) * IAVF_MAX_RING_DESC;
 500         ring_size = RTE_ALIGN(ring_size, IAVF_DMA_MEM_ALIGN);
 501         mz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
 502                                       ring_size, IAVF_RING_BASE_ALIGN,
 503                                       socket_id);
 504         if (!mz) {
 505                 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for TX");
 506                 rte_free(txq->sw_ring);
 507                 rte_free(txq);
 508                 return -ENOMEM;
 509         }
 510         txq->tx_ring_phys_addr = mz->iova;
 511         txq->tx_ring = (struct iavf_tx_desc *)mz->addr;
 512
 513         txq->mz = mz;
 514         reset_tx_queue(txq);
 515         txq->q_set = true;
 516         dev->data->tx_queues[queue_idx] = txq;
 517         txq->qtx_tail = hw->hw_addr + IAVF_QTX_TAIL1(queue_idx);
 518         txq->ops = &def_txq_ops;
 519
 520         if (check_tx_vec_allow(txq) == false) {
 521                 struct iavf_adapter *ad =
 522                         IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 523                 ad->tx_vec_allowed = false;
 524         }
 525
 526         return 0;
 527 }
 528
 529 int
 530 iavf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 531 {
 532         struct iavf_adapter *adapter =
 533                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 534         struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 535         struct iavf_rx_queue *rxq;
 536         int err = 0;
 537
 538         PMD_DRV_FUNC_TRACE();
 539
 540         if (rx_queue_id >= dev->data->nb_rx_queues)
 541                 return -EINVAL;
 542
 543         rxq = dev->data->rx_queues[rx_queue_id];
 544
 545         err = alloc_rxq_mbufs(rxq);
 546         if (err) {
 547                 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
 548                 return err;
 549         }
 550
 551         rte_wmb();
 552
 553         /* Init the RX tail register. */
 554         IAVF_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 555         IAVF_WRITE_FLUSH(hw);
 556
 557         /* Ready to switch the queue on */
 558         err = iavf_switch_queue(adapter, rx_queue_id, true, true);
 559         if (err)
 560                 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
 561                             rx_queue_id);
 562         else
 563                 dev->data->rx_queue_state[rx_queue_id] =
 564                         RTE_ETH_QUEUE_STATE_STARTED;
 565
 566         return err;
 567 }
 568
 569 int
 570 iavf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 571 {
 572         struct iavf_adapter *adapter =
 573                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 574         struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 575         struct iavf_tx_queue *txq;
 576         int err = 0;
 577
 578         PMD_DRV_FUNC_TRACE();
 579
 580         if (tx_queue_id >= dev->data->nb_tx_queues)
 581                 return -EINVAL;
 582
 583         txq = dev->data->tx_queues[tx_queue_id];
 584
 585         /* Init the RX tail register. */
 586         IAVF_PCI_REG_WRITE(txq->qtx_tail, 0);
 587         IAVF_WRITE_FLUSH(hw);
 588
 589         /* Ready to switch the queue on */
 590         err = iavf_switch_queue(adapter, tx_queue_id, false, true);
 591
 592         if (err)
 593                 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
 594                             tx_queue_id);
 595         else
 596                 dev->data->tx_queue_state[tx_queue_id] =
 597                         RTE_ETH_QUEUE_STATE_STARTED;
 598
 599         return err;
 600 }
 601
 602 int
 603 iavf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 604 {
 605         struct iavf_adapter *adapter =
 606                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 607         struct iavf_rx_queue *rxq;
 608         int err;
 609
 610         PMD_DRV_FUNC_TRACE();
 611
 612         if (rx_queue_id >= dev->data->nb_rx_queues)
 613                 return -EINVAL;
 614
 615         err = iavf_switch_queue(adapter, rx_queue_id, true, false);
 616         if (err) {
 617                 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
 618                             rx_queue_id);
 619                 return err;
 620         }
 621
 622         rxq = dev->data->rx_queues[rx_queue_id];
 623         rxq->ops->release_mbufs(rxq);
 624         reset_rx_queue(rxq);
 625         dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 626
 627         return 0;
 628 }
 629
 630 int
 631 iavf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 632 {
 633         struct iavf_adapter *adapter =
 634                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 635         struct iavf_tx_queue *txq;
 636         int err;
 637
 638         PMD_DRV_FUNC_TRACE();
 639
 640         if (tx_queue_id >= dev->data->nb_tx_queues)
 641                 return -EINVAL;
 642
 643         err = iavf_switch_queue(adapter, tx_queue_id, false, false);
 644         if (err) {
 645                 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u off",
 646                             tx_queue_id);
 647                 return err;
 648         }
 649
 650         txq = dev->data->tx_queues[tx_queue_id];
 651         txq->ops->release_mbufs(txq);
 652         reset_tx_queue(txq);
 653         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 654
 655         return 0;
 656 }
 657
 658 void
 659 iavf_dev_rx_queue_release(void *rxq)
 660 {
 661         struct iavf_rx_queue *q = (struct iavf_rx_queue *)rxq;
 662
 663         if (!q)
 664                 return;
 665
 666         q->ops->release_mbufs(q);
 667         rte_free(q->sw_ring);
 668         rte_memzone_free(q->mz);
 669         rte_free(q);
 670 }
 671
 672 void
 673 iavf_dev_tx_queue_release(void *txq)
 674 {
 675         struct iavf_tx_queue *q = (struct iavf_tx_queue *)txq;
 676
 677         if (!q)
 678                 return;
 679
 680         q->ops->release_mbufs(q);
 681         rte_free(q->sw_ring);
 682         rte_memzone_free(q->mz);
 683         rte_free(q);
 684 }
 685
 686 void
 687 iavf_stop_queues(struct rte_eth_dev *dev)
 688 {
 689         struct iavf_adapter *adapter =
 690                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 691         struct iavf_rx_queue *rxq;
 692         struct iavf_tx_queue *txq;
 693         int ret, i;
 694
 695         /* Stop All queues */
 696         ret = iavf_disable_queues(adapter);
 697         if (ret)
 698                 PMD_DRV_LOG(WARNING, "Fail to stop queues");
 699
 700         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 701                 txq = dev->data->tx_queues[i];
 702                 if (!txq)
 703                         continue;
 704                 txq->ops->release_mbufs(txq);
 705                 reset_tx_queue(txq);
 706                 dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED;
 707         }
 708         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 709                 rxq = dev->data->rx_queues[i];
 710                 if (!rxq)
 711                         continue;
 712                 rxq->ops->release_mbufs(rxq);
 713                 reset_rx_queue(rxq);
 714                 dev->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED;
 715         }
 716 }
 717
 718 static inline void
 719 iavf_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union iavf_rx_desc *rxdp)
 720 {
 721         if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
 722                 (1 << IAVF_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
 723                 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
 724                 mb->vlan_tci =
 725                         rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
 726         } else {
 727                 mb->vlan_tci = 0;
 728         }
 729 }
 730
 731 static inline void
 732 iavf_flex_rxd_to_vlan_tci(struct rte_mbuf *mb,
 733                           volatile union iavf_rx_flex_desc *rxdp)
 734 {
 735         if (rte_le_to_cpu_64(rxdp->wb.status_error0) &
 736                 (1 << IAVF_RX_FLEX_DESC_STATUS0_L2TAG1P_S)) {
 737                 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
 738                 mb->vlan_tci =
 739                         rte_le_to_cpu_16(rxdp->wb.l2tag1);
 740         } else {
 741                 mb->vlan_tci = 0;
 742         }
 743 }
 744
 745 /* Translate the rx descriptor status and error fields to pkt flags */
 746 static inline uint64_t
 747 iavf_rxd_to_pkt_flags(uint64_t qword)
 748 {
 749         uint64_t flags;
 750         uint64_t error_bits = (qword >> IAVF_RXD_QW1_ERROR_SHIFT);
 751
 752 #define IAVF_RX_ERR_BITS 0x3f
 753
 754         /* Check if RSS_HASH */
 755         flags = (((qword >> IAVF_RX_DESC_STATUS_FLTSTAT_SHIFT) &
 756                                         IAVF_RX_DESC_FLTSTAT_RSS_HASH) ==
 757                         IAVF_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;
 758
 759         /* Check if FDIR Match */
 760         flags |= (qword & (1 << IAVF_RX_DESC_STATUS_FLM_SHIFT) ?
 761                                 PKT_RX_FDIR : 0);
 762
 763         if (likely((error_bits & IAVF_RX_ERR_BITS) == 0)) {
 764                 flags |= (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD);
 765                 return flags;
 766         }
 767
 768         if (unlikely(error_bits & (1 << IAVF_RX_DESC_ERROR_IPE_SHIFT)))
 769                 flags |= PKT_RX_IP_CKSUM_BAD;
 770         else
 771                 flags |= PKT_RX_IP_CKSUM_GOOD;
 772
 773         if (unlikely(error_bits & (1 << IAVF_RX_DESC_ERROR_L4E_SHIFT)))
 774                 flags |= PKT_RX_L4_CKSUM_BAD;
 775         else
 776                 flags |= PKT_RX_L4_CKSUM_GOOD;
 777
 778         /* TODO: Oversize error bit is not processed here */
 779
 780         return flags;
 781 }
 782
 783 static inline uint64_t
 784 iavf_rxd_build_fdir(volatile union iavf_rx_desc *rxdp, struct rte_mbuf *mb)
 785 {
 786         uint64_t flags = 0;
 787 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
 788         uint16_t flexbh;
 789
 790         flexbh = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
 791                 IAVF_RX_DESC_EXT_STATUS_FLEXBH_SHIFT) &
 792                 IAVF_RX_DESC_EXT_STATUS_FLEXBH_MASK;
 793
 794         if (flexbh == IAVF_RX_DESC_EXT_STATUS_FLEXBH_FD_ID) {
 795                 mb->hash.fdir.hi =
 796                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.fd_id);
 797                 flags |= PKT_RX_FDIR_ID;
 798         }
 799 #else
 800         mb->hash.fdir.hi =
 801                 rte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.fd_id);
 802         flags |= PKT_RX_FDIR_ID;
 803 #endif
 804         return flags;
 805 }
 806
 807
 808 /* Translate the rx flex descriptor status to pkt flags */
 809 static inline void
 810 iavf_rxd_to_pkt_fields(struct rte_mbuf *mb,
 811                        volatile union iavf_rx_flex_desc *rxdp)
 812 {
 813         volatile struct iavf_32b_rx_flex_desc_comms_ovs *desc =
 814                         (volatile struct iavf_32b_rx_flex_desc_comms_ovs *)rxdp;
 815 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
 816         uint16_t stat_err;
 817
 818         stat_err = rte_le_to_cpu_16(desc->status_error0);
 819         if (likely(stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
 820                 mb->ol_flags |= PKT_RX_RSS_HASH;
 821                 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
 822         }
 823 #endif
 824
 825         if (desc->flow_id != 0xFFFFFFFF) {
 826                 mb->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
 827                 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
 828         }
 829 }
 830
 831 #define IAVF_RX_FLEX_ERR0_BITS  \
 832         ((1 << IAVF_RX_FLEX_DESC_STATUS0_HBO_S) |       \
 833          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_IPE_S) |  \
 834          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_L4E_S) |  \
 835          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S) | \
 836          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S) |        \
 837          (1 << IAVF_RX_FLEX_DESC_STATUS0_RXE_S))
 838
 839 /* Rx L3/L4 checksum */
 840 static inline uint64_t
 841 iavf_flex_rxd_error_to_pkt_flags(uint16_t stat_err0)
 842 {
 843         uint64_t flags = 0;
 844
 845         /* check if HW has decoded the packet and checksum */
 846         if (unlikely(!(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_L3L4P_S))))
 847                 return 0;
 848
 849         if (likely(!(stat_err0 & IAVF_RX_FLEX_ERR0_BITS))) {
 850                 flags |= (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD);
 851                 return flags;
 852         }
 853
 854         if (unlikely(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_IPE_S)))
 855                 flags |= PKT_RX_IP_CKSUM_BAD;
 856         else
 857                 flags |= PKT_RX_IP_CKSUM_GOOD;
 858
 859         if (unlikely(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_L4E_S)))
 860                 flags |= PKT_RX_L4_CKSUM_BAD;
 861         else
 862                 flags |= PKT_RX_L4_CKSUM_GOOD;
 863
 864         if (unlikely(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S)))
 865                 flags |= PKT_RX_EIP_CKSUM_BAD;
 866
 867         return flags;
 868 }
 869
 870 /* If the number of free RX descriptors is greater than the RX free
 871  * threshold of the queue, advance the Receive Descriptor Tail (RDT)
 872  * register. Update the RDT with the value of the last processed RX
 873  * descriptor minus 1, to guarantee that the RDT register is never
 874  * equal to the RDH register, which creates a "full" ring situation
 875  * from the hardware point of view.
 876  */
 877 static inline void
 878 iavf_update_rx_tail(struct iavf_rx_queue *rxq, uint16_t nb_hold, uint16_t rx_id)
 879 {
 880         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
 881
 882         if (nb_hold > rxq->rx_free_thresh) {
 883                 PMD_RX_LOG(DEBUG,
 884                            "port_id=%u queue_id=%u rx_tail=%u nb_hold=%u",
 885                            rxq->port_id, rxq->queue_id, rx_id, nb_hold);
 886                 rx_id = (uint16_t)((rx_id == 0) ?
 887                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
 888                 IAVF_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
 889                 nb_hold = 0;
 890         }
 891         rxq->nb_rx_hold = nb_hold;
 892 }
 893
 894 /* implement recv_pkts */
 895 uint16_t
 896 iavf_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 897 {
 898         volatile union iavf_rx_desc *rx_ring;
 899         volatile union iavf_rx_desc *rxdp;
 900         struct iavf_rx_queue *rxq;
 901         union iavf_rx_desc rxd;
 902         struct rte_mbuf *rxe;
 903         struct rte_eth_dev *dev;
 904         struct rte_mbuf *rxm;
 905         struct rte_mbuf *nmb;
 906         uint16_t nb_rx;
 907         uint32_t rx_status;
 908         uint64_t qword1;
 909         uint16_t rx_packet_len;
 910         uint16_t rx_id, nb_hold;
 911         uint64_t dma_addr;
 912         uint64_t pkt_flags;
 913         const uint32_t *ptype_tbl;
 914
 915         nb_rx = 0;
 916         nb_hold = 0;
 917         rxq = rx_queue;
 918         rx_id = rxq->rx_tail;
 919         rx_ring = rxq->rx_ring;
 920         ptype_tbl = rxq->vsi->adapter->ptype_tbl;
 921
 922         while (nb_rx < nb_pkts) {
 923                 rxdp = &rx_ring[rx_id];
 924                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 925                 rx_status = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
 926                             IAVF_RXD_QW1_STATUS_SHIFT;
 927
 928                 /* Check the DD bit first */
 929                 if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)))
 930                         break;
 931                 IAVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
 932
 933                 nmb = rte_mbuf_raw_alloc(rxq->mp);
 934                 if (unlikely(!nmb)) {
 935                         dev = &rte_eth_devices[rxq->port_id];
 936                         dev->data->rx_mbuf_alloc_failed++;
 937                         PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
 938                                    "queue_id=%u", rxq->port_id, rxq->queue_id);
 939                         break;
 940                 }
 941
 942                 rxd = *rxdp;
 943                 nb_hold++;
 944                 rxe = rxq->sw_ring[rx_id];
 945                 rx_id++;
 946                 if (unlikely(rx_id == rxq->nb_rx_desc))
 947                         rx_id = 0;
 948
 949                 /* Prefetch next mbuf */
 950                 rte_prefetch0(rxq->sw_ring[rx_id]);
 951
 952                 /* When next RX descriptor is on a cache line boundary,
 953                  * prefetch the next 4 RX descriptors and next 8 pointers
 954                  * to mbufs.
 955                  */
 956                 if ((rx_id & 0x3) == 0) {
 957                         rte_prefetch0(&rx_ring[rx_id]);
 958                         rte_prefetch0(rxq->sw_ring[rx_id]);
 959                 }
 960                 rxm = rxe;
 961                 dma_addr =
 962                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
 963                 rxdp->read.hdr_addr = 0;
 964                 rxdp->read.pkt_addr = dma_addr;
 965
 966                 rx_packet_len = ((qword1 & IAVF_RXD_QW1_LENGTH_PBUF_MASK) >>
 967                                 IAVF_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
 968
 969                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
 970                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
 971                 rxm->nb_segs = 1;
 972                 rxm->next = NULL;
 973                 rxm->pkt_len = rx_packet_len;
 974                 rxm->data_len = rx_packet_len;
 975                 rxm->port = rxq->port_id;
 976                 rxm->ol_flags = 0;
 977                 iavf_rxd_to_vlan_tci(rxm, &rxd);
 978                 pkt_flags = iavf_rxd_to_pkt_flags(qword1);
 979                 rxm->packet_type =
 980                         ptype_tbl[(uint8_t)((qword1 &
 981                         IAVF_RXD_QW1_PTYPE_MASK) >> IAVF_RXD_QW1_PTYPE_SHIFT)];
 982
 983                 if (pkt_flags & PKT_RX_RSS_HASH)
 984                         rxm->hash.rss =
 985                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
 986
 987                 if (pkt_flags & PKT_RX_FDIR)
 988                         pkt_flags |= iavf_rxd_build_fdir(&rxd, rxm);
 989
 990                 rxm->ol_flags |= pkt_flags;
 991
 992                 rx_pkts[nb_rx++] = rxm;
 993         }
 994         rxq->rx_tail = rx_id;
 995
 996         iavf_update_rx_tail(rxq, nb_hold, rx_id);
 997
 998         return nb_rx;
 999 }
1000
1001 /* implement recv_pkts for flexible Rx descriptor */
1002 uint16_t
1003 iavf_recv_pkts_flex_rxd(void *rx_queue,
1004                         struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1005 {
1006         volatile union iavf_rx_desc *rx_ring;
1007         volatile union iavf_rx_flex_desc *rxdp;
1008         struct iavf_rx_queue *rxq;
1009         union iavf_rx_flex_desc rxd;
1010         struct rte_mbuf *rxe;
1011         struct rte_eth_dev *dev;
1012         struct rte_mbuf *rxm;
1013         struct rte_mbuf *nmb;
1014         uint16_t nb_rx;
1015         uint16_t rx_stat_err0;
1016         uint16_t rx_packet_len;
1017         uint16_t rx_id, nb_hold;
1018         uint64_t dma_addr;
1019         uint64_t pkt_flags;
1020         const uint32_t *ptype_tbl;
1021
1022         nb_rx = 0;
1023         nb_hold = 0;
1024         rxq = rx_queue;
1025         rx_id = rxq->rx_tail;
1026         rx_ring = rxq->rx_ring;
1027         ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1028
1029         while (nb_rx < nb_pkts) {
1030                 rxdp = (volatile union iavf_rx_flex_desc *)&rx_ring[rx_id];
1031                 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1032
1033                 /* Check the DD bit first */
1034                 if (!(rx_stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S)))
1035                         break;
1036                 IAVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
1037
1038                 nmb = rte_mbuf_raw_alloc(rxq->mp);
1039                 if (unlikely(!nmb)) {
1040                         dev = &rte_eth_devices[rxq->port_id];
1041                         dev->data->rx_mbuf_alloc_failed++;
1042                         PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1043                                    "queue_id=%u", rxq->port_id, rxq->queue_id);
1044                         break;
1045                 }
1046
1047                 rxd = *rxdp;
1048                 nb_hold++;
1049                 rxe = rxq->sw_ring[rx_id];
1050                 rx_id++;
1051                 if (unlikely(rx_id == rxq->nb_rx_desc))
1052                         rx_id = 0;
1053
1054                 /* Prefetch next mbuf */
1055                 rte_prefetch0(rxq->sw_ring[rx_id]);
1056
1057                 /* When next RX descriptor is on a cache line boundary,
1058                  * prefetch the next 4 RX descriptors and next 8 pointers
1059                  * to mbufs.
1060                  */
1061                 if ((rx_id & 0x3) == 0) {
1062                         rte_prefetch0(&rx_ring[rx_id]);
1063                         rte_prefetch0(rxq->sw_ring[rx_id]);
1064                 }
1065                 rxm = rxe;
1066                 dma_addr =
1067                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1068                 rxdp->read.hdr_addr = 0;
1069                 rxdp->read.pkt_addr = dma_addr;
1070
1071                 rx_packet_len = (rte_le_to_cpu_16(rxd.wb.pkt_len) &
1072                                 IAVF_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
1073
1074                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1075                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
1076                 rxm->nb_segs = 1;
1077                 rxm->next = NULL;
1078                 rxm->pkt_len = rx_packet_len;
1079                 rxm->data_len = rx_packet_len;
1080                 rxm->port = rxq->port_id;
1081                 rxm->ol_flags = 0;
1082                 rxm->packet_type = ptype_tbl[IAVF_RX_FLEX_DESC_PTYPE_M &
1083                         rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
1084                 iavf_flex_rxd_to_vlan_tci(rxm, &rxd);
1085                 iavf_rxd_to_pkt_fields(rxm, &rxd);
1086                 pkt_flags = iavf_flex_rxd_error_to_pkt_flags(rx_stat_err0);
1087                 rxm->ol_flags |= pkt_flags;
1088
1089                 rx_pkts[nb_rx++] = rxm;
1090         }
1091         rxq->rx_tail = rx_id;
1092
1093         iavf_update_rx_tail(rxq, nb_hold, rx_id);
1094
1095         return nb_rx;
1096 }
1097
1098 /* implement recv_scattered_pkts for flexible Rx descriptor */
1099 uint16_t
1100 iavf_recv_scattered_pkts_flex_rxd(void *rx_queue, struct rte_mbuf **rx_pkts,
1101                                   uint16_t nb_pkts)
1102 {
1103         struct iavf_rx_queue *rxq = rx_queue;
1104         union iavf_rx_flex_desc rxd;
1105         struct rte_mbuf *rxe;
1106         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1107         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1108         struct rte_mbuf *nmb, *rxm;
1109         uint16_t rx_id = rxq->rx_tail;
1110         uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
1111         struct rte_eth_dev *dev;
1112         uint16_t rx_stat_err0;
1113         uint64_t dma_addr;
1114         uint64_t pkt_flags;
1115
1116         volatile union iavf_rx_desc *rx_ring = rxq->rx_ring;
1117         volatile union iavf_rx_flex_desc *rxdp;
1118         const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1119
1120         while (nb_rx < nb_pkts) {
1121                 rxdp = (volatile union iavf_rx_flex_desc *)&rx_ring[rx_id];
1122                 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1123
1124                 /* Check the DD bit */
1125                 if (!(rx_stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S)))
1126                         break;
1127                 IAVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
1128
1129                 nmb = rte_mbuf_raw_alloc(rxq->mp);
1130                 if (unlikely(!nmb)) {
1131                         PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1132                                    "queue_id=%u", rxq->port_id, rxq->queue_id);
1133                         dev = &rte_eth_devices[rxq->port_id];
1134                         dev->data->rx_mbuf_alloc_failed++;
1135                         break;
1136                 }
1137
1138                 rxd = *rxdp;
1139                 nb_hold++;
1140                 rxe = rxq->sw_ring[rx_id];
1141                 rx_id++;
1142                 if (rx_id == rxq->nb_rx_desc)
1143                         rx_id = 0;
1144
1145                 /* Prefetch next mbuf */
1146                 rte_prefetch0(rxq->sw_ring[rx_id]);
1147
1148                 /* When next RX descriptor is on a cache line boundary,
1149                  * prefetch the next 4 RX descriptors and next 8 pointers
1150                  * to mbufs.
1151                  */
1152                 if ((rx_id & 0x3) == 0) {
1153                         rte_prefetch0(&rx_ring[rx_id]);
1154                         rte_prefetch0(rxq->sw_ring[rx_id]);
1155                 }
1156
1157                 rxm = rxe;
1158                 dma_addr =
1159                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1160
1161                 /* Set data buffer address and data length of the mbuf */
1162                 rxdp->read.hdr_addr = 0;
1163                 rxdp->read.pkt_addr = dma_addr;
1164                 rx_packet_len = rte_le_to_cpu_16(rxd.wb.pkt_len) &
1165                                 IAVF_RX_FLX_DESC_PKT_LEN_M;
1166                 rxm->data_len = rx_packet_len;
1167                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1168
1169                 /* If this is the first buffer of the received packet, set the
1170                  * pointer to the first mbuf of the packet and initialize its
1171                  * context. Otherwise, update the total length and the number
1172                  * of segments of the current scattered packet, and update the
1173                  * pointer to the last mbuf of the current packet.
1174                  */
1175                 if (!first_seg) {
1176                         first_seg = rxm;
1177                         first_seg->nb_segs = 1;
1178                         first_seg->pkt_len = rx_packet_len;
1179                 } else {
1180                         first_seg->pkt_len =
1181                                 (uint16_t)(first_seg->pkt_len +
1182                                                 rx_packet_len);
1183                         first_seg->nb_segs++;
1184                         last_seg->next = rxm;
1185                 }
1186
1187                 /* If this is not the last buffer of the received packet,
1188                  * update the pointer to the last mbuf of the current scattered
1189                  * packet and continue to parse the RX ring.
1190                  */
1191                 if (!(rx_stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_EOF_S))) {
1192                         last_seg = rxm;
1193                         continue;
1194                 }
1195
1196                 /* This is the last buffer of the received packet. If the CRC
1197                  * is not stripped by the hardware:
1198                  *  - Subtract the CRC length from the total packet length.
1199                  *  - If the last buffer only contains the whole CRC or a part
1200                  *  of it, free the mbuf associated to the last buffer. If part
1201                  *  of the CRC is also contained in the previous mbuf, subtract
1202                  *  the length of that CRC part from the data length of the
1203                  *  previous mbuf.
1204                  */
1205                 rxm->next = NULL;
1206                 if (unlikely(rxq->crc_len > 0)) {
1207                         first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
1208                         if (rx_packet_len <= RTE_ETHER_CRC_LEN) {
1209                                 rte_pktmbuf_free_seg(rxm);
1210                                 first_seg->nb_segs--;
1211                                 last_seg->data_len =
1212                                         (uint16_t)(last_seg->data_len -
1213                                         (RTE_ETHER_CRC_LEN - rx_packet_len));
1214                                 last_seg->next = NULL;
1215                         } else {
1216                                 rxm->data_len = (uint16_t)(rx_packet_len -
1217                                                         RTE_ETHER_CRC_LEN);
1218                         }
1219                 }
1220
1221                 first_seg->port = rxq->port_id;
1222                 first_seg->ol_flags = 0;
1223                 first_seg->packet_type = ptype_tbl[IAVF_RX_FLEX_DESC_PTYPE_M &
1224                         rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
1225                 iavf_flex_rxd_to_vlan_tci(first_seg, &rxd);
1226                 iavf_rxd_to_pkt_fields(first_seg, &rxd);
1227                 pkt_flags = iavf_flex_rxd_error_to_pkt_flags(rx_stat_err0);
1228
1229                 first_seg->ol_flags |= pkt_flags;
1230
1231                 /* Prefetch data of first segment, if configured to do so. */
1232                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1233                                           first_seg->data_off));
1234                 rx_pkts[nb_rx++] = first_seg;
1235                 first_seg = NULL;
1236         }
1237
1238         /* Record index of the next RX descriptor to probe. */
1239         rxq->rx_tail = rx_id;
1240         rxq->pkt_first_seg = first_seg;
1241         rxq->pkt_last_seg = last_seg;
1242
1243         iavf_update_rx_tail(rxq, nb_hold, rx_id);
1244
1245         return nb_rx;
1246 }
1247
1248 /* implement recv_scattered_pkts  */
1249 uint16_t
1250 iavf_recv_scattered_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1251                         uint16_t nb_pkts)
1252 {
1253         struct iavf_rx_queue *rxq = rx_queue;
1254         union iavf_rx_desc rxd;
1255         struct rte_mbuf *rxe;
1256         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1257         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1258         struct rte_mbuf *nmb, *rxm;
1259         uint16_t rx_id = rxq->rx_tail;
1260         uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
1261         struct rte_eth_dev *dev;
1262         uint32_t rx_status;
1263         uint64_t qword1;
1264         uint64_t dma_addr;
1265         uint64_t pkt_flags;
1266
1267         volatile union iavf_rx_desc *rx_ring = rxq->rx_ring;
1268         volatile union iavf_rx_desc *rxdp;
1269         const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1270
1271         while (nb_rx < nb_pkts) {
1272                 rxdp = &rx_ring[rx_id];
1273                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1274                 rx_status = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
1275                             IAVF_RXD_QW1_STATUS_SHIFT;
1276
1277                 /* Check the DD bit */
1278                 if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)))
1279                         break;
1280                 IAVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
1281
1282                 nmb = rte_mbuf_raw_alloc(rxq->mp);
1283                 if (unlikely(!nmb)) {
1284                         PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1285                                    "queue_id=%u", rxq->port_id, rxq->queue_id);
1286                         dev = &rte_eth_devices[rxq->port_id];
1287                         dev->data->rx_mbuf_alloc_failed++;
1288                         break;
1289                 }
1290
1291                 rxd = *rxdp;
1292                 nb_hold++;
1293                 rxe = rxq->sw_ring[rx_id];
1294                 rx_id++;
1295                 if (rx_id == rxq->nb_rx_desc)
1296                         rx_id = 0;
1297
1298                 /* Prefetch next mbuf */
1299                 rte_prefetch0(rxq->sw_ring[rx_id]);
1300
1301                 /* When next RX descriptor is on a cache line boundary,
1302                  * prefetch the next 4 RX descriptors and next 8 pointers
1303                  * to mbufs.
1304                  */
1305                 if ((rx_id & 0x3) == 0) {
1306                         rte_prefetch0(&rx_ring[rx_id]);
1307                         rte_prefetch0(rxq->sw_ring[rx_id]);
1308                 }
1309
1310                 rxm = rxe;
1311                 dma_addr =
1312                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1313
1314                 /* Set data buffer address and data length of the mbuf */
1315                 rxdp->read.hdr_addr = 0;
1316                 rxdp->read.pkt_addr = dma_addr;
1317                 rx_packet_len = (qword1 & IAVF_RXD_QW1_LENGTH_PBUF_MASK) >>
1318                                  IAVF_RXD_QW1_LENGTH_PBUF_SHIFT;
1319                 rxm->data_len = rx_packet_len;
1320                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1321
1322                 /* If this is the first buffer of the received packet, set the
1323                  * pointer to the first mbuf of the packet and initialize its
1324                  * context. Otherwise, update the total length and the number
1325                  * of segments of the current scattered packet, and update the
1326                  * pointer to the last mbuf of the current packet.
1327                  */
1328                 if (!first_seg) {
1329                         first_seg = rxm;
1330                         first_seg->nb_segs = 1;
1331                         first_seg->pkt_len = rx_packet_len;
1332                 } else {
1333                         first_seg->pkt_len =
1334                                 (uint16_t)(first_seg->pkt_len +
1335                                                 rx_packet_len);
1336                         first_seg->nb_segs++;
1337                         last_seg->next = rxm;
1338                 }
1339
1340                 /* If this is not the last buffer of the received packet,
1341                  * update the pointer to the last mbuf of the current scattered
1342                  * packet and continue to parse the RX ring.
1343                  */
1344                 if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_EOF_SHIFT))) {
1345                         last_seg = rxm;
1346                         continue;
1347                 }
1348
1349                 /* This is the last buffer of the received packet. If the CRC
1350                  * is not stripped by the hardware:
1351                  *  - Subtract the CRC length from the total packet length.
1352                  *  - If the last buffer only contains the whole CRC or a part
1353                  *  of it, free the mbuf associated to the last buffer. If part
1354                  *  of the CRC is also contained in the previous mbuf, subtract
1355                  *  the length of that CRC part from the data length of the
1356                  *  previous mbuf.
1357                  */
1358                 rxm->next = NULL;
1359                 if (unlikely(rxq->crc_len > 0)) {
1360                         first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
1361                         if (rx_packet_len <= RTE_ETHER_CRC_LEN) {
1362                                 rte_pktmbuf_free_seg(rxm);
1363                                 first_seg->nb_segs--;
1364                                 last_seg->data_len =
1365                                         (uint16_t)(last_seg->data_len -
1366                                         (RTE_ETHER_CRC_LEN - rx_packet_len));
1367                                 last_seg->next = NULL;
1368                         } else
1369                                 rxm->data_len = (uint16_t)(rx_packet_len -
1370                                                         RTE_ETHER_CRC_LEN);
1371                 }
1372
1373                 first_seg->port = rxq->port_id;
1374                 first_seg->ol_flags = 0;
1375                 iavf_rxd_to_vlan_tci(first_seg, &rxd);
1376                 pkt_flags = iavf_rxd_to_pkt_flags(qword1);
1377                 first_seg->packet_type =
1378                         ptype_tbl[(uint8_t)((qword1 &
1379                         IAVF_RXD_QW1_PTYPE_MASK) >> IAVF_RXD_QW1_PTYPE_SHIFT)];
1380
1381                 if (pkt_flags & PKT_RX_RSS_HASH)
1382                         first_seg->hash.rss =
1383                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1384
1385                 if (pkt_flags & PKT_RX_FDIR)
1386                         pkt_flags |= iavf_rxd_build_fdir(&rxd, first_seg);
1387
1388                 first_seg->ol_flags |= pkt_flags;
1389
1390                 /* Prefetch data of first segment, if configured to do so. */
1391                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1392                                           first_seg->data_off));
1393                 rx_pkts[nb_rx++] = first_seg;
1394                 first_seg = NULL;
1395         }
1396
1397         /* Record index of the next RX descriptor to probe. */
1398         rxq->rx_tail = rx_id;
1399         rxq->pkt_first_seg = first_seg;
1400         rxq->pkt_last_seg = last_seg;
1401
1402         iavf_update_rx_tail(rxq, nb_hold, rx_id);
1403
1404         return nb_rx;
1405 }
1406
1407 #define IAVF_LOOK_AHEAD 8
1408 static inline int
1409 iavf_rx_scan_hw_ring_flex_rxd(struct iavf_rx_queue *rxq)
1410 {
1411         volatile union iavf_rx_flex_desc *rxdp;
1412         struct rte_mbuf **rxep;
1413         struct rte_mbuf *mb;
1414         uint16_t stat_err0;
1415         uint16_t pkt_len;
1416         int32_t s[IAVF_LOOK_AHEAD], nb_dd;
1417         int32_t i, j, nb_rx = 0;
1418         uint64_t pkt_flags;
1419         const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1420
1421         rxdp = (volatile union iavf_rx_flex_desc *)&rxq->rx_ring[rxq->rx_tail];
1422         rxep = &rxq->sw_ring[rxq->rx_tail];
1423
1424         stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1425
1426         /* Make sure there is at least 1 packet to receive */
1427         if (!(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S)))
1428                 return 0;
1429
1430         /* Scan LOOK_AHEAD descriptors at a time to determine which
1431          * descriptors reference packets that are ready to be received.
1432          */
1433         for (i = 0; i < IAVF_RX_MAX_BURST; i += IAVF_LOOK_AHEAD,
1434              rxdp += IAVF_LOOK_AHEAD, rxep += IAVF_LOOK_AHEAD) {
1435                 /* Read desc statuses backwards to avoid race condition */
1436                 for (j = IAVF_LOOK_AHEAD - 1; j >= 0; j--)
1437                         s[j] = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1438
1439                 rte_smp_rmb();
1440
1441                 /* Compute how many status bits were set */
1442                 for (j = 0, nb_dd = 0; j < IAVF_LOOK_AHEAD; j++)
1443                         nb_dd += s[j] & (1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S);
1444
1445                 nb_rx += nb_dd;
1446
1447                 /* Translate descriptor info to mbuf parameters */
1448                 for (j = 0; j < nb_dd; j++) {
1449                         IAVF_DUMP_RX_DESC(rxq, &rxdp[j],
1450                                           rxq->rx_tail +
1451                                           i * IAVF_LOOK_AHEAD + j);
1452
1453                         mb = rxep[j];
1454                         pkt_len = (rte_le_to_cpu_16(rxdp[j].wb.pkt_len) &
1455                                 IAVF_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
1456                         mb->data_len = pkt_len;
1457                         mb->pkt_len = pkt_len;
1458                         mb->ol_flags = 0;
1459
1460                         mb->packet_type = ptype_tbl[IAVF_RX_FLEX_DESC_PTYPE_M &
1461                                 rte_le_to_cpu_16(rxdp[j].wb.ptype_flex_flags0)];
1462                         iavf_flex_rxd_to_vlan_tci(mb, &rxdp[j]);
1463                         iavf_rxd_to_pkt_fields(mb, &rxdp[j]);
1464                         stat_err0 = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1465                         pkt_flags = iavf_flex_rxd_error_to_pkt_flags(stat_err0);
1466
1467                         mb->ol_flags |= pkt_flags;
1468                 }
1469
1470                 for (j = 0; j < IAVF_LOOK_AHEAD; j++)
1471                         rxq->rx_stage[i + j] = rxep[j];
1472
1473                 if (nb_dd != IAVF_LOOK_AHEAD)
1474                         break;
1475         }
1476
1477         /* Clear software ring entries */
1478         for (i = 0; i < nb_rx; i++)
1479                 rxq->sw_ring[rxq->rx_tail + i] = NULL;
1480
1481         return nb_rx;
1482 }
1483
1484 static inline int
1485 iavf_rx_scan_hw_ring(struct iavf_rx_queue *rxq)
1486 {
1487         volatile union iavf_rx_desc *rxdp;
1488         struct rte_mbuf **rxep;
1489         struct rte_mbuf *mb;
1490         uint16_t pkt_len;
1491         uint64_t qword1;
1492         uint32_t rx_status;
1493         int32_t s[IAVF_LOOK_AHEAD], nb_dd;
1494         int32_t i, j, nb_rx = 0;
1495         uint64_t pkt_flags;
1496         const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1497
1498         rxdp = &rxq->rx_ring[rxq->rx_tail];
1499         rxep = &rxq->sw_ring[rxq->rx_tail];
1500
1501         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1502         rx_status = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
1503                     IAVF_RXD_QW1_STATUS_SHIFT;
1504
1505         /* Make sure there is at least 1 packet to receive */
1506         if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)))
1507                 return 0;
1508
1509         /* Scan LOOK_AHEAD descriptors at a time to determine which
1510          * descriptors reference packets that are ready to be received.
1511          */
1512         for (i = 0; i < IAVF_RX_MAX_BURST; i += IAVF_LOOK_AHEAD,
1513              rxdp += IAVF_LOOK_AHEAD, rxep += IAVF_LOOK_AHEAD) {
1514                 /* Read desc statuses backwards to avoid race condition */
1515                 for (j = IAVF_LOOK_AHEAD - 1; j >= 0; j--) {
1516                         qword1 = rte_le_to_cpu_64(
1517                                 rxdp[j].wb.qword1.status_error_len);
1518                         s[j] = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
1519                                IAVF_RXD_QW1_STATUS_SHIFT;
1520                 }
1521
1522                 rte_smp_rmb();
1523
1524                 /* Compute how many status bits were set */
1525                 for (j = 0, nb_dd = 0; j < IAVF_LOOK_AHEAD; j++)
1526                         nb_dd += s[j] & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT);
1527
1528                 nb_rx += nb_dd;
1529
1530                 /* Translate descriptor info to mbuf parameters */
1531                 for (j = 0; j < nb_dd; j++) {
1532                         IAVF_DUMP_RX_DESC(rxq, &rxdp[j],
1533                                          rxq->rx_tail + i * IAVF_LOOK_AHEAD + j);
1534
1535                         mb = rxep[j];
1536                         qword1 = rte_le_to_cpu_64
1537                                         (rxdp[j].wb.qword1.status_error_len);
1538                         pkt_len = ((qword1 & IAVF_RXD_QW1_LENGTH_PBUF_MASK) >>
1539                                   IAVF_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
1540                         mb->data_len = pkt_len;
1541                         mb->pkt_len = pkt_len;
1542                         mb->ol_flags = 0;
1543                         iavf_rxd_to_vlan_tci(mb, &rxdp[j]);
1544                         pkt_flags = iavf_rxd_to_pkt_flags(qword1);
1545                         mb->packet_type =
1546                                 ptype_tbl[(uint8_t)((qword1 &
1547                                 IAVF_RXD_QW1_PTYPE_MASK) >>
1548                                 IAVF_RXD_QW1_PTYPE_SHIFT)];
1549
1550                         if (pkt_flags & PKT_RX_RSS_HASH)
1551                                 mb->hash.rss = rte_le_to_cpu_32(
1552                                         rxdp[j].wb.qword0.hi_dword.rss);
1553
1554                         if (pkt_flags & PKT_RX_FDIR)
1555                                 pkt_flags |= iavf_rxd_build_fdir(&rxdp[j], mb);
1556
1557                         mb->ol_flags |= pkt_flags;
1558                 }
1559
1560                 for (j = 0; j < IAVF_LOOK_AHEAD; j++)
1561                         rxq->rx_stage[i + j] = rxep[j];
1562
1563                 if (nb_dd != IAVF_LOOK_AHEAD)
1564                         break;
1565         }
1566
1567         /* Clear software ring entries */
1568         for (i = 0; i < nb_rx; i++)
1569                 rxq->sw_ring[rxq->rx_tail + i] = NULL;
1570
1571         return nb_rx;
1572 }
1573
1574 static inline uint16_t
1575 iavf_rx_fill_from_stage(struct iavf_rx_queue *rxq,
1576                        struct rte_mbuf **rx_pkts,
1577                        uint16_t nb_pkts)
1578 {
1579         uint16_t i;
1580         struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1581
1582         nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1583
1584         for (i = 0; i < nb_pkts; i++)
1585                 rx_pkts[i] = stage[i];
1586
1587         rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1588         rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1589
1590         return nb_pkts;
1591 }
1592
1593 static inline int
1594 iavf_rx_alloc_bufs(struct iavf_rx_queue *rxq)
1595 {
1596         volatile union iavf_rx_desc *rxdp;
1597         struct rte_mbuf **rxep;
1598         struct rte_mbuf *mb;
1599         uint16_t alloc_idx, i;
1600         uint64_t dma_addr;
1601         int diag;
1602
1603         /* Allocate buffers in bulk */
1604         alloc_idx = (uint16_t)(rxq->rx_free_trigger -
1605                                 (rxq->rx_free_thresh - 1));
1606         rxep = &rxq->sw_ring[alloc_idx];
1607         diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
1608                                     rxq->rx_free_thresh);
1609         if (unlikely(diag != 0)) {
1610                 PMD_RX_LOG(ERR, "Failed to get mbufs in bulk");
1611                 return -ENOMEM;
1612         }
1613
1614         rxdp = &rxq->rx_ring[alloc_idx];
1615         for (i = 0; i < rxq->rx_free_thresh; i++) {
1616                 if (likely(i < (rxq->rx_free_thresh - 1)))
1617                         /* Prefetch next mbuf */
1618                         rte_prefetch0(rxep[i + 1]);
1619
1620                 mb = rxep[i];
1621                 rte_mbuf_refcnt_set(mb, 1);
1622                 mb->next = NULL;
1623                 mb->data_off = RTE_PKTMBUF_HEADROOM;
1624                 mb->nb_segs = 1;
1625                 mb->port = rxq->port_id;
1626                 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mb));
1627                 rxdp[i].read.hdr_addr = 0;
1628                 rxdp[i].read.pkt_addr = dma_addr;
1629         }
1630
1631         /* Update rx tail register */
1632         rte_wmb();
1633         IAVF_PCI_REG_WRITE_RELAXED(rxq->qrx_tail, rxq->rx_free_trigger);
1634
1635         rxq->rx_free_trigger =
1636                 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
1637         if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1638                 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
1639
1640         return 0;
1641 }
1642
1643 static inline uint16_t
1644 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1645 {
1646         struct iavf_rx_queue *rxq = (struct iavf_rx_queue *)rx_queue;
1647         uint16_t nb_rx = 0;
1648
1649         if (!nb_pkts)
1650                 return 0;
1651
1652         if (rxq->rx_nb_avail)
1653                 return iavf_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1654
1655         if (rxq->rxdid == IAVF_RXDID_COMMS_OVS_1)
1656                 nb_rx = (uint16_t)iavf_rx_scan_hw_ring_flex_rxd(rxq);
1657         else
1658                 nb_rx = (uint16_t)iavf_rx_scan_hw_ring(rxq);
1659         rxq->rx_next_avail = 0;
1660         rxq->rx_nb_avail = nb_rx;
1661         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1662
1663         if (rxq->rx_tail > rxq->rx_free_trigger) {
1664                 if (iavf_rx_alloc_bufs(rxq) != 0) {
1665                         uint16_t i, j;
1666
1667                         /* TODO: count rx_mbuf_alloc_failed here */
1668
1669                         rxq->rx_nb_avail = 0;
1670                         rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1671                         for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
1672                                 rxq->sw_ring[j] = rxq->rx_stage[i];
1673
1674                         return 0;
1675                 }
1676         }
1677
1678         if (rxq->rx_tail >= rxq->nb_rx_desc)
1679                 rxq->rx_tail = 0;
1680
1681         PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u, nb_rx=%u",
1682                    rxq->port_id, rxq->queue_id,
1683                    rxq->rx_tail, nb_rx);
1684
1685         if (rxq->rx_nb_avail)
1686                 return iavf_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1687
1688         return 0;
1689 }
1690
1691 static uint16_t
1692 iavf_recv_pkts_bulk_alloc(void *rx_queue,
1693                          struct rte_mbuf **rx_pkts,
1694                          uint16_t nb_pkts)
1695 {
1696         uint16_t nb_rx = 0, n, count;
1697
1698         if (unlikely(nb_pkts == 0))
1699                 return 0;
1700
1701         if (likely(nb_pkts <= IAVF_RX_MAX_BURST))
1702                 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1703
1704         while (nb_pkts) {
1705                 n = RTE_MIN(nb_pkts, IAVF_RX_MAX_BURST);
1706                 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1707                 nb_rx = (uint16_t)(nb_rx + count);
1708                 nb_pkts = (uint16_t)(nb_pkts - count);
1709                 if (count < n)
1710                         break;
1711         }
1712
1713         return nb_rx;
1714 }
1715
1716 static inline int
1717 iavf_xmit_cleanup(struct iavf_tx_queue *txq)
1718 {
1719         struct iavf_tx_entry *sw_ring = txq->sw_ring;
1720         uint16_t last_desc_cleaned = txq->last_desc_cleaned;
1721         uint16_t nb_tx_desc = txq->nb_tx_desc;
1722         uint16_t desc_to_clean_to;
1723         uint16_t nb_tx_to_clean;
1724
1725         volatile struct iavf_tx_desc *txd = txq->tx_ring;
1726
1727         desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->rs_thresh);
1728         if (desc_to_clean_to >= nb_tx_desc)
1729                 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
1730
1731         desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
1732         if ((txd[desc_to_clean_to].cmd_type_offset_bsz &
1733                         rte_cpu_to_le_64(IAVF_TXD_QW1_DTYPE_MASK)) !=
1734                         rte_cpu_to_le_64(IAVF_TX_DESC_DTYPE_DESC_DONE)) {
1735                 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
1736                                 "(port=%d queue=%d)", desc_to_clean_to,
1737                                 txq->port_id, txq->queue_id);
1738                 return -1;
1739         }
1740
1741         if (last_desc_cleaned > desc_to_clean_to)
1742                 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
1743                                                         desc_to_clean_to);
1744         else
1745                 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
1746                                         last_desc_cleaned);
1747
1748         txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
1749
1750         txq->last_desc_cleaned = desc_to_clean_to;
1751         txq->nb_free = (uint16_t)(txq->nb_free + nb_tx_to_clean);
1752
1753         return 0;
1754 }
1755
1756 /* Check if the context descriptor is needed for TX offloading */
1757 static inline uint16_t
1758 iavf_calc_context_desc(uint64_t flags)
1759 {
1760         static uint64_t mask = PKT_TX_TCP_SEG;
1761
1762         return (flags & mask) ? 1 : 0;
1763 }
1764
1765 static inline void
1766 iavf_txd_enable_checksum(uint64_t ol_flags,
1767                         uint32_t *td_cmd,
1768                         uint32_t *td_offset,
1769                         union iavf_tx_offload tx_offload)
1770 {
1771         /* Set MACLEN */
1772         *td_offset |= (tx_offload.l2_len >> 1) <<
1773                       IAVF_TX_DESC_LENGTH_MACLEN_SHIFT;
1774
1775         /* Enable L3 checksum offloads */
1776         if (ol_flags & PKT_TX_IP_CKSUM) {
1777                 *td_cmd |= IAVF_TX_DESC_CMD_IIPT_IPV4_CSUM;
1778                 *td_offset |= (tx_offload.l3_len >> 2) <<
1779                               IAVF_TX_DESC_LENGTH_IPLEN_SHIFT;
1780         } else if (ol_flags & PKT_TX_IPV4) {
1781                 *td_cmd |= IAVF_TX_DESC_CMD_IIPT_IPV4;
1782                 *td_offset |= (tx_offload.l3_len >> 2) <<
1783                               IAVF_TX_DESC_LENGTH_IPLEN_SHIFT;
1784         } else if (ol_flags & PKT_TX_IPV6) {
1785                 *td_cmd |= IAVF_TX_DESC_CMD_IIPT_IPV6;
1786                 *td_offset |= (tx_offload.l3_len >> 2) <<
1787                               IAVF_TX_DESC_LENGTH_IPLEN_SHIFT;
1788         }
1789
1790         if (ol_flags & PKT_TX_TCP_SEG) {
1791                 *td_cmd |= IAVF_TX_DESC_CMD_L4T_EOFT_TCP;
1792                 *td_offset |= (tx_offload.l4_len >> 2) <<
1793                               IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1794                 return;
1795         }
1796
1797         /* Enable L4 checksum offloads */
1798         switch (ol_flags & PKT_TX_L4_MASK) {
1799         case PKT_TX_TCP_CKSUM:
1800                 *td_cmd |= IAVF_TX_DESC_CMD_L4T_EOFT_TCP;
1801                 *td_offset |= (sizeof(struct rte_tcp_hdr) >> 2) <<
1802                               IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1803                 break;
1804         case PKT_TX_SCTP_CKSUM:
1805                 *td_cmd |= IAVF_TX_DESC_CMD_L4T_EOFT_SCTP;
1806                 *td_offset |= (sizeof(struct rte_sctp_hdr) >> 2) <<
1807                               IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1808                 break;
1809         case PKT_TX_UDP_CKSUM:
1810                 *td_cmd |= IAVF_TX_DESC_CMD_L4T_EOFT_UDP;
1811                 *td_offset |= (sizeof(struct rte_udp_hdr) >> 2) <<
1812                               IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1813                 break;
1814         default:
1815                 break;
1816         }
1817 }
1818
1819 /* set TSO context descriptor
1820  * support IP -> L4 and IP -> IP -> L4
1821  */
1822 static inline uint64_t
1823 iavf_set_tso_ctx(struct rte_mbuf *mbuf, union iavf_tx_offload tx_offload)
1824 {
1825         uint64_t ctx_desc = 0;
1826         uint32_t cd_cmd, hdr_len, cd_tso_len;
1827
1828         if (!tx_offload.l4_len) {
1829                 PMD_TX_LOG(DEBUG, "L4 length set to 0");
1830                 return ctx_desc;
1831         }
1832
1833         hdr_len = tx_offload.l2_len +
1834                   tx_offload.l3_len +
1835                   tx_offload.l4_len;
1836
1837         cd_cmd = IAVF_TX_CTX_DESC_TSO;
1838         cd_tso_len = mbuf->pkt_len - hdr_len;
1839         ctx_desc |= ((uint64_t)cd_cmd << IAVF_TXD_CTX_QW1_CMD_SHIFT) |
1840                      ((uint64_t)cd_tso_len << IAVF_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1841                      ((uint64_t)mbuf->tso_segsz << IAVF_TXD_CTX_QW1_MSS_SHIFT);
1842
1843         return ctx_desc;
1844 }
1845
1846 /* Construct the tx flags */
1847 static inline uint64_t
1848 iavf_build_ctob(uint32_t td_cmd, uint32_t td_offset, unsigned int size,
1849                uint32_t td_tag)
1850 {
1851         return rte_cpu_to_le_64(IAVF_TX_DESC_DTYPE_DATA |
1852                                 ((uint64_t)td_cmd  << IAVF_TXD_QW1_CMD_SHIFT) |
1853                                 ((uint64_t)td_offset <<
1854                                  IAVF_TXD_QW1_OFFSET_SHIFT) |
1855                                 ((uint64_t)size  <<
1856                                  IAVF_TXD_QW1_TX_BUF_SZ_SHIFT) |
1857                                 ((uint64_t)td_tag  <<
1858                                  IAVF_TXD_QW1_L2TAG1_SHIFT));
1859 }
1860
1861 /* TX function */
1862 uint16_t
1863 iavf_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1864 {
1865         volatile struct iavf_tx_desc *txd;
1866         volatile struct iavf_tx_desc *txr;
1867         struct iavf_tx_queue *txq;
1868         struct iavf_tx_entry *sw_ring;
1869         struct iavf_tx_entry *txe, *txn;
1870         struct rte_mbuf *tx_pkt;
1871         struct rte_mbuf *m_seg;
1872         uint16_t tx_id;
1873         uint16_t nb_tx;
1874         uint32_t td_cmd;
1875         uint32_t td_offset;
1876         uint32_t td_tag;
1877         uint64_t ol_flags;
1878         uint16_t nb_used;
1879         uint16_t nb_ctx;
1880         uint16_t tx_last;
1881         uint16_t slen;
1882         uint64_t buf_dma_addr;
1883         union iavf_tx_offload tx_offload = {0};
1884
1885         txq = tx_queue;
1886         sw_ring = txq->sw_ring;
1887         txr = txq->tx_ring;
1888         tx_id = txq->tx_tail;
1889         txe = &sw_ring[tx_id];
1890
1891         /* Check if the descriptor ring needs to be cleaned. */
1892         if (txq->nb_free < txq->free_thresh)
1893                 iavf_xmit_cleanup(txq);
1894
1895         for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1896                 td_cmd = 0;
1897                 td_tag = 0;
1898                 td_offset = 0;
1899
1900                 tx_pkt = *tx_pkts++;
1901                 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
1902
1903                 ol_flags = tx_pkt->ol_flags;
1904                 tx_offload.l2_len = tx_pkt->l2_len;
1905                 tx_offload.l3_len = tx_pkt->l3_len;
1906                 tx_offload.l4_len = tx_pkt->l4_len;
1907                 tx_offload.tso_segsz = tx_pkt->tso_segsz;
1908
1909                 /* Calculate the number of context descriptors needed. */
1910                 nb_ctx = iavf_calc_context_desc(ol_flags);
1911
1912                 /* The number of descriptors that must be allocated for
1913                  * a packet equals to the number of the segments of that
1914                  * packet plus 1 context descriptor if needed.
1915                  */
1916                 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
1917                 tx_last = (uint16_t)(tx_id + nb_used - 1);
1918
1919                 /* Circular ring */
1920                 if (tx_last >= txq->nb_tx_desc)
1921                         tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
1922
1923                 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u"
1924                            " tx_first=%u tx_last=%u",
1925                            txq->port_id, txq->queue_id, tx_id, tx_last);
1926
1927                 if (nb_used > txq->nb_free) {
1928                         if (iavf_xmit_cleanup(txq)) {
1929                                 if (nb_tx == 0)
1930                                         return 0;
1931                                 goto end_of_tx;
1932                         }
1933                         if (unlikely(nb_used > txq->rs_thresh)) {
1934                                 while (nb_used > txq->nb_free) {
1935                                         if (iavf_xmit_cleanup(txq)) {
1936                                                 if (nb_tx == 0)
1937                                                         return 0;
1938                                                 goto end_of_tx;
1939                                         }
1940                                 }
1941                         }
1942                 }
1943
1944                 /* Descriptor based VLAN insertion */
1945                 if (ol_flags & PKT_TX_VLAN_PKT) {
1946                         td_cmd |= IAVF_TX_DESC_CMD_IL2TAG1;
1947                         td_tag = tx_pkt->vlan_tci;
1948                 }
1949
1950                 /* According to datasheet, the bit2 is reserved and must be
1951                  * set to 1.
1952                  */
1953                 td_cmd |= 0x04;
1954
1955                 /* Enable checksum offloading */
1956                 if (ol_flags & IAVF_TX_CKSUM_OFFLOAD_MASK)
1957                         iavf_txd_enable_checksum(ol_flags, &td_cmd,
1958                                                 &td_offset, tx_offload);
1959
1960                 if (nb_ctx) {
1961                         /* Setup TX context descriptor if required */
1962                         uint64_t cd_type_cmd_tso_mss =
1963                                 IAVF_TX_DESC_DTYPE_CONTEXT;
1964                         volatile struct iavf_tx_context_desc *ctx_txd =
1965                                 (volatile struct iavf_tx_context_desc *)
1966                                                         &txr[tx_id];
1967
1968                         txn = &sw_ring[txe->next_id];
1969                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
1970                         if (txe->mbuf) {
1971                                 rte_pktmbuf_free_seg(txe->mbuf);
1972                                 txe->mbuf = NULL;
1973                         }
1974
1975                         /* TSO enabled */
1976                         if (ol_flags & PKT_TX_TCP_SEG)
1977                                 cd_type_cmd_tso_mss |=
1978                                         iavf_set_tso_ctx(tx_pkt, tx_offload);
1979
1980                         ctx_txd->type_cmd_tso_mss =
1981                                 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
1982
1983                         IAVF_DUMP_TX_DESC(txq, &txr[tx_id], tx_id);
1984                         txe->last_id = tx_last;
1985                         tx_id = txe->next_id;
1986                         txe = txn;
1987                 }
1988
1989                 m_seg = tx_pkt;
1990                 do {
1991                         txd = &txr[tx_id];
1992                         txn = &sw_ring[txe->next_id];
1993
1994                         if (txe->mbuf)
1995                                 rte_pktmbuf_free_seg(txe->mbuf);
1996                         txe->mbuf = m_seg;
1997
1998                         /* Setup TX Descriptor */
1999                         slen = m_seg->data_len;
2000                         buf_dma_addr = rte_mbuf_data_iova(m_seg);
2001                         txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
2002                         txd->cmd_type_offset_bsz = iavf_build_ctob(td_cmd,
2003                                                                   td_offset,
2004                                                                   slen,
2005                                                                   td_tag);
2006
2007                         IAVF_DUMP_TX_DESC(txq, txd, tx_id);
2008                         txe->last_id = tx_last;
2009                         tx_id = txe->next_id;
2010                         txe = txn;
2011                         m_seg = m_seg->next;
2012                 } while (m_seg);
2013
2014                 /* The last packet data descriptor needs End Of Packet (EOP) */
2015                 td_cmd |= IAVF_TX_DESC_CMD_EOP;
2016                 txq->nb_used = (uint16_t)(txq->nb_used + nb_used);
2017                 txq->nb_free = (uint16_t)(txq->nb_free - nb_used);
2018
2019                 if (txq->nb_used >= txq->rs_thresh) {
2020                         PMD_TX_LOG(DEBUG, "Setting RS bit on TXD id="
2021                                    "%4u (port=%d queue=%d)",
2022                                    tx_last, txq->port_id, txq->queue_id);
2023
2024                         td_cmd |= IAVF_TX_DESC_CMD_RS;
2025
2026                         /* Update txq RS bit counters */
2027                         txq->nb_used = 0;
2028                 }
2029
2030                 txd->cmd_type_offset_bsz |=
2031                         rte_cpu_to_le_64(((uint64_t)td_cmd) <<
2032                                          IAVF_TXD_QW1_CMD_SHIFT);
2033                 IAVF_DUMP_TX_DESC(txq, txd, tx_id);
2034         }
2035
2036 end_of_tx:
2037         rte_wmb();
2038
2039         PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
2040                    txq->port_id, txq->queue_id, tx_id, nb_tx);
2041
2042         IAVF_PCI_REG_WRITE_RELAXED(txq->qtx_tail, tx_id);
2043         txq->tx_tail = tx_id;
2044
2045         return nb_tx;
2046 }
2047
2048 /* TX prep functions */
2049 uint16_t
2050 iavf_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
2051               uint16_t nb_pkts)
2052 {
2053         int i, ret;
2054         uint64_t ol_flags;
2055         struct rte_mbuf *m;
2056
2057         for (i = 0; i < nb_pkts; i++) {
2058                 m = tx_pkts[i];
2059                 ol_flags = m->ol_flags;
2060
2061                 /* Check condition for nb_segs > IAVF_TX_MAX_MTU_SEG. */
2062                 if (!(ol_flags & PKT_TX_TCP_SEG)) {
2063                         if (m->nb_segs > IAVF_TX_MAX_MTU_SEG) {
2064                                 rte_errno = EINVAL;
2065                                 return i;
2066                         }
2067                 } else if ((m->tso_segsz < IAVF_MIN_TSO_MSS) ||
2068                            (m->tso_segsz > IAVF_MAX_TSO_MSS)) {
2069                         /* MSS outside the range are considered malicious */
2070                         rte_errno = EINVAL;
2071                         return i;
2072                 }
2073
2074                 if (ol_flags & IAVF_TX_OFFLOAD_NOTSUP_MASK) {
2075                         rte_errno = ENOTSUP;
2076                         return i;
2077                 }
2078
2079 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
2080                 ret = rte_validate_tx_offload(m);
2081                 if (ret != 0) {
2082                         rte_errno = -ret;
2083                         return i;
2084                 }
2085 #endif
2086                 ret = rte_net_intel_cksum_prepare(m);
2087                 if (ret != 0) {
2088                         rte_errno = -ret;
2089                         return i;
2090                 }
2091         }
2092
2093         return i;
2094 }
2095
2096 /* choose rx function*/
2097 void
2098 iavf_set_rx_function(struct rte_eth_dev *dev)
2099 {
2100         struct iavf_adapter *adapter =
2101                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2102         struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2103 #ifdef RTE_ARCH_X86
2104         struct iavf_rx_queue *rxq;
2105         int i;
2106         bool use_avx2 = false;
2107
2108         if (!iavf_rx_vec_dev_check(dev)) {
2109                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2110                         rxq = dev->data->rx_queues[i];
2111                         (void)iavf_rxq_vec_setup(rxq);
2112                 }
2113
2114                 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
2115                     rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1)
2116                         use_avx2 = true;
2117
2118                 if (dev->data->scattered_rx) {
2119                         PMD_DRV_LOG(DEBUG,
2120                                     "Using %sVector Scattered Rx (port %d).",
2121                                     use_avx2 ? "avx2 " : "",
2122                                     dev->data->port_id);
2123                         if (vf->vf_res->vf_cap_flags &
2124                                 VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC)
2125                                 dev->rx_pkt_burst = use_avx2 ?
2126                                         iavf_recv_scattered_pkts_vec_avx2_flex_rxd :
2127                                         iavf_recv_scattered_pkts_vec_flex_rxd;
2128                         else
2129                                 dev->rx_pkt_burst = use_avx2 ?
2130                                         iavf_recv_scattered_pkts_vec_avx2 :
2131                                         iavf_recv_scattered_pkts_vec;
2132                 } else {
2133                         PMD_DRV_LOG(DEBUG, "Using %sVector Rx (port %d).",
2134                                     use_avx2 ? "avx2 " : "",
2135                                     dev->data->port_id);
2136                         if (vf->vf_res->vf_cap_flags &
2137                                 VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC)
2138                                 dev->rx_pkt_burst = use_avx2 ?
2139                                         iavf_recv_pkts_vec_avx2_flex_rxd :
2140                                         iavf_recv_pkts_vec_flex_rxd;
2141                         else
2142                                 dev->rx_pkt_burst = use_avx2 ?
2143                                         iavf_recv_pkts_vec_avx2 :
2144                                         iavf_recv_pkts_vec;
2145                 }
2146
2147                 return;
2148         }
2149 #endif
2150
2151         if (dev->data->scattered_rx) {
2152                 PMD_DRV_LOG(DEBUG, "Using a Scattered Rx callback (port=%d).",
2153                             dev->data->port_id);
2154                 if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC)
2155                         dev->rx_pkt_burst = iavf_recv_scattered_pkts_flex_rxd;
2156                 else
2157                         dev->rx_pkt_burst = iavf_recv_scattered_pkts;
2158         } else if (adapter->rx_bulk_alloc_allowed) {
2159                 PMD_DRV_LOG(DEBUG, "Using bulk Rx callback (port=%d).",
2160                             dev->data->port_id);
2161                 dev->rx_pkt_burst = iavf_recv_pkts_bulk_alloc;
2162         } else {
2163                 PMD_DRV_LOG(DEBUG, "Using Basic Rx callback (port=%d).",
2164                             dev->data->port_id);
2165                 if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC)
2166                         dev->rx_pkt_burst = iavf_recv_pkts_flex_rxd;
2167                 else
2168                         dev->rx_pkt_burst = iavf_recv_pkts;
2169         }
2170 }
2171
2172 /* choose tx function*/
2173 void
2174 iavf_set_tx_function(struct rte_eth_dev *dev)
2175 {
2176 #ifdef RTE_ARCH_X86
2177         struct iavf_tx_queue *txq;
2178         int i;
2179         bool use_avx2 = false;
2180
2181         if (!iavf_tx_vec_dev_check(dev)) {
2182                 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2183                         txq = dev->data->tx_queues[i];
2184                         if (!txq)
2185                                 continue;
2186                         iavf_txq_vec_setup(txq);
2187                 }
2188
2189                 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
2190                     rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1)
2191                         use_avx2 = true;
2192
2193                 PMD_DRV_LOG(DEBUG, "Using %sVector Tx (port %d).",
2194                             use_avx2 ? "avx2 " : "",
2195                             dev->data->port_id);
2196                 dev->tx_pkt_burst = use_avx2 ?
2197                                     iavf_xmit_pkts_vec_avx2 :
2198                                     iavf_xmit_pkts_vec;
2199                 dev->tx_pkt_prepare = NULL;
2200
2201                 return;
2202         }
2203 #endif
2204
2205         PMD_DRV_LOG(DEBUG, "Using Basic Tx callback (port=%d).",
2206                     dev->data->port_id);
2207         dev->tx_pkt_burst = iavf_xmit_pkts;
2208         dev->tx_pkt_prepare = iavf_prep_pkts;
2209 }
2210
2211 void
2212 iavf_dev_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2213                      struct rte_eth_rxq_info *qinfo)
2214 {
2215         struct iavf_rx_queue *rxq;
2216
2217         rxq = dev->data->rx_queues[queue_id];
2218
2219         qinfo->mp = rxq->mp;
2220         qinfo->scattered_rx = dev->data->scattered_rx;
2221         qinfo->nb_desc = rxq->nb_rx_desc;
2222
2223         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2224         qinfo->conf.rx_drop_en = true;
2225         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2226 }
2227
2228 void
2229 iavf_dev_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2230                      struct rte_eth_txq_info *qinfo)
2231 {
2232         struct iavf_tx_queue *txq;
2233
2234         txq = dev->data->tx_queues[queue_id];
2235
2236         qinfo->nb_desc = txq->nb_tx_desc;
2237
2238         qinfo->conf.tx_free_thresh = txq->free_thresh;
2239         qinfo->conf.tx_rs_thresh = txq->rs_thresh;
2240         qinfo->conf.offloads = txq->offloads;
2241         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2242 }
2243
2244 /* Get the number of used descriptors of a rx queue */
2245 uint32_t
2246 iavf_dev_rxq_count(struct rte_eth_dev *dev, uint16_t queue_id)
2247 {
2248 #define IAVF_RXQ_SCAN_INTERVAL 4
2249         volatile union iavf_rx_desc *rxdp;
2250         struct iavf_rx_queue *rxq;
2251         uint16_t desc = 0;
2252
2253         rxq = dev->data->rx_queues[queue_id];
2254         rxdp = &rxq->rx_ring[rxq->rx_tail];
2255
2256         while ((desc < rxq->nb_rx_desc) &&
2257                ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
2258                  IAVF_RXD_QW1_STATUS_MASK) >> IAVF_RXD_QW1_STATUS_SHIFT) &
2259                (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)) {
2260                 /* Check the DD bit of a rx descriptor of each 4 in a group,
2261                  * to avoid checking too frequently and downgrading performance
2262                  * too much.
2263                  */
2264                 desc += IAVF_RXQ_SCAN_INTERVAL;
2265                 rxdp += IAVF_RXQ_SCAN_INTERVAL;
2266                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
2267                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
2268                                         desc - rxq->nb_rx_desc]);
2269         }
2270
2271         return desc;
2272 }
2273
2274 int
2275 iavf_dev_rx_desc_status(void *rx_queue, uint16_t offset)
2276 {
2277         struct iavf_rx_queue *rxq = rx_queue;
2278         volatile uint64_t *status;
2279         uint64_t mask;
2280         uint32_t desc;
2281
2282         if (unlikely(offset >= rxq->nb_rx_desc))
2283                 return -EINVAL;
2284
2285         if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
2286                 return RTE_ETH_RX_DESC_UNAVAIL;
2287
2288         desc = rxq->rx_tail + offset;
2289         if (desc >= rxq->nb_rx_desc)
2290                 desc -= rxq->nb_rx_desc;
2291
2292         status = &rxq->rx_ring[desc].wb.qword1.status_error_len;
2293         mask = rte_le_to_cpu_64((1ULL << IAVF_RX_DESC_STATUS_DD_SHIFT)
2294                 << IAVF_RXD_QW1_STATUS_SHIFT);
2295         if (*status & mask)
2296                 return RTE_ETH_RX_DESC_DONE;
2297
2298         return RTE_ETH_RX_DESC_AVAIL;
2299 }
2300
2301 int
2302 iavf_dev_tx_desc_status(void *tx_queue, uint16_t offset)
2303 {
2304         struct iavf_tx_queue *txq = tx_queue;
2305         volatile uint64_t *status;
2306         uint64_t mask, expect;
2307         uint32_t desc;
2308
2309         if (unlikely(offset >= txq->nb_tx_desc))
2310                 return -EINVAL;
2311
2312         desc = txq->tx_tail + offset;
2313         /* go to next desc that has the RS bit */
2314         desc = ((desc + txq->rs_thresh - 1) / txq->rs_thresh) *
2315                 txq->rs_thresh;
2316         if (desc >= txq->nb_tx_desc) {
2317                 desc -= txq->nb_tx_desc;
2318                 if (desc >= txq->nb_tx_desc)
2319                         desc -= txq->nb_tx_desc;
2320         }
2321
2322         status = &txq->tx_ring[desc].cmd_type_offset_bsz;
2323         mask = rte_le_to_cpu_64(IAVF_TXD_QW1_DTYPE_MASK);
2324         expect = rte_cpu_to_le_64(
2325                  IAVF_TX_DESC_DTYPE_DESC_DONE << IAVF_TXD_QW1_DTYPE_SHIFT);
2326         if ((*status & mask) == expect)
2327                 return RTE_ETH_TX_DESC_DONE;
2328
2329         return RTE_ETH_TX_DESC_FULL;
2330 }
2331
2332 const uint32_t *
2333 iavf_get_default_ptype_table(void)
2334 {
2335         static const uint32_t ptype_tbl[IAVF_MAX_PKT_TYPE]
2336                 __rte_cache_aligned = {
2337                 /* L2 types */
2338                 /* [0] reserved */
2339                 [1] = RTE_PTYPE_L2_ETHER,
2340                 [2] = RTE_PTYPE_L2_ETHER_TIMESYNC,
2341                 /* [3] - [5] reserved */
2342                 [6] = RTE_PTYPE_L2_ETHER_LLDP,
2343                 /* [7] - [10] reserved */
2344                 [11] = RTE_PTYPE_L2_ETHER_ARP,
2345                 /* [12] - [21] reserved */
2346
2347                 /* Non tunneled IPv4 */
2348                 [22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2349                        RTE_PTYPE_L4_FRAG,
2350                 [23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2351                        RTE_PTYPE_L4_NONFRAG,
2352                 [24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2353                        RTE_PTYPE_L4_UDP,
2354                 /* [25] reserved */
2355                 [26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2356                        RTE_PTYPE_L4_TCP,
2357                 [27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2358                        RTE_PTYPE_L4_SCTP,
2359                 [28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2360                        RTE_PTYPE_L4_ICMP,
2361
2362                 /* IPv4 --> IPv4 */
2363                 [29] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2364                        RTE_PTYPE_TUNNEL_IP |
2365                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2366                        RTE_PTYPE_INNER_L4_FRAG,
2367                 [30] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2368                        RTE_PTYPE_TUNNEL_IP |
2369                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2370                        RTE_PTYPE_INNER_L4_NONFRAG,
2371                 [31] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2372                        RTE_PTYPE_TUNNEL_IP |
2373                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2374                        RTE_PTYPE_INNER_L4_UDP,
2375                 /* [32] reserved */
2376                 [33] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2377                        RTE_PTYPE_TUNNEL_IP |
2378                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2379                        RTE_PTYPE_INNER_L4_TCP,
2380                 [34] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2381                        RTE_PTYPE_TUNNEL_IP |
2382                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2383                        RTE_PTYPE_INNER_L4_SCTP,
2384                 [35] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2385                        RTE_PTYPE_TUNNEL_IP |
2386                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2387                        RTE_PTYPE_INNER_L4_ICMP,
2388
2389                 /* IPv4 --> IPv6 */
2390                 [36] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2391                        RTE_PTYPE_TUNNEL_IP |
2392                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2393                        RTE_PTYPE_INNER_L4_FRAG,
2394                 [37] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2395                        RTE_PTYPE_TUNNEL_IP |
2396                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2397                        RTE_PTYPE_INNER_L4_NONFRAG,
2398                 [38] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2399                        RTE_PTYPE_TUNNEL_IP |
2400                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2401                        RTE_PTYPE_INNER_L4_UDP,
2402                 /* [39] reserved */
2403                 [40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2404                        RTE_PTYPE_TUNNEL_IP |
2405                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2406                        RTE_PTYPE_INNER_L4_TCP,
2407                 [41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2408                        RTE_PTYPE_TUNNEL_IP |
2409                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2410                        RTE_PTYPE_INNER_L4_SCTP,
2411                 [42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2412                        RTE_PTYPE_TUNNEL_IP |
2413                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2414                        RTE_PTYPE_INNER_L4_ICMP,
2415
2416                 /* IPv4 --> GRE/Teredo/VXLAN */
2417                 [43] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2418                        RTE_PTYPE_TUNNEL_GRENAT,
2419
2420                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv4 */
2421                 [44] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2422                        RTE_PTYPE_TUNNEL_GRENAT |
2423                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2424                        RTE_PTYPE_INNER_L4_FRAG,
2425                 [45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2426                        RTE_PTYPE_TUNNEL_GRENAT |
2427                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2428                        RTE_PTYPE_INNER_L4_NONFRAG,
2429                 [46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2430                        RTE_PTYPE_TUNNEL_GRENAT |
2431                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2432                        RTE_PTYPE_INNER_L4_UDP,
2433                 /* [47] reserved */
2434                 [48] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2435                        RTE_PTYPE_TUNNEL_GRENAT |
2436                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2437                        RTE_PTYPE_INNER_L4_TCP,
2438                 [49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2439                        RTE_PTYPE_TUNNEL_GRENAT |
2440                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2441                        RTE_PTYPE_INNER_L4_SCTP,
2442                 [50] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2443                        RTE_PTYPE_TUNNEL_GRENAT |
2444                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2445                        RTE_PTYPE_INNER_L4_ICMP,
2446
2447                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv6 */
2448                 [51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2449                        RTE_PTYPE_TUNNEL_GRENAT |
2450                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2451                        RTE_PTYPE_INNER_L4_FRAG,
2452                 [52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2453                        RTE_PTYPE_TUNNEL_GRENAT |
2454                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2455                        RTE_PTYPE_INNER_L4_NONFRAG,
2456                 [53] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2457                        RTE_PTYPE_TUNNEL_GRENAT |
2458                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2459                        RTE_PTYPE_INNER_L4_UDP,
2460                 /* [54] reserved */
2461                 [55] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2462                        RTE_PTYPE_TUNNEL_GRENAT |
2463                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2464                        RTE_PTYPE_INNER_L4_TCP,
2465                 [56] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2466                        RTE_PTYPE_TUNNEL_GRENAT |
2467                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2468                        RTE_PTYPE_INNER_L4_SCTP,
2469                 [57] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2470                        RTE_PTYPE_TUNNEL_GRENAT |
2471                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2472                        RTE_PTYPE_INNER_L4_ICMP,
2473
2474                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC */
2475                 [58] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2476                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
2477
2478                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
2479                 [59] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2480                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2481                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2482                        RTE_PTYPE_INNER_L4_FRAG,
2483                 [60] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2484                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2485                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2486                        RTE_PTYPE_INNER_L4_NONFRAG,
2487                 [61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2488                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2489                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2490                        RTE_PTYPE_INNER_L4_UDP,
2491                 /* [62] reserved */
2492                 [63] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2493                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2494                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2495                        RTE_PTYPE_INNER_L4_TCP,
2496                 [64] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2497                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2498                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2499                        RTE_PTYPE_INNER_L4_SCTP,
2500                 [65] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2501                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2502                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2503                        RTE_PTYPE_INNER_L4_ICMP,
2504
2505                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
2506                 [66] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2507                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2508                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2509                        RTE_PTYPE_INNER_L4_FRAG,
2510                 [67] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2511                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2512                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2513                        RTE_PTYPE_INNER_L4_NONFRAG,
2514                 [68] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2515                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2516                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2517                        RTE_PTYPE_INNER_L4_UDP,
2518                 /* [69] reserved */
2519                 [70] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2520                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2521                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2522                        RTE_PTYPE_INNER_L4_TCP,
2523                 [71] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2524                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2525                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2526                        RTE_PTYPE_INNER_L4_SCTP,
2527                 [72] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2528                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2529                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2530                        RTE_PTYPE_INNER_L4_ICMP,
2531                 /* [73] - [87] reserved */
2532
2533                 /* Non tunneled IPv6 */
2534                 [88] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2535                        RTE_PTYPE_L4_FRAG,
2536                 [89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2537                        RTE_PTYPE_L4_NONFRAG,
2538                 [90] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2539                        RTE_PTYPE_L4_UDP,
2540                 /* [91] reserved */
2541                 [92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2542                        RTE_PTYPE_L4_TCP,
2543                 [93] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2544                        RTE_PTYPE_L4_SCTP,
2545                 [94] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2546                        RTE_PTYPE_L4_ICMP,
2547
2548                 /* IPv6 --> IPv4 */
2549                 [95] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2550                        RTE_PTYPE_TUNNEL_IP |
2551                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2552                        RTE_PTYPE_INNER_L4_FRAG,
2553                 [96] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2554                        RTE_PTYPE_TUNNEL_IP |
2555                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2556                        RTE_PTYPE_INNER_L4_NONFRAG,
2557                 [97] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2558                        RTE_PTYPE_TUNNEL_IP |
2559                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2560                        RTE_PTYPE_INNER_L4_UDP,
2561                 /* [98] reserved */
2562                 [99] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2563                        RTE_PTYPE_TUNNEL_IP |
2564                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2565                        RTE_PTYPE_INNER_L4_TCP,
2566                 [100] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2567                         RTE_PTYPE_TUNNEL_IP |
2568                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2569                         RTE_PTYPE_INNER_L4_SCTP,
2570                 [101] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2571                         RTE_PTYPE_TUNNEL_IP |
2572                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2573                         RTE_PTYPE_INNER_L4_ICMP,
2574
2575                 /* IPv6 --> IPv6 */
2576                 [102] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2577                         RTE_PTYPE_TUNNEL_IP |
2578                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2579                         RTE_PTYPE_INNER_L4_FRAG,
2580                 [103] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2581                         RTE_PTYPE_TUNNEL_IP |
2582                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2583                         RTE_PTYPE_INNER_L4_NONFRAG,
2584                 [104] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2585                         RTE_PTYPE_TUNNEL_IP |
2586                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2587                         RTE_PTYPE_INNER_L4_UDP,
2588                 /* [105] reserved */
2589                 [106] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2590                         RTE_PTYPE_TUNNEL_IP |
2591                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2592                         RTE_PTYPE_INNER_L4_TCP,
2593                 [107] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2594                         RTE_PTYPE_TUNNEL_IP |
2595                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2596                         RTE_PTYPE_INNER_L4_SCTP,
2597                 [108] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2598                         RTE_PTYPE_TUNNEL_IP |
2599                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2600                         RTE_PTYPE_INNER_L4_ICMP,
2601
2602                 /* IPv6 --> GRE/Teredo/VXLAN */
2603                 [109] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2604                         RTE_PTYPE_TUNNEL_GRENAT,
2605
2606                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv4 */
2607                 [110] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2608                         RTE_PTYPE_TUNNEL_GRENAT |
2609                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2610                         RTE_PTYPE_INNER_L4_FRAG,
2611                 [111] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2612                         RTE_PTYPE_TUNNEL_GRENAT |
2613                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2614                         RTE_PTYPE_INNER_L4_NONFRAG,
2615                 [112] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2616                         RTE_PTYPE_TUNNEL_GRENAT |
2617                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2618                         RTE_PTYPE_INNER_L4_UDP,
2619                 /* [113] reserved */
2620                 [114] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2621                         RTE_PTYPE_TUNNEL_GRENAT |
2622                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2623                         RTE_PTYPE_INNER_L4_TCP,
2624                 [115] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2625                         RTE_PTYPE_TUNNEL_GRENAT |
2626                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2627                         RTE_PTYPE_INNER_L4_SCTP,
2628                 [116] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2629                         RTE_PTYPE_TUNNEL_GRENAT |
2630                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2631                         RTE_PTYPE_INNER_L4_ICMP,
2632
2633                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv6 */
2634                 [117] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2635                         RTE_PTYPE_TUNNEL_GRENAT |
2636                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2637                         RTE_PTYPE_INNER_L4_FRAG,
2638                 [118] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2639                         RTE_PTYPE_TUNNEL_GRENAT |
2640                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2641                         RTE_PTYPE_INNER_L4_NONFRAG,
2642                 [119] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2643                         RTE_PTYPE_TUNNEL_GRENAT |
2644                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2645                         RTE_PTYPE_INNER_L4_UDP,
2646                 /* [120] reserved */
2647                 [121] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2648                         RTE_PTYPE_TUNNEL_GRENAT |
2649                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2650                         RTE_PTYPE_INNER_L4_TCP,
2651                 [122] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2652                         RTE_PTYPE_TUNNEL_GRENAT |
2653                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2654                         RTE_PTYPE_INNER_L4_SCTP,
2655                 [123] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2656                         RTE_PTYPE_TUNNEL_GRENAT |
2657                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2658                         RTE_PTYPE_INNER_L4_ICMP,
2659
2660                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC */
2661                 [124] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2662                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
2663
2664                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
2665                 [125] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2666                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2667                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2668                         RTE_PTYPE_INNER_L4_FRAG,
2669                 [126] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2670                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2671                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2672                         RTE_PTYPE_INNER_L4_NONFRAG,
2673                 [127] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2674                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2675                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2676                         RTE_PTYPE_INNER_L4_UDP,
2677                 /* [128] reserved */
2678                 [129] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2679                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2680                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2681                         RTE_PTYPE_INNER_L4_TCP,
2682                 [130] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2683                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2684                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2685                         RTE_PTYPE_INNER_L4_SCTP,
2686                 [131] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2687                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2688                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2689                         RTE_PTYPE_INNER_L4_ICMP,
2690
2691                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
2692                 [132] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2693                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2694                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2695                         RTE_PTYPE_INNER_L4_FRAG,
2696                 [133] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2697                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2698                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2699                         RTE_PTYPE_INNER_L4_NONFRAG,
2700                 [134] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2701                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2702                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2703                         RTE_PTYPE_INNER_L4_UDP,
2704                 /* [135] reserved */
2705                 [136] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2706                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2707                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2708                         RTE_PTYPE_INNER_L4_TCP,
2709                 [137] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2710                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2711                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2712                         RTE_PTYPE_INNER_L4_SCTP,
2713                 [138] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2714                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2715                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2716                         RTE_PTYPE_INNER_L4_ICMP,
2717                 /* [139] - [299] reserved */
2718
2719                 /* PPPoE */
2720                 [300] = RTE_PTYPE_L2_ETHER_PPPOE,
2721                 [301] = RTE_PTYPE_L2_ETHER_PPPOE,
2722
2723                 /* PPPoE --> IPv4 */
2724                 [302] = RTE_PTYPE_L2_ETHER_PPPOE |
2725                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2726                         RTE_PTYPE_L4_FRAG,
2727                 [303] = RTE_PTYPE_L2_ETHER_PPPOE |
2728                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2729                         RTE_PTYPE_L4_NONFRAG,
2730                 [304] = RTE_PTYPE_L2_ETHER_PPPOE |
2731                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2732                         RTE_PTYPE_L4_UDP,
2733                 [305] = RTE_PTYPE_L2_ETHER_PPPOE |
2734                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2735                         RTE_PTYPE_L4_TCP,
2736                 [306] = RTE_PTYPE_L2_ETHER_PPPOE |
2737                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2738                         RTE_PTYPE_L4_SCTP,
2739                 [307] = RTE_PTYPE_L2_ETHER_PPPOE |
2740                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2741                         RTE_PTYPE_L4_ICMP,
2742
2743                 /* PPPoE --> IPv6 */
2744                 [308] = RTE_PTYPE_L2_ETHER_PPPOE |
2745                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2746                         RTE_PTYPE_L4_FRAG,
2747                 [309] = RTE_PTYPE_L2_ETHER_PPPOE |
2748                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2749                         RTE_PTYPE_L4_NONFRAG,
2750                 [310] = RTE_PTYPE_L2_ETHER_PPPOE |
2751                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2752                         RTE_PTYPE_L4_UDP,
2753                 [311] = RTE_PTYPE_L2_ETHER_PPPOE |
2754                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2755                         RTE_PTYPE_L4_TCP,
2756                 [312] = RTE_PTYPE_L2_ETHER_PPPOE |
2757                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2758                         RTE_PTYPE_L4_SCTP,
2759                 [313] = RTE_PTYPE_L2_ETHER_PPPOE |
2760                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2761                         RTE_PTYPE_L4_ICMP,
2762                 /* [314] - [324] reserved */
2763
2764                 /* IPv4/IPv6 --> GTPC/GTPU */
2765                 [325] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2766                         RTE_PTYPE_TUNNEL_GTPC,
2767                 [326] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2768                         RTE_PTYPE_TUNNEL_GTPC,
2769                 [327] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2770                         RTE_PTYPE_TUNNEL_GTPC,
2771                 [328] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2772                         RTE_PTYPE_TUNNEL_GTPC,
2773                 [329] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2774                         RTE_PTYPE_TUNNEL_GTPU,
2775                 [330] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2776                         RTE_PTYPE_TUNNEL_GTPU,
2777
2778                 /* IPv4 --> GTPU --> IPv4 */
2779                 [331] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2780                         RTE_PTYPE_TUNNEL_GTPU |
2781                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2782                         RTE_PTYPE_INNER_L4_FRAG,
2783                 [332] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2784                         RTE_PTYPE_TUNNEL_GTPU |
2785                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2786                         RTE_PTYPE_INNER_L4_NONFRAG,
2787                 [333] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2788                         RTE_PTYPE_TUNNEL_GTPU |
2789                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2790                         RTE_PTYPE_INNER_L4_UDP,
2791                 [334] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2792                         RTE_PTYPE_TUNNEL_GTPU |
2793                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2794                         RTE_PTYPE_INNER_L4_TCP,
2795                 [335] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2796                         RTE_PTYPE_TUNNEL_GTPU |
2797                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2798                         RTE_PTYPE_INNER_L4_ICMP,
2799
2800                 /* IPv6 --> GTPU --> IPv4 */
2801                 [336] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2802                         RTE_PTYPE_TUNNEL_GTPU |
2803                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2804                         RTE_PTYPE_INNER_L4_FRAG,
2805                 [337] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2806                         RTE_PTYPE_TUNNEL_GTPU |
2807                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2808                         RTE_PTYPE_INNER_L4_NONFRAG,
2809                 [338] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2810                         RTE_PTYPE_TUNNEL_GTPU |
2811                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2812                         RTE_PTYPE_INNER_L4_UDP,
2813                 [339] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2814                         RTE_PTYPE_TUNNEL_GTPU |
2815                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2816                         RTE_PTYPE_INNER_L4_TCP,
2817                 [340] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2818                         RTE_PTYPE_TUNNEL_GTPU |
2819                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2820                         RTE_PTYPE_INNER_L4_ICMP,
2821
2822                 /* IPv4 --> GTPU --> IPv6 */
2823                 [341] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2824                         RTE_PTYPE_TUNNEL_GTPU |
2825                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2826                         RTE_PTYPE_INNER_L4_FRAG,
2827                 [342] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2828                         RTE_PTYPE_TUNNEL_GTPU |
2829                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2830                         RTE_PTYPE_INNER_L4_NONFRAG,
2831                 [343] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2832                         RTE_PTYPE_TUNNEL_GTPU |
2833                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2834                         RTE_PTYPE_INNER_L4_UDP,
2835                 [344] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2836                         RTE_PTYPE_TUNNEL_GTPU |
2837                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2838                         RTE_PTYPE_INNER_L4_TCP,
2839                 [345] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2840                         RTE_PTYPE_TUNNEL_GTPU |
2841                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2842                         RTE_PTYPE_INNER_L4_ICMP,
2843
2844                 /* IPv6 --> GTPU --> IPv6 */
2845                 [346] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2846                         RTE_PTYPE_TUNNEL_GTPU |
2847                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2848                         RTE_PTYPE_INNER_L4_FRAG,
2849                 [347] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2850                         RTE_PTYPE_TUNNEL_GTPU |
2851                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2852                         RTE_PTYPE_INNER_L4_NONFRAG,
2853                 [348] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2854                         RTE_PTYPE_TUNNEL_GTPU |
2855                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2856                         RTE_PTYPE_INNER_L4_UDP,
2857                 [349] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2858                         RTE_PTYPE_TUNNEL_GTPU |
2859                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2860                         RTE_PTYPE_INNER_L4_TCP,
2861                 [350] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2862                         RTE_PTYPE_TUNNEL_GTPU |
2863                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2864                         RTE_PTYPE_INNER_L4_ICMP,
2865                 /* All others reserved */
2866         };
2867
2868         return ptype_tbl;
2869 }