drivers/net/iavf/iavf_rxtx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2017 Intel Corporation
   3  */
   4
   5 #include <stdio.h>
   6 #include <stdlib.h>
   7 #include <string.h>
   8 #include <errno.h>
   9 #include <stdint.h>
  10 #include <stdarg.h>
  11 #include <unistd.h>
  12 #include <inttypes.h>
  13 #include <sys/queue.h>
  14
  15 #include <rte_string_fns.h>
  16 #include <rte_memzone.h>
  17 #include <rte_mbuf.h>
  18 #include <rte_malloc.h>
  19 #include <rte_ether.h>
  20 #include <ethdev_driver.h>
  21 #include <rte_tcp.h>
  22 #include <rte_sctp.h>
  23 #include <rte_udp.h>
  24 #include <rte_ip.h>
  25 #include <rte_net.h>
  26 #include <rte_vect.h>
  27
  28 #include "iavf.h"
  29 #include "iavf_rxtx.h"
  30 #include "iavf_ipsec_crypto.h"
  31 #include "rte_pmd_iavf.h"
  32
  33 /* Offset of mbuf dynamic field for protocol extraction's metadata */
  34 int rte_pmd_ifd_dynfield_proto_xtr_metadata_offs = -1;
  35
  36 /* Mask of mbuf dynamic flags for protocol extraction's type */
  37 uint64_t rte_pmd_ifd_dynflag_proto_xtr_vlan_mask;
  38 uint64_t rte_pmd_ifd_dynflag_proto_xtr_ipv4_mask;
  39 uint64_t rte_pmd_ifd_dynflag_proto_xtr_ipv6_mask;
  40 uint64_t rte_pmd_ifd_dynflag_proto_xtr_ipv6_flow_mask;
  41 uint64_t rte_pmd_ifd_dynflag_proto_xtr_tcp_mask;
  42 uint64_t rte_pmd_ifd_dynflag_proto_xtr_ip_offset_mask;
  43 uint64_t rte_pmd_ifd_dynflag_proto_xtr_ipsec_crypto_said_mask;
  44
  45 uint8_t
  46 iavf_proto_xtr_type_to_rxdid(uint8_t flex_type)
  47 {
  48         static uint8_t rxdid_map[] = {
  49                 [IAVF_PROTO_XTR_NONE]      = IAVF_RXDID_COMMS_OVS_1,
  50                 [IAVF_PROTO_XTR_VLAN]      = IAVF_RXDID_COMMS_AUX_VLAN,
  51                 [IAVF_PROTO_XTR_IPV4]      = IAVF_RXDID_COMMS_AUX_IPV4,
  52                 [IAVF_PROTO_XTR_IPV6]      = IAVF_RXDID_COMMS_AUX_IPV6,
  53                 [IAVF_PROTO_XTR_IPV6_FLOW] = IAVF_RXDID_COMMS_AUX_IPV6_FLOW,
  54                 [IAVF_PROTO_XTR_TCP]       = IAVF_RXDID_COMMS_AUX_TCP,
  55                 [IAVF_PROTO_XTR_IP_OFFSET] = IAVF_RXDID_COMMS_AUX_IP_OFFSET,
  56                 [IAVF_PROTO_XTR_IPSEC_CRYPTO_SAID] =
  57                                 IAVF_RXDID_COMMS_IPSEC_CRYPTO,
  58         };
  59
  60         return flex_type < RTE_DIM(rxdid_map) ?
  61                                 rxdid_map[flex_type] : IAVF_RXDID_COMMS_OVS_1;
  62 }
  63
  64 static int
  65 iavf_monitor_callback(const uint64_t value,
  66                 const uint64_t arg[RTE_POWER_MONITOR_OPAQUE_SZ] __rte_unused)
  67 {
  68         const uint64_t m = rte_cpu_to_le_64(1 << IAVF_RX_DESC_STATUS_DD_SHIFT);
  69         /*
  70          * we expect the DD bit to be set to 1 if this descriptor was already
  71          * written to.
  72          */
  73         return (value & m) == m ? -1 : 0;
  74 }
  75
  76 int
  77 iavf_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc)
  78 {
  79         struct iavf_rx_queue *rxq = rx_queue;
  80         volatile union iavf_rx_desc *rxdp;
  81         uint16_t desc;
  82
  83         desc = rxq->rx_tail;
  84         rxdp = &rxq->rx_ring[desc];
  85         /* watch for changes in status bit */
  86         pmc->addr = &rxdp->wb.qword1.status_error_len;
  87
  88         /* comparison callback */
  89         pmc->fn = iavf_monitor_callback;
  90
  91         /* registers are 64-bit */
  92         pmc->size = sizeof(uint64_t);
  93
  94         return 0;
  95 }
  96
  97 static inline int
  98 check_rx_thresh(uint16_t nb_desc, uint16_t thresh)
  99 {
 100         /* The following constraints must be satisfied:
 101          *   thresh < rxq->nb_rx_desc
 102          */
 103         if (thresh >= nb_desc) {
 104                 PMD_INIT_LOG(ERR, "rx_free_thresh (%u) must be less than %u",
 105                              thresh, nb_desc);
 106                 return -EINVAL;
 107         }
 108         return 0;
 109 }
 110
 111 static inline int
 112 check_tx_thresh(uint16_t nb_desc, uint16_t tx_rs_thresh,
 113                 uint16_t tx_free_thresh)
 114 {
 115         /* TX descriptors will have their RS bit set after tx_rs_thresh
 116          * descriptors have been used. The TX descriptor ring will be cleaned
 117          * after tx_free_thresh descriptors are used or if the number of
 118          * descriptors required to transmit a packet is greater than the
 119          * number of free TX descriptors.
 120          *
 121          * The following constraints must be satisfied:
 122          *  - tx_rs_thresh must be less than the size of the ring minus 2.
 123          *  - tx_free_thresh must be less than the size of the ring minus 3.
 124          *  - tx_rs_thresh must be less than or equal to tx_free_thresh.
 125          *  - tx_rs_thresh must be a divisor of the ring size.
 126          *
 127          * One descriptor in the TX ring is used as a sentinel to avoid a H/W
 128          * race condition, hence the maximum threshold constraints. When set
 129          * to zero use default values.
 130          */
 131         if (tx_rs_thresh >= (nb_desc - 2)) {
 132                 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be less than the "
 133                              "number of TX descriptors (%u) minus 2",
 134                              tx_rs_thresh, nb_desc);
 135                 return -EINVAL;
 136         }
 137         if (tx_free_thresh >= (nb_desc - 3)) {
 138                 PMD_INIT_LOG(ERR, "tx_free_thresh (%u) must be less than the "
 139                              "number of TX descriptors (%u) minus 3.",
 140                              tx_free_thresh, nb_desc);
 141                 return -EINVAL;
 142         }
 143         if (tx_rs_thresh > tx_free_thresh) {
 144                 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be less than or "
 145                              "equal to tx_free_thresh (%u).",
 146                              tx_rs_thresh, tx_free_thresh);
 147                 return -EINVAL;
 148         }
 149         if ((nb_desc % tx_rs_thresh) != 0) {
 150                 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be a divisor of the "
 151                              "number of TX descriptors (%u).",
 152                              tx_rs_thresh, nb_desc);
 153                 return -EINVAL;
 154         }
 155
 156         return 0;
 157 }
 158
 159 static inline bool
 160 check_rx_vec_allow(struct iavf_rx_queue *rxq)
 161 {
 162         if (rxq->rx_free_thresh >= IAVF_VPMD_RX_MAX_BURST &&
 163             rxq->nb_rx_desc % rxq->rx_free_thresh == 0) {
 164                 PMD_INIT_LOG(DEBUG, "Vector Rx can be enabled on this rxq.");
 165                 return true;
 166         }
 167
 168         PMD_INIT_LOG(DEBUG, "Vector Rx cannot be enabled on this rxq.");
 169         return false;
 170 }
 171
 172 static inline bool
 173 check_tx_vec_allow(struct iavf_tx_queue *txq)
 174 {
 175         if (!(txq->offloads & IAVF_TX_NO_VECTOR_FLAGS) &&
 176             txq->rs_thresh >= IAVF_VPMD_TX_MAX_BURST &&
 177             txq->rs_thresh <= IAVF_VPMD_TX_MAX_FREE_BUF) {
 178                 PMD_INIT_LOG(DEBUG, "Vector tx can be enabled on this txq.");
 179                 return true;
 180         }
 181         PMD_INIT_LOG(DEBUG, "Vector Tx cannot be enabled on this txq.");
 182         return false;
 183 }
 184
 185 static inline bool
 186 check_rx_bulk_allow(struct iavf_rx_queue *rxq)
 187 {
 188         int ret = true;
 189
 190         if (!(rxq->rx_free_thresh >= IAVF_RX_MAX_BURST)) {
 191                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 192                              "rxq->rx_free_thresh=%d, "
 193                              "IAVF_RX_MAX_BURST=%d",
 194                              rxq->rx_free_thresh, IAVF_RX_MAX_BURST);
 195                 ret = false;
 196         } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
 197                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 198                              "rxq->nb_rx_desc=%d, "
 199                              "rxq->rx_free_thresh=%d",
 200                              rxq->nb_rx_desc, rxq->rx_free_thresh);
 201                 ret = false;
 202         }
 203         return ret;
 204 }
 205
 206 static inline void
 207 reset_rx_queue(struct iavf_rx_queue *rxq)
 208 {
 209         uint16_t len;
 210         uint32_t i;
 211
 212         if (!rxq)
 213                 return;
 214
 215         len = rxq->nb_rx_desc + IAVF_RX_MAX_BURST;
 216
 217         for (i = 0; i < len * sizeof(union iavf_rx_desc); i++)
 218                 ((volatile char *)rxq->rx_ring)[i] = 0;
 219
 220         memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
 221
 222         for (i = 0; i < IAVF_RX_MAX_BURST; i++)
 223                 rxq->sw_ring[rxq->nb_rx_desc + i] = &rxq->fake_mbuf;
 224
 225         /* for rx bulk */
 226         rxq->rx_nb_avail = 0;
 227         rxq->rx_next_avail = 0;
 228         rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
 229
 230         rxq->rx_tail = 0;
 231         rxq->nb_rx_hold = 0;
 232
 233         rte_pktmbuf_free(rxq->pkt_first_seg);
 234
 235         rxq->pkt_first_seg = NULL;
 236         rxq->pkt_last_seg = NULL;
 237         rxq->rxrearm_nb = 0;
 238         rxq->rxrearm_start = 0;
 239 }
 240
 241 static inline void
 242 reset_tx_queue(struct iavf_tx_queue *txq)
 243 {
 244         struct iavf_tx_entry *txe;
 245         uint32_t i, size;
 246         uint16_t prev;
 247
 248         if (!txq) {
 249                 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
 250                 return;
 251         }
 252
 253         txe = txq->sw_ring;
 254         size = sizeof(struct iavf_tx_desc) * txq->nb_tx_desc;
 255         for (i = 0; i < size; i++)
 256                 ((volatile char *)txq->tx_ring)[i] = 0;
 257
 258         prev = (uint16_t)(txq->nb_tx_desc - 1);
 259         for (i = 0; i < txq->nb_tx_desc; i++) {
 260                 txq->tx_ring[i].cmd_type_offset_bsz =
 261                         rte_cpu_to_le_64(IAVF_TX_DESC_DTYPE_DESC_DONE);
 262                 txe[i].mbuf =  NULL;
 263                 txe[i].last_id = i;
 264                 txe[prev].next_id = i;
 265                 prev = i;
 266         }
 267
 268         txq->tx_tail = 0;
 269         txq->nb_used = 0;
 270
 271         txq->last_desc_cleaned = txq->nb_tx_desc - 1;
 272         txq->nb_free = txq->nb_tx_desc - 1;
 273
 274         txq->next_dd = txq->rs_thresh - 1;
 275         txq->next_rs = txq->rs_thresh - 1;
 276 }
 277
 278 static int
 279 alloc_rxq_mbufs(struct iavf_rx_queue *rxq)
 280 {
 281         volatile union iavf_rx_desc *rxd;
 282         struct rte_mbuf *mbuf = NULL;
 283         uint64_t dma_addr;
 284         uint16_t i, j;
 285
 286         for (i = 0; i < rxq->nb_rx_desc; i++) {
 287                 mbuf = rte_mbuf_raw_alloc(rxq->mp);
 288                 if (unlikely(!mbuf)) {
 289                         for (j = 0; j < i; j++) {
 290                                 rte_pktmbuf_free_seg(rxq->sw_ring[j]);
 291                                 rxq->sw_ring[j] = NULL;
 292                         }
 293                         PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
 294                         return -ENOMEM;
 295                 }
 296
 297                 rte_mbuf_refcnt_set(mbuf, 1);
 298                 mbuf->next = NULL;
 299                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
 300                 mbuf->nb_segs = 1;
 301                 mbuf->port = rxq->port_id;
 302
 303                 dma_addr =
 304                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
 305
 306                 rxd = &rxq->rx_ring[i];
 307                 rxd->read.pkt_addr = dma_addr;
 308                 rxd->read.hdr_addr = 0;
 309 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
 310                 rxd->read.rsvd1 = 0;
 311                 rxd->read.rsvd2 = 0;
 312 #endif
 313
 314                 rxq->sw_ring[i] = mbuf;
 315         }
 316
 317         return 0;
 318 }
 319
 320 static inline void
 321 release_rxq_mbufs(struct iavf_rx_queue *rxq)
 322 {
 323         uint16_t i;
 324
 325         if (!rxq->sw_ring)
 326                 return;
 327
 328         for (i = 0; i < rxq->nb_rx_desc; i++) {
 329                 if (rxq->sw_ring[i]) {
 330                         rte_pktmbuf_free_seg(rxq->sw_ring[i]);
 331                         rxq->sw_ring[i] = NULL;
 332                 }
 333         }
 334
 335         /* for rx bulk */
 336         if (rxq->rx_nb_avail == 0)
 337                 return;
 338         for (i = 0; i < rxq->rx_nb_avail; i++) {
 339                 struct rte_mbuf *mbuf;
 340
 341                 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
 342                 rte_pktmbuf_free_seg(mbuf);
 343         }
 344         rxq->rx_nb_avail = 0;
 345 }
 346
 347 static inline void
 348 release_txq_mbufs(struct iavf_tx_queue *txq)
 349 {
 350         uint16_t i;
 351
 352         if (!txq || !txq->sw_ring) {
 353                 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
 354                 return;
 355         }
 356
 357         for (i = 0; i < txq->nb_tx_desc; i++) {
 358                 if (txq->sw_ring[i].mbuf) {
 359                         rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
 360                         txq->sw_ring[i].mbuf = NULL;
 361                 }
 362         }
 363 }
 364
 365 static const
 366 struct iavf_rxq_ops iavf_rxq_release_mbufs_ops[] = {
 367         [IAVF_REL_MBUFS_DEFAULT].release_mbufs = release_rxq_mbufs,
 368 #ifdef RTE_ARCH_X86
 369         [IAVF_REL_MBUFS_SSE_VEC].release_mbufs = iavf_rx_queue_release_mbufs_sse,
 370 #endif
 371 };
 372
 373 static const
 374 struct iavf_txq_ops iavf_txq_release_mbufs_ops[] = {
 375         [IAVF_REL_MBUFS_DEFAULT].release_mbufs = release_txq_mbufs,
 376 #ifdef RTE_ARCH_X86
 377         [IAVF_REL_MBUFS_SSE_VEC].release_mbufs = iavf_tx_queue_release_mbufs_sse,
 378 #ifdef CC_AVX512_SUPPORT
 379         [IAVF_REL_MBUFS_AVX512_VEC].release_mbufs = iavf_tx_queue_release_mbufs_avx512,
 380 #endif
 381 #endif
 382
 383 };
 384
 385 static inline void
 386 iavf_rxd_to_pkt_fields_by_comms_ovs(__rte_unused struct iavf_rx_queue *rxq,
 387                                     struct rte_mbuf *mb,
 388                                     volatile union iavf_rx_flex_desc *rxdp)
 389 {
 390         volatile struct iavf_32b_rx_flex_desc_comms_ovs *desc =
 391                         (volatile struct iavf_32b_rx_flex_desc_comms_ovs *)rxdp;
 392 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
 393         uint16_t stat_err;
 394 #endif
 395
 396         if (desc->flow_id != 0xFFFFFFFF) {
 397                 mb->ol_flags |= RTE_MBUF_F_RX_FDIR | RTE_MBUF_F_RX_FDIR_ID;
 398                 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
 399         }
 400
 401 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
 402         stat_err = rte_le_to_cpu_16(desc->status_error0);
 403         if (likely(stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
 404                 mb->ol_flags |= RTE_MBUF_F_RX_RSS_HASH;
 405                 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
 406         }
 407 #endif
 408 }
 409
 410 static inline void
 411 iavf_rxd_to_pkt_fields_by_comms_aux_v1(struct iavf_rx_queue *rxq,
 412                                        struct rte_mbuf *mb,
 413                                        volatile union iavf_rx_flex_desc *rxdp)
 414 {
 415         volatile struct iavf_32b_rx_flex_desc_comms *desc =
 416                         (volatile struct iavf_32b_rx_flex_desc_comms *)rxdp;
 417         uint16_t stat_err;
 418
 419         stat_err = rte_le_to_cpu_16(desc->status_error0);
 420         if (likely(stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
 421                 mb->ol_flags |= RTE_MBUF_F_RX_RSS_HASH;
 422                 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
 423         }
 424
 425 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
 426         if (desc->flow_id != 0xFFFFFFFF) {
 427                 mb->ol_flags |= RTE_MBUF_F_RX_FDIR | RTE_MBUF_F_RX_FDIR_ID;
 428                 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
 429         }
 430
 431         if (rxq->xtr_ol_flag) {
 432                 uint32_t metadata = 0;
 433
 434                 stat_err = rte_le_to_cpu_16(desc->status_error1);
 435
 436                 if (stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS1_XTRMD4_VALID_S))
 437                         metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux0);
 438
 439                 if (stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS1_XTRMD5_VALID_S))
 440                         metadata |=
 441                                 rte_le_to_cpu_16(desc->flex_ts.flex.aux1) << 16;
 442
 443                 if (metadata) {
 444                         mb->ol_flags |= rxq->xtr_ol_flag;
 445
 446                         *RTE_PMD_IFD_DYNF_PROTO_XTR_METADATA(mb) = metadata;
 447                 }
 448         }
 449 #endif
 450 }
 451
 452 static inline void
 453 iavf_rxd_to_pkt_fields_by_comms_aux_v2(struct iavf_rx_queue *rxq,
 454                                        struct rte_mbuf *mb,
 455                                        volatile union iavf_rx_flex_desc *rxdp)
 456 {
 457         volatile struct iavf_32b_rx_flex_desc_comms *desc =
 458                         (volatile struct iavf_32b_rx_flex_desc_comms *)rxdp;
 459         uint16_t stat_err;
 460
 461         stat_err = rte_le_to_cpu_16(desc->status_error0);
 462         if (likely(stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
 463                 mb->ol_flags |= RTE_MBUF_F_RX_RSS_HASH;
 464                 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
 465         }
 466
 467 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
 468         if (desc->flow_id != 0xFFFFFFFF) {
 469                 mb->ol_flags |= RTE_MBUF_F_RX_FDIR | RTE_MBUF_F_RX_FDIR_ID;
 470                 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
 471         }
 472
 473         if (rxq->xtr_ol_flag) {
 474                 uint32_t metadata = 0;
 475
 476                 if (desc->flex_ts.flex.aux0 != 0xFFFF)
 477                         metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux0);
 478                 else if (desc->flex_ts.flex.aux1 != 0xFFFF)
 479                         metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux1);
 480
 481                 if (metadata) {
 482                         mb->ol_flags |= rxq->xtr_ol_flag;
 483
 484                         *RTE_PMD_IFD_DYNF_PROTO_XTR_METADATA(mb) = metadata;
 485                 }
 486         }
 487 #endif
 488 }
 489
 490 static const
 491 iavf_rxd_to_pkt_fields_t rxd_to_pkt_fields_ops[IAVF_RXDID_LAST + 1] = {
 492         [IAVF_RXDID_LEGACY_0] = iavf_rxd_to_pkt_fields_by_comms_ovs,
 493         [IAVF_RXDID_LEGACY_1] = iavf_rxd_to_pkt_fields_by_comms_ovs,
 494         [IAVF_RXDID_COMMS_AUX_VLAN] = iavf_rxd_to_pkt_fields_by_comms_aux_v1,
 495         [IAVF_RXDID_COMMS_AUX_IPV4] = iavf_rxd_to_pkt_fields_by_comms_aux_v1,
 496         [IAVF_RXDID_COMMS_AUX_IPV6] = iavf_rxd_to_pkt_fields_by_comms_aux_v1,
 497         [IAVF_RXDID_COMMS_AUX_IPV6_FLOW] =
 498                 iavf_rxd_to_pkt_fields_by_comms_aux_v1,
 499         [IAVF_RXDID_COMMS_AUX_TCP] = iavf_rxd_to_pkt_fields_by_comms_aux_v1,
 500         [IAVF_RXDID_COMMS_AUX_IP_OFFSET] =
 501                 iavf_rxd_to_pkt_fields_by_comms_aux_v2,
 502         [IAVF_RXDID_COMMS_IPSEC_CRYPTO] =
 503                 iavf_rxd_to_pkt_fields_by_comms_aux_v2,
 504         [IAVF_RXDID_COMMS_OVS_1] = iavf_rxd_to_pkt_fields_by_comms_ovs,
 505 };
 506
 507 static void
 508 iavf_select_rxd_to_pkt_fields_handler(struct iavf_rx_queue *rxq, uint32_t rxdid)
 509 {
 510         rxq->rxdid = rxdid;
 511
 512         switch (rxdid) {
 513         case IAVF_RXDID_COMMS_AUX_VLAN:
 514                 rxq->xtr_ol_flag = rte_pmd_ifd_dynflag_proto_xtr_vlan_mask;
 515                 break;
 516         case IAVF_RXDID_COMMS_AUX_IPV4:
 517                 rxq->xtr_ol_flag = rte_pmd_ifd_dynflag_proto_xtr_ipv4_mask;
 518                 break;
 519         case IAVF_RXDID_COMMS_AUX_IPV6:
 520                 rxq->xtr_ol_flag = rte_pmd_ifd_dynflag_proto_xtr_ipv6_mask;
 521                 break;
 522         case IAVF_RXDID_COMMS_AUX_IPV6_FLOW:
 523                 rxq->xtr_ol_flag =
 524                         rte_pmd_ifd_dynflag_proto_xtr_ipv6_flow_mask;
 525                 break;
 526         case IAVF_RXDID_COMMS_AUX_TCP:
 527                 rxq->xtr_ol_flag = rte_pmd_ifd_dynflag_proto_xtr_tcp_mask;
 528                 break;
 529         case IAVF_RXDID_COMMS_AUX_IP_OFFSET:
 530                 rxq->xtr_ol_flag =
 531                         rte_pmd_ifd_dynflag_proto_xtr_ip_offset_mask;
 532                 break;
 533         case IAVF_RXDID_COMMS_IPSEC_CRYPTO:
 534                 rxq->xtr_ol_flag =
 535                         rte_pmd_ifd_dynflag_proto_xtr_ipsec_crypto_said_mask;
 536                 break;
 537         case IAVF_RXDID_COMMS_OVS_1:
 538         case IAVF_RXDID_LEGACY_0:
 539         case IAVF_RXDID_LEGACY_1:
 540                 break;
 541         default:
 542                 /* update this according to the RXDID for FLEX_DESC_NONE */
 543                 rxq->rxdid = IAVF_RXDID_COMMS_OVS_1;
 544                 break;
 545         }
 546
 547         if (!rte_pmd_ifd_dynf_proto_xtr_metadata_avail())
 548                 rxq->xtr_ol_flag = 0;
 549 }
 550
 551 int
 552 iavf_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 553                        uint16_t nb_desc, unsigned int socket_id,
 554                        const struct rte_eth_rxconf *rx_conf,
 555                        struct rte_mempool *mp)
 556 {
 557         struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 558         struct iavf_adapter *ad =
 559                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 560         struct iavf_info *vf =
 561                 IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 562         struct iavf_vsi *vsi = &vf->vsi;
 563         struct iavf_rx_queue *rxq;
 564         const struct rte_memzone *mz;
 565         uint32_t ring_size;
 566         uint8_t proto_xtr;
 567         uint16_t len;
 568         uint16_t rx_free_thresh;
 569         uint64_t offloads;
 570
 571         PMD_INIT_FUNC_TRACE();
 572
 573         if (ad->closed)
 574                 return -EIO;
 575
 576         offloads = rx_conf->offloads | dev->data->dev_conf.rxmode.offloads;
 577
 578         if (nb_desc % IAVF_ALIGN_RING_DESC != 0 ||
 579             nb_desc > IAVF_MAX_RING_DESC ||
 580             nb_desc < IAVF_MIN_RING_DESC) {
 581                 PMD_INIT_LOG(ERR, "Number (%u) of receive descriptors is "
 582                              "invalid", nb_desc);
 583                 return -EINVAL;
 584         }
 585
 586         /* Check free threshold */
 587         rx_free_thresh = (rx_conf->rx_free_thresh == 0) ?
 588                          IAVF_DEFAULT_RX_FREE_THRESH :
 589                          rx_conf->rx_free_thresh;
 590         if (check_rx_thresh(nb_desc, rx_free_thresh) != 0)
 591                 return -EINVAL;
 592
 593         /* Free memory if needed */
 594         if (dev->data->rx_queues[queue_idx]) {
 595                 iavf_dev_rx_queue_release(dev, queue_idx);
 596                 dev->data->rx_queues[queue_idx] = NULL;
 597         }
 598
 599         /* Allocate the rx queue data structure */
 600         rxq = rte_zmalloc_socket("iavf rxq",
 601                                  sizeof(struct iavf_rx_queue),
 602                                  RTE_CACHE_LINE_SIZE,
 603                                  socket_id);
 604         if (!rxq) {
 605                 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
 606                              "rx queue data structure");
 607                 return -ENOMEM;
 608         }
 609
 610         if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC) {
 611                 proto_xtr = vf->proto_xtr ? vf->proto_xtr[queue_idx] :
 612                                 IAVF_PROTO_XTR_NONE;
 613                 rxq->rxdid = iavf_proto_xtr_type_to_rxdid(proto_xtr);
 614                 rxq->proto_xtr = proto_xtr;
 615         } else {
 616                 rxq->rxdid = IAVF_RXDID_LEGACY_1;
 617                 rxq->proto_xtr = IAVF_PROTO_XTR_NONE;
 618         }
 619
 620         if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_VLAN_V2) {
 621                 struct virtchnl_vlan_supported_caps *stripping_support =
 622                                 &vf->vlan_v2_caps.offloads.stripping_support;
 623                 uint32_t stripping_cap;
 624
 625                 if (stripping_support->outer)
 626                         stripping_cap = stripping_support->outer;
 627                 else
 628                         stripping_cap = stripping_support->inner;
 629
 630                 if (stripping_cap & VIRTCHNL_VLAN_TAG_LOCATION_L2TAG1)
 631                         rxq->rx_flags = IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG1;
 632                 else if (stripping_cap & VIRTCHNL_VLAN_TAG_LOCATION_L2TAG2_2)
 633                         rxq->rx_flags = IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG2_2;
 634         } else {
 635                 rxq->rx_flags = IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG1;
 636         }
 637
 638         iavf_select_rxd_to_pkt_fields_handler(rxq, rxq->rxdid);
 639
 640         rxq->mp = mp;
 641         rxq->nb_rx_desc = nb_desc;
 642         rxq->rx_free_thresh = rx_free_thresh;
 643         rxq->queue_id = queue_idx;
 644         rxq->port_id = dev->data->port_id;
 645         rxq->rx_deferred_start = rx_conf->rx_deferred_start;
 646         rxq->rx_hdr_len = 0;
 647         rxq->vsi = vsi;
 648         rxq->offloads = offloads;
 649
 650         if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_KEEP_CRC)
 651                 rxq->crc_len = RTE_ETHER_CRC_LEN;
 652         else
 653                 rxq->crc_len = 0;
 654
 655         len = rte_pktmbuf_data_room_size(rxq->mp) - RTE_PKTMBUF_HEADROOM;
 656         rxq->rx_buf_len = RTE_ALIGN_FLOOR(len, (1 << IAVF_RXQ_CTX_DBUFF_SHIFT));
 657
 658         /* Allocate the software ring. */
 659         len = nb_desc + IAVF_RX_MAX_BURST;
 660         rxq->sw_ring =
 661                 rte_zmalloc_socket("iavf rx sw ring",
 662                                    sizeof(struct rte_mbuf *) * len,
 663                                    RTE_CACHE_LINE_SIZE,
 664                                    socket_id);
 665         if (!rxq->sw_ring) {
 666                 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW ring");
 667                 rte_free(rxq);
 668                 return -ENOMEM;
 669         }
 670
 671         /* Allocate the maximum number of RX ring hardware descriptor with
 672          * a little more to support bulk allocate.
 673          */
 674         len = IAVF_MAX_RING_DESC + IAVF_RX_MAX_BURST;
 675         ring_size = RTE_ALIGN(len * sizeof(union iavf_rx_desc),
 676                               IAVF_DMA_MEM_ALIGN);
 677         mz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
 678                                       ring_size, IAVF_RING_BASE_ALIGN,
 679                                       socket_id);
 680         if (!mz) {
 681                 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for RX");
 682                 rte_free(rxq->sw_ring);
 683                 rte_free(rxq);
 684                 return -ENOMEM;
 685         }
 686         /* Zero all the descriptors in the ring. */
 687         memset(mz->addr, 0, ring_size);
 688         rxq->rx_ring_phys_addr = mz->iova;
 689         rxq->rx_ring = (union iavf_rx_desc *)mz->addr;
 690
 691         rxq->mz = mz;
 692         reset_rx_queue(rxq);
 693         rxq->q_set = true;
 694         dev->data->rx_queues[queue_idx] = rxq;
 695         rxq->qrx_tail = hw->hw_addr + IAVF_QRX_TAIL1(rxq->queue_id);
 696         rxq->rel_mbufs_type = IAVF_REL_MBUFS_DEFAULT;
 697
 698         if (check_rx_bulk_allow(rxq) == true) {
 699                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
 700                              "satisfied. Rx Burst Bulk Alloc function will be "
 701                              "used on port=%d, queue=%d.",
 702                              rxq->port_id, rxq->queue_id);
 703         } else {
 704                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
 705                              "not satisfied, Scattered Rx is requested "
 706                              "on port=%d, queue=%d.",
 707                              rxq->port_id, rxq->queue_id);
 708                 ad->rx_bulk_alloc_allowed = false;
 709         }
 710
 711         if (check_rx_vec_allow(rxq) == false)
 712                 ad->rx_vec_allowed = false;
 713
 714         return 0;
 715 }
 716
 717 int
 718 iavf_dev_tx_queue_setup(struct rte_eth_dev *dev,
 719                        uint16_t queue_idx,
 720                        uint16_t nb_desc,
 721                        unsigned int socket_id,
 722                        const struct rte_eth_txconf *tx_conf)
 723 {
 724         struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 725         struct iavf_adapter *adapter =
 726                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 727         struct iavf_info *vf =
 728                 IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 729         struct iavf_tx_queue *txq;
 730         const struct rte_memzone *mz;
 731         uint32_t ring_size;
 732         uint16_t tx_rs_thresh, tx_free_thresh;
 733         uint64_t offloads;
 734
 735         PMD_INIT_FUNC_TRACE();
 736
 737         if (adapter->closed)
 738                 return -EIO;
 739
 740         offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
 741
 742         if (nb_desc % IAVF_ALIGN_RING_DESC != 0 ||
 743             nb_desc > IAVF_MAX_RING_DESC ||
 744             nb_desc < IAVF_MIN_RING_DESC) {
 745                 PMD_INIT_LOG(ERR, "Number (%u) of transmit descriptors is "
 746                             "invalid", nb_desc);
 747                 return -EINVAL;
 748         }
 749
 750         tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
 751                 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
 752         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
 753                 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
 754         if (check_tx_thresh(nb_desc, tx_rs_thresh, tx_free_thresh) != 0)
 755                 return -EINVAL;
 756
 757         /* Free memory if needed. */
 758         if (dev->data->tx_queues[queue_idx]) {
 759                 iavf_dev_tx_queue_release(dev, queue_idx);
 760                 dev->data->tx_queues[queue_idx] = NULL;
 761         }
 762
 763         /* Allocate the TX queue data structure. */
 764         txq = rte_zmalloc_socket("iavf txq",
 765                                  sizeof(struct iavf_tx_queue),
 766                                  RTE_CACHE_LINE_SIZE,
 767                                  socket_id);
 768         if (!txq) {
 769                 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
 770                              "tx queue structure");
 771                 return -ENOMEM;
 772         }
 773
 774         if (adapter->vf.vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_VLAN_V2) {
 775                 struct virtchnl_vlan_supported_caps *insertion_support =
 776                         &adapter->vf.vlan_v2_caps.offloads.insertion_support;
 777                 uint32_t insertion_cap;
 778
 779                 if (insertion_support->outer)
 780                         insertion_cap = insertion_support->outer;
 781                 else
 782                         insertion_cap = insertion_support->inner;
 783
 784                 if (insertion_cap & VIRTCHNL_VLAN_TAG_LOCATION_L2TAG1)
 785                         txq->vlan_flag = IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG1;
 786                 else if (insertion_cap & VIRTCHNL_VLAN_TAG_LOCATION_L2TAG2)
 787                         txq->vlan_flag = IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG2;
 788         } else {
 789                 txq->vlan_flag = IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG1;
 790         }
 791
 792         txq->nb_tx_desc = nb_desc;
 793         txq->rs_thresh = tx_rs_thresh;
 794         txq->free_thresh = tx_free_thresh;
 795         txq->queue_id = queue_idx;
 796         txq->port_id = dev->data->port_id;
 797         txq->offloads = offloads;
 798         txq->tx_deferred_start = tx_conf->tx_deferred_start;
 799
 800         if (iavf_ipsec_crypto_supported(adapter))
 801                 txq->ipsec_crypto_pkt_md_offset =
 802                         iavf_security_get_pkt_md_offset(adapter);
 803
 804         /* Allocate software ring */
 805         txq->sw_ring =
 806                 rte_zmalloc_socket("iavf tx sw ring",
 807                                    sizeof(struct iavf_tx_entry) * nb_desc,
 808                                    RTE_CACHE_LINE_SIZE,
 809                                    socket_id);
 810         if (!txq->sw_ring) {
 811                 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW TX ring");
 812                 rte_free(txq);
 813                 return -ENOMEM;
 814         }
 815
 816         /* Allocate TX hardware ring descriptors. */
 817         ring_size = sizeof(struct iavf_tx_desc) * IAVF_MAX_RING_DESC;
 818         ring_size = RTE_ALIGN(ring_size, IAVF_DMA_MEM_ALIGN);
 819         mz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
 820                                       ring_size, IAVF_RING_BASE_ALIGN,
 821                                       socket_id);
 822         if (!mz) {
 823                 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for TX");
 824                 rte_free(txq->sw_ring);
 825                 rte_free(txq);
 826                 return -ENOMEM;
 827         }
 828         txq->tx_ring_phys_addr = mz->iova;
 829         txq->tx_ring = (struct iavf_tx_desc *)mz->addr;
 830
 831         txq->mz = mz;
 832         reset_tx_queue(txq);
 833         txq->q_set = true;
 834         dev->data->tx_queues[queue_idx] = txq;
 835         txq->qtx_tail = hw->hw_addr + IAVF_QTX_TAIL1(queue_idx);
 836         txq->rel_mbufs_type = IAVF_REL_MBUFS_DEFAULT;
 837
 838         if (check_tx_vec_allow(txq) == false) {
 839                 struct iavf_adapter *ad =
 840                         IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 841                 ad->tx_vec_allowed = false;
 842         }
 843
 844         if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_QOS &&
 845             vf->tm_conf.committed) {
 846                 int tc;
 847                 for (tc = 0; tc < vf->qos_cap->num_elem; tc++) {
 848                         if (txq->queue_id >= vf->qtc_map[tc].start_queue_id &&
 849                             txq->queue_id < (vf->qtc_map[tc].start_queue_id +
 850                             vf->qtc_map[tc].queue_count))
 851                                 break;
 852                 }
 853                 if (tc >= vf->qos_cap->num_elem) {
 854                         PMD_INIT_LOG(ERR, "Queue TC mapping is not correct");
 855                         return -EINVAL;
 856                 }
 857                 txq->tc = tc;
 858         }
 859
 860         return 0;
 861 }
 862
 863 int
 864 iavf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 865 {
 866         struct iavf_adapter *adapter =
 867                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 868         struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 869         struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 870         struct iavf_rx_queue *rxq;
 871         int err = 0;
 872
 873         PMD_DRV_FUNC_TRACE();
 874
 875         if (rx_queue_id >= dev->data->nb_rx_queues)
 876                 return -EINVAL;
 877
 878         rxq = dev->data->rx_queues[rx_queue_id];
 879
 880         err = alloc_rxq_mbufs(rxq);
 881         if (err) {
 882                 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
 883                 return err;
 884         }
 885
 886         rte_wmb();
 887
 888         /* Init the RX tail register. */
 889         IAVF_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 890         IAVF_WRITE_FLUSH(hw);
 891
 892         /* Ready to switch the queue on */
 893         if (!vf->lv_enabled)
 894                 err = iavf_switch_queue(adapter, rx_queue_id, true, true);
 895         else
 896                 err = iavf_switch_queue_lv(adapter, rx_queue_id, true, true);
 897
 898         if (err) {
 899                 release_rxq_mbufs(rxq);
 900                 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
 901                             rx_queue_id);
 902         } else {
 903                 dev->data->rx_queue_state[rx_queue_id] =
 904                         RTE_ETH_QUEUE_STATE_STARTED;
 905         }
 906
 907         if (dev->data->dev_conf.rxmode.offloads &
 908             RTE_ETH_RX_OFFLOAD_TIMESTAMP) {
 909                 if (iavf_get_phc_time(rxq)) {
 910                         PMD_DRV_LOG(ERR, "get physical time failed");
 911                         return err;
 912                 }
 913                 rxq->hw_time_update = rte_get_timer_cycles() / (rte_get_timer_hz() / 1000);
 914         }
 915
 916         return err;
 917 }
 918
 919 int
 920 iavf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 921 {
 922         struct iavf_adapter *adapter =
 923                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 924         struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 925         struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 926         struct iavf_tx_queue *txq;
 927         int err = 0;
 928
 929         PMD_DRV_FUNC_TRACE();
 930
 931         if (tx_queue_id >= dev->data->nb_tx_queues)
 932                 return -EINVAL;
 933
 934         txq = dev->data->tx_queues[tx_queue_id];
 935
 936         /* Init the RX tail register. */
 937         IAVF_PCI_REG_WRITE(txq->qtx_tail, 0);
 938         IAVF_WRITE_FLUSH(hw);
 939
 940         /* Ready to switch the queue on */
 941         if (!vf->lv_enabled)
 942                 err = iavf_switch_queue(adapter, tx_queue_id, false, true);
 943         else
 944                 err = iavf_switch_queue_lv(adapter, tx_queue_id, false, true);
 945
 946         if (err)
 947                 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
 948                             tx_queue_id);
 949         else
 950                 dev->data->tx_queue_state[tx_queue_id] =
 951                         RTE_ETH_QUEUE_STATE_STARTED;
 952
 953         return err;
 954 }
 955
 956 int
 957 iavf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 958 {
 959         struct iavf_adapter *adapter =
 960                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 961         struct iavf_rx_queue *rxq;
 962         int err;
 963
 964         PMD_DRV_FUNC_TRACE();
 965
 966         if (rx_queue_id >= dev->data->nb_rx_queues)
 967                 return -EINVAL;
 968
 969         err = iavf_switch_queue(adapter, rx_queue_id, true, false);
 970         if (err) {
 971                 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
 972                             rx_queue_id);
 973                 return err;
 974         }
 975
 976         rxq = dev->data->rx_queues[rx_queue_id];
 977         iavf_rxq_release_mbufs_ops[rxq->rel_mbufs_type].release_mbufs(rxq);
 978         reset_rx_queue(rxq);
 979         dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 980
 981         return 0;
 982 }
 983
 984 int
 985 iavf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 986 {
 987         struct iavf_adapter *adapter =
 988                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 989         struct iavf_tx_queue *txq;
 990         int err;
 991
 992         PMD_DRV_FUNC_TRACE();
 993
 994         if (tx_queue_id >= dev->data->nb_tx_queues)
 995                 return -EINVAL;
 996
 997         err = iavf_switch_queue(adapter, tx_queue_id, false, false);
 998         if (err) {
 999                 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u off",
1000                             tx_queue_id);
1001                 return err;
1002         }
1003
1004         txq = dev->data->tx_queues[tx_queue_id];
1005         iavf_txq_release_mbufs_ops[txq->rel_mbufs_type].release_mbufs(txq);
1006         reset_tx_queue(txq);
1007         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1008
1009         return 0;
1010 }
1011
1012 void
1013 iavf_dev_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
1014 {
1015         struct iavf_rx_queue *q = dev->data->rx_queues[qid];
1016
1017         if (!q)
1018                 return;
1019
1020         iavf_rxq_release_mbufs_ops[q->rel_mbufs_type].release_mbufs(q);
1021         rte_free(q->sw_ring);
1022         rte_memzone_free(q->mz);
1023         rte_free(q);
1024 }
1025
1026 void
1027 iavf_dev_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
1028 {
1029         struct iavf_tx_queue *q = dev->data->tx_queues[qid];
1030
1031         if (!q)
1032                 return;
1033
1034         iavf_txq_release_mbufs_ops[q->rel_mbufs_type].release_mbufs(q);
1035         rte_free(q->sw_ring);
1036         rte_memzone_free(q->mz);
1037         rte_free(q);
1038 }
1039
1040 void
1041 iavf_stop_queues(struct rte_eth_dev *dev)
1042 {
1043         struct iavf_adapter *adapter =
1044                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1045         struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1046         struct iavf_rx_queue *rxq;
1047         struct iavf_tx_queue *txq;
1048         int ret, i;
1049
1050         /* Stop All queues */
1051         if (!vf->lv_enabled) {
1052                 ret = iavf_disable_queues(adapter);
1053                 if (ret)
1054                         PMD_DRV_LOG(WARNING, "Fail to stop queues");
1055         } else {
1056                 ret = iavf_disable_queues_lv(adapter);
1057                 if (ret)
1058                         PMD_DRV_LOG(WARNING, "Fail to stop queues for large VF");
1059         }
1060
1061         if (ret)
1062                 PMD_DRV_LOG(WARNING, "Fail to stop queues");
1063
1064         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1065                 txq = dev->data->tx_queues[i];
1066                 if (!txq)
1067                         continue;
1068                 iavf_txq_release_mbufs_ops[txq->rel_mbufs_type].release_mbufs(txq);
1069                 reset_tx_queue(txq);
1070                 dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED;
1071         }
1072         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1073                 rxq = dev->data->rx_queues[i];
1074                 if (!rxq)
1075                         continue;
1076                 iavf_rxq_release_mbufs_ops[rxq->rel_mbufs_type].release_mbufs(rxq);
1077                 reset_rx_queue(rxq);
1078                 dev->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED;
1079         }
1080 }
1081
1082 #define IAVF_RX_FLEX_ERR0_BITS  \
1083         ((1 << IAVF_RX_FLEX_DESC_STATUS0_HBO_S) |       \
1084          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_IPE_S) |  \
1085          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_L4E_S) |  \
1086          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S) | \
1087          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S) |        \
1088          (1 << IAVF_RX_FLEX_DESC_STATUS0_RXE_S))
1089
1090 static inline void
1091 iavf_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union iavf_rx_desc *rxdp)
1092 {
1093         if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1094                 (1 << IAVF_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
1095                 mb->ol_flags |= RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED;
1096                 mb->vlan_tci =
1097                         rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
1098         } else {
1099                 mb->vlan_tci = 0;
1100         }
1101 }
1102
1103 static inline void
1104 iavf_flex_rxd_to_vlan_tci(struct rte_mbuf *mb,
1105                           volatile union iavf_rx_flex_desc *rxdp)
1106 {
1107         if (rte_le_to_cpu_64(rxdp->wb.status_error0) &
1108                 (1 << IAVF_RX_FLEX_DESC_STATUS0_L2TAG1P_S)) {
1109                 mb->ol_flags |= RTE_MBUF_F_RX_VLAN |
1110                                 RTE_MBUF_F_RX_VLAN_STRIPPED;
1111                 mb->vlan_tci =
1112                         rte_le_to_cpu_16(rxdp->wb.l2tag1);
1113         } else {
1114                 mb->vlan_tci = 0;
1115         }
1116
1117 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
1118         if (rte_le_to_cpu_16(rxdp->wb.status_error1) &
1119             (1 << IAVF_RX_FLEX_DESC_STATUS1_L2TAG2P_S)) {
1120                 mb->ol_flags |= RTE_MBUF_F_RX_QINQ_STRIPPED |
1121                                 RTE_MBUF_F_RX_QINQ |
1122                                 RTE_MBUF_F_RX_VLAN_STRIPPED |
1123                                 RTE_MBUF_F_RX_VLAN;
1124                 mb->vlan_tci_outer = mb->vlan_tci;
1125                 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.l2tag2_2nd);
1126                 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
1127                            rte_le_to_cpu_16(rxdp->wb.l2tag2_1st),
1128                            rte_le_to_cpu_16(rxdp->wb.l2tag2_2nd));
1129         } else {
1130                 mb->vlan_tci_outer = 0;
1131         }
1132 #endif
1133 }
1134
1135 static inline void
1136 iavf_flex_rxd_to_ipsec_crypto_said_get(struct rte_mbuf *mb,
1137                           volatile union iavf_rx_flex_desc *rxdp)
1138 {
1139         volatile struct iavf_32b_rx_flex_desc_comms_ipsec *desc =
1140                 (volatile struct iavf_32b_rx_flex_desc_comms_ipsec *)rxdp;
1141
1142         mb->dynfield1[0] = desc->ipsec_said &
1143                          IAVF_RX_FLEX_DESC_IPSEC_CRYPTO_SAID_MASK;
1144         }
1145
1146 static inline void
1147 iavf_flex_rxd_to_ipsec_crypto_status(struct rte_mbuf *mb,
1148                           volatile union iavf_rx_flex_desc *rxdp,
1149                           struct iavf_ipsec_crypto_stats *stats)
1150 {
1151         uint16_t status1 = rte_le_to_cpu_64(rxdp->wb.status_error1);
1152
1153         if (status1 & BIT(IAVF_RX_FLEX_DESC_STATUS1_IPSEC_CRYPTO_PROCESSED)) {
1154                 uint16_t ipsec_status;
1155
1156                 mb->ol_flags |= RTE_MBUF_F_RX_SEC_OFFLOAD;
1157
1158                 ipsec_status = status1 &
1159                         IAVF_RX_FLEX_DESC_IPSEC_CRYPTO_STATUS_MASK;
1160
1161
1162                 if (unlikely(ipsec_status !=
1163                         IAVF_IPSEC_CRYPTO_STATUS_SUCCESS)) {
1164                         mb->ol_flags |= RTE_MBUF_F_RX_SEC_OFFLOAD_FAILED;
1165
1166                         switch (ipsec_status) {
1167                         case IAVF_IPSEC_CRYPTO_STATUS_SAD_MISS:
1168                                 stats->ierrors.sad_miss++;
1169                                 break;
1170                         case IAVF_IPSEC_CRYPTO_STATUS_NOT_PROCESSED:
1171                                 stats->ierrors.not_processed++;
1172                                 break;
1173                         case IAVF_IPSEC_CRYPTO_STATUS_ICV_CHECK_FAIL:
1174                                 stats->ierrors.icv_check++;
1175                                 break;
1176                         case IAVF_IPSEC_CRYPTO_STATUS_LENGTH_ERR:
1177                                 stats->ierrors.ipsec_length++;
1178                                 break;
1179                         case IAVF_IPSEC_CRYPTO_STATUS_MISC_ERR:
1180                                 stats->ierrors.misc++;
1181                                 break;
1182 }
1183
1184                         stats->ierrors.count++;
1185                         return;
1186                 }
1187
1188                 stats->icount++;
1189                 stats->ibytes += rxdp->wb.pkt_len & 0x3FFF;
1190
1191                 if (rxdp->wb.rxdid == IAVF_RXDID_COMMS_IPSEC_CRYPTO &&
1192                         ipsec_status !=
1193                                 IAVF_IPSEC_CRYPTO_STATUS_SAD_MISS)
1194                         iavf_flex_rxd_to_ipsec_crypto_said_get(mb, rxdp);
1195         }
1196 }
1197
1198
1199 /* Translate the rx descriptor status and error fields to pkt flags */
1200 static inline uint64_t
1201 iavf_rxd_to_pkt_flags(uint64_t qword)
1202 {
1203         uint64_t flags;
1204         uint64_t error_bits = (qword >> IAVF_RXD_QW1_ERROR_SHIFT);
1205
1206 #define IAVF_RX_ERR_BITS 0x3f
1207
1208         /* Check if RSS_HASH */
1209         flags = (((qword >> IAVF_RX_DESC_STATUS_FLTSTAT_SHIFT) &
1210                                         IAVF_RX_DESC_FLTSTAT_RSS_HASH) ==
1211                         IAVF_RX_DESC_FLTSTAT_RSS_HASH) ? RTE_MBUF_F_RX_RSS_HASH : 0;
1212
1213         /* Check if FDIR Match */
1214         flags |= (qword & (1 << IAVF_RX_DESC_STATUS_FLM_SHIFT) ?
1215                                 RTE_MBUF_F_RX_FDIR : 0);
1216
1217         if (likely((error_bits & IAVF_RX_ERR_BITS) == 0)) {
1218                 flags |= (RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_GOOD);
1219                 return flags;
1220         }
1221
1222         if (unlikely(error_bits & (1 << IAVF_RX_DESC_ERROR_IPE_SHIFT)))
1223                 flags |= RTE_MBUF_F_RX_IP_CKSUM_BAD;
1224         else
1225                 flags |= RTE_MBUF_F_RX_IP_CKSUM_GOOD;
1226
1227         if (unlikely(error_bits & (1 << IAVF_RX_DESC_ERROR_L4E_SHIFT)))
1228                 flags |= RTE_MBUF_F_RX_L4_CKSUM_BAD;
1229         else
1230                 flags |= RTE_MBUF_F_RX_L4_CKSUM_GOOD;
1231
1232         /* TODO: Oversize error bit is not processed here */
1233
1234         return flags;
1235 }
1236
1237 static inline uint64_t
1238 iavf_rxd_build_fdir(volatile union iavf_rx_desc *rxdp, struct rte_mbuf *mb)
1239 {
1240         uint64_t flags = 0;
1241 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
1242         uint16_t flexbh;
1243
1244         flexbh = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
1245                 IAVF_RX_DESC_EXT_STATUS_FLEXBH_SHIFT) &
1246                 IAVF_RX_DESC_EXT_STATUS_FLEXBH_MASK;
1247
1248         if (flexbh == IAVF_RX_DESC_EXT_STATUS_FLEXBH_FD_ID) {
1249                 mb->hash.fdir.hi =
1250                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.fd_id);
1251                 flags |= RTE_MBUF_F_RX_FDIR_ID;
1252         }
1253 #else
1254         mb->hash.fdir.hi =
1255                 rte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.fd_id);
1256         flags |= RTE_MBUF_F_RX_FDIR_ID;
1257 #endif
1258         return flags;
1259 }
1260
1261 #define IAVF_RX_FLEX_ERR0_BITS  \
1262         ((1 << IAVF_RX_FLEX_DESC_STATUS0_HBO_S) |       \
1263          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_IPE_S) |  \
1264          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_L4E_S) |  \
1265          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S) | \
1266          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S) |        \
1267          (1 << IAVF_RX_FLEX_DESC_STATUS0_RXE_S))
1268
1269 /* Rx L3/L4 checksum */
1270 static inline uint64_t
1271 iavf_flex_rxd_error_to_pkt_flags(uint16_t stat_err0)
1272 {
1273         uint64_t flags = 0;
1274
1275         /* check if HW has decoded the packet and checksum */
1276         if (unlikely(!(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_L3L4P_S))))
1277                 return 0;
1278
1279         if (likely(!(stat_err0 & IAVF_RX_FLEX_ERR0_BITS))) {
1280                 flags |= (RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_GOOD);
1281                 return flags;
1282         }
1283
1284         if (unlikely(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_IPE_S)))
1285                 flags |= RTE_MBUF_F_RX_IP_CKSUM_BAD;
1286         else
1287                 flags |= RTE_MBUF_F_RX_IP_CKSUM_GOOD;
1288
1289         if (unlikely(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_L4E_S)))
1290                 flags |= RTE_MBUF_F_RX_L4_CKSUM_BAD;
1291         else
1292                 flags |= RTE_MBUF_F_RX_L4_CKSUM_GOOD;
1293
1294         if (unlikely(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S)))
1295                 flags |= RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD;
1296
1297         return flags;
1298 }
1299
1300 /* If the number of free RX descriptors is greater than the RX free
1301  * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1302  * register. Update the RDT with the value of the last processed RX
1303  * descriptor minus 1, to guarantee that the RDT register is never
1304  * equal to the RDH register, which creates a "full" ring situation
1305  * from the hardware point of view.
1306  */
1307 static inline void
1308 iavf_update_rx_tail(struct iavf_rx_queue *rxq, uint16_t nb_hold, uint16_t rx_id)
1309 {
1310         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1311
1312         if (nb_hold > rxq->rx_free_thresh) {
1313                 PMD_RX_LOG(DEBUG,
1314                            "port_id=%u queue_id=%u rx_tail=%u nb_hold=%u",
1315                            rxq->port_id, rxq->queue_id, rx_id, nb_hold);
1316                 rx_id = (uint16_t)((rx_id == 0) ?
1317                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
1318                 IAVF_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
1319                 nb_hold = 0;
1320         }
1321         rxq->nb_rx_hold = nb_hold;
1322 }
1323
1324 /* implement recv_pkts */
1325 uint16_t
1326 iavf_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1327 {
1328         volatile union iavf_rx_desc *rx_ring;
1329         volatile union iavf_rx_desc *rxdp;
1330         struct iavf_rx_queue *rxq;
1331         union iavf_rx_desc rxd;
1332         struct rte_mbuf *rxe;
1333         struct rte_eth_dev *dev;
1334         struct rte_mbuf *rxm;
1335         struct rte_mbuf *nmb;
1336         uint16_t nb_rx;
1337         uint32_t rx_status;
1338         uint64_t qword1;
1339         uint16_t rx_packet_len;
1340         uint16_t rx_id, nb_hold;
1341         uint64_t dma_addr;
1342         uint64_t pkt_flags;
1343         const uint32_t *ptype_tbl;
1344
1345         nb_rx = 0;
1346         nb_hold = 0;
1347         rxq = rx_queue;
1348         rx_id = rxq->rx_tail;
1349         rx_ring = rxq->rx_ring;
1350         ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1351
1352         while (nb_rx < nb_pkts) {
1353                 rxdp = &rx_ring[rx_id];
1354                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1355                 rx_status = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
1356                             IAVF_RXD_QW1_STATUS_SHIFT;
1357
1358                 /* Check the DD bit first */
1359                 if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)))
1360                         break;
1361                 IAVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
1362
1363                 nmb = rte_mbuf_raw_alloc(rxq->mp);
1364                 if (unlikely(!nmb)) {
1365                         dev = &rte_eth_devices[rxq->port_id];
1366                         dev->data->rx_mbuf_alloc_failed++;
1367                         PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1368                                    "queue_id=%u", rxq->port_id, rxq->queue_id);
1369                         break;
1370                 }
1371
1372                 rxd = *rxdp;
1373                 nb_hold++;
1374                 rxe = rxq->sw_ring[rx_id];
1375                 rxq->sw_ring[rx_id] = nmb;
1376                 rx_id++;
1377                 if (unlikely(rx_id == rxq->nb_rx_desc))
1378                         rx_id = 0;
1379
1380                 /* Prefetch next mbuf */
1381                 rte_prefetch0(rxq->sw_ring[rx_id]);
1382
1383                 /* When next RX descriptor is on a cache line boundary,
1384                  * prefetch the next 4 RX descriptors and next 8 pointers
1385                  * to mbufs.
1386                  */
1387                 if ((rx_id & 0x3) == 0) {
1388                         rte_prefetch0(&rx_ring[rx_id]);
1389                         rte_prefetch0(rxq->sw_ring[rx_id]);
1390                 }
1391                 rxm = rxe;
1392                 dma_addr =
1393                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1394                 rxdp->read.hdr_addr = 0;
1395                 rxdp->read.pkt_addr = dma_addr;
1396
1397                 rx_packet_len = ((qword1 & IAVF_RXD_QW1_LENGTH_PBUF_MASK) >>
1398                                 IAVF_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
1399
1400                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1401                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
1402                 rxm->nb_segs = 1;
1403                 rxm->next = NULL;
1404                 rxm->pkt_len = rx_packet_len;
1405                 rxm->data_len = rx_packet_len;
1406                 rxm->port = rxq->port_id;
1407                 rxm->ol_flags = 0;
1408                 iavf_rxd_to_vlan_tci(rxm, &rxd);
1409                 pkt_flags = iavf_rxd_to_pkt_flags(qword1);
1410                 rxm->packet_type =
1411                         ptype_tbl[(uint8_t)((qword1 &
1412                         IAVF_RXD_QW1_PTYPE_MASK) >> IAVF_RXD_QW1_PTYPE_SHIFT)];
1413
1414                 if (pkt_flags & RTE_MBUF_F_RX_RSS_HASH)
1415                         rxm->hash.rss =
1416                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1417
1418                 if (pkt_flags & RTE_MBUF_F_RX_FDIR)
1419                         pkt_flags |= iavf_rxd_build_fdir(&rxd, rxm);
1420
1421                 rxm->ol_flags |= pkt_flags;
1422
1423                 rx_pkts[nb_rx++] = rxm;
1424         }
1425         rxq->rx_tail = rx_id;
1426
1427         iavf_update_rx_tail(rxq, nb_hold, rx_id);
1428
1429         return nb_rx;
1430 }
1431
1432 /* implement recv_pkts for flexible Rx descriptor */
1433 uint16_t
1434 iavf_recv_pkts_flex_rxd(void *rx_queue,
1435                         struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1436 {
1437         volatile union iavf_rx_desc *rx_ring;
1438         volatile union iavf_rx_flex_desc *rxdp;
1439         struct iavf_rx_queue *rxq;
1440         union iavf_rx_flex_desc rxd;
1441         struct rte_mbuf *rxe;
1442         struct rte_eth_dev *dev;
1443         struct rte_mbuf *rxm;
1444         struct rte_mbuf *nmb;
1445         uint16_t nb_rx;
1446         uint16_t rx_stat_err0;
1447         uint16_t rx_packet_len;
1448         uint16_t rx_id, nb_hold;
1449         uint64_t dma_addr;
1450         uint64_t pkt_flags;
1451         const uint32_t *ptype_tbl;
1452         uint64_t ts_ns;
1453
1454         nb_rx = 0;
1455         nb_hold = 0;
1456         rxq = rx_queue;
1457         rx_id = rxq->rx_tail;
1458         rx_ring = rxq->rx_ring;
1459         ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1460
1461         if (rxq->offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) {
1462                 uint64_t sw_cur_time = rte_get_timer_cycles() / (rte_get_timer_hz() / 1000);
1463
1464                 if (sw_cur_time - rxq->hw_time_update > 4) {
1465                         if (iavf_get_phc_time(rxq))
1466                                 PMD_DRV_LOG(ERR, "get physical time failed");
1467                         rxq->hw_time_update = sw_cur_time;
1468                 }
1469         }
1470
1471         while (nb_rx < nb_pkts) {
1472                 rxdp = (volatile union iavf_rx_flex_desc *)&rx_ring[rx_id];
1473                 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1474
1475                 /* Check the DD bit first */
1476                 if (!(rx_stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S)))
1477                         break;
1478                 IAVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
1479
1480                 nmb = rte_mbuf_raw_alloc(rxq->mp);
1481                 if (unlikely(!nmb)) {
1482                         dev = &rte_eth_devices[rxq->port_id];
1483                         dev->data->rx_mbuf_alloc_failed++;
1484                         PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1485                                    "queue_id=%u", rxq->port_id, rxq->queue_id);
1486                         break;
1487                 }
1488
1489                 rxd = *rxdp;
1490                 nb_hold++;
1491                 rxe = rxq->sw_ring[rx_id];
1492                 rxq->sw_ring[rx_id] = nmb;
1493                 rx_id++;
1494                 if (unlikely(rx_id == rxq->nb_rx_desc))
1495                         rx_id = 0;
1496
1497                 /* Prefetch next mbuf */
1498                 rte_prefetch0(rxq->sw_ring[rx_id]);
1499
1500                 /* When next RX descriptor is on a cache line boundary,
1501                  * prefetch the next 4 RX descriptors and next 8 pointers
1502                  * to mbufs.
1503                  */
1504                 if ((rx_id & 0x3) == 0) {
1505                         rte_prefetch0(&rx_ring[rx_id]);
1506                         rte_prefetch0(rxq->sw_ring[rx_id]);
1507                 }
1508                 rxm = rxe;
1509                 dma_addr =
1510                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1511                 rxdp->read.hdr_addr = 0;
1512                 rxdp->read.pkt_addr = dma_addr;
1513
1514                 rx_packet_len = (rte_le_to_cpu_16(rxd.wb.pkt_len) &
1515                                 IAVF_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
1516
1517                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1518                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
1519                 rxm->nb_segs = 1;
1520                 rxm->next = NULL;
1521                 rxm->pkt_len = rx_packet_len;
1522                 rxm->data_len = rx_packet_len;
1523                 rxm->port = rxq->port_id;
1524                 rxm->ol_flags = 0;
1525                 rxm->packet_type = ptype_tbl[IAVF_RX_FLEX_DESC_PTYPE_M &
1526                         rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
1527                 iavf_flex_rxd_to_vlan_tci(rxm, &rxd);
1528                 iavf_flex_rxd_to_ipsec_crypto_status(rxm, &rxd,
1529                                 &rxq->stats.ipsec_crypto);
1530                 rxd_to_pkt_fields_ops[rxq->rxdid](rxq, rxm, &rxd);
1531                 pkt_flags = iavf_flex_rxd_error_to_pkt_flags(rx_stat_err0);
1532
1533                 if (iavf_timestamp_dynflag > 0) {
1534                         ts_ns = iavf_tstamp_convert_32b_64b(rxq->phc_time,
1535                                 rte_le_to_cpu_32(rxd.wb.flex_ts.ts_high));
1536
1537                         rxq->phc_time = ts_ns;
1538                         rxq->hw_time_update = rte_get_timer_cycles() / (rte_get_timer_hz() / 1000);
1539
1540                         *RTE_MBUF_DYNFIELD(rxm,
1541                                 iavf_timestamp_dynfield_offset,
1542                                 rte_mbuf_timestamp_t *) = ts_ns;
1543                         rxm->ol_flags |= iavf_timestamp_dynflag;
1544                 }
1545
1546                 rxm->ol_flags |= pkt_flags;
1547
1548                 rx_pkts[nb_rx++] = rxm;
1549         }
1550         rxq->rx_tail = rx_id;
1551
1552         iavf_update_rx_tail(rxq, nb_hold, rx_id);
1553
1554         return nb_rx;
1555 }
1556
1557 /* implement recv_scattered_pkts for flexible Rx descriptor */
1558 uint16_t
1559 iavf_recv_scattered_pkts_flex_rxd(void *rx_queue, struct rte_mbuf **rx_pkts,
1560                                   uint16_t nb_pkts)
1561 {
1562         struct iavf_rx_queue *rxq = rx_queue;
1563         union iavf_rx_flex_desc rxd;
1564         struct rte_mbuf *rxe;
1565         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1566         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1567         struct rte_mbuf *nmb, *rxm;
1568         uint16_t rx_id = rxq->rx_tail;
1569         uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
1570         struct rte_eth_dev *dev;
1571         uint16_t rx_stat_err0;
1572         uint64_t dma_addr;
1573         uint64_t pkt_flags;
1574         uint64_t ts_ns;
1575
1576         volatile union iavf_rx_desc *rx_ring = rxq->rx_ring;
1577         volatile union iavf_rx_flex_desc *rxdp;
1578         const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1579
1580         if (rxq->offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) {
1581                 uint64_t sw_cur_time = rte_get_timer_cycles() / (rte_get_timer_hz() / 1000);
1582
1583                 if (sw_cur_time - rxq->hw_time_update > 4) {
1584                         if (iavf_get_phc_time(rxq))
1585                                 PMD_DRV_LOG(ERR, "get physical time failed");
1586                         rxq->hw_time_update = sw_cur_time;
1587                 }
1588         }
1589
1590         while (nb_rx < nb_pkts) {
1591                 rxdp = (volatile union iavf_rx_flex_desc *)&rx_ring[rx_id];
1592                 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1593
1594                 /* Check the DD bit */
1595                 if (!(rx_stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S)))
1596                         break;
1597                 IAVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
1598
1599                 nmb = rte_mbuf_raw_alloc(rxq->mp);
1600                 if (unlikely(!nmb)) {
1601                         PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1602                                    "queue_id=%u", rxq->port_id, rxq->queue_id);
1603                         dev = &rte_eth_devices[rxq->port_id];
1604                         dev->data->rx_mbuf_alloc_failed++;
1605                         break;
1606                 }
1607
1608                 rxd = *rxdp;
1609                 nb_hold++;
1610                 rxe = rxq->sw_ring[rx_id];
1611                 rxq->sw_ring[rx_id] = nmb;
1612                 rx_id++;
1613                 if (rx_id == rxq->nb_rx_desc)
1614                         rx_id = 0;
1615
1616                 /* Prefetch next mbuf */
1617                 rte_prefetch0(rxq->sw_ring[rx_id]);
1618
1619                 /* When next RX descriptor is on a cache line boundary,
1620                  * prefetch the next 4 RX descriptors and next 8 pointers
1621                  * to mbufs.
1622                  */
1623                 if ((rx_id & 0x3) == 0) {
1624                         rte_prefetch0(&rx_ring[rx_id]);
1625                         rte_prefetch0(rxq->sw_ring[rx_id]);
1626                 }
1627
1628                 rxm = rxe;
1629                 dma_addr =
1630                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1631
1632                 /* Set data buffer address and data length of the mbuf */
1633                 rxdp->read.hdr_addr = 0;
1634                 rxdp->read.pkt_addr = dma_addr;
1635                 rx_packet_len = rte_le_to_cpu_16(rxd.wb.pkt_len) &
1636                                 IAVF_RX_FLX_DESC_PKT_LEN_M;
1637                 rxm->data_len = rx_packet_len;
1638                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1639
1640                 /* If this is the first buffer of the received packet, set the
1641                  * pointer to the first mbuf of the packet and initialize its
1642                  * context. Otherwise, update the total length and the number
1643                  * of segments of the current scattered packet, and update the
1644                  * pointer to the last mbuf of the current packet.
1645                  */
1646                 if (!first_seg) {
1647                         first_seg = rxm;
1648                         first_seg->nb_segs = 1;
1649                         first_seg->pkt_len = rx_packet_len;
1650                 } else {
1651                         first_seg->pkt_len =
1652                                 (uint16_t)(first_seg->pkt_len +
1653                                                 rx_packet_len);
1654                         first_seg->nb_segs++;
1655                         last_seg->next = rxm;
1656                 }
1657
1658                 /* If this is not the last buffer of the received packet,
1659                  * update the pointer to the last mbuf of the current scattered
1660                  * packet and continue to parse the RX ring.
1661                  */
1662                 if (!(rx_stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_EOF_S))) {
1663                         last_seg = rxm;
1664                         continue;
1665                 }
1666
1667                 /* This is the last buffer of the received packet. If the CRC
1668                  * is not stripped by the hardware:
1669                  *  - Subtract the CRC length from the total packet length.
1670                  *  - If the last buffer only contains the whole CRC or a part
1671                  *  of it, free the mbuf associated to the last buffer. If part
1672                  *  of the CRC is also contained in the previous mbuf, subtract
1673                  *  the length of that CRC part from the data length of the
1674                  *  previous mbuf.
1675                  */
1676                 rxm->next = NULL;
1677                 if (unlikely(rxq->crc_len > 0)) {
1678                         first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
1679                         if (rx_packet_len <= RTE_ETHER_CRC_LEN) {
1680                                 rte_pktmbuf_free_seg(rxm);
1681                                 first_seg->nb_segs--;
1682                                 last_seg->data_len =
1683                                         (uint16_t)(last_seg->data_len -
1684                                         (RTE_ETHER_CRC_LEN - rx_packet_len));
1685                                 last_seg->next = NULL;
1686                         } else {
1687                                 rxm->data_len = (uint16_t)(rx_packet_len -
1688                                                         RTE_ETHER_CRC_LEN);
1689                         }
1690                 }
1691
1692                 first_seg->port = rxq->port_id;
1693                 first_seg->ol_flags = 0;
1694                 first_seg->packet_type = ptype_tbl[IAVF_RX_FLEX_DESC_PTYPE_M &
1695                         rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
1696                 iavf_flex_rxd_to_vlan_tci(first_seg, &rxd);
1697                 iavf_flex_rxd_to_ipsec_crypto_status(first_seg, &rxd,
1698                                 &rxq->stats.ipsec_crypto);
1699                 rxd_to_pkt_fields_ops[rxq->rxdid](rxq, first_seg, &rxd);
1700                 pkt_flags = iavf_flex_rxd_error_to_pkt_flags(rx_stat_err0);
1701
1702                 if (iavf_timestamp_dynflag > 0) {
1703                         ts_ns = iavf_tstamp_convert_32b_64b(rxq->phc_time,
1704                                 rte_le_to_cpu_32(rxd.wb.flex_ts.ts_high));
1705
1706                         rxq->phc_time = ts_ns;
1707                         rxq->hw_time_update = rte_get_timer_cycles() / (rte_get_timer_hz() / 1000);
1708
1709                         *RTE_MBUF_DYNFIELD(first_seg,
1710                                 iavf_timestamp_dynfield_offset,
1711                                 rte_mbuf_timestamp_t *) = ts_ns;
1712                         first_seg->ol_flags |= iavf_timestamp_dynflag;
1713                 }
1714
1715                 first_seg->ol_flags |= pkt_flags;
1716
1717                 /* Prefetch data of first segment, if configured to do so. */
1718                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1719                                           first_seg->data_off));
1720                 rx_pkts[nb_rx++] = first_seg;
1721                 first_seg = NULL;
1722         }
1723
1724         /* Record index of the next RX descriptor to probe. */
1725         rxq->rx_tail = rx_id;
1726         rxq->pkt_first_seg = first_seg;
1727         rxq->pkt_last_seg = last_seg;
1728
1729         iavf_update_rx_tail(rxq, nb_hold, rx_id);
1730
1731         return nb_rx;
1732 }
1733
1734 /* implement recv_scattered_pkts  */
1735 uint16_t
1736 iavf_recv_scattered_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1737                         uint16_t nb_pkts)
1738 {
1739         struct iavf_rx_queue *rxq = rx_queue;
1740         union iavf_rx_desc rxd;
1741         struct rte_mbuf *rxe;
1742         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1743         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1744         struct rte_mbuf *nmb, *rxm;
1745         uint16_t rx_id = rxq->rx_tail;
1746         uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
1747         struct rte_eth_dev *dev;
1748         uint32_t rx_status;
1749         uint64_t qword1;
1750         uint64_t dma_addr;
1751         uint64_t pkt_flags;
1752
1753         volatile union iavf_rx_desc *rx_ring = rxq->rx_ring;
1754         volatile union iavf_rx_desc *rxdp;
1755         const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1756
1757         while (nb_rx < nb_pkts) {
1758                 rxdp = &rx_ring[rx_id];
1759                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1760                 rx_status = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
1761                             IAVF_RXD_QW1_STATUS_SHIFT;
1762
1763                 /* Check the DD bit */
1764                 if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)))
1765                         break;
1766                 IAVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
1767
1768                 nmb = rte_mbuf_raw_alloc(rxq->mp);
1769                 if (unlikely(!nmb)) {
1770                         PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1771                                    "queue_id=%u", rxq->port_id, rxq->queue_id);
1772                         dev = &rte_eth_devices[rxq->port_id];
1773                         dev->data->rx_mbuf_alloc_failed++;
1774                         break;
1775                 }
1776
1777                 rxd = *rxdp;
1778                 nb_hold++;
1779                 rxe = rxq->sw_ring[rx_id];
1780                 rxq->sw_ring[rx_id] = nmb;
1781                 rx_id++;
1782                 if (rx_id == rxq->nb_rx_desc)
1783                         rx_id = 0;
1784
1785                 /* Prefetch next mbuf */
1786                 rte_prefetch0(rxq->sw_ring[rx_id]);
1787
1788                 /* When next RX descriptor is on a cache line boundary,
1789                  * prefetch the next 4 RX descriptors and next 8 pointers
1790                  * to mbufs.
1791                  */
1792                 if ((rx_id & 0x3) == 0) {
1793                         rte_prefetch0(&rx_ring[rx_id]);
1794                         rte_prefetch0(rxq->sw_ring[rx_id]);
1795                 }
1796
1797                 rxm = rxe;
1798                 dma_addr =
1799                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1800
1801                 /* Set data buffer address and data length of the mbuf */
1802                 rxdp->read.hdr_addr = 0;
1803                 rxdp->read.pkt_addr = dma_addr;
1804                 rx_packet_len = (qword1 & IAVF_RXD_QW1_LENGTH_PBUF_MASK) >>
1805                                  IAVF_RXD_QW1_LENGTH_PBUF_SHIFT;
1806                 rxm->data_len = rx_packet_len;
1807                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1808
1809                 /* If this is the first buffer of the received packet, set the
1810                  * pointer to the first mbuf of the packet and initialize its
1811                  * context. Otherwise, update the total length and the number
1812                  * of segments of the current scattered packet, and update the
1813                  * pointer to the last mbuf of the current packet.
1814                  */
1815                 if (!first_seg) {
1816                         first_seg = rxm;
1817                         first_seg->nb_segs = 1;
1818                         first_seg->pkt_len = rx_packet_len;
1819                 } else {
1820                         first_seg->pkt_len =
1821                                 (uint16_t)(first_seg->pkt_len +
1822                                                 rx_packet_len);
1823                         first_seg->nb_segs++;
1824                         last_seg->next = rxm;
1825                 }
1826
1827                 /* If this is not the last buffer of the received packet,
1828                  * update the pointer to the last mbuf of the current scattered
1829                  * packet and continue to parse the RX ring.
1830                  */
1831                 if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_EOF_SHIFT))) {
1832                         last_seg = rxm;
1833                         continue;
1834                 }
1835
1836                 /* This is the last buffer of the received packet. If the CRC
1837                  * is not stripped by the hardware:
1838                  *  - Subtract the CRC length from the total packet length.
1839                  *  - If the last buffer only contains the whole CRC or a part
1840                  *  of it, free the mbuf associated to the last buffer. If part
1841                  *  of the CRC is also contained in the previous mbuf, subtract
1842                  *  the length of that CRC part from the data length of the
1843                  *  previous mbuf.
1844                  */
1845                 rxm->next = NULL;
1846                 if (unlikely(rxq->crc_len > 0)) {
1847                         first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
1848                         if (rx_packet_len <= RTE_ETHER_CRC_LEN) {
1849                                 rte_pktmbuf_free_seg(rxm);
1850                                 first_seg->nb_segs--;
1851                                 last_seg->data_len =
1852                                         (uint16_t)(last_seg->data_len -
1853                                         (RTE_ETHER_CRC_LEN - rx_packet_len));
1854                                 last_seg->next = NULL;
1855                         } else
1856                                 rxm->data_len = (uint16_t)(rx_packet_len -
1857                                                         RTE_ETHER_CRC_LEN);
1858                 }
1859
1860                 first_seg->port = rxq->port_id;
1861                 first_seg->ol_flags = 0;
1862                 iavf_rxd_to_vlan_tci(first_seg, &rxd);
1863                 pkt_flags = iavf_rxd_to_pkt_flags(qword1);
1864                 first_seg->packet_type =
1865                         ptype_tbl[(uint8_t)((qword1 &
1866                         IAVF_RXD_QW1_PTYPE_MASK) >> IAVF_RXD_QW1_PTYPE_SHIFT)];
1867
1868                 if (pkt_flags & RTE_MBUF_F_RX_RSS_HASH)
1869                         first_seg->hash.rss =
1870                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1871
1872                 if (pkt_flags & RTE_MBUF_F_RX_FDIR)
1873                         pkt_flags |= iavf_rxd_build_fdir(&rxd, first_seg);
1874
1875                 first_seg->ol_flags |= pkt_flags;
1876
1877                 /* Prefetch data of first segment, if configured to do so. */
1878                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1879                                           first_seg->data_off));
1880                 rx_pkts[nb_rx++] = first_seg;
1881                 first_seg = NULL;
1882         }
1883
1884         /* Record index of the next RX descriptor to probe. */
1885         rxq->rx_tail = rx_id;
1886         rxq->pkt_first_seg = first_seg;
1887         rxq->pkt_last_seg = last_seg;
1888
1889         iavf_update_rx_tail(rxq, nb_hold, rx_id);
1890
1891         return nb_rx;
1892 }
1893
1894 #define IAVF_LOOK_AHEAD 8
1895 static inline int
1896 iavf_rx_scan_hw_ring_flex_rxd(struct iavf_rx_queue *rxq,
1897                             struct rte_mbuf **rx_pkts,
1898                             uint16_t nb_pkts)
1899 {
1900         volatile union iavf_rx_flex_desc *rxdp;
1901         struct rte_mbuf **rxep;
1902         struct rte_mbuf *mb;
1903         uint16_t stat_err0;
1904         uint16_t pkt_len;
1905         int32_t s[IAVF_LOOK_AHEAD], var, nb_dd;
1906         int32_t i, j, nb_rx = 0;
1907         int32_t nb_staged = 0;
1908         uint64_t pkt_flags;
1909         const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1910         uint64_t ts_ns;
1911
1912         rxdp = (volatile union iavf_rx_flex_desc *)&rxq->rx_ring[rxq->rx_tail];
1913         rxep = &rxq->sw_ring[rxq->rx_tail];
1914
1915         stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1916
1917         /* Make sure there is at least 1 packet to receive */
1918         if (!(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S)))
1919                 return 0;
1920
1921         if (rxq->offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) {
1922                 uint64_t sw_cur_time = rte_get_timer_cycles() / (rte_get_timer_hz() / 1000);
1923
1924                 if (sw_cur_time - rxq->hw_time_update > 4) {
1925                         if (iavf_get_phc_time(rxq))
1926                                 PMD_DRV_LOG(ERR, "get physical time failed");
1927                         rxq->hw_time_update = sw_cur_time;
1928                 }
1929         }
1930
1931         /* Scan LOOK_AHEAD descriptors at a time to determine which
1932          * descriptors reference packets that are ready to be received.
1933          */
1934         for (i = 0; i < IAVF_RX_MAX_BURST; i += IAVF_LOOK_AHEAD,
1935              rxdp += IAVF_LOOK_AHEAD, rxep += IAVF_LOOK_AHEAD) {
1936                 /* Read desc statuses backwards to avoid race condition */
1937                 for (j = IAVF_LOOK_AHEAD - 1; j >= 0; j--)
1938                         s[j] = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1939
1940                 /* This barrier is to order loads of different words in the descriptor */
1941                 rte_atomic_thread_fence(__ATOMIC_ACQUIRE);
1942
1943                 /* Compute how many contiguous DD bits were set */
1944                 for (j = 0, nb_dd = 0; j < IAVF_LOOK_AHEAD; j++) {
1945                         var = s[j] & (1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S);
1946 #ifdef RTE_ARCH_ARM
1947                         /* For Arm platforms, count only contiguous descriptors
1948                          * whose DD bit is set to 1. On Arm platforms, reads of
1949                          * descriptors can be reordered. Since the CPU may
1950                          * be reading the descriptors as the NIC updates them
1951                          * in memory, it is possbile that the DD bit for a
1952                          * descriptor earlier in the queue is read as not set
1953                          * while the DD bit for a descriptor later in the queue
1954                          * is read as set.
1955                          */
1956                         if (var)
1957                                 nb_dd += 1;
1958                         else
1959                                 break;
1960 #else
1961                         nb_dd += var;
1962 #endif
1963                 }
1964
1965                 /* Translate descriptor info to mbuf parameters */
1966                 for (j = 0; j < nb_dd; j++) {
1967                         IAVF_DUMP_RX_DESC(rxq, &rxdp[j],
1968                                           rxq->rx_tail +
1969                                           i * IAVF_LOOK_AHEAD + j);
1970
1971                         mb = rxep[j];
1972                         pkt_len = (rte_le_to_cpu_16(rxdp[j].wb.pkt_len) &
1973                                 IAVF_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
1974                         mb->data_len = pkt_len;
1975                         mb->pkt_len = pkt_len;
1976                         mb->ol_flags = 0;
1977
1978                         mb->packet_type = ptype_tbl[IAVF_RX_FLEX_DESC_PTYPE_M &
1979                                 rte_le_to_cpu_16(rxdp[j].wb.ptype_flex_flags0)];
1980                         iavf_flex_rxd_to_vlan_tci(mb, &rxdp[j]);
1981                         iavf_flex_rxd_to_ipsec_crypto_status(mb, &rxdp[j],
1982                                 &rxq->stats.ipsec_crypto);
1983                         rxd_to_pkt_fields_ops[rxq->rxdid](rxq, mb, &rxdp[j]);
1984                         stat_err0 = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1985                         pkt_flags = iavf_flex_rxd_error_to_pkt_flags(stat_err0);
1986
1987                         if (iavf_timestamp_dynflag > 0) {
1988                                 ts_ns = iavf_tstamp_convert_32b_64b(rxq->phc_time,
1989                                         rte_le_to_cpu_32(rxdp[j].wb.flex_ts.ts_high));
1990
1991                                 rxq->phc_time = ts_ns;
1992                                 rxq->hw_time_update = rte_get_timer_cycles() /
1993                                         (rte_get_timer_hz() / 1000);
1994
1995                                 *RTE_MBUF_DYNFIELD(mb,
1996                                         iavf_timestamp_dynfield_offset,
1997                                         rte_mbuf_timestamp_t *) = ts_ns;
1998                                 mb->ol_flags |= iavf_timestamp_dynflag;
1999                         }
2000
2001                         mb->ol_flags |= pkt_flags;
2002
2003                         /* Put up to nb_pkts directly into buffers */
2004                         if ((i + j) < nb_pkts) {
2005                                 rx_pkts[i + j] = rxep[j];
2006                                 nb_rx++;
2007                         } else {
2008                                 /* Stage excess pkts received */
2009                                 rxq->rx_stage[nb_staged] = rxep[j];
2010                                 nb_staged++;
2011                         }
2012                 }
2013
2014                 if (nb_dd != IAVF_LOOK_AHEAD)
2015                         break;
2016         }
2017
2018         /* Update rxq->rx_nb_avail to reflect number of staged pkts */
2019         rxq->rx_nb_avail = nb_staged;
2020
2021         /* Clear software ring entries */
2022         for (i = 0; i < (nb_rx + nb_staged); i++)
2023                 rxq->sw_ring[rxq->rx_tail + i] = NULL;
2024
2025         return nb_rx;
2026 }
2027
2028 static inline int
2029 iavf_rx_scan_hw_ring(struct iavf_rx_queue *rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
2030 {
2031         volatile union iavf_rx_desc *rxdp;
2032         struct rte_mbuf **rxep;
2033         struct rte_mbuf *mb;
2034         uint16_t pkt_len;
2035         uint64_t qword1;
2036         uint32_t rx_status;
2037         int32_t s[IAVF_LOOK_AHEAD], var, nb_dd;
2038         int32_t i, j, nb_rx = 0;
2039         int32_t nb_staged = 0;
2040         uint64_t pkt_flags;
2041         const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
2042
2043         rxdp = &rxq->rx_ring[rxq->rx_tail];
2044         rxep = &rxq->sw_ring[rxq->rx_tail];
2045
2046         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
2047         rx_status = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
2048                     IAVF_RXD_QW1_STATUS_SHIFT;
2049
2050         /* Make sure there is at least 1 packet to receive */
2051         if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)))
2052                 return 0;
2053
2054         /* Scan LOOK_AHEAD descriptors at a time to determine which
2055          * descriptors reference packets that are ready to be received.
2056          */
2057         for (i = 0; i < IAVF_RX_MAX_BURST; i += IAVF_LOOK_AHEAD,
2058              rxdp += IAVF_LOOK_AHEAD, rxep += IAVF_LOOK_AHEAD) {
2059                 /* Read desc statuses backwards to avoid race condition */
2060                 for (j = IAVF_LOOK_AHEAD - 1; j >= 0; j--) {
2061                         qword1 = rte_le_to_cpu_64(
2062                                 rxdp[j].wb.qword1.status_error_len);
2063                         s[j] = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
2064                                IAVF_RXD_QW1_STATUS_SHIFT;
2065                 }
2066
2067                 /* This barrier is to order loads of different words in the descriptor */
2068                 rte_atomic_thread_fence(__ATOMIC_ACQUIRE);
2069
2070                 /* Compute how many contiguous DD bits were set */
2071                 for (j = 0, nb_dd = 0; j < IAVF_LOOK_AHEAD; j++) {
2072                         var = s[j] & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT);
2073 #ifdef RTE_ARCH_ARM
2074                         /* For Arm platforms, count only contiguous descriptors
2075                          * whose DD bit is set to 1. On Arm platforms, reads of
2076                          * descriptors can be reordered. Since the CPU may
2077                          * be reading the descriptors as the NIC updates them
2078                          * in memory, it is possbile that the DD bit for a
2079                          * descriptor earlier in the queue is read as not set
2080                          * while the DD bit for a descriptor later in the queue
2081                          * is read as set.
2082                          */
2083                         if (var)
2084                                 nb_dd += 1;
2085                         else
2086                                 break;
2087 #else
2088                         nb_dd += var;
2089 #endif
2090                 }
2091
2092                 /* Translate descriptor info to mbuf parameters */
2093                 for (j = 0; j < nb_dd; j++) {
2094                         IAVF_DUMP_RX_DESC(rxq, &rxdp[j],
2095                                          rxq->rx_tail + i * IAVF_LOOK_AHEAD + j);
2096
2097                         mb = rxep[j];
2098                         qword1 = rte_le_to_cpu_64
2099                                         (rxdp[j].wb.qword1.status_error_len);
2100                         pkt_len = ((qword1 & IAVF_RXD_QW1_LENGTH_PBUF_MASK) >>
2101                                   IAVF_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
2102                         mb->data_len = pkt_len;
2103                         mb->pkt_len = pkt_len;
2104                         mb->ol_flags = 0;
2105                         iavf_rxd_to_vlan_tci(mb, &rxdp[j]);
2106                         pkt_flags = iavf_rxd_to_pkt_flags(qword1);
2107                         mb->packet_type =
2108                                 ptype_tbl[(uint8_t)((qword1 &
2109                                 IAVF_RXD_QW1_PTYPE_MASK) >>
2110                                 IAVF_RXD_QW1_PTYPE_SHIFT)];
2111
2112                         if (pkt_flags & RTE_MBUF_F_RX_RSS_HASH)
2113                                 mb->hash.rss = rte_le_to_cpu_32(
2114                                         rxdp[j].wb.qword0.hi_dword.rss);
2115
2116                         if (pkt_flags & RTE_MBUF_F_RX_FDIR)
2117                                 pkt_flags |= iavf_rxd_build_fdir(&rxdp[j], mb);
2118
2119                         mb->ol_flags |= pkt_flags;
2120
2121                         /* Put up to nb_pkts directly into buffers */
2122                         if ((i + j) < nb_pkts) {
2123                                 rx_pkts[i + j] = rxep[j];
2124                                 nb_rx++;
2125                         } else { /* Stage excess pkts received */
2126                                 rxq->rx_stage[nb_staged] = rxep[j];
2127                                 nb_staged++;
2128                         }
2129                 }
2130
2131                 if (nb_dd != IAVF_LOOK_AHEAD)
2132                         break;
2133         }
2134
2135         /* Update rxq->rx_nb_avail to reflect number of staged pkts */
2136         rxq->rx_nb_avail = nb_staged;
2137
2138         /* Clear software ring entries */
2139         for (i = 0; i < (nb_rx + nb_staged); i++)
2140                 rxq->sw_ring[rxq->rx_tail + i] = NULL;
2141
2142         return nb_rx;
2143 }
2144
2145 static inline uint16_t
2146 iavf_rx_fill_from_stage(struct iavf_rx_queue *rxq,
2147                        struct rte_mbuf **rx_pkts,
2148                        uint16_t nb_pkts)
2149 {
2150         uint16_t i;
2151         struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
2152
2153         nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
2154
2155         for (i = 0; i < nb_pkts; i++)
2156                 rx_pkts[i] = stage[i];
2157
2158         rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
2159         rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
2160
2161         return nb_pkts;
2162 }
2163
2164 static inline int
2165 iavf_rx_alloc_bufs(struct iavf_rx_queue *rxq)
2166 {
2167         volatile union iavf_rx_desc *rxdp;
2168         struct rte_mbuf **rxep;
2169         struct rte_mbuf *mb;
2170         uint16_t alloc_idx, i;
2171         uint64_t dma_addr;
2172         int diag;
2173
2174         /* Allocate buffers in bulk */
2175         alloc_idx = (uint16_t)(rxq->rx_free_trigger -
2176                                 (rxq->rx_free_thresh - 1));
2177         rxep = &rxq->sw_ring[alloc_idx];
2178         diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
2179                                     rxq->rx_free_thresh);
2180         if (unlikely(diag != 0)) {
2181                 PMD_RX_LOG(ERR, "Failed to get mbufs in bulk");
2182                 return -ENOMEM;
2183         }
2184
2185         rxdp = &rxq->rx_ring[alloc_idx];
2186         for (i = 0; i < rxq->rx_free_thresh; i++) {
2187                 if (likely(i < (rxq->rx_free_thresh - 1)))
2188                         /* Prefetch next mbuf */
2189                         rte_prefetch0(rxep[i + 1]);
2190
2191                 mb = rxep[i];
2192                 rte_mbuf_refcnt_set(mb, 1);
2193                 mb->next = NULL;
2194                 mb->data_off = RTE_PKTMBUF_HEADROOM;
2195                 mb->nb_segs = 1;
2196                 mb->port = rxq->port_id;
2197                 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mb));
2198                 rxdp[i].read.hdr_addr = 0;
2199                 rxdp[i].read.pkt_addr = dma_addr;
2200         }
2201
2202         /* Update rx tail register */
2203         rte_wmb();
2204         IAVF_PCI_REG_WC_WRITE_RELAXED(rxq->qrx_tail, rxq->rx_free_trigger);
2205
2206         rxq->rx_free_trigger =
2207                 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
2208         if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
2209                 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2210
2211         return 0;
2212 }
2213
2214 static inline uint16_t
2215 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
2216 {
2217         struct iavf_rx_queue *rxq = (struct iavf_rx_queue *)rx_queue;
2218         uint16_t nb_rx = 0;
2219
2220         if (!nb_pkts)
2221                 return 0;
2222
2223         if (rxq->rx_nb_avail)
2224                 return iavf_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
2225
2226         if (rxq->rxdid >= IAVF_RXDID_FLEX_NIC && rxq->rxdid <= IAVF_RXDID_LAST)
2227                 nb_rx = (uint16_t)iavf_rx_scan_hw_ring_flex_rxd(rxq, rx_pkts, nb_pkts);
2228         else
2229                 nb_rx = (uint16_t)iavf_rx_scan_hw_ring(rxq, rx_pkts, nb_pkts);
2230
2231         rxq->rx_next_avail = 0;
2232         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx + rxq->rx_nb_avail);
2233
2234         if (rxq->rx_tail > rxq->rx_free_trigger) {
2235                 if (iavf_rx_alloc_bufs(rxq) != 0) {
2236                         uint16_t i, j, nb_staged;
2237
2238                         /* TODO: count rx_mbuf_alloc_failed here */
2239
2240                         nb_staged = rxq->rx_nb_avail;
2241                         rxq->rx_nb_avail = 0;
2242
2243                         rxq->rx_tail = (uint16_t)(rxq->rx_tail - (nb_rx + nb_staged));
2244                         for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++) {
2245                                 rxq->sw_ring[j] = rx_pkts[i];
2246                                 rx_pkts[i] = NULL;
2247                         }
2248                         for (i = 0, j = rxq->rx_tail + nb_rx; i < nb_staged; i++, j++) {
2249                                 rxq->sw_ring[j] = rxq->rx_stage[i];
2250                                 rx_pkts[i] = NULL;
2251                         }
2252
2253                         return 0;
2254                 }
2255         }
2256
2257         if (rxq->rx_tail >= rxq->nb_rx_desc)
2258                 rxq->rx_tail = 0;
2259
2260         PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u, nb_rx=%u",
2261                    rxq->port_id, rxq->queue_id,
2262                    rxq->rx_tail, nb_rx);
2263
2264         return nb_rx;
2265 }
2266
2267 static uint16_t
2268 iavf_recv_pkts_bulk_alloc(void *rx_queue,
2269                          struct rte_mbuf **rx_pkts,
2270                          uint16_t nb_pkts)
2271 {
2272         uint16_t nb_rx = 0, n, count;
2273
2274         if (unlikely(nb_pkts == 0))
2275                 return 0;
2276
2277         if (likely(nb_pkts <= IAVF_RX_MAX_BURST))
2278                 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
2279
2280         while (nb_pkts) {
2281                 n = RTE_MIN(nb_pkts, IAVF_RX_MAX_BURST);
2282                 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
2283                 nb_rx = (uint16_t)(nb_rx + count);
2284                 nb_pkts = (uint16_t)(nb_pkts - count);
2285                 if (count < n)
2286                         break;
2287         }
2288
2289         return nb_rx;
2290 }
2291
2292 static inline int
2293 iavf_xmit_cleanup(struct iavf_tx_queue *txq)
2294 {
2295         struct iavf_tx_entry *sw_ring = txq->sw_ring;
2296         uint16_t last_desc_cleaned = txq->last_desc_cleaned;
2297         uint16_t nb_tx_desc = txq->nb_tx_desc;
2298         uint16_t desc_to_clean_to;
2299         uint16_t nb_tx_to_clean;
2300
2301         volatile struct iavf_tx_desc *txd = txq->tx_ring;
2302
2303         desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->rs_thresh);
2304         if (desc_to_clean_to >= nb_tx_desc)
2305                 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
2306
2307         desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
2308         if ((txd[desc_to_clean_to].cmd_type_offset_bsz &
2309                         rte_cpu_to_le_64(IAVF_TXD_QW1_DTYPE_MASK)) !=
2310                         rte_cpu_to_le_64(IAVF_TX_DESC_DTYPE_DESC_DONE)) {
2311                 PMD_TX_LOG(DEBUG, "TX descriptor %4u is not done "
2312                            "(port=%d queue=%d)", desc_to_clean_to,
2313                            txq->port_id, txq->queue_id);
2314                 return -1;
2315         }
2316
2317         if (last_desc_cleaned > desc_to_clean_to)
2318                 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
2319                                                         desc_to_clean_to);
2320         else
2321                 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
2322                                         last_desc_cleaned);
2323
2324         txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
2325
2326         txq->last_desc_cleaned = desc_to_clean_to;
2327         txq->nb_free = (uint16_t)(txq->nb_free + nb_tx_to_clean);
2328
2329         return 0;
2330 }
2331
2332 /* Check if the context descriptor is needed for TX offloading */
2333 static inline uint16_t
2334 iavf_calc_context_desc(uint64_t flags, uint8_t vlan_flag)
2335 {
2336         if (flags & (RTE_MBUF_F_TX_TCP_SEG | RTE_MBUF_F_TX_UDP_SEG |
2337                         RTE_MBUF_F_TX_TUNNEL_MASK))
2338                 return 1;
2339         if (flags & RTE_MBUF_F_TX_VLAN &&
2340             vlan_flag & IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG2)
2341                 return 1;
2342         return 0;
2343 }
2344
2345 static inline void
2346 iavf_fill_ctx_desc_cmd_field(volatile uint64_t *field, struct rte_mbuf *m,
2347                 uint8_t vlan_flag)
2348 {
2349         uint64_t cmd = 0;
2350
2351         /* TSO enabled */
2352         if (m->ol_flags & (RTE_MBUF_F_TX_TCP_SEG | RTE_MBUF_F_TX_UDP_SEG))
2353                 cmd = IAVF_TX_CTX_DESC_TSO << IAVF_TXD_CTX_QW1_CMD_SHIFT;
2354
2355         if (m->ol_flags & RTE_MBUF_F_TX_VLAN &&
2356                         vlan_flag & IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG2) {
2357                 cmd |= IAVF_TX_CTX_DESC_IL2TAG2
2358                         << IAVF_TXD_CTX_QW1_CMD_SHIFT;
2359         }
2360
2361         *field |= cmd;
2362 }
2363
2364 static inline void
2365 iavf_fill_ctx_desc_ipsec_field(volatile uint64_t *field,
2366         struct iavf_ipsec_crypto_pkt_metadata *ipsec_md)
2367 {
2368         uint64_t ipsec_field =
2369                 (uint64_t)ipsec_md->ctx_desc_ipsec_params <<
2370                         IAVF_TXD_CTX_QW1_IPSEC_PARAMS_CIPHERBLK_SHIFT;
2371
2372         *field |= ipsec_field;
2373 }
2374
2375
2376 static inline void
2377 iavf_fill_ctx_desc_tunnelling_field(volatile uint64_t *qw0,
2378                 const struct rte_mbuf *m)
2379 {
2380         uint64_t eip_typ = IAVF_TX_CTX_DESC_EIPT_NONE;
2381         uint64_t eip_len = 0;
2382         uint64_t eip_noinc = 0;
2383         /* Default - IP_ID is increment in each segment of LSO */
2384
2385         switch (m->ol_flags & (RTE_MBUF_F_TX_OUTER_IPV4 |
2386                         RTE_MBUF_F_TX_OUTER_IPV6 |
2387                         RTE_MBUF_F_TX_OUTER_IP_CKSUM)) {
2388         case RTE_MBUF_F_TX_OUTER_IPV4:
2389                 eip_typ = IAVF_TX_CTX_DESC_EIPT_IPV4_NO_CHECKSUM_OFFLOAD;
2390                 eip_len = m->outer_l3_len >> 2;
2391         break;
2392         case RTE_MBUF_F_TX_OUTER_IPV4 | RTE_MBUF_F_TX_OUTER_IP_CKSUM:
2393                 eip_typ = IAVF_TX_CTX_DESC_EIPT_IPV4_CHECKSUM_OFFLOAD;
2394                 eip_len = m->outer_l3_len >> 2;
2395         break;
2396         case RTE_MBUF_F_TX_OUTER_IPV6:
2397                 eip_typ = IAVF_TX_CTX_DESC_EIPT_IPV6;
2398                 eip_len = m->outer_l3_len >> 2;
2399         break;
2400         }
2401
2402         *qw0 = eip_typ << IAVF_TXD_CTX_QW0_TUN_PARAMS_EIPT_SHIFT |
2403                 eip_len << IAVF_TXD_CTX_QW0_TUN_PARAMS_EIPLEN_SHIFT |
2404                 eip_noinc << IAVF_TXD_CTX_QW0_TUN_PARAMS_EIP_NOINC_SHIFT;
2405 }
2406
2407 static inline uint16_t
2408 iavf_fill_ctx_desc_segmentation_field(volatile uint64_t *field,
2409         struct rte_mbuf *m, struct iavf_ipsec_crypto_pkt_metadata *ipsec_md)
2410 {
2411         uint64_t segmentation_field = 0;
2412         uint64_t total_length = 0;
2413
2414         if (m->ol_flags & RTE_MBUF_F_TX_SEC_OFFLOAD) {
2415                 total_length = ipsec_md->l4_payload_len;
2416         } else {
2417                 total_length = m->pkt_len - (m->l2_len + m->l3_len + m->l4_len);
2418
2419                 if (m->ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK)
2420                         total_length -= m->outer_l3_len;
2421         }
2422
2423 #ifdef RTE_LIBRTE_IAVF_DEBUG_TX
2424         if (!m->l4_len || !m->tso_segsz)
2425                 PMD_TX_LOG(DEBUG, "L4 length %d, LSO Segment size %d",
2426                          m->l4_len, m->tso_segsz);
2427         if (m->tso_segsz < 88)
2428                 PMD_TX_LOG(DEBUG, "LSO Segment size %d is less than minimum %d",
2429                         m->tso_segsz, 88);
2430 #endif
2431         segmentation_field =
2432                 (((uint64_t)total_length << IAVF_TXD_CTX_QW1_TSO_LEN_SHIFT) &
2433                                 IAVF_TXD_CTX_QW1_TSO_LEN_MASK) |
2434                 (((uint64_t)m->tso_segsz << IAVF_TXD_CTX_QW1_MSS_SHIFT) &
2435                                 IAVF_TXD_CTX_QW1_MSS_MASK);
2436
2437         *field |= segmentation_field;
2438
2439         return total_length;
2440 }
2441
2442
2443 struct iavf_tx_context_desc_qws {
2444         __le64 qw0;
2445         __le64 qw1;
2446 };
2447
2448 static inline void
2449 iavf_fill_context_desc(volatile struct iavf_tx_context_desc *desc,
2450         struct rte_mbuf *m, struct iavf_ipsec_crypto_pkt_metadata *ipsec_md,
2451         uint16_t *tlen, uint8_t vlan_flag)
2452 {
2453         volatile struct iavf_tx_context_desc_qws *desc_qws =
2454                         (volatile struct iavf_tx_context_desc_qws *)desc;
2455         /* fill descriptor type field */
2456         desc_qws->qw1 = IAVF_TX_DESC_DTYPE_CONTEXT;
2457
2458         /* fill command field */
2459         iavf_fill_ctx_desc_cmd_field(&desc_qws->qw1, m, vlan_flag);
2460
2461         /* fill segmentation field */
2462         if (m->ol_flags & (RTE_MBUF_F_TX_TCP_SEG | RTE_MBUF_F_TX_UDP_SEG)) {
2463                 /* fill IPsec field */
2464                 if (m->ol_flags & RTE_MBUF_F_TX_SEC_OFFLOAD)
2465                         iavf_fill_ctx_desc_ipsec_field(&desc_qws->qw1,
2466                                 ipsec_md);
2467
2468                 *tlen = iavf_fill_ctx_desc_segmentation_field(&desc_qws->qw1,
2469                                 m, ipsec_md);
2470         }
2471
2472         /* fill tunnelling field */
2473         if (m->ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK)
2474                 iavf_fill_ctx_desc_tunnelling_field(&desc_qws->qw0, m);
2475         else
2476                 desc_qws->qw0 = 0;
2477
2478         desc_qws->qw0 = rte_cpu_to_le_64(desc_qws->qw0);
2479         desc_qws->qw1 = rte_cpu_to_le_64(desc_qws->qw1);
2480
2481         if (vlan_flag & IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG2)
2482                 desc->l2tag2 = m->vlan_tci;
2483 }
2484
2485
2486 static inline void
2487 iavf_fill_ipsec_desc(volatile struct iavf_tx_ipsec_desc *desc,
2488         const struct iavf_ipsec_crypto_pkt_metadata *md, uint16_t *ipsec_len)
2489 {
2490         desc->qw0 = rte_cpu_to_le_64(((uint64_t)md->l4_payload_len <<
2491                 IAVF_IPSEC_TX_DESC_QW0_L4PAYLEN_SHIFT) |
2492                 ((uint64_t)md->esn << IAVF_IPSEC_TX_DESC_QW0_IPSECESN_SHIFT) |
2493                 ((uint64_t)md->esp_trailer_len <<
2494                                 IAVF_IPSEC_TX_DESC_QW0_TRAILERLEN_SHIFT));
2495
2496         desc->qw1 = rte_cpu_to_le_64(((uint64_t)md->sa_idx <<
2497                 IAVF_IPSEC_TX_DESC_QW1_IPSECSA_SHIFT) |
2498                 ((uint64_t)md->next_proto <<
2499                                 IAVF_IPSEC_TX_DESC_QW1_IPSECNH_SHIFT) |
2500                 ((uint64_t)(md->len_iv & 0x3) <<
2501                                 IAVF_IPSEC_TX_DESC_QW1_IVLEN_SHIFT) |
2502                 ((uint64_t)(md->ol_flags & IAVF_IPSEC_CRYPTO_OL_FLAGS_NATT ?
2503                                 1ULL : 0ULL) <<
2504                                 IAVF_IPSEC_TX_DESC_QW1_UDP_SHIFT) |
2505                 (uint64_t)IAVF_TX_DESC_DTYPE_IPSEC);
2506
2507         /**
2508          * TODO: Pre-calculate this in the Session initialization
2509          *
2510          * Calculate IPsec length required in data descriptor func when TSO
2511          * offload is enabled
2512          */
2513         *ipsec_len = sizeof(struct rte_esp_hdr) + (md->len_iv >> 2) +
2514                         (md->ol_flags & IAVF_IPSEC_CRYPTO_OL_FLAGS_NATT ?
2515                         sizeof(struct rte_udp_hdr) : 0);
2516 }
2517
2518 static inline void
2519 iavf_build_data_desc_cmd_offset_fields(volatile uint64_t *qw1,
2520                 struct rte_mbuf *m, uint8_t vlan_flag)
2521 {
2522         uint64_t command = 0;
2523         uint64_t offset = 0;
2524         uint64_t l2tag1 = 0;
2525
2526         *qw1 = IAVF_TX_DESC_DTYPE_DATA;
2527
2528         command = (uint64_t)IAVF_TX_DESC_CMD_ICRC;
2529
2530         /* Descriptor based VLAN insertion */
2531         if ((vlan_flag & IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG1) &&
2532                         m->ol_flags & RTE_MBUF_F_TX_VLAN) {
2533                 command |= (uint64_t)IAVF_TX_DESC_CMD_IL2TAG1;
2534                 l2tag1 |= m->vlan_tci;
2535         }
2536
2537         /* Set MACLEN */
2538         offset |= (m->l2_len >> 1) << IAVF_TX_DESC_LENGTH_MACLEN_SHIFT;
2539
2540         /* Enable L3 checksum offloading inner */
2541         if (m->ol_flags & (RTE_MBUF_F_TX_IP_CKSUM | RTE_MBUF_F_TX_IPV4)) {
2542                 command |= IAVF_TX_DESC_CMD_IIPT_IPV4_CSUM;
2543                 offset |= (m->l3_len >> 2) << IAVF_TX_DESC_LENGTH_IPLEN_SHIFT;
2544         } else if (m->ol_flags & RTE_MBUF_F_TX_IPV4) {
2545                 command |= IAVF_TX_DESC_CMD_IIPT_IPV4;
2546                 offset |= (m->l3_len >> 2) << IAVF_TX_DESC_LENGTH_IPLEN_SHIFT;
2547         } else if (m->ol_flags & RTE_MBUF_F_TX_IPV6) {
2548                 command |= IAVF_TX_DESC_CMD_IIPT_IPV6;
2549                 offset |= (m->l3_len >> 2) << IAVF_TX_DESC_LENGTH_IPLEN_SHIFT;
2550         }
2551
2552         if (m->ol_flags & RTE_MBUF_F_TX_TCP_SEG) {
2553                 command |= IAVF_TX_DESC_CMD_L4T_EOFT_TCP;
2554                 offset |= (m->l4_len >> 2) <<
2555                               IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2556         }
2557
2558         /* Enable L4 checksum offloads */
2559         switch (m->ol_flags & RTE_MBUF_F_TX_L4_MASK) {
2560         case RTE_MBUF_F_TX_TCP_CKSUM:
2561                 command |= IAVF_TX_DESC_CMD_L4T_EOFT_TCP;
2562                 offset |= (sizeof(struct rte_tcp_hdr) >> 2) <<
2563                                 IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2564                 break;
2565         case RTE_MBUF_F_TX_SCTP_CKSUM:
2566                 command |= IAVF_TX_DESC_CMD_L4T_EOFT_SCTP;
2567                 offset |= (sizeof(struct rte_sctp_hdr) >> 2) <<
2568                                 IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2569                 break;
2570         case RTE_MBUF_F_TX_UDP_CKSUM:
2571                 command |= IAVF_TX_DESC_CMD_L4T_EOFT_UDP;
2572                 offset |= (sizeof(struct rte_udp_hdr) >> 2) <<
2573                                 IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2574                 break;
2575         }
2576
2577         *qw1 = rte_cpu_to_le_64((((uint64_t)command <<
2578                 IAVF_TXD_DATA_QW1_CMD_SHIFT) & IAVF_TXD_DATA_QW1_CMD_MASK) |
2579                 (((uint64_t)offset << IAVF_TXD_DATA_QW1_OFFSET_SHIFT) &
2580                 IAVF_TXD_DATA_QW1_OFFSET_MASK) |
2581                 ((uint64_t)l2tag1 << IAVF_TXD_DATA_QW1_L2TAG1_SHIFT));
2582 }
2583
2584 static inline void
2585 iavf_fill_data_desc(volatile struct iavf_tx_desc *desc,
2586         struct rte_mbuf *m, uint64_t desc_template,
2587         uint16_t tlen, uint16_t ipseclen)
2588 {
2589         uint32_t hdrlen = m->l2_len;
2590         uint32_t bufsz = 0;
2591
2592         /* fill data descriptor qw1 from template */
2593         desc->cmd_type_offset_bsz = desc_template;
2594
2595         /* set data buffer address */
2596         desc->buffer_addr = rte_mbuf_data_iova(m);
2597
2598         /* calculate data buffer size less set header lengths */
2599         if ((m->ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK) &&
2600                         (m->ol_flags & (RTE_MBUF_F_TX_TCP_SEG |
2601                                         RTE_MBUF_F_TX_UDP_SEG))) {
2602                 hdrlen += m->outer_l3_len;
2603                 if (m->ol_flags & RTE_MBUF_F_TX_L4_MASK)
2604                         hdrlen += m->l3_len + m->l4_len;
2605                 else
2606                         hdrlen += m->l3_len;
2607                 if (m->ol_flags & RTE_MBUF_F_TX_SEC_OFFLOAD)
2608                         hdrlen += ipseclen;
2609                 bufsz = hdrlen + tlen;
2610         } else if ((m->ol_flags & RTE_MBUF_F_TX_SEC_OFFLOAD) &&
2611                         (m->ol_flags & (RTE_MBUF_F_TX_TCP_SEG |
2612                                         RTE_MBUF_F_TX_UDP_SEG))) {
2613                 hdrlen += m->outer_l3_len + m->l3_len + ipseclen;
2614                 if (m->ol_flags & RTE_MBUF_F_TX_L4_MASK)
2615                         hdrlen += m->l4_len;
2616                 bufsz = hdrlen + tlen;
2617
2618         } else {
2619                 bufsz = m->data_len;
2620         }
2621
2622         /* set data buffer size */
2623         desc->cmd_type_offset_bsz |=
2624                 (((uint64_t)bufsz << IAVF_TXD_DATA_QW1_TX_BUF_SZ_SHIFT) &
2625                 IAVF_TXD_DATA_QW1_TX_BUF_SZ_MASK);
2626
2627         desc->buffer_addr = rte_cpu_to_le_64(desc->buffer_addr);
2628         desc->cmd_type_offset_bsz = rte_cpu_to_le_64(desc->cmd_type_offset_bsz);
2629 }
2630
2631
2632 static struct iavf_ipsec_crypto_pkt_metadata *
2633 iavf_ipsec_crypto_get_pkt_metadata(const struct iavf_tx_queue *txq,
2634                 struct rte_mbuf *m)
2635 {
2636         if (m->ol_flags & RTE_MBUF_F_TX_SEC_OFFLOAD)
2637                 return RTE_MBUF_DYNFIELD(m, txq->ipsec_crypto_pkt_md_offset,
2638                                 struct iavf_ipsec_crypto_pkt_metadata *);
2639
2640         return NULL;
2641 }
2642
2643 /* TX function */
2644 uint16_t
2645 iavf_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2646 {
2647         struct iavf_tx_queue *txq = tx_queue;
2648         volatile struct iavf_tx_desc *txr = txq->tx_ring;
2649         struct iavf_tx_entry *txe_ring = txq->sw_ring;
2650         struct iavf_tx_entry *txe, *txn;
2651         struct rte_mbuf *mb, *mb_seg;
2652         uint16_t desc_idx, desc_idx_last;
2653         uint16_t idx;
2654
2655
2656         /* Check if the descriptor ring needs to be cleaned. */
2657         if (txq->nb_free < txq->free_thresh)
2658                 iavf_xmit_cleanup(txq);
2659
2660         desc_idx = txq->tx_tail;
2661         txe = &txe_ring[desc_idx];
2662
2663         for (idx = 0; idx < nb_pkts; idx++) {
2664                 volatile struct iavf_tx_desc *ddesc;
2665                 struct iavf_ipsec_crypto_pkt_metadata *ipsec_md;
2666
2667                 uint16_t nb_desc_ctx, nb_desc_ipsec;
2668                 uint16_t nb_desc_data, nb_desc_required;
2669                 uint16_t tlen = 0, ipseclen = 0;
2670                 uint64_t ddesc_template = 0;
2671                 uint64_t ddesc_cmd = 0;
2672
2673                 mb = tx_pkts[idx];
2674
2675                 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
2676
2677                 /**
2678                  * Get metadata for ipsec crypto from mbuf dynamic fields if
2679                  * security offload is specified.
2680                  */
2681                 ipsec_md = iavf_ipsec_crypto_get_pkt_metadata(txq, mb);
2682
2683                 nb_desc_data = mb->nb_segs;
2684                 nb_desc_ctx =
2685                         iavf_calc_context_desc(mb->ol_flags, txq->vlan_flag);
2686                 nb_desc_ipsec = !!(mb->ol_flags & RTE_MBUF_F_TX_SEC_OFFLOAD);
2687
2688                 /**
2689                  * The number of descriptors that must be allocated for
2690                  * a packet equals to the number of the segments of that
2691                  * packet plus the context and ipsec descriptors if needed.
2692                  */
2693                 nb_desc_required = nb_desc_data + nb_desc_ctx + nb_desc_ipsec;
2694
2695                 desc_idx_last = (uint16_t)(desc_idx + nb_desc_required - 1);
2696
2697                 /* wrap descriptor ring */
2698                 if (desc_idx_last >= txq->nb_tx_desc)
2699                         desc_idx_last =
2700                                 (uint16_t)(desc_idx_last - txq->nb_tx_desc);
2701
2702                 PMD_TX_LOG(DEBUG,
2703                         "port_id=%u queue_id=%u tx_first=%u tx_last=%u",
2704                         txq->port_id, txq->queue_id, desc_idx, desc_idx_last);
2705
2706                 if (nb_desc_required > txq->nb_free) {
2707                         if (iavf_xmit_cleanup(txq)) {
2708                                 if (idx == 0)
2709                                         return 0;
2710                                 goto end_of_tx;
2711                         }
2712                         if (unlikely(nb_desc_required > txq->rs_thresh)) {
2713                                 while (nb_desc_required > txq->nb_free) {
2714                                         if (iavf_xmit_cleanup(txq)) {
2715                                                 if (idx == 0)
2716                                                         return 0;
2717                                                 goto end_of_tx;
2718                                         }
2719                                 }
2720                         }
2721                 }
2722
2723                 iavf_build_data_desc_cmd_offset_fields(&ddesc_template, mb,
2724                         txq->vlan_flag);
2725
2726                         /* Setup TX context descriptor if required */
2727                 if (nb_desc_ctx) {
2728                         volatile struct iavf_tx_context_desc *ctx_desc =
2729                                 (volatile struct iavf_tx_context_desc *)
2730                                         &txr[desc_idx];
2731
2732                         /* clear QW0 or the previous writeback value
2733                          * may impact next write
2734                          */
2735                         *(volatile uint64_t *)ctx_desc = 0;
2736
2737                         txn = &txe_ring[txe->next_id];
2738                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
2739
2740                         if (txe->mbuf) {
2741                                 rte_pktmbuf_free_seg(txe->mbuf);
2742                                 txe->mbuf = NULL;
2743                         }
2744
2745                         iavf_fill_context_desc(ctx_desc, mb, ipsec_md, &tlen,
2746                                 txq->vlan_flag);
2747                         IAVF_DUMP_TX_DESC(txq, ctx_desc, desc_idx);
2748
2749                         txe->last_id = desc_idx_last;
2750                         desc_idx = txe->next_id;
2751                         txe = txn;
2752                         }
2753
2754                 if (nb_desc_ipsec) {
2755                         volatile struct iavf_tx_ipsec_desc *ipsec_desc =
2756                                 (volatile struct iavf_tx_ipsec_desc *)
2757                                         &txr[desc_idx];
2758
2759                         txn = &txe_ring[txe->next_id];
2760                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
2761
2762                         if (txe->mbuf) {
2763                                 rte_pktmbuf_free_seg(txe->mbuf);
2764                                 txe->mbuf = NULL;
2765                 }
2766
2767                         iavf_fill_ipsec_desc(ipsec_desc, ipsec_md, &ipseclen);
2768
2769                         IAVF_DUMP_TX_DESC(txq, ipsec_desc, desc_idx);
2770
2771                         txe->last_id = desc_idx_last;
2772                         desc_idx = txe->next_id;
2773                         txe = txn;
2774                 }
2775
2776                 mb_seg = mb;
2777
2778                 do {
2779                         ddesc = (volatile struct iavf_tx_desc *)
2780                                         &txr[desc_idx];
2781
2782                         txn = &txe_ring[txe->next_id];
2783                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
2784
2785                         if (txe->mbuf)
2786                                 rte_pktmbuf_free_seg(txe->mbuf);
2787
2788                         txe->mbuf = mb_seg;
2789                         iavf_fill_data_desc(ddesc, mb_seg,
2790                                         ddesc_template, tlen, ipseclen);
2791
2792                         IAVF_DUMP_TX_DESC(txq, ddesc, desc_idx);
2793
2794                         txe->last_id = desc_idx_last;
2795                         desc_idx = txe->next_id;
2796                         txe = txn;
2797                         mb_seg = mb_seg->next;
2798                 } while (mb_seg);
2799
2800                 /* The last packet data descriptor needs End Of Packet (EOP) */
2801                 ddesc_cmd = IAVF_TX_DESC_CMD_EOP;
2802
2803                 txq->nb_used = (uint16_t)(txq->nb_used + nb_desc_required);
2804                 txq->nb_free = (uint16_t)(txq->nb_free - nb_desc_required);
2805
2806                 if (txq->nb_used >= txq->rs_thresh) {
2807                         PMD_TX_LOG(DEBUG, "Setting RS bit on TXD id="
2808                                    "%4u (port=%d queue=%d)",
2809                                    desc_idx_last, txq->port_id, txq->queue_id);
2810
2811                         ddesc_cmd |= IAVF_TX_DESC_CMD_RS;
2812
2813                         /* Update txq RS bit counters */
2814                         txq->nb_used = 0;
2815                 }
2816
2817                 ddesc->cmd_type_offset_bsz |= rte_cpu_to_le_64(ddesc_cmd <<
2818                                 IAVF_TXD_DATA_QW1_CMD_SHIFT);
2819
2820                 IAVF_DUMP_TX_DESC(txq, ddesc, desc_idx - 1);
2821         }
2822
2823 end_of_tx:
2824         rte_wmb();
2825
2826         PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
2827                    txq->port_id, txq->queue_id, desc_idx, idx);
2828
2829         IAVF_PCI_REG_WRITE_RELAXED(txq->qtx_tail, desc_idx);
2830         txq->tx_tail = desc_idx;
2831
2832         return idx;
2833 }
2834
2835 /* Check if the packet with vlan user priority is transmitted in the
2836  * correct queue.
2837  */
2838 static int
2839 iavf_check_vlan_up2tc(struct iavf_tx_queue *txq, struct rte_mbuf *m)
2840 {
2841         struct rte_eth_dev *dev = &rte_eth_devices[txq->port_id];
2842         struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2843         uint16_t up;
2844
2845         up = m->vlan_tci >> IAVF_VLAN_TAG_PCP_OFFSET;
2846
2847         if (!(vf->qos_cap->cap[txq->tc].tc_prio & BIT(up))) {
2848                 PMD_TX_LOG(ERR, "packet with vlan pcp %u cannot transmit in queue %u\n",
2849                         up, txq->queue_id);
2850                 return -1;
2851         } else {
2852                 return 0;
2853         }
2854 }
2855
2856 /* TX prep functions */
2857 uint16_t
2858 iavf_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
2859               uint16_t nb_pkts)
2860 {
2861         int i, ret;
2862         uint64_t ol_flags;
2863         struct rte_mbuf *m;
2864         struct iavf_tx_queue *txq = tx_queue;
2865         struct rte_eth_dev *dev = &rte_eth_devices[txq->port_id];
2866         struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2867         struct iavf_adapter *adapter = IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2868
2869         if (adapter->closed)
2870                 return 0;
2871
2872         for (i = 0; i < nb_pkts; i++) {
2873                 m = tx_pkts[i];
2874                 ol_flags = m->ol_flags;
2875
2876                 /* Check condition for nb_segs > IAVF_TX_MAX_MTU_SEG. */
2877                 if (!(ol_flags & RTE_MBUF_F_TX_TCP_SEG)) {
2878                         if (m->nb_segs > IAVF_TX_MAX_MTU_SEG) {
2879                                 rte_errno = EINVAL;
2880                                 return i;
2881                         }
2882                 } else if ((m->tso_segsz < IAVF_MIN_TSO_MSS) ||
2883                            (m->tso_segsz > IAVF_MAX_TSO_MSS)) {
2884                         /* MSS outside the range are considered malicious */
2885                         rte_errno = EINVAL;
2886                         return i;
2887                 }
2888
2889                 if (ol_flags & IAVF_TX_OFFLOAD_NOTSUP_MASK) {
2890                         rte_errno = ENOTSUP;
2891                         return i;
2892                 }
2893
2894 #ifdef RTE_ETHDEV_DEBUG_TX
2895                 ret = rte_validate_tx_offload(m);
2896                 if (ret != 0) {
2897                         rte_errno = -ret;
2898                         return i;
2899                 }
2900 #endif
2901                 ret = rte_net_intel_cksum_prepare(m);
2902                 if (ret != 0) {
2903                         rte_errno = -ret;
2904                         return i;
2905                 }
2906
2907                 if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_QOS &&
2908                     ol_flags & (RTE_MBUF_F_RX_VLAN_STRIPPED | RTE_MBUF_F_RX_VLAN)) {
2909                         ret = iavf_check_vlan_up2tc(txq, m);
2910                         if (ret != 0) {
2911                                 rte_errno = -ret;
2912                                 return i;
2913                         }
2914                 }
2915         }
2916
2917         return i;
2918 }
2919
2920 /* choose rx function*/
2921 void
2922 iavf_set_rx_function(struct rte_eth_dev *dev)
2923 {
2924         struct iavf_adapter *adapter =
2925                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2926         struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2927         int i;
2928         struct iavf_rx_queue *rxq;
2929         bool use_flex = true;
2930
2931         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2932                 rxq = dev->data->rx_queues[i];
2933                 if (rxq->rxdid <= IAVF_RXDID_LEGACY_1) {
2934                         PMD_DRV_LOG(NOTICE, "request RXDID[%d] in Queue[%d] is legacy, "
2935                                 "set rx_pkt_burst as legacy for all queues", rxq->rxdid, i);
2936                         use_flex = false;
2937                 } else if (!(vf->supported_rxdid & BIT(rxq->rxdid))) {
2938                         PMD_DRV_LOG(NOTICE, "request RXDID[%d] in Queue[%d] is not supported, "
2939                                 "set rx_pkt_burst as legacy for all queues", rxq->rxdid, i);
2940                         use_flex = false;
2941                 }
2942         }
2943
2944 #ifdef RTE_ARCH_X86
2945         int check_ret;
2946         bool use_avx2 = false;
2947         bool use_avx512 = false;
2948
2949         check_ret = iavf_rx_vec_dev_check(dev);
2950         if (check_ret >= 0 &&
2951             rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
2952                 if ((rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
2953                      rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) &&
2954                     rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256)
2955                         use_avx2 = true;
2956
2957 #ifdef CC_AVX512_SUPPORT
2958                 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 &&
2959                     rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1 &&
2960                     rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512)
2961                         use_avx512 = true;
2962 #endif
2963
2964                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2965                         rxq = dev->data->rx_queues[i];
2966                         (void)iavf_rxq_vec_setup(rxq);
2967                 }
2968
2969                 if (dev->data->scattered_rx) {
2970                         if (!use_avx512) {
2971                                 PMD_DRV_LOG(DEBUG,
2972                                             "Using %sVector Scattered Rx (port %d).",
2973                                             use_avx2 ? "avx2 " : "",
2974                                             dev->data->port_id);
2975                         } else {
2976                                 if (check_ret == IAVF_VECTOR_PATH)
2977                                         PMD_DRV_LOG(DEBUG,
2978                                                     "Using AVX512 Vector Scattered Rx (port %d).",
2979                                                     dev->data->port_id);
2980                                 else
2981                                         PMD_DRV_LOG(DEBUG,
2982                                                     "Using AVX512 OFFLOAD Vector Scattered Rx (port %d).",
2983                                                     dev->data->port_id);
2984                         }
2985                         if (use_flex) {
2986                                 dev->rx_pkt_burst = use_avx2 ?
2987                                         iavf_recv_scattered_pkts_vec_avx2_flex_rxd :
2988                                         iavf_recv_scattered_pkts_vec_flex_rxd;
2989 #ifdef CC_AVX512_SUPPORT
2990                                 if (use_avx512) {
2991                                         if (check_ret == IAVF_VECTOR_PATH)
2992                                                 dev->rx_pkt_burst =
2993                                                         iavf_recv_scattered_pkts_vec_avx512_flex_rxd;
2994                                         else
2995                                                 dev->rx_pkt_burst =
2996                                                         iavf_recv_scattered_pkts_vec_avx512_flex_rxd_offload;
2997                                 }
2998 #endif
2999                         } else {
3000                                 dev->rx_pkt_burst = use_avx2 ?
3001                                         iavf_recv_scattered_pkts_vec_avx2 :
3002                                         iavf_recv_scattered_pkts_vec;
3003 #ifdef CC_AVX512_SUPPORT
3004                                 if (use_avx512) {
3005                                         if (check_ret == IAVF_VECTOR_PATH)
3006                                                 dev->rx_pkt_burst =
3007                                                         iavf_recv_scattered_pkts_vec_avx512;
3008                                         else
3009                                                 dev->rx_pkt_burst =
3010                                                         iavf_recv_scattered_pkts_vec_avx512_offload;
3011                                 }
3012 #endif
3013                         }
3014                 } else {
3015                         if (!use_avx512) {
3016                                 PMD_DRV_LOG(DEBUG, "Using %sVector Rx (port %d).",
3017                                             use_avx2 ? "avx2 " : "",
3018                                             dev->data->port_id);
3019                         } else {
3020                                 if (check_ret == IAVF_VECTOR_PATH)
3021                                         PMD_DRV_LOG(DEBUG,
3022                                                     "Using AVX512 Vector Rx (port %d).",
3023                                                     dev->data->port_id);
3024                                 else
3025                                         PMD_DRV_LOG(DEBUG,
3026                                                     "Using AVX512 OFFLOAD Vector Rx (port %d).",
3027                                                     dev->data->port_id);
3028                         }
3029                         if (use_flex) {
3030                                 dev->rx_pkt_burst = use_avx2 ?
3031                                         iavf_recv_pkts_vec_avx2_flex_rxd :
3032                                         iavf_recv_pkts_vec_flex_rxd;
3033 #ifdef CC_AVX512_SUPPORT
3034                                 if (use_avx512) {
3035                                         if (check_ret == IAVF_VECTOR_PATH)
3036                                                 dev->rx_pkt_burst =
3037                                                         iavf_recv_pkts_vec_avx512_flex_rxd;
3038                                         else
3039                                                 dev->rx_pkt_burst =
3040                                                         iavf_recv_pkts_vec_avx512_flex_rxd_offload;
3041                                 }
3042 #endif
3043                         } else {
3044                                 dev->rx_pkt_burst = use_avx2 ?
3045                                         iavf_recv_pkts_vec_avx2 :
3046                                         iavf_recv_pkts_vec;
3047 #ifdef CC_AVX512_SUPPORT
3048                                 if (use_avx512) {
3049                                         if (check_ret == IAVF_VECTOR_PATH)
3050                                                 dev->rx_pkt_burst =
3051                                                         iavf_recv_pkts_vec_avx512;
3052                                         else
3053                                                 dev->rx_pkt_burst =
3054                                                         iavf_recv_pkts_vec_avx512_offload;
3055                                 }
3056 #endif
3057                         }
3058                 }
3059
3060                 return;
3061         }
3062 #elif defined RTE_ARCH_ARM
3063         int check_ret;
3064
3065         check_ret = iavf_rx_vec_dev_check(dev);
3066         if (check_ret >= 0 &&
3067             rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
3068                 PMD_DRV_LOG(DEBUG, "Using a Vector Rx callback (port=%d).",
3069                             dev->data->port_id);
3070                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3071                         rxq = dev->data->rx_queues[i];
3072                         (void)iavf_rxq_vec_setup(rxq);
3073                 }
3074                 dev->rx_pkt_burst = iavf_recv_pkts_vec;
3075                 return;
3076         }
3077 #endif
3078         if (dev->data->scattered_rx) {
3079                 PMD_DRV_LOG(DEBUG, "Using a Scattered Rx callback (port=%d).",
3080                             dev->data->port_id);
3081                 if (use_flex)
3082                         dev->rx_pkt_burst = iavf_recv_scattered_pkts_flex_rxd;
3083                 else
3084                         dev->rx_pkt_burst = iavf_recv_scattered_pkts;
3085         } else if (adapter->rx_bulk_alloc_allowed) {
3086                 PMD_DRV_LOG(DEBUG, "Using bulk Rx callback (port=%d).",
3087                             dev->data->port_id);
3088                 dev->rx_pkt_burst = iavf_recv_pkts_bulk_alloc;
3089         } else {
3090                 PMD_DRV_LOG(DEBUG, "Using Basic Rx callback (port=%d).",
3091                             dev->data->port_id);
3092                 if (use_flex)
3093                         dev->rx_pkt_burst = iavf_recv_pkts_flex_rxd;
3094                 else
3095                         dev->rx_pkt_burst = iavf_recv_pkts;
3096         }
3097 }
3098
3099 /* choose tx function*/
3100 void
3101 iavf_set_tx_function(struct rte_eth_dev *dev)
3102 {
3103 #ifdef RTE_ARCH_X86
3104         struct iavf_tx_queue *txq;
3105         int i;
3106         int check_ret;
3107         bool use_sse = false;
3108         bool use_avx2 = false;
3109         bool use_avx512 = false;
3110
3111         check_ret = iavf_tx_vec_dev_check(dev);
3112
3113         if (check_ret >= 0 &&
3114             rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
3115                 /* SSE and AVX2 not support offload path yet. */
3116                 if (check_ret == IAVF_VECTOR_PATH) {
3117                         use_sse = true;
3118                         if ((rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
3119                              rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) &&
3120                             rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256)
3121                                 use_avx2 = true;
3122                 }
3123 #ifdef CC_AVX512_SUPPORT
3124                 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 &&
3125                     rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1 &&
3126                     rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512)
3127                         use_avx512 = true;
3128 #endif
3129
3130                 if (!use_sse && !use_avx2 && !use_avx512)
3131                         goto normal;
3132
3133                 if (!use_avx512) {
3134                         PMD_DRV_LOG(DEBUG, "Using %sVector Tx (port %d).",
3135                                     use_avx2 ? "avx2 " : "",
3136                                     dev->data->port_id);
3137                         dev->tx_pkt_burst = use_avx2 ?
3138                                             iavf_xmit_pkts_vec_avx2 :
3139                                             iavf_xmit_pkts_vec;
3140                 }
3141                 dev->tx_pkt_prepare = NULL;
3142 #ifdef CC_AVX512_SUPPORT
3143                 if (use_avx512) {
3144                         if (check_ret == IAVF_VECTOR_PATH) {
3145                                 dev->tx_pkt_burst = iavf_xmit_pkts_vec_avx512;
3146                                 PMD_DRV_LOG(DEBUG, "Using AVX512 Vector Tx (port %d).",
3147                                             dev->data->port_id);
3148                         } else {
3149                                 dev->tx_pkt_burst = iavf_xmit_pkts_vec_avx512_offload;
3150                                 dev->tx_pkt_prepare = iavf_prep_pkts;
3151                                 PMD_DRV_LOG(DEBUG, "Using AVX512 OFFLOAD Vector Tx (port %d).",
3152                                             dev->data->port_id);
3153                         }
3154                 }
3155 #endif
3156
3157                 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3158                         txq = dev->data->tx_queues[i];
3159                         if (!txq)
3160                                 continue;
3161 #ifdef CC_AVX512_SUPPORT
3162                         if (use_avx512)
3163                                 iavf_txq_vec_setup_avx512(txq);
3164                         else
3165                                 iavf_txq_vec_setup(txq);
3166 #else
3167                         iavf_txq_vec_setup(txq);
3168 #endif
3169                 }
3170
3171                 return;
3172         }
3173
3174 normal:
3175 #endif
3176         PMD_DRV_LOG(DEBUG, "Using Basic Tx callback (port=%d).",
3177                     dev->data->port_id);
3178         dev->tx_pkt_burst = iavf_xmit_pkts;
3179         dev->tx_pkt_prepare = iavf_prep_pkts;
3180 }
3181
3182 static int
3183 iavf_tx_done_cleanup_full(struct iavf_tx_queue *txq,
3184                         uint32_t free_cnt)
3185 {
3186         struct iavf_tx_entry *swr_ring = txq->sw_ring;
3187         uint16_t i, tx_last, tx_id;
3188         uint16_t nb_tx_free_last;
3189         uint16_t nb_tx_to_clean;
3190         uint32_t pkt_cnt;
3191
3192         /* Start free mbuf from the next of tx_tail */
3193         tx_last = txq->tx_tail;
3194         tx_id  = swr_ring[tx_last].next_id;
3195
3196         if (txq->nb_free == 0 && iavf_xmit_cleanup(txq))
3197                 return 0;
3198
3199         nb_tx_to_clean = txq->nb_free;
3200         nb_tx_free_last = txq->nb_free;
3201         if (!free_cnt)
3202                 free_cnt = txq->nb_tx_desc;
3203
3204         /* Loop through swr_ring to count the amount of
3205          * freeable mubfs and packets.
3206          */
3207         for (pkt_cnt = 0; pkt_cnt < free_cnt; ) {
3208                 for (i = 0; i < nb_tx_to_clean &&
3209                         pkt_cnt < free_cnt &&
3210                         tx_id != tx_last; i++) {
3211                         if (swr_ring[tx_id].mbuf != NULL) {
3212                                 rte_pktmbuf_free_seg(swr_ring[tx_id].mbuf);
3213                                 swr_ring[tx_id].mbuf = NULL;
3214
3215                                 /*
3216                                  * last segment in the packet,
3217                                  * increment packet count
3218                                  */
3219                                 pkt_cnt += (swr_ring[tx_id].last_id == tx_id);
3220                         }
3221
3222                         tx_id = swr_ring[tx_id].next_id;
3223                 }
3224
3225                 if (txq->rs_thresh > txq->nb_tx_desc -
3226                         txq->nb_free || tx_id == tx_last)
3227                         break;
3228
3229                 if (pkt_cnt < free_cnt) {
3230                         if (iavf_xmit_cleanup(txq))
3231                                 break;
3232
3233                         nb_tx_to_clean = txq->nb_free - nb_tx_free_last;
3234                         nb_tx_free_last = txq->nb_free;
3235                 }
3236         }
3237
3238         return (int)pkt_cnt;
3239 }
3240
3241 int
3242 iavf_dev_tx_done_cleanup(void *txq, uint32_t free_cnt)
3243 {
3244         struct iavf_tx_queue *q = (struct iavf_tx_queue *)txq;
3245
3246         return iavf_tx_done_cleanup_full(q, free_cnt);
3247 }
3248
3249 void
3250 iavf_dev_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
3251                      struct rte_eth_rxq_info *qinfo)
3252 {
3253         struct iavf_rx_queue *rxq;
3254
3255         rxq = dev->data->rx_queues[queue_id];
3256
3257         qinfo->mp = rxq->mp;
3258         qinfo->scattered_rx = dev->data->scattered_rx;
3259         qinfo->nb_desc = rxq->nb_rx_desc;
3260
3261         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
3262         qinfo->conf.rx_drop_en = true;
3263         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
3264 }
3265
3266 void
3267 iavf_dev_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
3268                      struct rte_eth_txq_info *qinfo)
3269 {
3270         struct iavf_tx_queue *txq;
3271
3272         txq = dev->data->tx_queues[queue_id];
3273
3274         qinfo->nb_desc = txq->nb_tx_desc;
3275
3276         qinfo->conf.tx_free_thresh = txq->free_thresh;
3277         qinfo->conf.tx_rs_thresh = txq->rs_thresh;
3278         qinfo->conf.offloads = txq->offloads;
3279         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
3280 }
3281
3282 /* Get the number of used descriptors of a rx queue */
3283 uint32_t
3284 iavf_dev_rxq_count(void *rx_queue)
3285 {
3286 #define IAVF_RXQ_SCAN_INTERVAL 4
3287         volatile union iavf_rx_desc *rxdp;
3288         struct iavf_rx_queue *rxq;
3289         uint16_t desc = 0;
3290
3291         rxq = rx_queue;
3292         rxdp = &rxq->rx_ring[rxq->rx_tail];
3293
3294         while ((desc < rxq->nb_rx_desc) &&
3295                ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
3296                  IAVF_RXD_QW1_STATUS_MASK) >> IAVF_RXD_QW1_STATUS_SHIFT) &
3297                (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)) {
3298                 /* Check the DD bit of a rx descriptor of each 4 in a group,
3299                  * to avoid checking too frequently and downgrading performance
3300                  * too much.
3301                  */
3302                 desc += IAVF_RXQ_SCAN_INTERVAL;
3303                 rxdp += IAVF_RXQ_SCAN_INTERVAL;
3304                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
3305                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
3306                                         desc - rxq->nb_rx_desc]);
3307         }
3308
3309         return desc;
3310 }
3311
3312 int
3313 iavf_dev_rx_desc_status(void *rx_queue, uint16_t offset)
3314 {
3315         struct iavf_rx_queue *rxq = rx_queue;
3316         volatile uint64_t *status;
3317         uint64_t mask;
3318         uint32_t desc;
3319
3320         if (unlikely(offset >= rxq->nb_rx_desc))
3321                 return -EINVAL;
3322
3323         if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
3324                 return RTE_ETH_RX_DESC_UNAVAIL;
3325
3326         desc = rxq->rx_tail + offset;
3327         if (desc >= rxq->nb_rx_desc)
3328                 desc -= rxq->nb_rx_desc;
3329
3330         status = &rxq->rx_ring[desc].wb.qword1.status_error_len;
3331         mask = rte_le_to_cpu_64((1ULL << IAVF_RX_DESC_STATUS_DD_SHIFT)
3332                 << IAVF_RXD_QW1_STATUS_SHIFT);
3333         if (*status & mask)
3334                 return RTE_ETH_RX_DESC_DONE;
3335
3336         return RTE_ETH_RX_DESC_AVAIL;
3337 }
3338
3339 int
3340 iavf_dev_tx_desc_status(void *tx_queue, uint16_t offset)
3341 {
3342         struct iavf_tx_queue *txq = tx_queue;
3343         volatile uint64_t *status;
3344         uint64_t mask, expect;
3345         uint32_t desc;
3346
3347         if (unlikely(offset >= txq->nb_tx_desc))
3348                 return -EINVAL;
3349
3350         desc = txq->tx_tail + offset;
3351         /* go to next desc that has the RS bit */
3352         desc = ((desc + txq->rs_thresh - 1) / txq->rs_thresh) *
3353                 txq->rs_thresh;
3354         if (desc >= txq->nb_tx_desc) {
3355                 desc -= txq->nb_tx_desc;
3356                 if (desc >= txq->nb_tx_desc)
3357                         desc -= txq->nb_tx_desc;
3358         }
3359
3360         status = &txq->tx_ring[desc].cmd_type_offset_bsz;
3361         mask = rte_le_to_cpu_64(IAVF_TXD_QW1_DTYPE_MASK);
3362         expect = rte_cpu_to_le_64(
3363                  IAVF_TX_DESC_DTYPE_DESC_DONE << IAVF_TXD_QW1_DTYPE_SHIFT);
3364         if ((*status & mask) == expect)
3365                 return RTE_ETH_TX_DESC_DONE;
3366
3367         return RTE_ETH_TX_DESC_FULL;
3368 }
3369
3370 static inline uint32_t
3371 iavf_get_default_ptype(uint16_t ptype)
3372 {
3373         static const uint32_t ptype_tbl[IAVF_MAX_PKT_TYPE]
3374                 __rte_cache_aligned = {
3375                 /* L2 types */
3376                 /* [0] reserved */
3377                 [1] = RTE_PTYPE_L2_ETHER,
3378                 [2] = RTE_PTYPE_L2_ETHER_TIMESYNC,
3379                 /* [3] - [5] reserved */
3380                 [6] = RTE_PTYPE_L2_ETHER_LLDP,
3381                 /* [7] - [10] reserved */
3382                 [11] = RTE_PTYPE_L2_ETHER_ARP,
3383                 /* [12] - [21] reserved */
3384
3385                 /* Non tunneled IPv4 */
3386                 [22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3387                        RTE_PTYPE_L4_FRAG,
3388                 [23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3389                        RTE_PTYPE_L4_NONFRAG,
3390                 [24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3391                        RTE_PTYPE_L4_UDP,
3392                 /* [25] reserved */
3393                 [26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3394                        RTE_PTYPE_L4_TCP,
3395                 [27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3396                        RTE_PTYPE_L4_SCTP,
3397                 [28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3398                        RTE_PTYPE_L4_ICMP,
3399
3400                 /* IPv4 --> IPv4 */
3401                 [29] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3402                        RTE_PTYPE_TUNNEL_IP |
3403                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3404                        RTE_PTYPE_INNER_L4_FRAG,
3405                 [30] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3406                        RTE_PTYPE_TUNNEL_IP |
3407                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3408                        RTE_PTYPE_INNER_L4_NONFRAG,
3409                 [31] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3410                        RTE_PTYPE_TUNNEL_IP |
3411                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3412                        RTE_PTYPE_INNER_L4_UDP,
3413                 /* [32] reserved */
3414                 [33] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3415                        RTE_PTYPE_TUNNEL_IP |
3416                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3417                        RTE_PTYPE_INNER_L4_TCP,
3418                 [34] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3419                        RTE_PTYPE_TUNNEL_IP |
3420                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3421                        RTE_PTYPE_INNER_L4_SCTP,
3422                 [35] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3423                        RTE_PTYPE_TUNNEL_IP |
3424                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3425                        RTE_PTYPE_INNER_L4_ICMP,
3426
3427                 /* IPv4 --> IPv6 */
3428                 [36] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3429                        RTE_PTYPE_TUNNEL_IP |
3430                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3431                        RTE_PTYPE_INNER_L4_FRAG,
3432                 [37] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3433                        RTE_PTYPE_TUNNEL_IP |
3434                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3435                        RTE_PTYPE_INNER_L4_NONFRAG,
3436                 [38] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3437                        RTE_PTYPE_TUNNEL_IP |
3438                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3439                        RTE_PTYPE_INNER_L4_UDP,
3440                 /* [39] reserved */
3441                 [40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3442                        RTE_PTYPE_TUNNEL_IP |
3443                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3444                        RTE_PTYPE_INNER_L4_TCP,
3445                 [41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3446                        RTE_PTYPE_TUNNEL_IP |
3447                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3448                        RTE_PTYPE_INNER_L4_SCTP,
3449                 [42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3450                        RTE_PTYPE_TUNNEL_IP |
3451                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3452                        RTE_PTYPE_INNER_L4_ICMP,
3453
3454                 /* IPv4 --> GRE/Teredo/VXLAN */
3455                 [43] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3456                        RTE_PTYPE_TUNNEL_GRENAT,
3457
3458                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv4 */
3459                 [44] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3460                        RTE_PTYPE_TUNNEL_GRENAT |
3461                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3462                        RTE_PTYPE_INNER_L4_FRAG,
3463                 [45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3464                        RTE_PTYPE_TUNNEL_GRENAT |
3465                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3466                        RTE_PTYPE_INNER_L4_NONFRAG,
3467                 [46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3468                        RTE_PTYPE_TUNNEL_GRENAT |
3469                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3470                        RTE_PTYPE_INNER_L4_UDP,
3471                 /* [47] reserved */
3472                 [48] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3473                        RTE_PTYPE_TUNNEL_GRENAT |
3474                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3475                        RTE_PTYPE_INNER_L4_TCP,
3476                 [49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3477                        RTE_PTYPE_TUNNEL_GRENAT |
3478                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3479                        RTE_PTYPE_INNER_L4_SCTP,
3480                 [50] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3481                        RTE_PTYPE_TUNNEL_GRENAT |
3482                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3483                        RTE_PTYPE_INNER_L4_ICMP,
3484
3485                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv6 */
3486                 [51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3487                        RTE_PTYPE_TUNNEL_GRENAT |
3488                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3489                        RTE_PTYPE_INNER_L4_FRAG,
3490                 [52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3491                        RTE_PTYPE_TUNNEL_GRENAT |
3492                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3493                        RTE_PTYPE_INNER_L4_NONFRAG,
3494                 [53] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3495                        RTE_PTYPE_TUNNEL_GRENAT |
3496                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3497                        RTE_PTYPE_INNER_L4_UDP,
3498                 /* [54] reserved */
3499                 [55] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3500                        RTE_PTYPE_TUNNEL_GRENAT |
3501                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3502                        RTE_PTYPE_INNER_L4_TCP,
3503                 [56] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3504                        RTE_PTYPE_TUNNEL_GRENAT |
3505                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3506                        RTE_PTYPE_INNER_L4_SCTP,
3507                 [57] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3508                        RTE_PTYPE_TUNNEL_GRENAT |
3509                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3510                        RTE_PTYPE_INNER_L4_ICMP,
3511
3512                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC */
3513                 [58] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3514                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
3515
3516                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
3517                 [59] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3518                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3519                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3520                        RTE_PTYPE_INNER_L4_FRAG,
3521                 [60] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3522                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3523                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3524                        RTE_PTYPE_INNER_L4_NONFRAG,
3525                 [61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3526                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3527                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3528                        RTE_PTYPE_INNER_L4_UDP,
3529                 /* [62] reserved */
3530                 [63] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3531                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3532                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3533                        RTE_PTYPE_INNER_L4_TCP,
3534                 [64] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3535                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3536                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3537                        RTE_PTYPE_INNER_L4_SCTP,
3538                 [65] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3539                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3540                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3541                        RTE_PTYPE_INNER_L4_ICMP,
3542
3543                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
3544                 [66] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3545                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3546                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3547                        RTE_PTYPE_INNER_L4_FRAG,
3548                 [67] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3549                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3550                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3551                        RTE_PTYPE_INNER_L4_NONFRAG,
3552                 [68] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3553                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3554                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3555                        RTE_PTYPE_INNER_L4_UDP,
3556                 /* [69] reserved */
3557                 [70] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3558                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3559                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3560                        RTE_PTYPE_INNER_L4_TCP,
3561                 [71] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3562                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3563                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3564                        RTE_PTYPE_INNER_L4_SCTP,
3565                 [72] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3566                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3567                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3568                        RTE_PTYPE_INNER_L4_ICMP,
3569                 /* [73] - [87] reserved */
3570
3571                 /* Non tunneled IPv6 */
3572                 [88] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3573                        RTE_PTYPE_L4_FRAG,
3574                 [89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3575                        RTE_PTYPE_L4_NONFRAG,
3576                 [90] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3577                        RTE_PTYPE_L4_UDP,
3578                 /* [91] reserved */
3579                 [92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3580                        RTE_PTYPE_L4_TCP,
3581                 [93] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3582                        RTE_PTYPE_L4_SCTP,
3583                 [94] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3584                        RTE_PTYPE_L4_ICMP,
3585
3586                 /* IPv6 --> IPv4 */
3587                 [95] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3588                        RTE_PTYPE_TUNNEL_IP |
3589                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3590                        RTE_PTYPE_INNER_L4_FRAG,
3591                 [96] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3592                        RTE_PTYPE_TUNNEL_IP |
3593                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3594                        RTE_PTYPE_INNER_L4_NONFRAG,
3595                 [97] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3596                        RTE_PTYPE_TUNNEL_IP |
3597                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3598                        RTE_PTYPE_INNER_L4_UDP,
3599                 /* [98] reserved */
3600                 [99] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3601                        RTE_PTYPE_TUNNEL_IP |
3602                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3603                        RTE_PTYPE_INNER_L4_TCP,
3604                 [100] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3605                         RTE_PTYPE_TUNNEL_IP |
3606                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3607                         RTE_PTYPE_INNER_L4_SCTP,
3608                 [101] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3609                         RTE_PTYPE_TUNNEL_IP |
3610                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3611                         RTE_PTYPE_INNER_L4_ICMP,
3612
3613                 /* IPv6 --> IPv6 */
3614                 [102] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3615                         RTE_PTYPE_TUNNEL_IP |
3616                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3617                         RTE_PTYPE_INNER_L4_FRAG,
3618                 [103] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3619                         RTE_PTYPE_TUNNEL_IP |
3620                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3621                         RTE_PTYPE_INNER_L4_NONFRAG,
3622                 [104] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3623                         RTE_PTYPE_TUNNEL_IP |
3624                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3625                         RTE_PTYPE_INNER_L4_UDP,
3626                 /* [105] reserved */
3627                 [106] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3628                         RTE_PTYPE_TUNNEL_IP |
3629                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3630                         RTE_PTYPE_INNER_L4_TCP,
3631                 [107] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3632                         RTE_PTYPE_TUNNEL_IP |
3633                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3634                         RTE_PTYPE_INNER_L4_SCTP,
3635                 [108] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3636                         RTE_PTYPE_TUNNEL_IP |
3637                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3638                         RTE_PTYPE_INNER_L4_ICMP,
3639
3640                 /* IPv6 --> GRE/Teredo/VXLAN */
3641                 [109] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3642                         RTE_PTYPE_TUNNEL_GRENAT,
3643
3644                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv4 */
3645                 [110] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3646                         RTE_PTYPE_TUNNEL_GRENAT |
3647                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3648                         RTE_PTYPE_INNER_L4_FRAG,
3649                 [111] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3650                         RTE_PTYPE_TUNNEL_GRENAT |
3651                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3652                         RTE_PTYPE_INNER_L4_NONFRAG,
3653                 [112] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3654                         RTE_PTYPE_TUNNEL_GRENAT |
3655                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3656                         RTE_PTYPE_INNER_L4_UDP,
3657                 /* [113] reserved */
3658                 [114] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3659                         RTE_PTYPE_TUNNEL_GRENAT |
3660                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3661                         RTE_PTYPE_INNER_L4_TCP,
3662                 [115] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3663                         RTE_PTYPE_TUNNEL_GRENAT |
3664                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3665                         RTE_PTYPE_INNER_L4_SCTP,
3666                 [116] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3667                         RTE_PTYPE_TUNNEL_GRENAT |
3668                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3669                         RTE_PTYPE_INNER_L4_ICMP,
3670
3671                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv6 */
3672                 [117] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3673                         RTE_PTYPE_TUNNEL_GRENAT |
3674                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3675                         RTE_PTYPE_INNER_L4_FRAG,
3676                 [118] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3677                         RTE_PTYPE_TUNNEL_GRENAT |
3678                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3679                         RTE_PTYPE_INNER_L4_NONFRAG,
3680                 [119] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3681                         RTE_PTYPE_TUNNEL_GRENAT |
3682                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3683                         RTE_PTYPE_INNER_L4_UDP,
3684                 /* [120] reserved */
3685                 [121] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3686                         RTE_PTYPE_TUNNEL_GRENAT |
3687                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3688                         RTE_PTYPE_INNER_L4_TCP,
3689                 [122] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3690                         RTE_PTYPE_TUNNEL_GRENAT |
3691                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3692                         RTE_PTYPE_INNER_L4_SCTP,
3693                 [123] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3694                         RTE_PTYPE_TUNNEL_GRENAT |
3695                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3696                         RTE_PTYPE_INNER_L4_ICMP,
3697
3698                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC */
3699                 [124] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3700                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
3701
3702                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
3703                 [125] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3704                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3705                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3706                         RTE_PTYPE_INNER_L4_FRAG,
3707                 [126] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3708                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3709                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3710                         RTE_PTYPE_INNER_L4_NONFRAG,
3711                 [127] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3712                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3713                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3714                         RTE_PTYPE_INNER_L4_UDP,
3715                 /* [128] reserved */
3716                 [129] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3717                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3718                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3719                         RTE_PTYPE_INNER_L4_TCP,
3720                 [130] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3721                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3722                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3723                         RTE_PTYPE_INNER_L4_SCTP,
3724                 [131] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3725                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3726                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3727                         RTE_PTYPE_INNER_L4_ICMP,
3728
3729                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
3730                 [132] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3731                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3732                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3733                         RTE_PTYPE_INNER_L4_FRAG,
3734                 [133] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3735                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3736                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3737                         RTE_PTYPE_INNER_L4_NONFRAG,
3738                 [134] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3739                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3740                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3741                         RTE_PTYPE_INNER_L4_UDP,
3742                 /* [135] reserved */
3743                 [136] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3744                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3745                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3746                         RTE_PTYPE_INNER_L4_TCP,
3747                 [137] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3748                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3749                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3750                         RTE_PTYPE_INNER_L4_SCTP,
3751                 [138] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3752                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3753                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3754                         RTE_PTYPE_INNER_L4_ICMP,
3755                 /* [139] - [299] reserved */
3756
3757                 /* PPPoE */
3758                 [300] = RTE_PTYPE_L2_ETHER_PPPOE,
3759                 [301] = RTE_PTYPE_L2_ETHER_PPPOE,
3760
3761                 /* PPPoE --> IPv4 */
3762                 [302] = RTE_PTYPE_L2_ETHER_PPPOE |
3763                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3764                         RTE_PTYPE_L4_FRAG,
3765                 [303] = RTE_PTYPE_L2_ETHER_PPPOE |
3766                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3767                         RTE_PTYPE_L4_NONFRAG,
3768                 [304] = RTE_PTYPE_L2_ETHER_PPPOE |
3769                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3770                         RTE_PTYPE_L4_UDP,
3771                 [305] = RTE_PTYPE_L2_ETHER_PPPOE |
3772                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3773                         RTE_PTYPE_L4_TCP,
3774                 [306] = RTE_PTYPE_L2_ETHER_PPPOE |
3775                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3776                         RTE_PTYPE_L4_SCTP,
3777                 [307] = RTE_PTYPE_L2_ETHER_PPPOE |
3778                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3779                         RTE_PTYPE_L4_ICMP,
3780
3781                 /* PPPoE --> IPv6 */
3782                 [308] = RTE_PTYPE_L2_ETHER_PPPOE |
3783                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3784                         RTE_PTYPE_L4_FRAG,
3785                 [309] = RTE_PTYPE_L2_ETHER_PPPOE |
3786                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3787                         RTE_PTYPE_L4_NONFRAG,
3788                 [310] = RTE_PTYPE_L2_ETHER_PPPOE |
3789                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3790                         RTE_PTYPE_L4_UDP,
3791                 [311] = RTE_PTYPE_L2_ETHER_PPPOE |
3792                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3793                         RTE_PTYPE_L4_TCP,
3794                 [312] = RTE_PTYPE_L2_ETHER_PPPOE |
3795                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3796                         RTE_PTYPE_L4_SCTP,
3797                 [313] = RTE_PTYPE_L2_ETHER_PPPOE |
3798                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3799                         RTE_PTYPE_L4_ICMP,
3800                 /* [314] - [324] reserved */
3801
3802                 /* IPv4/IPv6 --> GTPC/GTPU */
3803                 [325] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3804                         RTE_PTYPE_TUNNEL_GTPC,
3805                 [326] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3806                         RTE_PTYPE_TUNNEL_GTPC,
3807                 [327] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3808                         RTE_PTYPE_TUNNEL_GTPC,
3809                 [328] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3810                         RTE_PTYPE_TUNNEL_GTPC,
3811                 [329] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3812                         RTE_PTYPE_TUNNEL_GTPU,
3813                 [330] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3814                         RTE_PTYPE_TUNNEL_GTPU,
3815
3816                 /* IPv4 --> GTPU --> IPv4 */
3817                 [331] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3818                         RTE_PTYPE_TUNNEL_GTPU |
3819                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3820                         RTE_PTYPE_INNER_L4_FRAG,
3821                 [332] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3822                         RTE_PTYPE_TUNNEL_GTPU |
3823                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3824                         RTE_PTYPE_INNER_L4_NONFRAG,
3825                 [333] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3826                         RTE_PTYPE_TUNNEL_GTPU |
3827                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3828                         RTE_PTYPE_INNER_L4_UDP,
3829                 [334] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3830                         RTE_PTYPE_TUNNEL_GTPU |
3831                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3832                         RTE_PTYPE_INNER_L4_TCP,
3833                 [335] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3834                         RTE_PTYPE_TUNNEL_GTPU |
3835                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3836                         RTE_PTYPE_INNER_L4_ICMP,
3837
3838                 /* IPv6 --> GTPU --> IPv4 */
3839                 [336] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3840                         RTE_PTYPE_TUNNEL_GTPU |
3841                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3842                         RTE_PTYPE_INNER_L4_FRAG,
3843                 [337] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3844                         RTE_PTYPE_TUNNEL_GTPU |
3845                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3846                         RTE_PTYPE_INNER_L4_NONFRAG,
3847                 [338] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3848                         RTE_PTYPE_TUNNEL_GTPU |
3849                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3850                         RTE_PTYPE_INNER_L4_UDP,
3851                 [339] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3852                         RTE_PTYPE_TUNNEL_GTPU |
3853                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3854                         RTE_PTYPE_INNER_L4_TCP,
3855                 [340] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3856                         RTE_PTYPE_TUNNEL_GTPU |
3857                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3858                         RTE_PTYPE_INNER_L4_ICMP,
3859
3860                 /* IPv4 --> GTPU --> IPv6 */
3861                 [341] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3862                         RTE_PTYPE_TUNNEL_GTPU |
3863                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3864                         RTE_PTYPE_INNER_L4_FRAG,
3865                 [342] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3866                         RTE_PTYPE_TUNNEL_GTPU |
3867                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3868                         RTE_PTYPE_INNER_L4_NONFRAG,
3869                 [343] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3870                         RTE_PTYPE_TUNNEL_GTPU |
3871                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3872                         RTE_PTYPE_INNER_L4_UDP,
3873                 [344] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3874                         RTE_PTYPE_TUNNEL_GTPU |
3875                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3876                         RTE_PTYPE_INNER_L4_TCP,
3877                 [345] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3878                         RTE_PTYPE_TUNNEL_GTPU |
3879                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3880                         RTE_PTYPE_INNER_L4_ICMP,
3881
3882                 /* IPv6 --> GTPU --> IPv6 */
3883                 [346] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3884                         RTE_PTYPE_TUNNEL_GTPU |
3885                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3886                         RTE_PTYPE_INNER_L4_FRAG,
3887                 [347] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3888                         RTE_PTYPE_TUNNEL_GTPU |
3889                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3890                         RTE_PTYPE_INNER_L4_NONFRAG,
3891                 [348] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3892                         RTE_PTYPE_TUNNEL_GTPU |
3893                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3894                         RTE_PTYPE_INNER_L4_UDP,
3895                 [349] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3896                         RTE_PTYPE_TUNNEL_GTPU |
3897                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3898                         RTE_PTYPE_INNER_L4_TCP,
3899                 [350] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3900                         RTE_PTYPE_TUNNEL_GTPU |
3901                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3902                         RTE_PTYPE_INNER_L4_ICMP,
3903
3904                 /* IPv4 --> UDP ECPRI */
3905                 [372] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3906                         RTE_PTYPE_L4_UDP,
3907                 [373] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3908                         RTE_PTYPE_L4_UDP,
3909                 [374] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3910                         RTE_PTYPE_L4_UDP,
3911                 [375] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3912                         RTE_PTYPE_L4_UDP,
3913                 [376] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3914                         RTE_PTYPE_L4_UDP,
3915                 [377] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3916                         RTE_PTYPE_L4_UDP,
3917                 [378] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3918                         RTE_PTYPE_L4_UDP,
3919                 [379] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3920                         RTE_PTYPE_L4_UDP,
3921                 [380] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3922                         RTE_PTYPE_L4_UDP,
3923                 [381] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3924                         RTE_PTYPE_L4_UDP,
3925
3926                 /* IPV6 --> UDP ECPRI */
3927                 [382] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3928                         RTE_PTYPE_L4_UDP,
3929                 [383] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3930                         RTE_PTYPE_L4_UDP,
3931                 [384] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3932                         RTE_PTYPE_L4_UDP,
3933                 [385] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3934                         RTE_PTYPE_L4_UDP,
3935                 [386] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3936                         RTE_PTYPE_L4_UDP,
3937                 [387] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3938                         RTE_PTYPE_L4_UDP,
3939                 [388] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3940                         RTE_PTYPE_L4_UDP,
3941                 [389] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3942                         RTE_PTYPE_L4_UDP,
3943                 [390] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3944                         RTE_PTYPE_L4_UDP,
3945                 [391] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3946                         RTE_PTYPE_L4_UDP,
3947                 /* All others reserved */
3948         };
3949
3950         return ptype_tbl[ptype];
3951 }
3952
3953 void __rte_cold
3954 iavf_set_default_ptype_table(struct rte_eth_dev *dev)
3955 {
3956         struct iavf_adapter *ad =
3957                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3958         int i;
3959
3960         for (i = 0; i < IAVF_MAX_PKT_TYPE; i++)
3961                 ad->ptype_tbl[i] = iavf_get_default_ptype(i);
3962 }