1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2017 Intel Corporation
13 #include <sys/queue.h>
15 #include <rte_string_fns.h>
16 #include <rte_memzone.h>
18 #include <rte_malloc.h>
19 #include <rte_ether.h>
20 #include <rte_ethdev_driver.h>
29 #include "iavf_rxtx.h"
30 #include "rte_pmd_iavf.h"
32 /* Offset of mbuf dynamic field for protocol extraction's metadata */
33 int rte_pmd_ifd_dynfield_proto_xtr_metadata_offs = -1;
35 /* Mask of mbuf dynamic flags for protocol extraction's type */
36 uint64_t rte_pmd_ifd_dynflag_proto_xtr_vlan_mask;
37 uint64_t rte_pmd_ifd_dynflag_proto_xtr_ipv4_mask;
38 uint64_t rte_pmd_ifd_dynflag_proto_xtr_ipv6_mask;
39 uint64_t rte_pmd_ifd_dynflag_proto_xtr_ipv6_flow_mask;
40 uint64_t rte_pmd_ifd_dynflag_proto_xtr_tcp_mask;
41 uint64_t rte_pmd_ifd_dynflag_proto_xtr_ip_offset_mask;
44 iavf_proto_xtr_type_to_rxdid(uint8_t flex_type)
46 static uint8_t rxdid_map[] = {
47 [IAVF_PROTO_XTR_NONE] = IAVF_RXDID_COMMS_OVS_1,
48 [IAVF_PROTO_XTR_VLAN] = IAVF_RXDID_COMMS_AUX_VLAN,
49 [IAVF_PROTO_XTR_IPV4] = IAVF_RXDID_COMMS_AUX_IPV4,
50 [IAVF_PROTO_XTR_IPV6] = IAVF_RXDID_COMMS_AUX_IPV6,
51 [IAVF_PROTO_XTR_IPV6_FLOW] = IAVF_RXDID_COMMS_AUX_IPV6_FLOW,
52 [IAVF_PROTO_XTR_TCP] = IAVF_RXDID_COMMS_AUX_TCP,
53 [IAVF_PROTO_XTR_IP_OFFSET] = IAVF_RXDID_COMMS_AUX_IP_OFFSET,
56 return flex_type < RTE_DIM(rxdid_map) ?
57 rxdid_map[flex_type] : IAVF_RXDID_COMMS_OVS_1;
61 check_rx_thresh(uint16_t nb_desc, uint16_t thresh)
63 /* The following constraints must be satisfied:
64 * thresh < rxq->nb_rx_desc
66 if (thresh >= nb_desc) {
67 PMD_INIT_LOG(ERR, "rx_free_thresh (%u) must be less than %u",
75 check_tx_thresh(uint16_t nb_desc, uint16_t tx_rs_thresh,
76 uint16_t tx_free_thresh)
78 /* TX descriptors will have their RS bit set after tx_rs_thresh
79 * descriptors have been used. The TX descriptor ring will be cleaned
80 * after tx_free_thresh descriptors are used or if the number of
81 * descriptors required to transmit a packet is greater than the
82 * number of free TX descriptors.
84 * The following constraints must be satisfied:
85 * - tx_rs_thresh must be less than the size of the ring minus 2.
86 * - tx_free_thresh must be less than the size of the ring minus 3.
87 * - tx_rs_thresh must be less than or equal to tx_free_thresh.
88 * - tx_rs_thresh must be a divisor of the ring size.
90 * One descriptor in the TX ring is used as a sentinel to avoid a H/W
91 * race condition, hence the maximum threshold constraints. When set
92 * to zero use default values.
94 if (tx_rs_thresh >= (nb_desc - 2)) {
95 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be less than the "
96 "number of TX descriptors (%u) minus 2",
97 tx_rs_thresh, nb_desc);
100 if (tx_free_thresh >= (nb_desc - 3)) {
101 PMD_INIT_LOG(ERR, "tx_free_thresh (%u) must be less than the "
102 "number of TX descriptors (%u) minus 3.",
103 tx_free_thresh, nb_desc);
106 if (tx_rs_thresh > tx_free_thresh) {
107 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be less than or "
108 "equal to tx_free_thresh (%u).",
109 tx_rs_thresh, tx_free_thresh);
112 if ((nb_desc % tx_rs_thresh) != 0) {
113 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be a divisor of the "
114 "number of TX descriptors (%u).",
115 tx_rs_thresh, nb_desc);
123 check_rx_vec_allow(struct iavf_rx_queue *rxq)
125 if (rxq->rx_free_thresh >= IAVF_VPMD_RX_MAX_BURST &&
126 rxq->nb_rx_desc % rxq->rx_free_thresh == 0) {
127 PMD_INIT_LOG(DEBUG, "Vector Rx can be enabled on this rxq.");
131 PMD_INIT_LOG(DEBUG, "Vector Rx cannot be enabled on this rxq.");
136 check_tx_vec_allow(struct iavf_tx_queue *txq)
138 if (!(txq->offloads & IAVF_NO_VECTOR_FLAGS) &&
139 txq->rs_thresh >= IAVF_VPMD_TX_MAX_BURST &&
140 txq->rs_thresh <= IAVF_VPMD_TX_MAX_FREE_BUF) {
141 PMD_INIT_LOG(DEBUG, "Vector tx can be enabled on this txq.");
144 PMD_INIT_LOG(DEBUG, "Vector Tx cannot be enabled on this txq.");
149 check_rx_bulk_allow(struct iavf_rx_queue *rxq)
153 if (!(rxq->rx_free_thresh >= IAVF_RX_MAX_BURST)) {
154 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
155 "rxq->rx_free_thresh=%d, "
156 "IAVF_RX_MAX_BURST=%d",
157 rxq->rx_free_thresh, IAVF_RX_MAX_BURST);
159 } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
160 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
161 "rxq->nb_rx_desc=%d, "
162 "rxq->rx_free_thresh=%d",
163 rxq->nb_rx_desc, rxq->rx_free_thresh);
170 reset_rx_queue(struct iavf_rx_queue *rxq)
178 len = rxq->nb_rx_desc + IAVF_RX_MAX_BURST;
180 for (i = 0; i < len * sizeof(union iavf_rx_desc); i++)
181 ((volatile char *)rxq->rx_ring)[i] = 0;
183 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
185 for (i = 0; i < IAVF_RX_MAX_BURST; i++)
186 rxq->sw_ring[rxq->nb_rx_desc + i] = &rxq->fake_mbuf;
189 rxq->rx_nb_avail = 0;
190 rxq->rx_next_avail = 0;
191 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
195 rxq->pkt_first_seg = NULL;
196 rxq->pkt_last_seg = NULL;
198 rxq->rxrearm_start = 0;
202 reset_tx_queue(struct iavf_tx_queue *txq)
204 struct iavf_tx_entry *txe;
209 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
214 size = sizeof(struct iavf_tx_desc) * txq->nb_tx_desc;
215 for (i = 0; i < size; i++)
216 ((volatile char *)txq->tx_ring)[i] = 0;
218 prev = (uint16_t)(txq->nb_tx_desc - 1);
219 for (i = 0; i < txq->nb_tx_desc; i++) {
220 txq->tx_ring[i].cmd_type_offset_bsz =
221 rte_cpu_to_le_64(IAVF_TX_DESC_DTYPE_DESC_DONE);
224 txe[prev].next_id = i;
231 txq->last_desc_cleaned = txq->nb_tx_desc - 1;
232 txq->nb_free = txq->nb_tx_desc - 1;
234 txq->next_dd = txq->rs_thresh - 1;
235 txq->next_rs = txq->rs_thresh - 1;
239 alloc_rxq_mbufs(struct iavf_rx_queue *rxq)
241 volatile union iavf_rx_desc *rxd;
242 struct rte_mbuf *mbuf = NULL;
246 for (i = 0; i < rxq->nb_rx_desc; i++) {
247 mbuf = rte_mbuf_raw_alloc(rxq->mp);
248 if (unlikely(!mbuf)) {
249 PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
253 rte_mbuf_refcnt_set(mbuf, 1);
255 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
257 mbuf->port = rxq->port_id;
260 rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
262 rxd = &rxq->rx_ring[i];
263 rxd->read.pkt_addr = dma_addr;
264 rxd->read.hdr_addr = 0;
265 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
270 rxq->sw_ring[i] = mbuf;
277 release_rxq_mbufs(struct iavf_rx_queue *rxq)
284 for (i = 0; i < rxq->nb_rx_desc; i++) {
285 if (rxq->sw_ring[i]) {
286 rte_pktmbuf_free_seg(rxq->sw_ring[i]);
287 rxq->sw_ring[i] = NULL;
292 if (rxq->rx_nb_avail == 0)
294 for (i = 0; i < rxq->rx_nb_avail; i++) {
295 struct rte_mbuf *mbuf;
297 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
298 rte_pktmbuf_free_seg(mbuf);
300 rxq->rx_nb_avail = 0;
304 release_txq_mbufs(struct iavf_tx_queue *txq)
308 if (!txq || !txq->sw_ring) {
309 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
313 for (i = 0; i < txq->nb_tx_desc; i++) {
314 if (txq->sw_ring[i].mbuf) {
315 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
316 txq->sw_ring[i].mbuf = NULL;
321 static const struct iavf_rxq_ops def_rxq_ops = {
322 .release_mbufs = release_rxq_mbufs,
325 static const struct iavf_txq_ops def_txq_ops = {
326 .release_mbufs = release_txq_mbufs,
330 iavf_rxd_to_pkt_fields_by_comms_ovs(__rte_unused struct iavf_rx_queue *rxq,
332 volatile union iavf_rx_flex_desc *rxdp)
334 volatile struct iavf_32b_rx_flex_desc_comms_ovs *desc =
335 (volatile struct iavf_32b_rx_flex_desc_comms_ovs *)rxdp;
336 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
340 if (desc->flow_id != 0xFFFFFFFF) {
341 mb->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
342 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
345 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
346 stat_err = rte_le_to_cpu_16(desc->status_error0);
347 if (likely(stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
348 mb->ol_flags |= PKT_RX_RSS_HASH;
349 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
355 iavf_rxd_to_pkt_fields_by_comms_aux_v1(struct iavf_rx_queue *rxq,
357 volatile union iavf_rx_flex_desc *rxdp)
359 volatile struct iavf_32b_rx_flex_desc_comms *desc =
360 (volatile struct iavf_32b_rx_flex_desc_comms *)rxdp;
363 stat_err = rte_le_to_cpu_16(desc->status_error0);
364 if (likely(stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
365 mb->ol_flags |= PKT_RX_RSS_HASH;
366 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
369 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
370 if (desc->flow_id != 0xFFFFFFFF) {
371 mb->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
372 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
375 if (rxq->xtr_ol_flag) {
376 uint32_t metadata = 0;
378 stat_err = rte_le_to_cpu_16(desc->status_error1);
380 if (stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS1_XTRMD4_VALID_S))
381 metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux0);
383 if (stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS1_XTRMD5_VALID_S))
385 rte_le_to_cpu_16(desc->flex_ts.flex.aux1) << 16;
388 mb->ol_flags |= rxq->xtr_ol_flag;
390 *RTE_PMD_IFD_DYNF_PROTO_XTR_METADATA(mb) = metadata;
397 iavf_rxd_to_pkt_fields_by_comms_aux_v2(struct iavf_rx_queue *rxq,
399 volatile union iavf_rx_flex_desc *rxdp)
401 volatile struct iavf_32b_rx_flex_desc_comms *desc =
402 (volatile struct iavf_32b_rx_flex_desc_comms *)rxdp;
405 stat_err = rte_le_to_cpu_16(desc->status_error0);
406 if (likely(stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
407 mb->ol_flags |= PKT_RX_RSS_HASH;
408 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
411 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
412 if (desc->flow_id != 0xFFFFFFFF) {
413 mb->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
414 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
417 if (rxq->xtr_ol_flag) {
418 uint32_t metadata = 0;
420 if (desc->flex_ts.flex.aux0 != 0xFFFF)
421 metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux0);
422 else if (desc->flex_ts.flex.aux1 != 0xFFFF)
423 metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux1);
426 mb->ol_flags |= rxq->xtr_ol_flag;
428 *RTE_PMD_IFD_DYNF_PROTO_XTR_METADATA(mb) = metadata;
435 iavf_select_rxd_to_pkt_fields_handler(struct iavf_rx_queue *rxq, uint32_t rxdid)
438 case IAVF_RXDID_COMMS_AUX_VLAN:
439 rxq->xtr_ol_flag = rte_pmd_ifd_dynflag_proto_xtr_vlan_mask;
440 rxq->rxd_to_pkt_fields =
441 iavf_rxd_to_pkt_fields_by_comms_aux_v1;
443 case IAVF_RXDID_COMMS_AUX_IPV4:
444 rxq->xtr_ol_flag = rte_pmd_ifd_dynflag_proto_xtr_ipv4_mask;
445 rxq->rxd_to_pkt_fields =
446 iavf_rxd_to_pkt_fields_by_comms_aux_v1;
448 case IAVF_RXDID_COMMS_AUX_IPV6:
449 rxq->xtr_ol_flag = rte_pmd_ifd_dynflag_proto_xtr_ipv6_mask;
450 rxq->rxd_to_pkt_fields =
451 iavf_rxd_to_pkt_fields_by_comms_aux_v1;
453 case IAVF_RXDID_COMMS_AUX_IPV6_FLOW:
455 rte_pmd_ifd_dynflag_proto_xtr_ipv6_flow_mask;
456 rxq->rxd_to_pkt_fields =
457 iavf_rxd_to_pkt_fields_by_comms_aux_v1;
459 case IAVF_RXDID_COMMS_AUX_TCP:
460 rxq->xtr_ol_flag = rte_pmd_ifd_dynflag_proto_xtr_tcp_mask;
461 rxq->rxd_to_pkt_fields =
462 iavf_rxd_to_pkt_fields_by_comms_aux_v1;
464 case IAVF_RXDID_COMMS_AUX_IP_OFFSET:
466 rte_pmd_ifd_dynflag_proto_xtr_ip_offset_mask;
467 rxq->rxd_to_pkt_fields =
468 iavf_rxd_to_pkt_fields_by_comms_aux_v2;
470 case IAVF_RXDID_COMMS_OVS_1:
471 rxq->rxd_to_pkt_fields = iavf_rxd_to_pkt_fields_by_comms_ovs;
474 /* update this according to the RXDID for FLEX_DESC_NONE */
475 rxq->rxd_to_pkt_fields = iavf_rxd_to_pkt_fields_by_comms_ovs;
479 if (!rte_pmd_ifd_dynf_proto_xtr_metadata_avail())
480 rxq->xtr_ol_flag = 0;
484 iavf_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
485 uint16_t nb_desc, unsigned int socket_id,
486 const struct rte_eth_rxconf *rx_conf,
487 struct rte_mempool *mp)
489 struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
490 struct iavf_adapter *ad =
491 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
492 struct iavf_info *vf =
493 IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
494 struct iavf_vsi *vsi = &vf->vsi;
495 struct iavf_rx_queue *rxq;
496 const struct rte_memzone *mz;
500 uint16_t rx_free_thresh;
502 PMD_INIT_FUNC_TRACE();
504 if (nb_desc % IAVF_ALIGN_RING_DESC != 0 ||
505 nb_desc > IAVF_MAX_RING_DESC ||
506 nb_desc < IAVF_MIN_RING_DESC) {
507 PMD_INIT_LOG(ERR, "Number (%u) of receive descriptors is "
512 /* Check free threshold */
513 rx_free_thresh = (rx_conf->rx_free_thresh == 0) ?
514 IAVF_DEFAULT_RX_FREE_THRESH :
515 rx_conf->rx_free_thresh;
516 if (check_rx_thresh(nb_desc, rx_free_thresh) != 0)
519 /* Free memory if needed */
520 if (dev->data->rx_queues[queue_idx]) {
521 iavf_dev_rx_queue_release(dev->data->rx_queues[queue_idx]);
522 dev->data->rx_queues[queue_idx] = NULL;
525 /* Allocate the rx queue data structure */
526 rxq = rte_zmalloc_socket("iavf rxq",
527 sizeof(struct iavf_rx_queue),
531 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
532 "rx queue data structure");
536 if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC) {
537 proto_xtr = vf->proto_xtr ? vf->proto_xtr[queue_idx] :
539 rxq->rxdid = iavf_proto_xtr_type_to_rxdid(proto_xtr);
540 rxq->proto_xtr = proto_xtr;
542 rxq->rxdid = IAVF_RXDID_LEGACY_1;
543 rxq->proto_xtr = IAVF_PROTO_XTR_NONE;
546 iavf_select_rxd_to_pkt_fields_handler(rxq, rxq->rxdid);
549 rxq->nb_rx_desc = nb_desc;
550 rxq->rx_free_thresh = rx_free_thresh;
551 rxq->queue_id = queue_idx;
552 rxq->port_id = dev->data->port_id;
553 rxq->rx_deferred_start = rx_conf->rx_deferred_start;
557 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
558 rxq->crc_len = RTE_ETHER_CRC_LEN;
562 len = rte_pktmbuf_data_room_size(rxq->mp) - RTE_PKTMBUF_HEADROOM;
563 rxq->rx_buf_len = RTE_ALIGN(len, (1 << IAVF_RXQ_CTX_DBUFF_SHIFT));
565 /* Allocate the software ring. */
566 len = nb_desc + IAVF_RX_MAX_BURST;
568 rte_zmalloc_socket("iavf rx sw ring",
569 sizeof(struct rte_mbuf *) * len,
573 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW ring");
578 /* Allocate the maximun number of RX ring hardware descriptor with
579 * a liitle more to support bulk allocate.
581 len = IAVF_MAX_RING_DESC + IAVF_RX_MAX_BURST;
582 ring_size = RTE_ALIGN(len * sizeof(union iavf_rx_desc),
584 mz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
585 ring_size, IAVF_RING_BASE_ALIGN,
588 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for RX");
589 rte_free(rxq->sw_ring);
593 /* Zero all the descriptors in the ring. */
594 memset(mz->addr, 0, ring_size);
595 rxq->rx_ring_phys_addr = mz->iova;
596 rxq->rx_ring = (union iavf_rx_desc *)mz->addr;
601 dev->data->rx_queues[queue_idx] = rxq;
602 rxq->qrx_tail = hw->hw_addr + IAVF_QRX_TAIL1(rxq->queue_id);
603 rxq->ops = &def_rxq_ops;
605 if (check_rx_bulk_allow(rxq) == true) {
606 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
607 "satisfied. Rx Burst Bulk Alloc function will be "
608 "used on port=%d, queue=%d.",
609 rxq->port_id, rxq->queue_id);
611 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
612 "not satisfied, Scattered Rx is requested "
613 "on port=%d, queue=%d.",
614 rxq->port_id, rxq->queue_id);
615 ad->rx_bulk_alloc_allowed = false;
618 if (check_rx_vec_allow(rxq) == false)
619 ad->rx_vec_allowed = false;
625 iavf_dev_tx_queue_setup(struct rte_eth_dev *dev,
628 unsigned int socket_id,
629 const struct rte_eth_txconf *tx_conf)
631 struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
632 struct iavf_tx_queue *txq;
633 const struct rte_memzone *mz;
635 uint16_t tx_rs_thresh, tx_free_thresh;
638 PMD_INIT_FUNC_TRACE();
640 offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
642 if (nb_desc % IAVF_ALIGN_RING_DESC != 0 ||
643 nb_desc > IAVF_MAX_RING_DESC ||
644 nb_desc < IAVF_MIN_RING_DESC) {
645 PMD_INIT_LOG(ERR, "Number (%u) of transmit descriptors is "
650 tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
651 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
652 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
653 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
654 check_tx_thresh(nb_desc, tx_rs_thresh, tx_rs_thresh);
656 /* Free memory if needed. */
657 if (dev->data->tx_queues[queue_idx]) {
658 iavf_dev_tx_queue_release(dev->data->tx_queues[queue_idx]);
659 dev->data->tx_queues[queue_idx] = NULL;
662 /* Allocate the TX queue data structure. */
663 txq = rte_zmalloc_socket("iavf txq",
664 sizeof(struct iavf_tx_queue),
668 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
669 "tx queue structure");
673 txq->nb_tx_desc = nb_desc;
674 txq->rs_thresh = tx_rs_thresh;
675 txq->free_thresh = tx_free_thresh;
676 txq->queue_id = queue_idx;
677 txq->port_id = dev->data->port_id;
678 txq->offloads = offloads;
679 txq->tx_deferred_start = tx_conf->tx_deferred_start;
681 /* Allocate software ring */
683 rte_zmalloc_socket("iavf tx sw ring",
684 sizeof(struct iavf_tx_entry) * nb_desc,
688 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW TX ring");
693 /* Allocate TX hardware ring descriptors. */
694 ring_size = sizeof(struct iavf_tx_desc) * IAVF_MAX_RING_DESC;
695 ring_size = RTE_ALIGN(ring_size, IAVF_DMA_MEM_ALIGN);
696 mz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
697 ring_size, IAVF_RING_BASE_ALIGN,
700 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for TX");
701 rte_free(txq->sw_ring);
705 txq->tx_ring_phys_addr = mz->iova;
706 txq->tx_ring = (struct iavf_tx_desc *)mz->addr;
711 dev->data->tx_queues[queue_idx] = txq;
712 txq->qtx_tail = hw->hw_addr + IAVF_QTX_TAIL1(queue_idx);
713 txq->ops = &def_txq_ops;
715 if (check_tx_vec_allow(txq) == false) {
716 struct iavf_adapter *ad =
717 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
718 ad->tx_vec_allowed = false;
725 iavf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
727 struct iavf_adapter *adapter =
728 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
729 struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
730 struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
731 struct iavf_rx_queue *rxq;
734 PMD_DRV_FUNC_TRACE();
736 if (rx_queue_id >= dev->data->nb_rx_queues)
739 rxq = dev->data->rx_queues[rx_queue_id];
741 err = alloc_rxq_mbufs(rxq);
743 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
749 /* Init the RX tail register. */
750 IAVF_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
751 IAVF_WRITE_FLUSH(hw);
753 /* Ready to switch the queue on */
755 err = iavf_switch_queue(adapter, rx_queue_id, true, true);
757 err = iavf_switch_queue_lv(adapter, rx_queue_id, true, true);
760 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
763 dev->data->rx_queue_state[rx_queue_id] =
764 RTE_ETH_QUEUE_STATE_STARTED;
770 iavf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
772 struct iavf_adapter *adapter =
773 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
774 struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
775 struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
776 struct iavf_tx_queue *txq;
779 PMD_DRV_FUNC_TRACE();
781 if (tx_queue_id >= dev->data->nb_tx_queues)
784 txq = dev->data->tx_queues[tx_queue_id];
786 /* Init the RX tail register. */
787 IAVF_PCI_REG_WRITE(txq->qtx_tail, 0);
788 IAVF_WRITE_FLUSH(hw);
790 /* Ready to switch the queue on */
792 err = iavf_switch_queue(adapter, tx_queue_id, false, true);
794 err = iavf_switch_queue_lv(adapter, tx_queue_id, false, true);
797 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
800 dev->data->tx_queue_state[tx_queue_id] =
801 RTE_ETH_QUEUE_STATE_STARTED;
807 iavf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
809 struct iavf_adapter *adapter =
810 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
811 struct iavf_rx_queue *rxq;
814 PMD_DRV_FUNC_TRACE();
816 if (rx_queue_id >= dev->data->nb_rx_queues)
819 err = iavf_switch_queue(adapter, rx_queue_id, true, false);
821 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
826 rxq = dev->data->rx_queues[rx_queue_id];
827 rxq->ops->release_mbufs(rxq);
829 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
835 iavf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
837 struct iavf_adapter *adapter =
838 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
839 struct iavf_tx_queue *txq;
842 PMD_DRV_FUNC_TRACE();
844 if (tx_queue_id >= dev->data->nb_tx_queues)
847 err = iavf_switch_queue(adapter, tx_queue_id, false, false);
849 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u off",
854 txq = dev->data->tx_queues[tx_queue_id];
855 txq->ops->release_mbufs(txq);
857 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
863 iavf_dev_rx_queue_release(void *rxq)
865 struct iavf_rx_queue *q = (struct iavf_rx_queue *)rxq;
870 q->ops->release_mbufs(q);
871 rte_free(q->sw_ring);
872 rte_memzone_free(q->mz);
877 iavf_dev_tx_queue_release(void *txq)
879 struct iavf_tx_queue *q = (struct iavf_tx_queue *)txq;
884 q->ops->release_mbufs(q);
885 rte_free(q->sw_ring);
886 rte_memzone_free(q->mz);
891 iavf_stop_queues(struct rte_eth_dev *dev)
893 struct iavf_adapter *adapter =
894 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
895 struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
896 struct iavf_rx_queue *rxq;
897 struct iavf_tx_queue *txq;
900 /* Stop All queues */
901 if (!vf->lv_enabled) {
902 ret = iavf_disable_queues(adapter);
904 PMD_DRV_LOG(WARNING, "Fail to stop queues");
906 ret = iavf_disable_queues_lv(adapter);
908 PMD_DRV_LOG(WARNING, "Fail to stop queues for large VF");
912 PMD_DRV_LOG(WARNING, "Fail to stop queues");
914 for (i = 0; i < dev->data->nb_tx_queues; i++) {
915 txq = dev->data->tx_queues[i];
918 txq->ops->release_mbufs(txq);
920 dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED;
922 for (i = 0; i < dev->data->nb_rx_queues; i++) {
923 rxq = dev->data->rx_queues[i];
926 rxq->ops->release_mbufs(rxq);
928 dev->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED;
932 #define IAVF_RX_FLEX_ERR0_BITS \
933 ((1 << IAVF_RX_FLEX_DESC_STATUS0_HBO_S) | \
934 (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_IPE_S) | \
935 (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_L4E_S) | \
936 (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S) | \
937 (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S) | \
938 (1 << IAVF_RX_FLEX_DESC_STATUS0_RXE_S))
941 iavf_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union iavf_rx_desc *rxdp)
943 if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
944 (1 << IAVF_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
945 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
947 rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
954 iavf_flex_rxd_to_vlan_tci(struct rte_mbuf *mb,
955 volatile union iavf_rx_flex_desc *rxdp)
957 if (rte_le_to_cpu_64(rxdp->wb.status_error0) &
958 (1 << IAVF_RX_FLEX_DESC_STATUS0_L2TAG1P_S)) {
959 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
961 rte_le_to_cpu_16(rxdp->wb.l2tag1);
966 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
967 if (rte_le_to_cpu_16(rxdp->wb.status_error1) &
968 (1 << IAVF_RX_FLEX_DESC_STATUS1_L2TAG2P_S)) {
969 mb->ol_flags |= PKT_RX_QINQ_STRIPPED | PKT_RX_QINQ |
970 PKT_RX_VLAN_STRIPPED | PKT_RX_VLAN;
971 mb->vlan_tci_outer = mb->vlan_tci;
972 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.l2tag2_2nd);
973 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
974 rte_le_to_cpu_16(rxdp->wb.l2tag2_1st),
975 rte_le_to_cpu_16(rxdp->wb.l2tag2_2nd));
977 mb->vlan_tci_outer = 0;
982 /* Translate the rx descriptor status and error fields to pkt flags */
983 static inline uint64_t
984 iavf_rxd_to_pkt_flags(uint64_t qword)
987 uint64_t error_bits = (qword >> IAVF_RXD_QW1_ERROR_SHIFT);
989 #define IAVF_RX_ERR_BITS 0x3f
991 /* Check if RSS_HASH */
992 flags = (((qword >> IAVF_RX_DESC_STATUS_FLTSTAT_SHIFT) &
993 IAVF_RX_DESC_FLTSTAT_RSS_HASH) ==
994 IAVF_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;
996 /* Check if FDIR Match */
997 flags |= (qword & (1 << IAVF_RX_DESC_STATUS_FLM_SHIFT) ?
1000 if (likely((error_bits & IAVF_RX_ERR_BITS) == 0)) {
1001 flags |= (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD);
1005 if (unlikely(error_bits & (1 << IAVF_RX_DESC_ERROR_IPE_SHIFT)))
1006 flags |= PKT_RX_IP_CKSUM_BAD;
1008 flags |= PKT_RX_IP_CKSUM_GOOD;
1010 if (unlikely(error_bits & (1 << IAVF_RX_DESC_ERROR_L4E_SHIFT)))
1011 flags |= PKT_RX_L4_CKSUM_BAD;
1013 flags |= PKT_RX_L4_CKSUM_GOOD;
1015 /* TODO: Oversize error bit is not processed here */
1020 static inline uint64_t
1021 iavf_rxd_build_fdir(volatile union iavf_rx_desc *rxdp, struct rte_mbuf *mb)
1024 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
1027 flexbh = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
1028 IAVF_RX_DESC_EXT_STATUS_FLEXBH_SHIFT) &
1029 IAVF_RX_DESC_EXT_STATUS_FLEXBH_MASK;
1031 if (flexbh == IAVF_RX_DESC_EXT_STATUS_FLEXBH_FD_ID) {
1033 rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.fd_id);
1034 flags |= PKT_RX_FDIR_ID;
1038 rte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.fd_id);
1039 flags |= PKT_RX_FDIR_ID;
1044 #define IAVF_RX_FLEX_ERR0_BITS \
1045 ((1 << IAVF_RX_FLEX_DESC_STATUS0_HBO_S) | \
1046 (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_IPE_S) | \
1047 (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_L4E_S) | \
1048 (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S) | \
1049 (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S) | \
1050 (1 << IAVF_RX_FLEX_DESC_STATUS0_RXE_S))
1052 /* Rx L3/L4 checksum */
1053 static inline uint64_t
1054 iavf_flex_rxd_error_to_pkt_flags(uint16_t stat_err0)
1058 /* check if HW has decoded the packet and checksum */
1059 if (unlikely(!(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_L3L4P_S))))
1062 if (likely(!(stat_err0 & IAVF_RX_FLEX_ERR0_BITS))) {
1063 flags |= (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD);
1067 if (unlikely(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_IPE_S)))
1068 flags |= PKT_RX_IP_CKSUM_BAD;
1070 flags |= PKT_RX_IP_CKSUM_GOOD;
1072 if (unlikely(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_L4E_S)))
1073 flags |= PKT_RX_L4_CKSUM_BAD;
1075 flags |= PKT_RX_L4_CKSUM_GOOD;
1077 if (unlikely(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S)))
1078 flags |= PKT_RX_EIP_CKSUM_BAD;
1083 /* If the number of free RX descriptors is greater than the RX free
1084 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1085 * register. Update the RDT with the value of the last processed RX
1086 * descriptor minus 1, to guarantee that the RDT register is never
1087 * equal to the RDH register, which creates a "full" ring situation
1088 * from the hardware point of view.
1091 iavf_update_rx_tail(struct iavf_rx_queue *rxq, uint16_t nb_hold, uint16_t rx_id)
1093 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1095 if (nb_hold > rxq->rx_free_thresh) {
1097 "port_id=%u queue_id=%u rx_tail=%u nb_hold=%u",
1098 rxq->port_id, rxq->queue_id, rx_id, nb_hold);
1099 rx_id = (uint16_t)((rx_id == 0) ?
1100 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1101 IAVF_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
1104 rxq->nb_rx_hold = nb_hold;
1107 /* implement recv_pkts */
1109 iavf_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1111 volatile union iavf_rx_desc *rx_ring;
1112 volatile union iavf_rx_desc *rxdp;
1113 struct iavf_rx_queue *rxq;
1114 union iavf_rx_desc rxd;
1115 struct rte_mbuf *rxe;
1116 struct rte_eth_dev *dev;
1117 struct rte_mbuf *rxm;
1118 struct rte_mbuf *nmb;
1122 uint16_t rx_packet_len;
1123 uint16_t rx_id, nb_hold;
1126 const uint32_t *ptype_tbl;
1131 rx_id = rxq->rx_tail;
1132 rx_ring = rxq->rx_ring;
1133 ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1135 while (nb_rx < nb_pkts) {
1136 rxdp = &rx_ring[rx_id];
1137 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1138 rx_status = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
1139 IAVF_RXD_QW1_STATUS_SHIFT;
1141 /* Check the DD bit first */
1142 if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)))
1144 IAVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
1146 nmb = rte_mbuf_raw_alloc(rxq->mp);
1147 if (unlikely(!nmb)) {
1148 dev = &rte_eth_devices[rxq->port_id];
1149 dev->data->rx_mbuf_alloc_failed++;
1150 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1151 "queue_id=%u", rxq->port_id, rxq->queue_id);
1157 rxe = rxq->sw_ring[rx_id];
1159 if (unlikely(rx_id == rxq->nb_rx_desc))
1162 /* Prefetch next mbuf */
1163 rte_prefetch0(rxq->sw_ring[rx_id]);
1165 /* When next RX descriptor is on a cache line boundary,
1166 * prefetch the next 4 RX descriptors and next 8 pointers
1169 if ((rx_id & 0x3) == 0) {
1170 rte_prefetch0(&rx_ring[rx_id]);
1171 rte_prefetch0(rxq->sw_ring[rx_id]);
1175 rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1176 rxdp->read.hdr_addr = 0;
1177 rxdp->read.pkt_addr = dma_addr;
1179 rx_packet_len = ((qword1 & IAVF_RXD_QW1_LENGTH_PBUF_MASK) >>
1180 IAVF_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
1182 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1183 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
1186 rxm->pkt_len = rx_packet_len;
1187 rxm->data_len = rx_packet_len;
1188 rxm->port = rxq->port_id;
1190 iavf_rxd_to_vlan_tci(rxm, &rxd);
1191 pkt_flags = iavf_rxd_to_pkt_flags(qword1);
1193 ptype_tbl[(uint8_t)((qword1 &
1194 IAVF_RXD_QW1_PTYPE_MASK) >> IAVF_RXD_QW1_PTYPE_SHIFT)];
1196 if (pkt_flags & PKT_RX_RSS_HASH)
1198 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1200 if (pkt_flags & PKT_RX_FDIR)
1201 pkt_flags |= iavf_rxd_build_fdir(&rxd, rxm);
1203 rxm->ol_flags |= pkt_flags;
1205 rx_pkts[nb_rx++] = rxm;
1207 rxq->rx_tail = rx_id;
1209 iavf_update_rx_tail(rxq, nb_hold, rx_id);
1214 /* implement recv_pkts for flexible Rx descriptor */
1216 iavf_recv_pkts_flex_rxd(void *rx_queue,
1217 struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1219 volatile union iavf_rx_desc *rx_ring;
1220 volatile union iavf_rx_flex_desc *rxdp;
1221 struct iavf_rx_queue *rxq;
1222 union iavf_rx_flex_desc rxd;
1223 struct rte_mbuf *rxe;
1224 struct rte_eth_dev *dev;
1225 struct rte_mbuf *rxm;
1226 struct rte_mbuf *nmb;
1228 uint16_t rx_stat_err0;
1229 uint16_t rx_packet_len;
1230 uint16_t rx_id, nb_hold;
1233 const uint32_t *ptype_tbl;
1238 rx_id = rxq->rx_tail;
1239 rx_ring = rxq->rx_ring;
1240 ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1242 while (nb_rx < nb_pkts) {
1243 rxdp = (volatile union iavf_rx_flex_desc *)&rx_ring[rx_id];
1244 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1246 /* Check the DD bit first */
1247 if (!(rx_stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S)))
1249 IAVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
1251 nmb = rte_mbuf_raw_alloc(rxq->mp);
1252 if (unlikely(!nmb)) {
1253 dev = &rte_eth_devices[rxq->port_id];
1254 dev->data->rx_mbuf_alloc_failed++;
1255 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1256 "queue_id=%u", rxq->port_id, rxq->queue_id);
1262 rxe = rxq->sw_ring[rx_id];
1264 if (unlikely(rx_id == rxq->nb_rx_desc))
1267 /* Prefetch next mbuf */
1268 rte_prefetch0(rxq->sw_ring[rx_id]);
1270 /* When next RX descriptor is on a cache line boundary,
1271 * prefetch the next 4 RX descriptors and next 8 pointers
1274 if ((rx_id & 0x3) == 0) {
1275 rte_prefetch0(&rx_ring[rx_id]);
1276 rte_prefetch0(rxq->sw_ring[rx_id]);
1280 rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1281 rxdp->read.hdr_addr = 0;
1282 rxdp->read.pkt_addr = dma_addr;
1284 rx_packet_len = (rte_le_to_cpu_16(rxd.wb.pkt_len) &
1285 IAVF_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
1287 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1288 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
1291 rxm->pkt_len = rx_packet_len;
1292 rxm->data_len = rx_packet_len;
1293 rxm->port = rxq->port_id;
1295 rxm->packet_type = ptype_tbl[IAVF_RX_FLEX_DESC_PTYPE_M &
1296 rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
1297 iavf_flex_rxd_to_vlan_tci(rxm, &rxd);
1298 rxq->rxd_to_pkt_fields(rxq, rxm, &rxd);
1299 pkt_flags = iavf_flex_rxd_error_to_pkt_flags(rx_stat_err0);
1300 rxm->ol_flags |= pkt_flags;
1302 rx_pkts[nb_rx++] = rxm;
1304 rxq->rx_tail = rx_id;
1306 iavf_update_rx_tail(rxq, nb_hold, rx_id);
1311 /* implement recv_scattered_pkts for flexible Rx descriptor */
1313 iavf_recv_scattered_pkts_flex_rxd(void *rx_queue, struct rte_mbuf **rx_pkts,
1316 struct iavf_rx_queue *rxq = rx_queue;
1317 union iavf_rx_flex_desc rxd;
1318 struct rte_mbuf *rxe;
1319 struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1320 struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1321 struct rte_mbuf *nmb, *rxm;
1322 uint16_t rx_id = rxq->rx_tail;
1323 uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
1324 struct rte_eth_dev *dev;
1325 uint16_t rx_stat_err0;
1329 volatile union iavf_rx_desc *rx_ring = rxq->rx_ring;
1330 volatile union iavf_rx_flex_desc *rxdp;
1331 const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1333 while (nb_rx < nb_pkts) {
1334 rxdp = (volatile union iavf_rx_flex_desc *)&rx_ring[rx_id];
1335 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1337 /* Check the DD bit */
1338 if (!(rx_stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S)))
1340 IAVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
1342 nmb = rte_mbuf_raw_alloc(rxq->mp);
1343 if (unlikely(!nmb)) {
1344 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1345 "queue_id=%u", rxq->port_id, rxq->queue_id);
1346 dev = &rte_eth_devices[rxq->port_id];
1347 dev->data->rx_mbuf_alloc_failed++;
1353 rxe = rxq->sw_ring[rx_id];
1355 if (rx_id == rxq->nb_rx_desc)
1358 /* Prefetch next mbuf */
1359 rte_prefetch0(rxq->sw_ring[rx_id]);
1361 /* When next RX descriptor is on a cache line boundary,
1362 * prefetch the next 4 RX descriptors and next 8 pointers
1365 if ((rx_id & 0x3) == 0) {
1366 rte_prefetch0(&rx_ring[rx_id]);
1367 rte_prefetch0(rxq->sw_ring[rx_id]);
1372 rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1374 /* Set data buffer address and data length of the mbuf */
1375 rxdp->read.hdr_addr = 0;
1376 rxdp->read.pkt_addr = dma_addr;
1377 rx_packet_len = rte_le_to_cpu_16(rxd.wb.pkt_len) &
1378 IAVF_RX_FLX_DESC_PKT_LEN_M;
1379 rxm->data_len = rx_packet_len;
1380 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1382 /* If this is the first buffer of the received packet, set the
1383 * pointer to the first mbuf of the packet and initialize its
1384 * context. Otherwise, update the total length and the number
1385 * of segments of the current scattered packet, and update the
1386 * pointer to the last mbuf of the current packet.
1390 first_seg->nb_segs = 1;
1391 first_seg->pkt_len = rx_packet_len;
1393 first_seg->pkt_len =
1394 (uint16_t)(first_seg->pkt_len +
1396 first_seg->nb_segs++;
1397 last_seg->next = rxm;
1400 /* If this is not the last buffer of the received packet,
1401 * update the pointer to the last mbuf of the current scattered
1402 * packet and continue to parse the RX ring.
1404 if (!(rx_stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_EOF_S))) {
1409 /* This is the last buffer of the received packet. If the CRC
1410 * is not stripped by the hardware:
1411 * - Subtract the CRC length from the total packet length.
1412 * - If the last buffer only contains the whole CRC or a part
1413 * of it, free the mbuf associated to the last buffer. If part
1414 * of the CRC is also contained in the previous mbuf, subtract
1415 * the length of that CRC part from the data length of the
1419 if (unlikely(rxq->crc_len > 0)) {
1420 first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
1421 if (rx_packet_len <= RTE_ETHER_CRC_LEN) {
1422 rte_pktmbuf_free_seg(rxm);
1423 first_seg->nb_segs--;
1424 last_seg->data_len =
1425 (uint16_t)(last_seg->data_len -
1426 (RTE_ETHER_CRC_LEN - rx_packet_len));
1427 last_seg->next = NULL;
1429 rxm->data_len = (uint16_t)(rx_packet_len -
1434 first_seg->port = rxq->port_id;
1435 first_seg->ol_flags = 0;
1436 first_seg->packet_type = ptype_tbl[IAVF_RX_FLEX_DESC_PTYPE_M &
1437 rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
1438 iavf_flex_rxd_to_vlan_tci(first_seg, &rxd);
1439 rxq->rxd_to_pkt_fields(rxq, first_seg, &rxd);
1440 pkt_flags = iavf_flex_rxd_error_to_pkt_flags(rx_stat_err0);
1442 first_seg->ol_flags |= pkt_flags;
1444 /* Prefetch data of first segment, if configured to do so. */
1445 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1446 first_seg->data_off));
1447 rx_pkts[nb_rx++] = first_seg;
1451 /* Record index of the next RX descriptor to probe. */
1452 rxq->rx_tail = rx_id;
1453 rxq->pkt_first_seg = first_seg;
1454 rxq->pkt_last_seg = last_seg;
1456 iavf_update_rx_tail(rxq, nb_hold, rx_id);
1461 /* implement recv_scattered_pkts */
1463 iavf_recv_scattered_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1466 struct iavf_rx_queue *rxq = rx_queue;
1467 union iavf_rx_desc rxd;
1468 struct rte_mbuf *rxe;
1469 struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1470 struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1471 struct rte_mbuf *nmb, *rxm;
1472 uint16_t rx_id = rxq->rx_tail;
1473 uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
1474 struct rte_eth_dev *dev;
1480 volatile union iavf_rx_desc *rx_ring = rxq->rx_ring;
1481 volatile union iavf_rx_desc *rxdp;
1482 const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1484 while (nb_rx < nb_pkts) {
1485 rxdp = &rx_ring[rx_id];
1486 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1487 rx_status = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
1488 IAVF_RXD_QW1_STATUS_SHIFT;
1490 /* Check the DD bit */
1491 if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)))
1493 IAVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
1495 nmb = rte_mbuf_raw_alloc(rxq->mp);
1496 if (unlikely(!nmb)) {
1497 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1498 "queue_id=%u", rxq->port_id, rxq->queue_id);
1499 dev = &rte_eth_devices[rxq->port_id];
1500 dev->data->rx_mbuf_alloc_failed++;
1506 rxe = rxq->sw_ring[rx_id];
1508 if (rx_id == rxq->nb_rx_desc)
1511 /* Prefetch next mbuf */
1512 rte_prefetch0(rxq->sw_ring[rx_id]);
1514 /* When next RX descriptor is on a cache line boundary,
1515 * prefetch the next 4 RX descriptors and next 8 pointers
1518 if ((rx_id & 0x3) == 0) {
1519 rte_prefetch0(&rx_ring[rx_id]);
1520 rte_prefetch0(rxq->sw_ring[rx_id]);
1525 rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1527 /* Set data buffer address and data length of the mbuf */
1528 rxdp->read.hdr_addr = 0;
1529 rxdp->read.pkt_addr = dma_addr;
1530 rx_packet_len = (qword1 & IAVF_RXD_QW1_LENGTH_PBUF_MASK) >>
1531 IAVF_RXD_QW1_LENGTH_PBUF_SHIFT;
1532 rxm->data_len = rx_packet_len;
1533 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1535 /* If this is the first buffer of the received packet, set the
1536 * pointer to the first mbuf of the packet and initialize its
1537 * context. Otherwise, update the total length and the number
1538 * of segments of the current scattered packet, and update the
1539 * pointer to the last mbuf of the current packet.
1543 first_seg->nb_segs = 1;
1544 first_seg->pkt_len = rx_packet_len;
1546 first_seg->pkt_len =
1547 (uint16_t)(first_seg->pkt_len +
1549 first_seg->nb_segs++;
1550 last_seg->next = rxm;
1553 /* If this is not the last buffer of the received packet,
1554 * update the pointer to the last mbuf of the current scattered
1555 * packet and continue to parse the RX ring.
1557 if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_EOF_SHIFT))) {
1562 /* This is the last buffer of the received packet. If the CRC
1563 * is not stripped by the hardware:
1564 * - Subtract the CRC length from the total packet length.
1565 * - If the last buffer only contains the whole CRC or a part
1566 * of it, free the mbuf associated to the last buffer. If part
1567 * of the CRC is also contained in the previous mbuf, subtract
1568 * the length of that CRC part from the data length of the
1572 if (unlikely(rxq->crc_len > 0)) {
1573 first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
1574 if (rx_packet_len <= RTE_ETHER_CRC_LEN) {
1575 rte_pktmbuf_free_seg(rxm);
1576 first_seg->nb_segs--;
1577 last_seg->data_len =
1578 (uint16_t)(last_seg->data_len -
1579 (RTE_ETHER_CRC_LEN - rx_packet_len));
1580 last_seg->next = NULL;
1582 rxm->data_len = (uint16_t)(rx_packet_len -
1586 first_seg->port = rxq->port_id;
1587 first_seg->ol_flags = 0;
1588 iavf_rxd_to_vlan_tci(first_seg, &rxd);
1589 pkt_flags = iavf_rxd_to_pkt_flags(qword1);
1590 first_seg->packet_type =
1591 ptype_tbl[(uint8_t)((qword1 &
1592 IAVF_RXD_QW1_PTYPE_MASK) >> IAVF_RXD_QW1_PTYPE_SHIFT)];
1594 if (pkt_flags & PKT_RX_RSS_HASH)
1595 first_seg->hash.rss =
1596 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1598 if (pkt_flags & PKT_RX_FDIR)
1599 pkt_flags |= iavf_rxd_build_fdir(&rxd, first_seg);
1601 first_seg->ol_flags |= pkt_flags;
1603 /* Prefetch data of first segment, if configured to do so. */
1604 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1605 first_seg->data_off));
1606 rx_pkts[nb_rx++] = first_seg;
1610 /* Record index of the next RX descriptor to probe. */
1611 rxq->rx_tail = rx_id;
1612 rxq->pkt_first_seg = first_seg;
1613 rxq->pkt_last_seg = last_seg;
1615 iavf_update_rx_tail(rxq, nb_hold, rx_id);
1620 #define IAVF_LOOK_AHEAD 8
1622 iavf_rx_scan_hw_ring_flex_rxd(struct iavf_rx_queue *rxq)
1624 volatile union iavf_rx_flex_desc *rxdp;
1625 struct rte_mbuf **rxep;
1626 struct rte_mbuf *mb;
1629 int32_t s[IAVF_LOOK_AHEAD], nb_dd;
1630 int32_t i, j, nb_rx = 0;
1632 const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1634 rxdp = (volatile union iavf_rx_flex_desc *)&rxq->rx_ring[rxq->rx_tail];
1635 rxep = &rxq->sw_ring[rxq->rx_tail];
1637 stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1639 /* Make sure there is at least 1 packet to receive */
1640 if (!(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S)))
1643 /* Scan LOOK_AHEAD descriptors at a time to determine which
1644 * descriptors reference packets that are ready to be received.
1646 for (i = 0; i < IAVF_RX_MAX_BURST; i += IAVF_LOOK_AHEAD,
1647 rxdp += IAVF_LOOK_AHEAD, rxep += IAVF_LOOK_AHEAD) {
1648 /* Read desc statuses backwards to avoid race condition */
1649 for (j = IAVF_LOOK_AHEAD - 1; j >= 0; j--)
1650 s[j] = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1654 /* Compute how many status bits were set */
1655 for (j = 0, nb_dd = 0; j < IAVF_LOOK_AHEAD; j++)
1656 nb_dd += s[j] & (1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S);
1660 /* Translate descriptor info to mbuf parameters */
1661 for (j = 0; j < nb_dd; j++) {
1662 IAVF_DUMP_RX_DESC(rxq, &rxdp[j],
1664 i * IAVF_LOOK_AHEAD + j);
1667 pkt_len = (rte_le_to_cpu_16(rxdp[j].wb.pkt_len) &
1668 IAVF_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
1669 mb->data_len = pkt_len;
1670 mb->pkt_len = pkt_len;
1673 mb->packet_type = ptype_tbl[IAVF_RX_FLEX_DESC_PTYPE_M &
1674 rte_le_to_cpu_16(rxdp[j].wb.ptype_flex_flags0)];
1675 iavf_flex_rxd_to_vlan_tci(mb, &rxdp[j]);
1676 rxq->rxd_to_pkt_fields(rxq, mb, &rxdp[j]);
1677 stat_err0 = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1678 pkt_flags = iavf_flex_rxd_error_to_pkt_flags(stat_err0);
1680 mb->ol_flags |= pkt_flags;
1683 for (j = 0; j < IAVF_LOOK_AHEAD; j++)
1684 rxq->rx_stage[i + j] = rxep[j];
1686 if (nb_dd != IAVF_LOOK_AHEAD)
1690 /* Clear software ring entries */
1691 for (i = 0; i < nb_rx; i++)
1692 rxq->sw_ring[rxq->rx_tail + i] = NULL;
1698 iavf_rx_scan_hw_ring(struct iavf_rx_queue *rxq)
1700 volatile union iavf_rx_desc *rxdp;
1701 struct rte_mbuf **rxep;
1702 struct rte_mbuf *mb;
1706 int32_t s[IAVF_LOOK_AHEAD], nb_dd;
1707 int32_t i, j, nb_rx = 0;
1709 const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1711 rxdp = &rxq->rx_ring[rxq->rx_tail];
1712 rxep = &rxq->sw_ring[rxq->rx_tail];
1714 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1715 rx_status = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
1716 IAVF_RXD_QW1_STATUS_SHIFT;
1718 /* Make sure there is at least 1 packet to receive */
1719 if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)))
1722 /* Scan LOOK_AHEAD descriptors at a time to determine which
1723 * descriptors reference packets that are ready to be received.
1725 for (i = 0; i < IAVF_RX_MAX_BURST; i += IAVF_LOOK_AHEAD,
1726 rxdp += IAVF_LOOK_AHEAD, rxep += IAVF_LOOK_AHEAD) {
1727 /* Read desc statuses backwards to avoid race condition */
1728 for (j = IAVF_LOOK_AHEAD - 1; j >= 0; j--) {
1729 qword1 = rte_le_to_cpu_64(
1730 rxdp[j].wb.qword1.status_error_len);
1731 s[j] = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
1732 IAVF_RXD_QW1_STATUS_SHIFT;
1737 /* Compute how many status bits were set */
1738 for (j = 0, nb_dd = 0; j < IAVF_LOOK_AHEAD; j++)
1739 nb_dd += s[j] & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT);
1743 /* Translate descriptor info to mbuf parameters */
1744 for (j = 0; j < nb_dd; j++) {
1745 IAVF_DUMP_RX_DESC(rxq, &rxdp[j],
1746 rxq->rx_tail + i * IAVF_LOOK_AHEAD + j);
1749 qword1 = rte_le_to_cpu_64
1750 (rxdp[j].wb.qword1.status_error_len);
1751 pkt_len = ((qword1 & IAVF_RXD_QW1_LENGTH_PBUF_MASK) >>
1752 IAVF_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
1753 mb->data_len = pkt_len;
1754 mb->pkt_len = pkt_len;
1756 iavf_rxd_to_vlan_tci(mb, &rxdp[j]);
1757 pkt_flags = iavf_rxd_to_pkt_flags(qword1);
1759 ptype_tbl[(uint8_t)((qword1 &
1760 IAVF_RXD_QW1_PTYPE_MASK) >>
1761 IAVF_RXD_QW1_PTYPE_SHIFT)];
1763 if (pkt_flags & PKT_RX_RSS_HASH)
1764 mb->hash.rss = rte_le_to_cpu_32(
1765 rxdp[j].wb.qword0.hi_dword.rss);
1767 if (pkt_flags & PKT_RX_FDIR)
1768 pkt_flags |= iavf_rxd_build_fdir(&rxdp[j], mb);
1770 mb->ol_flags |= pkt_flags;
1773 for (j = 0; j < IAVF_LOOK_AHEAD; j++)
1774 rxq->rx_stage[i + j] = rxep[j];
1776 if (nb_dd != IAVF_LOOK_AHEAD)
1780 /* Clear software ring entries */
1781 for (i = 0; i < nb_rx; i++)
1782 rxq->sw_ring[rxq->rx_tail + i] = NULL;
1787 static inline uint16_t
1788 iavf_rx_fill_from_stage(struct iavf_rx_queue *rxq,
1789 struct rte_mbuf **rx_pkts,
1793 struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1795 nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1797 for (i = 0; i < nb_pkts; i++)
1798 rx_pkts[i] = stage[i];
1800 rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1801 rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1807 iavf_rx_alloc_bufs(struct iavf_rx_queue *rxq)
1809 volatile union iavf_rx_desc *rxdp;
1810 struct rte_mbuf **rxep;
1811 struct rte_mbuf *mb;
1812 uint16_t alloc_idx, i;
1816 /* Allocate buffers in bulk */
1817 alloc_idx = (uint16_t)(rxq->rx_free_trigger -
1818 (rxq->rx_free_thresh - 1));
1819 rxep = &rxq->sw_ring[alloc_idx];
1820 diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
1821 rxq->rx_free_thresh);
1822 if (unlikely(diag != 0)) {
1823 PMD_RX_LOG(ERR, "Failed to get mbufs in bulk");
1827 rxdp = &rxq->rx_ring[alloc_idx];
1828 for (i = 0; i < rxq->rx_free_thresh; i++) {
1829 if (likely(i < (rxq->rx_free_thresh - 1)))
1830 /* Prefetch next mbuf */
1831 rte_prefetch0(rxep[i + 1]);
1834 rte_mbuf_refcnt_set(mb, 1);
1836 mb->data_off = RTE_PKTMBUF_HEADROOM;
1838 mb->port = rxq->port_id;
1839 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mb));
1840 rxdp[i].read.hdr_addr = 0;
1841 rxdp[i].read.pkt_addr = dma_addr;
1844 /* Update rx tail register */
1846 IAVF_PCI_REG_WRITE_RELAXED(rxq->qrx_tail, rxq->rx_free_trigger);
1848 rxq->rx_free_trigger =
1849 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
1850 if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1851 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
1856 static inline uint16_t
1857 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1859 struct iavf_rx_queue *rxq = (struct iavf_rx_queue *)rx_queue;
1865 if (rxq->rx_nb_avail)
1866 return iavf_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1868 if (rxq->rxdid >= IAVF_RXDID_FLEX_NIC && rxq->rxdid <= IAVF_RXDID_LAST)
1869 nb_rx = (uint16_t)iavf_rx_scan_hw_ring_flex_rxd(rxq);
1871 nb_rx = (uint16_t)iavf_rx_scan_hw_ring(rxq);
1872 rxq->rx_next_avail = 0;
1873 rxq->rx_nb_avail = nb_rx;
1874 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1876 if (rxq->rx_tail > rxq->rx_free_trigger) {
1877 if (iavf_rx_alloc_bufs(rxq) != 0) {
1880 /* TODO: count rx_mbuf_alloc_failed here */
1882 rxq->rx_nb_avail = 0;
1883 rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1884 for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
1885 rxq->sw_ring[j] = rxq->rx_stage[i];
1891 if (rxq->rx_tail >= rxq->nb_rx_desc)
1894 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u, nb_rx=%u",
1895 rxq->port_id, rxq->queue_id,
1896 rxq->rx_tail, nb_rx);
1898 if (rxq->rx_nb_avail)
1899 return iavf_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1905 iavf_recv_pkts_bulk_alloc(void *rx_queue,
1906 struct rte_mbuf **rx_pkts,
1909 uint16_t nb_rx = 0, n, count;
1911 if (unlikely(nb_pkts == 0))
1914 if (likely(nb_pkts <= IAVF_RX_MAX_BURST))
1915 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1918 n = RTE_MIN(nb_pkts, IAVF_RX_MAX_BURST);
1919 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1920 nb_rx = (uint16_t)(nb_rx + count);
1921 nb_pkts = (uint16_t)(nb_pkts - count);
1930 iavf_xmit_cleanup(struct iavf_tx_queue *txq)
1932 struct iavf_tx_entry *sw_ring = txq->sw_ring;
1933 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
1934 uint16_t nb_tx_desc = txq->nb_tx_desc;
1935 uint16_t desc_to_clean_to;
1936 uint16_t nb_tx_to_clean;
1938 volatile struct iavf_tx_desc *txd = txq->tx_ring;
1940 desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->rs_thresh);
1941 if (desc_to_clean_to >= nb_tx_desc)
1942 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
1944 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
1945 if ((txd[desc_to_clean_to].cmd_type_offset_bsz &
1946 rte_cpu_to_le_64(IAVF_TXD_QW1_DTYPE_MASK)) !=
1947 rte_cpu_to_le_64(IAVF_TX_DESC_DTYPE_DESC_DONE)) {
1948 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
1949 "(port=%d queue=%d)", desc_to_clean_to,
1950 txq->port_id, txq->queue_id);
1954 if (last_desc_cleaned > desc_to_clean_to)
1955 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
1958 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
1961 txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
1963 txq->last_desc_cleaned = desc_to_clean_to;
1964 txq->nb_free = (uint16_t)(txq->nb_free + nb_tx_to_clean);
1969 /* Check if the context descriptor is needed for TX offloading */
1970 static inline uint16_t
1971 iavf_calc_context_desc(uint64_t flags)
1973 static uint64_t mask = PKT_TX_TCP_SEG;
1975 return (flags & mask) ? 1 : 0;
1979 iavf_txd_enable_checksum(uint64_t ol_flags,
1981 uint32_t *td_offset,
1982 union iavf_tx_offload tx_offload)
1985 *td_offset |= (tx_offload.l2_len >> 1) <<
1986 IAVF_TX_DESC_LENGTH_MACLEN_SHIFT;
1988 /* Enable L3 checksum offloads */
1989 if (ol_flags & PKT_TX_IP_CKSUM) {
1990 *td_cmd |= IAVF_TX_DESC_CMD_IIPT_IPV4_CSUM;
1991 *td_offset |= (tx_offload.l3_len >> 2) <<
1992 IAVF_TX_DESC_LENGTH_IPLEN_SHIFT;
1993 } else if (ol_flags & PKT_TX_IPV4) {
1994 *td_cmd |= IAVF_TX_DESC_CMD_IIPT_IPV4;
1995 *td_offset |= (tx_offload.l3_len >> 2) <<
1996 IAVF_TX_DESC_LENGTH_IPLEN_SHIFT;
1997 } else if (ol_flags & PKT_TX_IPV6) {
1998 *td_cmd |= IAVF_TX_DESC_CMD_IIPT_IPV6;
1999 *td_offset |= (tx_offload.l3_len >> 2) <<
2000 IAVF_TX_DESC_LENGTH_IPLEN_SHIFT;
2003 if (ol_flags & PKT_TX_TCP_SEG) {
2004 *td_cmd |= IAVF_TX_DESC_CMD_L4T_EOFT_TCP;
2005 *td_offset |= (tx_offload.l4_len >> 2) <<
2006 IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2010 /* Enable L4 checksum offloads */
2011 switch (ol_flags & PKT_TX_L4_MASK) {
2012 case PKT_TX_TCP_CKSUM:
2013 *td_cmd |= IAVF_TX_DESC_CMD_L4T_EOFT_TCP;
2014 *td_offset |= (sizeof(struct rte_tcp_hdr) >> 2) <<
2015 IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2017 case PKT_TX_SCTP_CKSUM:
2018 *td_cmd |= IAVF_TX_DESC_CMD_L4T_EOFT_SCTP;
2019 *td_offset |= (sizeof(struct rte_sctp_hdr) >> 2) <<
2020 IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2022 case PKT_TX_UDP_CKSUM:
2023 *td_cmd |= IAVF_TX_DESC_CMD_L4T_EOFT_UDP;
2024 *td_offset |= (sizeof(struct rte_udp_hdr) >> 2) <<
2025 IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2032 /* set TSO context descriptor
2033 * support IP -> L4 and IP -> IP -> L4
2035 static inline uint64_t
2036 iavf_set_tso_ctx(struct rte_mbuf *mbuf, union iavf_tx_offload tx_offload)
2038 uint64_t ctx_desc = 0;
2039 uint32_t cd_cmd, hdr_len, cd_tso_len;
2041 if (!tx_offload.l4_len) {
2042 PMD_TX_LOG(DEBUG, "L4 length set to 0");
2046 hdr_len = tx_offload.l2_len +
2050 cd_cmd = IAVF_TX_CTX_DESC_TSO;
2051 cd_tso_len = mbuf->pkt_len - hdr_len;
2052 ctx_desc |= ((uint64_t)cd_cmd << IAVF_TXD_CTX_QW1_CMD_SHIFT) |
2053 ((uint64_t)cd_tso_len << IAVF_TXD_CTX_QW1_TSO_LEN_SHIFT) |
2054 ((uint64_t)mbuf->tso_segsz << IAVF_TXD_CTX_QW1_MSS_SHIFT);
2059 /* Construct the tx flags */
2060 static inline uint64_t
2061 iavf_build_ctob(uint32_t td_cmd, uint32_t td_offset, unsigned int size,
2064 return rte_cpu_to_le_64(IAVF_TX_DESC_DTYPE_DATA |
2065 ((uint64_t)td_cmd << IAVF_TXD_QW1_CMD_SHIFT) |
2066 ((uint64_t)td_offset <<
2067 IAVF_TXD_QW1_OFFSET_SHIFT) |
2069 IAVF_TXD_QW1_TX_BUF_SZ_SHIFT) |
2070 ((uint64_t)td_tag <<
2071 IAVF_TXD_QW1_L2TAG1_SHIFT));
2076 iavf_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2078 volatile struct iavf_tx_desc *txd;
2079 volatile struct iavf_tx_desc *txr;
2080 struct iavf_tx_queue *txq;
2081 struct iavf_tx_entry *sw_ring;
2082 struct iavf_tx_entry *txe, *txn;
2083 struct rte_mbuf *tx_pkt;
2084 struct rte_mbuf *m_seg;
2095 uint64_t buf_dma_addr;
2096 union iavf_tx_offload tx_offload = {0};
2099 sw_ring = txq->sw_ring;
2101 tx_id = txq->tx_tail;
2102 txe = &sw_ring[tx_id];
2104 /* Check if the descriptor ring needs to be cleaned. */
2105 if (txq->nb_free < txq->free_thresh)
2106 (void)iavf_xmit_cleanup(txq);
2108 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
2113 tx_pkt = *tx_pkts++;
2114 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
2116 ol_flags = tx_pkt->ol_flags;
2117 tx_offload.l2_len = tx_pkt->l2_len;
2118 tx_offload.l3_len = tx_pkt->l3_len;
2119 tx_offload.l4_len = tx_pkt->l4_len;
2120 tx_offload.tso_segsz = tx_pkt->tso_segsz;
2121 /* Calculate the number of context descriptors needed. */
2122 nb_ctx = iavf_calc_context_desc(ol_flags);
2124 /* The number of descriptors that must be allocated for
2125 * a packet equals to the number of the segments of that
2126 * packet plus 1 context descriptor if needed.
2128 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
2129 tx_last = (uint16_t)(tx_id + nb_used - 1);
2132 if (tx_last >= txq->nb_tx_desc)
2133 tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
2135 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u"
2136 " tx_first=%u tx_last=%u",
2137 txq->port_id, txq->queue_id, tx_id, tx_last);
2139 if (nb_used > txq->nb_free) {
2140 if (iavf_xmit_cleanup(txq)) {
2145 if (unlikely(nb_used > txq->rs_thresh)) {
2146 while (nb_used > txq->nb_free) {
2147 if (iavf_xmit_cleanup(txq)) {
2156 /* Descriptor based VLAN insertion */
2157 if (ol_flags & PKT_TX_VLAN_PKT) {
2158 td_cmd |= IAVF_TX_DESC_CMD_IL2TAG1;
2159 td_tag = tx_pkt->vlan_tci;
2162 /* According to datasheet, the bit2 is reserved and must be
2167 /* Enable checksum offloading */
2168 if (ol_flags & IAVF_TX_CKSUM_OFFLOAD_MASK)
2169 iavf_txd_enable_checksum(ol_flags, &td_cmd,
2170 &td_offset, tx_offload);
2173 /* Setup TX context descriptor if required */
2174 uint64_t cd_type_cmd_tso_mss =
2175 IAVF_TX_DESC_DTYPE_CONTEXT;
2176 volatile struct iavf_tx_context_desc *ctx_txd =
2177 (volatile struct iavf_tx_context_desc *)
2180 txn = &sw_ring[txe->next_id];
2181 RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
2183 rte_pktmbuf_free_seg(txe->mbuf);
2188 if (ol_flags & PKT_TX_TCP_SEG)
2189 cd_type_cmd_tso_mss |=
2190 iavf_set_tso_ctx(tx_pkt, tx_offload);
2192 ctx_txd->type_cmd_tso_mss =
2193 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
2195 IAVF_DUMP_TX_DESC(txq, &txr[tx_id], tx_id);
2196 txe->last_id = tx_last;
2197 tx_id = txe->next_id;
2204 txn = &sw_ring[txe->next_id];
2207 rte_pktmbuf_free_seg(txe->mbuf);
2210 /* Setup TX Descriptor */
2211 slen = m_seg->data_len;
2212 buf_dma_addr = rte_mbuf_data_iova(m_seg);
2213 txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
2214 txd->cmd_type_offset_bsz = iavf_build_ctob(td_cmd,
2219 IAVF_DUMP_TX_DESC(txq, txd, tx_id);
2220 txe->last_id = tx_last;
2221 tx_id = txe->next_id;
2223 m_seg = m_seg->next;
2226 /* The last packet data descriptor needs End Of Packet (EOP) */
2227 td_cmd |= IAVF_TX_DESC_CMD_EOP;
2228 txq->nb_used = (uint16_t)(txq->nb_used + nb_used);
2229 txq->nb_free = (uint16_t)(txq->nb_free - nb_used);
2231 if (txq->nb_used >= txq->rs_thresh) {
2232 PMD_TX_LOG(DEBUG, "Setting RS bit on TXD id="
2233 "%4u (port=%d queue=%d)",
2234 tx_last, txq->port_id, txq->queue_id);
2236 td_cmd |= IAVF_TX_DESC_CMD_RS;
2238 /* Update txq RS bit counters */
2242 txd->cmd_type_offset_bsz |=
2243 rte_cpu_to_le_64(((uint64_t)td_cmd) <<
2244 IAVF_TXD_QW1_CMD_SHIFT);
2245 IAVF_DUMP_TX_DESC(txq, txd, tx_id);
2251 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
2252 txq->port_id, txq->queue_id, tx_id, nb_tx);
2254 IAVF_PCI_REG_WRITE_RELAXED(txq->qtx_tail, tx_id);
2255 txq->tx_tail = tx_id;
2260 /* TX prep functions */
2262 iavf_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
2269 for (i = 0; i < nb_pkts; i++) {
2271 ol_flags = m->ol_flags;
2273 /* Check condition for nb_segs > IAVF_TX_MAX_MTU_SEG. */
2274 if (!(ol_flags & PKT_TX_TCP_SEG)) {
2275 if (m->nb_segs > IAVF_TX_MAX_MTU_SEG) {
2279 } else if ((m->tso_segsz < IAVF_MIN_TSO_MSS) ||
2280 (m->tso_segsz > IAVF_MAX_TSO_MSS)) {
2281 /* MSS outside the range are considered malicious */
2286 if (ol_flags & IAVF_TX_OFFLOAD_NOTSUP_MASK) {
2287 rte_errno = ENOTSUP;
2291 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
2292 ret = rte_validate_tx_offload(m);
2298 ret = rte_net_intel_cksum_prepare(m);
2308 /* choose rx function*/
2310 iavf_set_rx_function(struct rte_eth_dev *dev)
2312 struct iavf_adapter *adapter =
2313 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2314 struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2317 struct iavf_rx_queue *rxq;
2319 bool use_avx2 = false;
2320 #ifdef CC_AVX512_SUPPORT
2321 bool use_avx512 = false;
2324 if (!iavf_rx_vec_dev_check(dev) &&
2325 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
2326 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2327 rxq = dev->data->rx_queues[i];
2328 (void)iavf_rxq_vec_setup(rxq);
2331 if ((rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
2332 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) &&
2333 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256)
2335 #ifdef CC_AVX512_SUPPORT
2336 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 &&
2337 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1 &&
2338 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512)
2342 if (dev->data->scattered_rx) {
2344 "Using %sVector Scattered Rx (port %d).",
2345 use_avx2 ? "avx2 " : "",
2346 dev->data->port_id);
2347 if (vf->vf_res->vf_cap_flags &
2348 VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC) {
2349 dev->rx_pkt_burst = use_avx2 ?
2350 iavf_recv_scattered_pkts_vec_avx2_flex_rxd :
2351 iavf_recv_scattered_pkts_vec_flex_rxd;
2352 #ifdef CC_AVX512_SUPPORT
2355 iavf_recv_scattered_pkts_vec_avx512_flex_rxd;
2358 dev->rx_pkt_burst = use_avx2 ?
2359 iavf_recv_scattered_pkts_vec_avx2 :
2360 iavf_recv_scattered_pkts_vec;
2361 #ifdef CC_AVX512_SUPPORT
2364 iavf_recv_scattered_pkts_vec_avx512;
2368 PMD_DRV_LOG(DEBUG, "Using %sVector Rx (port %d).",
2369 use_avx2 ? "avx2 " : "",
2370 dev->data->port_id);
2371 if (vf->vf_res->vf_cap_flags &
2372 VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC) {
2373 dev->rx_pkt_burst = use_avx2 ?
2374 iavf_recv_pkts_vec_avx2_flex_rxd :
2375 iavf_recv_pkts_vec_flex_rxd;
2376 #ifdef CC_AVX512_SUPPORT
2379 iavf_recv_pkts_vec_avx512_flex_rxd;
2382 dev->rx_pkt_burst = use_avx2 ?
2383 iavf_recv_pkts_vec_avx2 :
2385 #ifdef CC_AVX512_SUPPORT
2388 iavf_recv_pkts_vec_avx512;
2397 if (dev->data->scattered_rx) {
2398 PMD_DRV_LOG(DEBUG, "Using a Scattered Rx callback (port=%d).",
2399 dev->data->port_id);
2400 if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC)
2401 dev->rx_pkt_burst = iavf_recv_scattered_pkts_flex_rxd;
2403 dev->rx_pkt_burst = iavf_recv_scattered_pkts;
2404 } else if (adapter->rx_bulk_alloc_allowed) {
2405 PMD_DRV_LOG(DEBUG, "Using bulk Rx callback (port=%d).",
2406 dev->data->port_id);
2407 dev->rx_pkt_burst = iavf_recv_pkts_bulk_alloc;
2409 PMD_DRV_LOG(DEBUG, "Using Basic Rx callback (port=%d).",
2410 dev->data->port_id);
2411 if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC)
2412 dev->rx_pkt_burst = iavf_recv_pkts_flex_rxd;
2414 dev->rx_pkt_burst = iavf_recv_pkts;
2418 /* choose tx function*/
2420 iavf_set_tx_function(struct rte_eth_dev *dev)
2423 struct iavf_tx_queue *txq;
2425 bool use_avx2 = false;
2426 #ifdef CC_AVX512_SUPPORT
2427 bool use_avx512 = false;
2430 if (!iavf_tx_vec_dev_check(dev) &&
2431 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
2432 if ((rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
2433 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) &&
2434 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256)
2436 #ifdef CC_AVX512_SUPPORT
2437 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 &&
2438 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1 &&
2439 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512)
2443 PMD_DRV_LOG(DEBUG, "Using %sVector Tx (port %d).",
2444 use_avx2 ? "avx2 " : "",
2445 dev->data->port_id);
2446 dev->tx_pkt_burst = use_avx2 ?
2447 iavf_xmit_pkts_vec_avx2 :
2449 #ifdef CC_AVX512_SUPPORT
2451 dev->tx_pkt_burst = iavf_xmit_pkts_vec_avx512;
2453 dev->tx_pkt_prepare = NULL;
2455 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2456 txq = dev->data->tx_queues[i];
2459 #ifdef CC_AVX512_SUPPORT
2461 iavf_txq_vec_setup_avx512(txq);
2463 iavf_txq_vec_setup(txq);
2465 iavf_txq_vec_setup(txq);
2473 PMD_DRV_LOG(DEBUG, "Using Basic Tx callback (port=%d).",
2474 dev->data->port_id);
2475 dev->tx_pkt_burst = iavf_xmit_pkts;
2476 dev->tx_pkt_prepare = iavf_prep_pkts;
2480 iavf_tx_done_cleanup_full(struct iavf_tx_queue *txq,
2483 struct iavf_tx_entry *swr_ring = txq->sw_ring;
2484 uint16_t i, tx_last, tx_id;
2485 uint16_t nb_tx_free_last;
2486 uint16_t nb_tx_to_clean;
2489 /* Start free mbuf from the next of tx_tail */
2490 tx_last = txq->tx_tail;
2491 tx_id = swr_ring[tx_last].next_id;
2493 if (txq->nb_free == 0 && iavf_xmit_cleanup(txq))
2496 nb_tx_to_clean = txq->nb_free;
2497 nb_tx_free_last = txq->nb_free;
2499 free_cnt = txq->nb_tx_desc;
2501 /* Loop through swr_ring to count the amount of
2502 * freeable mubfs and packets.
2504 for (pkt_cnt = 0; pkt_cnt < free_cnt; ) {
2505 for (i = 0; i < nb_tx_to_clean &&
2506 pkt_cnt < free_cnt &&
2507 tx_id != tx_last; i++) {
2508 if (swr_ring[tx_id].mbuf != NULL) {
2509 rte_pktmbuf_free_seg(swr_ring[tx_id].mbuf);
2510 swr_ring[tx_id].mbuf = NULL;
2513 * last segment in the packet,
2514 * increment packet count
2516 pkt_cnt += (swr_ring[tx_id].last_id == tx_id);
2519 tx_id = swr_ring[tx_id].next_id;
2522 if (txq->rs_thresh > txq->nb_tx_desc -
2523 txq->nb_free || tx_id == tx_last)
2526 if (pkt_cnt < free_cnt) {
2527 if (iavf_xmit_cleanup(txq))
2530 nb_tx_to_clean = txq->nb_free - nb_tx_free_last;
2531 nb_tx_free_last = txq->nb_free;
2535 return (int)pkt_cnt;
2539 iavf_dev_tx_done_cleanup(void *txq, uint32_t free_cnt)
2541 struct iavf_tx_queue *q = (struct iavf_tx_queue *)txq;
2543 return iavf_tx_done_cleanup_full(q, free_cnt);
2547 iavf_dev_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2548 struct rte_eth_rxq_info *qinfo)
2550 struct iavf_rx_queue *rxq;
2552 rxq = dev->data->rx_queues[queue_id];
2554 qinfo->mp = rxq->mp;
2555 qinfo->scattered_rx = dev->data->scattered_rx;
2556 qinfo->nb_desc = rxq->nb_rx_desc;
2558 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2559 qinfo->conf.rx_drop_en = true;
2560 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2564 iavf_dev_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2565 struct rte_eth_txq_info *qinfo)
2567 struct iavf_tx_queue *txq;
2569 txq = dev->data->tx_queues[queue_id];
2571 qinfo->nb_desc = txq->nb_tx_desc;
2573 qinfo->conf.tx_free_thresh = txq->free_thresh;
2574 qinfo->conf.tx_rs_thresh = txq->rs_thresh;
2575 qinfo->conf.offloads = txq->offloads;
2576 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2579 /* Get the number of used descriptors of a rx queue */
2581 iavf_dev_rxq_count(struct rte_eth_dev *dev, uint16_t queue_id)
2583 #define IAVF_RXQ_SCAN_INTERVAL 4
2584 volatile union iavf_rx_desc *rxdp;
2585 struct iavf_rx_queue *rxq;
2588 rxq = dev->data->rx_queues[queue_id];
2589 rxdp = &rxq->rx_ring[rxq->rx_tail];
2591 while ((desc < rxq->nb_rx_desc) &&
2592 ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
2593 IAVF_RXD_QW1_STATUS_MASK) >> IAVF_RXD_QW1_STATUS_SHIFT) &
2594 (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)) {
2595 /* Check the DD bit of a rx descriptor of each 4 in a group,
2596 * to avoid checking too frequently and downgrading performance
2599 desc += IAVF_RXQ_SCAN_INTERVAL;
2600 rxdp += IAVF_RXQ_SCAN_INTERVAL;
2601 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
2602 rxdp = &(rxq->rx_ring[rxq->rx_tail +
2603 desc - rxq->nb_rx_desc]);
2610 iavf_dev_rx_desc_status(void *rx_queue, uint16_t offset)
2612 struct iavf_rx_queue *rxq = rx_queue;
2613 volatile uint64_t *status;
2617 if (unlikely(offset >= rxq->nb_rx_desc))
2620 if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
2621 return RTE_ETH_RX_DESC_UNAVAIL;
2623 desc = rxq->rx_tail + offset;
2624 if (desc >= rxq->nb_rx_desc)
2625 desc -= rxq->nb_rx_desc;
2627 status = &rxq->rx_ring[desc].wb.qword1.status_error_len;
2628 mask = rte_le_to_cpu_64((1ULL << IAVF_RX_DESC_STATUS_DD_SHIFT)
2629 << IAVF_RXD_QW1_STATUS_SHIFT);
2631 return RTE_ETH_RX_DESC_DONE;
2633 return RTE_ETH_RX_DESC_AVAIL;
2637 iavf_dev_tx_desc_status(void *tx_queue, uint16_t offset)
2639 struct iavf_tx_queue *txq = tx_queue;
2640 volatile uint64_t *status;
2641 uint64_t mask, expect;
2644 if (unlikely(offset >= txq->nb_tx_desc))
2647 desc = txq->tx_tail + offset;
2648 /* go to next desc that has the RS bit */
2649 desc = ((desc + txq->rs_thresh - 1) / txq->rs_thresh) *
2651 if (desc >= txq->nb_tx_desc) {
2652 desc -= txq->nb_tx_desc;
2653 if (desc >= txq->nb_tx_desc)
2654 desc -= txq->nb_tx_desc;
2657 status = &txq->tx_ring[desc].cmd_type_offset_bsz;
2658 mask = rte_le_to_cpu_64(IAVF_TXD_QW1_DTYPE_MASK);
2659 expect = rte_cpu_to_le_64(
2660 IAVF_TX_DESC_DTYPE_DESC_DONE << IAVF_TXD_QW1_DTYPE_SHIFT);
2661 if ((*status & mask) == expect)
2662 return RTE_ETH_TX_DESC_DONE;
2664 return RTE_ETH_TX_DESC_FULL;
2668 iavf_get_default_ptype_table(void)
2670 static const uint32_t ptype_tbl[IAVF_MAX_PKT_TYPE]
2671 __rte_cache_aligned = {
2674 [1] = RTE_PTYPE_L2_ETHER,
2675 [2] = RTE_PTYPE_L2_ETHER_TIMESYNC,
2676 /* [3] - [5] reserved */
2677 [6] = RTE_PTYPE_L2_ETHER_LLDP,
2678 /* [7] - [10] reserved */
2679 [11] = RTE_PTYPE_L2_ETHER_ARP,
2680 /* [12] - [21] reserved */
2682 /* Non tunneled IPv4 */
2683 [22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2685 [23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2686 RTE_PTYPE_L4_NONFRAG,
2687 [24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2690 [26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2692 [27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2694 [28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2698 [29] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2699 RTE_PTYPE_TUNNEL_IP |
2700 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2701 RTE_PTYPE_INNER_L4_FRAG,
2702 [30] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2703 RTE_PTYPE_TUNNEL_IP |
2704 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2705 RTE_PTYPE_INNER_L4_NONFRAG,
2706 [31] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2707 RTE_PTYPE_TUNNEL_IP |
2708 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2709 RTE_PTYPE_INNER_L4_UDP,
2711 [33] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2712 RTE_PTYPE_TUNNEL_IP |
2713 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2714 RTE_PTYPE_INNER_L4_TCP,
2715 [34] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2716 RTE_PTYPE_TUNNEL_IP |
2717 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2718 RTE_PTYPE_INNER_L4_SCTP,
2719 [35] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2720 RTE_PTYPE_TUNNEL_IP |
2721 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2722 RTE_PTYPE_INNER_L4_ICMP,
2725 [36] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2726 RTE_PTYPE_TUNNEL_IP |
2727 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2728 RTE_PTYPE_INNER_L4_FRAG,
2729 [37] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2730 RTE_PTYPE_TUNNEL_IP |
2731 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2732 RTE_PTYPE_INNER_L4_NONFRAG,
2733 [38] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2734 RTE_PTYPE_TUNNEL_IP |
2735 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2736 RTE_PTYPE_INNER_L4_UDP,
2738 [40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2739 RTE_PTYPE_TUNNEL_IP |
2740 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2741 RTE_PTYPE_INNER_L4_TCP,
2742 [41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2743 RTE_PTYPE_TUNNEL_IP |
2744 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2745 RTE_PTYPE_INNER_L4_SCTP,
2746 [42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2747 RTE_PTYPE_TUNNEL_IP |
2748 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2749 RTE_PTYPE_INNER_L4_ICMP,
2751 /* IPv4 --> GRE/Teredo/VXLAN */
2752 [43] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2753 RTE_PTYPE_TUNNEL_GRENAT,
2755 /* IPv4 --> GRE/Teredo/VXLAN --> IPv4 */
2756 [44] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2757 RTE_PTYPE_TUNNEL_GRENAT |
2758 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2759 RTE_PTYPE_INNER_L4_FRAG,
2760 [45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2761 RTE_PTYPE_TUNNEL_GRENAT |
2762 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2763 RTE_PTYPE_INNER_L4_NONFRAG,
2764 [46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2765 RTE_PTYPE_TUNNEL_GRENAT |
2766 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2767 RTE_PTYPE_INNER_L4_UDP,
2769 [48] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2770 RTE_PTYPE_TUNNEL_GRENAT |
2771 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2772 RTE_PTYPE_INNER_L4_TCP,
2773 [49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2774 RTE_PTYPE_TUNNEL_GRENAT |
2775 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2776 RTE_PTYPE_INNER_L4_SCTP,
2777 [50] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2778 RTE_PTYPE_TUNNEL_GRENAT |
2779 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2780 RTE_PTYPE_INNER_L4_ICMP,
2782 /* IPv4 --> GRE/Teredo/VXLAN --> IPv6 */
2783 [51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2784 RTE_PTYPE_TUNNEL_GRENAT |
2785 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2786 RTE_PTYPE_INNER_L4_FRAG,
2787 [52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2788 RTE_PTYPE_TUNNEL_GRENAT |
2789 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2790 RTE_PTYPE_INNER_L4_NONFRAG,
2791 [53] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2792 RTE_PTYPE_TUNNEL_GRENAT |
2793 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2794 RTE_PTYPE_INNER_L4_UDP,
2796 [55] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2797 RTE_PTYPE_TUNNEL_GRENAT |
2798 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2799 RTE_PTYPE_INNER_L4_TCP,
2800 [56] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2801 RTE_PTYPE_TUNNEL_GRENAT |
2802 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2803 RTE_PTYPE_INNER_L4_SCTP,
2804 [57] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2805 RTE_PTYPE_TUNNEL_GRENAT |
2806 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2807 RTE_PTYPE_INNER_L4_ICMP,
2809 /* IPv4 --> GRE/Teredo/VXLAN --> MAC */
2810 [58] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2811 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
2813 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
2814 [59] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2815 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2816 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2817 RTE_PTYPE_INNER_L4_FRAG,
2818 [60] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2819 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2820 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2821 RTE_PTYPE_INNER_L4_NONFRAG,
2822 [61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2823 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2824 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2825 RTE_PTYPE_INNER_L4_UDP,
2827 [63] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2828 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2829 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2830 RTE_PTYPE_INNER_L4_TCP,
2831 [64] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2832 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2833 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2834 RTE_PTYPE_INNER_L4_SCTP,
2835 [65] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2836 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2837 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2838 RTE_PTYPE_INNER_L4_ICMP,
2840 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
2841 [66] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2842 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2843 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2844 RTE_PTYPE_INNER_L4_FRAG,
2845 [67] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2846 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2847 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2848 RTE_PTYPE_INNER_L4_NONFRAG,
2849 [68] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2850 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2851 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2852 RTE_PTYPE_INNER_L4_UDP,
2854 [70] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2855 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2856 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2857 RTE_PTYPE_INNER_L4_TCP,
2858 [71] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2859 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2860 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2861 RTE_PTYPE_INNER_L4_SCTP,
2862 [72] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2863 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2864 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2865 RTE_PTYPE_INNER_L4_ICMP,
2866 /* [73] - [87] reserved */
2868 /* Non tunneled IPv6 */
2869 [88] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2871 [89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2872 RTE_PTYPE_L4_NONFRAG,
2873 [90] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2876 [92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2878 [93] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2880 [94] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2884 [95] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2885 RTE_PTYPE_TUNNEL_IP |
2886 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2887 RTE_PTYPE_INNER_L4_FRAG,
2888 [96] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2889 RTE_PTYPE_TUNNEL_IP |
2890 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2891 RTE_PTYPE_INNER_L4_NONFRAG,
2892 [97] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2893 RTE_PTYPE_TUNNEL_IP |
2894 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2895 RTE_PTYPE_INNER_L4_UDP,
2897 [99] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2898 RTE_PTYPE_TUNNEL_IP |
2899 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2900 RTE_PTYPE_INNER_L4_TCP,
2901 [100] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2902 RTE_PTYPE_TUNNEL_IP |
2903 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2904 RTE_PTYPE_INNER_L4_SCTP,
2905 [101] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2906 RTE_PTYPE_TUNNEL_IP |
2907 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2908 RTE_PTYPE_INNER_L4_ICMP,
2911 [102] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2912 RTE_PTYPE_TUNNEL_IP |
2913 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2914 RTE_PTYPE_INNER_L4_FRAG,
2915 [103] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2916 RTE_PTYPE_TUNNEL_IP |
2917 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2918 RTE_PTYPE_INNER_L4_NONFRAG,
2919 [104] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2920 RTE_PTYPE_TUNNEL_IP |
2921 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2922 RTE_PTYPE_INNER_L4_UDP,
2923 /* [105] reserved */
2924 [106] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2925 RTE_PTYPE_TUNNEL_IP |
2926 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2927 RTE_PTYPE_INNER_L4_TCP,
2928 [107] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2929 RTE_PTYPE_TUNNEL_IP |
2930 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2931 RTE_PTYPE_INNER_L4_SCTP,
2932 [108] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2933 RTE_PTYPE_TUNNEL_IP |
2934 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2935 RTE_PTYPE_INNER_L4_ICMP,
2937 /* IPv6 --> GRE/Teredo/VXLAN */
2938 [109] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2939 RTE_PTYPE_TUNNEL_GRENAT,
2941 /* IPv6 --> GRE/Teredo/VXLAN --> IPv4 */
2942 [110] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2943 RTE_PTYPE_TUNNEL_GRENAT |
2944 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2945 RTE_PTYPE_INNER_L4_FRAG,
2946 [111] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2947 RTE_PTYPE_TUNNEL_GRENAT |
2948 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2949 RTE_PTYPE_INNER_L4_NONFRAG,
2950 [112] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2951 RTE_PTYPE_TUNNEL_GRENAT |
2952 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2953 RTE_PTYPE_INNER_L4_UDP,
2954 /* [113] reserved */
2955 [114] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2956 RTE_PTYPE_TUNNEL_GRENAT |
2957 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2958 RTE_PTYPE_INNER_L4_TCP,
2959 [115] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2960 RTE_PTYPE_TUNNEL_GRENAT |
2961 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2962 RTE_PTYPE_INNER_L4_SCTP,
2963 [116] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2964 RTE_PTYPE_TUNNEL_GRENAT |
2965 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2966 RTE_PTYPE_INNER_L4_ICMP,
2968 /* IPv6 --> GRE/Teredo/VXLAN --> IPv6 */
2969 [117] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2970 RTE_PTYPE_TUNNEL_GRENAT |
2971 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2972 RTE_PTYPE_INNER_L4_FRAG,
2973 [118] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2974 RTE_PTYPE_TUNNEL_GRENAT |
2975 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2976 RTE_PTYPE_INNER_L4_NONFRAG,
2977 [119] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2978 RTE_PTYPE_TUNNEL_GRENAT |
2979 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2980 RTE_PTYPE_INNER_L4_UDP,
2981 /* [120] reserved */
2982 [121] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2983 RTE_PTYPE_TUNNEL_GRENAT |
2984 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2985 RTE_PTYPE_INNER_L4_TCP,
2986 [122] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2987 RTE_PTYPE_TUNNEL_GRENAT |
2988 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2989 RTE_PTYPE_INNER_L4_SCTP,
2990 [123] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2991 RTE_PTYPE_TUNNEL_GRENAT |
2992 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2993 RTE_PTYPE_INNER_L4_ICMP,
2995 /* IPv6 --> GRE/Teredo/VXLAN --> MAC */
2996 [124] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2997 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
2999 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
3000 [125] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3001 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3002 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3003 RTE_PTYPE_INNER_L4_FRAG,
3004 [126] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3005 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3006 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3007 RTE_PTYPE_INNER_L4_NONFRAG,
3008 [127] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3009 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3010 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3011 RTE_PTYPE_INNER_L4_UDP,
3012 /* [128] reserved */
3013 [129] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3014 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3015 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3016 RTE_PTYPE_INNER_L4_TCP,
3017 [130] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3018 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3019 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3020 RTE_PTYPE_INNER_L4_SCTP,
3021 [131] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3022 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3023 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3024 RTE_PTYPE_INNER_L4_ICMP,
3026 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
3027 [132] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3028 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3029 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3030 RTE_PTYPE_INNER_L4_FRAG,
3031 [133] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3032 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3033 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3034 RTE_PTYPE_INNER_L4_NONFRAG,
3035 [134] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3036 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3037 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3038 RTE_PTYPE_INNER_L4_UDP,
3039 /* [135] reserved */
3040 [136] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3041 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3042 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3043 RTE_PTYPE_INNER_L4_TCP,
3044 [137] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3045 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3046 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3047 RTE_PTYPE_INNER_L4_SCTP,
3048 [138] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3049 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3050 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3051 RTE_PTYPE_INNER_L4_ICMP,
3052 /* [139] - [299] reserved */
3055 [300] = RTE_PTYPE_L2_ETHER_PPPOE,
3056 [301] = RTE_PTYPE_L2_ETHER_PPPOE,
3058 /* PPPoE --> IPv4 */
3059 [302] = RTE_PTYPE_L2_ETHER_PPPOE |
3060 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3062 [303] = RTE_PTYPE_L2_ETHER_PPPOE |
3063 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3064 RTE_PTYPE_L4_NONFRAG,
3065 [304] = RTE_PTYPE_L2_ETHER_PPPOE |
3066 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3068 [305] = RTE_PTYPE_L2_ETHER_PPPOE |
3069 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3071 [306] = RTE_PTYPE_L2_ETHER_PPPOE |
3072 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3074 [307] = RTE_PTYPE_L2_ETHER_PPPOE |
3075 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3078 /* PPPoE --> IPv6 */
3079 [308] = RTE_PTYPE_L2_ETHER_PPPOE |
3080 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3082 [309] = RTE_PTYPE_L2_ETHER_PPPOE |
3083 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3084 RTE_PTYPE_L4_NONFRAG,
3085 [310] = RTE_PTYPE_L2_ETHER_PPPOE |
3086 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3088 [311] = RTE_PTYPE_L2_ETHER_PPPOE |
3089 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3091 [312] = RTE_PTYPE_L2_ETHER_PPPOE |
3092 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3094 [313] = RTE_PTYPE_L2_ETHER_PPPOE |
3095 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3097 /* [314] - [324] reserved */
3099 /* IPv4/IPv6 --> GTPC/GTPU */
3100 [325] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3101 RTE_PTYPE_TUNNEL_GTPC,
3102 [326] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3103 RTE_PTYPE_TUNNEL_GTPC,
3104 [327] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3105 RTE_PTYPE_TUNNEL_GTPC,
3106 [328] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3107 RTE_PTYPE_TUNNEL_GTPC,
3108 [329] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3109 RTE_PTYPE_TUNNEL_GTPU,
3110 [330] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3111 RTE_PTYPE_TUNNEL_GTPU,
3113 /* IPv4 --> GTPU --> IPv4 */
3114 [331] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3115 RTE_PTYPE_TUNNEL_GTPU |
3116 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3117 RTE_PTYPE_INNER_L4_FRAG,
3118 [332] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3119 RTE_PTYPE_TUNNEL_GTPU |
3120 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3121 RTE_PTYPE_INNER_L4_NONFRAG,
3122 [333] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3123 RTE_PTYPE_TUNNEL_GTPU |
3124 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3125 RTE_PTYPE_INNER_L4_UDP,
3126 [334] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3127 RTE_PTYPE_TUNNEL_GTPU |
3128 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3129 RTE_PTYPE_INNER_L4_TCP,
3130 [335] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3131 RTE_PTYPE_TUNNEL_GTPU |
3132 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3133 RTE_PTYPE_INNER_L4_ICMP,
3135 /* IPv6 --> GTPU --> IPv4 */
3136 [336] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3137 RTE_PTYPE_TUNNEL_GTPU |
3138 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3139 RTE_PTYPE_INNER_L4_FRAG,
3140 [337] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3141 RTE_PTYPE_TUNNEL_GTPU |
3142 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3143 RTE_PTYPE_INNER_L4_NONFRAG,
3144 [338] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3145 RTE_PTYPE_TUNNEL_GTPU |
3146 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3147 RTE_PTYPE_INNER_L4_UDP,
3148 [339] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3149 RTE_PTYPE_TUNNEL_GTPU |
3150 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3151 RTE_PTYPE_INNER_L4_TCP,
3152 [340] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3153 RTE_PTYPE_TUNNEL_GTPU |
3154 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3155 RTE_PTYPE_INNER_L4_ICMP,
3157 /* IPv4 --> GTPU --> IPv6 */
3158 [341] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3159 RTE_PTYPE_TUNNEL_GTPU |
3160 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3161 RTE_PTYPE_INNER_L4_FRAG,
3162 [342] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3163 RTE_PTYPE_TUNNEL_GTPU |
3164 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3165 RTE_PTYPE_INNER_L4_NONFRAG,
3166 [343] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3167 RTE_PTYPE_TUNNEL_GTPU |
3168 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3169 RTE_PTYPE_INNER_L4_UDP,
3170 [344] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3171 RTE_PTYPE_TUNNEL_GTPU |
3172 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3173 RTE_PTYPE_INNER_L4_TCP,
3174 [345] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3175 RTE_PTYPE_TUNNEL_GTPU |
3176 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3177 RTE_PTYPE_INNER_L4_ICMP,
3179 /* IPv6 --> GTPU --> IPv6 */
3180 [346] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3181 RTE_PTYPE_TUNNEL_GTPU |
3182 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3183 RTE_PTYPE_INNER_L4_FRAG,
3184 [347] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3185 RTE_PTYPE_TUNNEL_GTPU |
3186 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3187 RTE_PTYPE_INNER_L4_NONFRAG,
3188 [348] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3189 RTE_PTYPE_TUNNEL_GTPU |
3190 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3191 RTE_PTYPE_INNER_L4_UDP,
3192 [349] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3193 RTE_PTYPE_TUNNEL_GTPU |
3194 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3195 RTE_PTYPE_INNER_L4_TCP,
3196 [350] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3197 RTE_PTYPE_TUNNEL_GTPU |
3198 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3199 RTE_PTYPE_INNER_L4_ICMP,
3201 /* IPv4 --> UDP ECPRI */
3202 [372] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3204 [373] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3206 [374] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3208 [375] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3210 [376] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3212 [377] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3214 [378] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3216 [379] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3218 [380] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3220 [381] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3223 /* IPV6 --> UDP ECPRI */
3224 [382] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3226 [383] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3228 [384] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3230 [385] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3232 [386] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3234 [387] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3236 [388] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3238 [389] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3240 [390] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3242 [391] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3244 /* All others reserved */