drivers/net/iavf/iavf_rxtx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2017 Intel Corporation
   3  */
   4
   5 #include <stdio.h>
   6 #include <stdlib.h>
   7 #include <string.h>
   8 #include <errno.h>
   9 #include <stdint.h>
  10 #include <stdarg.h>
  11 #include <unistd.h>
  12 #include <inttypes.h>
  13 #include <sys/queue.h>
  14
  15 #include <rte_string_fns.h>
  16 #include <rte_memzone.h>
  17 #include <rte_mbuf.h>
  18 #include <rte_malloc.h>
  19 #include <rte_ether.h>
  20 #include <rte_ethdev_driver.h>
  21 #include <rte_tcp.h>
  22 #include <rte_sctp.h>
  23 #include <rte_udp.h>
  24 #include <rte_ip.h>
  25 #include <rte_net.h>
  26
  27 #include "iavf_log.h"
  28 #include "base/iavf_prototype.h"
  29 #include "base/iavf_type.h"
  30 #include "iavf.h"
  31 #include "iavf_rxtx.h"
  32
  33 static inline int
  34 check_rx_thresh(uint16_t nb_desc, uint16_t thresh)
  35 {
  36         /* The following constraints must be satisfied:
  37          *   thresh < rxq->nb_rx_desc
  38          */
  39         if (thresh >= nb_desc) {
  40                 PMD_INIT_LOG(ERR, "rx_free_thresh (%u) must be less than %u",
  41                              thresh, nb_desc);
  42                 return -EINVAL;
  43         }
  44         return 0;
  45 }
  46
  47 static inline int
  48 check_tx_thresh(uint16_t nb_desc, uint16_t tx_rs_thresh,
  49                 uint16_t tx_free_thresh)
  50 {
  51         /* TX descriptors will have their RS bit set after tx_rs_thresh
  52          * descriptors have been used. The TX descriptor ring will be cleaned
  53          * after tx_free_thresh descriptors are used or if the number of
  54          * descriptors required to transmit a packet is greater than the
  55          * number of free TX descriptors.
  56          *
  57          * The following constraints must be satisfied:
  58          *  - tx_rs_thresh must be less than the size of the ring minus 2.
  59          *  - tx_free_thresh must be less than the size of the ring minus 3.
  60          *  - tx_rs_thresh must be less than or equal to tx_free_thresh.
  61          *  - tx_rs_thresh must be a divisor of the ring size.
  62          *
  63          * One descriptor in the TX ring is used as a sentinel to avoid a H/W
  64          * race condition, hence the maximum threshold constraints. When set
  65          * to zero use default values.
  66          */
  67         if (tx_rs_thresh >= (nb_desc - 2)) {
  68                 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be less than the "
  69                              "number of TX descriptors (%u) minus 2",
  70                              tx_rs_thresh, nb_desc);
  71                 return -EINVAL;
  72         }
  73         if (tx_free_thresh >= (nb_desc - 3)) {
  74                 PMD_INIT_LOG(ERR, "tx_free_thresh (%u) must be less than the "
  75                              "number of TX descriptors (%u) minus 3.",
  76                              tx_free_thresh, nb_desc);
  77                 return -EINVAL;
  78         }
  79         if (tx_rs_thresh > tx_free_thresh) {
  80                 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be less than or "
  81                              "equal to tx_free_thresh (%u).",
  82                              tx_rs_thresh, tx_free_thresh);
  83                 return -EINVAL;
  84         }
  85         if ((nb_desc % tx_rs_thresh) != 0) {
  86                 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be a divisor of the "
  87                              "number of TX descriptors (%u).",
  88                              tx_rs_thresh, nb_desc);
  89                 return -EINVAL;
  90         }
  91
  92         return 0;
  93 }
  94
  95 #ifdef RTE_LIBRTE_IAVF_INC_VECTOR
  96 static inline bool
  97 check_rx_vec_allow(struct iavf_rx_queue *rxq)
  98 {
  99         if (rxq->rx_free_thresh >= IAVF_VPMD_RX_MAX_BURST &&
 100             rxq->nb_rx_desc % rxq->rx_free_thresh == 0) {
 101                 PMD_INIT_LOG(DEBUG, "Vector Rx can be enabled on this rxq.");
 102                 return TRUE;
 103         }
 104
 105         PMD_INIT_LOG(DEBUG, "Vector Rx cannot be enabled on this rxq.");
 106         return FALSE;
 107 }
 108
 109 static inline bool
 110 check_tx_vec_allow(struct iavf_tx_queue *txq)
 111 {
 112         if (!(txq->offloads & IAVF_NO_VECTOR_FLAGS) &&
 113             txq->rs_thresh >= IAVF_VPMD_TX_MAX_BURST &&
 114             txq->rs_thresh <= IAVF_VPMD_TX_MAX_FREE_BUF) {
 115                 PMD_INIT_LOG(DEBUG, "Vector tx can be enabled on this txq.");
 116                 return TRUE;
 117         }
 118         PMD_INIT_LOG(DEBUG, "Vector Tx cannot be enabled on this txq.");
 119         return FALSE;
 120 }
 121 #endif
 122
 123 static inline bool
 124 check_rx_bulk_allow(struct iavf_rx_queue *rxq)
 125 {
 126         int ret = TRUE;
 127
 128         if (!(rxq->rx_free_thresh >= IAVF_RX_MAX_BURST)) {
 129                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 130                              "rxq->rx_free_thresh=%d, "
 131                              "IAVF_RX_MAX_BURST=%d",
 132                              rxq->rx_free_thresh, IAVF_RX_MAX_BURST);
 133                 ret = FALSE;
 134         } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
 135                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 136                              "rxq->nb_rx_desc=%d, "
 137                              "rxq->rx_free_thresh=%d",
 138                              rxq->nb_rx_desc, rxq->rx_free_thresh);
 139                 ret = FALSE;
 140         }
 141         return ret;
 142 }
 143
 144 static inline void
 145 reset_rx_queue(struct iavf_rx_queue *rxq)
 146 {
 147         uint16_t len;
 148         uint32_t i;
 149
 150         if (!rxq)
 151                 return;
 152
 153         len = rxq->nb_rx_desc + IAVF_RX_MAX_BURST;
 154
 155         for (i = 0; i < len * sizeof(union iavf_rx_desc); i++)
 156                 ((volatile char *)rxq->rx_ring)[i] = 0;
 157
 158         memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
 159
 160         for (i = 0; i < IAVF_RX_MAX_BURST; i++)
 161                 rxq->sw_ring[rxq->nb_rx_desc + i] = &rxq->fake_mbuf;
 162
 163         /* for rx bulk */
 164         rxq->rx_nb_avail = 0;
 165         rxq->rx_next_avail = 0;
 166         rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
 167
 168         rxq->rx_tail = 0;
 169         rxq->nb_rx_hold = 0;
 170         rxq->pkt_first_seg = NULL;
 171         rxq->pkt_last_seg = NULL;
 172 }
 173
 174 static inline void
 175 reset_tx_queue(struct iavf_tx_queue *txq)
 176 {
 177         struct iavf_tx_entry *txe;
 178         uint32_t i, size;
 179         uint16_t prev;
 180
 181         if (!txq) {
 182                 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
 183                 return;
 184         }
 185
 186         txe = txq->sw_ring;
 187         size = sizeof(struct iavf_tx_desc) * txq->nb_tx_desc;
 188         for (i = 0; i < size; i++)
 189                 ((volatile char *)txq->tx_ring)[i] = 0;
 190
 191         prev = (uint16_t)(txq->nb_tx_desc - 1);
 192         for (i = 0; i < txq->nb_tx_desc; i++) {
 193                 txq->tx_ring[i].cmd_type_offset_bsz =
 194                         rte_cpu_to_le_64(IAVF_TX_DESC_DTYPE_DESC_DONE);
 195                 txe[i].mbuf =  NULL;
 196                 txe[i].last_id = i;
 197                 txe[prev].next_id = i;
 198                 prev = i;
 199         }
 200
 201         txq->tx_tail = 0;
 202         txq->nb_used = 0;
 203
 204         txq->last_desc_cleaned = txq->nb_tx_desc - 1;
 205         txq->nb_free = txq->nb_tx_desc - 1;
 206
 207         txq->next_dd = txq->rs_thresh - 1;
 208         txq->next_rs = txq->rs_thresh - 1;
 209 }
 210
 211 static int
 212 alloc_rxq_mbufs(struct iavf_rx_queue *rxq)
 213 {
 214         volatile union iavf_rx_desc *rxd;
 215         struct rte_mbuf *mbuf = NULL;
 216         uint64_t dma_addr;
 217         uint16_t i;
 218
 219         for (i = 0; i < rxq->nb_rx_desc; i++) {
 220                 mbuf = rte_mbuf_raw_alloc(rxq->mp);
 221                 if (unlikely(!mbuf)) {
 222                         PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
 223                         return -ENOMEM;
 224                 }
 225
 226                 rte_mbuf_refcnt_set(mbuf, 1);
 227                 mbuf->next = NULL;
 228                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
 229                 mbuf->nb_segs = 1;
 230                 mbuf->port = rxq->port_id;
 231
 232                 dma_addr =
 233                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
 234
 235                 rxd = &rxq->rx_ring[i];
 236                 rxd->read.pkt_addr = dma_addr;
 237                 rxd->read.hdr_addr = 0;
 238 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
 239                 rxd->read.rsvd1 = 0;
 240                 rxd->read.rsvd2 = 0;
 241 #endif
 242
 243                 rxq->sw_ring[i] = mbuf;
 244         }
 245
 246         return 0;
 247 }
 248
 249 static inline void
 250 release_rxq_mbufs(struct iavf_rx_queue *rxq)
 251 {
 252         uint16_t i;
 253
 254         if (!rxq->sw_ring)
 255                 return;
 256
 257         for (i = 0; i < rxq->nb_rx_desc; i++) {
 258                 if (rxq->sw_ring[i]) {
 259                         rte_pktmbuf_free_seg(rxq->sw_ring[i]);
 260                         rxq->sw_ring[i] = NULL;
 261                 }
 262         }
 263
 264         /* for rx bulk */
 265         if (rxq->rx_nb_avail == 0)
 266                 return;
 267         for (i = 0; i < rxq->rx_nb_avail; i++) {
 268                 struct rte_mbuf *mbuf;
 269
 270                 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
 271                 rte_pktmbuf_free_seg(mbuf);
 272         }
 273         rxq->rx_nb_avail = 0;
 274 }
 275
 276 static inline void
 277 release_txq_mbufs(struct iavf_tx_queue *txq)
 278 {
 279         uint16_t i;
 280
 281         if (!txq || !txq->sw_ring) {
 282                 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
 283                 return;
 284         }
 285
 286         for (i = 0; i < txq->nb_tx_desc; i++) {
 287                 if (txq->sw_ring[i].mbuf) {
 288                         rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
 289                         txq->sw_ring[i].mbuf = NULL;
 290                 }
 291         }
 292 }
 293
 294 static const struct iavf_rxq_ops def_rxq_ops = {
 295         .release_mbufs = release_rxq_mbufs,
 296 };
 297
 298 static const struct iavf_txq_ops def_txq_ops = {
 299         .release_mbufs = release_txq_mbufs,
 300 };
 301
 302 int
 303 iavf_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 304                        uint16_t nb_desc, unsigned int socket_id,
 305                        const struct rte_eth_rxconf *rx_conf,
 306                        struct rte_mempool *mp)
 307 {
 308         struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 309         struct iavf_adapter *ad =
 310                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 311         struct iavf_rx_queue *rxq;
 312         const struct rte_memzone *mz;
 313         uint32_t ring_size;
 314         uint16_t len;
 315         uint16_t rx_free_thresh;
 316
 317         PMD_INIT_FUNC_TRACE();
 318
 319         if (nb_desc % IAVF_ALIGN_RING_DESC != 0 ||
 320             nb_desc > IAVF_MAX_RING_DESC ||
 321             nb_desc < IAVF_MIN_RING_DESC) {
 322                 PMD_INIT_LOG(ERR, "Number (%u) of receive descriptors is "
 323                              "invalid", nb_desc);
 324                 return -EINVAL;
 325         }
 326
 327         /* Check free threshold */
 328         rx_free_thresh = (rx_conf->rx_free_thresh == 0) ?
 329                          IAVF_DEFAULT_RX_FREE_THRESH :
 330                          rx_conf->rx_free_thresh;
 331         if (check_rx_thresh(nb_desc, rx_free_thresh) != 0)
 332                 return -EINVAL;
 333
 334         /* Free memory if needed */
 335         if (dev->data->rx_queues[queue_idx]) {
 336                 iavf_dev_rx_queue_release(dev->data->rx_queues[queue_idx]);
 337                 dev->data->rx_queues[queue_idx] = NULL;
 338         }
 339
 340         /* Allocate the rx queue data structure */
 341         rxq = rte_zmalloc_socket("iavf rxq",
 342                                  sizeof(struct iavf_rx_queue),
 343                                  RTE_CACHE_LINE_SIZE,
 344                                  socket_id);
 345         if (!rxq) {
 346                 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
 347                              "rx queue data structure");
 348                 return -ENOMEM;
 349         }
 350
 351         rxq->mp = mp;
 352         rxq->nb_rx_desc = nb_desc;
 353         rxq->rx_free_thresh = rx_free_thresh;
 354         rxq->queue_id = queue_idx;
 355         rxq->port_id = dev->data->port_id;
 356         rxq->crc_len = 0; /* crc stripping by default */
 357         rxq->rx_deferred_start = rx_conf->rx_deferred_start;
 358         rxq->rx_hdr_len = 0;
 359
 360         len = rte_pktmbuf_data_room_size(rxq->mp) - RTE_PKTMBUF_HEADROOM;
 361         rxq->rx_buf_len = RTE_ALIGN(len, (1 << IAVF_RXQ_CTX_DBUFF_SHIFT));
 362
 363         /* Allocate the software ring. */
 364         len = nb_desc + IAVF_RX_MAX_BURST;
 365         rxq->sw_ring =
 366                 rte_zmalloc_socket("iavf rx sw ring",
 367                                    sizeof(struct rte_mbuf *) * len,
 368                                    RTE_CACHE_LINE_SIZE,
 369                                    socket_id);
 370         if (!rxq->sw_ring) {
 371                 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW ring");
 372                 rte_free(rxq);
 373                 return -ENOMEM;
 374         }
 375
 376         /* Allocate the maximun number of RX ring hardware descriptor with
 377          * a liitle more to support bulk allocate.
 378          */
 379         len = IAVF_MAX_RING_DESC + IAVF_RX_MAX_BURST;
 380         ring_size = RTE_ALIGN(len * sizeof(union iavf_rx_desc),
 381                               IAVF_DMA_MEM_ALIGN);
 382         mz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
 383                                       ring_size, IAVF_RING_BASE_ALIGN,
 384                                       socket_id);
 385         if (!mz) {
 386                 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for RX");
 387                 rte_free(rxq->sw_ring);
 388                 rte_free(rxq);
 389                 return -ENOMEM;
 390         }
 391         /* Zero all the descriptors in the ring. */
 392         memset(mz->addr, 0, ring_size);
 393         rxq->rx_ring_phys_addr = mz->iova;
 394         rxq->rx_ring = (union iavf_rx_desc *)mz->addr;
 395
 396         rxq->mz = mz;
 397         reset_rx_queue(rxq);
 398         rxq->q_set = TRUE;
 399         dev->data->rx_queues[queue_idx] = rxq;
 400         rxq->qrx_tail = hw->hw_addr + IAVF_QRX_TAIL1(rxq->queue_id);
 401         rxq->ops = &def_rxq_ops;
 402
 403         if (check_rx_bulk_allow(rxq) == TRUE) {
 404                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
 405                              "satisfied. Rx Burst Bulk Alloc function will be "
 406                              "used on port=%d, queue=%d.",
 407                              rxq->port_id, rxq->queue_id);
 408         } else {
 409                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
 410                              "not satisfied, Scattered Rx is requested "
 411                              "on port=%d, queue=%d.",
 412                              rxq->port_id, rxq->queue_id);
 413                 ad->rx_bulk_alloc_allowed = false;
 414         }
 415
 416 #ifdef RTE_LIBRTE_IAVF_INC_VECTOR
 417         if (check_rx_vec_allow(rxq) == FALSE)
 418                 ad->rx_vec_allowed = false;
 419 #endif
 420         return 0;
 421 }
 422
 423 int
 424 iavf_dev_tx_queue_setup(struct rte_eth_dev *dev,
 425                        uint16_t queue_idx,
 426                        uint16_t nb_desc,
 427                        unsigned int socket_id,
 428                        const struct rte_eth_txconf *tx_conf)
 429 {
 430         struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 431         struct iavf_tx_queue *txq;
 432         const struct rte_memzone *mz;
 433         uint32_t ring_size;
 434         uint16_t tx_rs_thresh, tx_free_thresh;
 435         uint64_t offloads;
 436
 437         PMD_INIT_FUNC_TRACE();
 438
 439         offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
 440
 441         if (nb_desc % IAVF_ALIGN_RING_DESC != 0 ||
 442             nb_desc > IAVF_MAX_RING_DESC ||
 443             nb_desc < IAVF_MIN_RING_DESC) {
 444                 PMD_INIT_LOG(ERR, "Number (%u) of transmit descriptors is "
 445                             "invalid", nb_desc);
 446                 return -EINVAL;
 447         }
 448
 449         tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
 450                 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
 451         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
 452                 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
 453         check_tx_thresh(nb_desc, tx_rs_thresh, tx_rs_thresh);
 454
 455         /* Free memory if needed. */
 456         if (dev->data->tx_queues[queue_idx]) {
 457                 iavf_dev_tx_queue_release(dev->data->tx_queues[queue_idx]);
 458                 dev->data->tx_queues[queue_idx] = NULL;
 459         }
 460
 461         /* Allocate the TX queue data structure. */
 462         txq = rte_zmalloc_socket("iavf txq",
 463                                  sizeof(struct iavf_tx_queue),
 464                                  RTE_CACHE_LINE_SIZE,
 465                                  socket_id);
 466         if (!txq) {
 467                 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
 468                              "tx queue structure");
 469                 return -ENOMEM;
 470         }
 471
 472         txq->nb_tx_desc = nb_desc;
 473         txq->rs_thresh = tx_rs_thresh;
 474         txq->free_thresh = tx_free_thresh;
 475         txq->queue_id = queue_idx;
 476         txq->port_id = dev->data->port_id;
 477         txq->offloads = offloads;
 478         txq->tx_deferred_start = tx_conf->tx_deferred_start;
 479
 480         /* Allocate software ring */
 481         txq->sw_ring =
 482                 rte_zmalloc_socket("iavf tx sw ring",
 483                                    sizeof(struct iavf_tx_entry) * nb_desc,
 484                                    RTE_CACHE_LINE_SIZE,
 485                                    socket_id);
 486         if (!txq->sw_ring) {
 487                 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW TX ring");
 488                 rte_free(txq);
 489                 return -ENOMEM;
 490         }
 491
 492         /* Allocate TX hardware ring descriptors. */
 493         ring_size = sizeof(struct iavf_tx_desc) * IAVF_MAX_RING_DESC;
 494         ring_size = RTE_ALIGN(ring_size, IAVF_DMA_MEM_ALIGN);
 495         mz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
 496                                       ring_size, IAVF_RING_BASE_ALIGN,
 497                                       socket_id);
 498         if (!mz) {
 499                 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for TX");
 500                 rte_free(txq->sw_ring);
 501                 rte_free(txq);
 502                 return -ENOMEM;
 503         }
 504         txq->tx_ring_phys_addr = mz->iova;
 505         txq->tx_ring = (struct iavf_tx_desc *)mz->addr;
 506
 507         txq->mz = mz;
 508         reset_tx_queue(txq);
 509         txq->q_set = TRUE;
 510         dev->data->tx_queues[queue_idx] = txq;
 511         txq->qtx_tail = hw->hw_addr + IAVF_QTX_TAIL1(queue_idx);
 512         txq->ops = &def_txq_ops;
 513
 514 #ifdef RTE_LIBRTE_IAVF_INC_VECTOR
 515         if (check_tx_vec_allow(txq) == FALSE) {
 516                 struct iavf_adapter *ad =
 517                         IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 518                 ad->tx_vec_allowed = false;
 519         }
 520 #endif
 521
 522         return 0;
 523 }
 524
 525 int
 526 iavf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 527 {
 528         struct iavf_adapter *adapter =
 529                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 530         struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 531         struct iavf_rx_queue *rxq;
 532         int err = 0;
 533
 534         PMD_DRV_FUNC_TRACE();
 535
 536         if (rx_queue_id >= dev->data->nb_rx_queues)
 537                 return -EINVAL;
 538
 539         rxq = dev->data->rx_queues[rx_queue_id];
 540
 541         err = alloc_rxq_mbufs(rxq);
 542         if (err) {
 543                 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
 544                 return err;
 545         }
 546
 547         rte_wmb();
 548
 549         /* Init the RX tail register. */
 550         IAVF_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 551         IAVF_WRITE_FLUSH(hw);
 552
 553         /* Ready to switch the queue on */
 554         err = iavf_switch_queue(adapter, rx_queue_id, TRUE, TRUE);
 555         if (err)
 556                 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
 557                             rx_queue_id);
 558         else
 559                 dev->data->rx_queue_state[rx_queue_id] =
 560                         RTE_ETH_QUEUE_STATE_STARTED;
 561
 562         return err;
 563 }
 564
 565 int
 566 iavf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 567 {
 568         struct iavf_adapter *adapter =
 569                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 570         struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 571         struct iavf_tx_queue *txq;
 572         int err = 0;
 573
 574         PMD_DRV_FUNC_TRACE();
 575
 576         if (tx_queue_id >= dev->data->nb_tx_queues)
 577                 return -EINVAL;
 578
 579         txq = dev->data->tx_queues[tx_queue_id];
 580
 581         /* Init the RX tail register. */
 582         IAVF_PCI_REG_WRITE(txq->qtx_tail, 0);
 583         IAVF_WRITE_FLUSH(hw);
 584
 585         /* Ready to switch the queue on */
 586         err = iavf_switch_queue(adapter, tx_queue_id, FALSE, TRUE);
 587
 588         if (err)
 589                 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
 590                             tx_queue_id);
 591         else
 592                 dev->data->tx_queue_state[tx_queue_id] =
 593                         RTE_ETH_QUEUE_STATE_STARTED;
 594
 595         return err;
 596 }
 597
 598 int
 599 iavf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 600 {
 601         struct iavf_adapter *adapter =
 602                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 603         struct iavf_rx_queue *rxq;
 604         int err;
 605
 606         PMD_DRV_FUNC_TRACE();
 607
 608         if (rx_queue_id >= dev->data->nb_rx_queues)
 609                 return -EINVAL;
 610
 611         err = iavf_switch_queue(adapter, rx_queue_id, TRUE, FALSE);
 612         if (err) {
 613                 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
 614                             rx_queue_id);
 615                 return err;
 616         }
 617
 618         rxq = dev->data->rx_queues[rx_queue_id];
 619         rxq->ops->release_mbufs(rxq);
 620         reset_rx_queue(rxq);
 621         dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 622
 623         return 0;
 624 }
 625
 626 int
 627 iavf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 628 {
 629         struct iavf_adapter *adapter =
 630                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 631         struct iavf_tx_queue *txq;
 632         int err;
 633
 634         PMD_DRV_FUNC_TRACE();
 635
 636         if (tx_queue_id >= dev->data->nb_tx_queues)
 637                 return -EINVAL;
 638
 639         err = iavf_switch_queue(adapter, tx_queue_id, FALSE, FALSE);
 640         if (err) {
 641                 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u off",
 642                             tx_queue_id);
 643                 return err;
 644         }
 645
 646         txq = dev->data->tx_queues[tx_queue_id];
 647         txq->ops->release_mbufs(txq);
 648         reset_tx_queue(txq);
 649         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 650
 651         return 0;
 652 }
 653
 654 void
 655 iavf_dev_rx_queue_release(void *rxq)
 656 {
 657         struct iavf_rx_queue *q = (struct iavf_rx_queue *)rxq;
 658
 659         if (!q)
 660                 return;
 661
 662         q->ops->release_mbufs(q);
 663         rte_free(q->sw_ring);
 664         rte_memzone_free(q->mz);
 665         rte_free(q);
 666 }
 667
 668 void
 669 iavf_dev_tx_queue_release(void *txq)
 670 {
 671         struct iavf_tx_queue *q = (struct iavf_tx_queue *)txq;
 672
 673         if (!q)
 674                 return;
 675
 676         q->ops->release_mbufs(q);
 677         rte_free(q->sw_ring);
 678         rte_memzone_free(q->mz);
 679         rte_free(q);
 680 }
 681
 682 void
 683 iavf_stop_queues(struct rte_eth_dev *dev)
 684 {
 685         struct iavf_adapter *adapter =
 686                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 687         struct iavf_rx_queue *rxq;
 688         struct iavf_tx_queue *txq;
 689         int ret, i;
 690
 691         /* Stop All queues */
 692         ret = iavf_disable_queues(adapter);
 693         if (ret)
 694                 PMD_DRV_LOG(WARNING, "Fail to stop queues");
 695
 696         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 697                 txq = dev->data->tx_queues[i];
 698                 if (!txq)
 699                         continue;
 700                 txq->ops->release_mbufs(txq);
 701                 reset_tx_queue(txq);
 702                 dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED;
 703         }
 704         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 705                 rxq = dev->data->rx_queues[i];
 706                 if (!rxq)
 707                         continue;
 708                 rxq->ops->release_mbufs(rxq);
 709                 reset_rx_queue(rxq);
 710                 dev->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED;
 711         }
 712 }
 713
 714 static inline void
 715 iavf_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union iavf_rx_desc *rxdp)
 716 {
 717         if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
 718                 (1 << IAVF_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
 719                 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
 720                 mb->vlan_tci =
 721                         rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
 722         } else {
 723                 mb->vlan_tci = 0;
 724         }
 725 }
 726
 727 /* Translate the rx descriptor status and error fields to pkt flags */
 728 static inline uint64_t
 729 iavf_rxd_to_pkt_flags(uint64_t qword)
 730 {
 731         uint64_t flags;
 732         uint64_t error_bits = (qword >> IAVF_RXD_QW1_ERROR_SHIFT);
 733
 734 #define IAVF_RX_ERR_BITS 0x3f
 735
 736         /* Check if RSS_HASH */
 737         flags = (((qword >> IAVF_RX_DESC_STATUS_FLTSTAT_SHIFT) &
 738                                         IAVF_RX_DESC_FLTSTAT_RSS_HASH) ==
 739                         IAVF_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;
 740
 741         if (likely((error_bits & IAVF_RX_ERR_BITS) == 0)) {
 742                 flags |= (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD);
 743                 return flags;
 744         }
 745
 746         if (unlikely(error_bits & (1 << IAVF_RX_DESC_ERROR_IPE_SHIFT)))
 747                 flags |= PKT_RX_IP_CKSUM_BAD;
 748         else
 749                 flags |= PKT_RX_IP_CKSUM_GOOD;
 750
 751         if (unlikely(error_bits & (1 << IAVF_RX_DESC_ERROR_L4E_SHIFT)))
 752                 flags |= PKT_RX_L4_CKSUM_BAD;
 753         else
 754                 flags |= PKT_RX_L4_CKSUM_GOOD;
 755
 756         /* TODO: Oversize error bit is not processed here */
 757
 758         return flags;
 759 }
 760
 761 /* implement recv_pkts */
 762 uint16_t
 763 iavf_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 764 {
 765         volatile union iavf_rx_desc *rx_ring;
 766         volatile union iavf_rx_desc *rxdp;
 767         struct iavf_rx_queue *rxq;
 768         union iavf_rx_desc rxd;
 769         struct rte_mbuf *rxe;
 770         struct rte_eth_dev *dev;
 771         struct rte_mbuf *rxm;
 772         struct rte_mbuf *nmb;
 773         uint16_t nb_rx;
 774         uint32_t rx_status;
 775         uint64_t qword1;
 776         uint16_t rx_packet_len;
 777         uint16_t rx_id, nb_hold;
 778         uint64_t dma_addr;
 779         uint64_t pkt_flags;
 780         static const uint32_t ptype_tbl[UINT8_MAX + 1] __rte_cache_aligned = {
 781                 /* [0] reserved */
 782                 [1] = RTE_PTYPE_L2_ETHER,
 783                 /* [2] - [21] reserved */
 784                 [22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 785                         RTE_PTYPE_L4_FRAG,
 786                 [23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 787                         RTE_PTYPE_L4_NONFRAG,
 788                 [24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 789                         RTE_PTYPE_L4_UDP,
 790                 /* [25] reserved */
 791                 [26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 792                         RTE_PTYPE_L4_TCP,
 793                 [27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 794                         RTE_PTYPE_L4_SCTP,
 795                 [28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 796                         RTE_PTYPE_L4_ICMP,
 797                 /* All others reserved */
 798         };
 799
 800         nb_rx = 0;
 801         nb_hold = 0;
 802         rxq = rx_queue;
 803         rx_id = rxq->rx_tail;
 804         rx_ring = rxq->rx_ring;
 805
 806         while (nb_rx < nb_pkts) {
 807                 rxdp = &rx_ring[rx_id];
 808                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 809                 rx_status = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
 810                             IAVF_RXD_QW1_STATUS_SHIFT;
 811
 812                 /* Check the DD bit first */
 813                 if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)))
 814                         break;
 815                 IAVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
 816
 817                 nmb = rte_mbuf_raw_alloc(rxq->mp);
 818                 if (unlikely(!nmb)) {
 819                         dev = &rte_eth_devices[rxq->port_id];
 820                         dev->data->rx_mbuf_alloc_failed++;
 821                         PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
 822                                    "queue_id=%u", rxq->port_id, rxq->queue_id);
 823                         break;
 824                 }
 825
 826                 rxd = *rxdp;
 827                 nb_hold++;
 828                 rxe = rxq->sw_ring[rx_id];
 829                 rx_id++;
 830                 if (unlikely(rx_id == rxq->nb_rx_desc))
 831                         rx_id = 0;
 832
 833                 /* Prefetch next mbuf */
 834                 rte_prefetch0(rxq->sw_ring[rx_id]);
 835
 836                 /* When next RX descriptor is on a cache line boundary,
 837                  * prefetch the next 4 RX descriptors and next 8 pointers
 838                  * to mbufs.
 839                  */
 840                 if ((rx_id & 0x3) == 0) {
 841                         rte_prefetch0(&rx_ring[rx_id]);
 842                         rte_prefetch0(rxq->sw_ring[rx_id]);
 843                 }
 844                 rxm = rxe;
 845                 rxe = nmb;
 846                 dma_addr =
 847                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
 848                 rxdp->read.hdr_addr = 0;
 849                 rxdp->read.pkt_addr = dma_addr;
 850
 851                 rx_packet_len = ((qword1 & IAVF_RXD_QW1_LENGTH_PBUF_MASK) >>
 852                                 IAVF_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
 853
 854                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
 855                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
 856                 rxm->nb_segs = 1;
 857                 rxm->next = NULL;
 858                 rxm->pkt_len = rx_packet_len;
 859                 rxm->data_len = rx_packet_len;
 860                 rxm->port = rxq->port_id;
 861                 rxm->ol_flags = 0;
 862                 iavf_rxd_to_vlan_tci(rxm, &rxd);
 863                 pkt_flags = iavf_rxd_to_pkt_flags(qword1);
 864                 rxm->packet_type =
 865                         ptype_tbl[(uint8_t)((qword1 &
 866                         IAVF_RXD_QW1_PTYPE_MASK) >> IAVF_RXD_QW1_PTYPE_SHIFT)];
 867
 868                 if (pkt_flags & PKT_RX_RSS_HASH)
 869                         rxm->hash.rss =
 870                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
 871
 872                 rxm->ol_flags |= pkt_flags;
 873
 874                 rx_pkts[nb_rx++] = rxm;
 875         }
 876         rxq->rx_tail = rx_id;
 877
 878         /* If the number of free RX descriptors is greater than the RX free
 879          * threshold of the queue, advance the receive tail register of queue.
 880          * Update that register with the value of the last processed RX
 881          * descriptor minus 1.
 882          */
 883         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
 884         if (nb_hold > rxq->rx_free_thresh) {
 885                 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
 886                            "nb_hold=%u nb_rx=%u",
 887                            rxq->port_id, rxq->queue_id,
 888                            rx_id, nb_hold, nb_rx);
 889                 rx_id = (uint16_t)((rx_id == 0) ?
 890                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
 891                 IAVF_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
 892                 nb_hold = 0;
 893         }
 894         rxq->nb_rx_hold = nb_hold;
 895
 896         return nb_rx;
 897 }
 898
 899 /* implement recv_scattered_pkts  */
 900 uint16_t
 901 iavf_recv_scattered_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
 902                         uint16_t nb_pkts)
 903 {
 904         struct iavf_rx_queue *rxq = rx_queue;
 905         union iavf_rx_desc rxd;
 906         struct rte_mbuf *rxe;
 907         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
 908         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
 909         struct rte_mbuf *nmb, *rxm;
 910         uint16_t rx_id = rxq->rx_tail;
 911         uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
 912         struct rte_eth_dev *dev;
 913         uint32_t rx_status;
 914         uint64_t qword1;
 915         uint64_t dma_addr;
 916         uint64_t pkt_flags;
 917
 918         volatile union iavf_rx_desc *rx_ring = rxq->rx_ring;
 919         volatile union iavf_rx_desc *rxdp;
 920         static const uint32_t ptype_tbl[UINT8_MAX + 1] __rte_cache_aligned = {
 921                 /* [0] reserved */
 922                 [1] = RTE_PTYPE_L2_ETHER,
 923                 /* [2] - [21] reserved */
 924                 [22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 925                         RTE_PTYPE_L4_FRAG,
 926                 [23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 927                         RTE_PTYPE_L4_NONFRAG,
 928                 [24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 929                         RTE_PTYPE_L4_UDP,
 930                 /* [25] reserved */
 931                 [26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 932                         RTE_PTYPE_L4_TCP,
 933                 [27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 934                         RTE_PTYPE_L4_SCTP,
 935                 [28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 936                         RTE_PTYPE_L4_ICMP,
 937                 /* All others reserved */
 938         };
 939
 940         while (nb_rx < nb_pkts) {
 941                 rxdp = &rx_ring[rx_id];
 942                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 943                 rx_status = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
 944                             IAVF_RXD_QW1_STATUS_SHIFT;
 945
 946                 /* Check the DD bit */
 947                 if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)))
 948                         break;
 949                 IAVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
 950
 951                 nmb = rte_mbuf_raw_alloc(rxq->mp);
 952                 if (unlikely(!nmb)) {
 953                         PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
 954                                    "queue_id=%u", rxq->port_id, rxq->queue_id);
 955                         dev = &rte_eth_devices[rxq->port_id];
 956                         dev->data->rx_mbuf_alloc_failed++;
 957                         break;
 958                 }
 959
 960                 rxd = *rxdp;
 961                 nb_hold++;
 962                 rxe = rxq->sw_ring[rx_id];
 963                 rx_id++;
 964                 if (rx_id == rxq->nb_rx_desc)
 965                         rx_id = 0;
 966
 967                 /* Prefetch next mbuf */
 968                 rte_prefetch0(rxq->sw_ring[rx_id]);
 969
 970                 /* When next RX descriptor is on a cache line boundary,
 971                  * prefetch the next 4 RX descriptors and next 8 pointers
 972                  * to mbufs.
 973                  */
 974                 if ((rx_id & 0x3) == 0) {
 975                         rte_prefetch0(&rx_ring[rx_id]);
 976                         rte_prefetch0(rxq->sw_ring[rx_id]);
 977                 }
 978
 979                 rxm = rxe;
 980                 rxe = nmb;
 981                 dma_addr =
 982                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
 983
 984                 /* Set data buffer address and data length of the mbuf */
 985                 rxdp->read.hdr_addr = 0;
 986                 rxdp->read.pkt_addr = dma_addr;
 987                 rx_packet_len = (qword1 & IAVF_RXD_QW1_LENGTH_PBUF_MASK) >>
 988                                  IAVF_RXD_QW1_LENGTH_PBUF_SHIFT;
 989                 rxm->data_len = rx_packet_len;
 990                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
 991
 992                 /* If this is the first buffer of the received packet, set the
 993                  * pointer to the first mbuf of the packet and initialize its
 994                  * context. Otherwise, update the total length and the number
 995                  * of segments of the current scattered packet, and update the
 996                  * pointer to the last mbuf of the current packet.
 997                  */
 998                 if (!first_seg) {
 999                         first_seg = rxm;
1000                         first_seg->nb_segs = 1;
1001                         first_seg->pkt_len = rx_packet_len;
1002                 } else {
1003                         first_seg->pkt_len =
1004                                 (uint16_t)(first_seg->pkt_len +
1005                                                 rx_packet_len);
1006                         first_seg->nb_segs++;
1007                         last_seg->next = rxm;
1008                 }
1009
1010                 /* If this is not the last buffer of the received packet,
1011                  * update the pointer to the last mbuf of the current scattered
1012                  * packet and continue to parse the RX ring.
1013                  */
1014                 if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_EOF_SHIFT))) {
1015                         last_seg = rxm;
1016                         continue;
1017                 }
1018
1019                 /* This is the last buffer of the received packet. If the CRC
1020                  * is not stripped by the hardware:
1021                  *  - Subtract the CRC length from the total packet length.
1022                  *  - If the last buffer only contains the whole CRC or a part
1023                  *  of it, free the mbuf associated to the last buffer. If part
1024                  *  of the CRC is also contained in the previous mbuf, subtract
1025                  *  the length of that CRC part from the data length of the
1026                  *  previous mbuf.
1027                  */
1028                 rxm->next = NULL;
1029                 if (unlikely(rxq->crc_len > 0)) {
1030                         first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
1031                         if (rx_packet_len <= RTE_ETHER_CRC_LEN) {
1032                                 rte_pktmbuf_free_seg(rxm);
1033                                 first_seg->nb_segs--;
1034                                 last_seg->data_len =
1035                                         (uint16_t)(last_seg->data_len -
1036                                         (RTE_ETHER_CRC_LEN - rx_packet_len));
1037                                 last_seg->next = NULL;
1038                         } else
1039                                 rxm->data_len = (uint16_t)(rx_packet_len -
1040                                                         RTE_ETHER_CRC_LEN);
1041                 }
1042
1043                 first_seg->port = rxq->port_id;
1044                 first_seg->ol_flags = 0;
1045                 iavf_rxd_to_vlan_tci(first_seg, &rxd);
1046                 pkt_flags = iavf_rxd_to_pkt_flags(qword1);
1047                 first_seg->packet_type =
1048                         ptype_tbl[(uint8_t)((qword1 &
1049                         IAVF_RXD_QW1_PTYPE_MASK) >> IAVF_RXD_QW1_PTYPE_SHIFT)];
1050
1051                 if (pkt_flags & PKT_RX_RSS_HASH)
1052                         first_seg->hash.rss =
1053                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1054
1055                 first_seg->ol_flags |= pkt_flags;
1056
1057                 /* Prefetch data of first segment, if configured to do so. */
1058                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1059                                           first_seg->data_off));
1060                 rx_pkts[nb_rx++] = first_seg;
1061                 first_seg = NULL;
1062         }
1063
1064         /* Record index of the next RX descriptor to probe. */
1065         rxq->rx_tail = rx_id;
1066         rxq->pkt_first_seg = first_seg;
1067         rxq->pkt_last_seg = last_seg;
1068
1069         /* If the number of free RX descriptors is greater than the RX free
1070          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1071          * register. Update the RDT with the value of the last processed RX
1072          * descriptor minus 1, to guarantee that the RDT register is never
1073          * equal to the RDH register, which creates a "full" ring situtation
1074          * from the hardware point of view.
1075          */
1076         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1077         if (nb_hold > rxq->rx_free_thresh) {
1078                 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1079                            "nb_hold=%u nb_rx=%u",
1080                            rxq->port_id, rxq->queue_id,
1081                            rx_id, nb_hold, nb_rx);
1082                 rx_id = (uint16_t)(rx_id == 0 ?
1083                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
1084                 IAVF_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
1085                 nb_hold = 0;
1086         }
1087         rxq->nb_rx_hold = nb_hold;
1088
1089         return nb_rx;
1090 }
1091
1092 #define IAVF_LOOK_AHEAD 8
1093 static inline int
1094 iavf_rx_scan_hw_ring(struct iavf_rx_queue *rxq)
1095 {
1096         volatile union iavf_rx_desc *rxdp;
1097         struct rte_mbuf **rxep;
1098         struct rte_mbuf *mb;
1099         uint16_t pkt_len;
1100         uint64_t qword1;
1101         uint32_t rx_status;
1102         int32_t s[IAVF_LOOK_AHEAD], nb_dd;
1103         int32_t i, j, nb_rx = 0;
1104         uint64_t pkt_flags;
1105         static const uint32_t ptype_tbl[UINT8_MAX + 1] __rte_cache_aligned = {
1106                 /* [0] reserved */
1107                 [1] = RTE_PTYPE_L2_ETHER,
1108                 /* [2] - [21] reserved */
1109                 [22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1110                         RTE_PTYPE_L4_FRAG,
1111                 [23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1112                         RTE_PTYPE_L4_NONFRAG,
1113                 [24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1114                         RTE_PTYPE_L4_UDP,
1115                 /* [25] reserved */
1116                 [26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1117                         RTE_PTYPE_L4_TCP,
1118                 [27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1119                         RTE_PTYPE_L4_SCTP,
1120                 [28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1121                         RTE_PTYPE_L4_ICMP,
1122                 /* All others reserved */
1123         };
1124
1125         rxdp = &rxq->rx_ring[rxq->rx_tail];
1126         rxep = &rxq->sw_ring[rxq->rx_tail];
1127
1128         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1129         rx_status = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
1130                     IAVF_RXD_QW1_STATUS_SHIFT;
1131
1132         /* Make sure there is at least 1 packet to receive */
1133         if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)))
1134                 return 0;
1135
1136         /* Scan LOOK_AHEAD descriptors at a time to determine which
1137          * descriptors reference packets that are ready to be received.
1138          */
1139         for (i = 0; i < IAVF_RX_MAX_BURST; i += IAVF_LOOK_AHEAD,
1140              rxdp += IAVF_LOOK_AHEAD, rxep += IAVF_LOOK_AHEAD) {
1141                 /* Read desc statuses backwards to avoid race condition */
1142                 for (j = IAVF_LOOK_AHEAD - 1; j >= 0; j--) {
1143                         qword1 = rte_le_to_cpu_64(
1144                                 rxdp[j].wb.qword1.status_error_len);
1145                         s[j] = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
1146                                IAVF_RXD_QW1_STATUS_SHIFT;
1147                 }
1148
1149                 rte_smp_rmb();
1150
1151                 /* Compute how many status bits were set */
1152                 for (j = 0, nb_dd = 0; j < IAVF_LOOK_AHEAD; j++)
1153                         nb_dd += s[j] & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT);
1154
1155                 nb_rx += nb_dd;
1156
1157                 /* Translate descriptor info to mbuf parameters */
1158                 for (j = 0; j < nb_dd; j++) {
1159                         IAVF_DUMP_RX_DESC(rxq, &rxdp[j],
1160                                          rxq->rx_tail + i * IAVF_LOOK_AHEAD + j);
1161
1162                         mb = rxep[j];
1163                         qword1 = rte_le_to_cpu_64
1164                                         (rxdp[j].wb.qword1.status_error_len);
1165                         pkt_len = ((qword1 & IAVF_RXD_QW1_LENGTH_PBUF_MASK) >>
1166                                   IAVF_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
1167                         mb->data_len = pkt_len;
1168                         mb->pkt_len = pkt_len;
1169                         mb->ol_flags = 0;
1170                         iavf_rxd_to_vlan_tci(mb, &rxdp[j]);
1171                         pkt_flags = iavf_rxd_to_pkt_flags(qword1);
1172                         mb->packet_type =
1173                                 ptype_tbl[(uint8_t)((qword1 &
1174                                 IAVF_RXD_QW1_PTYPE_MASK) >>
1175                                 IAVF_RXD_QW1_PTYPE_SHIFT)];
1176
1177                         if (pkt_flags & PKT_RX_RSS_HASH)
1178                                 mb->hash.rss = rte_le_to_cpu_32(
1179                                         rxdp[j].wb.qword0.hi_dword.rss);
1180
1181                         mb->ol_flags |= pkt_flags;
1182                 }
1183
1184                 for (j = 0; j < IAVF_LOOK_AHEAD; j++)
1185                         rxq->rx_stage[i + j] = rxep[j];
1186
1187                 if (nb_dd != IAVF_LOOK_AHEAD)
1188                         break;
1189         }
1190
1191         /* Clear software ring entries */
1192         for (i = 0; i < nb_rx; i++)
1193                 rxq->sw_ring[rxq->rx_tail + i] = NULL;
1194
1195         return nb_rx;
1196 }
1197
1198 static inline uint16_t
1199 iavf_rx_fill_from_stage(struct iavf_rx_queue *rxq,
1200                        struct rte_mbuf **rx_pkts,
1201                        uint16_t nb_pkts)
1202 {
1203         uint16_t i;
1204         struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1205
1206         nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1207
1208         for (i = 0; i < nb_pkts; i++)
1209                 rx_pkts[i] = stage[i];
1210
1211         rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1212         rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1213
1214         return nb_pkts;
1215 }
1216
1217 static inline int
1218 iavf_rx_alloc_bufs(struct iavf_rx_queue *rxq)
1219 {
1220         volatile union iavf_rx_desc *rxdp;
1221         struct rte_mbuf **rxep;
1222         struct rte_mbuf *mb;
1223         uint16_t alloc_idx, i;
1224         uint64_t dma_addr;
1225         int diag;
1226
1227         /* Allocate buffers in bulk */
1228         alloc_idx = (uint16_t)(rxq->rx_free_trigger -
1229                                 (rxq->rx_free_thresh - 1));
1230         rxep = &rxq->sw_ring[alloc_idx];
1231         diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
1232                                     rxq->rx_free_thresh);
1233         if (unlikely(diag != 0)) {
1234                 PMD_RX_LOG(ERR, "Failed to get mbufs in bulk");
1235                 return -ENOMEM;
1236         }
1237
1238         rxdp = &rxq->rx_ring[alloc_idx];
1239         for (i = 0; i < rxq->rx_free_thresh; i++) {
1240                 if (likely(i < (rxq->rx_free_thresh - 1)))
1241                         /* Prefetch next mbuf */
1242                         rte_prefetch0(rxep[i + 1]);
1243
1244                 mb = rxep[i];
1245                 rte_mbuf_refcnt_set(mb, 1);
1246                 mb->next = NULL;
1247                 mb->data_off = RTE_PKTMBUF_HEADROOM;
1248                 mb->nb_segs = 1;
1249                 mb->port = rxq->port_id;
1250                 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mb));
1251                 rxdp[i].read.hdr_addr = 0;
1252                 rxdp[i].read.pkt_addr = dma_addr;
1253         }
1254
1255         /* Update rx tail register */
1256         rte_wmb();
1257         IAVF_PCI_REG_WRITE_RELAXED(rxq->qrx_tail, rxq->rx_free_trigger);
1258
1259         rxq->rx_free_trigger =
1260                 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
1261         if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1262                 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
1263
1264         return 0;
1265 }
1266
1267 static inline uint16_t
1268 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1269 {
1270         struct iavf_rx_queue *rxq = (struct iavf_rx_queue *)rx_queue;
1271         uint16_t nb_rx = 0;
1272
1273         if (!nb_pkts)
1274                 return 0;
1275
1276         if (rxq->rx_nb_avail)
1277                 return iavf_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1278
1279         nb_rx = (uint16_t)iavf_rx_scan_hw_ring(rxq);
1280         rxq->rx_next_avail = 0;
1281         rxq->rx_nb_avail = nb_rx;
1282         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1283
1284         if (rxq->rx_tail > rxq->rx_free_trigger) {
1285                 if (iavf_rx_alloc_bufs(rxq) != 0) {
1286                         uint16_t i, j;
1287
1288                         /* TODO: count rx_mbuf_alloc_failed here */
1289
1290                         rxq->rx_nb_avail = 0;
1291                         rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1292                         for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
1293                                 rxq->sw_ring[j] = rxq->rx_stage[i];
1294
1295                         return 0;
1296                 }
1297         }
1298
1299         if (rxq->rx_tail >= rxq->nb_rx_desc)
1300                 rxq->rx_tail = 0;
1301
1302         PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u, nb_rx=%u",
1303                    rxq->port_id, rxq->queue_id,
1304                    rxq->rx_tail, nb_rx);
1305
1306         if (rxq->rx_nb_avail)
1307                 return iavf_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1308
1309         return 0;
1310 }
1311
1312 static uint16_t
1313 iavf_recv_pkts_bulk_alloc(void *rx_queue,
1314                          struct rte_mbuf **rx_pkts,
1315                          uint16_t nb_pkts)
1316 {
1317         uint16_t nb_rx = 0, n, count;
1318
1319         if (unlikely(nb_pkts == 0))
1320                 return 0;
1321
1322         if (likely(nb_pkts <= IAVF_RX_MAX_BURST))
1323                 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1324
1325         while (nb_pkts) {
1326                 n = RTE_MIN(nb_pkts, IAVF_RX_MAX_BURST);
1327                 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1328                 nb_rx = (uint16_t)(nb_rx + count);
1329                 nb_pkts = (uint16_t)(nb_pkts - count);
1330                 if (count < n)
1331                         break;
1332         }
1333
1334         return nb_rx;
1335 }
1336
1337 static inline int
1338 iavf_xmit_cleanup(struct iavf_tx_queue *txq)
1339 {
1340         struct iavf_tx_entry *sw_ring = txq->sw_ring;
1341         uint16_t last_desc_cleaned = txq->last_desc_cleaned;
1342         uint16_t nb_tx_desc = txq->nb_tx_desc;
1343         uint16_t desc_to_clean_to;
1344         uint16_t nb_tx_to_clean;
1345
1346         volatile struct iavf_tx_desc *txd = txq->tx_ring;
1347
1348         desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->rs_thresh);
1349         if (desc_to_clean_to >= nb_tx_desc)
1350                 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
1351
1352         desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
1353         if ((txd[desc_to_clean_to].cmd_type_offset_bsz &
1354                         rte_cpu_to_le_64(IAVF_TXD_QW1_DTYPE_MASK)) !=
1355                         rte_cpu_to_le_64(IAVF_TX_DESC_DTYPE_DESC_DONE)) {
1356                 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
1357                                 "(port=%d queue=%d)", desc_to_clean_to,
1358                                 txq->port_id, txq->queue_id);
1359                 return -1;
1360         }
1361
1362         if (last_desc_cleaned > desc_to_clean_to)
1363                 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
1364                                                         desc_to_clean_to);
1365         else
1366                 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
1367                                         last_desc_cleaned);
1368
1369         txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
1370
1371         txq->last_desc_cleaned = desc_to_clean_to;
1372         txq->nb_free = (uint16_t)(txq->nb_free + nb_tx_to_clean);
1373
1374         return 0;
1375 }
1376
1377 /* Check if the context descriptor is needed for TX offloading */
1378 static inline uint16_t
1379 iavf_calc_context_desc(uint64_t flags)
1380 {
1381         static uint64_t mask = PKT_TX_TCP_SEG;
1382
1383         return (flags & mask) ? 1 : 0;
1384 }
1385
1386 static inline void
1387 iavf_txd_enable_checksum(uint64_t ol_flags,
1388                         uint32_t *td_cmd,
1389                         uint32_t *td_offset,
1390                         union iavf_tx_offload tx_offload)
1391 {
1392         /* Set MACLEN */
1393         *td_offset |= (tx_offload.l2_len >> 1) <<
1394                       IAVF_TX_DESC_LENGTH_MACLEN_SHIFT;
1395
1396         /* Enable L3 checksum offloads */
1397         if (ol_flags & PKT_TX_IP_CKSUM) {
1398                 *td_cmd |= IAVF_TX_DESC_CMD_IIPT_IPV4_CSUM;
1399                 *td_offset |= (tx_offload.l3_len >> 2) <<
1400                               IAVF_TX_DESC_LENGTH_IPLEN_SHIFT;
1401         } else if (ol_flags & PKT_TX_IPV4) {
1402                 *td_cmd |= IAVF_TX_DESC_CMD_IIPT_IPV4;
1403                 *td_offset |= (tx_offload.l3_len >> 2) <<
1404                               IAVF_TX_DESC_LENGTH_IPLEN_SHIFT;
1405         } else if (ol_flags & PKT_TX_IPV6) {
1406                 *td_cmd |= IAVF_TX_DESC_CMD_IIPT_IPV6;
1407                 *td_offset |= (tx_offload.l3_len >> 2) <<
1408                               IAVF_TX_DESC_LENGTH_IPLEN_SHIFT;
1409         }
1410
1411         if (ol_flags & PKT_TX_TCP_SEG) {
1412                 *td_cmd |= IAVF_TX_DESC_CMD_L4T_EOFT_TCP;
1413                 *td_offset |= (tx_offload.l4_len >> 2) <<
1414                               IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1415                 return;
1416         }
1417
1418         /* Enable L4 checksum offloads */
1419         switch (ol_flags & PKT_TX_L4_MASK) {
1420         case PKT_TX_TCP_CKSUM:
1421                 *td_cmd |= IAVF_TX_DESC_CMD_L4T_EOFT_TCP;
1422                 *td_offset |= (sizeof(struct rte_tcp_hdr) >> 2) <<
1423                               IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1424                 break;
1425         case PKT_TX_SCTP_CKSUM:
1426                 *td_cmd |= IAVF_TX_DESC_CMD_L4T_EOFT_SCTP;
1427                 *td_offset |= (sizeof(struct rte_sctp_hdr) >> 2) <<
1428                               IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1429                 break;
1430         case PKT_TX_UDP_CKSUM:
1431                 *td_cmd |= IAVF_TX_DESC_CMD_L4T_EOFT_UDP;
1432                 *td_offset |= (sizeof(struct rte_udp_hdr) >> 2) <<
1433                               IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1434                 break;
1435         default:
1436                 break;
1437         }
1438 }
1439
1440 /* set TSO context descriptor
1441  * support IP -> L4 and IP -> IP -> L4
1442  */
1443 static inline uint64_t
1444 iavf_set_tso_ctx(struct rte_mbuf *mbuf, union iavf_tx_offload tx_offload)
1445 {
1446         uint64_t ctx_desc = 0;
1447         uint32_t cd_cmd, hdr_len, cd_tso_len;
1448
1449         if (!tx_offload.l4_len) {
1450                 PMD_TX_LOG(DEBUG, "L4 length set to 0");
1451                 return ctx_desc;
1452         }
1453
1454         hdr_len = tx_offload.l2_len +
1455                   tx_offload.l3_len +
1456                   tx_offload.l4_len;
1457
1458         cd_cmd = IAVF_TX_CTX_DESC_TSO;
1459         cd_tso_len = mbuf->pkt_len - hdr_len;
1460         ctx_desc |= ((uint64_t)cd_cmd << IAVF_TXD_CTX_QW1_CMD_SHIFT) |
1461                      ((uint64_t)cd_tso_len << IAVF_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1462                      ((uint64_t)mbuf->tso_segsz << IAVF_TXD_CTX_QW1_MSS_SHIFT);
1463
1464         return ctx_desc;
1465 }
1466
1467 /* Construct the tx flags */
1468 static inline uint64_t
1469 iavf_build_ctob(uint32_t td_cmd, uint32_t td_offset, unsigned int size,
1470                uint32_t td_tag)
1471 {
1472         return rte_cpu_to_le_64(IAVF_TX_DESC_DTYPE_DATA |
1473                                 ((uint64_t)td_cmd  << IAVF_TXD_QW1_CMD_SHIFT) |
1474                                 ((uint64_t)td_offset <<
1475                                  IAVF_TXD_QW1_OFFSET_SHIFT) |
1476                                 ((uint64_t)size  <<
1477                                  IAVF_TXD_QW1_TX_BUF_SZ_SHIFT) |
1478                                 ((uint64_t)td_tag  <<
1479                                  IAVF_TXD_QW1_L2TAG1_SHIFT));
1480 }
1481
1482 /* TX function */
1483 uint16_t
1484 iavf_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1485 {
1486         volatile struct iavf_tx_desc *txd;
1487         volatile struct iavf_tx_desc *txr;
1488         struct iavf_tx_queue *txq;
1489         struct iavf_tx_entry *sw_ring;
1490         struct iavf_tx_entry *txe, *txn;
1491         struct rte_mbuf *tx_pkt;
1492         struct rte_mbuf *m_seg;
1493         uint16_t tx_id;
1494         uint16_t nb_tx;
1495         uint32_t td_cmd;
1496         uint32_t td_offset;
1497         uint32_t td_tag;
1498         uint64_t ol_flags;
1499         uint16_t nb_used;
1500         uint16_t nb_ctx;
1501         uint16_t tx_last;
1502         uint16_t slen;
1503         uint64_t buf_dma_addr;
1504         union iavf_tx_offload tx_offload = {0};
1505
1506         txq = tx_queue;
1507         sw_ring = txq->sw_ring;
1508         txr = txq->tx_ring;
1509         tx_id = txq->tx_tail;
1510         txe = &sw_ring[tx_id];
1511
1512         /* Check if the descriptor ring needs to be cleaned. */
1513         if (txq->nb_free < txq->free_thresh)
1514                 iavf_xmit_cleanup(txq);
1515
1516         for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1517                 td_cmd = 0;
1518                 td_tag = 0;
1519                 td_offset = 0;
1520
1521                 tx_pkt = *tx_pkts++;
1522                 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
1523
1524                 ol_flags = tx_pkt->ol_flags;
1525                 tx_offload.l2_len = tx_pkt->l2_len;
1526                 tx_offload.l3_len = tx_pkt->l3_len;
1527                 tx_offload.l4_len = tx_pkt->l4_len;
1528                 tx_offload.tso_segsz = tx_pkt->tso_segsz;
1529
1530                 /* Calculate the number of context descriptors needed. */
1531                 nb_ctx = iavf_calc_context_desc(ol_flags);
1532
1533                 /* The number of descriptors that must be allocated for
1534                  * a packet equals to the number of the segments of that
1535                  * packet plus 1 context descriptor if needed.
1536                  */
1537                 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
1538                 tx_last = (uint16_t)(tx_id + nb_used - 1);
1539
1540                 /* Circular ring */
1541                 if (tx_last >= txq->nb_tx_desc)
1542                         tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
1543
1544                 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u"
1545                            " tx_first=%u tx_last=%u",
1546                            txq->port_id, txq->queue_id, tx_id, tx_last);
1547
1548                 if (nb_used > txq->nb_free) {
1549                         if (iavf_xmit_cleanup(txq)) {
1550                                 if (nb_tx == 0)
1551                                         return 0;
1552                                 goto end_of_tx;
1553                         }
1554                         if (unlikely(nb_used > txq->rs_thresh)) {
1555                                 while (nb_used > txq->nb_free) {
1556                                         if (iavf_xmit_cleanup(txq)) {
1557                                                 if (nb_tx == 0)
1558                                                         return 0;
1559                                                 goto end_of_tx;
1560                                         }
1561                                 }
1562                         }
1563                 }
1564
1565                 /* Descriptor based VLAN insertion */
1566                 if (ol_flags & PKT_TX_VLAN_PKT) {
1567                         td_cmd |= IAVF_TX_DESC_CMD_IL2TAG1;
1568                         td_tag = tx_pkt->vlan_tci;
1569                 }
1570
1571                 /* According to datasheet, the bit2 is reserved and must be
1572                  * set to 1.
1573                  */
1574                 td_cmd |= 0x04;
1575
1576                 /* Enable checksum offloading */
1577                 if (ol_flags & IAVF_TX_CKSUM_OFFLOAD_MASK)
1578                         iavf_txd_enable_checksum(ol_flags, &td_cmd,
1579                                                 &td_offset, tx_offload);
1580
1581                 if (nb_ctx) {
1582                         /* Setup TX context descriptor if required */
1583                         uint64_t cd_type_cmd_tso_mss =
1584                                 IAVF_TX_DESC_DTYPE_CONTEXT;
1585                         volatile struct iavf_tx_context_desc *ctx_txd =
1586                                 (volatile struct iavf_tx_context_desc *)
1587                                                         &txr[tx_id];
1588
1589                         txn = &sw_ring[txe->next_id];
1590                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
1591                         if (txe->mbuf) {
1592                                 rte_pktmbuf_free_seg(txe->mbuf);
1593                                 txe->mbuf = NULL;
1594                         }
1595
1596                         /* TSO enabled */
1597                         if (ol_flags & PKT_TX_TCP_SEG)
1598                                 cd_type_cmd_tso_mss |=
1599                                         iavf_set_tso_ctx(tx_pkt, tx_offload);
1600
1601                         ctx_txd->type_cmd_tso_mss =
1602                                 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
1603
1604                         IAVF_DUMP_TX_DESC(txq, &txr[tx_id], tx_id);
1605                         txe->last_id = tx_last;
1606                         tx_id = txe->next_id;
1607                         txe = txn;
1608                 }
1609
1610                 m_seg = tx_pkt;
1611                 do {
1612                         txd = &txr[tx_id];
1613                         txn = &sw_ring[txe->next_id];
1614
1615                         if (txe->mbuf)
1616                                 rte_pktmbuf_free_seg(txe->mbuf);
1617                         txe->mbuf = m_seg;
1618
1619                         /* Setup TX Descriptor */
1620                         slen = m_seg->data_len;
1621                         buf_dma_addr = rte_mbuf_data_iova(m_seg);
1622                         txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
1623                         txd->cmd_type_offset_bsz = iavf_build_ctob(td_cmd,
1624                                                                   td_offset,
1625                                                                   slen,
1626                                                                   td_tag);
1627
1628                         IAVF_DUMP_TX_DESC(txq, txd, tx_id);
1629                         txe->last_id = tx_last;
1630                         tx_id = txe->next_id;
1631                         txe = txn;
1632                         m_seg = m_seg->next;
1633                 } while (m_seg);
1634
1635                 /* The last packet data descriptor needs End Of Packet (EOP) */
1636                 td_cmd |= IAVF_TX_DESC_CMD_EOP;
1637                 txq->nb_used = (uint16_t)(txq->nb_used + nb_used);
1638                 txq->nb_free = (uint16_t)(txq->nb_free - nb_used);
1639
1640                 if (txq->nb_used >= txq->rs_thresh) {
1641                         PMD_TX_LOG(DEBUG, "Setting RS bit on TXD id="
1642                                    "%4u (port=%d queue=%d)",
1643                                    tx_last, txq->port_id, txq->queue_id);
1644
1645                         td_cmd |= IAVF_TX_DESC_CMD_RS;
1646
1647                         /* Update txq RS bit counters */
1648                         txq->nb_used = 0;
1649                 }
1650
1651                 txd->cmd_type_offset_bsz |=
1652                         rte_cpu_to_le_64(((uint64_t)td_cmd) <<
1653                                          IAVF_TXD_QW1_CMD_SHIFT);
1654                 IAVF_DUMP_TX_DESC(txq, txd, tx_id);
1655         }
1656
1657 end_of_tx:
1658         rte_wmb();
1659
1660         PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
1661                    txq->port_id, txq->queue_id, tx_id, nb_tx);
1662
1663         IAVF_PCI_REG_WRITE_RELAXED(txq->qtx_tail, tx_id);
1664         txq->tx_tail = tx_id;
1665
1666         return nb_tx;
1667 }
1668
1669 static uint16_t
1670 iavf_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
1671                   uint16_t nb_pkts)
1672 {
1673         uint16_t nb_tx = 0;
1674         struct iavf_tx_queue *txq = (struct iavf_tx_queue *)tx_queue;
1675
1676         while (nb_pkts) {
1677                 uint16_t ret, num;
1678
1679                 num = (uint16_t)RTE_MIN(nb_pkts, txq->rs_thresh);
1680                 ret = iavf_xmit_fixed_burst_vec(tx_queue, &tx_pkts[nb_tx], num);
1681                 nb_tx += ret;
1682                 nb_pkts -= ret;
1683                 if (ret < num)
1684                         break;
1685         }
1686
1687         return nb_tx;
1688 }
1689
1690 /* TX prep functions */
1691 uint16_t
1692 iavf_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
1693               uint16_t nb_pkts)
1694 {
1695         int i, ret;
1696         uint64_t ol_flags;
1697         struct rte_mbuf *m;
1698
1699         for (i = 0; i < nb_pkts; i++) {
1700                 m = tx_pkts[i];
1701                 ol_flags = m->ol_flags;
1702
1703                 /* Check condition for nb_segs > IAVF_TX_MAX_MTU_SEG. */
1704                 if (!(ol_flags & PKT_TX_TCP_SEG)) {
1705                         if (m->nb_segs > IAVF_TX_MAX_MTU_SEG) {
1706                                 rte_errno = EINVAL;
1707                                 return i;
1708                         }
1709                 } else if ((m->tso_segsz < IAVF_MIN_TSO_MSS) ||
1710                            (m->tso_segsz > IAVF_MAX_TSO_MSS)) {
1711                         /* MSS outside the range are considered malicious */
1712                         rte_errno = EINVAL;
1713                         return i;
1714                 }
1715
1716                 if (ol_flags & IAVF_TX_OFFLOAD_NOTSUP_MASK) {
1717                         rte_errno = ENOTSUP;
1718                         return i;
1719                 }
1720
1721 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
1722                 ret = rte_validate_tx_offload(m);
1723                 if (ret != 0) {
1724                         rte_errno = -ret;
1725                         return i;
1726                 }
1727 #endif
1728                 ret = rte_net_intel_cksum_prepare(m);
1729                 if (ret != 0) {
1730                         rte_errno = -ret;
1731                         return i;
1732                 }
1733         }
1734
1735         return i;
1736 }
1737
1738 /* choose rx function*/
1739 void
1740 iavf_set_rx_function(struct rte_eth_dev *dev)
1741 {
1742         struct iavf_adapter *adapter =
1743                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1744         struct iavf_rx_queue *rxq;
1745         int i;
1746
1747         if (adapter->rx_vec_allowed) {
1748                 if (dev->data->scattered_rx) {
1749                         PMD_DRV_LOG(DEBUG, "Using Vector Scattered Rx callback"
1750                                     " (port=%d).", dev->data->port_id);
1751                         dev->rx_pkt_burst = iavf_recv_scattered_pkts_vec;
1752                 } else {
1753                         PMD_DRV_LOG(DEBUG, "Using Vector Rx callback"
1754                                     " (port=%d).", dev->data->port_id);
1755                         dev->rx_pkt_burst = iavf_recv_pkts_vec;
1756                 }
1757                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1758                         rxq = dev->data->rx_queues[i];
1759                         if (!rxq)
1760                                 continue;
1761                         iavf_rxq_vec_setup(rxq);
1762                 }
1763         } else if (dev->data->scattered_rx) {
1764                 PMD_DRV_LOG(DEBUG, "Using a Scattered Rx callback (port=%d).",
1765                             dev->data->port_id);
1766                 dev->rx_pkt_burst = iavf_recv_scattered_pkts;
1767         } else if (adapter->rx_bulk_alloc_allowed) {
1768                 PMD_DRV_LOG(DEBUG, "Using bulk Rx callback (port=%d).",
1769                             dev->data->port_id);
1770                 dev->rx_pkt_burst = iavf_recv_pkts_bulk_alloc;
1771         } else {
1772                 PMD_DRV_LOG(DEBUG, "Using Basic Rx callback (port=%d).",
1773                             dev->data->port_id);
1774                 dev->rx_pkt_burst = iavf_recv_pkts;
1775         }
1776 }
1777
1778 /* choose tx function*/
1779 void
1780 iavf_set_tx_function(struct rte_eth_dev *dev)
1781 {
1782         struct iavf_adapter *adapter =
1783                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1784         struct iavf_tx_queue *txq;
1785         int i;
1786
1787         if (adapter->tx_vec_allowed) {
1788                 PMD_DRV_LOG(DEBUG, "Using Vector Tx callback (port=%d).",
1789                             dev->data->port_id);
1790                 dev->tx_pkt_burst = iavf_xmit_pkts_vec;
1791                 dev->tx_pkt_prepare = NULL;
1792                 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1793                         txq = dev->data->tx_queues[i];
1794                         if (!txq)
1795                                 continue;
1796                         iavf_txq_vec_setup(txq);
1797                 }
1798         } else {
1799                 PMD_DRV_LOG(DEBUG, "Using Basic Tx callback (port=%d).",
1800                             dev->data->port_id);
1801                 dev->tx_pkt_burst = iavf_xmit_pkts;
1802                 dev->tx_pkt_prepare = iavf_prep_pkts;
1803         }
1804 }
1805
1806 void
1807 iavf_dev_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1808                      struct rte_eth_rxq_info *qinfo)
1809 {
1810         struct iavf_rx_queue *rxq;
1811
1812         rxq = dev->data->rx_queues[queue_id];
1813
1814         qinfo->mp = rxq->mp;
1815         qinfo->scattered_rx = dev->data->scattered_rx;
1816         qinfo->nb_desc = rxq->nb_rx_desc;
1817
1818         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1819         qinfo->conf.rx_drop_en = TRUE;
1820         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
1821 }
1822
1823 void
1824 iavf_dev_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1825                      struct rte_eth_txq_info *qinfo)
1826 {
1827         struct iavf_tx_queue *txq;
1828
1829         txq = dev->data->tx_queues[queue_id];
1830
1831         qinfo->nb_desc = txq->nb_tx_desc;
1832
1833         qinfo->conf.tx_free_thresh = txq->free_thresh;
1834         qinfo->conf.tx_rs_thresh = txq->rs_thresh;
1835         qinfo->conf.offloads = txq->offloads;
1836         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1837 }
1838
1839 /* Get the number of used descriptors of a rx queue */
1840 uint32_t
1841 iavf_dev_rxq_count(struct rte_eth_dev *dev, uint16_t queue_id)
1842 {
1843 #define IAVF_RXQ_SCAN_INTERVAL 4
1844         volatile union iavf_rx_desc *rxdp;
1845         struct iavf_rx_queue *rxq;
1846         uint16_t desc = 0;
1847
1848         rxq = dev->data->rx_queues[queue_id];
1849         rxdp = &rxq->rx_ring[rxq->rx_tail];
1850         while ((desc < rxq->nb_rx_desc) &&
1851                ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1852                  IAVF_RXD_QW1_STATUS_MASK) >> IAVF_RXD_QW1_STATUS_SHIFT) &
1853                (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)) {
1854                 /* Check the DD bit of a rx descriptor of each 4 in a group,
1855                  * to avoid checking too frequently and downgrading performance
1856                  * too much.
1857                  */
1858                 desc += IAVF_RXQ_SCAN_INTERVAL;
1859                 rxdp += IAVF_RXQ_SCAN_INTERVAL;
1860                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
1861                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
1862                                         desc - rxq->nb_rx_desc]);
1863         }
1864
1865         return desc;
1866 }
1867
1868 int
1869 iavf_dev_rx_desc_status(void *rx_queue, uint16_t offset)
1870 {
1871         struct iavf_rx_queue *rxq = rx_queue;
1872         volatile uint64_t *status;
1873         uint64_t mask;
1874         uint32_t desc;
1875
1876         if (unlikely(offset >= rxq->nb_rx_desc))
1877                 return -EINVAL;
1878
1879         if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
1880                 return RTE_ETH_RX_DESC_UNAVAIL;
1881
1882         desc = rxq->rx_tail + offset;
1883         if (desc >= rxq->nb_rx_desc)
1884                 desc -= rxq->nb_rx_desc;
1885
1886         status = &rxq->rx_ring[desc].wb.qword1.status_error_len;
1887         mask = rte_le_to_cpu_64((1ULL << IAVF_RX_DESC_STATUS_DD_SHIFT)
1888                 << IAVF_RXD_QW1_STATUS_SHIFT);
1889         if (*status & mask)
1890                 return RTE_ETH_RX_DESC_DONE;
1891
1892         return RTE_ETH_RX_DESC_AVAIL;
1893 }
1894
1895 int
1896 iavf_dev_tx_desc_status(void *tx_queue, uint16_t offset)
1897 {
1898         struct iavf_tx_queue *txq = tx_queue;
1899         volatile uint64_t *status;
1900         uint64_t mask, expect;
1901         uint32_t desc;
1902
1903         if (unlikely(offset >= txq->nb_tx_desc))
1904                 return -EINVAL;
1905
1906         desc = txq->tx_tail + offset;
1907         /* go to next desc that has the RS bit */
1908         desc = ((desc + txq->rs_thresh - 1) / txq->rs_thresh) *
1909                 txq->rs_thresh;
1910         if (desc >= txq->nb_tx_desc) {
1911                 desc -= txq->nb_tx_desc;
1912                 if (desc >= txq->nb_tx_desc)
1913                         desc -= txq->nb_tx_desc;
1914         }
1915
1916         status = &txq->tx_ring[desc].cmd_type_offset_bsz;
1917         mask = rte_le_to_cpu_64(IAVF_TXD_QW1_DTYPE_MASK);
1918         expect = rte_cpu_to_le_64(
1919                  IAVF_TX_DESC_DTYPE_DESC_DONE << IAVF_TXD_QW1_DTYPE_SHIFT);
1920         if ((*status & mask) == expect)
1921                 return RTE_ETH_TX_DESC_DONE;
1922
1923         return RTE_ETH_TX_DESC_FULL;
1924 }
1925
1926 __rte_weak uint16_t
1927 iavf_recv_pkts_vec(__rte_unused void *rx_queue,
1928                   __rte_unused struct rte_mbuf **rx_pkts,
1929                   __rte_unused uint16_t nb_pkts)
1930 {
1931         return 0;
1932 }
1933
1934 __rte_weak uint16_t
1935 iavf_recv_scattered_pkts_vec(__rte_unused void *rx_queue,
1936                             __rte_unused struct rte_mbuf **rx_pkts,
1937                             __rte_unused uint16_t nb_pkts)
1938 {
1939         return 0;
1940 }
1941
1942 __rte_weak uint16_t
1943 iavf_xmit_fixed_burst_vec(__rte_unused void *tx_queue,
1944                          __rte_unused struct rte_mbuf **tx_pkts,
1945                          __rte_unused uint16_t nb_pkts)
1946 {
1947         return 0;
1948 }
1949
1950 __rte_weak int
1951 iavf_rxq_vec_setup(__rte_unused struct iavf_rx_queue *rxq)
1952 {
1953         return -1;
1954 }
1955
1956 __rte_weak int
1957 iavf_txq_vec_setup(__rte_unused struct iavf_tx_queue *txq)
1958 {
1959         return -1;
1960 }