1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2017 Intel Corporation
13 #include <sys/queue.h>
15 #include <rte_string_fns.h>
16 #include <rte_memzone.h>
18 #include <rte_malloc.h>
19 #include <rte_ether.h>
20 #include <rte_ethdev_driver.h>
28 #include "iavf_rxtx.h"
31 check_rx_thresh(uint16_t nb_desc, uint16_t thresh)
33 /* The following constraints must be satisfied:
34 * thresh < rxq->nb_rx_desc
36 if (thresh >= nb_desc) {
37 PMD_INIT_LOG(ERR, "rx_free_thresh (%u) must be less than %u",
45 check_tx_thresh(uint16_t nb_desc, uint16_t tx_rs_thresh,
46 uint16_t tx_free_thresh)
48 /* TX descriptors will have their RS bit set after tx_rs_thresh
49 * descriptors have been used. The TX descriptor ring will be cleaned
50 * after tx_free_thresh descriptors are used or if the number of
51 * descriptors required to transmit a packet is greater than the
52 * number of free TX descriptors.
54 * The following constraints must be satisfied:
55 * - tx_rs_thresh must be less than the size of the ring minus 2.
56 * - tx_free_thresh must be less than the size of the ring minus 3.
57 * - tx_rs_thresh must be less than or equal to tx_free_thresh.
58 * - tx_rs_thresh must be a divisor of the ring size.
60 * One descriptor in the TX ring is used as a sentinel to avoid a H/W
61 * race condition, hence the maximum threshold constraints. When set
62 * to zero use default values.
64 if (tx_rs_thresh >= (nb_desc - 2)) {
65 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be less than the "
66 "number of TX descriptors (%u) minus 2",
67 tx_rs_thresh, nb_desc);
70 if (tx_free_thresh >= (nb_desc - 3)) {
71 PMD_INIT_LOG(ERR, "tx_free_thresh (%u) must be less than the "
72 "number of TX descriptors (%u) minus 3.",
73 tx_free_thresh, nb_desc);
76 if (tx_rs_thresh > tx_free_thresh) {
77 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be less than or "
78 "equal to tx_free_thresh (%u).",
79 tx_rs_thresh, tx_free_thresh);
82 if ((nb_desc % tx_rs_thresh) != 0) {
83 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be a divisor of the "
84 "number of TX descriptors (%u).",
85 tx_rs_thresh, nb_desc);
93 check_rx_vec_allow(struct iavf_rx_queue *rxq)
95 if (rxq->rx_free_thresh >= IAVF_VPMD_RX_MAX_BURST &&
96 rxq->nb_rx_desc % rxq->rx_free_thresh == 0) {
97 PMD_INIT_LOG(DEBUG, "Vector Rx can be enabled on this rxq.");
101 PMD_INIT_LOG(DEBUG, "Vector Rx cannot be enabled on this rxq.");
106 check_tx_vec_allow(struct iavf_tx_queue *txq)
108 if (!(txq->offloads & IAVF_NO_VECTOR_FLAGS) &&
109 txq->rs_thresh >= IAVF_VPMD_TX_MAX_BURST &&
110 txq->rs_thresh <= IAVF_VPMD_TX_MAX_FREE_BUF) {
111 PMD_INIT_LOG(DEBUG, "Vector tx can be enabled on this txq.");
114 PMD_INIT_LOG(DEBUG, "Vector Tx cannot be enabled on this txq.");
119 check_rx_bulk_allow(struct iavf_rx_queue *rxq)
123 if (!(rxq->rx_free_thresh >= IAVF_RX_MAX_BURST)) {
124 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
125 "rxq->rx_free_thresh=%d, "
126 "IAVF_RX_MAX_BURST=%d",
127 rxq->rx_free_thresh, IAVF_RX_MAX_BURST);
129 } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
130 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
131 "rxq->nb_rx_desc=%d, "
132 "rxq->rx_free_thresh=%d",
133 rxq->nb_rx_desc, rxq->rx_free_thresh);
140 reset_rx_queue(struct iavf_rx_queue *rxq)
148 len = rxq->nb_rx_desc + IAVF_RX_MAX_BURST;
150 for (i = 0; i < len * sizeof(union iavf_rx_desc); i++)
151 ((volatile char *)rxq->rx_ring)[i] = 0;
153 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
155 for (i = 0; i < IAVF_RX_MAX_BURST; i++)
156 rxq->sw_ring[rxq->nb_rx_desc + i] = &rxq->fake_mbuf;
159 rxq->rx_nb_avail = 0;
160 rxq->rx_next_avail = 0;
161 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
165 rxq->pkt_first_seg = NULL;
166 rxq->pkt_last_seg = NULL;
170 reset_tx_queue(struct iavf_tx_queue *txq)
172 struct iavf_tx_entry *txe;
177 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
182 size = sizeof(struct iavf_tx_desc) * txq->nb_tx_desc;
183 for (i = 0; i < size; i++)
184 ((volatile char *)txq->tx_ring)[i] = 0;
186 prev = (uint16_t)(txq->nb_tx_desc - 1);
187 for (i = 0; i < txq->nb_tx_desc; i++) {
188 txq->tx_ring[i].cmd_type_offset_bsz =
189 rte_cpu_to_le_64(IAVF_TX_DESC_DTYPE_DESC_DONE);
192 txe[prev].next_id = i;
199 txq->last_desc_cleaned = txq->nb_tx_desc - 1;
200 txq->nb_free = txq->nb_tx_desc - 1;
202 txq->next_dd = txq->rs_thresh - 1;
203 txq->next_rs = txq->rs_thresh - 1;
207 alloc_rxq_mbufs(struct iavf_rx_queue *rxq)
209 volatile union iavf_rx_desc *rxd;
210 struct rte_mbuf *mbuf = NULL;
214 for (i = 0; i < rxq->nb_rx_desc; i++) {
215 mbuf = rte_mbuf_raw_alloc(rxq->mp);
216 if (unlikely(!mbuf)) {
217 PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
221 rte_mbuf_refcnt_set(mbuf, 1);
223 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
225 mbuf->port = rxq->port_id;
228 rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
230 rxd = &rxq->rx_ring[i];
231 rxd->read.pkt_addr = dma_addr;
232 rxd->read.hdr_addr = 0;
233 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
238 rxq->sw_ring[i] = mbuf;
245 release_rxq_mbufs(struct iavf_rx_queue *rxq)
252 for (i = 0; i < rxq->nb_rx_desc; i++) {
253 if (rxq->sw_ring[i]) {
254 rte_pktmbuf_free_seg(rxq->sw_ring[i]);
255 rxq->sw_ring[i] = NULL;
260 if (rxq->rx_nb_avail == 0)
262 for (i = 0; i < rxq->rx_nb_avail; i++) {
263 struct rte_mbuf *mbuf;
265 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
266 rte_pktmbuf_free_seg(mbuf);
268 rxq->rx_nb_avail = 0;
272 release_txq_mbufs(struct iavf_tx_queue *txq)
276 if (!txq || !txq->sw_ring) {
277 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
281 for (i = 0; i < txq->nb_tx_desc; i++) {
282 if (txq->sw_ring[i].mbuf) {
283 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
284 txq->sw_ring[i].mbuf = NULL;
289 static const struct iavf_rxq_ops def_rxq_ops = {
290 .release_mbufs = release_rxq_mbufs,
293 static const struct iavf_txq_ops def_txq_ops = {
294 .release_mbufs = release_txq_mbufs,
298 iavf_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
299 uint16_t nb_desc, unsigned int socket_id,
300 const struct rte_eth_rxconf *rx_conf,
301 struct rte_mempool *mp)
303 struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
304 struct iavf_adapter *ad =
305 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
306 struct iavf_info *vf =
307 IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
308 struct iavf_vsi *vsi = &vf->vsi;
309 struct iavf_rx_queue *rxq;
310 const struct rte_memzone *mz;
313 uint16_t rx_free_thresh;
315 PMD_INIT_FUNC_TRACE();
317 if (nb_desc % IAVF_ALIGN_RING_DESC != 0 ||
318 nb_desc > IAVF_MAX_RING_DESC ||
319 nb_desc < IAVF_MIN_RING_DESC) {
320 PMD_INIT_LOG(ERR, "Number (%u) of receive descriptors is "
325 /* Check free threshold */
326 rx_free_thresh = (rx_conf->rx_free_thresh == 0) ?
327 IAVF_DEFAULT_RX_FREE_THRESH :
328 rx_conf->rx_free_thresh;
329 if (check_rx_thresh(nb_desc, rx_free_thresh) != 0)
332 /* Free memory if needed */
333 if (dev->data->rx_queues[queue_idx]) {
334 iavf_dev_rx_queue_release(dev->data->rx_queues[queue_idx]);
335 dev->data->rx_queues[queue_idx] = NULL;
338 /* Allocate the rx queue data structure */
339 rxq = rte_zmalloc_socket("iavf rxq",
340 sizeof(struct iavf_rx_queue),
344 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
345 "rx queue data structure");
349 if (vf->vf_res->vf_cap_flags &
350 VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC &&
351 vf->supported_rxdid & BIT(IAVF_RXDID_COMMS_OVS_1)) {
352 rxq->rxdid = IAVF_RXDID_COMMS_OVS_1;
354 rxq->rxdid = IAVF_RXDID_LEGACY_1;
358 rxq->nb_rx_desc = nb_desc;
359 rxq->rx_free_thresh = rx_free_thresh;
360 rxq->queue_id = queue_idx;
361 rxq->port_id = dev->data->port_id;
362 rxq->crc_len = 0; /* crc stripping by default */
363 rxq->rx_deferred_start = rx_conf->rx_deferred_start;
367 len = rte_pktmbuf_data_room_size(rxq->mp) - RTE_PKTMBUF_HEADROOM;
368 rxq->rx_buf_len = RTE_ALIGN(len, (1 << IAVF_RXQ_CTX_DBUFF_SHIFT));
370 /* Allocate the software ring. */
371 len = nb_desc + IAVF_RX_MAX_BURST;
373 rte_zmalloc_socket("iavf rx sw ring",
374 sizeof(struct rte_mbuf *) * len,
378 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW ring");
383 /* Allocate the maximun number of RX ring hardware descriptor with
384 * a liitle more to support bulk allocate.
386 len = IAVF_MAX_RING_DESC + IAVF_RX_MAX_BURST;
387 ring_size = RTE_ALIGN(len * sizeof(union iavf_rx_desc),
389 mz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
390 ring_size, IAVF_RING_BASE_ALIGN,
393 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for RX");
394 rte_free(rxq->sw_ring);
398 /* Zero all the descriptors in the ring. */
399 memset(mz->addr, 0, ring_size);
400 rxq->rx_ring_phys_addr = mz->iova;
401 rxq->rx_ring = (union iavf_rx_desc *)mz->addr;
406 dev->data->rx_queues[queue_idx] = rxq;
407 rxq->qrx_tail = hw->hw_addr + IAVF_QRX_TAIL1(rxq->queue_id);
408 rxq->ops = &def_rxq_ops;
410 if (check_rx_bulk_allow(rxq) == true) {
411 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
412 "satisfied. Rx Burst Bulk Alloc function will be "
413 "used on port=%d, queue=%d.",
414 rxq->port_id, rxq->queue_id);
416 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
417 "not satisfied, Scattered Rx is requested "
418 "on port=%d, queue=%d.",
419 rxq->port_id, rxq->queue_id);
420 ad->rx_bulk_alloc_allowed = false;
423 if (check_rx_vec_allow(rxq) == false)
424 ad->rx_vec_allowed = false;
430 iavf_dev_tx_queue_setup(struct rte_eth_dev *dev,
433 unsigned int socket_id,
434 const struct rte_eth_txconf *tx_conf)
436 struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
437 struct iavf_tx_queue *txq;
438 const struct rte_memzone *mz;
440 uint16_t tx_rs_thresh, tx_free_thresh;
443 PMD_INIT_FUNC_TRACE();
445 offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
447 if (nb_desc % IAVF_ALIGN_RING_DESC != 0 ||
448 nb_desc > IAVF_MAX_RING_DESC ||
449 nb_desc < IAVF_MIN_RING_DESC) {
450 PMD_INIT_LOG(ERR, "Number (%u) of transmit descriptors is "
455 tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
456 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
457 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
458 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
459 check_tx_thresh(nb_desc, tx_rs_thresh, tx_rs_thresh);
461 /* Free memory if needed. */
462 if (dev->data->tx_queues[queue_idx]) {
463 iavf_dev_tx_queue_release(dev->data->tx_queues[queue_idx]);
464 dev->data->tx_queues[queue_idx] = NULL;
467 /* Allocate the TX queue data structure. */
468 txq = rte_zmalloc_socket("iavf txq",
469 sizeof(struct iavf_tx_queue),
473 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
474 "tx queue structure");
478 txq->nb_tx_desc = nb_desc;
479 txq->rs_thresh = tx_rs_thresh;
480 txq->free_thresh = tx_free_thresh;
481 txq->queue_id = queue_idx;
482 txq->port_id = dev->data->port_id;
483 txq->offloads = offloads;
484 txq->tx_deferred_start = tx_conf->tx_deferred_start;
486 /* Allocate software ring */
488 rte_zmalloc_socket("iavf tx sw ring",
489 sizeof(struct iavf_tx_entry) * nb_desc,
493 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW TX ring");
498 /* Allocate TX hardware ring descriptors. */
499 ring_size = sizeof(struct iavf_tx_desc) * IAVF_MAX_RING_DESC;
500 ring_size = RTE_ALIGN(ring_size, IAVF_DMA_MEM_ALIGN);
501 mz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
502 ring_size, IAVF_RING_BASE_ALIGN,
505 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for TX");
506 rte_free(txq->sw_ring);
510 txq->tx_ring_phys_addr = mz->iova;
511 txq->tx_ring = (struct iavf_tx_desc *)mz->addr;
516 dev->data->tx_queues[queue_idx] = txq;
517 txq->qtx_tail = hw->hw_addr + IAVF_QTX_TAIL1(queue_idx);
518 txq->ops = &def_txq_ops;
520 if (check_tx_vec_allow(txq) == false) {
521 struct iavf_adapter *ad =
522 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
523 ad->tx_vec_allowed = false;
530 iavf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
532 struct iavf_adapter *adapter =
533 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
534 struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
535 struct iavf_rx_queue *rxq;
538 PMD_DRV_FUNC_TRACE();
540 if (rx_queue_id >= dev->data->nb_rx_queues)
543 rxq = dev->data->rx_queues[rx_queue_id];
545 err = alloc_rxq_mbufs(rxq);
547 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
553 /* Init the RX tail register. */
554 IAVF_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
555 IAVF_WRITE_FLUSH(hw);
557 /* Ready to switch the queue on */
558 err = iavf_switch_queue(adapter, rx_queue_id, true, true);
560 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
563 dev->data->rx_queue_state[rx_queue_id] =
564 RTE_ETH_QUEUE_STATE_STARTED;
570 iavf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
572 struct iavf_adapter *adapter =
573 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
574 struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
575 struct iavf_tx_queue *txq;
578 PMD_DRV_FUNC_TRACE();
580 if (tx_queue_id >= dev->data->nb_tx_queues)
583 txq = dev->data->tx_queues[tx_queue_id];
585 /* Init the RX tail register. */
586 IAVF_PCI_REG_WRITE(txq->qtx_tail, 0);
587 IAVF_WRITE_FLUSH(hw);
589 /* Ready to switch the queue on */
590 err = iavf_switch_queue(adapter, tx_queue_id, false, true);
593 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
596 dev->data->tx_queue_state[tx_queue_id] =
597 RTE_ETH_QUEUE_STATE_STARTED;
603 iavf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
605 struct iavf_adapter *adapter =
606 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
607 struct iavf_rx_queue *rxq;
610 PMD_DRV_FUNC_TRACE();
612 if (rx_queue_id >= dev->data->nb_rx_queues)
615 err = iavf_switch_queue(adapter, rx_queue_id, true, false);
617 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
622 rxq = dev->data->rx_queues[rx_queue_id];
623 rxq->ops->release_mbufs(rxq);
625 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
631 iavf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
633 struct iavf_adapter *adapter =
634 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
635 struct iavf_tx_queue *txq;
638 PMD_DRV_FUNC_TRACE();
640 if (tx_queue_id >= dev->data->nb_tx_queues)
643 err = iavf_switch_queue(adapter, tx_queue_id, false, false);
645 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u off",
650 txq = dev->data->tx_queues[tx_queue_id];
651 txq->ops->release_mbufs(txq);
653 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
659 iavf_dev_rx_queue_release(void *rxq)
661 struct iavf_rx_queue *q = (struct iavf_rx_queue *)rxq;
666 q->ops->release_mbufs(q);
667 rte_free(q->sw_ring);
668 rte_memzone_free(q->mz);
673 iavf_dev_tx_queue_release(void *txq)
675 struct iavf_tx_queue *q = (struct iavf_tx_queue *)txq;
680 q->ops->release_mbufs(q);
681 rte_free(q->sw_ring);
682 rte_memzone_free(q->mz);
687 iavf_stop_queues(struct rte_eth_dev *dev)
689 struct iavf_adapter *adapter =
690 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
691 struct iavf_rx_queue *rxq;
692 struct iavf_tx_queue *txq;
695 /* Stop All queues */
696 ret = iavf_disable_queues(adapter);
698 PMD_DRV_LOG(WARNING, "Fail to stop queues");
700 for (i = 0; i < dev->data->nb_tx_queues; i++) {
701 txq = dev->data->tx_queues[i];
704 txq->ops->release_mbufs(txq);
706 dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED;
708 for (i = 0; i < dev->data->nb_rx_queues; i++) {
709 rxq = dev->data->rx_queues[i];
712 rxq->ops->release_mbufs(rxq);
714 dev->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED;
719 iavf_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union iavf_rx_desc *rxdp)
721 if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
722 (1 << IAVF_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
723 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
725 rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
732 iavf_flex_rxd_to_vlan_tci(struct rte_mbuf *mb,
733 volatile union iavf_rx_flex_desc *rxdp)
735 if (rte_le_to_cpu_64(rxdp->wb.status_error0) &
736 (1 << IAVF_RX_FLEX_DESC_STATUS0_L2TAG1P_S)) {
737 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
739 rte_le_to_cpu_16(rxdp->wb.l2tag1);
745 /* Translate the rx descriptor status and error fields to pkt flags */
746 static inline uint64_t
747 iavf_rxd_to_pkt_flags(uint64_t qword)
750 uint64_t error_bits = (qword >> IAVF_RXD_QW1_ERROR_SHIFT);
752 #define IAVF_RX_ERR_BITS 0x3f
754 /* Check if RSS_HASH */
755 flags = (((qword >> IAVF_RX_DESC_STATUS_FLTSTAT_SHIFT) &
756 IAVF_RX_DESC_FLTSTAT_RSS_HASH) ==
757 IAVF_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;
759 /* Check if FDIR Match */
760 flags |= (qword & (1 << IAVF_RX_DESC_STATUS_FLM_SHIFT) ?
763 if (likely((error_bits & IAVF_RX_ERR_BITS) == 0)) {
764 flags |= (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD);
768 if (unlikely(error_bits & (1 << IAVF_RX_DESC_ERROR_IPE_SHIFT)))
769 flags |= PKT_RX_IP_CKSUM_BAD;
771 flags |= PKT_RX_IP_CKSUM_GOOD;
773 if (unlikely(error_bits & (1 << IAVF_RX_DESC_ERROR_L4E_SHIFT)))
774 flags |= PKT_RX_L4_CKSUM_BAD;
776 flags |= PKT_RX_L4_CKSUM_GOOD;
778 /* TODO: Oversize error bit is not processed here */
783 static inline uint64_t
784 iavf_rxd_build_fdir(volatile union iavf_rx_desc *rxdp, struct rte_mbuf *mb)
787 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
790 flexbh = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
791 IAVF_RX_DESC_EXT_STATUS_FLEXBH_SHIFT) &
792 IAVF_RX_DESC_EXT_STATUS_FLEXBH_MASK;
794 if (flexbh == IAVF_RX_DESC_EXT_STATUS_FLEXBH_FD_ID) {
796 rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.fd_id);
797 flags |= PKT_RX_FDIR_ID;
801 rte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.fd_id);
802 flags |= PKT_RX_FDIR_ID;
808 /* Translate the rx flex descriptor status to pkt flags */
810 iavf_rxd_to_pkt_fields(struct rte_mbuf *mb,
811 volatile union iavf_rx_flex_desc *rxdp)
813 volatile struct iavf_32b_rx_flex_desc_comms_ovs *desc =
814 (volatile struct iavf_32b_rx_flex_desc_comms_ovs *)rxdp;
815 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
818 stat_err = rte_le_to_cpu_16(desc->status_error0);
819 if (likely(stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
820 mb->ol_flags |= PKT_RX_RSS_HASH;
821 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
825 if (desc->flow_id != 0xFFFFFFFF) {
826 mb->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
827 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
831 #define IAVF_RX_FLEX_ERR0_BITS \
832 ((1 << IAVF_RX_FLEX_DESC_STATUS0_HBO_S) | \
833 (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_IPE_S) | \
834 (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_L4E_S) | \
835 (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S) | \
836 (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S) | \
837 (1 << IAVF_RX_FLEX_DESC_STATUS0_RXE_S))
839 /* Rx L3/L4 checksum */
840 static inline uint64_t
841 iavf_flex_rxd_error_to_pkt_flags(uint16_t stat_err0)
845 /* check if HW has decoded the packet and checksum */
846 if (unlikely(!(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_L3L4P_S))))
849 if (likely(!(stat_err0 & IAVF_RX_FLEX_ERR0_BITS))) {
850 flags |= (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD);
854 if (unlikely(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_IPE_S)))
855 flags |= PKT_RX_IP_CKSUM_BAD;
857 flags |= PKT_RX_IP_CKSUM_GOOD;
859 if (unlikely(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_L4E_S)))
860 flags |= PKT_RX_L4_CKSUM_BAD;
862 flags |= PKT_RX_L4_CKSUM_GOOD;
864 if (unlikely(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S)))
865 flags |= PKT_RX_EIP_CKSUM_BAD;
870 /* If the number of free RX descriptors is greater than the RX free
871 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
872 * register. Update the RDT with the value of the last processed RX
873 * descriptor minus 1, to guarantee that the RDT register is never
874 * equal to the RDH register, which creates a "full" ring situation
875 * from the hardware point of view.
878 iavf_update_rx_tail(struct iavf_rx_queue *rxq, uint16_t nb_hold, uint16_t rx_id)
880 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
882 if (nb_hold > rxq->rx_free_thresh) {
884 "port_id=%u queue_id=%u rx_tail=%u nb_hold=%u",
885 rxq->port_id, rxq->queue_id, rx_id, nb_hold);
886 rx_id = (uint16_t)((rx_id == 0) ?
887 (rxq->nb_rx_desc - 1) : (rx_id - 1));
888 IAVF_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
891 rxq->nb_rx_hold = nb_hold;
894 /* implement recv_pkts */
896 iavf_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
898 volatile union iavf_rx_desc *rx_ring;
899 volatile union iavf_rx_desc *rxdp;
900 struct iavf_rx_queue *rxq;
901 union iavf_rx_desc rxd;
902 struct rte_mbuf *rxe;
903 struct rte_eth_dev *dev;
904 struct rte_mbuf *rxm;
905 struct rte_mbuf *nmb;
909 uint16_t rx_packet_len;
910 uint16_t rx_id, nb_hold;
913 const uint32_t *ptype_tbl;
918 rx_id = rxq->rx_tail;
919 rx_ring = rxq->rx_ring;
920 ptype_tbl = rxq->vsi->adapter->ptype_tbl;
922 while (nb_rx < nb_pkts) {
923 rxdp = &rx_ring[rx_id];
924 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
925 rx_status = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
926 IAVF_RXD_QW1_STATUS_SHIFT;
928 /* Check the DD bit first */
929 if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)))
931 IAVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
933 nmb = rte_mbuf_raw_alloc(rxq->mp);
934 if (unlikely(!nmb)) {
935 dev = &rte_eth_devices[rxq->port_id];
936 dev->data->rx_mbuf_alloc_failed++;
937 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
938 "queue_id=%u", rxq->port_id, rxq->queue_id);
944 rxe = rxq->sw_ring[rx_id];
946 if (unlikely(rx_id == rxq->nb_rx_desc))
949 /* Prefetch next mbuf */
950 rte_prefetch0(rxq->sw_ring[rx_id]);
952 /* When next RX descriptor is on a cache line boundary,
953 * prefetch the next 4 RX descriptors and next 8 pointers
956 if ((rx_id & 0x3) == 0) {
957 rte_prefetch0(&rx_ring[rx_id]);
958 rte_prefetch0(rxq->sw_ring[rx_id]);
963 rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
964 rxdp->read.hdr_addr = 0;
965 rxdp->read.pkt_addr = dma_addr;
967 rx_packet_len = ((qword1 & IAVF_RXD_QW1_LENGTH_PBUF_MASK) >>
968 IAVF_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
970 rxm->data_off = RTE_PKTMBUF_HEADROOM;
971 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
974 rxm->pkt_len = rx_packet_len;
975 rxm->data_len = rx_packet_len;
976 rxm->port = rxq->port_id;
978 iavf_rxd_to_vlan_tci(rxm, &rxd);
979 pkt_flags = iavf_rxd_to_pkt_flags(qword1);
981 ptype_tbl[(uint8_t)((qword1 &
982 IAVF_RXD_QW1_PTYPE_MASK) >> IAVF_RXD_QW1_PTYPE_SHIFT)];
984 if (pkt_flags & PKT_RX_RSS_HASH)
986 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
988 if (pkt_flags & PKT_RX_FDIR)
989 pkt_flags |= iavf_rxd_build_fdir(&rxd, rxm);
991 rxm->ol_flags |= pkt_flags;
993 rx_pkts[nb_rx++] = rxm;
995 rxq->rx_tail = rx_id;
997 iavf_update_rx_tail(rxq, nb_hold, rx_id);
1002 /* implement recv_pkts for flexible Rx descriptor */
1004 iavf_recv_pkts_flex_rxd(void *rx_queue,
1005 struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1007 volatile union iavf_rx_desc *rx_ring;
1008 volatile union iavf_rx_flex_desc *rxdp;
1009 struct iavf_rx_queue *rxq;
1010 union iavf_rx_flex_desc rxd;
1011 struct rte_mbuf *rxe;
1012 struct rte_eth_dev *dev;
1013 struct rte_mbuf *rxm;
1014 struct rte_mbuf *nmb;
1016 uint16_t rx_stat_err0;
1017 uint16_t rx_packet_len;
1018 uint16_t rx_id, nb_hold;
1021 const uint32_t *ptype_tbl;
1026 rx_id = rxq->rx_tail;
1027 rx_ring = rxq->rx_ring;
1028 ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1030 while (nb_rx < nb_pkts) {
1031 rxdp = (volatile union iavf_rx_flex_desc *)&rx_ring[rx_id];
1032 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1034 /* Check the DD bit first */
1035 if (!(rx_stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S)))
1037 IAVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
1039 nmb = rte_mbuf_raw_alloc(rxq->mp);
1040 if (unlikely(!nmb)) {
1041 dev = &rte_eth_devices[rxq->port_id];
1042 dev->data->rx_mbuf_alloc_failed++;
1043 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1044 "queue_id=%u", rxq->port_id, rxq->queue_id);
1050 rxe = rxq->sw_ring[rx_id];
1052 if (unlikely(rx_id == rxq->nb_rx_desc))
1055 /* Prefetch next mbuf */
1056 rte_prefetch0(rxq->sw_ring[rx_id]);
1058 /* When next RX descriptor is on a cache line boundary,
1059 * prefetch the next 4 RX descriptors and next 8 pointers
1062 if ((rx_id & 0x3) == 0) {
1063 rte_prefetch0(&rx_ring[rx_id]);
1064 rte_prefetch0(rxq->sw_ring[rx_id]);
1069 rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1070 rxdp->read.hdr_addr = 0;
1071 rxdp->read.pkt_addr = dma_addr;
1073 rx_packet_len = (rte_le_to_cpu_16(rxd.wb.pkt_len) &
1074 IAVF_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
1076 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1077 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
1080 rxm->pkt_len = rx_packet_len;
1081 rxm->data_len = rx_packet_len;
1082 rxm->port = rxq->port_id;
1084 rxm->packet_type = ptype_tbl[IAVF_RX_FLEX_DESC_PTYPE_M &
1085 rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
1086 iavf_flex_rxd_to_vlan_tci(rxm, &rxd);
1087 iavf_rxd_to_pkt_fields(rxm, &rxd);
1088 pkt_flags = iavf_flex_rxd_error_to_pkt_flags(rx_stat_err0);
1089 rxm->ol_flags |= pkt_flags;
1091 rx_pkts[nb_rx++] = rxm;
1093 rxq->rx_tail = rx_id;
1095 iavf_update_rx_tail(rxq, nb_hold, rx_id);
1100 /* implement recv_scattered_pkts for flexible Rx descriptor */
1102 iavf_recv_scattered_pkts_flex_rxd(void *rx_queue, struct rte_mbuf **rx_pkts,
1105 struct iavf_rx_queue *rxq = rx_queue;
1106 union iavf_rx_flex_desc rxd;
1107 struct rte_mbuf *rxe;
1108 struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1109 struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1110 struct rte_mbuf *nmb, *rxm;
1111 uint16_t rx_id = rxq->rx_tail;
1112 uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
1113 struct rte_eth_dev *dev;
1114 uint16_t rx_stat_err0;
1118 volatile union iavf_rx_desc *rx_ring = rxq->rx_ring;
1119 volatile union iavf_rx_flex_desc *rxdp;
1120 const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1122 while (nb_rx < nb_pkts) {
1123 rxdp = (volatile union iavf_rx_flex_desc *)&rx_ring[rx_id];
1124 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1126 /* Check the DD bit */
1127 if (!(rx_stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S)))
1129 IAVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
1131 nmb = rte_mbuf_raw_alloc(rxq->mp);
1132 if (unlikely(!nmb)) {
1133 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1134 "queue_id=%u", rxq->port_id, rxq->queue_id);
1135 dev = &rte_eth_devices[rxq->port_id];
1136 dev->data->rx_mbuf_alloc_failed++;
1142 rxe = rxq->sw_ring[rx_id];
1144 if (rx_id == rxq->nb_rx_desc)
1147 /* Prefetch next mbuf */
1148 rte_prefetch0(rxq->sw_ring[rx_id]);
1150 /* When next RX descriptor is on a cache line boundary,
1151 * prefetch the next 4 RX descriptors and next 8 pointers
1154 if ((rx_id & 0x3) == 0) {
1155 rte_prefetch0(&rx_ring[rx_id]);
1156 rte_prefetch0(rxq->sw_ring[rx_id]);
1162 rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1164 /* Set data buffer address and data length of the mbuf */
1165 rxdp->read.hdr_addr = 0;
1166 rxdp->read.pkt_addr = dma_addr;
1167 rx_packet_len = rte_le_to_cpu_16(rxd.wb.pkt_len) &
1168 IAVF_RX_FLX_DESC_PKT_LEN_M;
1169 rxm->data_len = rx_packet_len;
1170 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1172 /* If this is the first buffer of the received packet, set the
1173 * pointer to the first mbuf of the packet and initialize its
1174 * context. Otherwise, update the total length and the number
1175 * of segments of the current scattered packet, and update the
1176 * pointer to the last mbuf of the current packet.
1180 first_seg->nb_segs = 1;
1181 first_seg->pkt_len = rx_packet_len;
1183 first_seg->pkt_len =
1184 (uint16_t)(first_seg->pkt_len +
1186 first_seg->nb_segs++;
1187 last_seg->next = rxm;
1190 /* If this is not the last buffer of the received packet,
1191 * update the pointer to the last mbuf of the current scattered
1192 * packet and continue to parse the RX ring.
1194 if (!(rx_stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_EOF_S))) {
1199 /* This is the last buffer of the received packet. If the CRC
1200 * is not stripped by the hardware:
1201 * - Subtract the CRC length from the total packet length.
1202 * - If the last buffer only contains the whole CRC or a part
1203 * of it, free the mbuf associated to the last buffer. If part
1204 * of the CRC is also contained in the previous mbuf, subtract
1205 * the length of that CRC part from the data length of the
1209 if (unlikely(rxq->crc_len > 0)) {
1210 first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
1211 if (rx_packet_len <= RTE_ETHER_CRC_LEN) {
1212 rte_pktmbuf_free_seg(rxm);
1213 first_seg->nb_segs--;
1214 last_seg->data_len =
1215 (uint16_t)(last_seg->data_len -
1216 (RTE_ETHER_CRC_LEN - rx_packet_len));
1217 last_seg->next = NULL;
1219 rxm->data_len = (uint16_t)(rx_packet_len -
1224 first_seg->port = rxq->port_id;
1225 first_seg->ol_flags = 0;
1226 first_seg->packet_type = ptype_tbl[IAVF_RX_FLEX_DESC_PTYPE_M &
1227 rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
1228 iavf_flex_rxd_to_vlan_tci(first_seg, &rxd);
1229 iavf_rxd_to_pkt_fields(first_seg, &rxd);
1230 pkt_flags = iavf_flex_rxd_error_to_pkt_flags(rx_stat_err0);
1232 first_seg->ol_flags |= pkt_flags;
1234 /* Prefetch data of first segment, if configured to do so. */
1235 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1236 first_seg->data_off));
1237 rx_pkts[nb_rx++] = first_seg;
1241 /* Record index of the next RX descriptor to probe. */
1242 rxq->rx_tail = rx_id;
1243 rxq->pkt_first_seg = first_seg;
1244 rxq->pkt_last_seg = last_seg;
1246 iavf_update_rx_tail(rxq, nb_hold, rx_id);
1251 /* implement recv_scattered_pkts */
1253 iavf_recv_scattered_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1256 struct iavf_rx_queue *rxq = rx_queue;
1257 union iavf_rx_desc rxd;
1258 struct rte_mbuf *rxe;
1259 struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1260 struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1261 struct rte_mbuf *nmb, *rxm;
1262 uint16_t rx_id = rxq->rx_tail;
1263 uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
1264 struct rte_eth_dev *dev;
1270 volatile union iavf_rx_desc *rx_ring = rxq->rx_ring;
1271 volatile union iavf_rx_desc *rxdp;
1272 const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1274 while (nb_rx < nb_pkts) {
1275 rxdp = &rx_ring[rx_id];
1276 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1277 rx_status = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
1278 IAVF_RXD_QW1_STATUS_SHIFT;
1280 /* Check the DD bit */
1281 if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)))
1283 IAVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
1285 nmb = rte_mbuf_raw_alloc(rxq->mp);
1286 if (unlikely(!nmb)) {
1287 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1288 "queue_id=%u", rxq->port_id, rxq->queue_id);
1289 dev = &rte_eth_devices[rxq->port_id];
1290 dev->data->rx_mbuf_alloc_failed++;
1296 rxe = rxq->sw_ring[rx_id];
1298 if (rx_id == rxq->nb_rx_desc)
1301 /* Prefetch next mbuf */
1302 rte_prefetch0(rxq->sw_ring[rx_id]);
1304 /* When next RX descriptor is on a cache line boundary,
1305 * prefetch the next 4 RX descriptors and next 8 pointers
1308 if ((rx_id & 0x3) == 0) {
1309 rte_prefetch0(&rx_ring[rx_id]);
1310 rte_prefetch0(rxq->sw_ring[rx_id]);
1316 rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1318 /* Set data buffer address and data length of the mbuf */
1319 rxdp->read.hdr_addr = 0;
1320 rxdp->read.pkt_addr = dma_addr;
1321 rx_packet_len = (qword1 & IAVF_RXD_QW1_LENGTH_PBUF_MASK) >>
1322 IAVF_RXD_QW1_LENGTH_PBUF_SHIFT;
1323 rxm->data_len = rx_packet_len;
1324 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1326 /* If this is the first buffer of the received packet, set the
1327 * pointer to the first mbuf of the packet and initialize its
1328 * context. Otherwise, update the total length and the number
1329 * of segments of the current scattered packet, and update the
1330 * pointer to the last mbuf of the current packet.
1334 first_seg->nb_segs = 1;
1335 first_seg->pkt_len = rx_packet_len;
1337 first_seg->pkt_len =
1338 (uint16_t)(first_seg->pkt_len +
1340 first_seg->nb_segs++;
1341 last_seg->next = rxm;
1344 /* If this is not the last buffer of the received packet,
1345 * update the pointer to the last mbuf of the current scattered
1346 * packet and continue to parse the RX ring.
1348 if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_EOF_SHIFT))) {
1353 /* This is the last buffer of the received packet. If the CRC
1354 * is not stripped by the hardware:
1355 * - Subtract the CRC length from the total packet length.
1356 * - If the last buffer only contains the whole CRC or a part
1357 * of it, free the mbuf associated to the last buffer. If part
1358 * of the CRC is also contained in the previous mbuf, subtract
1359 * the length of that CRC part from the data length of the
1363 if (unlikely(rxq->crc_len > 0)) {
1364 first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
1365 if (rx_packet_len <= RTE_ETHER_CRC_LEN) {
1366 rte_pktmbuf_free_seg(rxm);
1367 first_seg->nb_segs--;
1368 last_seg->data_len =
1369 (uint16_t)(last_seg->data_len -
1370 (RTE_ETHER_CRC_LEN - rx_packet_len));
1371 last_seg->next = NULL;
1373 rxm->data_len = (uint16_t)(rx_packet_len -
1377 first_seg->port = rxq->port_id;
1378 first_seg->ol_flags = 0;
1379 iavf_rxd_to_vlan_tci(first_seg, &rxd);
1380 pkt_flags = iavf_rxd_to_pkt_flags(qword1);
1381 first_seg->packet_type =
1382 ptype_tbl[(uint8_t)((qword1 &
1383 IAVF_RXD_QW1_PTYPE_MASK) >> IAVF_RXD_QW1_PTYPE_SHIFT)];
1385 if (pkt_flags & PKT_RX_RSS_HASH)
1386 first_seg->hash.rss =
1387 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1389 if (pkt_flags & PKT_RX_FDIR)
1390 pkt_flags |= iavf_rxd_build_fdir(&rxd, first_seg);
1392 first_seg->ol_flags |= pkt_flags;
1394 /* Prefetch data of first segment, if configured to do so. */
1395 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1396 first_seg->data_off));
1397 rx_pkts[nb_rx++] = first_seg;
1401 /* Record index of the next RX descriptor to probe. */
1402 rxq->rx_tail = rx_id;
1403 rxq->pkt_first_seg = first_seg;
1404 rxq->pkt_last_seg = last_seg;
1406 iavf_update_rx_tail(rxq, nb_hold, rx_id);
1411 #define IAVF_LOOK_AHEAD 8
1413 iavf_rx_scan_hw_ring_flex_rxd(struct iavf_rx_queue *rxq)
1415 volatile union iavf_rx_flex_desc *rxdp;
1416 struct rte_mbuf **rxep;
1417 struct rte_mbuf *mb;
1420 int32_t s[IAVF_LOOK_AHEAD], nb_dd;
1421 int32_t i, j, nb_rx = 0;
1423 const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1425 rxdp = (volatile union iavf_rx_flex_desc *)&rxq->rx_ring[rxq->rx_tail];
1426 rxep = &rxq->sw_ring[rxq->rx_tail];
1428 stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1430 /* Make sure there is at least 1 packet to receive */
1431 if (!(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S)))
1434 /* Scan LOOK_AHEAD descriptors at a time to determine which
1435 * descriptors reference packets that are ready to be received.
1437 for (i = 0; i < IAVF_RX_MAX_BURST; i += IAVF_LOOK_AHEAD,
1438 rxdp += IAVF_LOOK_AHEAD, rxep += IAVF_LOOK_AHEAD) {
1439 /* Read desc statuses backwards to avoid race condition */
1440 for (j = IAVF_LOOK_AHEAD - 1; j >= 0; j--)
1441 s[j] = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1445 /* Compute how many status bits were set */
1446 for (j = 0, nb_dd = 0; j < IAVF_LOOK_AHEAD; j++)
1447 nb_dd += s[j] & (1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S);
1451 /* Translate descriptor info to mbuf parameters */
1452 for (j = 0; j < nb_dd; j++) {
1453 IAVF_DUMP_RX_DESC(rxq, &rxdp[j],
1455 i * IAVF_LOOK_AHEAD + j);
1458 pkt_len = (rte_le_to_cpu_16(rxdp[j].wb.pkt_len) &
1459 IAVF_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
1460 mb->data_len = pkt_len;
1461 mb->pkt_len = pkt_len;
1464 mb->packet_type = ptype_tbl[IAVF_RX_FLEX_DESC_PTYPE_M &
1465 rte_le_to_cpu_16(rxdp[j].wb.ptype_flex_flags0)];
1466 iavf_flex_rxd_to_vlan_tci(mb, &rxdp[j]);
1467 iavf_rxd_to_pkt_fields(mb, &rxdp[j]);
1468 stat_err0 = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1469 pkt_flags = iavf_flex_rxd_error_to_pkt_flags(stat_err0);
1471 mb->ol_flags |= pkt_flags;
1474 for (j = 0; j < IAVF_LOOK_AHEAD; j++)
1475 rxq->rx_stage[i + j] = rxep[j];
1477 if (nb_dd != IAVF_LOOK_AHEAD)
1481 /* Clear software ring entries */
1482 for (i = 0; i < nb_rx; i++)
1483 rxq->sw_ring[rxq->rx_tail + i] = NULL;
1489 iavf_rx_scan_hw_ring(struct iavf_rx_queue *rxq)
1491 volatile union iavf_rx_desc *rxdp;
1492 struct rte_mbuf **rxep;
1493 struct rte_mbuf *mb;
1497 int32_t s[IAVF_LOOK_AHEAD], nb_dd;
1498 int32_t i, j, nb_rx = 0;
1500 const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1502 rxdp = &rxq->rx_ring[rxq->rx_tail];
1503 rxep = &rxq->sw_ring[rxq->rx_tail];
1505 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1506 rx_status = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
1507 IAVF_RXD_QW1_STATUS_SHIFT;
1509 /* Make sure there is at least 1 packet to receive */
1510 if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)))
1513 /* Scan LOOK_AHEAD descriptors at a time to determine which
1514 * descriptors reference packets that are ready to be received.
1516 for (i = 0; i < IAVF_RX_MAX_BURST; i += IAVF_LOOK_AHEAD,
1517 rxdp += IAVF_LOOK_AHEAD, rxep += IAVF_LOOK_AHEAD) {
1518 /* Read desc statuses backwards to avoid race condition */
1519 for (j = IAVF_LOOK_AHEAD - 1; j >= 0; j--) {
1520 qword1 = rte_le_to_cpu_64(
1521 rxdp[j].wb.qword1.status_error_len);
1522 s[j] = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
1523 IAVF_RXD_QW1_STATUS_SHIFT;
1528 /* Compute how many status bits were set */
1529 for (j = 0, nb_dd = 0; j < IAVF_LOOK_AHEAD; j++)
1530 nb_dd += s[j] & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT);
1534 /* Translate descriptor info to mbuf parameters */
1535 for (j = 0; j < nb_dd; j++) {
1536 IAVF_DUMP_RX_DESC(rxq, &rxdp[j],
1537 rxq->rx_tail + i * IAVF_LOOK_AHEAD + j);
1540 qword1 = rte_le_to_cpu_64
1541 (rxdp[j].wb.qword1.status_error_len);
1542 pkt_len = ((qword1 & IAVF_RXD_QW1_LENGTH_PBUF_MASK) >>
1543 IAVF_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
1544 mb->data_len = pkt_len;
1545 mb->pkt_len = pkt_len;
1547 iavf_rxd_to_vlan_tci(mb, &rxdp[j]);
1548 pkt_flags = iavf_rxd_to_pkt_flags(qword1);
1550 ptype_tbl[(uint8_t)((qword1 &
1551 IAVF_RXD_QW1_PTYPE_MASK) >>
1552 IAVF_RXD_QW1_PTYPE_SHIFT)];
1554 if (pkt_flags & PKT_RX_RSS_HASH)
1555 mb->hash.rss = rte_le_to_cpu_32(
1556 rxdp[j].wb.qword0.hi_dword.rss);
1558 if (pkt_flags & PKT_RX_FDIR)
1559 pkt_flags |= iavf_rxd_build_fdir(&rxdp[j], mb);
1561 mb->ol_flags |= pkt_flags;
1564 for (j = 0; j < IAVF_LOOK_AHEAD; j++)
1565 rxq->rx_stage[i + j] = rxep[j];
1567 if (nb_dd != IAVF_LOOK_AHEAD)
1571 /* Clear software ring entries */
1572 for (i = 0; i < nb_rx; i++)
1573 rxq->sw_ring[rxq->rx_tail + i] = NULL;
1578 static inline uint16_t
1579 iavf_rx_fill_from_stage(struct iavf_rx_queue *rxq,
1580 struct rte_mbuf **rx_pkts,
1584 struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1586 nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1588 for (i = 0; i < nb_pkts; i++)
1589 rx_pkts[i] = stage[i];
1591 rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1592 rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1598 iavf_rx_alloc_bufs(struct iavf_rx_queue *rxq)
1600 volatile union iavf_rx_desc *rxdp;
1601 struct rte_mbuf **rxep;
1602 struct rte_mbuf *mb;
1603 uint16_t alloc_idx, i;
1607 /* Allocate buffers in bulk */
1608 alloc_idx = (uint16_t)(rxq->rx_free_trigger -
1609 (rxq->rx_free_thresh - 1));
1610 rxep = &rxq->sw_ring[alloc_idx];
1611 diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
1612 rxq->rx_free_thresh);
1613 if (unlikely(diag != 0)) {
1614 PMD_RX_LOG(ERR, "Failed to get mbufs in bulk");
1618 rxdp = &rxq->rx_ring[alloc_idx];
1619 for (i = 0; i < rxq->rx_free_thresh; i++) {
1620 if (likely(i < (rxq->rx_free_thresh - 1)))
1621 /* Prefetch next mbuf */
1622 rte_prefetch0(rxep[i + 1]);
1625 rte_mbuf_refcnt_set(mb, 1);
1627 mb->data_off = RTE_PKTMBUF_HEADROOM;
1629 mb->port = rxq->port_id;
1630 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mb));
1631 rxdp[i].read.hdr_addr = 0;
1632 rxdp[i].read.pkt_addr = dma_addr;
1635 /* Update rx tail register */
1637 IAVF_PCI_REG_WRITE_RELAXED(rxq->qrx_tail, rxq->rx_free_trigger);
1639 rxq->rx_free_trigger =
1640 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
1641 if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1642 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
1647 static inline uint16_t
1648 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1650 struct iavf_rx_queue *rxq = (struct iavf_rx_queue *)rx_queue;
1656 if (rxq->rx_nb_avail)
1657 return iavf_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1659 if (rxq->rxdid == IAVF_RXDID_COMMS_OVS_1)
1660 nb_rx = (uint16_t)iavf_rx_scan_hw_ring_flex_rxd(rxq);
1662 nb_rx = (uint16_t)iavf_rx_scan_hw_ring(rxq);
1663 rxq->rx_next_avail = 0;
1664 rxq->rx_nb_avail = nb_rx;
1665 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1667 if (rxq->rx_tail > rxq->rx_free_trigger) {
1668 if (iavf_rx_alloc_bufs(rxq) != 0) {
1671 /* TODO: count rx_mbuf_alloc_failed here */
1673 rxq->rx_nb_avail = 0;
1674 rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1675 for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
1676 rxq->sw_ring[j] = rxq->rx_stage[i];
1682 if (rxq->rx_tail >= rxq->nb_rx_desc)
1685 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u, nb_rx=%u",
1686 rxq->port_id, rxq->queue_id,
1687 rxq->rx_tail, nb_rx);
1689 if (rxq->rx_nb_avail)
1690 return iavf_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1696 iavf_recv_pkts_bulk_alloc(void *rx_queue,
1697 struct rte_mbuf **rx_pkts,
1700 uint16_t nb_rx = 0, n, count;
1702 if (unlikely(nb_pkts == 0))
1705 if (likely(nb_pkts <= IAVF_RX_MAX_BURST))
1706 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1709 n = RTE_MIN(nb_pkts, IAVF_RX_MAX_BURST);
1710 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1711 nb_rx = (uint16_t)(nb_rx + count);
1712 nb_pkts = (uint16_t)(nb_pkts - count);
1721 iavf_xmit_cleanup(struct iavf_tx_queue *txq)
1723 struct iavf_tx_entry *sw_ring = txq->sw_ring;
1724 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
1725 uint16_t nb_tx_desc = txq->nb_tx_desc;
1726 uint16_t desc_to_clean_to;
1727 uint16_t nb_tx_to_clean;
1729 volatile struct iavf_tx_desc *txd = txq->tx_ring;
1731 desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->rs_thresh);
1732 if (desc_to_clean_to >= nb_tx_desc)
1733 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
1735 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
1736 if ((txd[desc_to_clean_to].cmd_type_offset_bsz &
1737 rte_cpu_to_le_64(IAVF_TXD_QW1_DTYPE_MASK)) !=
1738 rte_cpu_to_le_64(IAVF_TX_DESC_DTYPE_DESC_DONE)) {
1739 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
1740 "(port=%d queue=%d)", desc_to_clean_to,
1741 txq->port_id, txq->queue_id);
1745 if (last_desc_cleaned > desc_to_clean_to)
1746 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
1749 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
1752 txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
1754 txq->last_desc_cleaned = desc_to_clean_to;
1755 txq->nb_free = (uint16_t)(txq->nb_free + nb_tx_to_clean);
1760 /* Check if the context descriptor is needed for TX offloading */
1761 static inline uint16_t
1762 iavf_calc_context_desc(uint64_t flags)
1764 static uint64_t mask = PKT_TX_TCP_SEG;
1766 return (flags & mask) ? 1 : 0;
1770 iavf_txd_enable_checksum(uint64_t ol_flags,
1772 uint32_t *td_offset,
1773 union iavf_tx_offload tx_offload)
1776 *td_offset |= (tx_offload.l2_len >> 1) <<
1777 IAVF_TX_DESC_LENGTH_MACLEN_SHIFT;
1779 /* Enable L3 checksum offloads */
1780 if (ol_flags & PKT_TX_IP_CKSUM) {
1781 *td_cmd |= IAVF_TX_DESC_CMD_IIPT_IPV4_CSUM;
1782 *td_offset |= (tx_offload.l3_len >> 2) <<
1783 IAVF_TX_DESC_LENGTH_IPLEN_SHIFT;
1784 } else if (ol_flags & PKT_TX_IPV4) {
1785 *td_cmd |= IAVF_TX_DESC_CMD_IIPT_IPV4;
1786 *td_offset |= (tx_offload.l3_len >> 2) <<
1787 IAVF_TX_DESC_LENGTH_IPLEN_SHIFT;
1788 } else if (ol_flags & PKT_TX_IPV6) {
1789 *td_cmd |= IAVF_TX_DESC_CMD_IIPT_IPV6;
1790 *td_offset |= (tx_offload.l3_len >> 2) <<
1791 IAVF_TX_DESC_LENGTH_IPLEN_SHIFT;
1794 if (ol_flags & PKT_TX_TCP_SEG) {
1795 *td_cmd |= IAVF_TX_DESC_CMD_L4T_EOFT_TCP;
1796 *td_offset |= (tx_offload.l4_len >> 2) <<
1797 IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1801 /* Enable L4 checksum offloads */
1802 switch (ol_flags & PKT_TX_L4_MASK) {
1803 case PKT_TX_TCP_CKSUM:
1804 *td_cmd |= IAVF_TX_DESC_CMD_L4T_EOFT_TCP;
1805 *td_offset |= (sizeof(struct rte_tcp_hdr) >> 2) <<
1806 IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1808 case PKT_TX_SCTP_CKSUM:
1809 *td_cmd |= IAVF_TX_DESC_CMD_L4T_EOFT_SCTP;
1810 *td_offset |= (sizeof(struct rte_sctp_hdr) >> 2) <<
1811 IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1813 case PKT_TX_UDP_CKSUM:
1814 *td_cmd |= IAVF_TX_DESC_CMD_L4T_EOFT_UDP;
1815 *td_offset |= (sizeof(struct rte_udp_hdr) >> 2) <<
1816 IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1823 /* set TSO context descriptor
1824 * support IP -> L4 and IP -> IP -> L4
1826 static inline uint64_t
1827 iavf_set_tso_ctx(struct rte_mbuf *mbuf, union iavf_tx_offload tx_offload)
1829 uint64_t ctx_desc = 0;
1830 uint32_t cd_cmd, hdr_len, cd_tso_len;
1832 if (!tx_offload.l4_len) {
1833 PMD_TX_LOG(DEBUG, "L4 length set to 0");
1837 hdr_len = tx_offload.l2_len +
1841 cd_cmd = IAVF_TX_CTX_DESC_TSO;
1842 cd_tso_len = mbuf->pkt_len - hdr_len;
1843 ctx_desc |= ((uint64_t)cd_cmd << IAVF_TXD_CTX_QW1_CMD_SHIFT) |
1844 ((uint64_t)cd_tso_len << IAVF_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1845 ((uint64_t)mbuf->tso_segsz << IAVF_TXD_CTX_QW1_MSS_SHIFT);
1850 /* Construct the tx flags */
1851 static inline uint64_t
1852 iavf_build_ctob(uint32_t td_cmd, uint32_t td_offset, unsigned int size,
1855 return rte_cpu_to_le_64(IAVF_TX_DESC_DTYPE_DATA |
1856 ((uint64_t)td_cmd << IAVF_TXD_QW1_CMD_SHIFT) |
1857 ((uint64_t)td_offset <<
1858 IAVF_TXD_QW1_OFFSET_SHIFT) |
1860 IAVF_TXD_QW1_TX_BUF_SZ_SHIFT) |
1861 ((uint64_t)td_tag <<
1862 IAVF_TXD_QW1_L2TAG1_SHIFT));
1867 iavf_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1869 volatile struct iavf_tx_desc *txd;
1870 volatile struct iavf_tx_desc *txr;
1871 struct iavf_tx_queue *txq;
1872 struct iavf_tx_entry *sw_ring;
1873 struct iavf_tx_entry *txe, *txn;
1874 struct rte_mbuf *tx_pkt;
1875 struct rte_mbuf *m_seg;
1886 uint64_t buf_dma_addr;
1887 union iavf_tx_offload tx_offload = {0};
1890 sw_ring = txq->sw_ring;
1892 tx_id = txq->tx_tail;
1893 txe = &sw_ring[tx_id];
1895 /* Check if the descriptor ring needs to be cleaned. */
1896 if (txq->nb_free < txq->free_thresh)
1897 iavf_xmit_cleanup(txq);
1899 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1904 tx_pkt = *tx_pkts++;
1905 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
1907 ol_flags = tx_pkt->ol_flags;
1908 tx_offload.l2_len = tx_pkt->l2_len;
1909 tx_offload.l3_len = tx_pkt->l3_len;
1910 tx_offload.l4_len = tx_pkt->l4_len;
1911 tx_offload.tso_segsz = tx_pkt->tso_segsz;
1913 /* Calculate the number of context descriptors needed. */
1914 nb_ctx = iavf_calc_context_desc(ol_flags);
1916 /* The number of descriptors that must be allocated for
1917 * a packet equals to the number of the segments of that
1918 * packet plus 1 context descriptor if needed.
1920 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
1921 tx_last = (uint16_t)(tx_id + nb_used - 1);
1924 if (tx_last >= txq->nb_tx_desc)
1925 tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
1927 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u"
1928 " tx_first=%u tx_last=%u",
1929 txq->port_id, txq->queue_id, tx_id, tx_last);
1931 if (nb_used > txq->nb_free) {
1932 if (iavf_xmit_cleanup(txq)) {
1937 if (unlikely(nb_used > txq->rs_thresh)) {
1938 while (nb_used > txq->nb_free) {
1939 if (iavf_xmit_cleanup(txq)) {
1948 /* Descriptor based VLAN insertion */
1949 if (ol_flags & PKT_TX_VLAN_PKT) {
1950 td_cmd |= IAVF_TX_DESC_CMD_IL2TAG1;
1951 td_tag = tx_pkt->vlan_tci;
1954 /* According to datasheet, the bit2 is reserved and must be
1959 /* Enable checksum offloading */
1960 if (ol_flags & IAVF_TX_CKSUM_OFFLOAD_MASK)
1961 iavf_txd_enable_checksum(ol_flags, &td_cmd,
1962 &td_offset, tx_offload);
1965 /* Setup TX context descriptor if required */
1966 uint64_t cd_type_cmd_tso_mss =
1967 IAVF_TX_DESC_DTYPE_CONTEXT;
1968 volatile struct iavf_tx_context_desc *ctx_txd =
1969 (volatile struct iavf_tx_context_desc *)
1972 txn = &sw_ring[txe->next_id];
1973 RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
1975 rte_pktmbuf_free_seg(txe->mbuf);
1980 if (ol_flags & PKT_TX_TCP_SEG)
1981 cd_type_cmd_tso_mss |=
1982 iavf_set_tso_ctx(tx_pkt, tx_offload);
1984 ctx_txd->type_cmd_tso_mss =
1985 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
1987 IAVF_DUMP_TX_DESC(txq, &txr[tx_id], tx_id);
1988 txe->last_id = tx_last;
1989 tx_id = txe->next_id;
1996 txn = &sw_ring[txe->next_id];
1999 rte_pktmbuf_free_seg(txe->mbuf);
2002 /* Setup TX Descriptor */
2003 slen = m_seg->data_len;
2004 buf_dma_addr = rte_mbuf_data_iova(m_seg);
2005 txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
2006 txd->cmd_type_offset_bsz = iavf_build_ctob(td_cmd,
2011 IAVF_DUMP_TX_DESC(txq, txd, tx_id);
2012 txe->last_id = tx_last;
2013 tx_id = txe->next_id;
2015 m_seg = m_seg->next;
2018 /* The last packet data descriptor needs End Of Packet (EOP) */
2019 td_cmd |= IAVF_TX_DESC_CMD_EOP;
2020 txq->nb_used = (uint16_t)(txq->nb_used + nb_used);
2021 txq->nb_free = (uint16_t)(txq->nb_free - nb_used);
2023 if (txq->nb_used >= txq->rs_thresh) {
2024 PMD_TX_LOG(DEBUG, "Setting RS bit on TXD id="
2025 "%4u (port=%d queue=%d)",
2026 tx_last, txq->port_id, txq->queue_id);
2028 td_cmd |= IAVF_TX_DESC_CMD_RS;
2030 /* Update txq RS bit counters */
2034 txd->cmd_type_offset_bsz |=
2035 rte_cpu_to_le_64(((uint64_t)td_cmd) <<
2036 IAVF_TXD_QW1_CMD_SHIFT);
2037 IAVF_DUMP_TX_DESC(txq, txd, tx_id);
2043 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
2044 txq->port_id, txq->queue_id, tx_id, nb_tx);
2046 IAVF_PCI_REG_WRITE_RELAXED(txq->qtx_tail, tx_id);
2047 txq->tx_tail = tx_id;
2052 /* TX prep functions */
2054 iavf_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
2061 for (i = 0; i < nb_pkts; i++) {
2063 ol_flags = m->ol_flags;
2065 /* Check condition for nb_segs > IAVF_TX_MAX_MTU_SEG. */
2066 if (!(ol_flags & PKT_TX_TCP_SEG)) {
2067 if (m->nb_segs > IAVF_TX_MAX_MTU_SEG) {
2071 } else if ((m->tso_segsz < IAVF_MIN_TSO_MSS) ||
2072 (m->tso_segsz > IAVF_MAX_TSO_MSS)) {
2073 /* MSS outside the range are considered malicious */
2078 if (ol_flags & IAVF_TX_OFFLOAD_NOTSUP_MASK) {
2079 rte_errno = ENOTSUP;
2083 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
2084 ret = rte_validate_tx_offload(m);
2090 ret = rte_net_intel_cksum_prepare(m);
2100 /* choose rx function*/
2102 iavf_set_rx_function(struct rte_eth_dev *dev)
2104 struct iavf_adapter *adapter =
2105 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2106 struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2108 struct iavf_rx_queue *rxq;
2110 bool use_avx2 = false;
2112 if (!iavf_rx_vec_dev_check(dev)) {
2113 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2114 rxq = dev->data->rx_queues[i];
2115 (void)iavf_rxq_vec_setup(rxq);
2118 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
2119 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1)
2122 if (dev->data->scattered_rx) {
2124 "Using %sVector Scattered Rx (port %d).",
2125 use_avx2 ? "avx2 " : "",
2126 dev->data->port_id);
2127 if (vf->vf_res->vf_cap_flags &
2128 VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC)
2129 dev->rx_pkt_burst = use_avx2 ?
2130 iavf_recv_scattered_pkts_vec_avx2_flex_rxd :
2131 iavf_recv_scattered_pkts_vec_flex_rxd;
2133 dev->rx_pkt_burst = use_avx2 ?
2134 iavf_recv_scattered_pkts_vec_avx2 :
2135 iavf_recv_scattered_pkts_vec;
2137 PMD_DRV_LOG(DEBUG, "Using %sVector Rx (port %d).",
2138 use_avx2 ? "avx2 " : "",
2139 dev->data->port_id);
2140 if (vf->vf_res->vf_cap_flags &
2141 VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC)
2142 dev->rx_pkt_burst = use_avx2 ?
2143 iavf_recv_pkts_vec_avx2_flex_rxd :
2144 iavf_recv_pkts_vec_flex_rxd;
2146 dev->rx_pkt_burst = use_avx2 ?
2147 iavf_recv_pkts_vec_avx2 :
2155 if (dev->data->scattered_rx) {
2156 PMD_DRV_LOG(DEBUG, "Using a Scattered Rx callback (port=%d).",
2157 dev->data->port_id);
2158 if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC)
2159 dev->rx_pkt_burst = iavf_recv_scattered_pkts_flex_rxd;
2161 dev->rx_pkt_burst = iavf_recv_scattered_pkts;
2162 } else if (adapter->rx_bulk_alloc_allowed) {
2163 PMD_DRV_LOG(DEBUG, "Using bulk Rx callback (port=%d).",
2164 dev->data->port_id);
2165 dev->rx_pkt_burst = iavf_recv_pkts_bulk_alloc;
2167 PMD_DRV_LOG(DEBUG, "Using Basic Rx callback (port=%d).",
2168 dev->data->port_id);
2169 if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC)
2170 dev->rx_pkt_burst = iavf_recv_pkts_flex_rxd;
2172 dev->rx_pkt_burst = iavf_recv_pkts;
2176 /* choose tx function*/
2178 iavf_set_tx_function(struct rte_eth_dev *dev)
2181 struct iavf_tx_queue *txq;
2183 bool use_avx2 = false;
2185 if (!iavf_tx_vec_dev_check(dev)) {
2186 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2187 txq = dev->data->tx_queues[i];
2190 iavf_txq_vec_setup(txq);
2193 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
2194 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1)
2197 PMD_DRV_LOG(DEBUG, "Using %sVector Tx (port %d).",
2198 use_avx2 ? "avx2 " : "",
2199 dev->data->port_id);
2200 dev->tx_pkt_burst = use_avx2 ?
2201 iavf_xmit_pkts_vec_avx2 :
2203 dev->tx_pkt_prepare = NULL;
2209 PMD_DRV_LOG(DEBUG, "Using Basic Tx callback (port=%d).",
2210 dev->data->port_id);
2211 dev->tx_pkt_burst = iavf_xmit_pkts;
2212 dev->tx_pkt_prepare = iavf_prep_pkts;
2216 iavf_dev_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2217 struct rte_eth_rxq_info *qinfo)
2219 struct iavf_rx_queue *rxq;
2221 rxq = dev->data->rx_queues[queue_id];
2223 qinfo->mp = rxq->mp;
2224 qinfo->scattered_rx = dev->data->scattered_rx;
2225 qinfo->nb_desc = rxq->nb_rx_desc;
2227 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2228 qinfo->conf.rx_drop_en = true;
2229 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2233 iavf_dev_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2234 struct rte_eth_txq_info *qinfo)
2236 struct iavf_tx_queue *txq;
2238 txq = dev->data->tx_queues[queue_id];
2240 qinfo->nb_desc = txq->nb_tx_desc;
2242 qinfo->conf.tx_free_thresh = txq->free_thresh;
2243 qinfo->conf.tx_rs_thresh = txq->rs_thresh;
2244 qinfo->conf.offloads = txq->offloads;
2245 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2248 /* Get the number of used descriptors of a rx queue */
2250 iavf_dev_rxq_count(struct rte_eth_dev *dev, uint16_t queue_id)
2252 #define IAVF_RXQ_SCAN_INTERVAL 4
2253 volatile union iavf_rx_desc *rxdp;
2254 struct iavf_rx_queue *rxq;
2257 rxq = dev->data->rx_queues[queue_id];
2258 rxdp = &rxq->rx_ring[rxq->rx_tail];
2260 while ((desc < rxq->nb_rx_desc) &&
2261 ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
2262 IAVF_RXD_QW1_STATUS_MASK) >> IAVF_RXD_QW1_STATUS_SHIFT) &
2263 (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)) {
2264 /* Check the DD bit of a rx descriptor of each 4 in a group,
2265 * to avoid checking too frequently and downgrading performance
2268 desc += IAVF_RXQ_SCAN_INTERVAL;
2269 rxdp += IAVF_RXQ_SCAN_INTERVAL;
2270 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
2271 rxdp = &(rxq->rx_ring[rxq->rx_tail +
2272 desc - rxq->nb_rx_desc]);
2279 iavf_dev_rx_desc_status(void *rx_queue, uint16_t offset)
2281 struct iavf_rx_queue *rxq = rx_queue;
2282 volatile uint64_t *status;
2286 if (unlikely(offset >= rxq->nb_rx_desc))
2289 if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
2290 return RTE_ETH_RX_DESC_UNAVAIL;
2292 desc = rxq->rx_tail + offset;
2293 if (desc >= rxq->nb_rx_desc)
2294 desc -= rxq->nb_rx_desc;
2296 status = &rxq->rx_ring[desc].wb.qword1.status_error_len;
2297 mask = rte_le_to_cpu_64((1ULL << IAVF_RX_DESC_STATUS_DD_SHIFT)
2298 << IAVF_RXD_QW1_STATUS_SHIFT);
2300 return RTE_ETH_RX_DESC_DONE;
2302 return RTE_ETH_RX_DESC_AVAIL;
2306 iavf_dev_tx_desc_status(void *tx_queue, uint16_t offset)
2308 struct iavf_tx_queue *txq = tx_queue;
2309 volatile uint64_t *status;
2310 uint64_t mask, expect;
2313 if (unlikely(offset >= txq->nb_tx_desc))
2316 desc = txq->tx_tail + offset;
2317 /* go to next desc that has the RS bit */
2318 desc = ((desc + txq->rs_thresh - 1) / txq->rs_thresh) *
2320 if (desc >= txq->nb_tx_desc) {
2321 desc -= txq->nb_tx_desc;
2322 if (desc >= txq->nb_tx_desc)
2323 desc -= txq->nb_tx_desc;
2326 status = &txq->tx_ring[desc].cmd_type_offset_bsz;
2327 mask = rte_le_to_cpu_64(IAVF_TXD_QW1_DTYPE_MASK);
2328 expect = rte_cpu_to_le_64(
2329 IAVF_TX_DESC_DTYPE_DESC_DONE << IAVF_TXD_QW1_DTYPE_SHIFT);
2330 if ((*status & mask) == expect)
2331 return RTE_ETH_TX_DESC_DONE;
2333 return RTE_ETH_TX_DESC_FULL;
2337 iavf_get_default_ptype_table(void)
2339 static const uint32_t ptype_tbl[IAVF_MAX_PKT_TYPE]
2340 __rte_cache_aligned = {
2343 [1] = RTE_PTYPE_L2_ETHER,
2344 [2] = RTE_PTYPE_L2_ETHER_TIMESYNC,
2345 /* [3] - [5] reserved */
2346 [6] = RTE_PTYPE_L2_ETHER_LLDP,
2347 /* [7] - [10] reserved */
2348 [11] = RTE_PTYPE_L2_ETHER_ARP,
2349 /* [12] - [21] reserved */
2351 /* Non tunneled IPv4 */
2352 [22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2354 [23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2355 RTE_PTYPE_L4_NONFRAG,
2356 [24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2359 [26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2361 [27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2363 [28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2367 [29] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2368 RTE_PTYPE_TUNNEL_IP |
2369 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2370 RTE_PTYPE_INNER_L4_FRAG,
2371 [30] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2372 RTE_PTYPE_TUNNEL_IP |
2373 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2374 RTE_PTYPE_INNER_L4_NONFRAG,
2375 [31] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2376 RTE_PTYPE_TUNNEL_IP |
2377 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2378 RTE_PTYPE_INNER_L4_UDP,
2380 [33] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2381 RTE_PTYPE_TUNNEL_IP |
2382 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2383 RTE_PTYPE_INNER_L4_TCP,
2384 [34] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2385 RTE_PTYPE_TUNNEL_IP |
2386 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2387 RTE_PTYPE_INNER_L4_SCTP,
2388 [35] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2389 RTE_PTYPE_TUNNEL_IP |
2390 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2391 RTE_PTYPE_INNER_L4_ICMP,
2394 [36] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2395 RTE_PTYPE_TUNNEL_IP |
2396 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2397 RTE_PTYPE_INNER_L4_FRAG,
2398 [37] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2399 RTE_PTYPE_TUNNEL_IP |
2400 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2401 RTE_PTYPE_INNER_L4_NONFRAG,
2402 [38] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2403 RTE_PTYPE_TUNNEL_IP |
2404 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2405 RTE_PTYPE_INNER_L4_UDP,
2407 [40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2408 RTE_PTYPE_TUNNEL_IP |
2409 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2410 RTE_PTYPE_INNER_L4_TCP,
2411 [41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2412 RTE_PTYPE_TUNNEL_IP |
2413 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2414 RTE_PTYPE_INNER_L4_SCTP,
2415 [42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2416 RTE_PTYPE_TUNNEL_IP |
2417 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2418 RTE_PTYPE_INNER_L4_ICMP,
2420 /* IPv4 --> GRE/Teredo/VXLAN */
2421 [43] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2422 RTE_PTYPE_TUNNEL_GRENAT,
2424 /* IPv4 --> GRE/Teredo/VXLAN --> IPv4 */
2425 [44] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2426 RTE_PTYPE_TUNNEL_GRENAT |
2427 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2428 RTE_PTYPE_INNER_L4_FRAG,
2429 [45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2430 RTE_PTYPE_TUNNEL_GRENAT |
2431 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2432 RTE_PTYPE_INNER_L4_NONFRAG,
2433 [46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2434 RTE_PTYPE_TUNNEL_GRENAT |
2435 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2436 RTE_PTYPE_INNER_L4_UDP,
2438 [48] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2439 RTE_PTYPE_TUNNEL_GRENAT |
2440 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2441 RTE_PTYPE_INNER_L4_TCP,
2442 [49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2443 RTE_PTYPE_TUNNEL_GRENAT |
2444 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2445 RTE_PTYPE_INNER_L4_SCTP,
2446 [50] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2447 RTE_PTYPE_TUNNEL_GRENAT |
2448 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2449 RTE_PTYPE_INNER_L4_ICMP,
2451 /* IPv4 --> GRE/Teredo/VXLAN --> IPv6 */
2452 [51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2453 RTE_PTYPE_TUNNEL_GRENAT |
2454 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2455 RTE_PTYPE_INNER_L4_FRAG,
2456 [52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2457 RTE_PTYPE_TUNNEL_GRENAT |
2458 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2459 RTE_PTYPE_INNER_L4_NONFRAG,
2460 [53] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2461 RTE_PTYPE_TUNNEL_GRENAT |
2462 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2463 RTE_PTYPE_INNER_L4_UDP,
2465 [55] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2466 RTE_PTYPE_TUNNEL_GRENAT |
2467 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2468 RTE_PTYPE_INNER_L4_TCP,
2469 [56] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2470 RTE_PTYPE_TUNNEL_GRENAT |
2471 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2472 RTE_PTYPE_INNER_L4_SCTP,
2473 [57] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2474 RTE_PTYPE_TUNNEL_GRENAT |
2475 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2476 RTE_PTYPE_INNER_L4_ICMP,
2478 /* IPv4 --> GRE/Teredo/VXLAN --> MAC */
2479 [58] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2480 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
2482 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
2483 [59] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2484 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2485 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2486 RTE_PTYPE_INNER_L4_FRAG,
2487 [60] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2488 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2489 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2490 RTE_PTYPE_INNER_L4_NONFRAG,
2491 [61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2492 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2493 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2494 RTE_PTYPE_INNER_L4_UDP,
2496 [63] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2497 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2498 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2499 RTE_PTYPE_INNER_L4_TCP,
2500 [64] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2501 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2502 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2503 RTE_PTYPE_INNER_L4_SCTP,
2504 [65] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2505 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2506 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2507 RTE_PTYPE_INNER_L4_ICMP,
2509 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
2510 [66] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2511 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2512 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2513 RTE_PTYPE_INNER_L4_FRAG,
2514 [67] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2515 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2516 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2517 RTE_PTYPE_INNER_L4_NONFRAG,
2518 [68] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2519 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2520 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2521 RTE_PTYPE_INNER_L4_UDP,
2523 [70] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2524 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2525 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2526 RTE_PTYPE_INNER_L4_TCP,
2527 [71] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2528 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2529 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2530 RTE_PTYPE_INNER_L4_SCTP,
2531 [72] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2532 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2533 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2534 RTE_PTYPE_INNER_L4_ICMP,
2535 /* [73] - [87] reserved */
2537 /* Non tunneled IPv6 */
2538 [88] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2540 [89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2541 RTE_PTYPE_L4_NONFRAG,
2542 [90] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2545 [92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2547 [93] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2549 [94] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2553 [95] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2554 RTE_PTYPE_TUNNEL_IP |
2555 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2556 RTE_PTYPE_INNER_L4_FRAG,
2557 [96] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2558 RTE_PTYPE_TUNNEL_IP |
2559 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2560 RTE_PTYPE_INNER_L4_NONFRAG,
2561 [97] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2562 RTE_PTYPE_TUNNEL_IP |
2563 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2564 RTE_PTYPE_INNER_L4_UDP,
2566 [99] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2567 RTE_PTYPE_TUNNEL_IP |
2568 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2569 RTE_PTYPE_INNER_L4_TCP,
2570 [100] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2571 RTE_PTYPE_TUNNEL_IP |
2572 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2573 RTE_PTYPE_INNER_L4_SCTP,
2574 [101] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2575 RTE_PTYPE_TUNNEL_IP |
2576 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2577 RTE_PTYPE_INNER_L4_ICMP,
2580 [102] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2581 RTE_PTYPE_TUNNEL_IP |
2582 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2583 RTE_PTYPE_INNER_L4_FRAG,
2584 [103] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2585 RTE_PTYPE_TUNNEL_IP |
2586 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2587 RTE_PTYPE_INNER_L4_NONFRAG,
2588 [104] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2589 RTE_PTYPE_TUNNEL_IP |
2590 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2591 RTE_PTYPE_INNER_L4_UDP,
2592 /* [105] reserved */
2593 [106] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2594 RTE_PTYPE_TUNNEL_IP |
2595 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2596 RTE_PTYPE_INNER_L4_TCP,
2597 [107] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2598 RTE_PTYPE_TUNNEL_IP |
2599 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2600 RTE_PTYPE_INNER_L4_SCTP,
2601 [108] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2602 RTE_PTYPE_TUNNEL_IP |
2603 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2604 RTE_PTYPE_INNER_L4_ICMP,
2606 /* IPv6 --> GRE/Teredo/VXLAN */
2607 [109] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2608 RTE_PTYPE_TUNNEL_GRENAT,
2610 /* IPv6 --> GRE/Teredo/VXLAN --> IPv4 */
2611 [110] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2612 RTE_PTYPE_TUNNEL_GRENAT |
2613 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2614 RTE_PTYPE_INNER_L4_FRAG,
2615 [111] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2616 RTE_PTYPE_TUNNEL_GRENAT |
2617 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2618 RTE_PTYPE_INNER_L4_NONFRAG,
2619 [112] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2620 RTE_PTYPE_TUNNEL_GRENAT |
2621 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2622 RTE_PTYPE_INNER_L4_UDP,
2623 /* [113] reserved */
2624 [114] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2625 RTE_PTYPE_TUNNEL_GRENAT |
2626 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2627 RTE_PTYPE_INNER_L4_TCP,
2628 [115] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2629 RTE_PTYPE_TUNNEL_GRENAT |
2630 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2631 RTE_PTYPE_INNER_L4_SCTP,
2632 [116] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2633 RTE_PTYPE_TUNNEL_GRENAT |
2634 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2635 RTE_PTYPE_INNER_L4_ICMP,
2637 /* IPv6 --> GRE/Teredo/VXLAN --> IPv6 */
2638 [117] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2639 RTE_PTYPE_TUNNEL_GRENAT |
2640 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2641 RTE_PTYPE_INNER_L4_FRAG,
2642 [118] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2643 RTE_PTYPE_TUNNEL_GRENAT |
2644 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2645 RTE_PTYPE_INNER_L4_NONFRAG,
2646 [119] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2647 RTE_PTYPE_TUNNEL_GRENAT |
2648 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2649 RTE_PTYPE_INNER_L4_UDP,
2650 /* [120] reserved */
2651 [121] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2652 RTE_PTYPE_TUNNEL_GRENAT |
2653 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2654 RTE_PTYPE_INNER_L4_TCP,
2655 [122] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2656 RTE_PTYPE_TUNNEL_GRENAT |
2657 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2658 RTE_PTYPE_INNER_L4_SCTP,
2659 [123] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2660 RTE_PTYPE_TUNNEL_GRENAT |
2661 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2662 RTE_PTYPE_INNER_L4_ICMP,
2664 /* IPv6 --> GRE/Teredo/VXLAN --> MAC */
2665 [124] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2666 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
2668 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
2669 [125] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2670 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2671 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2672 RTE_PTYPE_INNER_L4_FRAG,
2673 [126] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2674 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2675 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2676 RTE_PTYPE_INNER_L4_NONFRAG,
2677 [127] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2678 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2679 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2680 RTE_PTYPE_INNER_L4_UDP,
2681 /* [128] reserved */
2682 [129] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2683 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2684 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2685 RTE_PTYPE_INNER_L4_TCP,
2686 [130] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2687 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2688 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2689 RTE_PTYPE_INNER_L4_SCTP,
2690 [131] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2691 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2692 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2693 RTE_PTYPE_INNER_L4_ICMP,
2695 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
2696 [132] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2697 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2698 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2699 RTE_PTYPE_INNER_L4_FRAG,
2700 [133] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2701 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2702 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2703 RTE_PTYPE_INNER_L4_NONFRAG,
2704 [134] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2705 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2706 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2707 RTE_PTYPE_INNER_L4_UDP,
2708 /* [135] reserved */
2709 [136] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2710 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2711 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2712 RTE_PTYPE_INNER_L4_TCP,
2713 [137] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2714 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2715 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2716 RTE_PTYPE_INNER_L4_SCTP,
2717 [138] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2718 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2719 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2720 RTE_PTYPE_INNER_L4_ICMP,
2721 /* [139] - [299] reserved */
2724 [300] = RTE_PTYPE_L2_ETHER_PPPOE,
2725 [301] = RTE_PTYPE_L2_ETHER_PPPOE,
2727 /* PPPoE --> IPv4 */
2728 [302] = RTE_PTYPE_L2_ETHER_PPPOE |
2729 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2731 [303] = RTE_PTYPE_L2_ETHER_PPPOE |
2732 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2733 RTE_PTYPE_L4_NONFRAG,
2734 [304] = RTE_PTYPE_L2_ETHER_PPPOE |
2735 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2737 [305] = RTE_PTYPE_L2_ETHER_PPPOE |
2738 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2740 [306] = RTE_PTYPE_L2_ETHER_PPPOE |
2741 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2743 [307] = RTE_PTYPE_L2_ETHER_PPPOE |
2744 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2747 /* PPPoE --> IPv6 */
2748 [308] = RTE_PTYPE_L2_ETHER_PPPOE |
2749 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2751 [309] = RTE_PTYPE_L2_ETHER_PPPOE |
2752 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2753 RTE_PTYPE_L4_NONFRAG,
2754 [310] = RTE_PTYPE_L2_ETHER_PPPOE |
2755 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2757 [311] = RTE_PTYPE_L2_ETHER_PPPOE |
2758 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2760 [312] = RTE_PTYPE_L2_ETHER_PPPOE |
2761 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2763 [313] = RTE_PTYPE_L2_ETHER_PPPOE |
2764 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2766 /* [314] - [324] reserved */
2768 /* IPv4/IPv6 --> GTPC/GTPU */
2769 [325] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2770 RTE_PTYPE_TUNNEL_GTPC,
2771 [326] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2772 RTE_PTYPE_TUNNEL_GTPC,
2773 [327] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2774 RTE_PTYPE_TUNNEL_GTPC,
2775 [328] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2776 RTE_PTYPE_TUNNEL_GTPC,
2777 [329] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2778 RTE_PTYPE_TUNNEL_GTPU,
2779 [330] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2780 RTE_PTYPE_TUNNEL_GTPU,
2782 /* IPv4 --> GTPU --> IPv4 */
2783 [331] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2784 RTE_PTYPE_TUNNEL_GTPU |
2785 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2786 RTE_PTYPE_INNER_L4_FRAG,
2787 [332] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2788 RTE_PTYPE_TUNNEL_GTPU |
2789 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2790 RTE_PTYPE_INNER_L4_NONFRAG,
2791 [333] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2792 RTE_PTYPE_TUNNEL_GTPU |
2793 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2794 RTE_PTYPE_INNER_L4_UDP,
2795 [334] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2796 RTE_PTYPE_TUNNEL_GTPU |
2797 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2798 RTE_PTYPE_INNER_L4_TCP,
2799 [335] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2800 RTE_PTYPE_TUNNEL_GTPU |
2801 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2802 RTE_PTYPE_INNER_L4_ICMP,
2804 /* IPv6 --> GTPU --> IPv4 */
2805 [336] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2806 RTE_PTYPE_TUNNEL_GTPU |
2807 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2808 RTE_PTYPE_INNER_L4_FRAG,
2809 [337] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2810 RTE_PTYPE_TUNNEL_GTPU |
2811 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2812 RTE_PTYPE_INNER_L4_NONFRAG,
2813 [338] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2814 RTE_PTYPE_TUNNEL_GTPU |
2815 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2816 RTE_PTYPE_INNER_L4_UDP,
2817 [339] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2818 RTE_PTYPE_TUNNEL_GTPU |
2819 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2820 RTE_PTYPE_INNER_L4_TCP,
2821 [340] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2822 RTE_PTYPE_TUNNEL_GTPU |
2823 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2824 RTE_PTYPE_INNER_L4_ICMP,
2826 /* IPv4 --> GTPU --> IPv6 */
2827 [341] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2828 RTE_PTYPE_TUNNEL_GTPU |
2829 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2830 RTE_PTYPE_INNER_L4_FRAG,
2831 [342] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2832 RTE_PTYPE_TUNNEL_GTPU |
2833 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2834 RTE_PTYPE_INNER_L4_NONFRAG,
2835 [343] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2836 RTE_PTYPE_TUNNEL_GTPU |
2837 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2838 RTE_PTYPE_INNER_L4_UDP,
2839 [344] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2840 RTE_PTYPE_TUNNEL_GTPU |
2841 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2842 RTE_PTYPE_INNER_L4_TCP,
2843 [345] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2844 RTE_PTYPE_TUNNEL_GTPU |
2845 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2846 RTE_PTYPE_INNER_L4_ICMP,
2848 /* IPv6 --> GTPU --> IPv6 */
2849 [346] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2850 RTE_PTYPE_TUNNEL_GTPU |
2851 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2852 RTE_PTYPE_INNER_L4_FRAG,
2853 [347] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2854 RTE_PTYPE_TUNNEL_GTPU |
2855 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2856 RTE_PTYPE_INNER_L4_NONFRAG,
2857 [348] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2858 RTE_PTYPE_TUNNEL_GTPU |
2859 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2860 RTE_PTYPE_INNER_L4_UDP,
2861 [349] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2862 RTE_PTYPE_TUNNEL_GTPU |
2863 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2864 RTE_PTYPE_INNER_L4_TCP,
2865 [350] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2866 RTE_PTYPE_TUNNEL_GTPU |
2867 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2868 RTE_PTYPE_INNER_L4_ICMP,
2869 /* All others reserved */