drivers/net/iavf/iavf_rxtx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2017 Intel Corporation
   3  */
   4
   5 #include <stdio.h>
   6 #include <stdlib.h>
   7 #include <string.h>
   8 #include <errno.h>
   9 #include <stdint.h>
  10 #include <stdarg.h>
  11 #include <unistd.h>
  12 #include <inttypes.h>
  13 #include <sys/queue.h>
  14
  15 #include <rte_string_fns.h>
  16 #include <rte_memzone.h>
  17 #include <rte_mbuf.h>
  18 #include <rte_malloc.h>
  19 #include <rte_ether.h>
  20 #include <rte_ethdev_driver.h>
  21 #include <rte_tcp.h>
  22 #include <rte_sctp.h>
  23 #include <rte_udp.h>
  24 #include <rte_ip.h>
  25 #include <rte_net.h>
  26
  27 #include "iavf_log.h"
  28 #include "base/iavf_prototype.h"
  29 #include "base/iavf_type.h"
  30 #include "iavf.h"
  31 #include "iavf_rxtx.h"
  32
  33 static inline int
  34 check_rx_thresh(uint16_t nb_desc, uint16_t thresh)
  35 {
  36         /* The following constraints must be satisfied:
  37          *   thresh < rxq->nb_rx_desc
  38          */
  39         if (thresh >= nb_desc) {
  40                 PMD_INIT_LOG(ERR, "rx_free_thresh (%u) must be less than %u",
  41                              thresh, nb_desc);
  42                 return -EINVAL;
  43         }
  44         return 0;
  45 }
  46
  47 static inline int
  48 check_tx_thresh(uint16_t nb_desc, uint16_t tx_rs_thresh,
  49                 uint16_t tx_free_thresh)
  50 {
  51         /* TX descriptors will have their RS bit set after tx_rs_thresh
  52          * descriptors have been used. The TX descriptor ring will be cleaned
  53          * after tx_free_thresh descriptors are used or if the number of
  54          * descriptors required to transmit a packet is greater than the
  55          * number of free TX descriptors.
  56          *
  57          * The following constraints must be satisfied:
  58          *  - tx_rs_thresh must be less than the size of the ring minus 2.
  59          *  - tx_free_thresh must be less than the size of the ring minus 3.
  60          *  - tx_rs_thresh must be less than or equal to tx_free_thresh.
  61          *  - tx_rs_thresh must be a divisor of the ring size.
  62          *
  63          * One descriptor in the TX ring is used as a sentinel to avoid a H/W
  64          * race condition, hence the maximum threshold constraints. When set
  65          * to zero use default values.
  66          */
  67         if (tx_rs_thresh >= (nb_desc - 2)) {
  68                 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be less than the "
  69                              "number of TX descriptors (%u) minus 2",
  70                              tx_rs_thresh, nb_desc);
  71                 return -EINVAL;
  72         }
  73         if (tx_free_thresh >= (nb_desc - 3)) {
  74                 PMD_INIT_LOG(ERR, "tx_free_thresh (%u) must be less than the "
  75                              "number of TX descriptors (%u) minus 3.",
  76                              tx_free_thresh, nb_desc);
  77                 return -EINVAL;
  78         }
  79         if (tx_rs_thresh > tx_free_thresh) {
  80                 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be less than or "
  81                              "equal to tx_free_thresh (%u).",
  82                              tx_rs_thresh, tx_free_thresh);
  83                 return -EINVAL;
  84         }
  85         if ((nb_desc % tx_rs_thresh) != 0) {
  86                 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be a divisor of the "
  87                              "number of TX descriptors (%u).",
  88                              tx_rs_thresh, nb_desc);
  89                 return -EINVAL;
  90         }
  91
  92         return 0;
  93 }
  94
  95 static inline bool
  96 check_rx_vec_allow(struct iavf_rx_queue *rxq)
  97 {
  98         if (rxq->rx_free_thresh >= IAVF_VPMD_RX_MAX_BURST &&
  99             rxq->nb_rx_desc % rxq->rx_free_thresh == 0) {
 100                 PMD_INIT_LOG(DEBUG, "Vector Rx can be enabled on this rxq.");
 101                 return TRUE;
 102         }
 103
 104         PMD_INIT_LOG(DEBUG, "Vector Rx cannot be enabled on this rxq.");
 105         return FALSE;
 106 }
 107
 108 static inline bool
 109 check_tx_vec_allow(struct iavf_tx_queue *txq)
 110 {
 111         if (!(txq->offloads & IAVF_NO_VECTOR_FLAGS) &&
 112             txq->rs_thresh >= IAVF_VPMD_TX_MAX_BURST &&
 113             txq->rs_thresh <= IAVF_VPMD_TX_MAX_FREE_BUF) {
 114                 PMD_INIT_LOG(DEBUG, "Vector tx can be enabled on this txq.");
 115                 return TRUE;
 116         }
 117         PMD_INIT_LOG(DEBUG, "Vector Tx cannot be enabled on this txq.");
 118         return FALSE;
 119 }
 120
 121 static inline bool
 122 check_rx_bulk_allow(struct iavf_rx_queue *rxq)
 123 {
 124         int ret = TRUE;
 125
 126         if (!(rxq->rx_free_thresh >= IAVF_RX_MAX_BURST)) {
 127                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 128                              "rxq->rx_free_thresh=%d, "
 129                              "IAVF_RX_MAX_BURST=%d",
 130                              rxq->rx_free_thresh, IAVF_RX_MAX_BURST);
 131                 ret = FALSE;
 132         } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
 133                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 134                              "rxq->nb_rx_desc=%d, "
 135                              "rxq->rx_free_thresh=%d",
 136                              rxq->nb_rx_desc, rxq->rx_free_thresh);
 137                 ret = FALSE;
 138         }
 139         return ret;
 140 }
 141
 142 static inline void
 143 reset_rx_queue(struct iavf_rx_queue *rxq)
 144 {
 145         uint16_t len;
 146         uint32_t i;
 147
 148         if (!rxq)
 149                 return;
 150
 151         len = rxq->nb_rx_desc + IAVF_RX_MAX_BURST;
 152
 153         for (i = 0; i < len * sizeof(union iavf_rx_desc); i++)
 154                 ((volatile char *)rxq->rx_ring)[i] = 0;
 155
 156         memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
 157
 158         for (i = 0; i < IAVF_RX_MAX_BURST; i++)
 159                 rxq->sw_ring[rxq->nb_rx_desc + i] = &rxq->fake_mbuf;
 160
 161         /* for rx bulk */
 162         rxq->rx_nb_avail = 0;
 163         rxq->rx_next_avail = 0;
 164         rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
 165
 166         rxq->rx_tail = 0;
 167         rxq->nb_rx_hold = 0;
 168         rxq->pkt_first_seg = NULL;
 169         rxq->pkt_last_seg = NULL;
 170 }
 171
 172 static inline void
 173 reset_tx_queue(struct iavf_tx_queue *txq)
 174 {
 175         struct iavf_tx_entry *txe;
 176         uint32_t i, size;
 177         uint16_t prev;
 178
 179         if (!txq) {
 180                 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
 181                 return;
 182         }
 183
 184         txe = txq->sw_ring;
 185         size = sizeof(struct iavf_tx_desc) * txq->nb_tx_desc;
 186         for (i = 0; i < size; i++)
 187                 ((volatile char *)txq->tx_ring)[i] = 0;
 188
 189         prev = (uint16_t)(txq->nb_tx_desc - 1);
 190         for (i = 0; i < txq->nb_tx_desc; i++) {
 191                 txq->tx_ring[i].cmd_type_offset_bsz =
 192                         rte_cpu_to_le_64(IAVF_TX_DESC_DTYPE_DESC_DONE);
 193                 txe[i].mbuf =  NULL;
 194                 txe[i].last_id = i;
 195                 txe[prev].next_id = i;
 196                 prev = i;
 197         }
 198
 199         txq->tx_tail = 0;
 200         txq->nb_used = 0;
 201
 202         txq->last_desc_cleaned = txq->nb_tx_desc - 1;
 203         txq->nb_free = txq->nb_tx_desc - 1;
 204
 205         txq->next_dd = txq->rs_thresh - 1;
 206         txq->next_rs = txq->rs_thresh - 1;
 207 }
 208
 209 static int
 210 alloc_rxq_mbufs(struct iavf_rx_queue *rxq)
 211 {
 212         volatile union iavf_rx_desc *rxd;
 213         struct rte_mbuf *mbuf = NULL;
 214         uint64_t dma_addr;
 215         uint16_t i;
 216
 217         for (i = 0; i < rxq->nb_rx_desc; i++) {
 218                 mbuf = rte_mbuf_raw_alloc(rxq->mp);
 219                 if (unlikely(!mbuf)) {
 220                         PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
 221                         return -ENOMEM;
 222                 }
 223
 224                 rte_mbuf_refcnt_set(mbuf, 1);
 225                 mbuf->next = NULL;
 226                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
 227                 mbuf->nb_segs = 1;
 228                 mbuf->port = rxq->port_id;
 229
 230                 dma_addr =
 231                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
 232
 233                 rxd = &rxq->rx_ring[i];
 234                 rxd->read.pkt_addr = dma_addr;
 235                 rxd->read.hdr_addr = 0;
 236 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
 237                 rxd->read.rsvd1 = 0;
 238                 rxd->read.rsvd2 = 0;
 239 #endif
 240
 241                 rxq->sw_ring[i] = mbuf;
 242         }
 243
 244         return 0;
 245 }
 246
 247 static inline void
 248 release_rxq_mbufs(struct iavf_rx_queue *rxq)
 249 {
 250         uint16_t i;
 251
 252         if (!rxq->sw_ring)
 253                 return;
 254
 255         for (i = 0; i < rxq->nb_rx_desc; i++) {
 256                 if (rxq->sw_ring[i]) {
 257                         rte_pktmbuf_free_seg(rxq->sw_ring[i]);
 258                         rxq->sw_ring[i] = NULL;
 259                 }
 260         }
 261
 262         /* for rx bulk */
 263         if (rxq->rx_nb_avail == 0)
 264                 return;
 265         for (i = 0; i < rxq->rx_nb_avail; i++) {
 266                 struct rte_mbuf *mbuf;
 267
 268                 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
 269                 rte_pktmbuf_free_seg(mbuf);
 270         }
 271         rxq->rx_nb_avail = 0;
 272 }
 273
 274 static inline void
 275 release_txq_mbufs(struct iavf_tx_queue *txq)
 276 {
 277         uint16_t i;
 278
 279         if (!txq || !txq->sw_ring) {
 280                 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
 281                 return;
 282         }
 283
 284         for (i = 0; i < txq->nb_tx_desc; i++) {
 285                 if (txq->sw_ring[i].mbuf) {
 286                         rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
 287                         txq->sw_ring[i].mbuf = NULL;
 288                 }
 289         }
 290 }
 291
 292 static const struct iavf_rxq_ops def_rxq_ops = {
 293         .release_mbufs = release_rxq_mbufs,
 294 };
 295
 296 static const struct iavf_txq_ops def_txq_ops = {
 297         .release_mbufs = release_txq_mbufs,
 298 };
 299
 300 int
 301 iavf_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 302                        uint16_t nb_desc, unsigned int socket_id,
 303                        const struct rte_eth_rxconf *rx_conf,
 304                        struct rte_mempool *mp)
 305 {
 306         struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 307         struct iavf_adapter *ad =
 308                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 309         struct iavf_rx_queue *rxq;
 310         const struct rte_memzone *mz;
 311         uint32_t ring_size;
 312         uint16_t len;
 313         uint16_t rx_free_thresh;
 314
 315         PMD_INIT_FUNC_TRACE();
 316
 317         if (nb_desc % IAVF_ALIGN_RING_DESC != 0 ||
 318             nb_desc > IAVF_MAX_RING_DESC ||
 319             nb_desc < IAVF_MIN_RING_DESC) {
 320                 PMD_INIT_LOG(ERR, "Number (%u) of receive descriptors is "
 321                              "invalid", nb_desc);
 322                 return -EINVAL;
 323         }
 324
 325         /* Check free threshold */
 326         rx_free_thresh = (rx_conf->rx_free_thresh == 0) ?
 327                          IAVF_DEFAULT_RX_FREE_THRESH :
 328                          rx_conf->rx_free_thresh;
 329         if (check_rx_thresh(nb_desc, rx_free_thresh) != 0)
 330                 return -EINVAL;
 331
 332         /* Free memory if needed */
 333         if (dev->data->rx_queues[queue_idx]) {
 334                 iavf_dev_rx_queue_release(dev->data->rx_queues[queue_idx]);
 335                 dev->data->rx_queues[queue_idx] = NULL;
 336         }
 337
 338         /* Allocate the rx queue data structure */
 339         rxq = rte_zmalloc_socket("iavf rxq",
 340                                  sizeof(struct iavf_rx_queue),
 341                                  RTE_CACHE_LINE_SIZE,
 342                                  socket_id);
 343         if (!rxq) {
 344                 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
 345                              "rx queue data structure");
 346                 return -ENOMEM;
 347         }
 348
 349         rxq->mp = mp;
 350         rxq->nb_rx_desc = nb_desc;
 351         rxq->rx_free_thresh = rx_free_thresh;
 352         rxq->queue_id = queue_idx;
 353         rxq->port_id = dev->data->port_id;
 354         rxq->crc_len = 0; /* crc stripping by default */
 355         rxq->rx_deferred_start = rx_conf->rx_deferred_start;
 356         rxq->rx_hdr_len = 0;
 357
 358         len = rte_pktmbuf_data_room_size(rxq->mp) - RTE_PKTMBUF_HEADROOM;
 359         rxq->rx_buf_len = RTE_ALIGN(len, (1 << IAVF_RXQ_CTX_DBUFF_SHIFT));
 360
 361         /* Allocate the software ring. */
 362         len = nb_desc + IAVF_RX_MAX_BURST;
 363         rxq->sw_ring =
 364                 rte_zmalloc_socket("iavf rx sw ring",
 365                                    sizeof(struct rte_mbuf *) * len,
 366                                    RTE_CACHE_LINE_SIZE,
 367                                    socket_id);
 368         if (!rxq->sw_ring) {
 369                 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW ring");
 370                 rte_free(rxq);
 371                 return -ENOMEM;
 372         }
 373
 374         /* Allocate the maximun number of RX ring hardware descriptor with
 375          * a liitle more to support bulk allocate.
 376          */
 377         len = IAVF_MAX_RING_DESC + IAVF_RX_MAX_BURST;
 378         ring_size = RTE_ALIGN(len * sizeof(union iavf_rx_desc),
 379                               IAVF_DMA_MEM_ALIGN);
 380         mz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
 381                                       ring_size, IAVF_RING_BASE_ALIGN,
 382                                       socket_id);
 383         if (!mz) {
 384                 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for RX");
 385                 rte_free(rxq->sw_ring);
 386                 rte_free(rxq);
 387                 return -ENOMEM;
 388         }
 389         /* Zero all the descriptors in the ring. */
 390         memset(mz->addr, 0, ring_size);
 391         rxq->rx_ring_phys_addr = mz->iova;
 392         rxq->rx_ring = (union iavf_rx_desc *)mz->addr;
 393
 394         rxq->mz = mz;
 395         reset_rx_queue(rxq);
 396         rxq->q_set = TRUE;
 397         dev->data->rx_queues[queue_idx] = rxq;
 398         rxq->qrx_tail = hw->hw_addr + IAVF_QRX_TAIL1(rxq->queue_id);
 399         rxq->ops = &def_rxq_ops;
 400
 401         if (check_rx_bulk_allow(rxq) == TRUE) {
 402                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
 403                              "satisfied. Rx Burst Bulk Alloc function will be "
 404                              "used on port=%d, queue=%d.",
 405                              rxq->port_id, rxq->queue_id);
 406         } else {
 407                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
 408                              "not satisfied, Scattered Rx is requested "
 409                              "on port=%d, queue=%d.",
 410                              rxq->port_id, rxq->queue_id);
 411                 ad->rx_bulk_alloc_allowed = false;
 412         }
 413
 414         if (check_rx_vec_allow(rxq) == FALSE)
 415                 ad->rx_vec_allowed = false;
 416
 417         return 0;
 418 }
 419
 420 int
 421 iavf_dev_tx_queue_setup(struct rte_eth_dev *dev,
 422                        uint16_t queue_idx,
 423                        uint16_t nb_desc,
 424                        unsigned int socket_id,
 425                        const struct rte_eth_txconf *tx_conf)
 426 {
 427         struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 428         struct iavf_tx_queue *txq;
 429         const struct rte_memzone *mz;
 430         uint32_t ring_size;
 431         uint16_t tx_rs_thresh, tx_free_thresh;
 432         uint64_t offloads;
 433
 434         PMD_INIT_FUNC_TRACE();
 435
 436         offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
 437
 438         if (nb_desc % IAVF_ALIGN_RING_DESC != 0 ||
 439             nb_desc > IAVF_MAX_RING_DESC ||
 440             nb_desc < IAVF_MIN_RING_DESC) {
 441                 PMD_INIT_LOG(ERR, "Number (%u) of transmit descriptors is "
 442                             "invalid", nb_desc);
 443                 return -EINVAL;
 444         }
 445
 446         tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
 447                 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
 448         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
 449                 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
 450         check_tx_thresh(nb_desc, tx_rs_thresh, tx_rs_thresh);
 451
 452         /* Free memory if needed. */
 453         if (dev->data->tx_queues[queue_idx]) {
 454                 iavf_dev_tx_queue_release(dev->data->tx_queues[queue_idx]);
 455                 dev->data->tx_queues[queue_idx] = NULL;
 456         }
 457
 458         /* Allocate the TX queue data structure. */
 459         txq = rte_zmalloc_socket("iavf txq",
 460                                  sizeof(struct iavf_tx_queue),
 461                                  RTE_CACHE_LINE_SIZE,
 462                                  socket_id);
 463         if (!txq) {
 464                 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
 465                              "tx queue structure");
 466                 return -ENOMEM;
 467         }
 468
 469         txq->nb_tx_desc = nb_desc;
 470         txq->rs_thresh = tx_rs_thresh;
 471         txq->free_thresh = tx_free_thresh;
 472         txq->queue_id = queue_idx;
 473         txq->port_id = dev->data->port_id;
 474         txq->offloads = offloads;
 475         txq->tx_deferred_start = tx_conf->tx_deferred_start;
 476
 477         /* Allocate software ring */
 478         txq->sw_ring =
 479                 rte_zmalloc_socket("iavf tx sw ring",
 480                                    sizeof(struct iavf_tx_entry) * nb_desc,
 481                                    RTE_CACHE_LINE_SIZE,
 482                                    socket_id);
 483         if (!txq->sw_ring) {
 484                 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW TX ring");
 485                 rte_free(txq);
 486                 return -ENOMEM;
 487         }
 488
 489         /* Allocate TX hardware ring descriptors. */
 490         ring_size = sizeof(struct iavf_tx_desc) * IAVF_MAX_RING_DESC;
 491         ring_size = RTE_ALIGN(ring_size, IAVF_DMA_MEM_ALIGN);
 492         mz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
 493                                       ring_size, IAVF_RING_BASE_ALIGN,
 494                                       socket_id);
 495         if (!mz) {
 496                 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for TX");
 497                 rte_free(txq->sw_ring);
 498                 rte_free(txq);
 499                 return -ENOMEM;
 500         }
 501         txq->tx_ring_phys_addr = mz->iova;
 502         txq->tx_ring = (struct iavf_tx_desc *)mz->addr;
 503
 504         txq->mz = mz;
 505         reset_tx_queue(txq);
 506         txq->q_set = TRUE;
 507         dev->data->tx_queues[queue_idx] = txq;
 508         txq->qtx_tail = hw->hw_addr + IAVF_QTX_TAIL1(queue_idx);
 509         txq->ops = &def_txq_ops;
 510
 511         if (check_tx_vec_allow(txq) == FALSE) {
 512                 struct iavf_adapter *ad =
 513                         IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 514                 ad->tx_vec_allowed = false;
 515         }
 516
 517         return 0;
 518 }
 519
 520 int
 521 iavf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 522 {
 523         struct iavf_adapter *adapter =
 524                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 525         struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 526         struct iavf_rx_queue *rxq;
 527         int err = 0;
 528
 529         PMD_DRV_FUNC_TRACE();
 530
 531         if (rx_queue_id >= dev->data->nb_rx_queues)
 532                 return -EINVAL;
 533
 534         rxq = dev->data->rx_queues[rx_queue_id];
 535
 536         err = alloc_rxq_mbufs(rxq);
 537         if (err) {
 538                 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
 539                 return err;
 540         }
 541
 542         rte_wmb();
 543
 544         /* Init the RX tail register. */
 545         IAVF_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 546         IAVF_WRITE_FLUSH(hw);
 547
 548         /* Ready to switch the queue on */
 549         err = iavf_switch_queue(adapter, rx_queue_id, TRUE, TRUE);
 550         if (err)
 551                 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
 552                             rx_queue_id);
 553         else
 554                 dev->data->rx_queue_state[rx_queue_id] =
 555                         RTE_ETH_QUEUE_STATE_STARTED;
 556
 557         return err;
 558 }
 559
 560 int
 561 iavf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 562 {
 563         struct iavf_adapter *adapter =
 564                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 565         struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 566         struct iavf_tx_queue *txq;
 567         int err = 0;
 568
 569         PMD_DRV_FUNC_TRACE();
 570
 571         if (tx_queue_id >= dev->data->nb_tx_queues)
 572                 return -EINVAL;
 573
 574         txq = dev->data->tx_queues[tx_queue_id];
 575
 576         /* Init the RX tail register. */
 577         IAVF_PCI_REG_WRITE(txq->qtx_tail, 0);
 578         IAVF_WRITE_FLUSH(hw);
 579
 580         /* Ready to switch the queue on */
 581         err = iavf_switch_queue(adapter, tx_queue_id, FALSE, TRUE);
 582
 583         if (err)
 584                 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
 585                             tx_queue_id);
 586         else
 587                 dev->data->tx_queue_state[tx_queue_id] =
 588                         RTE_ETH_QUEUE_STATE_STARTED;
 589
 590         return err;
 591 }
 592
 593 int
 594 iavf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 595 {
 596         struct iavf_adapter *adapter =
 597                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 598         struct iavf_rx_queue *rxq;
 599         int err;
 600
 601         PMD_DRV_FUNC_TRACE();
 602
 603         if (rx_queue_id >= dev->data->nb_rx_queues)
 604                 return -EINVAL;
 605
 606         err = iavf_switch_queue(adapter, rx_queue_id, TRUE, FALSE);
 607         if (err) {
 608                 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
 609                             rx_queue_id);
 610                 return err;
 611         }
 612
 613         rxq = dev->data->rx_queues[rx_queue_id];
 614         rxq->ops->release_mbufs(rxq);
 615         reset_rx_queue(rxq);
 616         dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 617
 618         return 0;
 619 }
 620
 621 int
 622 iavf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 623 {
 624         struct iavf_adapter *adapter =
 625                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 626         struct iavf_tx_queue *txq;
 627         int err;
 628
 629         PMD_DRV_FUNC_TRACE();
 630
 631         if (tx_queue_id >= dev->data->nb_tx_queues)
 632                 return -EINVAL;
 633
 634         err = iavf_switch_queue(adapter, tx_queue_id, FALSE, FALSE);
 635         if (err) {
 636                 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u off",
 637                             tx_queue_id);
 638                 return err;
 639         }
 640
 641         txq = dev->data->tx_queues[tx_queue_id];
 642         txq->ops->release_mbufs(txq);
 643         reset_tx_queue(txq);
 644         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 645
 646         return 0;
 647 }
 648
 649 void
 650 iavf_dev_rx_queue_release(void *rxq)
 651 {
 652         struct iavf_rx_queue *q = (struct iavf_rx_queue *)rxq;
 653
 654         if (!q)
 655                 return;
 656
 657         q->ops->release_mbufs(q);
 658         rte_free(q->sw_ring);
 659         rte_memzone_free(q->mz);
 660         rte_free(q);
 661 }
 662
 663 void
 664 iavf_dev_tx_queue_release(void *txq)
 665 {
 666         struct iavf_tx_queue *q = (struct iavf_tx_queue *)txq;
 667
 668         if (!q)
 669                 return;
 670
 671         q->ops->release_mbufs(q);
 672         rte_free(q->sw_ring);
 673         rte_memzone_free(q->mz);
 674         rte_free(q);
 675 }
 676
 677 void
 678 iavf_stop_queues(struct rte_eth_dev *dev)
 679 {
 680         struct iavf_adapter *adapter =
 681                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 682         struct iavf_rx_queue *rxq;
 683         struct iavf_tx_queue *txq;
 684         int ret, i;
 685
 686         /* Stop All queues */
 687         ret = iavf_disable_queues(adapter);
 688         if (ret)
 689                 PMD_DRV_LOG(WARNING, "Fail to stop queues");
 690
 691         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 692                 txq = dev->data->tx_queues[i];
 693                 if (!txq)
 694                         continue;
 695                 txq->ops->release_mbufs(txq);
 696                 reset_tx_queue(txq);
 697                 dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED;
 698         }
 699         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 700                 rxq = dev->data->rx_queues[i];
 701                 if (!rxq)
 702                         continue;
 703                 rxq->ops->release_mbufs(rxq);
 704                 reset_rx_queue(rxq);
 705                 dev->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED;
 706         }
 707 }
 708
 709 static inline void
 710 iavf_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union iavf_rx_desc *rxdp)
 711 {
 712         if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
 713                 (1 << IAVF_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
 714                 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
 715                 mb->vlan_tci =
 716                         rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
 717         } else {
 718                 mb->vlan_tci = 0;
 719         }
 720 }
 721
 722 /* Translate the rx descriptor status and error fields to pkt flags */
 723 static inline uint64_t
 724 iavf_rxd_to_pkt_flags(uint64_t qword)
 725 {
 726         uint64_t flags;
 727         uint64_t error_bits = (qword >> IAVF_RXD_QW1_ERROR_SHIFT);
 728
 729 #define IAVF_RX_ERR_BITS 0x3f
 730
 731         /* Check if RSS_HASH */
 732         flags = (((qword >> IAVF_RX_DESC_STATUS_FLTSTAT_SHIFT) &
 733                                         IAVF_RX_DESC_FLTSTAT_RSS_HASH) ==
 734                         IAVF_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;
 735
 736         if (likely((error_bits & IAVF_RX_ERR_BITS) == 0)) {
 737                 flags |= (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD);
 738                 return flags;
 739         }
 740
 741         if (unlikely(error_bits & (1 << IAVF_RX_DESC_ERROR_IPE_SHIFT)))
 742                 flags |= PKT_RX_IP_CKSUM_BAD;
 743         else
 744                 flags |= PKT_RX_IP_CKSUM_GOOD;
 745
 746         if (unlikely(error_bits & (1 << IAVF_RX_DESC_ERROR_L4E_SHIFT)))
 747                 flags |= PKT_RX_L4_CKSUM_BAD;
 748         else
 749                 flags |= PKT_RX_L4_CKSUM_GOOD;
 750
 751         /* TODO: Oversize error bit is not processed here */
 752
 753         return flags;
 754 }
 755
 756 /* implement recv_pkts */
 757 uint16_t
 758 iavf_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 759 {
 760         volatile union iavf_rx_desc *rx_ring;
 761         volatile union iavf_rx_desc *rxdp;
 762         struct iavf_rx_queue *rxq;
 763         union iavf_rx_desc rxd;
 764         struct rte_mbuf *rxe;
 765         struct rte_eth_dev *dev;
 766         struct rte_mbuf *rxm;
 767         struct rte_mbuf *nmb;
 768         uint16_t nb_rx;
 769         uint32_t rx_status;
 770         uint64_t qword1;
 771         uint16_t rx_packet_len;
 772         uint16_t rx_id, nb_hold;
 773         uint64_t dma_addr;
 774         uint64_t pkt_flags;
 775         static const uint32_t ptype_tbl[UINT8_MAX + 1] __rte_cache_aligned = {
 776                 /* [0] reserved */
 777                 [1] = RTE_PTYPE_L2_ETHER,
 778                 /* [2] - [21] reserved */
 779                 [22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 780                         RTE_PTYPE_L4_FRAG,
 781                 [23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 782                         RTE_PTYPE_L4_NONFRAG,
 783                 [24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 784                         RTE_PTYPE_L4_UDP,
 785                 /* [25] reserved */
 786                 [26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 787                         RTE_PTYPE_L4_TCP,
 788                 [27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 789                         RTE_PTYPE_L4_SCTP,
 790                 [28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 791                         RTE_PTYPE_L4_ICMP,
 792                 /* All others reserved */
 793         };
 794
 795         nb_rx = 0;
 796         nb_hold = 0;
 797         rxq = rx_queue;
 798         rx_id = rxq->rx_tail;
 799         rx_ring = rxq->rx_ring;
 800
 801         while (nb_rx < nb_pkts) {
 802                 rxdp = &rx_ring[rx_id];
 803                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 804                 rx_status = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
 805                             IAVF_RXD_QW1_STATUS_SHIFT;
 806
 807                 /* Check the DD bit first */
 808                 if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)))
 809                         break;
 810                 IAVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
 811
 812                 nmb = rte_mbuf_raw_alloc(rxq->mp);
 813                 if (unlikely(!nmb)) {
 814                         dev = &rte_eth_devices[rxq->port_id];
 815                         dev->data->rx_mbuf_alloc_failed++;
 816                         PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
 817                                    "queue_id=%u", rxq->port_id, rxq->queue_id);
 818                         break;
 819                 }
 820
 821                 rxd = *rxdp;
 822                 nb_hold++;
 823                 rxe = rxq->sw_ring[rx_id];
 824                 rx_id++;
 825                 if (unlikely(rx_id == rxq->nb_rx_desc))
 826                         rx_id = 0;
 827
 828                 /* Prefetch next mbuf */
 829                 rte_prefetch0(rxq->sw_ring[rx_id]);
 830
 831                 /* When next RX descriptor is on a cache line boundary,
 832                  * prefetch the next 4 RX descriptors and next 8 pointers
 833                  * to mbufs.
 834                  */
 835                 if ((rx_id & 0x3) == 0) {
 836                         rte_prefetch0(&rx_ring[rx_id]);
 837                         rte_prefetch0(rxq->sw_ring[rx_id]);
 838                 }
 839                 rxm = rxe;
 840                 rxe = nmb;
 841                 dma_addr =
 842                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
 843                 rxdp->read.hdr_addr = 0;
 844                 rxdp->read.pkt_addr = dma_addr;
 845
 846                 rx_packet_len = ((qword1 & IAVF_RXD_QW1_LENGTH_PBUF_MASK) >>
 847                                 IAVF_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
 848
 849                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
 850                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
 851                 rxm->nb_segs = 1;
 852                 rxm->next = NULL;
 853                 rxm->pkt_len = rx_packet_len;
 854                 rxm->data_len = rx_packet_len;
 855                 rxm->port = rxq->port_id;
 856                 rxm->ol_flags = 0;
 857                 iavf_rxd_to_vlan_tci(rxm, &rxd);
 858                 pkt_flags = iavf_rxd_to_pkt_flags(qword1);
 859                 rxm->packet_type =
 860                         ptype_tbl[(uint8_t)((qword1 &
 861                         IAVF_RXD_QW1_PTYPE_MASK) >> IAVF_RXD_QW1_PTYPE_SHIFT)];
 862
 863                 if (pkt_flags & PKT_RX_RSS_HASH)
 864                         rxm->hash.rss =
 865                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
 866
 867                 rxm->ol_flags |= pkt_flags;
 868
 869                 rx_pkts[nb_rx++] = rxm;
 870         }
 871         rxq->rx_tail = rx_id;
 872
 873         /* If the number of free RX descriptors is greater than the RX free
 874          * threshold of the queue, advance the receive tail register of queue.
 875          * Update that register with the value of the last processed RX
 876          * descriptor minus 1.
 877          */
 878         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
 879         if (nb_hold > rxq->rx_free_thresh) {
 880                 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
 881                            "nb_hold=%u nb_rx=%u",
 882                            rxq->port_id, rxq->queue_id,
 883                            rx_id, nb_hold, nb_rx);
 884                 rx_id = (uint16_t)((rx_id == 0) ?
 885                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
 886                 IAVF_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
 887                 nb_hold = 0;
 888         }
 889         rxq->nb_rx_hold = nb_hold;
 890
 891         return nb_rx;
 892 }
 893
 894 /* implement recv_scattered_pkts  */
 895 uint16_t
 896 iavf_recv_scattered_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
 897                         uint16_t nb_pkts)
 898 {
 899         struct iavf_rx_queue *rxq = rx_queue;
 900         union iavf_rx_desc rxd;
 901         struct rte_mbuf *rxe;
 902         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
 903         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
 904         struct rte_mbuf *nmb, *rxm;
 905         uint16_t rx_id = rxq->rx_tail;
 906         uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
 907         struct rte_eth_dev *dev;
 908         uint32_t rx_status;
 909         uint64_t qword1;
 910         uint64_t dma_addr;
 911         uint64_t pkt_flags;
 912
 913         volatile union iavf_rx_desc *rx_ring = rxq->rx_ring;
 914         volatile union iavf_rx_desc *rxdp;
 915         static const uint32_t ptype_tbl[UINT8_MAX + 1] __rte_cache_aligned = {
 916                 /* [0] reserved */
 917                 [1] = RTE_PTYPE_L2_ETHER,
 918                 /* [2] - [21] reserved */
 919                 [22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 920                         RTE_PTYPE_L4_FRAG,
 921                 [23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 922                         RTE_PTYPE_L4_NONFRAG,
 923                 [24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 924                         RTE_PTYPE_L4_UDP,
 925                 /* [25] reserved */
 926                 [26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 927                         RTE_PTYPE_L4_TCP,
 928                 [27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 929                         RTE_PTYPE_L4_SCTP,
 930                 [28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 931                         RTE_PTYPE_L4_ICMP,
 932                 /* All others reserved */
 933         };
 934
 935         while (nb_rx < nb_pkts) {
 936                 rxdp = &rx_ring[rx_id];
 937                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 938                 rx_status = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
 939                             IAVF_RXD_QW1_STATUS_SHIFT;
 940
 941                 /* Check the DD bit */
 942                 if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)))
 943                         break;
 944                 IAVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
 945
 946                 nmb = rte_mbuf_raw_alloc(rxq->mp);
 947                 if (unlikely(!nmb)) {
 948                         PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
 949                                    "queue_id=%u", rxq->port_id, rxq->queue_id);
 950                         dev = &rte_eth_devices[rxq->port_id];
 951                         dev->data->rx_mbuf_alloc_failed++;
 952                         break;
 953                 }
 954
 955                 rxd = *rxdp;
 956                 nb_hold++;
 957                 rxe = rxq->sw_ring[rx_id];
 958                 rx_id++;
 959                 if (rx_id == rxq->nb_rx_desc)
 960                         rx_id = 0;
 961
 962                 /* Prefetch next mbuf */
 963                 rte_prefetch0(rxq->sw_ring[rx_id]);
 964
 965                 /* When next RX descriptor is on a cache line boundary,
 966                  * prefetch the next 4 RX descriptors and next 8 pointers
 967                  * to mbufs.
 968                  */
 969                 if ((rx_id & 0x3) == 0) {
 970                         rte_prefetch0(&rx_ring[rx_id]);
 971                         rte_prefetch0(rxq->sw_ring[rx_id]);
 972                 }
 973
 974                 rxm = rxe;
 975                 rxe = nmb;
 976                 dma_addr =
 977                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
 978
 979                 /* Set data buffer address and data length of the mbuf */
 980                 rxdp->read.hdr_addr = 0;
 981                 rxdp->read.pkt_addr = dma_addr;
 982                 rx_packet_len = (qword1 & IAVF_RXD_QW1_LENGTH_PBUF_MASK) >>
 983                                  IAVF_RXD_QW1_LENGTH_PBUF_SHIFT;
 984                 rxm->data_len = rx_packet_len;
 985                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
 986
 987                 /* If this is the first buffer of the received packet, set the
 988                  * pointer to the first mbuf of the packet and initialize its
 989                  * context. Otherwise, update the total length and the number
 990                  * of segments of the current scattered packet, and update the
 991                  * pointer to the last mbuf of the current packet.
 992                  */
 993                 if (!first_seg) {
 994                         first_seg = rxm;
 995                         first_seg->nb_segs = 1;
 996                         first_seg->pkt_len = rx_packet_len;
 997                 } else {
 998                         first_seg->pkt_len =
 999                                 (uint16_t)(first_seg->pkt_len +
1000                                                 rx_packet_len);
1001                         first_seg->nb_segs++;
1002                         last_seg->next = rxm;
1003                 }
1004
1005                 /* If this is not the last buffer of the received packet,
1006                  * update the pointer to the last mbuf of the current scattered
1007                  * packet and continue to parse the RX ring.
1008                  */
1009                 if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_EOF_SHIFT))) {
1010                         last_seg = rxm;
1011                         continue;
1012                 }
1013
1014                 /* This is the last buffer of the received packet. If the CRC
1015                  * is not stripped by the hardware:
1016                  *  - Subtract the CRC length from the total packet length.
1017                  *  - If the last buffer only contains the whole CRC or a part
1018                  *  of it, free the mbuf associated to the last buffer. If part
1019                  *  of the CRC is also contained in the previous mbuf, subtract
1020                  *  the length of that CRC part from the data length of the
1021                  *  previous mbuf.
1022                  */
1023                 rxm->next = NULL;
1024                 if (unlikely(rxq->crc_len > 0)) {
1025                         first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
1026                         if (rx_packet_len <= RTE_ETHER_CRC_LEN) {
1027                                 rte_pktmbuf_free_seg(rxm);
1028                                 first_seg->nb_segs--;
1029                                 last_seg->data_len =
1030                                         (uint16_t)(last_seg->data_len -
1031                                         (RTE_ETHER_CRC_LEN - rx_packet_len));
1032                                 last_seg->next = NULL;
1033                         } else
1034                                 rxm->data_len = (uint16_t)(rx_packet_len -
1035                                                         RTE_ETHER_CRC_LEN);
1036                 }
1037
1038                 first_seg->port = rxq->port_id;
1039                 first_seg->ol_flags = 0;
1040                 iavf_rxd_to_vlan_tci(first_seg, &rxd);
1041                 pkt_flags = iavf_rxd_to_pkt_flags(qword1);
1042                 first_seg->packet_type =
1043                         ptype_tbl[(uint8_t)((qword1 &
1044                         IAVF_RXD_QW1_PTYPE_MASK) >> IAVF_RXD_QW1_PTYPE_SHIFT)];
1045
1046                 if (pkt_flags & PKT_RX_RSS_HASH)
1047                         first_seg->hash.rss =
1048                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1049
1050                 first_seg->ol_flags |= pkt_flags;
1051
1052                 /* Prefetch data of first segment, if configured to do so. */
1053                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1054                                           first_seg->data_off));
1055                 rx_pkts[nb_rx++] = first_seg;
1056                 first_seg = NULL;
1057         }
1058
1059         /* Record index of the next RX descriptor to probe. */
1060         rxq->rx_tail = rx_id;
1061         rxq->pkt_first_seg = first_seg;
1062         rxq->pkt_last_seg = last_seg;
1063
1064         /* If the number of free RX descriptors is greater than the RX free
1065          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1066          * register. Update the RDT with the value of the last processed RX
1067          * descriptor minus 1, to guarantee that the RDT register is never
1068          * equal to the RDH register, which creates a "full" ring situtation
1069          * from the hardware point of view.
1070          */
1071         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1072         if (nb_hold > rxq->rx_free_thresh) {
1073                 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1074                            "nb_hold=%u nb_rx=%u",
1075                            rxq->port_id, rxq->queue_id,
1076                            rx_id, nb_hold, nb_rx);
1077                 rx_id = (uint16_t)(rx_id == 0 ?
1078                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
1079                 IAVF_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
1080                 nb_hold = 0;
1081         }
1082         rxq->nb_rx_hold = nb_hold;
1083
1084         return nb_rx;
1085 }
1086
1087 #define IAVF_LOOK_AHEAD 8
1088 static inline int
1089 iavf_rx_scan_hw_ring(struct iavf_rx_queue *rxq)
1090 {
1091         volatile union iavf_rx_desc *rxdp;
1092         struct rte_mbuf **rxep;
1093         struct rte_mbuf *mb;
1094         uint16_t pkt_len;
1095         uint64_t qword1;
1096         uint32_t rx_status;
1097         int32_t s[IAVF_LOOK_AHEAD], nb_dd;
1098         int32_t i, j, nb_rx = 0;
1099         uint64_t pkt_flags;
1100         static const uint32_t ptype_tbl[UINT8_MAX + 1] __rte_cache_aligned = {
1101                 /* [0] reserved */
1102                 [1] = RTE_PTYPE_L2_ETHER,
1103                 /* [2] - [21] reserved */
1104                 [22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1105                         RTE_PTYPE_L4_FRAG,
1106                 [23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1107                         RTE_PTYPE_L4_NONFRAG,
1108                 [24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1109                         RTE_PTYPE_L4_UDP,
1110                 /* [25] reserved */
1111                 [26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1112                         RTE_PTYPE_L4_TCP,
1113                 [27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1114                         RTE_PTYPE_L4_SCTP,
1115                 [28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1116                         RTE_PTYPE_L4_ICMP,
1117                 /* All others reserved */
1118         };
1119
1120         rxdp = &rxq->rx_ring[rxq->rx_tail];
1121         rxep = &rxq->sw_ring[rxq->rx_tail];
1122
1123         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1124         rx_status = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
1125                     IAVF_RXD_QW1_STATUS_SHIFT;
1126
1127         /* Make sure there is at least 1 packet to receive */
1128         if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)))
1129                 return 0;
1130
1131         /* Scan LOOK_AHEAD descriptors at a time to determine which
1132          * descriptors reference packets that are ready to be received.
1133          */
1134         for (i = 0; i < IAVF_RX_MAX_BURST; i += IAVF_LOOK_AHEAD,
1135              rxdp += IAVF_LOOK_AHEAD, rxep += IAVF_LOOK_AHEAD) {
1136                 /* Read desc statuses backwards to avoid race condition */
1137                 for (j = IAVF_LOOK_AHEAD - 1; j >= 0; j--) {
1138                         qword1 = rte_le_to_cpu_64(
1139                                 rxdp[j].wb.qword1.status_error_len);
1140                         s[j] = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
1141                                IAVF_RXD_QW1_STATUS_SHIFT;
1142                 }
1143
1144                 rte_smp_rmb();
1145
1146                 /* Compute how many status bits were set */
1147                 for (j = 0, nb_dd = 0; j < IAVF_LOOK_AHEAD; j++)
1148                         nb_dd += s[j] & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT);
1149
1150                 nb_rx += nb_dd;
1151
1152                 /* Translate descriptor info to mbuf parameters */
1153                 for (j = 0; j < nb_dd; j++) {
1154                         IAVF_DUMP_RX_DESC(rxq, &rxdp[j],
1155                                          rxq->rx_tail + i * IAVF_LOOK_AHEAD + j);
1156
1157                         mb = rxep[j];
1158                         qword1 = rte_le_to_cpu_64
1159                                         (rxdp[j].wb.qword1.status_error_len);
1160                         pkt_len = ((qword1 & IAVF_RXD_QW1_LENGTH_PBUF_MASK) >>
1161                                   IAVF_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
1162                         mb->data_len = pkt_len;
1163                         mb->pkt_len = pkt_len;
1164                         mb->ol_flags = 0;
1165                         iavf_rxd_to_vlan_tci(mb, &rxdp[j]);
1166                         pkt_flags = iavf_rxd_to_pkt_flags(qword1);
1167                         mb->packet_type =
1168                                 ptype_tbl[(uint8_t)((qword1 &
1169                                 IAVF_RXD_QW1_PTYPE_MASK) >>
1170                                 IAVF_RXD_QW1_PTYPE_SHIFT)];
1171
1172                         if (pkt_flags & PKT_RX_RSS_HASH)
1173                                 mb->hash.rss = rte_le_to_cpu_32(
1174                                         rxdp[j].wb.qword0.hi_dword.rss);
1175
1176                         mb->ol_flags |= pkt_flags;
1177                 }
1178
1179                 for (j = 0; j < IAVF_LOOK_AHEAD; j++)
1180                         rxq->rx_stage[i + j] = rxep[j];
1181
1182                 if (nb_dd != IAVF_LOOK_AHEAD)
1183                         break;
1184         }
1185
1186         /* Clear software ring entries */
1187         for (i = 0; i < nb_rx; i++)
1188                 rxq->sw_ring[rxq->rx_tail + i] = NULL;
1189
1190         return nb_rx;
1191 }
1192
1193 static inline uint16_t
1194 iavf_rx_fill_from_stage(struct iavf_rx_queue *rxq,
1195                        struct rte_mbuf **rx_pkts,
1196                        uint16_t nb_pkts)
1197 {
1198         uint16_t i;
1199         struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1200
1201         nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1202
1203         for (i = 0; i < nb_pkts; i++)
1204                 rx_pkts[i] = stage[i];
1205
1206         rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1207         rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1208
1209         return nb_pkts;
1210 }
1211
1212 static inline int
1213 iavf_rx_alloc_bufs(struct iavf_rx_queue *rxq)
1214 {
1215         volatile union iavf_rx_desc *rxdp;
1216         struct rte_mbuf **rxep;
1217         struct rte_mbuf *mb;
1218         uint16_t alloc_idx, i;
1219         uint64_t dma_addr;
1220         int diag;
1221
1222         /* Allocate buffers in bulk */
1223         alloc_idx = (uint16_t)(rxq->rx_free_trigger -
1224                                 (rxq->rx_free_thresh - 1));
1225         rxep = &rxq->sw_ring[alloc_idx];
1226         diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
1227                                     rxq->rx_free_thresh);
1228         if (unlikely(diag != 0)) {
1229                 PMD_RX_LOG(ERR, "Failed to get mbufs in bulk");
1230                 return -ENOMEM;
1231         }
1232
1233         rxdp = &rxq->rx_ring[alloc_idx];
1234         for (i = 0; i < rxq->rx_free_thresh; i++) {
1235                 if (likely(i < (rxq->rx_free_thresh - 1)))
1236                         /* Prefetch next mbuf */
1237                         rte_prefetch0(rxep[i + 1]);
1238
1239                 mb = rxep[i];
1240                 rte_mbuf_refcnt_set(mb, 1);
1241                 mb->next = NULL;
1242                 mb->data_off = RTE_PKTMBUF_HEADROOM;
1243                 mb->nb_segs = 1;
1244                 mb->port = rxq->port_id;
1245                 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mb));
1246                 rxdp[i].read.hdr_addr = 0;
1247                 rxdp[i].read.pkt_addr = dma_addr;
1248         }
1249
1250         /* Update rx tail register */
1251         rte_wmb();
1252         IAVF_PCI_REG_WRITE_RELAXED(rxq->qrx_tail, rxq->rx_free_trigger);
1253
1254         rxq->rx_free_trigger =
1255                 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
1256         if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1257                 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
1258
1259         return 0;
1260 }
1261
1262 static inline uint16_t
1263 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1264 {
1265         struct iavf_rx_queue *rxq = (struct iavf_rx_queue *)rx_queue;
1266         uint16_t nb_rx = 0;
1267
1268         if (!nb_pkts)
1269                 return 0;
1270
1271         if (rxq->rx_nb_avail)
1272                 return iavf_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1273
1274         nb_rx = (uint16_t)iavf_rx_scan_hw_ring(rxq);
1275         rxq->rx_next_avail = 0;
1276         rxq->rx_nb_avail = nb_rx;
1277         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1278
1279         if (rxq->rx_tail > rxq->rx_free_trigger) {
1280                 if (iavf_rx_alloc_bufs(rxq) != 0) {
1281                         uint16_t i, j;
1282
1283                         /* TODO: count rx_mbuf_alloc_failed here */
1284
1285                         rxq->rx_nb_avail = 0;
1286                         rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1287                         for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
1288                                 rxq->sw_ring[j] = rxq->rx_stage[i];
1289
1290                         return 0;
1291                 }
1292         }
1293
1294         if (rxq->rx_tail >= rxq->nb_rx_desc)
1295                 rxq->rx_tail = 0;
1296
1297         PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u, nb_rx=%u",
1298                    rxq->port_id, rxq->queue_id,
1299                    rxq->rx_tail, nb_rx);
1300
1301         if (rxq->rx_nb_avail)
1302                 return iavf_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1303
1304         return 0;
1305 }
1306
1307 static uint16_t
1308 iavf_recv_pkts_bulk_alloc(void *rx_queue,
1309                          struct rte_mbuf **rx_pkts,
1310                          uint16_t nb_pkts)
1311 {
1312         uint16_t nb_rx = 0, n, count;
1313
1314         if (unlikely(nb_pkts == 0))
1315                 return 0;
1316
1317         if (likely(nb_pkts <= IAVF_RX_MAX_BURST))
1318                 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1319
1320         while (nb_pkts) {
1321                 n = RTE_MIN(nb_pkts, IAVF_RX_MAX_BURST);
1322                 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1323                 nb_rx = (uint16_t)(nb_rx + count);
1324                 nb_pkts = (uint16_t)(nb_pkts - count);
1325                 if (count < n)
1326                         break;
1327         }
1328
1329         return nb_rx;
1330 }
1331
1332 static inline int
1333 iavf_xmit_cleanup(struct iavf_tx_queue *txq)
1334 {
1335         struct iavf_tx_entry *sw_ring = txq->sw_ring;
1336         uint16_t last_desc_cleaned = txq->last_desc_cleaned;
1337         uint16_t nb_tx_desc = txq->nb_tx_desc;
1338         uint16_t desc_to_clean_to;
1339         uint16_t nb_tx_to_clean;
1340
1341         volatile struct iavf_tx_desc *txd = txq->tx_ring;
1342
1343         desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->rs_thresh);
1344         if (desc_to_clean_to >= nb_tx_desc)
1345                 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
1346
1347         desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
1348         if ((txd[desc_to_clean_to].cmd_type_offset_bsz &
1349                         rte_cpu_to_le_64(IAVF_TXD_QW1_DTYPE_MASK)) !=
1350                         rte_cpu_to_le_64(IAVF_TX_DESC_DTYPE_DESC_DONE)) {
1351                 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
1352                                 "(port=%d queue=%d)", desc_to_clean_to,
1353                                 txq->port_id, txq->queue_id);
1354                 return -1;
1355         }
1356
1357         if (last_desc_cleaned > desc_to_clean_to)
1358                 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
1359                                                         desc_to_clean_to);
1360         else
1361                 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
1362                                         last_desc_cleaned);
1363
1364         txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
1365
1366         txq->last_desc_cleaned = desc_to_clean_to;
1367         txq->nb_free = (uint16_t)(txq->nb_free + nb_tx_to_clean);
1368
1369         return 0;
1370 }
1371
1372 /* Check if the context descriptor is needed for TX offloading */
1373 static inline uint16_t
1374 iavf_calc_context_desc(uint64_t flags)
1375 {
1376         static uint64_t mask = PKT_TX_TCP_SEG;
1377
1378         return (flags & mask) ? 1 : 0;
1379 }
1380
1381 static inline void
1382 iavf_txd_enable_checksum(uint64_t ol_flags,
1383                         uint32_t *td_cmd,
1384                         uint32_t *td_offset,
1385                         union iavf_tx_offload tx_offload)
1386 {
1387         /* Set MACLEN */
1388         *td_offset |= (tx_offload.l2_len >> 1) <<
1389                       IAVF_TX_DESC_LENGTH_MACLEN_SHIFT;
1390
1391         /* Enable L3 checksum offloads */
1392         if (ol_flags & PKT_TX_IP_CKSUM) {
1393                 *td_cmd |= IAVF_TX_DESC_CMD_IIPT_IPV4_CSUM;
1394                 *td_offset |= (tx_offload.l3_len >> 2) <<
1395                               IAVF_TX_DESC_LENGTH_IPLEN_SHIFT;
1396         } else if (ol_flags & PKT_TX_IPV4) {
1397                 *td_cmd |= IAVF_TX_DESC_CMD_IIPT_IPV4;
1398                 *td_offset |= (tx_offload.l3_len >> 2) <<
1399                               IAVF_TX_DESC_LENGTH_IPLEN_SHIFT;
1400         } else if (ol_flags & PKT_TX_IPV6) {
1401                 *td_cmd |= IAVF_TX_DESC_CMD_IIPT_IPV6;
1402                 *td_offset |= (tx_offload.l3_len >> 2) <<
1403                               IAVF_TX_DESC_LENGTH_IPLEN_SHIFT;
1404         }
1405
1406         if (ol_flags & PKT_TX_TCP_SEG) {
1407                 *td_cmd |= IAVF_TX_DESC_CMD_L4T_EOFT_TCP;
1408                 *td_offset |= (tx_offload.l4_len >> 2) <<
1409                               IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1410                 return;
1411         }
1412
1413         /* Enable L4 checksum offloads */
1414         switch (ol_flags & PKT_TX_L4_MASK) {
1415         case PKT_TX_TCP_CKSUM:
1416                 *td_cmd |= IAVF_TX_DESC_CMD_L4T_EOFT_TCP;
1417                 *td_offset |= (sizeof(struct rte_tcp_hdr) >> 2) <<
1418                               IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1419                 break;
1420         case PKT_TX_SCTP_CKSUM:
1421                 *td_cmd |= IAVF_TX_DESC_CMD_L4T_EOFT_SCTP;
1422                 *td_offset |= (sizeof(struct rte_sctp_hdr) >> 2) <<
1423                               IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1424                 break;
1425         case PKT_TX_UDP_CKSUM:
1426                 *td_cmd |= IAVF_TX_DESC_CMD_L4T_EOFT_UDP;
1427                 *td_offset |= (sizeof(struct rte_udp_hdr) >> 2) <<
1428                               IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1429                 break;
1430         default:
1431                 break;
1432         }
1433 }
1434
1435 /* set TSO context descriptor
1436  * support IP -> L4 and IP -> IP -> L4
1437  */
1438 static inline uint64_t
1439 iavf_set_tso_ctx(struct rte_mbuf *mbuf, union iavf_tx_offload tx_offload)
1440 {
1441         uint64_t ctx_desc = 0;
1442         uint32_t cd_cmd, hdr_len, cd_tso_len;
1443
1444         if (!tx_offload.l4_len) {
1445                 PMD_TX_LOG(DEBUG, "L4 length set to 0");
1446                 return ctx_desc;
1447         }
1448
1449         hdr_len = tx_offload.l2_len +
1450                   tx_offload.l3_len +
1451                   tx_offload.l4_len;
1452
1453         cd_cmd = IAVF_TX_CTX_DESC_TSO;
1454         cd_tso_len = mbuf->pkt_len - hdr_len;
1455         ctx_desc |= ((uint64_t)cd_cmd << IAVF_TXD_CTX_QW1_CMD_SHIFT) |
1456                      ((uint64_t)cd_tso_len << IAVF_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1457                      ((uint64_t)mbuf->tso_segsz << IAVF_TXD_CTX_QW1_MSS_SHIFT);
1458
1459         return ctx_desc;
1460 }
1461
1462 /* Construct the tx flags */
1463 static inline uint64_t
1464 iavf_build_ctob(uint32_t td_cmd, uint32_t td_offset, unsigned int size,
1465                uint32_t td_tag)
1466 {
1467         return rte_cpu_to_le_64(IAVF_TX_DESC_DTYPE_DATA |
1468                                 ((uint64_t)td_cmd  << IAVF_TXD_QW1_CMD_SHIFT) |
1469                                 ((uint64_t)td_offset <<
1470                                  IAVF_TXD_QW1_OFFSET_SHIFT) |
1471                                 ((uint64_t)size  <<
1472                                  IAVF_TXD_QW1_TX_BUF_SZ_SHIFT) |
1473                                 ((uint64_t)td_tag  <<
1474                                  IAVF_TXD_QW1_L2TAG1_SHIFT));
1475 }
1476
1477 /* TX function */
1478 uint16_t
1479 iavf_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1480 {
1481         volatile struct iavf_tx_desc *txd;
1482         volatile struct iavf_tx_desc *txr;
1483         struct iavf_tx_queue *txq;
1484         struct iavf_tx_entry *sw_ring;
1485         struct iavf_tx_entry *txe, *txn;
1486         struct rte_mbuf *tx_pkt;
1487         struct rte_mbuf *m_seg;
1488         uint16_t tx_id;
1489         uint16_t nb_tx;
1490         uint32_t td_cmd;
1491         uint32_t td_offset;
1492         uint32_t td_tag;
1493         uint64_t ol_flags;
1494         uint16_t nb_used;
1495         uint16_t nb_ctx;
1496         uint16_t tx_last;
1497         uint16_t slen;
1498         uint64_t buf_dma_addr;
1499         union iavf_tx_offload tx_offload = {0};
1500
1501         txq = tx_queue;
1502         sw_ring = txq->sw_ring;
1503         txr = txq->tx_ring;
1504         tx_id = txq->tx_tail;
1505         txe = &sw_ring[tx_id];
1506
1507         /* Check if the descriptor ring needs to be cleaned. */
1508         if (txq->nb_free < txq->free_thresh)
1509                 iavf_xmit_cleanup(txq);
1510
1511         for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1512                 td_cmd = 0;
1513                 td_tag = 0;
1514                 td_offset = 0;
1515
1516                 tx_pkt = *tx_pkts++;
1517                 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
1518
1519                 ol_flags = tx_pkt->ol_flags;
1520                 tx_offload.l2_len = tx_pkt->l2_len;
1521                 tx_offload.l3_len = tx_pkt->l3_len;
1522                 tx_offload.l4_len = tx_pkt->l4_len;
1523                 tx_offload.tso_segsz = tx_pkt->tso_segsz;
1524
1525                 /* Calculate the number of context descriptors needed. */
1526                 nb_ctx = iavf_calc_context_desc(ol_flags);
1527
1528                 /* The number of descriptors that must be allocated for
1529                  * a packet equals to the number of the segments of that
1530                  * packet plus 1 context descriptor if needed.
1531                  */
1532                 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
1533                 tx_last = (uint16_t)(tx_id + nb_used - 1);
1534
1535                 /* Circular ring */
1536                 if (tx_last >= txq->nb_tx_desc)
1537                         tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
1538
1539                 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u"
1540                            " tx_first=%u tx_last=%u",
1541                            txq->port_id, txq->queue_id, tx_id, tx_last);
1542
1543                 if (nb_used > txq->nb_free) {
1544                         if (iavf_xmit_cleanup(txq)) {
1545                                 if (nb_tx == 0)
1546                                         return 0;
1547                                 goto end_of_tx;
1548                         }
1549                         if (unlikely(nb_used > txq->rs_thresh)) {
1550                                 while (nb_used > txq->nb_free) {
1551                                         if (iavf_xmit_cleanup(txq)) {
1552                                                 if (nb_tx == 0)
1553                                                         return 0;
1554                                                 goto end_of_tx;
1555                                         }
1556                                 }
1557                         }
1558                 }
1559
1560                 /* Descriptor based VLAN insertion */
1561                 if (ol_flags & PKT_TX_VLAN_PKT) {
1562                         td_cmd |= IAVF_TX_DESC_CMD_IL2TAG1;
1563                         td_tag = tx_pkt->vlan_tci;
1564                 }
1565
1566                 /* According to datasheet, the bit2 is reserved and must be
1567                  * set to 1.
1568                  */
1569                 td_cmd |= 0x04;
1570
1571                 /* Enable checksum offloading */
1572                 if (ol_flags & IAVF_TX_CKSUM_OFFLOAD_MASK)
1573                         iavf_txd_enable_checksum(ol_flags, &td_cmd,
1574                                                 &td_offset, tx_offload);
1575
1576                 if (nb_ctx) {
1577                         /* Setup TX context descriptor if required */
1578                         uint64_t cd_type_cmd_tso_mss =
1579                                 IAVF_TX_DESC_DTYPE_CONTEXT;
1580                         volatile struct iavf_tx_context_desc *ctx_txd =
1581                                 (volatile struct iavf_tx_context_desc *)
1582                                                         &txr[tx_id];
1583
1584                         txn = &sw_ring[txe->next_id];
1585                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
1586                         if (txe->mbuf) {
1587                                 rte_pktmbuf_free_seg(txe->mbuf);
1588                                 txe->mbuf = NULL;
1589                         }
1590
1591                         /* TSO enabled */
1592                         if (ol_flags & PKT_TX_TCP_SEG)
1593                                 cd_type_cmd_tso_mss |=
1594                                         iavf_set_tso_ctx(tx_pkt, tx_offload);
1595
1596                         ctx_txd->type_cmd_tso_mss =
1597                                 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
1598
1599                         IAVF_DUMP_TX_DESC(txq, &txr[tx_id], tx_id);
1600                         txe->last_id = tx_last;
1601                         tx_id = txe->next_id;
1602                         txe = txn;
1603                 }
1604
1605                 m_seg = tx_pkt;
1606                 do {
1607                         txd = &txr[tx_id];
1608                         txn = &sw_ring[txe->next_id];
1609
1610                         if (txe->mbuf)
1611                                 rte_pktmbuf_free_seg(txe->mbuf);
1612                         txe->mbuf = m_seg;
1613
1614                         /* Setup TX Descriptor */
1615                         slen = m_seg->data_len;
1616                         buf_dma_addr = rte_mbuf_data_iova(m_seg);
1617                         txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
1618                         txd->cmd_type_offset_bsz = iavf_build_ctob(td_cmd,
1619                                                                   td_offset,
1620                                                                   slen,
1621                                                                   td_tag);
1622
1623                         IAVF_DUMP_TX_DESC(txq, txd, tx_id);
1624                         txe->last_id = tx_last;
1625                         tx_id = txe->next_id;
1626                         txe = txn;
1627                         m_seg = m_seg->next;
1628                 } while (m_seg);
1629
1630                 /* The last packet data descriptor needs End Of Packet (EOP) */
1631                 td_cmd |= IAVF_TX_DESC_CMD_EOP;
1632                 txq->nb_used = (uint16_t)(txq->nb_used + nb_used);
1633                 txq->nb_free = (uint16_t)(txq->nb_free - nb_used);
1634
1635                 if (txq->nb_used >= txq->rs_thresh) {
1636                         PMD_TX_LOG(DEBUG, "Setting RS bit on TXD id="
1637                                    "%4u (port=%d queue=%d)",
1638                                    tx_last, txq->port_id, txq->queue_id);
1639
1640                         td_cmd |= IAVF_TX_DESC_CMD_RS;
1641
1642                         /* Update txq RS bit counters */
1643                         txq->nb_used = 0;
1644                 }
1645
1646                 txd->cmd_type_offset_bsz |=
1647                         rte_cpu_to_le_64(((uint64_t)td_cmd) <<
1648                                          IAVF_TXD_QW1_CMD_SHIFT);
1649                 IAVF_DUMP_TX_DESC(txq, txd, tx_id);
1650         }
1651
1652 end_of_tx:
1653         rte_wmb();
1654
1655         PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
1656                    txq->port_id, txq->queue_id, tx_id, nb_tx);
1657
1658         IAVF_PCI_REG_WRITE_RELAXED(txq->qtx_tail, tx_id);
1659         txq->tx_tail = tx_id;
1660
1661         return nb_tx;
1662 }
1663
1664 /* TX prep functions */
1665 uint16_t
1666 iavf_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
1667               uint16_t nb_pkts)
1668 {
1669         int i, ret;
1670         uint64_t ol_flags;
1671         struct rte_mbuf *m;
1672
1673         for (i = 0; i < nb_pkts; i++) {
1674                 m = tx_pkts[i];
1675                 ol_flags = m->ol_flags;
1676
1677                 /* Check condition for nb_segs > IAVF_TX_MAX_MTU_SEG. */
1678                 if (!(ol_flags & PKT_TX_TCP_SEG)) {
1679                         if (m->nb_segs > IAVF_TX_MAX_MTU_SEG) {
1680                                 rte_errno = EINVAL;
1681                                 return i;
1682                         }
1683                 } else if ((m->tso_segsz < IAVF_MIN_TSO_MSS) ||
1684                            (m->tso_segsz > IAVF_MAX_TSO_MSS)) {
1685                         /* MSS outside the range are considered malicious */
1686                         rte_errno = EINVAL;
1687                         return i;
1688                 }
1689
1690                 if (ol_flags & IAVF_TX_OFFLOAD_NOTSUP_MASK) {
1691                         rte_errno = ENOTSUP;
1692                         return i;
1693                 }
1694
1695 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
1696                 ret = rte_validate_tx_offload(m);
1697                 if (ret != 0) {
1698                         rte_errno = -ret;
1699                         return i;
1700                 }
1701 #endif
1702                 ret = rte_net_intel_cksum_prepare(m);
1703                 if (ret != 0) {
1704                         rte_errno = -ret;
1705                         return i;
1706                 }
1707         }
1708
1709         return i;
1710 }
1711
1712 /* choose rx function*/
1713 void
1714 iavf_set_rx_function(struct rte_eth_dev *dev)
1715 {
1716         struct iavf_adapter *adapter =
1717                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1718 #ifdef RTE_ARCH_X86
1719         struct iavf_rx_queue *rxq;
1720         int i;
1721         bool use_avx2 = false;
1722
1723         if (!iavf_rx_vec_dev_check(dev)) {
1724                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1725                         rxq = dev->data->rx_queues[i];
1726                         (void)iavf_rxq_vec_setup(rxq);
1727                 }
1728
1729                 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
1730                     rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1)
1731                         use_avx2 = true;
1732
1733                 if (dev->data->scattered_rx) {
1734                         PMD_DRV_LOG(DEBUG,
1735                                     "Using %sVector Scattered Rx (port %d).",
1736                                     use_avx2 ? "avx2 " : "",
1737                                     dev->data->port_id);
1738                         dev->rx_pkt_burst = use_avx2 ?
1739                                             iavf_recv_scattered_pkts_vec_avx2 :
1740                                             iavf_recv_scattered_pkts_vec;
1741                 } else {
1742                         PMD_DRV_LOG(DEBUG, "Using %sVector Rx (port %d).",
1743                                     use_avx2 ? "avx2 " : "",
1744                                     dev->data->port_id);
1745                         dev->rx_pkt_burst = use_avx2 ?
1746                                             iavf_recv_pkts_vec_avx2 :
1747                                             iavf_recv_pkts_vec;
1748                 }
1749
1750                 return;
1751         }
1752 #endif
1753
1754         if (dev->data->scattered_rx) {
1755                 PMD_DRV_LOG(DEBUG, "Using a Scattered Rx callback (port=%d).",
1756                             dev->data->port_id);
1757                 dev->rx_pkt_burst = iavf_recv_scattered_pkts;
1758         } else if (adapter->rx_bulk_alloc_allowed) {
1759                 PMD_DRV_LOG(DEBUG, "Using bulk Rx callback (port=%d).",
1760                             dev->data->port_id);
1761                 dev->rx_pkt_burst = iavf_recv_pkts_bulk_alloc;
1762         } else {
1763                 PMD_DRV_LOG(DEBUG, "Using Basic Rx callback (port=%d).",
1764                             dev->data->port_id);
1765                 dev->rx_pkt_burst = iavf_recv_pkts;
1766         }
1767 }
1768
1769 /* choose tx function*/
1770 void
1771 iavf_set_tx_function(struct rte_eth_dev *dev)
1772 {
1773 #ifdef RTE_ARCH_X86
1774         struct iavf_tx_queue *txq;
1775         int i;
1776         bool use_avx2 = false;
1777
1778         if (!iavf_tx_vec_dev_check(dev)) {
1779                 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1780                         txq = dev->data->tx_queues[i];
1781                         if (!txq)
1782                                 continue;
1783                         iavf_txq_vec_setup(txq);
1784                 }
1785
1786                 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
1787                     rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1)
1788                         use_avx2 = true;
1789
1790                 PMD_DRV_LOG(DEBUG, "Using %sVector Tx (port %d).",
1791                             use_avx2 ? "avx2 " : "",
1792                             dev->data->port_id);
1793                 dev->tx_pkt_burst = use_avx2 ?
1794                                     iavf_xmit_pkts_vec_avx2 :
1795                                     iavf_xmit_pkts_vec;
1796                 dev->tx_pkt_prepare = NULL;
1797
1798                 return;
1799         }
1800 #endif
1801
1802         PMD_DRV_LOG(DEBUG, "Using Basic Tx callback (port=%d).",
1803                     dev->data->port_id);
1804         dev->tx_pkt_burst = iavf_xmit_pkts;
1805         dev->tx_pkt_prepare = iavf_prep_pkts;
1806 }
1807
1808 void
1809 iavf_dev_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1810                      struct rte_eth_rxq_info *qinfo)
1811 {
1812         struct iavf_rx_queue *rxq;
1813
1814         rxq = dev->data->rx_queues[queue_id];
1815
1816         qinfo->mp = rxq->mp;
1817         qinfo->scattered_rx = dev->data->scattered_rx;
1818         qinfo->nb_desc = rxq->nb_rx_desc;
1819
1820         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1821         qinfo->conf.rx_drop_en = TRUE;
1822         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
1823 }
1824
1825 void
1826 iavf_dev_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1827                      struct rte_eth_txq_info *qinfo)
1828 {
1829         struct iavf_tx_queue *txq;
1830
1831         txq = dev->data->tx_queues[queue_id];
1832
1833         qinfo->nb_desc = txq->nb_tx_desc;
1834
1835         qinfo->conf.tx_free_thresh = txq->free_thresh;
1836         qinfo->conf.tx_rs_thresh = txq->rs_thresh;
1837         qinfo->conf.offloads = txq->offloads;
1838         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1839 }
1840
1841 /* Get the number of used descriptors of a rx queue */
1842 uint32_t
1843 iavf_dev_rxq_count(struct rte_eth_dev *dev, uint16_t queue_id)
1844 {
1845 #define IAVF_RXQ_SCAN_INTERVAL 4
1846         volatile union iavf_rx_desc *rxdp;
1847         struct iavf_rx_queue *rxq;
1848         uint16_t desc = 0;
1849
1850         rxq = dev->data->rx_queues[queue_id];
1851         rxdp = &rxq->rx_ring[rxq->rx_tail];
1852         while ((desc < rxq->nb_rx_desc) &&
1853                ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1854                  IAVF_RXD_QW1_STATUS_MASK) >> IAVF_RXD_QW1_STATUS_SHIFT) &
1855                (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)) {
1856                 /* Check the DD bit of a rx descriptor of each 4 in a group,
1857                  * to avoid checking too frequently and downgrading performance
1858                  * too much.
1859                  */
1860                 desc += IAVF_RXQ_SCAN_INTERVAL;
1861                 rxdp += IAVF_RXQ_SCAN_INTERVAL;
1862                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
1863                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
1864                                         desc - rxq->nb_rx_desc]);
1865         }
1866
1867         return desc;
1868 }
1869
1870 int
1871 iavf_dev_rx_desc_status(void *rx_queue, uint16_t offset)
1872 {
1873         struct iavf_rx_queue *rxq = rx_queue;
1874         volatile uint64_t *status;
1875         uint64_t mask;
1876         uint32_t desc;
1877
1878         if (unlikely(offset >= rxq->nb_rx_desc))
1879                 return -EINVAL;
1880
1881         if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
1882                 return RTE_ETH_RX_DESC_UNAVAIL;
1883
1884         desc = rxq->rx_tail + offset;
1885         if (desc >= rxq->nb_rx_desc)
1886                 desc -= rxq->nb_rx_desc;
1887
1888         status = &rxq->rx_ring[desc].wb.qword1.status_error_len;
1889         mask = rte_le_to_cpu_64((1ULL << IAVF_RX_DESC_STATUS_DD_SHIFT)
1890                 << IAVF_RXD_QW1_STATUS_SHIFT);
1891         if (*status & mask)
1892                 return RTE_ETH_RX_DESC_DONE;
1893
1894         return RTE_ETH_RX_DESC_AVAIL;
1895 }
1896
1897 int
1898 iavf_dev_tx_desc_status(void *tx_queue, uint16_t offset)
1899 {
1900         struct iavf_tx_queue *txq = tx_queue;
1901         volatile uint64_t *status;
1902         uint64_t mask, expect;
1903         uint32_t desc;
1904
1905         if (unlikely(offset >= txq->nb_tx_desc))
1906                 return -EINVAL;
1907
1908         desc = txq->tx_tail + offset;
1909         /* go to next desc that has the RS bit */
1910         desc = ((desc + txq->rs_thresh - 1) / txq->rs_thresh) *
1911                 txq->rs_thresh;
1912         if (desc >= txq->nb_tx_desc) {
1913                 desc -= txq->nb_tx_desc;
1914                 if (desc >= txq->nb_tx_desc)
1915                         desc -= txq->nb_tx_desc;
1916         }
1917
1918         status = &txq->tx_ring[desc].cmd_type_offset_bsz;
1919         mask = rte_le_to_cpu_64(IAVF_TXD_QW1_DTYPE_MASK);
1920         expect = rte_cpu_to_le_64(
1921                  IAVF_TX_DESC_DTYPE_DESC_DONE << IAVF_TXD_QW1_DTYPE_SHIFT);
1922         if ((*status & mask) == expect)
1923                 return RTE_ETH_TX_DESC_DONE;
1924
1925         return RTE_ETH_TX_DESC_FULL;
1926 }
1927