drivers/net/iavf/iavf_rxtx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2017 Intel Corporation
   3  */
   4
   5 #include <stdio.h>
   6 #include <stdlib.h>
   7 #include <string.h>
   8 #include <errno.h>
   9 #include <stdint.h>
  10 #include <stdarg.h>
  11 #include <unistd.h>
  12 #include <inttypes.h>
  13 #include <sys/queue.h>
  14
  15 #include <rte_string_fns.h>
  16 #include <rte_memzone.h>
  17 #include <rte_mbuf.h>
  18 #include <rte_malloc.h>
  19 #include <rte_ether.h>
  20 #include <ethdev_driver.h>
  21 #include <rte_tcp.h>
  22 #include <rte_sctp.h>
  23 #include <rte_udp.h>
  24 #include <rte_ip.h>
  25 #include <rte_net.h>
  26 #include <rte_vect.h>
  27
  28 #include "iavf.h"
  29 #include "iavf_rxtx.h"
  30 #include "iavf_ipsec_crypto.h"
  31 #include "rte_pmd_iavf.h"
  32
  33 /* Offset of mbuf dynamic field for protocol extraction's metadata */
  34 int rte_pmd_ifd_dynfield_proto_xtr_metadata_offs = -1;
  35
  36 /* Mask of mbuf dynamic flags for protocol extraction's type */
  37 uint64_t rte_pmd_ifd_dynflag_proto_xtr_vlan_mask;
  38 uint64_t rte_pmd_ifd_dynflag_proto_xtr_ipv4_mask;
  39 uint64_t rte_pmd_ifd_dynflag_proto_xtr_ipv6_mask;
  40 uint64_t rte_pmd_ifd_dynflag_proto_xtr_ipv6_flow_mask;
  41 uint64_t rte_pmd_ifd_dynflag_proto_xtr_tcp_mask;
  42 uint64_t rte_pmd_ifd_dynflag_proto_xtr_ip_offset_mask;
  43 uint64_t rte_pmd_ifd_dynflag_proto_xtr_ipsec_crypto_said_mask;
  44
  45 uint8_t
  46 iavf_proto_xtr_type_to_rxdid(uint8_t flex_type)
  47 {
  48         static uint8_t rxdid_map[] = {
  49                 [IAVF_PROTO_XTR_NONE]      = IAVF_RXDID_COMMS_OVS_1,
  50                 [IAVF_PROTO_XTR_VLAN]      = IAVF_RXDID_COMMS_AUX_VLAN,
  51                 [IAVF_PROTO_XTR_IPV4]      = IAVF_RXDID_COMMS_AUX_IPV4,
  52                 [IAVF_PROTO_XTR_IPV6]      = IAVF_RXDID_COMMS_AUX_IPV6,
  53                 [IAVF_PROTO_XTR_IPV6_FLOW] = IAVF_RXDID_COMMS_AUX_IPV6_FLOW,
  54                 [IAVF_PROTO_XTR_TCP]       = IAVF_RXDID_COMMS_AUX_TCP,
  55                 [IAVF_PROTO_XTR_IP_OFFSET] = IAVF_RXDID_COMMS_AUX_IP_OFFSET,
  56                 [IAVF_PROTO_XTR_IPSEC_CRYPTO_SAID] =
  57                                 IAVF_RXDID_COMMS_IPSEC_CRYPTO,
  58         };
  59
  60         return flex_type < RTE_DIM(rxdid_map) ?
  61                                 rxdid_map[flex_type] : IAVF_RXDID_COMMS_OVS_1;
  62 }
  63
  64 static int
  65 iavf_monitor_callback(const uint64_t value,
  66                 const uint64_t arg[RTE_POWER_MONITOR_OPAQUE_SZ] __rte_unused)
  67 {
  68         const uint64_t m = rte_cpu_to_le_64(1 << IAVF_RX_DESC_STATUS_DD_SHIFT);
  69         /*
  70          * we expect the DD bit to be set to 1 if this descriptor was already
  71          * written to.
  72          */
  73         return (value & m) == m ? -1 : 0;
  74 }
  75
  76 int
  77 iavf_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc)
  78 {
  79         struct iavf_rx_queue *rxq = rx_queue;
  80         volatile union iavf_rx_desc *rxdp;
  81         uint16_t desc;
  82
  83         desc = rxq->rx_tail;
  84         rxdp = &rxq->rx_ring[desc];
  85         /* watch for changes in status bit */
  86         pmc->addr = &rxdp->wb.qword1.status_error_len;
  87
  88         /* comparison callback */
  89         pmc->fn = iavf_monitor_callback;
  90
  91         /* registers are 64-bit */
  92         pmc->size = sizeof(uint64_t);
  93
  94         return 0;
  95 }
  96
  97 static inline int
  98 check_rx_thresh(uint16_t nb_desc, uint16_t thresh)
  99 {
 100         /* The following constraints must be satisfied:
 101          *   thresh < rxq->nb_rx_desc
 102          */
 103         if (thresh >= nb_desc) {
 104                 PMD_INIT_LOG(ERR, "rx_free_thresh (%u) must be less than %u",
 105                              thresh, nb_desc);
 106                 return -EINVAL;
 107         }
 108         return 0;
 109 }
 110
 111 static inline int
 112 check_tx_thresh(uint16_t nb_desc, uint16_t tx_rs_thresh,
 113                 uint16_t tx_free_thresh)
 114 {
 115         /* TX descriptors will have their RS bit set after tx_rs_thresh
 116          * descriptors have been used. The TX descriptor ring will be cleaned
 117          * after tx_free_thresh descriptors are used or if the number of
 118          * descriptors required to transmit a packet is greater than the
 119          * number of free TX descriptors.
 120          *
 121          * The following constraints must be satisfied:
 122          *  - tx_rs_thresh must be less than the size of the ring minus 2.
 123          *  - tx_free_thresh must be less than the size of the ring minus 3.
 124          *  - tx_rs_thresh must be less than or equal to tx_free_thresh.
 125          *  - tx_rs_thresh must be a divisor of the ring size.
 126          *
 127          * One descriptor in the TX ring is used as a sentinel to avoid a H/W
 128          * race condition, hence the maximum threshold constraints. When set
 129          * to zero use default values.
 130          */
 131         if (tx_rs_thresh >= (nb_desc - 2)) {
 132                 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be less than the "
 133                              "number of TX descriptors (%u) minus 2",
 134                              tx_rs_thresh, nb_desc);
 135                 return -EINVAL;
 136         }
 137         if (tx_free_thresh >= (nb_desc - 3)) {
 138                 PMD_INIT_LOG(ERR, "tx_free_thresh (%u) must be less than the "
 139                              "number of TX descriptors (%u) minus 3.",
 140                              tx_free_thresh, nb_desc);
 141                 return -EINVAL;
 142         }
 143         if (tx_rs_thresh > tx_free_thresh) {
 144                 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be less than or "
 145                              "equal to tx_free_thresh (%u).",
 146                              tx_rs_thresh, tx_free_thresh);
 147                 return -EINVAL;
 148         }
 149         if ((nb_desc % tx_rs_thresh) != 0) {
 150                 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be a divisor of the "
 151                              "number of TX descriptors (%u).",
 152                              tx_rs_thresh, nb_desc);
 153                 return -EINVAL;
 154         }
 155
 156         return 0;
 157 }
 158
 159 static inline bool
 160 check_rx_vec_allow(struct iavf_rx_queue *rxq)
 161 {
 162         if (rxq->rx_free_thresh >= IAVF_VPMD_RX_MAX_BURST &&
 163             rxq->nb_rx_desc % rxq->rx_free_thresh == 0) {
 164                 PMD_INIT_LOG(DEBUG, "Vector Rx can be enabled on this rxq.");
 165                 return true;
 166         }
 167
 168         PMD_INIT_LOG(DEBUG, "Vector Rx cannot be enabled on this rxq.");
 169         return false;
 170 }
 171
 172 static inline bool
 173 check_tx_vec_allow(struct iavf_tx_queue *txq)
 174 {
 175         if (!(txq->offloads & IAVF_TX_NO_VECTOR_FLAGS) &&
 176             txq->rs_thresh >= IAVF_VPMD_TX_MAX_BURST &&
 177             txq->rs_thresh <= IAVF_VPMD_TX_MAX_FREE_BUF) {
 178                 PMD_INIT_LOG(DEBUG, "Vector tx can be enabled on this txq.");
 179                 return true;
 180         }
 181         PMD_INIT_LOG(DEBUG, "Vector Tx cannot be enabled on this txq.");
 182         return false;
 183 }
 184
 185 static inline bool
 186 check_rx_bulk_allow(struct iavf_rx_queue *rxq)
 187 {
 188         int ret = true;
 189
 190         if (!(rxq->rx_free_thresh >= IAVF_RX_MAX_BURST)) {
 191                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 192                              "rxq->rx_free_thresh=%d, "
 193                              "IAVF_RX_MAX_BURST=%d",
 194                              rxq->rx_free_thresh, IAVF_RX_MAX_BURST);
 195                 ret = false;
 196         } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
 197                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 198                              "rxq->nb_rx_desc=%d, "
 199                              "rxq->rx_free_thresh=%d",
 200                              rxq->nb_rx_desc, rxq->rx_free_thresh);
 201                 ret = false;
 202         }
 203         return ret;
 204 }
 205
 206 static inline void
 207 reset_rx_queue(struct iavf_rx_queue *rxq)
 208 {
 209         uint16_t len;
 210         uint32_t i;
 211
 212         if (!rxq)
 213                 return;
 214
 215         len = rxq->nb_rx_desc + IAVF_RX_MAX_BURST;
 216
 217         for (i = 0; i < len * sizeof(union iavf_rx_desc); i++)
 218                 ((volatile char *)rxq->rx_ring)[i] = 0;
 219
 220         memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
 221
 222         for (i = 0; i < IAVF_RX_MAX_BURST; i++)
 223                 rxq->sw_ring[rxq->nb_rx_desc + i] = &rxq->fake_mbuf;
 224
 225         /* for rx bulk */
 226         rxq->rx_nb_avail = 0;
 227         rxq->rx_next_avail = 0;
 228         rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
 229
 230         rxq->rx_tail = 0;
 231         rxq->nb_rx_hold = 0;
 232
 233         rte_pktmbuf_free(rxq->pkt_first_seg);
 234
 235         rxq->pkt_first_seg = NULL;
 236         rxq->pkt_last_seg = NULL;
 237         rxq->rxrearm_nb = 0;
 238         rxq->rxrearm_start = 0;
 239 }
 240
 241 static inline void
 242 reset_tx_queue(struct iavf_tx_queue *txq)
 243 {
 244         struct iavf_tx_entry *txe;
 245         uint32_t i, size;
 246         uint16_t prev;
 247
 248         if (!txq) {
 249                 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
 250                 return;
 251         }
 252
 253         txe = txq->sw_ring;
 254         size = sizeof(struct iavf_tx_desc) * txq->nb_tx_desc;
 255         for (i = 0; i < size; i++)
 256                 ((volatile char *)txq->tx_ring)[i] = 0;
 257
 258         prev = (uint16_t)(txq->nb_tx_desc - 1);
 259         for (i = 0; i < txq->nb_tx_desc; i++) {
 260                 txq->tx_ring[i].cmd_type_offset_bsz =
 261                         rte_cpu_to_le_64(IAVF_TX_DESC_DTYPE_DESC_DONE);
 262                 txe[i].mbuf =  NULL;
 263                 txe[i].last_id = i;
 264                 txe[prev].next_id = i;
 265                 prev = i;
 266         }
 267
 268         txq->tx_tail = 0;
 269         txq->nb_used = 0;
 270
 271         txq->last_desc_cleaned = txq->nb_tx_desc - 1;
 272         txq->nb_free = txq->nb_tx_desc - 1;
 273
 274         txq->next_dd = txq->rs_thresh - 1;
 275         txq->next_rs = txq->rs_thresh - 1;
 276 }
 277
 278 static int
 279 alloc_rxq_mbufs(struct iavf_rx_queue *rxq)
 280 {
 281         volatile union iavf_rx_desc *rxd;
 282         struct rte_mbuf *mbuf = NULL;
 283         uint64_t dma_addr;
 284         uint16_t i, j;
 285
 286         for (i = 0; i < rxq->nb_rx_desc; i++) {
 287                 mbuf = rte_mbuf_raw_alloc(rxq->mp);
 288                 if (unlikely(!mbuf)) {
 289                         for (j = 0; j < i; j++) {
 290                                 rte_pktmbuf_free_seg(rxq->sw_ring[j]);
 291                                 rxq->sw_ring[j] = NULL;
 292                         }
 293                         PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
 294                         return -ENOMEM;
 295                 }
 296
 297                 rte_mbuf_refcnt_set(mbuf, 1);
 298                 mbuf->next = NULL;
 299                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
 300                 mbuf->nb_segs = 1;
 301                 mbuf->port = rxq->port_id;
 302
 303                 dma_addr =
 304                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
 305
 306                 rxd = &rxq->rx_ring[i];
 307                 rxd->read.pkt_addr = dma_addr;
 308                 rxd->read.hdr_addr = 0;
 309 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
 310                 rxd->read.rsvd1 = 0;
 311                 rxd->read.rsvd2 = 0;
 312 #endif
 313
 314                 rxq->sw_ring[i] = mbuf;
 315         }
 316
 317         return 0;
 318 }
 319
 320 static inline void
 321 release_rxq_mbufs(struct iavf_rx_queue *rxq)
 322 {
 323         uint16_t i;
 324
 325         if (!rxq->sw_ring)
 326                 return;
 327
 328         for (i = 0; i < rxq->nb_rx_desc; i++) {
 329                 if (rxq->sw_ring[i]) {
 330                         rte_pktmbuf_free_seg(rxq->sw_ring[i]);
 331                         rxq->sw_ring[i] = NULL;
 332                 }
 333         }
 334
 335         /* for rx bulk */
 336         if (rxq->rx_nb_avail == 0)
 337                 return;
 338         for (i = 0; i < rxq->rx_nb_avail; i++) {
 339                 struct rte_mbuf *mbuf;
 340
 341                 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
 342                 rte_pktmbuf_free_seg(mbuf);
 343         }
 344         rxq->rx_nb_avail = 0;
 345 }
 346
 347 static inline void
 348 release_txq_mbufs(struct iavf_tx_queue *txq)
 349 {
 350         uint16_t i;
 351
 352         if (!txq || !txq->sw_ring) {
 353                 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
 354                 return;
 355         }
 356
 357         for (i = 0; i < txq->nb_tx_desc; i++) {
 358                 if (txq->sw_ring[i].mbuf) {
 359                         rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
 360                         txq->sw_ring[i].mbuf = NULL;
 361                 }
 362         }
 363 }
 364
 365 static const struct iavf_rxq_ops def_rxq_ops = {
 366         .release_mbufs = release_rxq_mbufs,
 367 };
 368
 369 static const struct iavf_txq_ops def_txq_ops = {
 370         .release_mbufs = release_txq_mbufs,
 371 };
 372
 373 static inline void
 374 iavf_rxd_to_pkt_fields_by_comms_ovs(__rte_unused struct iavf_rx_queue *rxq,
 375                                     struct rte_mbuf *mb,
 376                                     volatile union iavf_rx_flex_desc *rxdp)
 377 {
 378         volatile struct iavf_32b_rx_flex_desc_comms_ovs *desc =
 379                         (volatile struct iavf_32b_rx_flex_desc_comms_ovs *)rxdp;
 380 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
 381         uint16_t stat_err;
 382 #endif
 383
 384         if (desc->flow_id != 0xFFFFFFFF) {
 385                 mb->ol_flags |= RTE_MBUF_F_RX_FDIR | RTE_MBUF_F_RX_FDIR_ID;
 386                 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
 387         }
 388
 389 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
 390         stat_err = rte_le_to_cpu_16(desc->status_error0);
 391         if (likely(stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
 392                 mb->ol_flags |= RTE_MBUF_F_RX_RSS_HASH;
 393                 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
 394         }
 395 #endif
 396 }
 397
 398 static inline void
 399 iavf_rxd_to_pkt_fields_by_comms_aux_v1(struct iavf_rx_queue *rxq,
 400                                        struct rte_mbuf *mb,
 401                                        volatile union iavf_rx_flex_desc *rxdp)
 402 {
 403         volatile struct iavf_32b_rx_flex_desc_comms *desc =
 404                         (volatile struct iavf_32b_rx_flex_desc_comms *)rxdp;
 405         uint16_t stat_err;
 406
 407         stat_err = rte_le_to_cpu_16(desc->status_error0);
 408         if (likely(stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
 409                 mb->ol_flags |= RTE_MBUF_F_RX_RSS_HASH;
 410                 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
 411         }
 412
 413 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
 414         if (desc->flow_id != 0xFFFFFFFF) {
 415                 mb->ol_flags |= RTE_MBUF_F_RX_FDIR | RTE_MBUF_F_RX_FDIR_ID;
 416                 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
 417         }
 418
 419         if (rxq->xtr_ol_flag) {
 420                 uint32_t metadata = 0;
 421
 422                 stat_err = rte_le_to_cpu_16(desc->status_error1);
 423
 424                 if (stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS1_XTRMD4_VALID_S))
 425                         metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux0);
 426
 427                 if (stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS1_XTRMD5_VALID_S))
 428                         metadata |=
 429                                 rte_le_to_cpu_16(desc->flex_ts.flex.aux1) << 16;
 430
 431                 if (metadata) {
 432                         mb->ol_flags |= rxq->xtr_ol_flag;
 433
 434                         *RTE_PMD_IFD_DYNF_PROTO_XTR_METADATA(mb) = metadata;
 435                 }
 436         }
 437 #endif
 438 }
 439
 440 static inline void
 441 iavf_rxd_to_pkt_fields_by_comms_aux_v2(struct iavf_rx_queue *rxq,
 442                                        struct rte_mbuf *mb,
 443                                        volatile union iavf_rx_flex_desc *rxdp)
 444 {
 445         volatile struct iavf_32b_rx_flex_desc_comms *desc =
 446                         (volatile struct iavf_32b_rx_flex_desc_comms *)rxdp;
 447         uint16_t stat_err;
 448
 449         stat_err = rte_le_to_cpu_16(desc->status_error0);
 450         if (likely(stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
 451                 mb->ol_flags |= RTE_MBUF_F_RX_RSS_HASH;
 452                 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
 453         }
 454
 455 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
 456         if (desc->flow_id != 0xFFFFFFFF) {
 457                 mb->ol_flags |= RTE_MBUF_F_RX_FDIR | RTE_MBUF_F_RX_FDIR_ID;
 458                 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
 459         }
 460
 461         if (rxq->xtr_ol_flag) {
 462                 uint32_t metadata = 0;
 463
 464                 if (desc->flex_ts.flex.aux0 != 0xFFFF)
 465                         metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux0);
 466                 else if (desc->flex_ts.flex.aux1 != 0xFFFF)
 467                         metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux1);
 468
 469                 if (metadata) {
 470                         mb->ol_flags |= rxq->xtr_ol_flag;
 471
 472                         *RTE_PMD_IFD_DYNF_PROTO_XTR_METADATA(mb) = metadata;
 473                 }
 474         }
 475 #endif
 476 }
 477
 478 static const
 479 iavf_rxd_to_pkt_fields_t rxd_to_pkt_fields_ops[IAVF_RXDID_LAST + 1] = {
 480         [IAVF_RXDID_LEGACY_0] = iavf_rxd_to_pkt_fields_by_comms_ovs,
 481         [IAVF_RXDID_LEGACY_1] = iavf_rxd_to_pkt_fields_by_comms_ovs,
 482         [IAVF_RXDID_COMMS_AUX_VLAN] = iavf_rxd_to_pkt_fields_by_comms_aux_v1,
 483         [IAVF_RXDID_COMMS_AUX_IPV4] = iavf_rxd_to_pkt_fields_by_comms_aux_v1,
 484         [IAVF_RXDID_COMMS_AUX_IPV6] = iavf_rxd_to_pkt_fields_by_comms_aux_v1,
 485         [IAVF_RXDID_COMMS_AUX_IPV6_FLOW] =
 486                 iavf_rxd_to_pkt_fields_by_comms_aux_v1,
 487         [IAVF_RXDID_COMMS_AUX_TCP] = iavf_rxd_to_pkt_fields_by_comms_aux_v1,
 488         [IAVF_RXDID_COMMS_AUX_IP_OFFSET] =
 489                 iavf_rxd_to_pkt_fields_by_comms_aux_v2,
 490         [IAVF_RXDID_COMMS_IPSEC_CRYPTO] =
 491                 iavf_rxd_to_pkt_fields_by_comms_aux_v2,
 492         [IAVF_RXDID_COMMS_OVS_1] = iavf_rxd_to_pkt_fields_by_comms_ovs,
 493 };
 494
 495 static void
 496 iavf_select_rxd_to_pkt_fields_handler(struct iavf_rx_queue *rxq, uint32_t rxdid)
 497 {
 498         rxq->rxdid = rxdid;
 499
 500         switch (rxdid) {
 501         case IAVF_RXDID_COMMS_AUX_VLAN:
 502                 rxq->xtr_ol_flag = rte_pmd_ifd_dynflag_proto_xtr_vlan_mask;
 503                 break;
 504         case IAVF_RXDID_COMMS_AUX_IPV4:
 505                 rxq->xtr_ol_flag = rte_pmd_ifd_dynflag_proto_xtr_ipv4_mask;
 506                 break;
 507         case IAVF_RXDID_COMMS_AUX_IPV6:
 508                 rxq->xtr_ol_flag = rte_pmd_ifd_dynflag_proto_xtr_ipv6_mask;
 509                 break;
 510         case IAVF_RXDID_COMMS_AUX_IPV6_FLOW:
 511                 rxq->xtr_ol_flag =
 512                         rte_pmd_ifd_dynflag_proto_xtr_ipv6_flow_mask;
 513                 break;
 514         case IAVF_RXDID_COMMS_AUX_TCP:
 515                 rxq->xtr_ol_flag = rte_pmd_ifd_dynflag_proto_xtr_tcp_mask;
 516                 break;
 517         case IAVF_RXDID_COMMS_AUX_IP_OFFSET:
 518                 rxq->xtr_ol_flag =
 519                         rte_pmd_ifd_dynflag_proto_xtr_ip_offset_mask;
 520                 break;
 521         case IAVF_RXDID_COMMS_IPSEC_CRYPTO:
 522                 rxq->xtr_ol_flag =
 523                         rte_pmd_ifd_dynflag_proto_xtr_ipsec_crypto_said_mask;
 524                 break;
 525         case IAVF_RXDID_COMMS_OVS_1:
 526         case IAVF_RXDID_LEGACY_0:
 527         case IAVF_RXDID_LEGACY_1:
 528                 break;
 529         default:
 530                 /* update this according to the RXDID for FLEX_DESC_NONE */
 531                 rxq->rxdid = IAVF_RXDID_COMMS_OVS_1;
 532                 break;
 533         }
 534
 535         if (!rte_pmd_ifd_dynf_proto_xtr_metadata_avail())
 536                 rxq->xtr_ol_flag = 0;
 537 }
 538
 539 int
 540 iavf_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 541                        uint16_t nb_desc, unsigned int socket_id,
 542                        const struct rte_eth_rxconf *rx_conf,
 543                        struct rte_mempool *mp)
 544 {
 545         struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 546         struct iavf_adapter *ad =
 547                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 548         struct iavf_info *vf =
 549                 IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 550         struct iavf_vsi *vsi = &vf->vsi;
 551         struct iavf_rx_queue *rxq;
 552         const struct rte_memzone *mz;
 553         uint32_t ring_size;
 554         uint8_t proto_xtr;
 555         uint16_t len;
 556         uint16_t rx_free_thresh;
 557         uint64_t offloads;
 558
 559         PMD_INIT_FUNC_TRACE();
 560
 561         offloads = rx_conf->offloads | dev->data->dev_conf.rxmode.offloads;
 562
 563         if (nb_desc % IAVF_ALIGN_RING_DESC != 0 ||
 564             nb_desc > IAVF_MAX_RING_DESC ||
 565             nb_desc < IAVF_MIN_RING_DESC) {
 566                 PMD_INIT_LOG(ERR, "Number (%u) of receive descriptors is "
 567                              "invalid", nb_desc);
 568                 return -EINVAL;
 569         }
 570
 571         /* Check free threshold */
 572         rx_free_thresh = (rx_conf->rx_free_thresh == 0) ?
 573                          IAVF_DEFAULT_RX_FREE_THRESH :
 574                          rx_conf->rx_free_thresh;
 575         if (check_rx_thresh(nb_desc, rx_free_thresh) != 0)
 576                 return -EINVAL;
 577
 578         /* Free memory if needed */
 579         if (dev->data->rx_queues[queue_idx]) {
 580                 iavf_dev_rx_queue_release(dev, queue_idx);
 581                 dev->data->rx_queues[queue_idx] = NULL;
 582         }
 583
 584         /* Allocate the rx queue data structure */
 585         rxq = rte_zmalloc_socket("iavf rxq",
 586                                  sizeof(struct iavf_rx_queue),
 587                                  RTE_CACHE_LINE_SIZE,
 588                                  socket_id);
 589         if (!rxq) {
 590                 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
 591                              "rx queue data structure");
 592                 return -ENOMEM;
 593         }
 594
 595         if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC) {
 596                 proto_xtr = vf->proto_xtr ? vf->proto_xtr[queue_idx] :
 597                                 IAVF_PROTO_XTR_NONE;
 598                 rxq->rxdid = iavf_proto_xtr_type_to_rxdid(proto_xtr);
 599                 rxq->proto_xtr = proto_xtr;
 600         } else {
 601                 rxq->rxdid = IAVF_RXDID_LEGACY_1;
 602                 rxq->proto_xtr = IAVF_PROTO_XTR_NONE;
 603         }
 604
 605         if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_VLAN_V2) {
 606                 struct virtchnl_vlan_supported_caps *stripping_support =
 607                                 &vf->vlan_v2_caps.offloads.stripping_support;
 608                 uint32_t stripping_cap;
 609
 610                 if (stripping_support->outer)
 611                         stripping_cap = stripping_support->outer;
 612                 else
 613                         stripping_cap = stripping_support->inner;
 614
 615                 if (stripping_cap & VIRTCHNL_VLAN_TAG_LOCATION_L2TAG1)
 616                         rxq->rx_flags = IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG1;
 617                 else if (stripping_cap & VIRTCHNL_VLAN_TAG_LOCATION_L2TAG2_2)
 618                         rxq->rx_flags = IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG2_2;
 619         } else {
 620                 rxq->rx_flags = IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG1;
 621         }
 622
 623         iavf_select_rxd_to_pkt_fields_handler(rxq, rxq->rxdid);
 624
 625         rxq->mp = mp;
 626         rxq->nb_rx_desc = nb_desc;
 627         rxq->rx_free_thresh = rx_free_thresh;
 628         rxq->queue_id = queue_idx;
 629         rxq->port_id = dev->data->port_id;
 630         rxq->rx_deferred_start = rx_conf->rx_deferred_start;
 631         rxq->rx_hdr_len = 0;
 632         rxq->vsi = vsi;
 633         rxq->offloads = offloads;
 634
 635         if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_KEEP_CRC)
 636                 rxq->crc_len = RTE_ETHER_CRC_LEN;
 637         else
 638                 rxq->crc_len = 0;
 639
 640         len = rte_pktmbuf_data_room_size(rxq->mp) - RTE_PKTMBUF_HEADROOM;
 641         rxq->rx_buf_len = RTE_ALIGN_FLOOR(len, (1 << IAVF_RXQ_CTX_DBUFF_SHIFT));
 642
 643         /* Allocate the software ring. */
 644         len = nb_desc + IAVF_RX_MAX_BURST;
 645         rxq->sw_ring =
 646                 rte_zmalloc_socket("iavf rx sw ring",
 647                                    sizeof(struct rte_mbuf *) * len,
 648                                    RTE_CACHE_LINE_SIZE,
 649                                    socket_id);
 650         if (!rxq->sw_ring) {
 651                 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW ring");
 652                 rte_free(rxq);
 653                 return -ENOMEM;
 654         }
 655
 656         /* Allocate the maximum number of RX ring hardware descriptor with
 657          * a little more to support bulk allocate.
 658          */
 659         len = IAVF_MAX_RING_DESC + IAVF_RX_MAX_BURST;
 660         ring_size = RTE_ALIGN(len * sizeof(union iavf_rx_desc),
 661                               IAVF_DMA_MEM_ALIGN);
 662         mz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
 663                                       ring_size, IAVF_RING_BASE_ALIGN,
 664                                       socket_id);
 665         if (!mz) {
 666                 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for RX");
 667                 rte_free(rxq->sw_ring);
 668                 rte_free(rxq);
 669                 return -ENOMEM;
 670         }
 671         /* Zero all the descriptors in the ring. */
 672         memset(mz->addr, 0, ring_size);
 673         rxq->rx_ring_phys_addr = mz->iova;
 674         rxq->rx_ring = (union iavf_rx_desc *)mz->addr;
 675
 676         rxq->mz = mz;
 677         reset_rx_queue(rxq);
 678         rxq->q_set = true;
 679         dev->data->rx_queues[queue_idx] = rxq;
 680         rxq->qrx_tail = hw->hw_addr + IAVF_QRX_TAIL1(rxq->queue_id);
 681         rxq->ops = &def_rxq_ops;
 682
 683         if (check_rx_bulk_allow(rxq) == true) {
 684                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
 685                              "satisfied. Rx Burst Bulk Alloc function will be "
 686                              "used on port=%d, queue=%d.",
 687                              rxq->port_id, rxq->queue_id);
 688         } else {
 689                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
 690                              "not satisfied, Scattered Rx is requested "
 691                              "on port=%d, queue=%d.",
 692                              rxq->port_id, rxq->queue_id);
 693                 ad->rx_bulk_alloc_allowed = false;
 694         }
 695
 696         if (check_rx_vec_allow(rxq) == false)
 697                 ad->rx_vec_allowed = false;
 698
 699         return 0;
 700 }
 701
 702 int
 703 iavf_dev_tx_queue_setup(struct rte_eth_dev *dev,
 704                        uint16_t queue_idx,
 705                        uint16_t nb_desc,
 706                        unsigned int socket_id,
 707                        const struct rte_eth_txconf *tx_conf)
 708 {
 709         struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 710         struct iavf_adapter *adapter =
 711                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 712         struct iavf_info *vf =
 713                 IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 714         struct iavf_tx_queue *txq;
 715         const struct rte_memzone *mz;
 716         uint32_t ring_size;
 717         uint16_t tx_rs_thresh, tx_free_thresh;
 718         uint64_t offloads;
 719
 720         PMD_INIT_FUNC_TRACE();
 721
 722         offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
 723
 724         if (nb_desc % IAVF_ALIGN_RING_DESC != 0 ||
 725             nb_desc > IAVF_MAX_RING_DESC ||
 726             nb_desc < IAVF_MIN_RING_DESC) {
 727                 PMD_INIT_LOG(ERR, "Number (%u) of transmit descriptors is "
 728                             "invalid", nb_desc);
 729                 return -EINVAL;
 730         }
 731
 732         tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
 733                 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
 734         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
 735                 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
 736         if (check_tx_thresh(nb_desc, tx_rs_thresh, tx_free_thresh) != 0)
 737                 return -EINVAL;
 738
 739         /* Free memory if needed. */
 740         if (dev->data->tx_queues[queue_idx]) {
 741                 iavf_dev_tx_queue_release(dev, queue_idx);
 742                 dev->data->tx_queues[queue_idx] = NULL;
 743         }
 744
 745         /* Allocate the TX queue data structure. */
 746         txq = rte_zmalloc_socket("iavf txq",
 747                                  sizeof(struct iavf_tx_queue),
 748                                  RTE_CACHE_LINE_SIZE,
 749                                  socket_id);
 750         if (!txq) {
 751                 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
 752                              "tx queue structure");
 753                 return -ENOMEM;
 754         }
 755
 756         if (adapter->vf.vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_VLAN_V2) {
 757                 struct virtchnl_vlan_supported_caps *insertion_support =
 758                         &adapter->vf.vlan_v2_caps.offloads.insertion_support;
 759                 uint32_t insertion_cap;
 760
 761                 if (insertion_support->outer)
 762                         insertion_cap = insertion_support->outer;
 763                 else
 764                         insertion_cap = insertion_support->inner;
 765
 766                 if (insertion_cap & VIRTCHNL_VLAN_TAG_LOCATION_L2TAG1)
 767                         txq->vlan_flag = IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG1;
 768                 else if (insertion_cap & VIRTCHNL_VLAN_TAG_LOCATION_L2TAG2)
 769                         txq->vlan_flag = IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG2;
 770         } else {
 771                 txq->vlan_flag = IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG1;
 772         }
 773
 774         txq->nb_tx_desc = nb_desc;
 775         txq->rs_thresh = tx_rs_thresh;
 776         txq->free_thresh = tx_free_thresh;
 777         txq->queue_id = queue_idx;
 778         txq->port_id = dev->data->port_id;
 779         txq->offloads = offloads;
 780         txq->tx_deferred_start = tx_conf->tx_deferred_start;
 781
 782         if (iavf_ipsec_crypto_supported(adapter))
 783                 txq->ipsec_crypto_pkt_md_offset =
 784                         iavf_security_get_pkt_md_offset(adapter);
 785
 786         /* Allocate software ring */
 787         txq->sw_ring =
 788                 rte_zmalloc_socket("iavf tx sw ring",
 789                                    sizeof(struct iavf_tx_entry) * nb_desc,
 790                                    RTE_CACHE_LINE_SIZE,
 791                                    socket_id);
 792         if (!txq->sw_ring) {
 793                 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW TX ring");
 794                 rte_free(txq);
 795                 return -ENOMEM;
 796         }
 797
 798         /* Allocate TX hardware ring descriptors. */
 799         ring_size = sizeof(struct iavf_tx_desc) * IAVF_MAX_RING_DESC;
 800         ring_size = RTE_ALIGN(ring_size, IAVF_DMA_MEM_ALIGN);
 801         mz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
 802                                       ring_size, IAVF_RING_BASE_ALIGN,
 803                                       socket_id);
 804         if (!mz) {
 805                 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for TX");
 806                 rte_free(txq->sw_ring);
 807                 rte_free(txq);
 808                 return -ENOMEM;
 809         }
 810         txq->tx_ring_phys_addr = mz->iova;
 811         txq->tx_ring = (struct iavf_tx_desc *)mz->addr;
 812
 813         txq->mz = mz;
 814         reset_tx_queue(txq);
 815         txq->q_set = true;
 816         dev->data->tx_queues[queue_idx] = txq;
 817         txq->qtx_tail = hw->hw_addr + IAVF_QTX_TAIL1(queue_idx);
 818         txq->ops = &def_txq_ops;
 819
 820         if (check_tx_vec_allow(txq) == false) {
 821                 struct iavf_adapter *ad =
 822                         IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 823                 ad->tx_vec_allowed = false;
 824         }
 825
 826         if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_QOS &&
 827             vf->tm_conf.committed) {
 828                 int tc;
 829                 for (tc = 0; tc < vf->qos_cap->num_elem; tc++) {
 830                         if (txq->queue_id >= vf->qtc_map[tc].start_queue_id &&
 831                             txq->queue_id < (vf->qtc_map[tc].start_queue_id +
 832                             vf->qtc_map[tc].queue_count))
 833                                 break;
 834                 }
 835                 if (tc >= vf->qos_cap->num_elem) {
 836                         PMD_INIT_LOG(ERR, "Queue TC mapping is not correct");
 837                         return -EINVAL;
 838                 }
 839                 txq->tc = tc;
 840         }
 841
 842         return 0;
 843 }
 844
 845 int
 846 iavf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 847 {
 848         struct iavf_adapter *adapter =
 849                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 850         struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 851         struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 852         struct iavf_rx_queue *rxq;
 853         int err = 0;
 854
 855         PMD_DRV_FUNC_TRACE();
 856
 857         if (rx_queue_id >= dev->data->nb_rx_queues)
 858                 return -EINVAL;
 859
 860         rxq = dev->data->rx_queues[rx_queue_id];
 861
 862         err = alloc_rxq_mbufs(rxq);
 863         if (err) {
 864                 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
 865                 return err;
 866         }
 867
 868         rte_wmb();
 869
 870         /* Init the RX tail register. */
 871         IAVF_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 872         IAVF_WRITE_FLUSH(hw);
 873
 874         /* Ready to switch the queue on */
 875         if (!vf->lv_enabled)
 876                 err = iavf_switch_queue(adapter, rx_queue_id, true, true);
 877         else
 878                 err = iavf_switch_queue_lv(adapter, rx_queue_id, true, true);
 879
 880         if (err) {
 881                 release_rxq_mbufs(rxq);
 882                 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
 883                             rx_queue_id);
 884         } else {
 885                 dev->data->rx_queue_state[rx_queue_id] =
 886                         RTE_ETH_QUEUE_STATE_STARTED;
 887         }
 888
 889         return err;
 890 }
 891
 892 int
 893 iavf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 894 {
 895         struct iavf_adapter *adapter =
 896                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 897         struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 898         struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 899         struct iavf_tx_queue *txq;
 900         int err = 0;
 901
 902         PMD_DRV_FUNC_TRACE();
 903
 904         if (tx_queue_id >= dev->data->nb_tx_queues)
 905                 return -EINVAL;
 906
 907         txq = dev->data->tx_queues[tx_queue_id];
 908
 909         /* Init the RX tail register. */
 910         IAVF_PCI_REG_WRITE(txq->qtx_tail, 0);
 911         IAVF_WRITE_FLUSH(hw);
 912
 913         /* Ready to switch the queue on */
 914         if (!vf->lv_enabled)
 915                 err = iavf_switch_queue(adapter, tx_queue_id, false, true);
 916         else
 917                 err = iavf_switch_queue_lv(adapter, tx_queue_id, false, true);
 918
 919         if (err)
 920                 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
 921                             tx_queue_id);
 922         else
 923                 dev->data->tx_queue_state[tx_queue_id] =
 924                         RTE_ETH_QUEUE_STATE_STARTED;
 925
 926         return err;
 927 }
 928
 929 int
 930 iavf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 931 {
 932         struct iavf_adapter *adapter =
 933                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 934         struct iavf_rx_queue *rxq;
 935         int err;
 936
 937         PMD_DRV_FUNC_TRACE();
 938
 939         if (rx_queue_id >= dev->data->nb_rx_queues)
 940                 return -EINVAL;
 941
 942         err = iavf_switch_queue(adapter, rx_queue_id, true, false);
 943         if (err) {
 944                 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
 945                             rx_queue_id);
 946                 return err;
 947         }
 948
 949         rxq = dev->data->rx_queues[rx_queue_id];
 950         rxq->ops->release_mbufs(rxq);
 951         reset_rx_queue(rxq);
 952         dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 953
 954         return 0;
 955 }
 956
 957 int
 958 iavf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 959 {
 960         struct iavf_adapter *adapter =
 961                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 962         struct iavf_tx_queue *txq;
 963         int err;
 964
 965         PMD_DRV_FUNC_TRACE();
 966
 967         if (tx_queue_id >= dev->data->nb_tx_queues)
 968                 return -EINVAL;
 969
 970         err = iavf_switch_queue(adapter, tx_queue_id, false, false);
 971         if (err) {
 972                 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u off",
 973                             tx_queue_id);
 974                 return err;
 975         }
 976
 977         txq = dev->data->tx_queues[tx_queue_id];
 978         txq->ops->release_mbufs(txq);
 979         reset_tx_queue(txq);
 980         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 981
 982         return 0;
 983 }
 984
 985 void
 986 iavf_dev_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
 987 {
 988         struct iavf_rx_queue *q = dev->data->rx_queues[qid];
 989
 990         if (!q)
 991                 return;
 992
 993         q->ops->release_mbufs(q);
 994         rte_free(q->sw_ring);
 995         rte_memzone_free(q->mz);
 996         rte_free(q);
 997 }
 998
 999 void
1000 iavf_dev_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
1001 {
1002         struct iavf_tx_queue *q = dev->data->tx_queues[qid];
1003
1004         if (!q)
1005                 return;
1006
1007         q->ops->release_mbufs(q);
1008         rte_free(q->sw_ring);
1009         rte_memzone_free(q->mz);
1010         rte_free(q);
1011 }
1012
1013 void
1014 iavf_stop_queues(struct rte_eth_dev *dev)
1015 {
1016         struct iavf_adapter *adapter =
1017                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1018         struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1019         struct iavf_rx_queue *rxq;
1020         struct iavf_tx_queue *txq;
1021         int ret, i;
1022
1023         /* Stop All queues */
1024         if (!vf->lv_enabled) {
1025                 ret = iavf_disable_queues(adapter);
1026                 if (ret)
1027                         PMD_DRV_LOG(WARNING, "Fail to stop queues");
1028         } else {
1029                 ret = iavf_disable_queues_lv(adapter);
1030                 if (ret)
1031                         PMD_DRV_LOG(WARNING, "Fail to stop queues for large VF");
1032         }
1033
1034         if (ret)
1035                 PMD_DRV_LOG(WARNING, "Fail to stop queues");
1036
1037         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1038                 txq = dev->data->tx_queues[i];
1039                 if (!txq)
1040                         continue;
1041                 txq->ops->release_mbufs(txq);
1042                 reset_tx_queue(txq);
1043                 dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED;
1044         }
1045         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1046                 rxq = dev->data->rx_queues[i];
1047                 if (!rxq)
1048                         continue;
1049                 rxq->ops->release_mbufs(rxq);
1050                 reset_rx_queue(rxq);
1051                 dev->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED;
1052         }
1053 }
1054
1055 #define IAVF_RX_FLEX_ERR0_BITS  \
1056         ((1 << IAVF_RX_FLEX_DESC_STATUS0_HBO_S) |       \
1057          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_IPE_S) |  \
1058          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_L4E_S) |  \
1059          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S) | \
1060          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S) |        \
1061          (1 << IAVF_RX_FLEX_DESC_STATUS0_RXE_S))
1062
1063 static inline void
1064 iavf_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union iavf_rx_desc *rxdp)
1065 {
1066         if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1067                 (1 << IAVF_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
1068                 mb->ol_flags |= RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED;
1069                 mb->vlan_tci =
1070                         rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
1071         } else {
1072                 mb->vlan_tci = 0;
1073         }
1074 }
1075
1076 static inline void
1077 iavf_flex_rxd_to_vlan_tci(struct rte_mbuf *mb,
1078                           volatile union iavf_rx_flex_desc *rxdp)
1079 {
1080         if (rte_le_to_cpu_64(rxdp->wb.status_error0) &
1081                 (1 << IAVF_RX_FLEX_DESC_STATUS0_L2TAG1P_S)) {
1082                 mb->ol_flags |= RTE_MBUF_F_RX_VLAN |
1083                                 RTE_MBUF_F_RX_VLAN_STRIPPED;
1084                 mb->vlan_tci =
1085                         rte_le_to_cpu_16(rxdp->wb.l2tag1);
1086         } else {
1087                 mb->vlan_tci = 0;
1088         }
1089
1090 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
1091         if (rte_le_to_cpu_16(rxdp->wb.status_error1) &
1092             (1 << IAVF_RX_FLEX_DESC_STATUS1_L2TAG2P_S)) {
1093                 mb->ol_flags |= RTE_MBUF_F_RX_QINQ_STRIPPED |
1094                                 RTE_MBUF_F_RX_QINQ |
1095                                 RTE_MBUF_F_RX_VLAN_STRIPPED |
1096                                 RTE_MBUF_F_RX_VLAN;
1097                 mb->vlan_tci_outer = mb->vlan_tci;
1098                 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.l2tag2_2nd);
1099                 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
1100                            rte_le_to_cpu_16(rxdp->wb.l2tag2_1st),
1101                            rte_le_to_cpu_16(rxdp->wb.l2tag2_2nd));
1102         } else {
1103                 mb->vlan_tci_outer = 0;
1104         }
1105 #endif
1106 }
1107
1108 static inline void
1109 iavf_flex_rxd_to_ipsec_crypto_said_get(struct rte_mbuf *mb,
1110                           volatile union iavf_rx_flex_desc *rxdp)
1111 {
1112         volatile struct iavf_32b_rx_flex_desc_comms_ipsec *desc =
1113                 (volatile struct iavf_32b_rx_flex_desc_comms_ipsec *)rxdp;
1114
1115         mb->dynfield1[0] = desc->ipsec_said &
1116                          IAVF_RX_FLEX_DESC_IPSEC_CRYPTO_SAID_MASK;
1117         }
1118
1119 static inline void
1120 iavf_flex_rxd_to_ipsec_crypto_status(struct rte_mbuf *mb,
1121                           volatile union iavf_rx_flex_desc *rxdp,
1122                           struct iavf_ipsec_crypto_stats *stats)
1123 {
1124         uint16_t status1 = rte_le_to_cpu_64(rxdp->wb.status_error1);
1125
1126         if (status1 & BIT(IAVF_RX_FLEX_DESC_STATUS1_IPSEC_CRYPTO_PROCESSED)) {
1127                 uint16_t ipsec_status;
1128
1129                 mb->ol_flags |= RTE_MBUF_F_RX_SEC_OFFLOAD;
1130
1131                 ipsec_status = status1 &
1132                         IAVF_RX_FLEX_DESC_IPSEC_CRYPTO_STATUS_MASK;
1133
1134
1135                 if (unlikely(ipsec_status !=
1136                         IAVF_IPSEC_CRYPTO_STATUS_SUCCESS)) {
1137                         mb->ol_flags |= RTE_MBUF_F_RX_SEC_OFFLOAD_FAILED;
1138
1139                         switch (ipsec_status) {
1140                         case IAVF_IPSEC_CRYPTO_STATUS_SAD_MISS:
1141                                 stats->ierrors.sad_miss++;
1142                                 break;
1143                         case IAVF_IPSEC_CRYPTO_STATUS_NOT_PROCESSED:
1144                                 stats->ierrors.not_processed++;
1145                                 break;
1146                         case IAVF_IPSEC_CRYPTO_STATUS_ICV_CHECK_FAIL:
1147                                 stats->ierrors.icv_check++;
1148                                 break;
1149                         case IAVF_IPSEC_CRYPTO_STATUS_LENGTH_ERR:
1150                                 stats->ierrors.ipsec_length++;
1151                                 break;
1152                         case IAVF_IPSEC_CRYPTO_STATUS_MISC_ERR:
1153                                 stats->ierrors.misc++;
1154                                 break;
1155 }
1156
1157                         stats->ierrors.count++;
1158                         return;
1159                 }
1160
1161                 stats->icount++;
1162                 stats->ibytes += rxdp->wb.pkt_len & 0x3FFF;
1163
1164                 if (rxdp->wb.rxdid == IAVF_RXDID_COMMS_IPSEC_CRYPTO &&
1165                         ipsec_status !=
1166                                 IAVF_IPSEC_CRYPTO_STATUS_SAD_MISS)
1167                         iavf_flex_rxd_to_ipsec_crypto_said_get(mb, rxdp);
1168         }
1169 }
1170
1171
1172 /* Translate the rx descriptor status and error fields to pkt flags */
1173 static inline uint64_t
1174 iavf_rxd_to_pkt_flags(uint64_t qword)
1175 {
1176         uint64_t flags;
1177         uint64_t error_bits = (qword >> IAVF_RXD_QW1_ERROR_SHIFT);
1178
1179 #define IAVF_RX_ERR_BITS 0x3f
1180
1181         /* Check if RSS_HASH */
1182         flags = (((qword >> IAVF_RX_DESC_STATUS_FLTSTAT_SHIFT) &
1183                                         IAVF_RX_DESC_FLTSTAT_RSS_HASH) ==
1184                         IAVF_RX_DESC_FLTSTAT_RSS_HASH) ? RTE_MBUF_F_RX_RSS_HASH : 0;
1185
1186         /* Check if FDIR Match */
1187         flags |= (qword & (1 << IAVF_RX_DESC_STATUS_FLM_SHIFT) ?
1188                                 RTE_MBUF_F_RX_FDIR : 0);
1189
1190         if (likely((error_bits & IAVF_RX_ERR_BITS) == 0)) {
1191                 flags |= (RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_GOOD);
1192                 return flags;
1193         }
1194
1195         if (unlikely(error_bits & (1 << IAVF_RX_DESC_ERROR_IPE_SHIFT)))
1196                 flags |= RTE_MBUF_F_RX_IP_CKSUM_BAD;
1197         else
1198                 flags |= RTE_MBUF_F_RX_IP_CKSUM_GOOD;
1199
1200         if (unlikely(error_bits & (1 << IAVF_RX_DESC_ERROR_L4E_SHIFT)))
1201                 flags |= RTE_MBUF_F_RX_L4_CKSUM_BAD;
1202         else
1203                 flags |= RTE_MBUF_F_RX_L4_CKSUM_GOOD;
1204
1205         /* TODO: Oversize error bit is not processed here */
1206
1207         return flags;
1208 }
1209
1210 static inline uint64_t
1211 iavf_rxd_build_fdir(volatile union iavf_rx_desc *rxdp, struct rte_mbuf *mb)
1212 {
1213         uint64_t flags = 0;
1214 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
1215         uint16_t flexbh;
1216
1217         flexbh = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
1218                 IAVF_RX_DESC_EXT_STATUS_FLEXBH_SHIFT) &
1219                 IAVF_RX_DESC_EXT_STATUS_FLEXBH_MASK;
1220
1221         if (flexbh == IAVF_RX_DESC_EXT_STATUS_FLEXBH_FD_ID) {
1222                 mb->hash.fdir.hi =
1223                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.fd_id);
1224                 flags |= RTE_MBUF_F_RX_FDIR_ID;
1225         }
1226 #else
1227         mb->hash.fdir.hi =
1228                 rte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.fd_id);
1229         flags |= RTE_MBUF_F_RX_FDIR_ID;
1230 #endif
1231         return flags;
1232 }
1233
1234 #define IAVF_RX_FLEX_ERR0_BITS  \
1235         ((1 << IAVF_RX_FLEX_DESC_STATUS0_HBO_S) |       \
1236          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_IPE_S) |  \
1237          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_L4E_S) |  \
1238          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S) | \
1239          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S) |        \
1240          (1 << IAVF_RX_FLEX_DESC_STATUS0_RXE_S))
1241
1242 /* Rx L3/L4 checksum */
1243 static inline uint64_t
1244 iavf_flex_rxd_error_to_pkt_flags(uint16_t stat_err0)
1245 {
1246         uint64_t flags = 0;
1247
1248         /* check if HW has decoded the packet and checksum */
1249         if (unlikely(!(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_L3L4P_S))))
1250                 return 0;
1251
1252         if (likely(!(stat_err0 & IAVF_RX_FLEX_ERR0_BITS))) {
1253                 flags |= (RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_GOOD);
1254                 return flags;
1255         }
1256
1257         if (unlikely(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_IPE_S)))
1258                 flags |= RTE_MBUF_F_RX_IP_CKSUM_BAD;
1259         else
1260                 flags |= RTE_MBUF_F_RX_IP_CKSUM_GOOD;
1261
1262         if (unlikely(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_L4E_S)))
1263                 flags |= RTE_MBUF_F_RX_L4_CKSUM_BAD;
1264         else
1265                 flags |= RTE_MBUF_F_RX_L4_CKSUM_GOOD;
1266
1267         if (unlikely(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S)))
1268                 flags |= RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD;
1269
1270         return flags;
1271 }
1272
1273 /* If the number of free RX descriptors is greater than the RX free
1274  * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1275  * register. Update the RDT with the value of the last processed RX
1276  * descriptor minus 1, to guarantee that the RDT register is never
1277  * equal to the RDH register, which creates a "full" ring situation
1278  * from the hardware point of view.
1279  */
1280 static inline void
1281 iavf_update_rx_tail(struct iavf_rx_queue *rxq, uint16_t nb_hold, uint16_t rx_id)
1282 {
1283         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1284
1285         if (nb_hold > rxq->rx_free_thresh) {
1286                 PMD_RX_LOG(DEBUG,
1287                            "port_id=%u queue_id=%u rx_tail=%u nb_hold=%u",
1288                            rxq->port_id, rxq->queue_id, rx_id, nb_hold);
1289                 rx_id = (uint16_t)((rx_id == 0) ?
1290                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
1291                 IAVF_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
1292                 nb_hold = 0;
1293         }
1294         rxq->nb_rx_hold = nb_hold;
1295 }
1296
1297 /* implement recv_pkts */
1298 uint16_t
1299 iavf_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1300 {
1301         volatile union iavf_rx_desc *rx_ring;
1302         volatile union iavf_rx_desc *rxdp;
1303         struct iavf_rx_queue *rxq;
1304         union iavf_rx_desc rxd;
1305         struct rte_mbuf *rxe;
1306         struct rte_eth_dev *dev;
1307         struct rte_mbuf *rxm;
1308         struct rte_mbuf *nmb;
1309         uint16_t nb_rx;
1310         uint32_t rx_status;
1311         uint64_t qword1;
1312         uint16_t rx_packet_len;
1313         uint16_t rx_id, nb_hold;
1314         uint64_t dma_addr;
1315         uint64_t pkt_flags;
1316         const uint32_t *ptype_tbl;
1317
1318         nb_rx = 0;
1319         nb_hold = 0;
1320         rxq = rx_queue;
1321         rx_id = rxq->rx_tail;
1322         rx_ring = rxq->rx_ring;
1323         ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1324
1325         while (nb_rx < nb_pkts) {
1326                 rxdp = &rx_ring[rx_id];
1327                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1328                 rx_status = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
1329                             IAVF_RXD_QW1_STATUS_SHIFT;
1330
1331                 /* Check the DD bit first */
1332                 if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)))
1333                         break;
1334                 IAVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
1335
1336                 nmb = rte_mbuf_raw_alloc(rxq->mp);
1337                 if (unlikely(!nmb)) {
1338                         dev = &rte_eth_devices[rxq->port_id];
1339                         dev->data->rx_mbuf_alloc_failed++;
1340                         PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1341                                    "queue_id=%u", rxq->port_id, rxq->queue_id);
1342                         break;
1343                 }
1344
1345                 rxd = *rxdp;
1346                 nb_hold++;
1347                 rxe = rxq->sw_ring[rx_id];
1348                 rxq->sw_ring[rx_id] = nmb;
1349                 rx_id++;
1350                 if (unlikely(rx_id == rxq->nb_rx_desc))
1351                         rx_id = 0;
1352
1353                 /* Prefetch next mbuf */
1354                 rte_prefetch0(rxq->sw_ring[rx_id]);
1355
1356                 /* When next RX descriptor is on a cache line boundary,
1357                  * prefetch the next 4 RX descriptors and next 8 pointers
1358                  * to mbufs.
1359                  */
1360                 if ((rx_id & 0x3) == 0) {
1361                         rte_prefetch0(&rx_ring[rx_id]);
1362                         rte_prefetch0(rxq->sw_ring[rx_id]);
1363                 }
1364                 rxm = rxe;
1365                 dma_addr =
1366                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1367                 rxdp->read.hdr_addr = 0;
1368                 rxdp->read.pkt_addr = dma_addr;
1369
1370                 rx_packet_len = ((qword1 & IAVF_RXD_QW1_LENGTH_PBUF_MASK) >>
1371                                 IAVF_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
1372
1373                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1374                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
1375                 rxm->nb_segs = 1;
1376                 rxm->next = NULL;
1377                 rxm->pkt_len = rx_packet_len;
1378                 rxm->data_len = rx_packet_len;
1379                 rxm->port = rxq->port_id;
1380                 rxm->ol_flags = 0;
1381                 iavf_rxd_to_vlan_tci(rxm, &rxd);
1382                 pkt_flags = iavf_rxd_to_pkt_flags(qword1);
1383                 rxm->packet_type =
1384                         ptype_tbl[(uint8_t)((qword1 &
1385                         IAVF_RXD_QW1_PTYPE_MASK) >> IAVF_RXD_QW1_PTYPE_SHIFT)];
1386
1387                 if (pkt_flags & RTE_MBUF_F_RX_RSS_HASH)
1388                         rxm->hash.rss =
1389                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1390
1391                 if (pkt_flags & RTE_MBUF_F_RX_FDIR)
1392                         pkt_flags |= iavf_rxd_build_fdir(&rxd, rxm);
1393
1394                 rxm->ol_flags |= pkt_flags;
1395
1396                 rx_pkts[nb_rx++] = rxm;
1397         }
1398         rxq->rx_tail = rx_id;
1399
1400         iavf_update_rx_tail(rxq, nb_hold, rx_id);
1401
1402         return nb_rx;
1403 }
1404
1405 /* implement recv_pkts for flexible Rx descriptor */
1406 uint16_t
1407 iavf_recv_pkts_flex_rxd(void *rx_queue,
1408                         struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1409 {
1410         volatile union iavf_rx_desc *rx_ring;
1411         volatile union iavf_rx_flex_desc *rxdp;
1412         struct iavf_rx_queue *rxq;
1413         union iavf_rx_flex_desc rxd;
1414         struct rte_mbuf *rxe;
1415         struct rte_eth_dev *dev;
1416         struct rte_mbuf *rxm;
1417         struct rte_mbuf *nmb;
1418         uint16_t nb_rx;
1419         uint16_t rx_stat_err0;
1420         uint16_t rx_packet_len;
1421         uint16_t rx_id, nb_hold;
1422         uint64_t dma_addr;
1423         uint64_t pkt_flags;
1424         const uint32_t *ptype_tbl;
1425
1426         nb_rx = 0;
1427         nb_hold = 0;
1428         rxq = rx_queue;
1429         rx_id = rxq->rx_tail;
1430         rx_ring = rxq->rx_ring;
1431         ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1432
1433         struct iavf_adapter *ad = rxq->vsi->adapter;
1434         uint64_t ts_ns;
1435
1436         if (rxq->offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP)
1437                 rxq->hw_register_set = 1;
1438
1439         while (nb_rx < nb_pkts) {
1440                 rxdp = (volatile union iavf_rx_flex_desc *)&rx_ring[rx_id];
1441                 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1442
1443                 /* Check the DD bit first */
1444                 if (!(rx_stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S)))
1445                         break;
1446                 IAVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
1447
1448                 nmb = rte_mbuf_raw_alloc(rxq->mp);
1449                 if (unlikely(!nmb)) {
1450                         dev = &rte_eth_devices[rxq->port_id];
1451                         dev->data->rx_mbuf_alloc_failed++;
1452                         PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1453                                    "queue_id=%u", rxq->port_id, rxq->queue_id);
1454                         break;
1455                 }
1456
1457                 rxd = *rxdp;
1458                 nb_hold++;
1459                 rxe = rxq->sw_ring[rx_id];
1460                 rxq->sw_ring[rx_id] = nmb;
1461                 rx_id++;
1462                 if (unlikely(rx_id == rxq->nb_rx_desc))
1463                         rx_id = 0;
1464
1465                 /* Prefetch next mbuf */
1466                 rte_prefetch0(rxq->sw_ring[rx_id]);
1467
1468                 /* When next RX descriptor is on a cache line boundary,
1469                  * prefetch the next 4 RX descriptors and next 8 pointers
1470                  * to mbufs.
1471                  */
1472                 if ((rx_id & 0x3) == 0) {
1473                         rte_prefetch0(&rx_ring[rx_id]);
1474                         rte_prefetch0(rxq->sw_ring[rx_id]);
1475                 }
1476                 rxm = rxe;
1477                 dma_addr =
1478                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1479                 rxdp->read.hdr_addr = 0;
1480                 rxdp->read.pkt_addr = dma_addr;
1481
1482                 rx_packet_len = (rte_le_to_cpu_16(rxd.wb.pkt_len) &
1483                                 IAVF_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
1484
1485                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1486                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
1487                 rxm->nb_segs = 1;
1488                 rxm->next = NULL;
1489                 rxm->pkt_len = rx_packet_len;
1490                 rxm->data_len = rx_packet_len;
1491                 rxm->port = rxq->port_id;
1492                 rxm->ol_flags = 0;
1493                 rxm->packet_type = ptype_tbl[IAVF_RX_FLEX_DESC_PTYPE_M &
1494                         rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
1495                 iavf_flex_rxd_to_vlan_tci(rxm, &rxd);
1496                 iavf_flex_rxd_to_ipsec_crypto_status(rxm, &rxd,
1497                                 &rxq->stats.ipsec_crypto);
1498                 rxd_to_pkt_fields_ops[rxq->rxdid](rxq, rxm, &rxd);
1499                 pkt_flags = iavf_flex_rxd_error_to_pkt_flags(rx_stat_err0);
1500
1501                 if (iavf_timestamp_dynflag > 0) {
1502                         if (rxq->hw_register_set)
1503                                 iavf_get_phc_time(ad);
1504
1505                         rxq->hw_register_set = 0;
1506                         ts_ns = iavf_tstamp_convert_32b_64b(ad->phc_time,
1507                                 rte_le_to_cpu_32(rxd.wb.flex_ts.ts_high));
1508
1509                         *RTE_MBUF_DYNFIELD(rxm,
1510                                 iavf_timestamp_dynfield_offset,
1511                                 rte_mbuf_timestamp_t *) = ts_ns;
1512                         rxm->ol_flags |= iavf_timestamp_dynflag;
1513                 }
1514
1515                 rxm->ol_flags |= pkt_flags;
1516
1517                 rx_pkts[nb_rx++] = rxm;
1518         }
1519         rxq->rx_tail = rx_id;
1520
1521         iavf_update_rx_tail(rxq, nb_hold, rx_id);
1522
1523         return nb_rx;
1524 }
1525
1526 /* implement recv_scattered_pkts for flexible Rx descriptor */
1527 uint16_t
1528 iavf_recv_scattered_pkts_flex_rxd(void *rx_queue, struct rte_mbuf **rx_pkts,
1529                                   uint16_t nb_pkts)
1530 {
1531         struct iavf_rx_queue *rxq = rx_queue;
1532         union iavf_rx_flex_desc rxd;
1533         struct rte_mbuf *rxe;
1534         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1535         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1536         struct rte_mbuf *nmb, *rxm;
1537         uint16_t rx_id = rxq->rx_tail;
1538         uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
1539         struct rte_eth_dev *dev;
1540         uint16_t rx_stat_err0;
1541         uint64_t dma_addr;
1542         uint64_t pkt_flags;
1543         struct iavf_adapter *ad = rxq->vsi->adapter;
1544         uint64_t ts_ns;
1545
1546         volatile union iavf_rx_desc *rx_ring = rxq->rx_ring;
1547         volatile union iavf_rx_flex_desc *rxdp;
1548         const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1549
1550         if (rxq->offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP)
1551                 rxq->hw_register_set = 1;
1552
1553         while (nb_rx < nb_pkts) {
1554                 rxdp = (volatile union iavf_rx_flex_desc *)&rx_ring[rx_id];
1555                 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1556
1557                 /* Check the DD bit */
1558                 if (!(rx_stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S)))
1559                         break;
1560                 IAVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
1561
1562                 nmb = rte_mbuf_raw_alloc(rxq->mp);
1563                 if (unlikely(!nmb)) {
1564                         PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1565                                    "queue_id=%u", rxq->port_id, rxq->queue_id);
1566                         dev = &rte_eth_devices[rxq->port_id];
1567                         dev->data->rx_mbuf_alloc_failed++;
1568                         break;
1569                 }
1570
1571                 rxd = *rxdp;
1572                 nb_hold++;
1573                 rxe = rxq->sw_ring[rx_id];
1574                 rxq->sw_ring[rx_id] = nmb;
1575                 rx_id++;
1576                 if (rx_id == rxq->nb_rx_desc)
1577                         rx_id = 0;
1578
1579                 /* Prefetch next mbuf */
1580                 rte_prefetch0(rxq->sw_ring[rx_id]);
1581
1582                 /* When next RX descriptor is on a cache line boundary,
1583                  * prefetch the next 4 RX descriptors and next 8 pointers
1584                  * to mbufs.
1585                  */
1586                 if ((rx_id & 0x3) == 0) {
1587                         rte_prefetch0(&rx_ring[rx_id]);
1588                         rte_prefetch0(rxq->sw_ring[rx_id]);
1589                 }
1590
1591                 rxm = rxe;
1592                 dma_addr =
1593                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1594
1595                 /* Set data buffer address and data length of the mbuf */
1596                 rxdp->read.hdr_addr = 0;
1597                 rxdp->read.pkt_addr = dma_addr;
1598                 rx_packet_len = rte_le_to_cpu_16(rxd.wb.pkt_len) &
1599                                 IAVF_RX_FLX_DESC_PKT_LEN_M;
1600                 rxm->data_len = rx_packet_len;
1601                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1602
1603                 /* If this is the first buffer of the received packet, set the
1604                  * pointer to the first mbuf of the packet and initialize its
1605                  * context. Otherwise, update the total length and the number
1606                  * of segments of the current scattered packet, and update the
1607                  * pointer to the last mbuf of the current packet.
1608                  */
1609                 if (!first_seg) {
1610                         first_seg = rxm;
1611                         first_seg->nb_segs = 1;
1612                         first_seg->pkt_len = rx_packet_len;
1613                 } else {
1614                         first_seg->pkt_len =
1615                                 (uint16_t)(first_seg->pkt_len +
1616                                                 rx_packet_len);
1617                         first_seg->nb_segs++;
1618                         last_seg->next = rxm;
1619                 }
1620
1621                 /* If this is not the last buffer of the received packet,
1622                  * update the pointer to the last mbuf of the current scattered
1623                  * packet and continue to parse the RX ring.
1624                  */
1625                 if (!(rx_stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_EOF_S))) {
1626                         last_seg = rxm;
1627                         continue;
1628                 }
1629
1630                 /* This is the last buffer of the received packet. If the CRC
1631                  * is not stripped by the hardware:
1632                  *  - Subtract the CRC length from the total packet length.
1633                  *  - If the last buffer only contains the whole CRC or a part
1634                  *  of it, free the mbuf associated to the last buffer. If part
1635                  *  of the CRC is also contained in the previous mbuf, subtract
1636                  *  the length of that CRC part from the data length of the
1637                  *  previous mbuf.
1638                  */
1639                 rxm->next = NULL;
1640                 if (unlikely(rxq->crc_len > 0)) {
1641                         first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
1642                         if (rx_packet_len <= RTE_ETHER_CRC_LEN) {
1643                                 rte_pktmbuf_free_seg(rxm);
1644                                 first_seg->nb_segs--;
1645                                 last_seg->data_len =
1646                                         (uint16_t)(last_seg->data_len -
1647                                         (RTE_ETHER_CRC_LEN - rx_packet_len));
1648                                 last_seg->next = NULL;
1649                         } else {
1650                                 rxm->data_len = (uint16_t)(rx_packet_len -
1651                                                         RTE_ETHER_CRC_LEN);
1652                         }
1653                 }
1654
1655                 first_seg->port = rxq->port_id;
1656                 first_seg->ol_flags = 0;
1657                 first_seg->packet_type = ptype_tbl[IAVF_RX_FLEX_DESC_PTYPE_M &
1658                         rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
1659                 iavf_flex_rxd_to_vlan_tci(first_seg, &rxd);
1660                 iavf_flex_rxd_to_ipsec_crypto_status(first_seg, &rxd,
1661                                 &rxq->stats.ipsec_crypto);
1662                 rxd_to_pkt_fields_ops[rxq->rxdid](rxq, first_seg, &rxd);
1663                 pkt_flags = iavf_flex_rxd_error_to_pkt_flags(rx_stat_err0);
1664
1665                 if (iavf_timestamp_dynflag > 0) {
1666                         if (rxq->hw_register_set)
1667                                 iavf_get_phc_time(ad);
1668
1669                         rxq->hw_register_set = 0;
1670                         ts_ns = iavf_tstamp_convert_32b_64b(ad->phc_time,
1671                                 rte_le_to_cpu_32(rxd.wb.flex_ts.ts_high));
1672
1673                         *RTE_MBUF_DYNFIELD(first_seg,
1674                                 iavf_timestamp_dynfield_offset,
1675                                 rte_mbuf_timestamp_t *) = ts_ns;
1676                         first_seg->ol_flags |= iavf_timestamp_dynflag;
1677                 }
1678
1679                 first_seg->ol_flags |= pkt_flags;
1680
1681                 /* Prefetch data of first segment, if configured to do so. */
1682                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1683                                           first_seg->data_off));
1684                 rx_pkts[nb_rx++] = first_seg;
1685                 first_seg = NULL;
1686         }
1687
1688         /* Record index of the next RX descriptor to probe. */
1689         rxq->rx_tail = rx_id;
1690         rxq->pkt_first_seg = first_seg;
1691         rxq->pkt_last_seg = last_seg;
1692
1693         iavf_update_rx_tail(rxq, nb_hold, rx_id);
1694
1695         return nb_rx;
1696 }
1697
1698 /* implement recv_scattered_pkts  */
1699 uint16_t
1700 iavf_recv_scattered_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1701                         uint16_t nb_pkts)
1702 {
1703         struct iavf_rx_queue *rxq = rx_queue;
1704         union iavf_rx_desc rxd;
1705         struct rte_mbuf *rxe;
1706         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1707         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1708         struct rte_mbuf *nmb, *rxm;
1709         uint16_t rx_id = rxq->rx_tail;
1710         uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
1711         struct rte_eth_dev *dev;
1712         uint32_t rx_status;
1713         uint64_t qword1;
1714         uint64_t dma_addr;
1715         uint64_t pkt_flags;
1716
1717         volatile union iavf_rx_desc *rx_ring = rxq->rx_ring;
1718         volatile union iavf_rx_desc *rxdp;
1719         const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1720
1721         while (nb_rx < nb_pkts) {
1722                 rxdp = &rx_ring[rx_id];
1723                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1724                 rx_status = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
1725                             IAVF_RXD_QW1_STATUS_SHIFT;
1726
1727                 /* Check the DD bit */
1728                 if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)))
1729                         break;
1730                 IAVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
1731
1732                 nmb = rte_mbuf_raw_alloc(rxq->mp);
1733                 if (unlikely(!nmb)) {
1734                         PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1735                                    "queue_id=%u", rxq->port_id, rxq->queue_id);
1736                         dev = &rte_eth_devices[rxq->port_id];
1737                         dev->data->rx_mbuf_alloc_failed++;
1738                         break;
1739                 }
1740
1741                 rxd = *rxdp;
1742                 nb_hold++;
1743                 rxe = rxq->sw_ring[rx_id];
1744                 rxq->sw_ring[rx_id] = nmb;
1745                 rx_id++;
1746                 if (rx_id == rxq->nb_rx_desc)
1747                         rx_id = 0;
1748
1749                 /* Prefetch next mbuf */
1750                 rte_prefetch0(rxq->sw_ring[rx_id]);
1751
1752                 /* When next RX descriptor is on a cache line boundary,
1753                  * prefetch the next 4 RX descriptors and next 8 pointers
1754                  * to mbufs.
1755                  */
1756                 if ((rx_id & 0x3) == 0) {
1757                         rte_prefetch0(&rx_ring[rx_id]);
1758                         rte_prefetch0(rxq->sw_ring[rx_id]);
1759                 }
1760
1761                 rxm = rxe;
1762                 dma_addr =
1763                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1764
1765                 /* Set data buffer address and data length of the mbuf */
1766                 rxdp->read.hdr_addr = 0;
1767                 rxdp->read.pkt_addr = dma_addr;
1768                 rx_packet_len = (qword1 & IAVF_RXD_QW1_LENGTH_PBUF_MASK) >>
1769                                  IAVF_RXD_QW1_LENGTH_PBUF_SHIFT;
1770                 rxm->data_len = rx_packet_len;
1771                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1772
1773                 /* If this is the first buffer of the received packet, set the
1774                  * pointer to the first mbuf of the packet and initialize its
1775                  * context. Otherwise, update the total length and the number
1776                  * of segments of the current scattered packet, and update the
1777                  * pointer to the last mbuf of the current packet.
1778                  */
1779                 if (!first_seg) {
1780                         first_seg = rxm;
1781                         first_seg->nb_segs = 1;
1782                         first_seg->pkt_len = rx_packet_len;
1783                 } else {
1784                         first_seg->pkt_len =
1785                                 (uint16_t)(first_seg->pkt_len +
1786                                                 rx_packet_len);
1787                         first_seg->nb_segs++;
1788                         last_seg->next = rxm;
1789                 }
1790
1791                 /* If this is not the last buffer of the received packet,
1792                  * update the pointer to the last mbuf of the current scattered
1793                  * packet and continue to parse the RX ring.
1794                  */
1795                 if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_EOF_SHIFT))) {
1796                         last_seg = rxm;
1797                         continue;
1798                 }
1799
1800                 /* This is the last buffer of the received packet. If the CRC
1801                  * is not stripped by the hardware:
1802                  *  - Subtract the CRC length from the total packet length.
1803                  *  - If the last buffer only contains the whole CRC or a part
1804                  *  of it, free the mbuf associated to the last buffer. If part
1805                  *  of the CRC is also contained in the previous mbuf, subtract
1806                  *  the length of that CRC part from the data length of the
1807                  *  previous mbuf.
1808                  */
1809                 rxm->next = NULL;
1810                 if (unlikely(rxq->crc_len > 0)) {
1811                         first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
1812                         if (rx_packet_len <= RTE_ETHER_CRC_LEN) {
1813                                 rte_pktmbuf_free_seg(rxm);
1814                                 first_seg->nb_segs--;
1815                                 last_seg->data_len =
1816                                         (uint16_t)(last_seg->data_len -
1817                                         (RTE_ETHER_CRC_LEN - rx_packet_len));
1818                                 last_seg->next = NULL;
1819                         } else
1820                                 rxm->data_len = (uint16_t)(rx_packet_len -
1821                                                         RTE_ETHER_CRC_LEN);
1822                 }
1823
1824                 first_seg->port = rxq->port_id;
1825                 first_seg->ol_flags = 0;
1826                 iavf_rxd_to_vlan_tci(first_seg, &rxd);
1827                 pkt_flags = iavf_rxd_to_pkt_flags(qword1);
1828                 first_seg->packet_type =
1829                         ptype_tbl[(uint8_t)((qword1 &
1830                         IAVF_RXD_QW1_PTYPE_MASK) >> IAVF_RXD_QW1_PTYPE_SHIFT)];
1831
1832                 if (pkt_flags & RTE_MBUF_F_RX_RSS_HASH)
1833                         first_seg->hash.rss =
1834                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1835
1836                 if (pkt_flags & RTE_MBUF_F_RX_FDIR)
1837                         pkt_flags |= iavf_rxd_build_fdir(&rxd, first_seg);
1838
1839                 first_seg->ol_flags |= pkt_flags;
1840
1841                 /* Prefetch data of first segment, if configured to do so. */
1842                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1843                                           first_seg->data_off));
1844                 rx_pkts[nb_rx++] = first_seg;
1845                 first_seg = NULL;
1846         }
1847
1848         /* Record index of the next RX descriptor to probe. */
1849         rxq->rx_tail = rx_id;
1850         rxq->pkt_first_seg = first_seg;
1851         rxq->pkt_last_seg = last_seg;
1852
1853         iavf_update_rx_tail(rxq, nb_hold, rx_id);
1854
1855         return nb_rx;
1856 }
1857
1858 #define IAVF_LOOK_AHEAD 8
1859 static inline int
1860 iavf_rx_scan_hw_ring_flex_rxd(struct iavf_rx_queue *rxq,
1861                             struct rte_mbuf **rx_pkts,
1862                             uint16_t nb_pkts)
1863 {
1864         volatile union iavf_rx_flex_desc *rxdp;
1865         struct rte_mbuf **rxep;
1866         struct rte_mbuf *mb;
1867         uint16_t stat_err0;
1868         uint16_t pkt_len;
1869         int32_t s[IAVF_LOOK_AHEAD], var, nb_dd;
1870         int32_t i, j, nb_rx = 0;
1871         int32_t nb_staged = 0;
1872         uint64_t pkt_flags;
1873         const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1874         struct iavf_adapter *ad = rxq->vsi->adapter;
1875         uint64_t ts_ns;
1876
1877         rxdp = (volatile union iavf_rx_flex_desc *)&rxq->rx_ring[rxq->rx_tail];
1878         rxep = &rxq->sw_ring[rxq->rx_tail];
1879
1880         stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1881
1882         /* Make sure there is at least 1 packet to receive */
1883         if (!(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S)))
1884                 return 0;
1885
1886         if (rxq->offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP)
1887                 rxq->hw_register_set = 1;
1888
1889         /* Scan LOOK_AHEAD descriptors at a time to determine which
1890          * descriptors reference packets that are ready to be received.
1891          */
1892         for (i = 0; i < IAVF_RX_MAX_BURST; i += IAVF_LOOK_AHEAD,
1893              rxdp += IAVF_LOOK_AHEAD, rxep += IAVF_LOOK_AHEAD) {
1894                 /* Read desc statuses backwards to avoid race condition */
1895                 for (j = IAVF_LOOK_AHEAD - 1; j >= 0; j--)
1896                         s[j] = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1897
1898                 /* This barrier is to order loads of different words in the descriptor */
1899                 rte_atomic_thread_fence(__ATOMIC_ACQUIRE);
1900
1901                 /* Compute how many contiguous DD bits were set */
1902                 for (j = 0, nb_dd = 0; j < IAVF_LOOK_AHEAD; j++) {
1903                         var = s[j] & (1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S);
1904 #ifdef RTE_ARCH_ARM
1905                         /* For Arm platforms, count only contiguous descriptors
1906                          * whose DD bit is set to 1. On Arm platforms, reads of
1907                          * descriptors can be reordered. Since the CPU may
1908                          * be reading the descriptors as the NIC updates them
1909                          * in memory, it is possbile that the DD bit for a
1910                          * descriptor earlier in the queue is read as not set
1911                          * while the DD bit for a descriptor later in the queue
1912                          * is read as set.
1913                          */
1914                         if (var)
1915                                 nb_dd += 1;
1916                         else
1917                                 break;
1918 #else
1919                         nb_dd += var;
1920 #endif
1921                 }
1922
1923                 /* Translate descriptor info to mbuf parameters */
1924                 for (j = 0; j < nb_dd; j++) {
1925                         IAVF_DUMP_RX_DESC(rxq, &rxdp[j],
1926                                           rxq->rx_tail +
1927                                           i * IAVF_LOOK_AHEAD + j);
1928
1929                         mb = rxep[j];
1930                         pkt_len = (rte_le_to_cpu_16(rxdp[j].wb.pkt_len) &
1931                                 IAVF_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
1932                         mb->data_len = pkt_len;
1933                         mb->pkt_len = pkt_len;
1934                         mb->ol_flags = 0;
1935
1936                         mb->packet_type = ptype_tbl[IAVF_RX_FLEX_DESC_PTYPE_M &
1937                                 rte_le_to_cpu_16(rxdp[j].wb.ptype_flex_flags0)];
1938                         iavf_flex_rxd_to_vlan_tci(mb, &rxdp[j]);
1939                         iavf_flex_rxd_to_ipsec_crypto_status(mb, &rxdp[j],
1940                                 &rxq->stats.ipsec_crypto);
1941                         rxd_to_pkt_fields_ops[rxq->rxdid](rxq, mb, &rxdp[j]);
1942                         stat_err0 = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1943                         pkt_flags = iavf_flex_rxd_error_to_pkt_flags(stat_err0);
1944
1945                         if (iavf_timestamp_dynflag > 0) {
1946                                 if (rxq->hw_register_set)
1947                                         iavf_get_phc_time(ad);
1948
1949                                 rxq->hw_register_set = 0;
1950                                 ts_ns = iavf_tstamp_convert_32b_64b(ad->phc_time,
1951                                         rte_le_to_cpu_32(rxdp[j].wb.flex_ts.ts_high));
1952
1953                                 *RTE_MBUF_DYNFIELD(mb,
1954                                         iavf_timestamp_dynfield_offset,
1955                                         rte_mbuf_timestamp_t *) = ts_ns;
1956                                 mb->ol_flags |= iavf_timestamp_dynflag;
1957                         }
1958
1959                         mb->ol_flags |= pkt_flags;
1960
1961                         /* Put up to nb_pkts directly into buffers */
1962                         if ((i + j) < nb_pkts) {
1963                                 rx_pkts[i + j] = rxep[j];
1964                                 nb_rx++;
1965                         } else {
1966                                 /* Stage excess pkts received */
1967                                 rxq->rx_stage[nb_staged] = rxep[j];
1968                                 nb_staged++;
1969                         }
1970                 }
1971
1972                 if (nb_dd != IAVF_LOOK_AHEAD)
1973                         break;
1974         }
1975
1976         /* Update rxq->rx_nb_avail to reflect number of staged pkts */
1977         rxq->rx_nb_avail = nb_staged;
1978
1979         /* Clear software ring entries */
1980         for (i = 0; i < (nb_rx + nb_staged); i++)
1981                 rxq->sw_ring[rxq->rx_tail + i] = NULL;
1982
1983         return nb_rx;
1984 }
1985
1986 static inline int
1987 iavf_rx_scan_hw_ring(struct iavf_rx_queue *rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1988 {
1989         volatile union iavf_rx_desc *rxdp;
1990         struct rte_mbuf **rxep;
1991         struct rte_mbuf *mb;
1992         uint16_t pkt_len;
1993         uint64_t qword1;
1994         uint32_t rx_status;
1995         int32_t s[IAVF_LOOK_AHEAD], var, nb_dd;
1996         int32_t i, j, nb_rx = 0;
1997         int32_t nb_staged = 0;
1998         uint64_t pkt_flags;
1999         const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
2000
2001         rxdp = &rxq->rx_ring[rxq->rx_tail];
2002         rxep = &rxq->sw_ring[rxq->rx_tail];
2003
2004         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
2005         rx_status = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
2006                     IAVF_RXD_QW1_STATUS_SHIFT;
2007
2008         /* Make sure there is at least 1 packet to receive */
2009         if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)))
2010                 return 0;
2011
2012         /* Scan LOOK_AHEAD descriptors at a time to determine which
2013          * descriptors reference packets that are ready to be received.
2014          */
2015         for (i = 0; i < IAVF_RX_MAX_BURST; i += IAVF_LOOK_AHEAD,
2016              rxdp += IAVF_LOOK_AHEAD, rxep += IAVF_LOOK_AHEAD) {
2017                 /* Read desc statuses backwards to avoid race condition */
2018                 for (j = IAVF_LOOK_AHEAD - 1; j >= 0; j--) {
2019                         qword1 = rte_le_to_cpu_64(
2020                                 rxdp[j].wb.qword1.status_error_len);
2021                         s[j] = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
2022                                IAVF_RXD_QW1_STATUS_SHIFT;
2023                 }
2024
2025                 /* This barrier is to order loads of different words in the descriptor */
2026                 rte_atomic_thread_fence(__ATOMIC_ACQUIRE);
2027
2028                 /* Compute how many contiguous DD bits were set */
2029                 for (j = 0, nb_dd = 0; j < IAVF_LOOK_AHEAD; j++) {
2030                         var = s[j] & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT);
2031 #ifdef RTE_ARCH_ARM
2032                         /* For Arm platforms, count only contiguous descriptors
2033                          * whose DD bit is set to 1. On Arm platforms, reads of
2034                          * descriptors can be reordered. Since the CPU may
2035                          * be reading the descriptors as the NIC updates them
2036                          * in memory, it is possbile that the DD bit for a
2037                          * descriptor earlier in the queue is read as not set
2038                          * while the DD bit for a descriptor later in the queue
2039                          * is read as set.
2040                          */
2041                         if (var)
2042                                 nb_dd += 1;
2043                         else
2044                                 break;
2045 #else
2046                         nb_dd += var;
2047 #endif
2048                 }
2049
2050                 /* Translate descriptor info to mbuf parameters */
2051                 for (j = 0; j < nb_dd; j++) {
2052                         IAVF_DUMP_RX_DESC(rxq, &rxdp[j],
2053                                          rxq->rx_tail + i * IAVF_LOOK_AHEAD + j);
2054
2055                         mb = rxep[j];
2056                         qword1 = rte_le_to_cpu_64
2057                                         (rxdp[j].wb.qword1.status_error_len);
2058                         pkt_len = ((qword1 & IAVF_RXD_QW1_LENGTH_PBUF_MASK) >>
2059                                   IAVF_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
2060                         mb->data_len = pkt_len;
2061                         mb->pkt_len = pkt_len;
2062                         mb->ol_flags = 0;
2063                         iavf_rxd_to_vlan_tci(mb, &rxdp[j]);
2064                         pkt_flags = iavf_rxd_to_pkt_flags(qword1);
2065                         mb->packet_type =
2066                                 ptype_tbl[(uint8_t)((qword1 &
2067                                 IAVF_RXD_QW1_PTYPE_MASK) >>
2068                                 IAVF_RXD_QW1_PTYPE_SHIFT)];
2069
2070                         if (pkt_flags & RTE_MBUF_F_RX_RSS_HASH)
2071                                 mb->hash.rss = rte_le_to_cpu_32(
2072                                         rxdp[j].wb.qword0.hi_dword.rss);
2073
2074                         if (pkt_flags & RTE_MBUF_F_RX_FDIR)
2075                                 pkt_flags |= iavf_rxd_build_fdir(&rxdp[j], mb);
2076
2077                         mb->ol_flags |= pkt_flags;
2078
2079                         /* Put up to nb_pkts directly into buffers */
2080                         if ((i + j) < nb_pkts) {
2081                                 rx_pkts[i + j] = rxep[j];
2082                                 nb_rx++;
2083                         } else { /* Stage excess pkts received */
2084                                 rxq->rx_stage[nb_staged] = rxep[j];
2085                                 nb_staged++;
2086                         }
2087                 }
2088
2089                 if (nb_dd != IAVF_LOOK_AHEAD)
2090                         break;
2091         }
2092
2093         /* Update rxq->rx_nb_avail to reflect number of staged pkts */
2094         rxq->rx_nb_avail = nb_staged;
2095
2096         /* Clear software ring entries */
2097         for (i = 0; i < (nb_rx + nb_staged); i++)
2098                 rxq->sw_ring[rxq->rx_tail + i] = NULL;
2099
2100         return nb_rx;
2101 }
2102
2103 static inline uint16_t
2104 iavf_rx_fill_from_stage(struct iavf_rx_queue *rxq,
2105                        struct rte_mbuf **rx_pkts,
2106                        uint16_t nb_pkts)
2107 {
2108         uint16_t i;
2109         struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
2110
2111         nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
2112
2113         for (i = 0; i < nb_pkts; i++)
2114                 rx_pkts[i] = stage[i];
2115
2116         rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
2117         rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
2118
2119         return nb_pkts;
2120 }
2121
2122 static inline int
2123 iavf_rx_alloc_bufs(struct iavf_rx_queue *rxq)
2124 {
2125         volatile union iavf_rx_desc *rxdp;
2126         struct rte_mbuf **rxep;
2127         struct rte_mbuf *mb;
2128         uint16_t alloc_idx, i;
2129         uint64_t dma_addr;
2130         int diag;
2131
2132         /* Allocate buffers in bulk */
2133         alloc_idx = (uint16_t)(rxq->rx_free_trigger -
2134                                 (rxq->rx_free_thresh - 1));
2135         rxep = &rxq->sw_ring[alloc_idx];
2136         diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
2137                                     rxq->rx_free_thresh);
2138         if (unlikely(diag != 0)) {
2139                 PMD_RX_LOG(ERR, "Failed to get mbufs in bulk");
2140                 return -ENOMEM;
2141         }
2142
2143         rxdp = &rxq->rx_ring[alloc_idx];
2144         for (i = 0; i < rxq->rx_free_thresh; i++) {
2145                 if (likely(i < (rxq->rx_free_thresh - 1)))
2146                         /* Prefetch next mbuf */
2147                         rte_prefetch0(rxep[i + 1]);
2148
2149                 mb = rxep[i];
2150                 rte_mbuf_refcnt_set(mb, 1);
2151                 mb->next = NULL;
2152                 mb->data_off = RTE_PKTMBUF_HEADROOM;
2153                 mb->nb_segs = 1;
2154                 mb->port = rxq->port_id;
2155                 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mb));
2156                 rxdp[i].read.hdr_addr = 0;
2157                 rxdp[i].read.pkt_addr = dma_addr;
2158         }
2159
2160         /* Update rx tail register */
2161         rte_wmb();
2162         IAVF_PCI_REG_WC_WRITE_RELAXED(rxq->qrx_tail, rxq->rx_free_trigger);
2163
2164         rxq->rx_free_trigger =
2165                 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
2166         if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
2167                 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2168
2169         return 0;
2170 }
2171
2172 static inline uint16_t
2173 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
2174 {
2175         struct iavf_rx_queue *rxq = (struct iavf_rx_queue *)rx_queue;
2176         uint16_t nb_rx = 0;
2177
2178         if (!nb_pkts)
2179                 return 0;
2180
2181         if (rxq->rx_nb_avail)
2182                 return iavf_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
2183
2184         if (rxq->rxdid >= IAVF_RXDID_FLEX_NIC && rxq->rxdid <= IAVF_RXDID_LAST)
2185                 nb_rx = (uint16_t)iavf_rx_scan_hw_ring_flex_rxd(rxq, rx_pkts, nb_pkts);
2186         else
2187                 nb_rx = (uint16_t)iavf_rx_scan_hw_ring(rxq, rx_pkts, nb_pkts);
2188
2189         rxq->rx_next_avail = 0;
2190         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx + rxq->rx_nb_avail);
2191
2192         if (rxq->rx_tail > rxq->rx_free_trigger) {
2193                 if (iavf_rx_alloc_bufs(rxq) != 0) {
2194                         uint16_t i, j, nb_staged;
2195
2196                         /* TODO: count rx_mbuf_alloc_failed here */
2197
2198                         nb_staged = rxq->rx_nb_avail;
2199                         rxq->rx_nb_avail = 0;
2200
2201                         rxq->rx_tail = (uint16_t)(rxq->rx_tail - (nb_rx + nb_staged));
2202                         for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++) {
2203                                 rxq->sw_ring[j] = rx_pkts[i];
2204                                 rx_pkts[i] = NULL;
2205                         }
2206                         for (i = 0, j = rxq->rx_tail + nb_rx; i < nb_staged; i++, j++) {
2207                                 rxq->sw_ring[j] = rxq->rx_stage[i];
2208                                 rx_pkts[i] = NULL;
2209                         }
2210
2211                         return 0;
2212                 }
2213         }
2214
2215         if (rxq->rx_tail >= rxq->nb_rx_desc)
2216                 rxq->rx_tail = 0;
2217
2218         PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u, nb_rx=%u",
2219                    rxq->port_id, rxq->queue_id,
2220                    rxq->rx_tail, nb_rx);
2221
2222         return nb_rx;
2223 }
2224
2225 static uint16_t
2226 iavf_recv_pkts_bulk_alloc(void *rx_queue,
2227                          struct rte_mbuf **rx_pkts,
2228                          uint16_t nb_pkts)
2229 {
2230         uint16_t nb_rx = 0, n, count;
2231
2232         if (unlikely(nb_pkts == 0))
2233                 return 0;
2234
2235         if (likely(nb_pkts <= IAVF_RX_MAX_BURST))
2236                 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
2237
2238         while (nb_pkts) {
2239                 n = RTE_MIN(nb_pkts, IAVF_RX_MAX_BURST);
2240                 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
2241                 nb_rx = (uint16_t)(nb_rx + count);
2242                 nb_pkts = (uint16_t)(nb_pkts - count);
2243                 if (count < n)
2244                         break;
2245         }
2246
2247         return nb_rx;
2248 }
2249
2250 static inline int
2251 iavf_xmit_cleanup(struct iavf_tx_queue *txq)
2252 {
2253         struct iavf_tx_entry *sw_ring = txq->sw_ring;
2254         uint16_t last_desc_cleaned = txq->last_desc_cleaned;
2255         uint16_t nb_tx_desc = txq->nb_tx_desc;
2256         uint16_t desc_to_clean_to;
2257         uint16_t nb_tx_to_clean;
2258
2259         volatile struct iavf_tx_desc *txd = txq->tx_ring;
2260
2261         desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->rs_thresh);
2262         if (desc_to_clean_to >= nb_tx_desc)
2263                 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
2264
2265         desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
2266         if ((txd[desc_to_clean_to].cmd_type_offset_bsz &
2267                         rte_cpu_to_le_64(IAVF_TXD_QW1_DTYPE_MASK)) !=
2268                         rte_cpu_to_le_64(IAVF_TX_DESC_DTYPE_DESC_DONE)) {
2269                 PMD_TX_LOG(DEBUG, "TX descriptor %4u is not done "
2270                            "(port=%d queue=%d)", desc_to_clean_to,
2271                            txq->port_id, txq->queue_id);
2272                 return -1;
2273         }
2274
2275         if (last_desc_cleaned > desc_to_clean_to)
2276                 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
2277                                                         desc_to_clean_to);
2278         else
2279                 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
2280                                         last_desc_cleaned);
2281
2282         txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
2283
2284         txq->last_desc_cleaned = desc_to_clean_to;
2285         txq->nb_free = (uint16_t)(txq->nb_free + nb_tx_to_clean);
2286
2287         return 0;
2288 }
2289
2290 /* Check if the context descriptor is needed for TX offloading */
2291 static inline uint16_t
2292 iavf_calc_context_desc(uint64_t flags, uint8_t vlan_flag)
2293 {
2294         if (flags & (RTE_MBUF_F_TX_TCP_SEG | RTE_MBUF_F_TX_UDP_SEG |
2295                         RTE_MBUF_F_TX_TUNNEL_MASK))
2296                 return 1;
2297         if (flags & RTE_MBUF_F_TX_VLAN &&
2298             vlan_flag & IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG2)
2299                 return 1;
2300         return 0;
2301 }
2302
2303 static inline void
2304 iavf_fill_ctx_desc_cmd_field(volatile uint64_t *field, struct rte_mbuf *m,
2305                 uint8_t vlan_flag)
2306 {
2307         uint64_t cmd = 0;
2308
2309         /* TSO enabled */
2310         if (m->ol_flags & (RTE_MBUF_F_TX_TCP_SEG | RTE_MBUF_F_TX_UDP_SEG))
2311                 cmd = IAVF_TX_CTX_DESC_TSO << IAVF_TXD_CTX_QW1_CMD_SHIFT;
2312
2313         if (m->ol_flags & RTE_MBUF_F_TX_VLAN &&
2314                         vlan_flag & IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG2) {
2315                 cmd |= IAVF_TX_CTX_DESC_IL2TAG2
2316                         << IAVF_TXD_CTX_QW1_CMD_SHIFT;
2317         }
2318
2319         *field |= cmd;
2320 }
2321
2322 static inline void
2323 iavf_fill_ctx_desc_ipsec_field(volatile uint64_t *field,
2324         struct iavf_ipsec_crypto_pkt_metadata *ipsec_md)
2325 {
2326         uint64_t ipsec_field =
2327                 (uint64_t)ipsec_md->ctx_desc_ipsec_params <<
2328                         IAVF_TXD_CTX_QW1_IPSEC_PARAMS_CIPHERBLK_SHIFT;
2329
2330         *field |= ipsec_field;
2331 }
2332
2333
2334 static inline void
2335 iavf_fill_ctx_desc_tunnelling_field(volatile uint64_t *qw0,
2336                 const struct rte_mbuf *m)
2337 {
2338         uint64_t eip_typ = IAVF_TX_CTX_DESC_EIPT_NONE;
2339         uint64_t eip_len = 0;
2340         uint64_t eip_noinc = 0;
2341         /* Default - IP_ID is increment in each segment of LSO */
2342
2343         switch (m->ol_flags & (RTE_MBUF_F_TX_OUTER_IPV4 |
2344                         RTE_MBUF_F_TX_OUTER_IPV6 |
2345                         RTE_MBUF_F_TX_OUTER_IP_CKSUM)) {
2346         case RTE_MBUF_F_TX_OUTER_IPV4:
2347                 eip_typ = IAVF_TX_CTX_DESC_EIPT_IPV4_NO_CHECKSUM_OFFLOAD;
2348                 eip_len = m->outer_l3_len >> 2;
2349         break;
2350         case RTE_MBUF_F_TX_OUTER_IPV4 | RTE_MBUF_F_TX_OUTER_IP_CKSUM:
2351                 eip_typ = IAVF_TX_CTX_DESC_EIPT_IPV4_CHECKSUM_OFFLOAD;
2352                 eip_len = m->outer_l3_len >> 2;
2353         break;
2354         case RTE_MBUF_F_TX_OUTER_IPV6:
2355                 eip_typ = IAVF_TX_CTX_DESC_EIPT_IPV6;
2356                 eip_len = m->outer_l3_len >> 2;
2357         break;
2358         }
2359
2360         *qw0 = eip_typ << IAVF_TXD_CTX_QW0_TUN_PARAMS_EIPT_SHIFT |
2361                 eip_len << IAVF_TXD_CTX_QW0_TUN_PARAMS_EIPLEN_SHIFT |
2362                 eip_noinc << IAVF_TXD_CTX_QW0_TUN_PARAMS_EIP_NOINC_SHIFT;
2363 }
2364
2365 static inline uint16_t
2366 iavf_fill_ctx_desc_segmentation_field(volatile uint64_t *field,
2367         struct rte_mbuf *m, struct iavf_ipsec_crypto_pkt_metadata *ipsec_md)
2368 {
2369         uint64_t segmentation_field = 0;
2370         uint64_t total_length = 0;
2371
2372         if (m->ol_flags & RTE_MBUF_F_TX_SEC_OFFLOAD) {
2373                 total_length = ipsec_md->l4_payload_len;
2374         } else {
2375                 total_length = m->pkt_len - (m->l2_len + m->l3_len + m->l4_len);
2376
2377                 if (m->ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK)
2378                         total_length -= m->outer_l3_len;
2379         }
2380
2381 #ifdef RTE_LIBRTE_IAVF_DEBUG_TX
2382         if (!m->l4_len || !m->tso_segsz)
2383                 PMD_TX_LOG(DEBUG, "L4 length %d, LSO Segment size %d",
2384                          m->l4_len, m->tso_segsz);
2385         if (m->tso_segsz < 88)
2386                 PMD_TX_LOG(DEBUG, "LSO Segment size %d is less than minimum %d",
2387                         m->tso_segsz, 88);
2388 #endif
2389         segmentation_field =
2390                 (((uint64_t)total_length << IAVF_TXD_CTX_QW1_TSO_LEN_SHIFT) &
2391                                 IAVF_TXD_CTX_QW1_TSO_LEN_MASK) |
2392                 (((uint64_t)m->tso_segsz << IAVF_TXD_CTX_QW1_MSS_SHIFT) &
2393                                 IAVF_TXD_CTX_QW1_MSS_MASK);
2394
2395         *field |= segmentation_field;
2396
2397         return total_length;
2398 }
2399
2400
2401 struct iavf_tx_context_desc_qws {
2402         __le64 qw0;
2403         __le64 qw1;
2404 };
2405
2406 static inline void
2407 iavf_fill_context_desc(volatile struct iavf_tx_context_desc *desc,
2408         struct rte_mbuf *m, struct iavf_ipsec_crypto_pkt_metadata *ipsec_md,
2409         uint16_t *tlen, uint8_t vlan_flag)
2410 {
2411         volatile struct iavf_tx_context_desc_qws *desc_qws =
2412                         (volatile struct iavf_tx_context_desc_qws *)desc;
2413         /* fill descriptor type field */
2414         desc_qws->qw1 = IAVF_TX_DESC_DTYPE_CONTEXT;
2415
2416         /* fill command field */
2417         iavf_fill_ctx_desc_cmd_field(&desc_qws->qw1, m, vlan_flag);
2418
2419         /* fill segmentation field */
2420         if (m->ol_flags & (RTE_MBUF_F_TX_TCP_SEG | RTE_MBUF_F_TX_UDP_SEG)) {
2421                 /* fill IPsec field */
2422                 if (m->ol_flags & RTE_MBUF_F_TX_SEC_OFFLOAD)
2423                         iavf_fill_ctx_desc_ipsec_field(&desc_qws->qw1,
2424                                 ipsec_md);
2425
2426                 *tlen = iavf_fill_ctx_desc_segmentation_field(&desc_qws->qw1,
2427                                 m, ipsec_md);
2428         }
2429
2430         /* fill tunnelling field */
2431         if (m->ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK)
2432                 iavf_fill_ctx_desc_tunnelling_field(&desc_qws->qw0, m);
2433         else
2434                 desc_qws->qw0 = 0;
2435
2436         desc_qws->qw0 = rte_cpu_to_le_64(desc_qws->qw0);
2437         desc_qws->qw1 = rte_cpu_to_le_64(desc_qws->qw1);
2438
2439         if (vlan_flag & IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG2)
2440                 desc->l2tag2 = m->vlan_tci;
2441 }
2442
2443
2444 static inline void
2445 iavf_fill_ipsec_desc(volatile struct iavf_tx_ipsec_desc *desc,
2446         const struct iavf_ipsec_crypto_pkt_metadata *md, uint16_t *ipsec_len)
2447 {
2448         desc->qw0 = rte_cpu_to_le_64(((uint64_t)md->l4_payload_len <<
2449                 IAVF_IPSEC_TX_DESC_QW0_L4PAYLEN_SHIFT) |
2450                 ((uint64_t)md->esn << IAVF_IPSEC_TX_DESC_QW0_IPSECESN_SHIFT) |
2451                 ((uint64_t)md->esp_trailer_len <<
2452                                 IAVF_IPSEC_TX_DESC_QW0_TRAILERLEN_SHIFT));
2453
2454         desc->qw1 = rte_cpu_to_le_64(((uint64_t)md->sa_idx <<
2455                 IAVF_IPSEC_TX_DESC_QW1_IPSECSA_SHIFT) |
2456                 ((uint64_t)md->next_proto <<
2457                                 IAVF_IPSEC_TX_DESC_QW1_IPSECNH_SHIFT) |
2458                 ((uint64_t)(md->len_iv & 0x3) <<
2459                                 IAVF_IPSEC_TX_DESC_QW1_IVLEN_SHIFT) |
2460                 ((uint64_t)(md->ol_flags & IAVF_IPSEC_CRYPTO_OL_FLAGS_NATT ?
2461                                 1ULL : 0ULL) <<
2462                                 IAVF_IPSEC_TX_DESC_QW1_UDP_SHIFT) |
2463                 (uint64_t)IAVF_TX_DESC_DTYPE_IPSEC);
2464
2465         /**
2466          * TODO: Pre-calculate this in the Session initialization
2467          *
2468          * Calculate IPsec length required in data descriptor func when TSO
2469          * offload is enabled
2470          */
2471         *ipsec_len = sizeof(struct rte_esp_hdr) + (md->len_iv >> 2) +
2472                         (md->ol_flags & IAVF_IPSEC_CRYPTO_OL_FLAGS_NATT ?
2473                         sizeof(struct rte_udp_hdr) : 0);
2474 }
2475
2476 static inline void
2477 iavf_build_data_desc_cmd_offset_fields(volatile uint64_t *qw1,
2478                 struct rte_mbuf *m, uint8_t vlan_flag)
2479 {
2480         uint64_t command = 0;
2481         uint64_t offset = 0;
2482         uint64_t l2tag1 = 0;
2483
2484         *qw1 = IAVF_TX_DESC_DTYPE_DATA;
2485
2486         command = (uint64_t)IAVF_TX_DESC_CMD_ICRC;
2487
2488         /* Descriptor based VLAN insertion */
2489         if ((vlan_flag & IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG1) &&
2490                         m->ol_flags & RTE_MBUF_F_TX_VLAN) {
2491                 command |= (uint64_t)IAVF_TX_DESC_CMD_IL2TAG1;
2492                 l2tag1 |= m->vlan_tci;
2493         }
2494
2495         /* Set MACLEN */
2496         offset |= (m->l2_len >> 1) << IAVF_TX_DESC_LENGTH_MACLEN_SHIFT;
2497
2498         /* Enable L3 checksum offloading inner */
2499         if (m->ol_flags & (RTE_MBUF_F_TX_IP_CKSUM | RTE_MBUF_F_TX_IPV4)) {
2500                 command |= IAVF_TX_DESC_CMD_IIPT_IPV4_CSUM;
2501                 offset |= (m->l3_len >> 2) << IAVF_TX_DESC_LENGTH_IPLEN_SHIFT;
2502         } else if (m->ol_flags & RTE_MBUF_F_TX_IPV4) {
2503                 command |= IAVF_TX_DESC_CMD_IIPT_IPV4;
2504                 offset |= (m->l3_len >> 2) << IAVF_TX_DESC_LENGTH_IPLEN_SHIFT;
2505         } else if (m->ol_flags & RTE_MBUF_F_TX_IPV6) {
2506                 command |= IAVF_TX_DESC_CMD_IIPT_IPV6;
2507                 offset |= (m->l3_len >> 2) << IAVF_TX_DESC_LENGTH_IPLEN_SHIFT;
2508         }
2509
2510         if (m->ol_flags & RTE_MBUF_F_TX_TCP_SEG) {
2511                 command |= IAVF_TX_DESC_CMD_L4T_EOFT_TCP;
2512                 offset |= (m->l4_len >> 2) <<
2513                               IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2514         }
2515
2516         /* Enable L4 checksum offloads */
2517         switch (m->ol_flags & RTE_MBUF_F_TX_L4_MASK) {
2518         case RTE_MBUF_F_TX_TCP_CKSUM:
2519                 command |= IAVF_TX_DESC_CMD_L4T_EOFT_TCP;
2520                 offset |= (sizeof(struct rte_tcp_hdr) >> 2) <<
2521                                 IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2522                 break;
2523         case RTE_MBUF_F_TX_SCTP_CKSUM:
2524                 command |= IAVF_TX_DESC_CMD_L4T_EOFT_SCTP;
2525                 offset |= (sizeof(struct rte_sctp_hdr) >> 2) <<
2526                                 IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2527                 break;
2528         case RTE_MBUF_F_TX_UDP_CKSUM:
2529                 command |= IAVF_TX_DESC_CMD_L4T_EOFT_UDP;
2530                 offset |= (sizeof(struct rte_udp_hdr) >> 2) <<
2531                                 IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2532                 break;
2533         }
2534
2535         *qw1 = rte_cpu_to_le_64((((uint64_t)command <<
2536                 IAVF_TXD_DATA_QW1_CMD_SHIFT) & IAVF_TXD_DATA_QW1_CMD_MASK) |
2537                 (((uint64_t)offset << IAVF_TXD_DATA_QW1_OFFSET_SHIFT) &
2538                 IAVF_TXD_DATA_QW1_OFFSET_MASK) |
2539                 ((uint64_t)l2tag1 << IAVF_TXD_DATA_QW1_L2TAG1_SHIFT));
2540 }
2541
2542 static inline void
2543 iavf_fill_data_desc(volatile struct iavf_tx_desc *desc,
2544         struct rte_mbuf *m, uint64_t desc_template,
2545         uint16_t tlen, uint16_t ipseclen)
2546 {
2547         uint32_t hdrlen = m->l2_len;
2548         uint32_t bufsz = 0;
2549
2550         /* fill data descriptor qw1 from template */
2551         desc->cmd_type_offset_bsz = desc_template;
2552
2553         /* set data buffer address */
2554         desc->buffer_addr = rte_mbuf_data_iova(m);
2555
2556         /* calculate data buffer size less set header lengths */
2557         if ((m->ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK) &&
2558                         (m->ol_flags & (RTE_MBUF_F_TX_TCP_SEG |
2559                                         RTE_MBUF_F_TX_UDP_SEG))) {
2560                 hdrlen += m->outer_l3_len;
2561                 if (m->ol_flags & RTE_MBUF_F_TX_L4_MASK)
2562                         hdrlen += m->l3_len + m->l4_len;
2563                 else
2564                         hdrlen += m->l3_len;
2565                 if (m->ol_flags & RTE_MBUF_F_TX_SEC_OFFLOAD)
2566                         hdrlen += ipseclen;
2567                 bufsz = hdrlen + tlen;
2568         } else if ((m->ol_flags & RTE_MBUF_F_TX_SEC_OFFLOAD) &&
2569                         (m->ol_flags & (RTE_MBUF_F_TX_TCP_SEG |
2570                                         RTE_MBUF_F_TX_UDP_SEG))) {
2571                 hdrlen += m->outer_l3_len + m->l3_len + ipseclen;
2572                 if (m->ol_flags & RTE_MBUF_F_TX_L4_MASK)
2573                         hdrlen += m->l4_len;
2574                 bufsz = hdrlen + tlen;
2575
2576         } else {
2577                 bufsz = m->data_len;
2578         }
2579
2580         /* set data buffer size */
2581         desc->cmd_type_offset_bsz |=
2582                 (((uint64_t)bufsz << IAVF_TXD_DATA_QW1_TX_BUF_SZ_SHIFT) &
2583                 IAVF_TXD_DATA_QW1_TX_BUF_SZ_MASK);
2584
2585         desc->buffer_addr = rte_cpu_to_le_64(desc->buffer_addr);
2586         desc->cmd_type_offset_bsz = rte_cpu_to_le_64(desc->cmd_type_offset_bsz);
2587 }
2588
2589
2590 static struct iavf_ipsec_crypto_pkt_metadata *
2591 iavf_ipsec_crypto_get_pkt_metadata(const struct iavf_tx_queue *txq,
2592                 struct rte_mbuf *m)
2593 {
2594         if (m->ol_flags & RTE_MBUF_F_TX_SEC_OFFLOAD)
2595                 return RTE_MBUF_DYNFIELD(m, txq->ipsec_crypto_pkt_md_offset,
2596                                 struct iavf_ipsec_crypto_pkt_metadata *);
2597
2598         return NULL;
2599 }
2600
2601 /* TX function */
2602 uint16_t
2603 iavf_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2604 {
2605         struct iavf_tx_queue *txq = tx_queue;
2606         volatile struct iavf_tx_desc *txr = txq->tx_ring;
2607         struct iavf_tx_entry *txe_ring = txq->sw_ring;
2608         struct iavf_tx_entry *txe, *txn;
2609         struct rte_mbuf *mb, *mb_seg;
2610         uint16_t desc_idx, desc_idx_last;
2611         uint16_t idx;
2612
2613
2614         /* Check if the descriptor ring needs to be cleaned. */
2615         if (txq->nb_free < txq->free_thresh)
2616                 iavf_xmit_cleanup(txq);
2617
2618         desc_idx = txq->tx_tail;
2619         txe = &txe_ring[desc_idx];
2620
2621 #ifdef RTE_LIBRTE_IAVF_DEBUG_TX_DESC_RING
2622                 iavf_dump_tx_entry_ring(txq);
2623                 iavf_dump_tx_desc_ring(txq);
2624 #endif
2625
2626
2627         for (idx = 0; idx < nb_pkts; idx++) {
2628                 volatile struct iavf_tx_desc *ddesc;
2629                 struct iavf_ipsec_crypto_pkt_metadata *ipsec_md;
2630
2631                 uint16_t nb_desc_ctx, nb_desc_ipsec;
2632                 uint16_t nb_desc_data, nb_desc_required;
2633                 uint16_t tlen = 0, ipseclen = 0;
2634                 uint64_t ddesc_template = 0;
2635                 uint64_t ddesc_cmd = 0;
2636
2637                 mb = tx_pkts[idx];
2638
2639                 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
2640
2641                 /**
2642                  * Get metadata for ipsec crypto from mbuf dynamic fields if
2643                  * security offload is specified.
2644                  */
2645                 ipsec_md = iavf_ipsec_crypto_get_pkt_metadata(txq, mb);
2646
2647                 nb_desc_data = mb->nb_segs;
2648                 nb_desc_ctx =
2649                         iavf_calc_context_desc(mb->ol_flags, txq->vlan_flag);
2650                 nb_desc_ipsec = !!(mb->ol_flags & RTE_MBUF_F_TX_SEC_OFFLOAD);
2651
2652                 /**
2653                  * The number of descriptors that must be allocated for
2654                  * a packet equals to the number of the segments of that
2655                  * packet plus the context and ipsec descriptors if needed.
2656                  */
2657                 nb_desc_required = nb_desc_data + nb_desc_ctx + nb_desc_ipsec;
2658
2659                 desc_idx_last = (uint16_t)(desc_idx + nb_desc_required - 1);
2660
2661                 /* wrap descriptor ring */
2662                 if (desc_idx_last >= txq->nb_tx_desc)
2663                         desc_idx_last =
2664                                 (uint16_t)(desc_idx_last - txq->nb_tx_desc);
2665
2666                 PMD_TX_LOG(DEBUG,
2667                         "port_id=%u queue_id=%u tx_first=%u tx_last=%u",
2668                         txq->port_id, txq->queue_id, desc_idx, desc_idx_last);
2669
2670                 if (nb_desc_required > txq->nb_free) {
2671                         if (iavf_xmit_cleanup(txq)) {
2672                                 if (idx == 0)
2673                                         return 0;
2674                                 goto end_of_tx;
2675                         }
2676                         if (unlikely(nb_desc_required > txq->rs_thresh)) {
2677                                 while (nb_desc_required > txq->nb_free) {
2678                                         if (iavf_xmit_cleanup(txq)) {
2679                                                 if (idx == 0)
2680                                                         return 0;
2681                                                 goto end_of_tx;
2682                                         }
2683                                 }
2684                         }
2685                 }
2686
2687                 iavf_build_data_desc_cmd_offset_fields(&ddesc_template, mb,
2688                         txq->vlan_flag);
2689
2690                         /* Setup TX context descriptor if required */
2691                 if (nb_desc_ctx) {
2692                         volatile struct iavf_tx_context_desc *ctx_desc =
2693                                 (volatile struct iavf_tx_context_desc *)
2694                                         &txr[desc_idx];
2695
2696                         /* clear QW0 or the previous writeback value
2697                          * may impact next write
2698                          */
2699                         *(volatile uint64_t *)ctx_desc = 0;
2700
2701                         txn = &txe_ring[txe->next_id];
2702                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
2703
2704                         if (txe->mbuf) {
2705                                 rte_pktmbuf_free_seg(txe->mbuf);
2706                                 txe->mbuf = NULL;
2707                         }
2708
2709                         iavf_fill_context_desc(ctx_desc, mb, ipsec_md, &tlen,
2710                                 txq->vlan_flag);
2711                         IAVF_DUMP_TX_DESC(txq, ctx_desc, desc_idx);
2712
2713                         txe->last_id = desc_idx_last;
2714                         desc_idx = txe->next_id;
2715                         txe = txn;
2716                         }
2717
2718                 if (nb_desc_ipsec) {
2719                         volatile struct iavf_tx_ipsec_desc *ipsec_desc =
2720                                 (volatile struct iavf_tx_ipsec_desc *)
2721                                         &txr[desc_idx];
2722
2723                         txn = &txe_ring[txe->next_id];
2724                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
2725
2726                         if (txe->mbuf) {
2727                                 rte_pktmbuf_free_seg(txe->mbuf);
2728                                 txe->mbuf = NULL;
2729                 }
2730
2731                         iavf_fill_ipsec_desc(ipsec_desc, ipsec_md, &ipseclen);
2732
2733                         IAVF_DUMP_TX_DESC(txq, ipsec_desc, desc_idx);
2734
2735                         txe->last_id = desc_idx_last;
2736                         desc_idx = txe->next_id;
2737                         txe = txn;
2738                 }
2739
2740                 mb_seg = mb;
2741
2742                 do {
2743                         ddesc = (volatile struct iavf_tx_desc *)
2744                                         &txr[desc_idx];
2745
2746                         txn = &txe_ring[txe->next_id];
2747                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
2748
2749                         if (txe->mbuf)
2750                                 rte_pktmbuf_free_seg(txe->mbuf);
2751
2752                         txe->mbuf = mb_seg;
2753                         iavf_fill_data_desc(ddesc, mb_seg,
2754                                         ddesc_template, tlen, ipseclen);
2755
2756                         IAVF_DUMP_TX_DESC(txq, ddesc, desc_idx);
2757
2758                         txe->last_id = desc_idx_last;
2759                         desc_idx = txe->next_id;
2760                         txe = txn;
2761                         mb_seg = mb_seg->next;
2762                 } while (mb_seg);
2763
2764                 /* The last packet data descriptor needs End Of Packet (EOP) */
2765                 ddesc_cmd = IAVF_TX_DESC_CMD_EOP;
2766
2767                 txq->nb_used = (uint16_t)(txq->nb_used + nb_desc_required);
2768                 txq->nb_free = (uint16_t)(txq->nb_free - nb_desc_required);
2769
2770                 if (txq->nb_used >= txq->rs_thresh) {
2771                         PMD_TX_LOG(DEBUG, "Setting RS bit on TXD id="
2772                                    "%4u (port=%d queue=%d)",
2773                                    desc_idx_last, txq->port_id, txq->queue_id);
2774
2775                         ddesc_cmd |= IAVF_TX_DESC_CMD_RS;
2776
2777                         /* Update txq RS bit counters */
2778                         txq->nb_used = 0;
2779                 }
2780
2781                 ddesc->cmd_type_offset_bsz |= rte_cpu_to_le_64(ddesc_cmd <<
2782                                 IAVF_TXD_DATA_QW1_CMD_SHIFT);
2783
2784                 IAVF_DUMP_TX_DESC(txq, ddesc, desc_idx - 1);
2785         }
2786
2787 end_of_tx:
2788         rte_wmb();
2789
2790         PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
2791                    txq->port_id, txq->queue_id, desc_idx, idx);
2792
2793         IAVF_PCI_REG_WRITE_RELAXED(txq->qtx_tail, desc_idx);
2794         txq->tx_tail = desc_idx;
2795
2796         return idx;
2797 }
2798
2799 /* Check if the packet with vlan user priority is transmitted in the
2800  * correct queue.
2801  */
2802 static int
2803 iavf_check_vlan_up2tc(struct iavf_tx_queue *txq, struct rte_mbuf *m)
2804 {
2805         struct rte_eth_dev *dev = &rte_eth_devices[txq->port_id];
2806         struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2807         uint16_t up;
2808
2809         up = m->vlan_tci >> IAVF_VLAN_TAG_PCP_OFFSET;
2810
2811         if (!(vf->qos_cap->cap[txq->tc].tc_prio & BIT(up))) {
2812                 PMD_TX_LOG(ERR, "packet with vlan pcp %u cannot transmit in queue %u\n",
2813                         up, txq->queue_id);
2814                 return -1;
2815         } else {
2816                 return 0;
2817         }
2818 }
2819
2820 /* TX prep functions */
2821 uint16_t
2822 iavf_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
2823               uint16_t nb_pkts)
2824 {
2825         int i, ret;
2826         uint64_t ol_flags;
2827         struct rte_mbuf *m;
2828         struct iavf_tx_queue *txq = tx_queue;
2829         struct rte_eth_dev *dev = &rte_eth_devices[txq->port_id];
2830         struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2831
2832         for (i = 0; i < nb_pkts; i++) {
2833                 m = tx_pkts[i];
2834                 ol_flags = m->ol_flags;
2835
2836                 /* Check condition for nb_segs > IAVF_TX_MAX_MTU_SEG. */
2837                 if (!(ol_flags & RTE_MBUF_F_TX_TCP_SEG)) {
2838                         if (m->nb_segs > IAVF_TX_MAX_MTU_SEG) {
2839                                 rte_errno = EINVAL;
2840                                 return i;
2841                         }
2842                 } else if ((m->tso_segsz < IAVF_MIN_TSO_MSS) ||
2843                            (m->tso_segsz > IAVF_MAX_TSO_MSS)) {
2844                         /* MSS outside the range are considered malicious */
2845                         rte_errno = EINVAL;
2846                         return i;
2847                 }
2848
2849                 if (ol_flags & IAVF_TX_OFFLOAD_NOTSUP_MASK) {
2850                         rte_errno = ENOTSUP;
2851                         return i;
2852                 }
2853
2854 #ifdef RTE_ETHDEV_DEBUG_TX
2855                 ret = rte_validate_tx_offload(m);
2856                 if (ret != 0) {
2857                         rte_errno = -ret;
2858                         return i;
2859                 }
2860 #endif
2861                 ret = rte_net_intel_cksum_prepare(m);
2862                 if (ret != 0) {
2863                         rte_errno = -ret;
2864                         return i;
2865                 }
2866
2867                 if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_QOS &&
2868                     ol_flags & (RTE_MBUF_F_RX_VLAN_STRIPPED | RTE_MBUF_F_RX_VLAN)) {
2869                         ret = iavf_check_vlan_up2tc(txq, m);
2870                         if (ret != 0) {
2871                                 rte_errno = -ret;
2872                                 return i;
2873                         }
2874                 }
2875         }
2876
2877         return i;
2878 }
2879
2880 /* choose rx function*/
2881 void
2882 iavf_set_rx_function(struct rte_eth_dev *dev)
2883 {
2884         struct iavf_adapter *adapter =
2885                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2886         struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2887
2888 #ifdef RTE_ARCH_X86
2889         struct iavf_rx_queue *rxq;
2890         int i;
2891         int check_ret;
2892         bool use_avx2 = false;
2893         bool use_avx512 = false;
2894         bool use_flex = false;
2895
2896         check_ret = iavf_rx_vec_dev_check(dev);
2897         if (check_ret >= 0 &&
2898             rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
2899                 if ((rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
2900                      rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) &&
2901                     rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256)
2902                         use_avx2 = true;
2903
2904 #ifdef CC_AVX512_SUPPORT
2905                 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 &&
2906                     rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1 &&
2907                     rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512)
2908                         use_avx512 = true;
2909 #endif
2910
2911                 if (vf->vf_res->vf_cap_flags &
2912                         VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC)
2913                         use_flex = true;
2914
2915                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2916                         rxq = dev->data->rx_queues[i];
2917                         (void)iavf_rxq_vec_setup(rxq);
2918                 }
2919
2920                 if (dev->data->scattered_rx) {
2921                         if (!use_avx512) {
2922                                 PMD_DRV_LOG(DEBUG,
2923                                             "Using %sVector Scattered Rx (port %d).",
2924                                             use_avx2 ? "avx2 " : "",
2925                                             dev->data->port_id);
2926                         } else {
2927                                 if (check_ret == IAVF_VECTOR_PATH)
2928                                         PMD_DRV_LOG(DEBUG,
2929                                                     "Using AVX512 Vector Scattered Rx (port %d).",
2930                                                     dev->data->port_id);
2931                                 else
2932                                         PMD_DRV_LOG(DEBUG,
2933                                                     "Using AVX512 OFFLOAD Vector Scattered Rx (port %d).",
2934                                                     dev->data->port_id);
2935                         }
2936                         if (use_flex) {
2937                                 dev->rx_pkt_burst = use_avx2 ?
2938                                         iavf_recv_scattered_pkts_vec_avx2_flex_rxd :
2939                                         iavf_recv_scattered_pkts_vec_flex_rxd;
2940 #ifdef CC_AVX512_SUPPORT
2941                                 if (use_avx512) {
2942                                         if (check_ret == IAVF_VECTOR_PATH)
2943                                                 dev->rx_pkt_burst =
2944                                                         iavf_recv_scattered_pkts_vec_avx512_flex_rxd;
2945                                         else
2946                                                 dev->rx_pkt_burst =
2947                                                         iavf_recv_scattered_pkts_vec_avx512_flex_rxd_offload;
2948                                 }
2949 #endif
2950                         } else {
2951                                 dev->rx_pkt_burst = use_avx2 ?
2952                                         iavf_recv_scattered_pkts_vec_avx2 :
2953                                         iavf_recv_scattered_pkts_vec;
2954 #ifdef CC_AVX512_SUPPORT
2955                                 if (use_avx512) {
2956                                         if (check_ret == IAVF_VECTOR_PATH)
2957                                                 dev->rx_pkt_burst =
2958                                                         iavf_recv_scattered_pkts_vec_avx512;
2959                                         else
2960                                                 dev->rx_pkt_burst =
2961                                                         iavf_recv_scattered_pkts_vec_avx512_offload;
2962                                 }
2963 #endif
2964                         }
2965                 } else {
2966                         if (!use_avx512) {
2967                                 PMD_DRV_LOG(DEBUG, "Using %sVector Rx (port %d).",
2968                                             use_avx2 ? "avx2 " : "",
2969                                             dev->data->port_id);
2970                         } else {
2971                                 if (check_ret == IAVF_VECTOR_PATH)
2972                                         PMD_DRV_LOG(DEBUG,
2973                                                     "Using AVX512 Vector Rx (port %d).",
2974                                                     dev->data->port_id);
2975                                 else
2976                                         PMD_DRV_LOG(DEBUG,
2977                                                     "Using AVX512 OFFLOAD Vector Rx (port %d).",
2978                                                     dev->data->port_id);
2979                         }
2980                         if (use_flex) {
2981                                 dev->rx_pkt_burst = use_avx2 ?
2982                                         iavf_recv_pkts_vec_avx2_flex_rxd :
2983                                         iavf_recv_pkts_vec_flex_rxd;
2984 #ifdef CC_AVX512_SUPPORT
2985                                 if (use_avx512) {
2986                                         if (check_ret == IAVF_VECTOR_PATH)
2987                                                 dev->rx_pkt_burst =
2988                                                         iavf_recv_pkts_vec_avx512_flex_rxd;
2989                                         else
2990                                                 dev->rx_pkt_burst =
2991                                                         iavf_recv_pkts_vec_avx512_flex_rxd_offload;
2992                                 }
2993 #endif
2994                         } else {
2995                                 dev->rx_pkt_burst = use_avx2 ?
2996                                         iavf_recv_pkts_vec_avx2 :
2997                                         iavf_recv_pkts_vec;
2998 #ifdef CC_AVX512_SUPPORT
2999                                 if (use_avx512) {
3000                                         if (check_ret == IAVF_VECTOR_PATH)
3001                                                 dev->rx_pkt_burst =
3002                                                         iavf_recv_pkts_vec_avx512;
3003                                         else
3004                                                 dev->rx_pkt_burst =
3005                                                         iavf_recv_pkts_vec_avx512_offload;
3006                                 }
3007 #endif
3008                         }
3009                 }
3010
3011                 return;
3012         }
3013
3014 #endif
3015         if (dev->data->scattered_rx) {
3016                 PMD_DRV_LOG(DEBUG, "Using a Scattered Rx callback (port=%d).",
3017                             dev->data->port_id);
3018                 if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC)
3019                         dev->rx_pkt_burst = iavf_recv_scattered_pkts_flex_rxd;
3020                 else
3021                         dev->rx_pkt_burst = iavf_recv_scattered_pkts;
3022         } else if (adapter->rx_bulk_alloc_allowed) {
3023                 PMD_DRV_LOG(DEBUG, "Using bulk Rx callback (port=%d).",
3024                             dev->data->port_id);
3025                 dev->rx_pkt_burst = iavf_recv_pkts_bulk_alloc;
3026         } else {
3027                 PMD_DRV_LOG(DEBUG, "Using Basic Rx callback (port=%d).",
3028                             dev->data->port_id);
3029                 if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC)
3030                         dev->rx_pkt_burst = iavf_recv_pkts_flex_rxd;
3031                 else
3032                         dev->rx_pkt_burst = iavf_recv_pkts;
3033         }
3034 }
3035
3036 /* choose tx function*/
3037 void
3038 iavf_set_tx_function(struct rte_eth_dev *dev)
3039 {
3040 #ifdef RTE_ARCH_X86
3041         struct iavf_tx_queue *txq;
3042         int i;
3043         int check_ret;
3044         bool use_sse = false;
3045         bool use_avx2 = false;
3046         bool use_avx512 = false;
3047
3048         check_ret = iavf_tx_vec_dev_check(dev);
3049
3050         if (check_ret >= 0 &&
3051             rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
3052                 /* SSE and AVX2 not support offload path yet. */
3053                 if (check_ret == IAVF_VECTOR_PATH) {
3054                         use_sse = true;
3055                         if ((rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
3056                              rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) &&
3057                             rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256)
3058                                 use_avx2 = true;
3059                 }
3060 #ifdef CC_AVX512_SUPPORT
3061                 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 &&
3062                     rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1 &&
3063                     rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512)
3064                         use_avx512 = true;
3065 #endif
3066
3067                 if (!use_sse && !use_avx2 && !use_avx512)
3068                         goto normal;
3069
3070                 if (!use_avx512) {
3071                         PMD_DRV_LOG(DEBUG, "Using %sVector Tx (port %d).",
3072                                     use_avx2 ? "avx2 " : "",
3073                                     dev->data->port_id);
3074                         dev->tx_pkt_burst = use_avx2 ?
3075                                             iavf_xmit_pkts_vec_avx2 :
3076                                             iavf_xmit_pkts_vec;
3077                 }
3078                 dev->tx_pkt_prepare = NULL;
3079 #ifdef CC_AVX512_SUPPORT
3080                 if (use_avx512) {
3081                         if (check_ret == IAVF_VECTOR_PATH) {
3082                                 dev->tx_pkt_burst = iavf_xmit_pkts_vec_avx512;
3083                                 PMD_DRV_LOG(DEBUG, "Using AVX512 Vector Tx (port %d).",
3084                                             dev->data->port_id);
3085                         } else {
3086                                 dev->tx_pkt_burst = iavf_xmit_pkts_vec_avx512_offload;
3087                                 dev->tx_pkt_prepare = iavf_prep_pkts;
3088                                 PMD_DRV_LOG(DEBUG, "Using AVX512 OFFLOAD Vector Tx (port %d).",
3089                                             dev->data->port_id);
3090                         }
3091                 }
3092 #endif
3093
3094                 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3095                         txq = dev->data->tx_queues[i];
3096                         if (!txq)
3097                                 continue;
3098 #ifdef CC_AVX512_SUPPORT
3099                         if (use_avx512)
3100                                 iavf_txq_vec_setup_avx512(txq);
3101                         else
3102                                 iavf_txq_vec_setup(txq);
3103 #else
3104                         iavf_txq_vec_setup(txq);
3105 #endif
3106                 }
3107
3108                 return;
3109         }
3110
3111 normal:
3112 #endif
3113         PMD_DRV_LOG(DEBUG, "Using Basic Tx callback (port=%d).",
3114                     dev->data->port_id);
3115         dev->tx_pkt_burst = iavf_xmit_pkts;
3116         dev->tx_pkt_prepare = iavf_prep_pkts;
3117 }
3118
3119 static int
3120 iavf_tx_done_cleanup_full(struct iavf_tx_queue *txq,
3121                         uint32_t free_cnt)
3122 {
3123         struct iavf_tx_entry *swr_ring = txq->sw_ring;
3124         uint16_t i, tx_last, tx_id;
3125         uint16_t nb_tx_free_last;
3126         uint16_t nb_tx_to_clean;
3127         uint32_t pkt_cnt;
3128
3129         /* Start free mbuf from the next of tx_tail */
3130         tx_last = txq->tx_tail;
3131         tx_id  = swr_ring[tx_last].next_id;
3132
3133         if (txq->nb_free == 0 && iavf_xmit_cleanup(txq))
3134                 return 0;
3135
3136         nb_tx_to_clean = txq->nb_free;
3137         nb_tx_free_last = txq->nb_free;
3138         if (!free_cnt)
3139                 free_cnt = txq->nb_tx_desc;
3140
3141         /* Loop through swr_ring to count the amount of
3142          * freeable mubfs and packets.
3143          */
3144         for (pkt_cnt = 0; pkt_cnt < free_cnt; ) {
3145                 for (i = 0; i < nb_tx_to_clean &&
3146                         pkt_cnt < free_cnt &&
3147                         tx_id != tx_last; i++) {
3148                         if (swr_ring[tx_id].mbuf != NULL) {
3149                                 rte_pktmbuf_free_seg(swr_ring[tx_id].mbuf);
3150                                 swr_ring[tx_id].mbuf = NULL;
3151
3152                                 /*
3153                                  * last segment in the packet,
3154                                  * increment packet count
3155                                  */
3156                                 pkt_cnt += (swr_ring[tx_id].last_id == tx_id);
3157                         }
3158
3159                         tx_id = swr_ring[tx_id].next_id;
3160                 }
3161
3162                 if (txq->rs_thresh > txq->nb_tx_desc -
3163                         txq->nb_free || tx_id == tx_last)
3164                         break;
3165
3166                 if (pkt_cnt < free_cnt) {
3167                         if (iavf_xmit_cleanup(txq))
3168                                 break;
3169
3170                         nb_tx_to_clean = txq->nb_free - nb_tx_free_last;
3171                         nb_tx_free_last = txq->nb_free;
3172                 }
3173         }
3174
3175         return (int)pkt_cnt;
3176 }
3177
3178 int
3179 iavf_dev_tx_done_cleanup(void *txq, uint32_t free_cnt)
3180 {
3181         struct iavf_tx_queue *q = (struct iavf_tx_queue *)txq;
3182
3183         return iavf_tx_done_cleanup_full(q, free_cnt);
3184 }
3185
3186 void
3187 iavf_dev_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
3188                      struct rte_eth_rxq_info *qinfo)
3189 {
3190         struct iavf_rx_queue *rxq;
3191
3192         rxq = dev->data->rx_queues[queue_id];
3193
3194         qinfo->mp = rxq->mp;
3195         qinfo->scattered_rx = dev->data->scattered_rx;
3196         qinfo->nb_desc = rxq->nb_rx_desc;
3197
3198         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
3199         qinfo->conf.rx_drop_en = true;
3200         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
3201 }
3202
3203 void
3204 iavf_dev_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
3205                      struct rte_eth_txq_info *qinfo)
3206 {
3207         struct iavf_tx_queue *txq;
3208
3209         txq = dev->data->tx_queues[queue_id];
3210
3211         qinfo->nb_desc = txq->nb_tx_desc;
3212
3213         qinfo->conf.tx_free_thresh = txq->free_thresh;
3214         qinfo->conf.tx_rs_thresh = txq->rs_thresh;
3215         qinfo->conf.offloads = txq->offloads;
3216         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
3217 }
3218
3219 /* Get the number of used descriptors of a rx queue */
3220 uint32_t
3221 iavf_dev_rxq_count(void *rx_queue)
3222 {
3223 #define IAVF_RXQ_SCAN_INTERVAL 4
3224         volatile union iavf_rx_desc *rxdp;
3225         struct iavf_rx_queue *rxq;
3226         uint16_t desc = 0;
3227
3228         rxq = rx_queue;
3229         rxdp = &rxq->rx_ring[rxq->rx_tail];
3230
3231         while ((desc < rxq->nb_rx_desc) &&
3232                ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
3233                  IAVF_RXD_QW1_STATUS_MASK) >> IAVF_RXD_QW1_STATUS_SHIFT) &
3234                (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)) {
3235                 /* Check the DD bit of a rx descriptor of each 4 in a group,
3236                  * to avoid checking too frequently and downgrading performance
3237                  * too much.
3238                  */
3239                 desc += IAVF_RXQ_SCAN_INTERVAL;
3240                 rxdp += IAVF_RXQ_SCAN_INTERVAL;
3241                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
3242                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
3243                                         desc - rxq->nb_rx_desc]);
3244         }
3245
3246         return desc;
3247 }
3248
3249 int
3250 iavf_dev_rx_desc_status(void *rx_queue, uint16_t offset)
3251 {
3252         struct iavf_rx_queue *rxq = rx_queue;
3253         volatile uint64_t *status;
3254         uint64_t mask;
3255         uint32_t desc;
3256
3257         if (unlikely(offset >= rxq->nb_rx_desc))
3258                 return -EINVAL;
3259
3260         if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
3261                 return RTE_ETH_RX_DESC_UNAVAIL;
3262
3263         desc = rxq->rx_tail + offset;
3264         if (desc >= rxq->nb_rx_desc)
3265                 desc -= rxq->nb_rx_desc;
3266
3267         status = &rxq->rx_ring[desc].wb.qword1.status_error_len;
3268         mask = rte_le_to_cpu_64((1ULL << IAVF_RX_DESC_STATUS_DD_SHIFT)
3269                 << IAVF_RXD_QW1_STATUS_SHIFT);
3270         if (*status & mask)
3271                 return RTE_ETH_RX_DESC_DONE;
3272
3273         return RTE_ETH_RX_DESC_AVAIL;
3274 }
3275
3276 int
3277 iavf_dev_tx_desc_status(void *tx_queue, uint16_t offset)
3278 {
3279         struct iavf_tx_queue *txq = tx_queue;
3280         volatile uint64_t *status;
3281         uint64_t mask, expect;
3282         uint32_t desc;
3283
3284         if (unlikely(offset >= txq->nb_tx_desc))
3285                 return -EINVAL;
3286
3287         desc = txq->tx_tail + offset;
3288         /* go to next desc that has the RS bit */
3289         desc = ((desc + txq->rs_thresh - 1) / txq->rs_thresh) *
3290                 txq->rs_thresh;
3291         if (desc >= txq->nb_tx_desc) {
3292                 desc -= txq->nb_tx_desc;
3293                 if (desc >= txq->nb_tx_desc)
3294                         desc -= txq->nb_tx_desc;
3295         }
3296
3297         status = &txq->tx_ring[desc].cmd_type_offset_bsz;
3298         mask = rte_le_to_cpu_64(IAVF_TXD_QW1_DTYPE_MASK);
3299         expect = rte_cpu_to_le_64(
3300                  IAVF_TX_DESC_DTYPE_DESC_DONE << IAVF_TXD_QW1_DTYPE_SHIFT);
3301         if ((*status & mask) == expect)
3302                 return RTE_ETH_TX_DESC_DONE;
3303
3304         return RTE_ETH_TX_DESC_FULL;
3305 }
3306
3307 static inline uint32_t
3308 iavf_get_default_ptype(uint16_t ptype)
3309 {
3310         static const uint32_t ptype_tbl[IAVF_MAX_PKT_TYPE]
3311                 __rte_cache_aligned = {
3312                 /* L2 types */
3313                 /* [0] reserved */
3314                 [1] = RTE_PTYPE_L2_ETHER,
3315                 [2] = RTE_PTYPE_L2_ETHER_TIMESYNC,
3316                 /* [3] - [5] reserved */
3317                 [6] = RTE_PTYPE_L2_ETHER_LLDP,
3318                 /* [7] - [10] reserved */
3319                 [11] = RTE_PTYPE_L2_ETHER_ARP,
3320                 /* [12] - [21] reserved */
3321
3322                 /* Non tunneled IPv4 */
3323                 [22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3324                        RTE_PTYPE_L4_FRAG,
3325                 [23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3326                        RTE_PTYPE_L4_NONFRAG,
3327                 [24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3328                        RTE_PTYPE_L4_UDP,
3329                 /* [25] reserved */
3330                 [26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3331                        RTE_PTYPE_L4_TCP,
3332                 [27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3333                        RTE_PTYPE_L4_SCTP,
3334                 [28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3335                        RTE_PTYPE_L4_ICMP,
3336
3337                 /* IPv4 --> IPv4 */
3338                 [29] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3339                        RTE_PTYPE_TUNNEL_IP |
3340                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3341                        RTE_PTYPE_INNER_L4_FRAG,
3342                 [30] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3343                        RTE_PTYPE_TUNNEL_IP |
3344                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3345                        RTE_PTYPE_INNER_L4_NONFRAG,
3346                 [31] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3347                        RTE_PTYPE_TUNNEL_IP |
3348                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3349                        RTE_PTYPE_INNER_L4_UDP,
3350                 /* [32] reserved */
3351                 [33] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3352                        RTE_PTYPE_TUNNEL_IP |
3353                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3354                        RTE_PTYPE_INNER_L4_TCP,
3355                 [34] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3356                        RTE_PTYPE_TUNNEL_IP |
3357                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3358                        RTE_PTYPE_INNER_L4_SCTP,
3359                 [35] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3360                        RTE_PTYPE_TUNNEL_IP |
3361                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3362                        RTE_PTYPE_INNER_L4_ICMP,
3363
3364                 /* IPv4 --> IPv6 */
3365                 [36] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3366                        RTE_PTYPE_TUNNEL_IP |
3367                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3368                        RTE_PTYPE_INNER_L4_FRAG,
3369                 [37] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3370                        RTE_PTYPE_TUNNEL_IP |
3371                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3372                        RTE_PTYPE_INNER_L4_NONFRAG,
3373                 [38] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3374                        RTE_PTYPE_TUNNEL_IP |
3375                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3376                        RTE_PTYPE_INNER_L4_UDP,
3377                 /* [39] reserved */
3378                 [40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3379                        RTE_PTYPE_TUNNEL_IP |
3380                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3381                        RTE_PTYPE_INNER_L4_TCP,
3382                 [41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3383                        RTE_PTYPE_TUNNEL_IP |
3384                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3385                        RTE_PTYPE_INNER_L4_SCTP,
3386                 [42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3387                        RTE_PTYPE_TUNNEL_IP |
3388                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3389                        RTE_PTYPE_INNER_L4_ICMP,
3390
3391                 /* IPv4 --> GRE/Teredo/VXLAN */
3392                 [43] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3393                        RTE_PTYPE_TUNNEL_GRENAT,
3394
3395                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv4 */
3396                 [44] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3397                        RTE_PTYPE_TUNNEL_GRENAT |
3398                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3399                        RTE_PTYPE_INNER_L4_FRAG,
3400                 [45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3401                        RTE_PTYPE_TUNNEL_GRENAT |
3402                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3403                        RTE_PTYPE_INNER_L4_NONFRAG,
3404                 [46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3405                        RTE_PTYPE_TUNNEL_GRENAT |
3406                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3407                        RTE_PTYPE_INNER_L4_UDP,
3408                 /* [47] reserved */
3409                 [48] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3410                        RTE_PTYPE_TUNNEL_GRENAT |
3411                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3412                        RTE_PTYPE_INNER_L4_TCP,
3413                 [49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3414                        RTE_PTYPE_TUNNEL_GRENAT |
3415                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3416                        RTE_PTYPE_INNER_L4_SCTP,
3417                 [50] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3418                        RTE_PTYPE_TUNNEL_GRENAT |
3419                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3420                        RTE_PTYPE_INNER_L4_ICMP,
3421
3422                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv6 */
3423                 [51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3424                        RTE_PTYPE_TUNNEL_GRENAT |
3425                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3426                        RTE_PTYPE_INNER_L4_FRAG,
3427                 [52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3428                        RTE_PTYPE_TUNNEL_GRENAT |
3429                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3430                        RTE_PTYPE_INNER_L4_NONFRAG,
3431                 [53] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3432                        RTE_PTYPE_TUNNEL_GRENAT |
3433                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3434                        RTE_PTYPE_INNER_L4_UDP,
3435                 /* [54] reserved */
3436                 [55] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3437                        RTE_PTYPE_TUNNEL_GRENAT |
3438                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3439                        RTE_PTYPE_INNER_L4_TCP,
3440                 [56] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3441                        RTE_PTYPE_TUNNEL_GRENAT |
3442                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3443                        RTE_PTYPE_INNER_L4_SCTP,
3444                 [57] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3445                        RTE_PTYPE_TUNNEL_GRENAT |
3446                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3447                        RTE_PTYPE_INNER_L4_ICMP,
3448
3449                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC */
3450                 [58] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3451                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
3452
3453                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
3454                 [59] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3455                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3456                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3457                        RTE_PTYPE_INNER_L4_FRAG,
3458                 [60] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3459                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3460                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3461                        RTE_PTYPE_INNER_L4_NONFRAG,
3462                 [61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3463                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3464                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3465                        RTE_PTYPE_INNER_L4_UDP,
3466                 /* [62] reserved */
3467                 [63] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3468                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3469                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3470                        RTE_PTYPE_INNER_L4_TCP,
3471                 [64] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3472                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3473                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3474                        RTE_PTYPE_INNER_L4_SCTP,
3475                 [65] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3476                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3477                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3478                        RTE_PTYPE_INNER_L4_ICMP,
3479
3480                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
3481                 [66] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3482                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3483                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3484                        RTE_PTYPE_INNER_L4_FRAG,
3485                 [67] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3486                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3487                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3488                        RTE_PTYPE_INNER_L4_NONFRAG,
3489                 [68] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3490                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3491                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3492                        RTE_PTYPE_INNER_L4_UDP,
3493                 /* [69] reserved */
3494                 [70] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3495                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3496                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3497                        RTE_PTYPE_INNER_L4_TCP,
3498                 [71] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3499                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3500                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3501                        RTE_PTYPE_INNER_L4_SCTP,
3502                 [72] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3503                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3504                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3505                        RTE_PTYPE_INNER_L4_ICMP,
3506                 /* [73] - [87] reserved */
3507
3508                 /* Non tunneled IPv6 */
3509                 [88] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3510                        RTE_PTYPE_L4_FRAG,
3511                 [89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3512                        RTE_PTYPE_L4_NONFRAG,
3513                 [90] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3514                        RTE_PTYPE_L4_UDP,
3515                 /* [91] reserved */
3516                 [92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3517                        RTE_PTYPE_L4_TCP,
3518                 [93] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3519                        RTE_PTYPE_L4_SCTP,
3520                 [94] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3521                        RTE_PTYPE_L4_ICMP,
3522
3523                 /* IPv6 --> IPv4 */
3524                 [95] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3525                        RTE_PTYPE_TUNNEL_IP |
3526                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3527                        RTE_PTYPE_INNER_L4_FRAG,
3528                 [96] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3529                        RTE_PTYPE_TUNNEL_IP |
3530                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3531                        RTE_PTYPE_INNER_L4_NONFRAG,
3532                 [97] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3533                        RTE_PTYPE_TUNNEL_IP |
3534                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3535                        RTE_PTYPE_INNER_L4_UDP,
3536                 /* [98] reserved */
3537                 [99] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3538                        RTE_PTYPE_TUNNEL_IP |
3539                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3540                        RTE_PTYPE_INNER_L4_TCP,
3541                 [100] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3542                         RTE_PTYPE_TUNNEL_IP |
3543                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3544                         RTE_PTYPE_INNER_L4_SCTP,
3545                 [101] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3546                         RTE_PTYPE_TUNNEL_IP |
3547                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3548                         RTE_PTYPE_INNER_L4_ICMP,
3549
3550                 /* IPv6 --> IPv6 */
3551                 [102] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3552                         RTE_PTYPE_TUNNEL_IP |
3553                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3554                         RTE_PTYPE_INNER_L4_FRAG,
3555                 [103] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3556                         RTE_PTYPE_TUNNEL_IP |
3557                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3558                         RTE_PTYPE_INNER_L4_NONFRAG,
3559                 [104] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3560                         RTE_PTYPE_TUNNEL_IP |
3561                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3562                         RTE_PTYPE_INNER_L4_UDP,
3563                 /* [105] reserved */
3564                 [106] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3565                         RTE_PTYPE_TUNNEL_IP |
3566                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3567                         RTE_PTYPE_INNER_L4_TCP,
3568                 [107] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3569                         RTE_PTYPE_TUNNEL_IP |
3570                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3571                         RTE_PTYPE_INNER_L4_SCTP,
3572                 [108] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3573                         RTE_PTYPE_TUNNEL_IP |
3574                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3575                         RTE_PTYPE_INNER_L4_ICMP,
3576
3577                 /* IPv6 --> GRE/Teredo/VXLAN */
3578                 [109] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3579                         RTE_PTYPE_TUNNEL_GRENAT,
3580
3581                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv4 */
3582                 [110] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3583                         RTE_PTYPE_TUNNEL_GRENAT |
3584                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3585                         RTE_PTYPE_INNER_L4_FRAG,
3586                 [111] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3587                         RTE_PTYPE_TUNNEL_GRENAT |
3588                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3589                         RTE_PTYPE_INNER_L4_NONFRAG,
3590                 [112] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3591                         RTE_PTYPE_TUNNEL_GRENAT |
3592                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3593                         RTE_PTYPE_INNER_L4_UDP,
3594                 /* [113] reserved */
3595                 [114] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3596                         RTE_PTYPE_TUNNEL_GRENAT |
3597                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3598                         RTE_PTYPE_INNER_L4_TCP,
3599                 [115] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3600                         RTE_PTYPE_TUNNEL_GRENAT |
3601                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3602                         RTE_PTYPE_INNER_L4_SCTP,
3603                 [116] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3604                         RTE_PTYPE_TUNNEL_GRENAT |
3605                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3606                         RTE_PTYPE_INNER_L4_ICMP,
3607
3608                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv6 */
3609                 [117] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3610                         RTE_PTYPE_TUNNEL_GRENAT |
3611                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3612                         RTE_PTYPE_INNER_L4_FRAG,
3613                 [118] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3614                         RTE_PTYPE_TUNNEL_GRENAT |
3615                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3616                         RTE_PTYPE_INNER_L4_NONFRAG,
3617                 [119] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3618                         RTE_PTYPE_TUNNEL_GRENAT |
3619                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3620                         RTE_PTYPE_INNER_L4_UDP,
3621                 /* [120] reserved */
3622                 [121] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3623                         RTE_PTYPE_TUNNEL_GRENAT |
3624                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3625                         RTE_PTYPE_INNER_L4_TCP,
3626                 [122] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3627                         RTE_PTYPE_TUNNEL_GRENAT |
3628                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3629                         RTE_PTYPE_INNER_L4_SCTP,
3630                 [123] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3631                         RTE_PTYPE_TUNNEL_GRENAT |
3632                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3633                         RTE_PTYPE_INNER_L4_ICMP,
3634
3635                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC */
3636                 [124] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3637                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
3638
3639                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
3640                 [125] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3641                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3642                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3643                         RTE_PTYPE_INNER_L4_FRAG,
3644                 [126] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3645                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3646                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3647                         RTE_PTYPE_INNER_L4_NONFRAG,
3648                 [127] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3649                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3650                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3651                         RTE_PTYPE_INNER_L4_UDP,
3652                 /* [128] reserved */
3653                 [129] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3654                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3655                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3656                         RTE_PTYPE_INNER_L4_TCP,
3657                 [130] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3658                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3659                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3660                         RTE_PTYPE_INNER_L4_SCTP,
3661                 [131] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3662                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3663                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3664                         RTE_PTYPE_INNER_L4_ICMP,
3665
3666                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
3667                 [132] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3668                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3669                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3670                         RTE_PTYPE_INNER_L4_FRAG,
3671                 [133] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3672                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3673                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3674                         RTE_PTYPE_INNER_L4_NONFRAG,
3675                 [134] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3676                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3677                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3678                         RTE_PTYPE_INNER_L4_UDP,
3679                 /* [135] reserved */
3680                 [136] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3681                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3682                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3683                         RTE_PTYPE_INNER_L4_TCP,
3684                 [137] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3685                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3686                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3687                         RTE_PTYPE_INNER_L4_SCTP,
3688                 [138] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3689                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3690                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3691                         RTE_PTYPE_INNER_L4_ICMP,
3692                 /* [139] - [299] reserved */
3693
3694                 /* PPPoE */
3695                 [300] = RTE_PTYPE_L2_ETHER_PPPOE,
3696                 [301] = RTE_PTYPE_L2_ETHER_PPPOE,
3697
3698                 /* PPPoE --> IPv4 */
3699                 [302] = RTE_PTYPE_L2_ETHER_PPPOE |
3700                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3701                         RTE_PTYPE_L4_FRAG,
3702                 [303] = RTE_PTYPE_L2_ETHER_PPPOE |
3703                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3704                         RTE_PTYPE_L4_NONFRAG,
3705                 [304] = RTE_PTYPE_L2_ETHER_PPPOE |
3706                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3707                         RTE_PTYPE_L4_UDP,
3708                 [305] = RTE_PTYPE_L2_ETHER_PPPOE |
3709                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3710                         RTE_PTYPE_L4_TCP,
3711                 [306] = RTE_PTYPE_L2_ETHER_PPPOE |
3712                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3713                         RTE_PTYPE_L4_SCTP,
3714                 [307] = RTE_PTYPE_L2_ETHER_PPPOE |
3715                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3716                         RTE_PTYPE_L4_ICMP,
3717
3718                 /* PPPoE --> IPv6 */
3719                 [308] = RTE_PTYPE_L2_ETHER_PPPOE |
3720                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3721                         RTE_PTYPE_L4_FRAG,
3722                 [309] = RTE_PTYPE_L2_ETHER_PPPOE |
3723                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3724                         RTE_PTYPE_L4_NONFRAG,
3725                 [310] = RTE_PTYPE_L2_ETHER_PPPOE |
3726                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3727                         RTE_PTYPE_L4_UDP,
3728                 [311] = RTE_PTYPE_L2_ETHER_PPPOE |
3729                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3730                         RTE_PTYPE_L4_TCP,
3731                 [312] = RTE_PTYPE_L2_ETHER_PPPOE |
3732                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3733                         RTE_PTYPE_L4_SCTP,
3734                 [313] = RTE_PTYPE_L2_ETHER_PPPOE |
3735                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3736                         RTE_PTYPE_L4_ICMP,
3737                 /* [314] - [324] reserved */
3738
3739                 /* IPv4/IPv6 --> GTPC/GTPU */
3740                 [325] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3741                         RTE_PTYPE_TUNNEL_GTPC,
3742                 [326] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3743                         RTE_PTYPE_TUNNEL_GTPC,
3744                 [327] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3745                         RTE_PTYPE_TUNNEL_GTPC,
3746                 [328] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3747                         RTE_PTYPE_TUNNEL_GTPC,
3748                 [329] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3749                         RTE_PTYPE_TUNNEL_GTPU,
3750                 [330] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3751                         RTE_PTYPE_TUNNEL_GTPU,
3752
3753                 /* IPv4 --> GTPU --> IPv4 */
3754                 [331] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3755                         RTE_PTYPE_TUNNEL_GTPU |
3756                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3757                         RTE_PTYPE_INNER_L4_FRAG,
3758                 [332] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3759                         RTE_PTYPE_TUNNEL_GTPU |
3760                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3761                         RTE_PTYPE_INNER_L4_NONFRAG,
3762                 [333] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3763                         RTE_PTYPE_TUNNEL_GTPU |
3764                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3765                         RTE_PTYPE_INNER_L4_UDP,
3766                 [334] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3767                         RTE_PTYPE_TUNNEL_GTPU |
3768                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3769                         RTE_PTYPE_INNER_L4_TCP,
3770                 [335] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3771                         RTE_PTYPE_TUNNEL_GTPU |
3772                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3773                         RTE_PTYPE_INNER_L4_ICMP,
3774
3775                 /* IPv6 --> GTPU --> IPv4 */
3776                 [336] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3777                         RTE_PTYPE_TUNNEL_GTPU |
3778                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3779                         RTE_PTYPE_INNER_L4_FRAG,
3780                 [337] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3781                         RTE_PTYPE_TUNNEL_GTPU |
3782                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3783                         RTE_PTYPE_INNER_L4_NONFRAG,
3784                 [338] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3785                         RTE_PTYPE_TUNNEL_GTPU |
3786                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3787                         RTE_PTYPE_INNER_L4_UDP,
3788                 [339] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3789                         RTE_PTYPE_TUNNEL_GTPU |
3790                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3791                         RTE_PTYPE_INNER_L4_TCP,
3792                 [340] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3793                         RTE_PTYPE_TUNNEL_GTPU |
3794                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3795                         RTE_PTYPE_INNER_L4_ICMP,
3796
3797                 /* IPv4 --> GTPU --> IPv6 */
3798                 [341] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3799                         RTE_PTYPE_TUNNEL_GTPU |
3800                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3801                         RTE_PTYPE_INNER_L4_FRAG,
3802                 [342] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3803                         RTE_PTYPE_TUNNEL_GTPU |
3804                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3805                         RTE_PTYPE_INNER_L4_NONFRAG,
3806                 [343] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3807                         RTE_PTYPE_TUNNEL_GTPU |
3808                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3809                         RTE_PTYPE_INNER_L4_UDP,
3810                 [344] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3811                         RTE_PTYPE_TUNNEL_GTPU |
3812                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3813                         RTE_PTYPE_INNER_L4_TCP,
3814                 [345] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3815                         RTE_PTYPE_TUNNEL_GTPU |
3816                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3817                         RTE_PTYPE_INNER_L4_ICMP,
3818
3819                 /* IPv6 --> GTPU --> IPv6 */
3820                 [346] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3821                         RTE_PTYPE_TUNNEL_GTPU |
3822                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3823                         RTE_PTYPE_INNER_L4_FRAG,
3824                 [347] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3825                         RTE_PTYPE_TUNNEL_GTPU |
3826                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3827                         RTE_PTYPE_INNER_L4_NONFRAG,
3828                 [348] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3829                         RTE_PTYPE_TUNNEL_GTPU |
3830                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3831                         RTE_PTYPE_INNER_L4_UDP,
3832                 [349] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3833                         RTE_PTYPE_TUNNEL_GTPU |
3834                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3835                         RTE_PTYPE_INNER_L4_TCP,
3836                 [350] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3837                         RTE_PTYPE_TUNNEL_GTPU |
3838                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3839                         RTE_PTYPE_INNER_L4_ICMP,
3840
3841                 /* IPv4 --> UDP ECPRI */
3842                 [372] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3843                         RTE_PTYPE_L4_UDP,
3844                 [373] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3845                         RTE_PTYPE_L4_UDP,
3846                 [374] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3847                         RTE_PTYPE_L4_UDP,
3848                 [375] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3849                         RTE_PTYPE_L4_UDP,
3850                 [376] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3851                         RTE_PTYPE_L4_UDP,
3852                 [377] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3853                         RTE_PTYPE_L4_UDP,
3854                 [378] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3855                         RTE_PTYPE_L4_UDP,
3856                 [379] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3857                         RTE_PTYPE_L4_UDP,
3858                 [380] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3859                         RTE_PTYPE_L4_UDP,
3860                 [381] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3861                         RTE_PTYPE_L4_UDP,
3862
3863                 /* IPV6 --> UDP ECPRI */
3864                 [382] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3865                         RTE_PTYPE_L4_UDP,
3866                 [383] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3867                         RTE_PTYPE_L4_UDP,
3868                 [384] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3869                         RTE_PTYPE_L4_UDP,
3870                 [385] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3871                         RTE_PTYPE_L4_UDP,
3872                 [386] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3873                         RTE_PTYPE_L4_UDP,
3874                 [387] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3875                         RTE_PTYPE_L4_UDP,
3876                 [388] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3877                         RTE_PTYPE_L4_UDP,
3878                 [389] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3879                         RTE_PTYPE_L4_UDP,
3880                 [390] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3881                         RTE_PTYPE_L4_UDP,
3882                 [391] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3883                         RTE_PTYPE_L4_UDP,
3884                 /* All others reserved */
3885         };
3886
3887         return ptype_tbl[ptype];
3888 }
3889
3890 void __rte_cold
3891 iavf_set_default_ptype_table(struct rte_eth_dev *dev)
3892 {
3893         struct iavf_adapter *ad =
3894                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3895         int i;
3896
3897         for (i = 0; i < IAVF_MAX_PKT_TYPE; i++)
3898                 ad->ptype_tbl[i] = iavf_get_default_ptype(i);
3899 }