1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2017 Intel Corporation
13 #include <sys/queue.h>
15 #include <rte_string_fns.h>
16 #include <rte_memzone.h>
18 #include <rte_malloc.h>
19 #include <rte_ether.h>
20 #include <ethdev_driver.h>
29 #include "iavf_rxtx.h"
30 #include "rte_pmd_iavf.h"
32 /* Offset of mbuf dynamic field for protocol extraction's metadata */
33 int rte_pmd_ifd_dynfield_proto_xtr_metadata_offs = -1;
35 /* Mask of mbuf dynamic flags for protocol extraction's type */
36 uint64_t rte_pmd_ifd_dynflag_proto_xtr_vlan_mask;
37 uint64_t rte_pmd_ifd_dynflag_proto_xtr_ipv4_mask;
38 uint64_t rte_pmd_ifd_dynflag_proto_xtr_ipv6_mask;
39 uint64_t rte_pmd_ifd_dynflag_proto_xtr_ipv6_flow_mask;
40 uint64_t rte_pmd_ifd_dynflag_proto_xtr_tcp_mask;
41 uint64_t rte_pmd_ifd_dynflag_proto_xtr_ip_offset_mask;
44 iavf_proto_xtr_type_to_rxdid(uint8_t flex_type)
46 static uint8_t rxdid_map[] = {
47 [IAVF_PROTO_XTR_NONE] = IAVF_RXDID_COMMS_OVS_1,
48 [IAVF_PROTO_XTR_VLAN] = IAVF_RXDID_COMMS_AUX_VLAN,
49 [IAVF_PROTO_XTR_IPV4] = IAVF_RXDID_COMMS_AUX_IPV4,
50 [IAVF_PROTO_XTR_IPV6] = IAVF_RXDID_COMMS_AUX_IPV6,
51 [IAVF_PROTO_XTR_IPV6_FLOW] = IAVF_RXDID_COMMS_AUX_IPV6_FLOW,
52 [IAVF_PROTO_XTR_TCP] = IAVF_RXDID_COMMS_AUX_TCP,
53 [IAVF_PROTO_XTR_IP_OFFSET] = IAVF_RXDID_COMMS_AUX_IP_OFFSET,
56 return flex_type < RTE_DIM(rxdid_map) ?
57 rxdid_map[flex_type] : IAVF_RXDID_COMMS_OVS_1;
61 iavf_monitor_callback(const uint64_t value,
62 const uint64_t arg[RTE_POWER_MONITOR_OPAQUE_SZ] __rte_unused)
64 const uint64_t m = rte_cpu_to_le_64(1 << IAVF_RX_DESC_STATUS_DD_SHIFT);
66 * we expect the DD bit to be set to 1 if this descriptor was already
69 return (value & m) == m ? -1 : 0;
73 iavf_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc)
75 struct iavf_rx_queue *rxq = rx_queue;
76 volatile union iavf_rx_desc *rxdp;
80 rxdp = &rxq->rx_ring[desc];
81 /* watch for changes in status bit */
82 pmc->addr = &rxdp->wb.qword1.status_error_len;
84 /* comparison callback */
85 pmc->fn = iavf_monitor_callback;
87 /* registers are 64-bit */
88 pmc->size = sizeof(uint64_t);
94 check_rx_thresh(uint16_t nb_desc, uint16_t thresh)
96 /* The following constraints must be satisfied:
97 * thresh < rxq->nb_rx_desc
99 if (thresh >= nb_desc) {
100 PMD_INIT_LOG(ERR, "rx_free_thresh (%u) must be less than %u",
108 check_tx_thresh(uint16_t nb_desc, uint16_t tx_rs_thresh,
109 uint16_t tx_free_thresh)
111 /* TX descriptors will have their RS bit set after tx_rs_thresh
112 * descriptors have been used. The TX descriptor ring will be cleaned
113 * after tx_free_thresh descriptors are used or if the number of
114 * descriptors required to transmit a packet is greater than the
115 * number of free TX descriptors.
117 * The following constraints must be satisfied:
118 * - tx_rs_thresh must be less than the size of the ring minus 2.
119 * - tx_free_thresh must be less than the size of the ring minus 3.
120 * - tx_rs_thresh must be less than or equal to tx_free_thresh.
121 * - tx_rs_thresh must be a divisor of the ring size.
123 * One descriptor in the TX ring is used as a sentinel to avoid a H/W
124 * race condition, hence the maximum threshold constraints. When set
125 * to zero use default values.
127 if (tx_rs_thresh >= (nb_desc - 2)) {
128 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be less than the "
129 "number of TX descriptors (%u) minus 2",
130 tx_rs_thresh, nb_desc);
133 if (tx_free_thresh >= (nb_desc - 3)) {
134 PMD_INIT_LOG(ERR, "tx_free_thresh (%u) must be less than the "
135 "number of TX descriptors (%u) minus 3.",
136 tx_free_thresh, nb_desc);
139 if (tx_rs_thresh > tx_free_thresh) {
140 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be less than or "
141 "equal to tx_free_thresh (%u).",
142 tx_rs_thresh, tx_free_thresh);
145 if ((nb_desc % tx_rs_thresh) != 0) {
146 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be a divisor of the "
147 "number of TX descriptors (%u).",
148 tx_rs_thresh, nb_desc);
156 check_rx_vec_allow(struct iavf_rx_queue *rxq)
158 if (rxq->rx_free_thresh >= IAVF_VPMD_RX_MAX_BURST &&
159 rxq->nb_rx_desc % rxq->rx_free_thresh == 0) {
160 PMD_INIT_LOG(DEBUG, "Vector Rx can be enabled on this rxq.");
164 PMD_INIT_LOG(DEBUG, "Vector Rx cannot be enabled on this rxq.");
169 check_tx_vec_allow(struct iavf_tx_queue *txq)
171 if (!(txq->offloads & IAVF_TX_NO_VECTOR_FLAGS) &&
172 txq->rs_thresh >= IAVF_VPMD_TX_MAX_BURST &&
173 txq->rs_thresh <= IAVF_VPMD_TX_MAX_FREE_BUF) {
174 PMD_INIT_LOG(DEBUG, "Vector tx can be enabled on this txq.");
177 PMD_INIT_LOG(DEBUG, "Vector Tx cannot be enabled on this txq.");
182 check_rx_bulk_allow(struct iavf_rx_queue *rxq)
186 if (!(rxq->rx_free_thresh >= IAVF_RX_MAX_BURST)) {
187 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
188 "rxq->rx_free_thresh=%d, "
189 "IAVF_RX_MAX_BURST=%d",
190 rxq->rx_free_thresh, IAVF_RX_MAX_BURST);
192 } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
193 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
194 "rxq->nb_rx_desc=%d, "
195 "rxq->rx_free_thresh=%d",
196 rxq->nb_rx_desc, rxq->rx_free_thresh);
203 reset_rx_queue(struct iavf_rx_queue *rxq)
211 len = rxq->nb_rx_desc + IAVF_RX_MAX_BURST;
213 for (i = 0; i < len * sizeof(union iavf_rx_desc); i++)
214 ((volatile char *)rxq->rx_ring)[i] = 0;
216 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
218 for (i = 0; i < IAVF_RX_MAX_BURST; i++)
219 rxq->sw_ring[rxq->nb_rx_desc + i] = &rxq->fake_mbuf;
222 rxq->rx_nb_avail = 0;
223 rxq->rx_next_avail = 0;
224 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
229 if (rxq->pkt_first_seg != NULL)
230 rte_pktmbuf_free(rxq->pkt_first_seg);
232 rxq->pkt_first_seg = NULL;
233 rxq->pkt_last_seg = NULL;
235 rxq->rxrearm_start = 0;
239 reset_tx_queue(struct iavf_tx_queue *txq)
241 struct iavf_tx_entry *txe;
246 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
251 size = sizeof(struct iavf_tx_desc) * txq->nb_tx_desc;
252 for (i = 0; i < size; i++)
253 ((volatile char *)txq->tx_ring)[i] = 0;
255 prev = (uint16_t)(txq->nb_tx_desc - 1);
256 for (i = 0; i < txq->nb_tx_desc; i++) {
257 txq->tx_ring[i].cmd_type_offset_bsz =
258 rte_cpu_to_le_64(IAVF_TX_DESC_DTYPE_DESC_DONE);
261 txe[prev].next_id = i;
268 txq->last_desc_cleaned = txq->nb_tx_desc - 1;
269 txq->nb_free = txq->nb_tx_desc - 1;
271 txq->next_dd = txq->rs_thresh - 1;
272 txq->next_rs = txq->rs_thresh - 1;
276 alloc_rxq_mbufs(struct iavf_rx_queue *rxq)
278 volatile union iavf_rx_desc *rxd;
279 struct rte_mbuf *mbuf = NULL;
283 for (i = 0; i < rxq->nb_rx_desc; i++) {
284 mbuf = rte_mbuf_raw_alloc(rxq->mp);
285 if (unlikely(!mbuf)) {
286 PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
290 rte_mbuf_refcnt_set(mbuf, 1);
292 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
294 mbuf->port = rxq->port_id;
297 rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
299 rxd = &rxq->rx_ring[i];
300 rxd->read.pkt_addr = dma_addr;
301 rxd->read.hdr_addr = 0;
302 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
307 rxq->sw_ring[i] = mbuf;
314 release_rxq_mbufs(struct iavf_rx_queue *rxq)
321 for (i = 0; i < rxq->nb_rx_desc; i++) {
322 if (rxq->sw_ring[i]) {
323 rte_pktmbuf_free_seg(rxq->sw_ring[i]);
324 rxq->sw_ring[i] = NULL;
329 if (rxq->rx_nb_avail == 0)
331 for (i = 0; i < rxq->rx_nb_avail; i++) {
332 struct rte_mbuf *mbuf;
334 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
335 rte_pktmbuf_free_seg(mbuf);
337 rxq->rx_nb_avail = 0;
341 release_txq_mbufs(struct iavf_tx_queue *txq)
345 if (!txq || !txq->sw_ring) {
346 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
350 for (i = 0; i < txq->nb_tx_desc; i++) {
351 if (txq->sw_ring[i].mbuf) {
352 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
353 txq->sw_ring[i].mbuf = NULL;
358 static const struct iavf_rxq_ops def_rxq_ops = {
359 .release_mbufs = release_rxq_mbufs,
362 static const struct iavf_txq_ops def_txq_ops = {
363 .release_mbufs = release_txq_mbufs,
367 iavf_rxd_to_pkt_fields_by_comms_ovs(__rte_unused struct iavf_rx_queue *rxq,
369 volatile union iavf_rx_flex_desc *rxdp)
371 volatile struct iavf_32b_rx_flex_desc_comms_ovs *desc =
372 (volatile struct iavf_32b_rx_flex_desc_comms_ovs *)rxdp;
373 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
377 if (desc->flow_id != 0xFFFFFFFF) {
378 mb->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
379 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
382 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
383 stat_err = rte_le_to_cpu_16(desc->status_error0);
384 if (likely(stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
385 mb->ol_flags |= PKT_RX_RSS_HASH;
386 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
392 iavf_rxd_to_pkt_fields_by_comms_aux_v1(struct iavf_rx_queue *rxq,
394 volatile union iavf_rx_flex_desc *rxdp)
396 volatile struct iavf_32b_rx_flex_desc_comms *desc =
397 (volatile struct iavf_32b_rx_flex_desc_comms *)rxdp;
400 stat_err = rte_le_to_cpu_16(desc->status_error0);
401 if (likely(stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
402 mb->ol_flags |= PKT_RX_RSS_HASH;
403 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
406 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
407 if (desc->flow_id != 0xFFFFFFFF) {
408 mb->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
409 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
412 if (rxq->xtr_ol_flag) {
413 uint32_t metadata = 0;
415 stat_err = rte_le_to_cpu_16(desc->status_error1);
417 if (stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS1_XTRMD4_VALID_S))
418 metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux0);
420 if (stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS1_XTRMD5_VALID_S))
422 rte_le_to_cpu_16(desc->flex_ts.flex.aux1) << 16;
425 mb->ol_flags |= rxq->xtr_ol_flag;
427 *RTE_PMD_IFD_DYNF_PROTO_XTR_METADATA(mb) = metadata;
434 iavf_rxd_to_pkt_fields_by_comms_aux_v2(struct iavf_rx_queue *rxq,
436 volatile union iavf_rx_flex_desc *rxdp)
438 volatile struct iavf_32b_rx_flex_desc_comms *desc =
439 (volatile struct iavf_32b_rx_flex_desc_comms *)rxdp;
442 stat_err = rte_le_to_cpu_16(desc->status_error0);
443 if (likely(stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
444 mb->ol_flags |= PKT_RX_RSS_HASH;
445 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
448 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
449 if (desc->flow_id != 0xFFFFFFFF) {
450 mb->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
451 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
454 if (rxq->xtr_ol_flag) {
455 uint32_t metadata = 0;
457 if (desc->flex_ts.flex.aux0 != 0xFFFF)
458 metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux0);
459 else if (desc->flex_ts.flex.aux1 != 0xFFFF)
460 metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux1);
463 mb->ol_flags |= rxq->xtr_ol_flag;
465 *RTE_PMD_IFD_DYNF_PROTO_XTR_METADATA(mb) = metadata;
472 iavf_select_rxd_to_pkt_fields_handler(struct iavf_rx_queue *rxq, uint32_t rxdid)
475 case IAVF_RXDID_COMMS_AUX_VLAN:
476 rxq->xtr_ol_flag = rte_pmd_ifd_dynflag_proto_xtr_vlan_mask;
477 rxq->rxd_to_pkt_fields =
478 iavf_rxd_to_pkt_fields_by_comms_aux_v1;
480 case IAVF_RXDID_COMMS_AUX_IPV4:
481 rxq->xtr_ol_flag = rte_pmd_ifd_dynflag_proto_xtr_ipv4_mask;
482 rxq->rxd_to_pkt_fields =
483 iavf_rxd_to_pkt_fields_by_comms_aux_v1;
485 case IAVF_RXDID_COMMS_AUX_IPV6:
486 rxq->xtr_ol_flag = rte_pmd_ifd_dynflag_proto_xtr_ipv6_mask;
487 rxq->rxd_to_pkt_fields =
488 iavf_rxd_to_pkt_fields_by_comms_aux_v1;
490 case IAVF_RXDID_COMMS_AUX_IPV6_FLOW:
492 rte_pmd_ifd_dynflag_proto_xtr_ipv6_flow_mask;
493 rxq->rxd_to_pkt_fields =
494 iavf_rxd_to_pkt_fields_by_comms_aux_v1;
496 case IAVF_RXDID_COMMS_AUX_TCP:
497 rxq->xtr_ol_flag = rte_pmd_ifd_dynflag_proto_xtr_tcp_mask;
498 rxq->rxd_to_pkt_fields =
499 iavf_rxd_to_pkt_fields_by_comms_aux_v1;
501 case IAVF_RXDID_COMMS_AUX_IP_OFFSET:
503 rte_pmd_ifd_dynflag_proto_xtr_ip_offset_mask;
504 rxq->rxd_to_pkt_fields =
505 iavf_rxd_to_pkt_fields_by_comms_aux_v2;
507 case IAVF_RXDID_COMMS_OVS_1:
508 rxq->rxd_to_pkt_fields = iavf_rxd_to_pkt_fields_by_comms_ovs;
511 /* update this according to the RXDID for FLEX_DESC_NONE */
512 rxq->rxd_to_pkt_fields = iavf_rxd_to_pkt_fields_by_comms_ovs;
516 if (!rte_pmd_ifd_dynf_proto_xtr_metadata_avail())
517 rxq->xtr_ol_flag = 0;
521 iavf_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
522 uint16_t nb_desc, unsigned int socket_id,
523 const struct rte_eth_rxconf *rx_conf,
524 struct rte_mempool *mp)
526 struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
527 struct iavf_adapter *ad =
528 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
529 struct iavf_info *vf =
530 IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
531 struct iavf_vsi *vsi = &vf->vsi;
532 struct iavf_rx_queue *rxq;
533 const struct rte_memzone *mz;
537 uint16_t rx_free_thresh;
540 PMD_INIT_FUNC_TRACE();
542 offloads = rx_conf->offloads | dev->data->dev_conf.rxmode.offloads;
544 if (nb_desc % IAVF_ALIGN_RING_DESC != 0 ||
545 nb_desc > IAVF_MAX_RING_DESC ||
546 nb_desc < IAVF_MIN_RING_DESC) {
547 PMD_INIT_LOG(ERR, "Number (%u) of receive descriptors is "
552 /* Check free threshold */
553 rx_free_thresh = (rx_conf->rx_free_thresh == 0) ?
554 IAVF_DEFAULT_RX_FREE_THRESH :
555 rx_conf->rx_free_thresh;
556 if (check_rx_thresh(nb_desc, rx_free_thresh) != 0)
559 /* Free memory if needed */
560 if (dev->data->rx_queues[queue_idx]) {
561 iavf_dev_rx_queue_release(dev->data->rx_queues[queue_idx]);
562 dev->data->rx_queues[queue_idx] = NULL;
565 /* Allocate the rx queue data structure */
566 rxq = rte_zmalloc_socket("iavf rxq",
567 sizeof(struct iavf_rx_queue),
571 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
572 "rx queue data structure");
576 if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC) {
577 proto_xtr = vf->proto_xtr ? vf->proto_xtr[queue_idx] :
579 rxq->rxdid = iavf_proto_xtr_type_to_rxdid(proto_xtr);
580 rxq->proto_xtr = proto_xtr;
582 rxq->rxdid = IAVF_RXDID_LEGACY_1;
583 rxq->proto_xtr = IAVF_PROTO_XTR_NONE;
586 if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_VLAN_V2) {
587 struct virtchnl_vlan_supported_caps *stripping_support =
588 &vf->vlan_v2_caps.offloads.stripping_support;
589 uint32_t stripping_cap;
591 if (stripping_support->outer)
592 stripping_cap = stripping_support->outer;
594 stripping_cap = stripping_support->inner;
596 if (stripping_cap & VIRTCHNL_VLAN_TAG_LOCATION_L2TAG1)
597 rxq->rx_flags = IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG1;
598 else if (stripping_cap & VIRTCHNL_VLAN_TAG_LOCATION_L2TAG2_2)
599 rxq->rx_flags = IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG2_2;
601 rxq->rx_flags = IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG1;
604 iavf_select_rxd_to_pkt_fields_handler(rxq, rxq->rxdid);
607 rxq->nb_rx_desc = nb_desc;
608 rxq->rx_free_thresh = rx_free_thresh;
609 rxq->queue_id = queue_idx;
610 rxq->port_id = dev->data->port_id;
611 rxq->rx_deferred_start = rx_conf->rx_deferred_start;
614 rxq->offloads = offloads;
616 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
617 rxq->crc_len = RTE_ETHER_CRC_LEN;
621 len = rte_pktmbuf_data_room_size(rxq->mp) - RTE_PKTMBUF_HEADROOM;
622 rxq->rx_buf_len = RTE_ALIGN(len, (1 << IAVF_RXQ_CTX_DBUFF_SHIFT));
624 /* Allocate the software ring. */
625 len = nb_desc + IAVF_RX_MAX_BURST;
627 rte_zmalloc_socket("iavf rx sw ring",
628 sizeof(struct rte_mbuf *) * len,
632 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW ring");
637 /* Allocate the maximun number of RX ring hardware descriptor with
638 * a liitle more to support bulk allocate.
640 len = IAVF_MAX_RING_DESC + IAVF_RX_MAX_BURST;
641 ring_size = RTE_ALIGN(len * sizeof(union iavf_rx_desc),
643 mz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
644 ring_size, IAVF_RING_BASE_ALIGN,
647 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for RX");
648 rte_free(rxq->sw_ring);
652 /* Zero all the descriptors in the ring. */
653 memset(mz->addr, 0, ring_size);
654 rxq->rx_ring_phys_addr = mz->iova;
655 rxq->rx_ring = (union iavf_rx_desc *)mz->addr;
660 dev->data->rx_queues[queue_idx] = rxq;
661 rxq->qrx_tail = hw->hw_addr + IAVF_QRX_TAIL1(rxq->queue_id);
662 rxq->ops = &def_rxq_ops;
664 if (check_rx_bulk_allow(rxq) == true) {
665 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
666 "satisfied. Rx Burst Bulk Alloc function will be "
667 "used on port=%d, queue=%d.",
668 rxq->port_id, rxq->queue_id);
670 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
671 "not satisfied, Scattered Rx is requested "
672 "on port=%d, queue=%d.",
673 rxq->port_id, rxq->queue_id);
674 ad->rx_bulk_alloc_allowed = false;
677 if (check_rx_vec_allow(rxq) == false)
678 ad->rx_vec_allowed = false;
684 iavf_dev_tx_queue_setup(struct rte_eth_dev *dev,
687 unsigned int socket_id,
688 const struct rte_eth_txconf *tx_conf)
690 struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
691 struct iavf_info *vf =
692 IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
693 struct iavf_tx_queue *txq;
694 const struct rte_memzone *mz;
696 uint16_t tx_rs_thresh, tx_free_thresh;
699 PMD_INIT_FUNC_TRACE();
701 offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
703 if (nb_desc % IAVF_ALIGN_RING_DESC != 0 ||
704 nb_desc > IAVF_MAX_RING_DESC ||
705 nb_desc < IAVF_MIN_RING_DESC) {
706 PMD_INIT_LOG(ERR, "Number (%u) of transmit descriptors is "
711 tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
712 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
713 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
714 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
715 if (check_tx_thresh(nb_desc, tx_rs_thresh, tx_free_thresh) != 0)
718 /* Free memory if needed. */
719 if (dev->data->tx_queues[queue_idx]) {
720 iavf_dev_tx_queue_release(dev->data->tx_queues[queue_idx]);
721 dev->data->tx_queues[queue_idx] = NULL;
724 /* Allocate the TX queue data structure. */
725 txq = rte_zmalloc_socket("iavf txq",
726 sizeof(struct iavf_tx_queue),
730 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
731 "tx queue structure");
735 if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_VLAN_V2) {
736 struct virtchnl_vlan_supported_caps *insertion_support =
737 &vf->vlan_v2_caps.offloads.insertion_support;
738 uint32_t insertion_cap;
740 if (insertion_support->outer)
741 insertion_cap = insertion_support->outer;
743 insertion_cap = insertion_support->inner;
745 if (insertion_cap & VIRTCHNL_VLAN_TAG_LOCATION_L2TAG1)
746 txq->vlan_flag = IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG1;
747 else if (insertion_cap & VIRTCHNL_VLAN_TAG_LOCATION_L2TAG2)
748 txq->vlan_flag = IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG2;
750 txq->vlan_flag = IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG1;
753 txq->nb_tx_desc = nb_desc;
754 txq->rs_thresh = tx_rs_thresh;
755 txq->free_thresh = tx_free_thresh;
756 txq->queue_id = queue_idx;
757 txq->port_id = dev->data->port_id;
758 txq->offloads = offloads;
759 txq->tx_deferred_start = tx_conf->tx_deferred_start;
761 /* Allocate software ring */
763 rte_zmalloc_socket("iavf tx sw ring",
764 sizeof(struct iavf_tx_entry) * nb_desc,
768 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW TX ring");
773 /* Allocate TX hardware ring descriptors. */
774 ring_size = sizeof(struct iavf_tx_desc) * IAVF_MAX_RING_DESC;
775 ring_size = RTE_ALIGN(ring_size, IAVF_DMA_MEM_ALIGN);
776 mz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
777 ring_size, IAVF_RING_BASE_ALIGN,
780 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for TX");
781 rte_free(txq->sw_ring);
785 txq->tx_ring_phys_addr = mz->iova;
786 txq->tx_ring = (struct iavf_tx_desc *)mz->addr;
791 dev->data->tx_queues[queue_idx] = txq;
792 txq->qtx_tail = hw->hw_addr + IAVF_QTX_TAIL1(queue_idx);
793 txq->ops = &def_txq_ops;
795 if (check_tx_vec_allow(txq) == false) {
796 struct iavf_adapter *ad =
797 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
798 ad->tx_vec_allowed = false;
801 if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_QOS &&
802 vf->tm_conf.committed) {
804 for (tc = 0; tc < vf->qos_cap->num_elem; tc++) {
805 if (txq->queue_id >= vf->qtc_map[tc].start_queue_id &&
806 txq->queue_id < (vf->qtc_map[tc].start_queue_id +
807 vf->qtc_map[tc].queue_count))
810 if (tc >= vf->qos_cap->num_elem) {
811 PMD_INIT_LOG(ERR, "Queue TC mapping is not correct");
821 iavf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
823 struct iavf_adapter *adapter =
824 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
825 struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
826 struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
827 struct iavf_rx_queue *rxq;
830 PMD_DRV_FUNC_TRACE();
832 if (rx_queue_id >= dev->data->nb_rx_queues)
835 rxq = dev->data->rx_queues[rx_queue_id];
837 err = alloc_rxq_mbufs(rxq);
839 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
845 /* Init the RX tail register. */
846 IAVF_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
847 IAVF_WRITE_FLUSH(hw);
849 /* Ready to switch the queue on */
851 err = iavf_switch_queue(adapter, rx_queue_id, true, true);
853 err = iavf_switch_queue_lv(adapter, rx_queue_id, true, true);
856 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
859 dev->data->rx_queue_state[rx_queue_id] =
860 RTE_ETH_QUEUE_STATE_STARTED;
866 iavf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
868 struct iavf_adapter *adapter =
869 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
870 struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
871 struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
872 struct iavf_tx_queue *txq;
875 PMD_DRV_FUNC_TRACE();
877 if (tx_queue_id >= dev->data->nb_tx_queues)
880 txq = dev->data->tx_queues[tx_queue_id];
882 /* Init the RX tail register. */
883 IAVF_PCI_REG_WRITE(txq->qtx_tail, 0);
884 IAVF_WRITE_FLUSH(hw);
886 /* Ready to switch the queue on */
888 err = iavf_switch_queue(adapter, tx_queue_id, false, true);
890 err = iavf_switch_queue_lv(adapter, tx_queue_id, false, true);
893 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
896 dev->data->tx_queue_state[tx_queue_id] =
897 RTE_ETH_QUEUE_STATE_STARTED;
903 iavf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
905 struct iavf_adapter *adapter =
906 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
907 struct iavf_rx_queue *rxq;
910 PMD_DRV_FUNC_TRACE();
912 if (rx_queue_id >= dev->data->nb_rx_queues)
915 err = iavf_switch_queue(adapter, rx_queue_id, true, false);
917 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
922 rxq = dev->data->rx_queues[rx_queue_id];
923 rxq->ops->release_mbufs(rxq);
925 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
931 iavf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
933 struct iavf_adapter *adapter =
934 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
935 struct iavf_tx_queue *txq;
938 PMD_DRV_FUNC_TRACE();
940 if (tx_queue_id >= dev->data->nb_tx_queues)
943 err = iavf_switch_queue(adapter, tx_queue_id, false, false);
945 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u off",
950 txq = dev->data->tx_queues[tx_queue_id];
951 txq->ops->release_mbufs(txq);
953 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
959 iavf_dev_rx_queue_release(void *rxq)
961 struct iavf_rx_queue *q = (struct iavf_rx_queue *)rxq;
966 q->ops->release_mbufs(q);
967 rte_free(q->sw_ring);
968 rte_memzone_free(q->mz);
973 iavf_dev_tx_queue_release(void *txq)
975 struct iavf_tx_queue *q = (struct iavf_tx_queue *)txq;
980 q->ops->release_mbufs(q);
981 rte_free(q->sw_ring);
982 rte_memzone_free(q->mz);
987 iavf_stop_queues(struct rte_eth_dev *dev)
989 struct iavf_adapter *adapter =
990 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
991 struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
992 struct iavf_rx_queue *rxq;
993 struct iavf_tx_queue *txq;
996 /* Stop All queues */
997 if (!vf->lv_enabled) {
998 ret = iavf_disable_queues(adapter);
1000 PMD_DRV_LOG(WARNING, "Fail to stop queues");
1002 ret = iavf_disable_queues_lv(adapter);
1004 PMD_DRV_LOG(WARNING, "Fail to stop queues for large VF");
1008 PMD_DRV_LOG(WARNING, "Fail to stop queues");
1010 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1011 txq = dev->data->tx_queues[i];
1014 txq->ops->release_mbufs(txq);
1015 reset_tx_queue(txq);
1016 dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED;
1018 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1019 rxq = dev->data->rx_queues[i];
1022 rxq->ops->release_mbufs(rxq);
1023 reset_rx_queue(rxq);
1024 dev->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED;
1028 #define IAVF_RX_FLEX_ERR0_BITS \
1029 ((1 << IAVF_RX_FLEX_DESC_STATUS0_HBO_S) | \
1030 (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_IPE_S) | \
1031 (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_L4E_S) | \
1032 (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S) | \
1033 (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S) | \
1034 (1 << IAVF_RX_FLEX_DESC_STATUS0_RXE_S))
1037 iavf_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union iavf_rx_desc *rxdp)
1039 if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1040 (1 << IAVF_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
1041 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1043 rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
1050 iavf_flex_rxd_to_vlan_tci(struct rte_mbuf *mb,
1051 volatile union iavf_rx_flex_desc *rxdp,
1054 uint16_t vlan_tci = 0;
1056 if (rx_flags & IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG1 &&
1057 rte_le_to_cpu_64(rxdp->wb.status_error0) &
1058 (1 << IAVF_RX_FLEX_DESC_STATUS0_L2TAG1P_S))
1059 vlan_tci = rte_le_to_cpu_16(rxdp->wb.l2tag1);
1061 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
1062 if (rx_flags & IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG2_2 &&
1063 rte_le_to_cpu_16(rxdp->wb.status_error1) &
1064 (1 << IAVF_RX_FLEX_DESC_STATUS1_L2TAG2P_S))
1065 vlan_tci = rte_le_to_cpu_16(rxdp->wb.l2tag2_2nd);
1069 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1070 mb->vlan_tci = vlan_tci;
1074 /* Translate the rx descriptor status and error fields to pkt flags */
1075 static inline uint64_t
1076 iavf_rxd_to_pkt_flags(uint64_t qword)
1079 uint64_t error_bits = (qword >> IAVF_RXD_QW1_ERROR_SHIFT);
1081 #define IAVF_RX_ERR_BITS 0x3f
1083 /* Check if RSS_HASH */
1084 flags = (((qword >> IAVF_RX_DESC_STATUS_FLTSTAT_SHIFT) &
1085 IAVF_RX_DESC_FLTSTAT_RSS_HASH) ==
1086 IAVF_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;
1088 /* Check if FDIR Match */
1089 flags |= (qword & (1 << IAVF_RX_DESC_STATUS_FLM_SHIFT) ?
1092 if (likely((error_bits & IAVF_RX_ERR_BITS) == 0)) {
1093 flags |= (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD);
1097 if (unlikely(error_bits & (1 << IAVF_RX_DESC_ERROR_IPE_SHIFT)))
1098 flags |= PKT_RX_IP_CKSUM_BAD;
1100 flags |= PKT_RX_IP_CKSUM_GOOD;
1102 if (unlikely(error_bits & (1 << IAVF_RX_DESC_ERROR_L4E_SHIFT)))
1103 flags |= PKT_RX_L4_CKSUM_BAD;
1105 flags |= PKT_RX_L4_CKSUM_GOOD;
1107 /* TODO: Oversize error bit is not processed here */
1112 static inline uint64_t
1113 iavf_rxd_build_fdir(volatile union iavf_rx_desc *rxdp, struct rte_mbuf *mb)
1116 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
1119 flexbh = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
1120 IAVF_RX_DESC_EXT_STATUS_FLEXBH_SHIFT) &
1121 IAVF_RX_DESC_EXT_STATUS_FLEXBH_MASK;
1123 if (flexbh == IAVF_RX_DESC_EXT_STATUS_FLEXBH_FD_ID) {
1125 rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.fd_id);
1126 flags |= PKT_RX_FDIR_ID;
1130 rte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.fd_id);
1131 flags |= PKT_RX_FDIR_ID;
1136 #define IAVF_RX_FLEX_ERR0_BITS \
1137 ((1 << IAVF_RX_FLEX_DESC_STATUS0_HBO_S) | \
1138 (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_IPE_S) | \
1139 (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_L4E_S) | \
1140 (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S) | \
1141 (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S) | \
1142 (1 << IAVF_RX_FLEX_DESC_STATUS0_RXE_S))
1144 /* Rx L3/L4 checksum */
1145 static inline uint64_t
1146 iavf_flex_rxd_error_to_pkt_flags(uint16_t stat_err0)
1150 /* check if HW has decoded the packet and checksum */
1151 if (unlikely(!(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_L3L4P_S))))
1154 if (likely(!(stat_err0 & IAVF_RX_FLEX_ERR0_BITS))) {
1155 flags |= (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD);
1159 if (unlikely(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_IPE_S)))
1160 flags |= PKT_RX_IP_CKSUM_BAD;
1162 flags |= PKT_RX_IP_CKSUM_GOOD;
1164 if (unlikely(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_L4E_S)))
1165 flags |= PKT_RX_L4_CKSUM_BAD;
1167 flags |= PKT_RX_L4_CKSUM_GOOD;
1169 if (unlikely(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S)))
1170 flags |= PKT_RX_OUTER_IP_CKSUM_BAD;
1175 /* If the number of free RX descriptors is greater than the RX free
1176 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1177 * register. Update the RDT with the value of the last processed RX
1178 * descriptor minus 1, to guarantee that the RDT register is never
1179 * equal to the RDH register, which creates a "full" ring situation
1180 * from the hardware point of view.
1183 iavf_update_rx_tail(struct iavf_rx_queue *rxq, uint16_t nb_hold, uint16_t rx_id)
1185 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1187 if (nb_hold > rxq->rx_free_thresh) {
1189 "port_id=%u queue_id=%u rx_tail=%u nb_hold=%u",
1190 rxq->port_id, rxq->queue_id, rx_id, nb_hold);
1191 rx_id = (uint16_t)((rx_id == 0) ?
1192 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1193 IAVF_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
1196 rxq->nb_rx_hold = nb_hold;
1199 /* implement recv_pkts */
1201 iavf_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1203 volatile union iavf_rx_desc *rx_ring;
1204 volatile union iavf_rx_desc *rxdp;
1205 struct iavf_rx_queue *rxq;
1206 union iavf_rx_desc rxd;
1207 struct rte_mbuf *rxe;
1208 struct rte_eth_dev *dev;
1209 struct rte_mbuf *rxm;
1210 struct rte_mbuf *nmb;
1214 uint16_t rx_packet_len;
1215 uint16_t rx_id, nb_hold;
1218 const uint32_t *ptype_tbl;
1223 rx_id = rxq->rx_tail;
1224 rx_ring = rxq->rx_ring;
1225 ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1227 while (nb_rx < nb_pkts) {
1228 rxdp = &rx_ring[rx_id];
1229 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1230 rx_status = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
1231 IAVF_RXD_QW1_STATUS_SHIFT;
1233 /* Check the DD bit first */
1234 if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)))
1236 IAVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
1238 nmb = rte_mbuf_raw_alloc(rxq->mp);
1239 if (unlikely(!nmb)) {
1240 dev = &rte_eth_devices[rxq->port_id];
1241 dev->data->rx_mbuf_alloc_failed++;
1242 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1243 "queue_id=%u", rxq->port_id, rxq->queue_id);
1249 rxe = rxq->sw_ring[rx_id];
1250 rxq->sw_ring[rx_id] = nmb;
1252 if (unlikely(rx_id == rxq->nb_rx_desc))
1255 /* Prefetch next mbuf */
1256 rte_prefetch0(rxq->sw_ring[rx_id]);
1258 /* When next RX descriptor is on a cache line boundary,
1259 * prefetch the next 4 RX descriptors and next 8 pointers
1262 if ((rx_id & 0x3) == 0) {
1263 rte_prefetch0(&rx_ring[rx_id]);
1264 rte_prefetch0(rxq->sw_ring[rx_id]);
1268 rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1269 rxdp->read.hdr_addr = 0;
1270 rxdp->read.pkt_addr = dma_addr;
1272 rx_packet_len = ((qword1 & IAVF_RXD_QW1_LENGTH_PBUF_MASK) >>
1273 IAVF_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
1275 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1276 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
1279 rxm->pkt_len = rx_packet_len;
1280 rxm->data_len = rx_packet_len;
1281 rxm->port = rxq->port_id;
1283 iavf_rxd_to_vlan_tci(rxm, &rxd);
1284 pkt_flags = iavf_rxd_to_pkt_flags(qword1);
1286 ptype_tbl[(uint8_t)((qword1 &
1287 IAVF_RXD_QW1_PTYPE_MASK) >> IAVF_RXD_QW1_PTYPE_SHIFT)];
1289 if (pkt_flags & PKT_RX_RSS_HASH)
1291 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1293 if (pkt_flags & PKT_RX_FDIR)
1294 pkt_flags |= iavf_rxd_build_fdir(&rxd, rxm);
1296 rxm->ol_flags |= pkt_flags;
1298 rx_pkts[nb_rx++] = rxm;
1300 rxq->rx_tail = rx_id;
1302 iavf_update_rx_tail(rxq, nb_hold, rx_id);
1307 /* implement recv_pkts for flexible Rx descriptor */
1309 iavf_recv_pkts_flex_rxd(void *rx_queue,
1310 struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1312 volatile union iavf_rx_desc *rx_ring;
1313 volatile union iavf_rx_flex_desc *rxdp;
1314 struct iavf_rx_queue *rxq;
1315 union iavf_rx_flex_desc rxd;
1316 struct rte_mbuf *rxe;
1317 struct rte_eth_dev *dev;
1318 struct rte_mbuf *rxm;
1319 struct rte_mbuf *nmb;
1321 uint16_t rx_stat_err0;
1322 uint16_t rx_packet_len;
1323 uint16_t rx_id, nb_hold;
1326 const uint32_t *ptype_tbl;
1331 rx_id = rxq->rx_tail;
1332 rx_ring = rxq->rx_ring;
1333 ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1335 while (nb_rx < nb_pkts) {
1336 rxdp = (volatile union iavf_rx_flex_desc *)&rx_ring[rx_id];
1337 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1339 /* Check the DD bit first */
1340 if (!(rx_stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S)))
1342 IAVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
1344 nmb = rte_mbuf_raw_alloc(rxq->mp);
1345 if (unlikely(!nmb)) {
1346 dev = &rte_eth_devices[rxq->port_id];
1347 dev->data->rx_mbuf_alloc_failed++;
1348 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1349 "queue_id=%u", rxq->port_id, rxq->queue_id);
1355 rxe = rxq->sw_ring[rx_id];
1356 rxq->sw_ring[rx_id] = nmb;
1358 if (unlikely(rx_id == rxq->nb_rx_desc))
1361 /* Prefetch next mbuf */
1362 rte_prefetch0(rxq->sw_ring[rx_id]);
1364 /* When next RX descriptor is on a cache line boundary,
1365 * prefetch the next 4 RX descriptors and next 8 pointers
1368 if ((rx_id & 0x3) == 0) {
1369 rte_prefetch0(&rx_ring[rx_id]);
1370 rte_prefetch0(rxq->sw_ring[rx_id]);
1374 rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1375 rxdp->read.hdr_addr = 0;
1376 rxdp->read.pkt_addr = dma_addr;
1378 rx_packet_len = (rte_le_to_cpu_16(rxd.wb.pkt_len) &
1379 IAVF_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
1381 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1382 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
1385 rxm->pkt_len = rx_packet_len;
1386 rxm->data_len = rx_packet_len;
1387 rxm->port = rxq->port_id;
1389 rxm->packet_type = ptype_tbl[IAVF_RX_FLEX_DESC_PTYPE_M &
1390 rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
1391 iavf_flex_rxd_to_vlan_tci(rxm, &rxd, rxq->rx_flags);
1392 rxq->rxd_to_pkt_fields(rxq, rxm, &rxd);
1393 pkt_flags = iavf_flex_rxd_error_to_pkt_flags(rx_stat_err0);
1394 rxm->ol_flags |= pkt_flags;
1396 rx_pkts[nb_rx++] = rxm;
1398 rxq->rx_tail = rx_id;
1400 iavf_update_rx_tail(rxq, nb_hold, rx_id);
1405 /* implement recv_scattered_pkts for flexible Rx descriptor */
1407 iavf_recv_scattered_pkts_flex_rxd(void *rx_queue, struct rte_mbuf **rx_pkts,
1410 struct iavf_rx_queue *rxq = rx_queue;
1411 union iavf_rx_flex_desc rxd;
1412 struct rte_mbuf *rxe;
1413 struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1414 struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1415 struct rte_mbuf *nmb, *rxm;
1416 uint16_t rx_id = rxq->rx_tail;
1417 uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
1418 struct rte_eth_dev *dev;
1419 uint16_t rx_stat_err0;
1423 volatile union iavf_rx_desc *rx_ring = rxq->rx_ring;
1424 volatile union iavf_rx_flex_desc *rxdp;
1425 const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1427 while (nb_rx < nb_pkts) {
1428 rxdp = (volatile union iavf_rx_flex_desc *)&rx_ring[rx_id];
1429 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1431 /* Check the DD bit */
1432 if (!(rx_stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S)))
1434 IAVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
1436 nmb = rte_mbuf_raw_alloc(rxq->mp);
1437 if (unlikely(!nmb)) {
1438 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1439 "queue_id=%u", rxq->port_id, rxq->queue_id);
1440 dev = &rte_eth_devices[rxq->port_id];
1441 dev->data->rx_mbuf_alloc_failed++;
1447 rxe = rxq->sw_ring[rx_id];
1448 rxq->sw_ring[rx_id] = nmb;
1450 if (rx_id == rxq->nb_rx_desc)
1453 /* Prefetch next mbuf */
1454 rte_prefetch0(rxq->sw_ring[rx_id]);
1456 /* When next RX descriptor is on a cache line boundary,
1457 * prefetch the next 4 RX descriptors and next 8 pointers
1460 if ((rx_id & 0x3) == 0) {
1461 rte_prefetch0(&rx_ring[rx_id]);
1462 rte_prefetch0(rxq->sw_ring[rx_id]);
1467 rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1469 /* Set data buffer address and data length of the mbuf */
1470 rxdp->read.hdr_addr = 0;
1471 rxdp->read.pkt_addr = dma_addr;
1472 rx_packet_len = rte_le_to_cpu_16(rxd.wb.pkt_len) &
1473 IAVF_RX_FLX_DESC_PKT_LEN_M;
1474 rxm->data_len = rx_packet_len;
1475 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1477 /* If this is the first buffer of the received packet, set the
1478 * pointer to the first mbuf of the packet and initialize its
1479 * context. Otherwise, update the total length and the number
1480 * of segments of the current scattered packet, and update the
1481 * pointer to the last mbuf of the current packet.
1485 first_seg->nb_segs = 1;
1486 first_seg->pkt_len = rx_packet_len;
1488 first_seg->pkt_len =
1489 (uint16_t)(first_seg->pkt_len +
1491 first_seg->nb_segs++;
1492 last_seg->next = rxm;
1495 /* If this is not the last buffer of the received packet,
1496 * update the pointer to the last mbuf of the current scattered
1497 * packet and continue to parse the RX ring.
1499 if (!(rx_stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_EOF_S))) {
1504 /* This is the last buffer of the received packet. If the CRC
1505 * is not stripped by the hardware:
1506 * - Subtract the CRC length from the total packet length.
1507 * - If the last buffer only contains the whole CRC or a part
1508 * of it, free the mbuf associated to the last buffer. If part
1509 * of the CRC is also contained in the previous mbuf, subtract
1510 * the length of that CRC part from the data length of the
1514 if (unlikely(rxq->crc_len > 0)) {
1515 first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
1516 if (rx_packet_len <= RTE_ETHER_CRC_LEN) {
1517 rte_pktmbuf_free_seg(rxm);
1518 first_seg->nb_segs--;
1519 last_seg->data_len =
1520 (uint16_t)(last_seg->data_len -
1521 (RTE_ETHER_CRC_LEN - rx_packet_len));
1522 last_seg->next = NULL;
1524 rxm->data_len = (uint16_t)(rx_packet_len -
1529 first_seg->port = rxq->port_id;
1530 first_seg->ol_flags = 0;
1531 first_seg->packet_type = ptype_tbl[IAVF_RX_FLEX_DESC_PTYPE_M &
1532 rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
1533 iavf_flex_rxd_to_vlan_tci(first_seg, &rxd, rxq->rx_flags);
1534 rxq->rxd_to_pkt_fields(rxq, first_seg, &rxd);
1535 pkt_flags = iavf_flex_rxd_error_to_pkt_flags(rx_stat_err0);
1537 first_seg->ol_flags |= pkt_flags;
1539 /* Prefetch data of first segment, if configured to do so. */
1540 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1541 first_seg->data_off));
1542 rx_pkts[nb_rx++] = first_seg;
1546 /* Record index of the next RX descriptor to probe. */
1547 rxq->rx_tail = rx_id;
1548 rxq->pkt_first_seg = first_seg;
1549 rxq->pkt_last_seg = last_seg;
1551 iavf_update_rx_tail(rxq, nb_hold, rx_id);
1556 /* implement recv_scattered_pkts */
1558 iavf_recv_scattered_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1561 struct iavf_rx_queue *rxq = rx_queue;
1562 union iavf_rx_desc rxd;
1563 struct rte_mbuf *rxe;
1564 struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1565 struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1566 struct rte_mbuf *nmb, *rxm;
1567 uint16_t rx_id = rxq->rx_tail;
1568 uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
1569 struct rte_eth_dev *dev;
1575 volatile union iavf_rx_desc *rx_ring = rxq->rx_ring;
1576 volatile union iavf_rx_desc *rxdp;
1577 const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1579 while (nb_rx < nb_pkts) {
1580 rxdp = &rx_ring[rx_id];
1581 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1582 rx_status = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
1583 IAVF_RXD_QW1_STATUS_SHIFT;
1585 /* Check the DD bit */
1586 if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)))
1588 IAVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
1590 nmb = rte_mbuf_raw_alloc(rxq->mp);
1591 if (unlikely(!nmb)) {
1592 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1593 "queue_id=%u", rxq->port_id, rxq->queue_id);
1594 dev = &rte_eth_devices[rxq->port_id];
1595 dev->data->rx_mbuf_alloc_failed++;
1601 rxe = rxq->sw_ring[rx_id];
1602 rxq->sw_ring[rx_id] = nmb;
1604 if (rx_id == rxq->nb_rx_desc)
1607 /* Prefetch next mbuf */
1608 rte_prefetch0(rxq->sw_ring[rx_id]);
1610 /* When next RX descriptor is on a cache line boundary,
1611 * prefetch the next 4 RX descriptors and next 8 pointers
1614 if ((rx_id & 0x3) == 0) {
1615 rte_prefetch0(&rx_ring[rx_id]);
1616 rte_prefetch0(rxq->sw_ring[rx_id]);
1621 rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1623 /* Set data buffer address and data length of the mbuf */
1624 rxdp->read.hdr_addr = 0;
1625 rxdp->read.pkt_addr = dma_addr;
1626 rx_packet_len = (qword1 & IAVF_RXD_QW1_LENGTH_PBUF_MASK) >>
1627 IAVF_RXD_QW1_LENGTH_PBUF_SHIFT;
1628 rxm->data_len = rx_packet_len;
1629 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1631 /* If this is the first buffer of the received packet, set the
1632 * pointer to the first mbuf of the packet and initialize its
1633 * context. Otherwise, update the total length and the number
1634 * of segments of the current scattered packet, and update the
1635 * pointer to the last mbuf of the current packet.
1639 first_seg->nb_segs = 1;
1640 first_seg->pkt_len = rx_packet_len;
1642 first_seg->pkt_len =
1643 (uint16_t)(first_seg->pkt_len +
1645 first_seg->nb_segs++;
1646 last_seg->next = rxm;
1649 /* If this is not the last buffer of the received packet,
1650 * update the pointer to the last mbuf of the current scattered
1651 * packet and continue to parse the RX ring.
1653 if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_EOF_SHIFT))) {
1658 /* This is the last buffer of the received packet. If the CRC
1659 * is not stripped by the hardware:
1660 * - Subtract the CRC length from the total packet length.
1661 * - If the last buffer only contains the whole CRC or a part
1662 * of it, free the mbuf associated to the last buffer. If part
1663 * of the CRC is also contained in the previous mbuf, subtract
1664 * the length of that CRC part from the data length of the
1668 if (unlikely(rxq->crc_len > 0)) {
1669 first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
1670 if (rx_packet_len <= RTE_ETHER_CRC_LEN) {
1671 rte_pktmbuf_free_seg(rxm);
1672 first_seg->nb_segs--;
1673 last_seg->data_len =
1674 (uint16_t)(last_seg->data_len -
1675 (RTE_ETHER_CRC_LEN - rx_packet_len));
1676 last_seg->next = NULL;
1678 rxm->data_len = (uint16_t)(rx_packet_len -
1682 first_seg->port = rxq->port_id;
1683 first_seg->ol_flags = 0;
1684 iavf_rxd_to_vlan_tci(first_seg, &rxd);
1685 pkt_flags = iavf_rxd_to_pkt_flags(qword1);
1686 first_seg->packet_type =
1687 ptype_tbl[(uint8_t)((qword1 &
1688 IAVF_RXD_QW1_PTYPE_MASK) >> IAVF_RXD_QW1_PTYPE_SHIFT)];
1690 if (pkt_flags & PKT_RX_RSS_HASH)
1691 first_seg->hash.rss =
1692 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1694 if (pkt_flags & PKT_RX_FDIR)
1695 pkt_flags |= iavf_rxd_build_fdir(&rxd, first_seg);
1697 first_seg->ol_flags |= pkt_flags;
1699 /* Prefetch data of first segment, if configured to do so. */
1700 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1701 first_seg->data_off));
1702 rx_pkts[nb_rx++] = first_seg;
1706 /* Record index of the next RX descriptor to probe. */
1707 rxq->rx_tail = rx_id;
1708 rxq->pkt_first_seg = first_seg;
1709 rxq->pkt_last_seg = last_seg;
1711 iavf_update_rx_tail(rxq, nb_hold, rx_id);
1716 #define IAVF_LOOK_AHEAD 8
1718 iavf_rx_scan_hw_ring_flex_rxd(struct iavf_rx_queue *rxq)
1720 volatile union iavf_rx_flex_desc *rxdp;
1721 struct rte_mbuf **rxep;
1722 struct rte_mbuf *mb;
1725 int32_t s[IAVF_LOOK_AHEAD], nb_dd;
1726 int32_t i, j, nb_rx = 0;
1728 const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1730 rxdp = (volatile union iavf_rx_flex_desc *)&rxq->rx_ring[rxq->rx_tail];
1731 rxep = &rxq->sw_ring[rxq->rx_tail];
1733 stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1735 /* Make sure there is at least 1 packet to receive */
1736 if (!(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S)))
1739 /* Scan LOOK_AHEAD descriptors at a time to determine which
1740 * descriptors reference packets that are ready to be received.
1742 for (i = 0; i < IAVF_RX_MAX_BURST; i += IAVF_LOOK_AHEAD,
1743 rxdp += IAVF_LOOK_AHEAD, rxep += IAVF_LOOK_AHEAD) {
1744 /* Read desc statuses backwards to avoid race condition */
1745 for (j = IAVF_LOOK_AHEAD - 1; j >= 0; j--)
1746 s[j] = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1750 /* Compute how many status bits were set */
1751 for (j = 0, nb_dd = 0; j < IAVF_LOOK_AHEAD; j++)
1752 nb_dd += s[j] & (1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S);
1756 /* Translate descriptor info to mbuf parameters */
1757 for (j = 0; j < nb_dd; j++) {
1758 IAVF_DUMP_RX_DESC(rxq, &rxdp[j],
1760 i * IAVF_LOOK_AHEAD + j);
1763 pkt_len = (rte_le_to_cpu_16(rxdp[j].wb.pkt_len) &
1764 IAVF_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
1765 mb->data_len = pkt_len;
1766 mb->pkt_len = pkt_len;
1769 mb->packet_type = ptype_tbl[IAVF_RX_FLEX_DESC_PTYPE_M &
1770 rte_le_to_cpu_16(rxdp[j].wb.ptype_flex_flags0)];
1771 iavf_flex_rxd_to_vlan_tci(mb, &rxdp[j], rxq->rx_flags);
1772 rxq->rxd_to_pkt_fields(rxq, mb, &rxdp[j]);
1773 stat_err0 = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1774 pkt_flags = iavf_flex_rxd_error_to_pkt_flags(stat_err0);
1776 mb->ol_flags |= pkt_flags;
1779 for (j = 0; j < IAVF_LOOK_AHEAD; j++)
1780 rxq->rx_stage[i + j] = rxep[j];
1782 if (nb_dd != IAVF_LOOK_AHEAD)
1786 /* Clear software ring entries */
1787 for (i = 0; i < nb_rx; i++)
1788 rxq->sw_ring[rxq->rx_tail + i] = NULL;
1794 iavf_rx_scan_hw_ring(struct iavf_rx_queue *rxq)
1796 volatile union iavf_rx_desc *rxdp;
1797 struct rte_mbuf **rxep;
1798 struct rte_mbuf *mb;
1802 int32_t s[IAVF_LOOK_AHEAD], nb_dd;
1803 int32_t i, j, nb_rx = 0;
1805 const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1807 rxdp = &rxq->rx_ring[rxq->rx_tail];
1808 rxep = &rxq->sw_ring[rxq->rx_tail];
1810 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1811 rx_status = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
1812 IAVF_RXD_QW1_STATUS_SHIFT;
1814 /* Make sure there is at least 1 packet to receive */
1815 if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)))
1818 /* Scan LOOK_AHEAD descriptors at a time to determine which
1819 * descriptors reference packets that are ready to be received.
1821 for (i = 0; i < IAVF_RX_MAX_BURST; i += IAVF_LOOK_AHEAD,
1822 rxdp += IAVF_LOOK_AHEAD, rxep += IAVF_LOOK_AHEAD) {
1823 /* Read desc statuses backwards to avoid race condition */
1824 for (j = IAVF_LOOK_AHEAD - 1; j >= 0; j--) {
1825 qword1 = rte_le_to_cpu_64(
1826 rxdp[j].wb.qword1.status_error_len);
1827 s[j] = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
1828 IAVF_RXD_QW1_STATUS_SHIFT;
1833 /* Compute how many status bits were set */
1834 for (j = 0, nb_dd = 0; j < IAVF_LOOK_AHEAD; j++)
1835 nb_dd += s[j] & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT);
1839 /* Translate descriptor info to mbuf parameters */
1840 for (j = 0; j < nb_dd; j++) {
1841 IAVF_DUMP_RX_DESC(rxq, &rxdp[j],
1842 rxq->rx_tail + i * IAVF_LOOK_AHEAD + j);
1845 qword1 = rte_le_to_cpu_64
1846 (rxdp[j].wb.qword1.status_error_len);
1847 pkt_len = ((qword1 & IAVF_RXD_QW1_LENGTH_PBUF_MASK) >>
1848 IAVF_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
1849 mb->data_len = pkt_len;
1850 mb->pkt_len = pkt_len;
1852 iavf_rxd_to_vlan_tci(mb, &rxdp[j]);
1853 pkt_flags = iavf_rxd_to_pkt_flags(qword1);
1855 ptype_tbl[(uint8_t)((qword1 &
1856 IAVF_RXD_QW1_PTYPE_MASK) >>
1857 IAVF_RXD_QW1_PTYPE_SHIFT)];
1859 if (pkt_flags & PKT_RX_RSS_HASH)
1860 mb->hash.rss = rte_le_to_cpu_32(
1861 rxdp[j].wb.qword0.hi_dword.rss);
1863 if (pkt_flags & PKT_RX_FDIR)
1864 pkt_flags |= iavf_rxd_build_fdir(&rxdp[j], mb);
1866 mb->ol_flags |= pkt_flags;
1869 for (j = 0; j < IAVF_LOOK_AHEAD; j++)
1870 rxq->rx_stage[i + j] = rxep[j];
1872 if (nb_dd != IAVF_LOOK_AHEAD)
1876 /* Clear software ring entries */
1877 for (i = 0; i < nb_rx; i++)
1878 rxq->sw_ring[rxq->rx_tail + i] = NULL;
1883 static inline uint16_t
1884 iavf_rx_fill_from_stage(struct iavf_rx_queue *rxq,
1885 struct rte_mbuf **rx_pkts,
1889 struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1891 nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1893 for (i = 0; i < nb_pkts; i++)
1894 rx_pkts[i] = stage[i];
1896 rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1897 rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1903 iavf_rx_alloc_bufs(struct iavf_rx_queue *rxq)
1905 volatile union iavf_rx_desc *rxdp;
1906 struct rte_mbuf **rxep;
1907 struct rte_mbuf *mb;
1908 uint16_t alloc_idx, i;
1912 /* Allocate buffers in bulk */
1913 alloc_idx = (uint16_t)(rxq->rx_free_trigger -
1914 (rxq->rx_free_thresh - 1));
1915 rxep = &rxq->sw_ring[alloc_idx];
1916 diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
1917 rxq->rx_free_thresh);
1918 if (unlikely(diag != 0)) {
1919 PMD_RX_LOG(ERR, "Failed to get mbufs in bulk");
1923 rxdp = &rxq->rx_ring[alloc_idx];
1924 for (i = 0; i < rxq->rx_free_thresh; i++) {
1925 if (likely(i < (rxq->rx_free_thresh - 1)))
1926 /* Prefetch next mbuf */
1927 rte_prefetch0(rxep[i + 1]);
1930 rte_mbuf_refcnt_set(mb, 1);
1932 mb->data_off = RTE_PKTMBUF_HEADROOM;
1934 mb->port = rxq->port_id;
1935 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mb));
1936 rxdp[i].read.hdr_addr = 0;
1937 rxdp[i].read.pkt_addr = dma_addr;
1940 /* Update rx tail register */
1942 IAVF_PCI_REG_WC_WRITE_RELAXED(rxq->qrx_tail, rxq->rx_free_trigger);
1944 rxq->rx_free_trigger =
1945 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
1946 if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1947 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
1952 static inline uint16_t
1953 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1955 struct iavf_rx_queue *rxq = (struct iavf_rx_queue *)rx_queue;
1961 if (rxq->rx_nb_avail)
1962 return iavf_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1964 if (rxq->rxdid >= IAVF_RXDID_FLEX_NIC && rxq->rxdid <= IAVF_RXDID_LAST)
1965 nb_rx = (uint16_t)iavf_rx_scan_hw_ring_flex_rxd(rxq);
1967 nb_rx = (uint16_t)iavf_rx_scan_hw_ring(rxq);
1968 rxq->rx_next_avail = 0;
1969 rxq->rx_nb_avail = nb_rx;
1970 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1972 if (rxq->rx_tail > rxq->rx_free_trigger) {
1973 if (iavf_rx_alloc_bufs(rxq) != 0) {
1976 /* TODO: count rx_mbuf_alloc_failed here */
1978 rxq->rx_nb_avail = 0;
1979 rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1980 for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
1981 rxq->sw_ring[j] = rxq->rx_stage[i];
1987 if (rxq->rx_tail >= rxq->nb_rx_desc)
1990 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u, nb_rx=%u",
1991 rxq->port_id, rxq->queue_id,
1992 rxq->rx_tail, nb_rx);
1994 if (rxq->rx_nb_avail)
1995 return iavf_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
2001 iavf_recv_pkts_bulk_alloc(void *rx_queue,
2002 struct rte_mbuf **rx_pkts,
2005 uint16_t nb_rx = 0, n, count;
2007 if (unlikely(nb_pkts == 0))
2010 if (likely(nb_pkts <= IAVF_RX_MAX_BURST))
2011 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
2014 n = RTE_MIN(nb_pkts, IAVF_RX_MAX_BURST);
2015 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
2016 nb_rx = (uint16_t)(nb_rx + count);
2017 nb_pkts = (uint16_t)(nb_pkts - count);
2026 iavf_xmit_cleanup(struct iavf_tx_queue *txq)
2028 struct iavf_tx_entry *sw_ring = txq->sw_ring;
2029 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
2030 uint16_t nb_tx_desc = txq->nb_tx_desc;
2031 uint16_t desc_to_clean_to;
2032 uint16_t nb_tx_to_clean;
2034 volatile struct iavf_tx_desc *txd = txq->tx_ring;
2036 desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->rs_thresh);
2037 if (desc_to_clean_to >= nb_tx_desc)
2038 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
2040 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
2041 if ((txd[desc_to_clean_to].cmd_type_offset_bsz &
2042 rte_cpu_to_le_64(IAVF_TXD_QW1_DTYPE_MASK)) !=
2043 rte_cpu_to_le_64(IAVF_TX_DESC_DTYPE_DESC_DONE)) {
2044 PMD_TX_LOG(DEBUG, "TX descriptor %4u is not done "
2045 "(port=%d queue=%d)", desc_to_clean_to,
2046 txq->port_id, txq->queue_id);
2050 if (last_desc_cleaned > desc_to_clean_to)
2051 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
2054 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
2057 txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
2059 txq->last_desc_cleaned = desc_to_clean_to;
2060 txq->nb_free = (uint16_t)(txq->nb_free + nb_tx_to_clean);
2065 /* Check if the context descriptor is needed for TX offloading */
2066 static inline uint16_t
2067 iavf_calc_context_desc(uint64_t flags, uint8_t vlan_flag)
2069 if (flags & PKT_TX_TCP_SEG)
2071 if (flags & PKT_TX_VLAN_PKT &&
2072 vlan_flag & IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG2)
2078 iavf_txd_enable_checksum(uint64_t ol_flags,
2080 uint32_t *td_offset,
2081 union iavf_tx_offload tx_offload)
2084 *td_offset |= (tx_offload.l2_len >> 1) <<
2085 IAVF_TX_DESC_LENGTH_MACLEN_SHIFT;
2087 /* Enable L3 checksum offloads */
2088 if (ol_flags & PKT_TX_IP_CKSUM) {
2089 *td_cmd |= IAVF_TX_DESC_CMD_IIPT_IPV4_CSUM;
2090 *td_offset |= (tx_offload.l3_len >> 2) <<
2091 IAVF_TX_DESC_LENGTH_IPLEN_SHIFT;
2092 } else if (ol_flags & PKT_TX_IPV4) {
2093 *td_cmd |= IAVF_TX_DESC_CMD_IIPT_IPV4;
2094 *td_offset |= (tx_offload.l3_len >> 2) <<
2095 IAVF_TX_DESC_LENGTH_IPLEN_SHIFT;
2096 } else if (ol_flags & PKT_TX_IPV6) {
2097 *td_cmd |= IAVF_TX_DESC_CMD_IIPT_IPV6;
2098 *td_offset |= (tx_offload.l3_len >> 2) <<
2099 IAVF_TX_DESC_LENGTH_IPLEN_SHIFT;
2102 if (ol_flags & PKT_TX_TCP_SEG) {
2103 *td_cmd |= IAVF_TX_DESC_CMD_L4T_EOFT_TCP;
2104 *td_offset |= (tx_offload.l4_len >> 2) <<
2105 IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2109 /* Enable L4 checksum offloads */
2110 switch (ol_flags & PKT_TX_L4_MASK) {
2111 case PKT_TX_TCP_CKSUM:
2112 *td_cmd |= IAVF_TX_DESC_CMD_L4T_EOFT_TCP;
2113 *td_offset |= (sizeof(struct rte_tcp_hdr) >> 2) <<
2114 IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2116 case PKT_TX_SCTP_CKSUM:
2117 *td_cmd |= IAVF_TX_DESC_CMD_L4T_EOFT_SCTP;
2118 *td_offset |= (sizeof(struct rte_sctp_hdr) >> 2) <<
2119 IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2121 case PKT_TX_UDP_CKSUM:
2122 *td_cmd |= IAVF_TX_DESC_CMD_L4T_EOFT_UDP;
2123 *td_offset |= (sizeof(struct rte_udp_hdr) >> 2) <<
2124 IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2131 /* set TSO context descriptor
2132 * support IP -> L4 and IP -> IP -> L4
2134 static inline uint64_t
2135 iavf_set_tso_ctx(struct rte_mbuf *mbuf, union iavf_tx_offload tx_offload)
2137 uint64_t ctx_desc = 0;
2138 uint32_t cd_cmd, hdr_len, cd_tso_len;
2140 if (!tx_offload.l4_len) {
2141 PMD_TX_LOG(DEBUG, "L4 length set to 0");
2145 hdr_len = tx_offload.l2_len +
2149 cd_cmd = IAVF_TX_CTX_DESC_TSO;
2150 cd_tso_len = mbuf->pkt_len - hdr_len;
2151 ctx_desc |= ((uint64_t)cd_cmd << IAVF_TXD_CTX_QW1_CMD_SHIFT) |
2152 ((uint64_t)cd_tso_len << IAVF_TXD_CTX_QW1_TSO_LEN_SHIFT) |
2153 ((uint64_t)mbuf->tso_segsz << IAVF_TXD_CTX_QW1_MSS_SHIFT);
2158 /* Construct the tx flags */
2159 static inline uint64_t
2160 iavf_build_ctob(uint32_t td_cmd, uint32_t td_offset, unsigned int size,
2163 return rte_cpu_to_le_64(IAVF_TX_DESC_DTYPE_DATA |
2164 ((uint64_t)td_cmd << IAVF_TXD_QW1_CMD_SHIFT) |
2165 ((uint64_t)td_offset <<
2166 IAVF_TXD_QW1_OFFSET_SHIFT) |
2168 IAVF_TXD_QW1_TX_BUF_SZ_SHIFT) |
2169 ((uint64_t)td_tag <<
2170 IAVF_TXD_QW1_L2TAG1_SHIFT));
2175 iavf_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2177 volatile struct iavf_tx_desc *txd;
2178 volatile struct iavf_tx_desc *txr;
2179 struct iavf_tx_queue *txq;
2180 struct iavf_tx_entry *sw_ring;
2181 struct iavf_tx_entry *txe, *txn;
2182 struct rte_mbuf *tx_pkt;
2183 struct rte_mbuf *m_seg;
2194 uint64_t buf_dma_addr;
2195 uint16_t cd_l2tag2 = 0;
2196 union iavf_tx_offload tx_offload = {0};
2199 sw_ring = txq->sw_ring;
2201 tx_id = txq->tx_tail;
2202 txe = &sw_ring[tx_id];
2204 /* Check if the descriptor ring needs to be cleaned. */
2205 if (txq->nb_free < txq->free_thresh)
2206 (void)iavf_xmit_cleanup(txq);
2208 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
2213 tx_pkt = *tx_pkts++;
2214 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
2216 ol_flags = tx_pkt->ol_flags;
2217 tx_offload.l2_len = tx_pkt->l2_len;
2218 tx_offload.l3_len = tx_pkt->l3_len;
2219 tx_offload.l4_len = tx_pkt->l4_len;
2220 tx_offload.tso_segsz = tx_pkt->tso_segsz;
2221 /* Calculate the number of context descriptors needed. */
2222 nb_ctx = iavf_calc_context_desc(ol_flags, txq->vlan_flag);
2224 /* The number of descriptors that must be allocated for
2225 * a packet equals to the number of the segments of that
2226 * packet plus 1 context descriptor if needed.
2228 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
2229 tx_last = (uint16_t)(tx_id + nb_used - 1);
2232 if (tx_last >= txq->nb_tx_desc)
2233 tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
2235 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u"
2236 " tx_first=%u tx_last=%u",
2237 txq->port_id, txq->queue_id, tx_id, tx_last);
2239 if (nb_used > txq->nb_free) {
2240 if (iavf_xmit_cleanup(txq)) {
2245 if (unlikely(nb_used > txq->rs_thresh)) {
2246 while (nb_used > txq->nb_free) {
2247 if (iavf_xmit_cleanup(txq)) {
2256 /* Descriptor based VLAN insertion */
2257 if (ol_flags & PKT_TX_VLAN_PKT &&
2258 txq->vlan_flag & IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG1) {
2259 td_cmd |= IAVF_TX_DESC_CMD_IL2TAG1;
2260 td_tag = tx_pkt->vlan_tci;
2263 /* According to datasheet, the bit2 is reserved and must be
2268 /* Enable checksum offloading */
2269 if (ol_flags & IAVF_TX_CKSUM_OFFLOAD_MASK)
2270 iavf_txd_enable_checksum(ol_flags, &td_cmd,
2271 &td_offset, tx_offload);
2274 /* Setup TX context descriptor if required */
2275 uint64_t cd_type_cmd_tso_mss =
2276 IAVF_TX_DESC_DTYPE_CONTEXT;
2277 volatile struct iavf_tx_context_desc *ctx_txd =
2278 (volatile struct iavf_tx_context_desc *)
2281 /* clear QW0 or the previous writeback value
2282 * may impact next write
2284 *(volatile uint64_t *)ctx_txd = 0;
2286 txn = &sw_ring[txe->next_id];
2287 RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
2289 rte_pktmbuf_free_seg(txe->mbuf);
2294 if (ol_flags & PKT_TX_TCP_SEG)
2295 cd_type_cmd_tso_mss |=
2296 iavf_set_tso_ctx(tx_pkt, tx_offload);
2298 if (ol_flags & PKT_TX_VLAN_PKT &&
2299 txq->vlan_flag & IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG2) {
2300 cd_type_cmd_tso_mss |= IAVF_TX_CTX_DESC_IL2TAG2
2301 << IAVF_TXD_CTX_QW1_CMD_SHIFT;
2302 cd_l2tag2 = tx_pkt->vlan_tci;
2305 ctx_txd->type_cmd_tso_mss =
2306 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
2307 ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
2309 IAVF_DUMP_TX_DESC(txq, &txr[tx_id], tx_id);
2310 txe->last_id = tx_last;
2311 tx_id = txe->next_id;
2318 txn = &sw_ring[txe->next_id];
2321 rte_pktmbuf_free_seg(txe->mbuf);
2324 /* Setup TX Descriptor */
2325 slen = m_seg->data_len;
2326 buf_dma_addr = rte_mbuf_data_iova(m_seg);
2327 txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
2328 txd->cmd_type_offset_bsz = iavf_build_ctob(td_cmd,
2333 IAVF_DUMP_TX_DESC(txq, txd, tx_id);
2334 txe->last_id = tx_last;
2335 tx_id = txe->next_id;
2337 m_seg = m_seg->next;
2340 /* The last packet data descriptor needs End Of Packet (EOP) */
2341 td_cmd |= IAVF_TX_DESC_CMD_EOP;
2342 txq->nb_used = (uint16_t)(txq->nb_used + nb_used);
2343 txq->nb_free = (uint16_t)(txq->nb_free - nb_used);
2345 if (txq->nb_used >= txq->rs_thresh) {
2346 PMD_TX_LOG(DEBUG, "Setting RS bit on TXD id="
2347 "%4u (port=%d queue=%d)",
2348 tx_last, txq->port_id, txq->queue_id);
2350 td_cmd |= IAVF_TX_DESC_CMD_RS;
2352 /* Update txq RS bit counters */
2356 txd->cmd_type_offset_bsz |=
2357 rte_cpu_to_le_64(((uint64_t)td_cmd) <<
2358 IAVF_TXD_QW1_CMD_SHIFT);
2359 IAVF_DUMP_TX_DESC(txq, txd, tx_id);
2365 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
2366 txq->port_id, txq->queue_id, tx_id, nb_tx);
2368 IAVF_PCI_REG_WC_WRITE_RELAXED(txq->qtx_tail, tx_id);
2369 txq->tx_tail = tx_id;
2374 /* Check if the packet with vlan user priority is transmitted in the
2378 iavf_check_vlan_up2tc(struct iavf_tx_queue *txq, struct rte_mbuf *m)
2380 struct rte_eth_dev *dev = &rte_eth_devices[txq->port_id];
2381 struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2384 up = m->vlan_tci >> IAVF_VLAN_TAG_PCP_OFFSET;
2386 if (!(vf->qos_cap->cap[txq->tc].tc_prio & BIT(up))) {
2387 PMD_TX_LOG(ERR, "packet with vlan pcp %u cannot transmit in queue %u\n",
2395 /* TX prep functions */
2397 iavf_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
2403 struct iavf_tx_queue *txq = tx_queue;
2404 struct rte_eth_dev *dev = &rte_eth_devices[txq->port_id];
2405 struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2407 for (i = 0; i < nb_pkts; i++) {
2409 ol_flags = m->ol_flags;
2411 /* Check condition for nb_segs > IAVF_TX_MAX_MTU_SEG. */
2412 if (!(ol_flags & PKT_TX_TCP_SEG)) {
2413 if (m->nb_segs > IAVF_TX_MAX_MTU_SEG) {
2417 } else if ((m->tso_segsz < IAVF_MIN_TSO_MSS) ||
2418 (m->tso_segsz > IAVF_MAX_TSO_MSS)) {
2419 /* MSS outside the range are considered malicious */
2424 if (ol_flags & IAVF_TX_OFFLOAD_NOTSUP_MASK) {
2425 rte_errno = ENOTSUP;
2429 #ifdef RTE_ETHDEV_DEBUG_TX
2430 ret = rte_validate_tx_offload(m);
2436 ret = rte_net_intel_cksum_prepare(m);
2442 if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_QOS &&
2443 ol_flags & (PKT_RX_VLAN_STRIPPED | PKT_RX_VLAN)) {
2444 ret = iavf_check_vlan_up2tc(txq, m);
2455 /* choose rx function*/
2457 iavf_set_rx_function(struct rte_eth_dev *dev)
2459 struct iavf_adapter *adapter =
2460 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2461 struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2464 struct iavf_rx_queue *rxq;
2467 bool use_avx2 = false;
2468 bool use_avx512 = false;
2469 bool use_flex = false;
2471 check_ret = iavf_rx_vec_dev_check(dev);
2472 if (check_ret >= 0 &&
2473 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
2474 if ((rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
2475 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) &&
2476 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256)
2479 #ifdef CC_AVX512_SUPPORT
2480 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 &&
2481 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1 &&
2482 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512)
2486 if (vf->vf_res->vf_cap_flags &
2487 VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC)
2490 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2491 rxq = dev->data->rx_queues[i];
2492 (void)iavf_rxq_vec_setup(rxq);
2495 if (dev->data->scattered_rx) {
2498 "Using %sVector Scattered Rx (port %d).",
2499 use_avx2 ? "avx2 " : "",
2500 dev->data->port_id);
2502 if (check_ret == IAVF_VECTOR_PATH)
2504 "Using AVX512 Vector Scattered Rx (port %d).",
2505 dev->data->port_id);
2508 "Using AVX512 OFFLOAD Vector Scattered Rx (port %d).",
2509 dev->data->port_id);
2512 dev->rx_pkt_burst = use_avx2 ?
2513 iavf_recv_scattered_pkts_vec_avx2_flex_rxd :
2514 iavf_recv_scattered_pkts_vec_flex_rxd;
2515 #ifdef CC_AVX512_SUPPORT
2517 if (check_ret == IAVF_VECTOR_PATH)
2519 iavf_recv_scattered_pkts_vec_avx512_flex_rxd;
2522 iavf_recv_scattered_pkts_vec_avx512_flex_rxd_offload;
2526 dev->rx_pkt_burst = use_avx2 ?
2527 iavf_recv_scattered_pkts_vec_avx2 :
2528 iavf_recv_scattered_pkts_vec;
2529 #ifdef CC_AVX512_SUPPORT
2531 if (check_ret == IAVF_VECTOR_PATH)
2533 iavf_recv_scattered_pkts_vec_avx512;
2536 iavf_recv_scattered_pkts_vec_avx512_offload;
2542 PMD_DRV_LOG(DEBUG, "Using %sVector Rx (port %d).",
2543 use_avx2 ? "avx2 " : "",
2544 dev->data->port_id);
2546 if (check_ret == IAVF_VECTOR_PATH)
2548 "Using AVX512 Vector Rx (port %d).",
2549 dev->data->port_id);
2552 "Using AVX512 OFFLOAD Vector Rx (port %d).",
2553 dev->data->port_id);
2556 dev->rx_pkt_burst = use_avx2 ?
2557 iavf_recv_pkts_vec_avx2_flex_rxd :
2558 iavf_recv_pkts_vec_flex_rxd;
2559 #ifdef CC_AVX512_SUPPORT
2561 if (check_ret == IAVF_VECTOR_PATH)
2563 iavf_recv_pkts_vec_avx512_flex_rxd;
2566 iavf_recv_pkts_vec_avx512_flex_rxd_offload;
2570 dev->rx_pkt_burst = use_avx2 ?
2571 iavf_recv_pkts_vec_avx2 :
2573 #ifdef CC_AVX512_SUPPORT
2575 if (check_ret == IAVF_VECTOR_PATH)
2577 iavf_recv_pkts_vec_avx512;
2580 iavf_recv_pkts_vec_avx512_offload;
2590 if (dev->data->scattered_rx) {
2591 PMD_DRV_LOG(DEBUG, "Using a Scattered Rx callback (port=%d).",
2592 dev->data->port_id);
2593 if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC)
2594 dev->rx_pkt_burst = iavf_recv_scattered_pkts_flex_rxd;
2596 dev->rx_pkt_burst = iavf_recv_scattered_pkts;
2597 } else if (adapter->rx_bulk_alloc_allowed) {
2598 PMD_DRV_LOG(DEBUG, "Using bulk Rx callback (port=%d).",
2599 dev->data->port_id);
2600 dev->rx_pkt_burst = iavf_recv_pkts_bulk_alloc;
2602 PMD_DRV_LOG(DEBUG, "Using Basic Rx callback (port=%d).",
2603 dev->data->port_id);
2604 if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC)
2605 dev->rx_pkt_burst = iavf_recv_pkts_flex_rxd;
2607 dev->rx_pkt_burst = iavf_recv_pkts;
2611 /* choose tx function*/
2613 iavf_set_tx_function(struct rte_eth_dev *dev)
2616 struct iavf_tx_queue *txq;
2619 bool use_sse = false;
2620 bool use_avx2 = false;
2621 bool use_avx512 = false;
2623 check_ret = iavf_tx_vec_dev_check(dev);
2625 if (check_ret >= 0 &&
2626 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
2627 /* SSE and AVX2 not support offload path yet. */
2628 if (check_ret == IAVF_VECTOR_PATH) {
2630 if ((rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
2631 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) &&
2632 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256)
2635 #ifdef CC_AVX512_SUPPORT
2636 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 &&
2637 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1 &&
2638 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512)
2642 if (!use_sse && !use_avx2 && !use_avx512)
2646 PMD_DRV_LOG(DEBUG, "Using %sVector Tx (port %d).",
2647 use_avx2 ? "avx2 " : "",
2648 dev->data->port_id);
2649 dev->tx_pkt_burst = use_avx2 ?
2650 iavf_xmit_pkts_vec_avx2 :
2653 dev->tx_pkt_prepare = NULL;
2654 #ifdef CC_AVX512_SUPPORT
2656 if (check_ret == IAVF_VECTOR_PATH) {
2657 dev->tx_pkt_burst = iavf_xmit_pkts_vec_avx512;
2658 PMD_DRV_LOG(DEBUG, "Using AVX512 Vector Tx (port %d).",
2659 dev->data->port_id);
2661 dev->tx_pkt_burst = iavf_xmit_pkts_vec_avx512_offload;
2662 dev->tx_pkt_prepare = iavf_prep_pkts;
2663 PMD_DRV_LOG(DEBUG, "Using AVX512 OFFLOAD Vector Tx (port %d).",
2664 dev->data->port_id);
2669 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2670 txq = dev->data->tx_queues[i];
2673 #ifdef CC_AVX512_SUPPORT
2675 iavf_txq_vec_setup_avx512(txq);
2677 iavf_txq_vec_setup(txq);
2679 iavf_txq_vec_setup(txq);
2688 PMD_DRV_LOG(DEBUG, "Using Basic Tx callback (port=%d).",
2689 dev->data->port_id);
2690 dev->tx_pkt_burst = iavf_xmit_pkts;
2691 dev->tx_pkt_prepare = iavf_prep_pkts;
2695 iavf_tx_done_cleanup_full(struct iavf_tx_queue *txq,
2698 struct iavf_tx_entry *swr_ring = txq->sw_ring;
2699 uint16_t i, tx_last, tx_id;
2700 uint16_t nb_tx_free_last;
2701 uint16_t nb_tx_to_clean;
2704 /* Start free mbuf from the next of tx_tail */
2705 tx_last = txq->tx_tail;
2706 tx_id = swr_ring[tx_last].next_id;
2708 if (txq->nb_free == 0 && iavf_xmit_cleanup(txq))
2711 nb_tx_to_clean = txq->nb_free;
2712 nb_tx_free_last = txq->nb_free;
2714 free_cnt = txq->nb_tx_desc;
2716 /* Loop through swr_ring to count the amount of
2717 * freeable mubfs and packets.
2719 for (pkt_cnt = 0; pkt_cnt < free_cnt; ) {
2720 for (i = 0; i < nb_tx_to_clean &&
2721 pkt_cnt < free_cnt &&
2722 tx_id != tx_last; i++) {
2723 if (swr_ring[tx_id].mbuf != NULL) {
2724 rte_pktmbuf_free_seg(swr_ring[tx_id].mbuf);
2725 swr_ring[tx_id].mbuf = NULL;
2728 * last segment in the packet,
2729 * increment packet count
2731 pkt_cnt += (swr_ring[tx_id].last_id == tx_id);
2734 tx_id = swr_ring[tx_id].next_id;
2737 if (txq->rs_thresh > txq->nb_tx_desc -
2738 txq->nb_free || tx_id == tx_last)
2741 if (pkt_cnt < free_cnt) {
2742 if (iavf_xmit_cleanup(txq))
2745 nb_tx_to_clean = txq->nb_free - nb_tx_free_last;
2746 nb_tx_free_last = txq->nb_free;
2750 return (int)pkt_cnt;
2754 iavf_dev_tx_done_cleanup(void *txq, uint32_t free_cnt)
2756 struct iavf_tx_queue *q = (struct iavf_tx_queue *)txq;
2758 return iavf_tx_done_cleanup_full(q, free_cnt);
2762 iavf_dev_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2763 struct rte_eth_rxq_info *qinfo)
2765 struct iavf_rx_queue *rxq;
2767 rxq = dev->data->rx_queues[queue_id];
2769 qinfo->mp = rxq->mp;
2770 qinfo->scattered_rx = dev->data->scattered_rx;
2771 qinfo->nb_desc = rxq->nb_rx_desc;
2773 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2774 qinfo->conf.rx_drop_en = true;
2775 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2779 iavf_dev_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2780 struct rte_eth_txq_info *qinfo)
2782 struct iavf_tx_queue *txq;
2784 txq = dev->data->tx_queues[queue_id];
2786 qinfo->nb_desc = txq->nb_tx_desc;
2788 qinfo->conf.tx_free_thresh = txq->free_thresh;
2789 qinfo->conf.tx_rs_thresh = txq->rs_thresh;
2790 qinfo->conf.offloads = txq->offloads;
2791 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2794 /* Get the number of used descriptors of a rx queue */
2796 iavf_dev_rxq_count(struct rte_eth_dev *dev, uint16_t queue_id)
2798 #define IAVF_RXQ_SCAN_INTERVAL 4
2799 volatile union iavf_rx_desc *rxdp;
2800 struct iavf_rx_queue *rxq;
2803 rxq = dev->data->rx_queues[queue_id];
2804 rxdp = &rxq->rx_ring[rxq->rx_tail];
2806 while ((desc < rxq->nb_rx_desc) &&
2807 ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
2808 IAVF_RXD_QW1_STATUS_MASK) >> IAVF_RXD_QW1_STATUS_SHIFT) &
2809 (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)) {
2810 /* Check the DD bit of a rx descriptor of each 4 in a group,
2811 * to avoid checking too frequently and downgrading performance
2814 desc += IAVF_RXQ_SCAN_INTERVAL;
2815 rxdp += IAVF_RXQ_SCAN_INTERVAL;
2816 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
2817 rxdp = &(rxq->rx_ring[rxq->rx_tail +
2818 desc - rxq->nb_rx_desc]);
2825 iavf_dev_rx_desc_status(void *rx_queue, uint16_t offset)
2827 struct iavf_rx_queue *rxq = rx_queue;
2828 volatile uint64_t *status;
2832 if (unlikely(offset >= rxq->nb_rx_desc))
2835 if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
2836 return RTE_ETH_RX_DESC_UNAVAIL;
2838 desc = rxq->rx_tail + offset;
2839 if (desc >= rxq->nb_rx_desc)
2840 desc -= rxq->nb_rx_desc;
2842 status = &rxq->rx_ring[desc].wb.qword1.status_error_len;
2843 mask = rte_le_to_cpu_64((1ULL << IAVF_RX_DESC_STATUS_DD_SHIFT)
2844 << IAVF_RXD_QW1_STATUS_SHIFT);
2846 return RTE_ETH_RX_DESC_DONE;
2848 return RTE_ETH_RX_DESC_AVAIL;
2852 iavf_dev_tx_desc_status(void *tx_queue, uint16_t offset)
2854 struct iavf_tx_queue *txq = tx_queue;
2855 volatile uint64_t *status;
2856 uint64_t mask, expect;
2859 if (unlikely(offset >= txq->nb_tx_desc))
2862 desc = txq->tx_tail + offset;
2863 /* go to next desc that has the RS bit */
2864 desc = ((desc + txq->rs_thresh - 1) / txq->rs_thresh) *
2866 if (desc >= txq->nb_tx_desc) {
2867 desc -= txq->nb_tx_desc;
2868 if (desc >= txq->nb_tx_desc)
2869 desc -= txq->nb_tx_desc;
2872 status = &txq->tx_ring[desc].cmd_type_offset_bsz;
2873 mask = rte_le_to_cpu_64(IAVF_TXD_QW1_DTYPE_MASK);
2874 expect = rte_cpu_to_le_64(
2875 IAVF_TX_DESC_DTYPE_DESC_DONE << IAVF_TXD_QW1_DTYPE_SHIFT);
2876 if ((*status & mask) == expect)
2877 return RTE_ETH_TX_DESC_DONE;
2879 return RTE_ETH_TX_DESC_FULL;
2883 iavf_get_default_ptype_table(void)
2885 static const uint32_t ptype_tbl[IAVF_MAX_PKT_TYPE]
2886 __rte_cache_aligned = {
2889 [1] = RTE_PTYPE_L2_ETHER,
2890 [2] = RTE_PTYPE_L2_ETHER_TIMESYNC,
2891 /* [3] - [5] reserved */
2892 [6] = RTE_PTYPE_L2_ETHER_LLDP,
2893 /* [7] - [10] reserved */
2894 [11] = RTE_PTYPE_L2_ETHER_ARP,
2895 /* [12] - [21] reserved */
2897 /* Non tunneled IPv4 */
2898 [22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2900 [23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2901 RTE_PTYPE_L4_NONFRAG,
2902 [24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2905 [26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2907 [27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2909 [28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2913 [29] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2914 RTE_PTYPE_TUNNEL_IP |
2915 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2916 RTE_PTYPE_INNER_L4_FRAG,
2917 [30] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2918 RTE_PTYPE_TUNNEL_IP |
2919 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2920 RTE_PTYPE_INNER_L4_NONFRAG,
2921 [31] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2922 RTE_PTYPE_TUNNEL_IP |
2923 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2924 RTE_PTYPE_INNER_L4_UDP,
2926 [33] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2927 RTE_PTYPE_TUNNEL_IP |
2928 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2929 RTE_PTYPE_INNER_L4_TCP,
2930 [34] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2931 RTE_PTYPE_TUNNEL_IP |
2932 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2933 RTE_PTYPE_INNER_L4_SCTP,
2934 [35] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2935 RTE_PTYPE_TUNNEL_IP |
2936 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2937 RTE_PTYPE_INNER_L4_ICMP,
2940 [36] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2941 RTE_PTYPE_TUNNEL_IP |
2942 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2943 RTE_PTYPE_INNER_L4_FRAG,
2944 [37] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2945 RTE_PTYPE_TUNNEL_IP |
2946 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2947 RTE_PTYPE_INNER_L4_NONFRAG,
2948 [38] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2949 RTE_PTYPE_TUNNEL_IP |
2950 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2951 RTE_PTYPE_INNER_L4_UDP,
2953 [40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2954 RTE_PTYPE_TUNNEL_IP |
2955 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2956 RTE_PTYPE_INNER_L4_TCP,
2957 [41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2958 RTE_PTYPE_TUNNEL_IP |
2959 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2960 RTE_PTYPE_INNER_L4_SCTP,
2961 [42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2962 RTE_PTYPE_TUNNEL_IP |
2963 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2964 RTE_PTYPE_INNER_L4_ICMP,
2966 /* IPv4 --> GRE/Teredo/VXLAN */
2967 [43] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2968 RTE_PTYPE_TUNNEL_GRENAT,
2970 /* IPv4 --> GRE/Teredo/VXLAN --> IPv4 */
2971 [44] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2972 RTE_PTYPE_TUNNEL_GRENAT |
2973 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2974 RTE_PTYPE_INNER_L4_FRAG,
2975 [45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2976 RTE_PTYPE_TUNNEL_GRENAT |
2977 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2978 RTE_PTYPE_INNER_L4_NONFRAG,
2979 [46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2980 RTE_PTYPE_TUNNEL_GRENAT |
2981 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2982 RTE_PTYPE_INNER_L4_UDP,
2984 [48] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2985 RTE_PTYPE_TUNNEL_GRENAT |
2986 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2987 RTE_PTYPE_INNER_L4_TCP,
2988 [49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2989 RTE_PTYPE_TUNNEL_GRENAT |
2990 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2991 RTE_PTYPE_INNER_L4_SCTP,
2992 [50] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2993 RTE_PTYPE_TUNNEL_GRENAT |
2994 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2995 RTE_PTYPE_INNER_L4_ICMP,
2997 /* IPv4 --> GRE/Teredo/VXLAN --> IPv6 */
2998 [51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2999 RTE_PTYPE_TUNNEL_GRENAT |
3000 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3001 RTE_PTYPE_INNER_L4_FRAG,
3002 [52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3003 RTE_PTYPE_TUNNEL_GRENAT |
3004 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3005 RTE_PTYPE_INNER_L4_NONFRAG,
3006 [53] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3007 RTE_PTYPE_TUNNEL_GRENAT |
3008 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3009 RTE_PTYPE_INNER_L4_UDP,
3011 [55] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3012 RTE_PTYPE_TUNNEL_GRENAT |
3013 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3014 RTE_PTYPE_INNER_L4_TCP,
3015 [56] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3016 RTE_PTYPE_TUNNEL_GRENAT |
3017 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3018 RTE_PTYPE_INNER_L4_SCTP,
3019 [57] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3020 RTE_PTYPE_TUNNEL_GRENAT |
3021 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3022 RTE_PTYPE_INNER_L4_ICMP,
3024 /* IPv4 --> GRE/Teredo/VXLAN --> MAC */
3025 [58] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3026 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
3028 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
3029 [59] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3030 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3031 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3032 RTE_PTYPE_INNER_L4_FRAG,
3033 [60] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3034 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3035 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3036 RTE_PTYPE_INNER_L4_NONFRAG,
3037 [61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3038 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3039 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3040 RTE_PTYPE_INNER_L4_UDP,
3042 [63] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3043 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3044 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3045 RTE_PTYPE_INNER_L4_TCP,
3046 [64] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3047 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3048 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3049 RTE_PTYPE_INNER_L4_SCTP,
3050 [65] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3051 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3052 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3053 RTE_PTYPE_INNER_L4_ICMP,
3055 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
3056 [66] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3057 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3058 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3059 RTE_PTYPE_INNER_L4_FRAG,
3060 [67] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3061 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3062 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3063 RTE_PTYPE_INNER_L4_NONFRAG,
3064 [68] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3065 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3066 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3067 RTE_PTYPE_INNER_L4_UDP,
3069 [70] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3070 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3071 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3072 RTE_PTYPE_INNER_L4_TCP,
3073 [71] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3074 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3075 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3076 RTE_PTYPE_INNER_L4_SCTP,
3077 [72] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3078 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3079 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3080 RTE_PTYPE_INNER_L4_ICMP,
3081 /* [73] - [87] reserved */
3083 /* Non tunneled IPv6 */
3084 [88] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3086 [89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3087 RTE_PTYPE_L4_NONFRAG,
3088 [90] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3091 [92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3093 [93] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3095 [94] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3099 [95] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3100 RTE_PTYPE_TUNNEL_IP |
3101 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3102 RTE_PTYPE_INNER_L4_FRAG,
3103 [96] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3104 RTE_PTYPE_TUNNEL_IP |
3105 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3106 RTE_PTYPE_INNER_L4_NONFRAG,
3107 [97] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3108 RTE_PTYPE_TUNNEL_IP |
3109 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3110 RTE_PTYPE_INNER_L4_UDP,
3112 [99] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3113 RTE_PTYPE_TUNNEL_IP |
3114 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3115 RTE_PTYPE_INNER_L4_TCP,
3116 [100] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3117 RTE_PTYPE_TUNNEL_IP |
3118 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3119 RTE_PTYPE_INNER_L4_SCTP,
3120 [101] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3121 RTE_PTYPE_TUNNEL_IP |
3122 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3123 RTE_PTYPE_INNER_L4_ICMP,
3126 [102] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3127 RTE_PTYPE_TUNNEL_IP |
3128 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3129 RTE_PTYPE_INNER_L4_FRAG,
3130 [103] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3131 RTE_PTYPE_TUNNEL_IP |
3132 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3133 RTE_PTYPE_INNER_L4_NONFRAG,
3134 [104] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3135 RTE_PTYPE_TUNNEL_IP |
3136 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3137 RTE_PTYPE_INNER_L4_UDP,
3138 /* [105] reserved */
3139 [106] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3140 RTE_PTYPE_TUNNEL_IP |
3141 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3142 RTE_PTYPE_INNER_L4_TCP,
3143 [107] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3144 RTE_PTYPE_TUNNEL_IP |
3145 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3146 RTE_PTYPE_INNER_L4_SCTP,
3147 [108] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3148 RTE_PTYPE_TUNNEL_IP |
3149 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3150 RTE_PTYPE_INNER_L4_ICMP,
3152 /* IPv6 --> GRE/Teredo/VXLAN */
3153 [109] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3154 RTE_PTYPE_TUNNEL_GRENAT,
3156 /* IPv6 --> GRE/Teredo/VXLAN --> IPv4 */
3157 [110] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3158 RTE_PTYPE_TUNNEL_GRENAT |
3159 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3160 RTE_PTYPE_INNER_L4_FRAG,
3161 [111] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3162 RTE_PTYPE_TUNNEL_GRENAT |
3163 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3164 RTE_PTYPE_INNER_L4_NONFRAG,
3165 [112] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3166 RTE_PTYPE_TUNNEL_GRENAT |
3167 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3168 RTE_PTYPE_INNER_L4_UDP,
3169 /* [113] reserved */
3170 [114] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3171 RTE_PTYPE_TUNNEL_GRENAT |
3172 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3173 RTE_PTYPE_INNER_L4_TCP,
3174 [115] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3175 RTE_PTYPE_TUNNEL_GRENAT |
3176 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3177 RTE_PTYPE_INNER_L4_SCTP,
3178 [116] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3179 RTE_PTYPE_TUNNEL_GRENAT |
3180 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3181 RTE_PTYPE_INNER_L4_ICMP,
3183 /* IPv6 --> GRE/Teredo/VXLAN --> IPv6 */
3184 [117] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3185 RTE_PTYPE_TUNNEL_GRENAT |
3186 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3187 RTE_PTYPE_INNER_L4_FRAG,
3188 [118] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3189 RTE_PTYPE_TUNNEL_GRENAT |
3190 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3191 RTE_PTYPE_INNER_L4_NONFRAG,
3192 [119] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3193 RTE_PTYPE_TUNNEL_GRENAT |
3194 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3195 RTE_PTYPE_INNER_L4_UDP,
3196 /* [120] reserved */
3197 [121] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3198 RTE_PTYPE_TUNNEL_GRENAT |
3199 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3200 RTE_PTYPE_INNER_L4_TCP,
3201 [122] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3202 RTE_PTYPE_TUNNEL_GRENAT |
3203 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3204 RTE_PTYPE_INNER_L4_SCTP,
3205 [123] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3206 RTE_PTYPE_TUNNEL_GRENAT |
3207 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3208 RTE_PTYPE_INNER_L4_ICMP,
3210 /* IPv6 --> GRE/Teredo/VXLAN --> MAC */
3211 [124] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3212 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
3214 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
3215 [125] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3216 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3217 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3218 RTE_PTYPE_INNER_L4_FRAG,
3219 [126] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3220 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3221 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3222 RTE_PTYPE_INNER_L4_NONFRAG,
3223 [127] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3224 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3225 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3226 RTE_PTYPE_INNER_L4_UDP,
3227 /* [128] reserved */
3228 [129] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3229 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3230 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3231 RTE_PTYPE_INNER_L4_TCP,
3232 [130] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3233 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3234 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3235 RTE_PTYPE_INNER_L4_SCTP,
3236 [131] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3237 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3238 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3239 RTE_PTYPE_INNER_L4_ICMP,
3241 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
3242 [132] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3243 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3244 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3245 RTE_PTYPE_INNER_L4_FRAG,
3246 [133] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3247 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3248 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3249 RTE_PTYPE_INNER_L4_NONFRAG,
3250 [134] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3251 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3252 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3253 RTE_PTYPE_INNER_L4_UDP,
3254 /* [135] reserved */
3255 [136] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3256 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3257 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3258 RTE_PTYPE_INNER_L4_TCP,
3259 [137] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3260 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3261 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3262 RTE_PTYPE_INNER_L4_SCTP,
3263 [138] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3264 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3265 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3266 RTE_PTYPE_INNER_L4_ICMP,
3267 /* [139] - [299] reserved */
3270 [300] = RTE_PTYPE_L2_ETHER_PPPOE,
3271 [301] = RTE_PTYPE_L2_ETHER_PPPOE,
3273 /* PPPoE --> IPv4 */
3274 [302] = RTE_PTYPE_L2_ETHER_PPPOE |
3275 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3277 [303] = RTE_PTYPE_L2_ETHER_PPPOE |
3278 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3279 RTE_PTYPE_L4_NONFRAG,
3280 [304] = RTE_PTYPE_L2_ETHER_PPPOE |
3281 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3283 [305] = RTE_PTYPE_L2_ETHER_PPPOE |
3284 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3286 [306] = RTE_PTYPE_L2_ETHER_PPPOE |
3287 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3289 [307] = RTE_PTYPE_L2_ETHER_PPPOE |
3290 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3293 /* PPPoE --> IPv6 */
3294 [308] = RTE_PTYPE_L2_ETHER_PPPOE |
3295 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3297 [309] = RTE_PTYPE_L2_ETHER_PPPOE |
3298 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3299 RTE_PTYPE_L4_NONFRAG,
3300 [310] = RTE_PTYPE_L2_ETHER_PPPOE |
3301 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3303 [311] = RTE_PTYPE_L2_ETHER_PPPOE |
3304 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3306 [312] = RTE_PTYPE_L2_ETHER_PPPOE |
3307 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3309 [313] = RTE_PTYPE_L2_ETHER_PPPOE |
3310 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3312 /* [314] - [324] reserved */
3314 /* IPv4/IPv6 --> GTPC/GTPU */
3315 [325] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3316 RTE_PTYPE_TUNNEL_GTPC,
3317 [326] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3318 RTE_PTYPE_TUNNEL_GTPC,
3319 [327] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3320 RTE_PTYPE_TUNNEL_GTPC,
3321 [328] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3322 RTE_PTYPE_TUNNEL_GTPC,
3323 [329] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3324 RTE_PTYPE_TUNNEL_GTPU,
3325 [330] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3326 RTE_PTYPE_TUNNEL_GTPU,
3328 /* IPv4 --> GTPU --> IPv4 */
3329 [331] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3330 RTE_PTYPE_TUNNEL_GTPU |
3331 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3332 RTE_PTYPE_INNER_L4_FRAG,
3333 [332] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3334 RTE_PTYPE_TUNNEL_GTPU |
3335 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3336 RTE_PTYPE_INNER_L4_NONFRAG,
3337 [333] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3338 RTE_PTYPE_TUNNEL_GTPU |
3339 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3340 RTE_PTYPE_INNER_L4_UDP,
3341 [334] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3342 RTE_PTYPE_TUNNEL_GTPU |
3343 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3344 RTE_PTYPE_INNER_L4_TCP,
3345 [335] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3346 RTE_PTYPE_TUNNEL_GTPU |
3347 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3348 RTE_PTYPE_INNER_L4_ICMP,
3350 /* IPv6 --> GTPU --> IPv4 */
3351 [336] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3352 RTE_PTYPE_TUNNEL_GTPU |
3353 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3354 RTE_PTYPE_INNER_L4_FRAG,
3355 [337] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3356 RTE_PTYPE_TUNNEL_GTPU |
3357 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3358 RTE_PTYPE_INNER_L4_NONFRAG,
3359 [338] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3360 RTE_PTYPE_TUNNEL_GTPU |
3361 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3362 RTE_PTYPE_INNER_L4_UDP,
3363 [339] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3364 RTE_PTYPE_TUNNEL_GTPU |
3365 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3366 RTE_PTYPE_INNER_L4_TCP,
3367 [340] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3368 RTE_PTYPE_TUNNEL_GTPU |
3369 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3370 RTE_PTYPE_INNER_L4_ICMP,
3372 /* IPv4 --> GTPU --> IPv6 */
3373 [341] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3374 RTE_PTYPE_TUNNEL_GTPU |
3375 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3376 RTE_PTYPE_INNER_L4_FRAG,
3377 [342] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3378 RTE_PTYPE_TUNNEL_GTPU |
3379 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3380 RTE_PTYPE_INNER_L4_NONFRAG,
3381 [343] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3382 RTE_PTYPE_TUNNEL_GTPU |
3383 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3384 RTE_PTYPE_INNER_L4_UDP,
3385 [344] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3386 RTE_PTYPE_TUNNEL_GTPU |
3387 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3388 RTE_PTYPE_INNER_L4_TCP,
3389 [345] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3390 RTE_PTYPE_TUNNEL_GTPU |
3391 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3392 RTE_PTYPE_INNER_L4_ICMP,
3394 /* IPv6 --> GTPU --> IPv6 */
3395 [346] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3396 RTE_PTYPE_TUNNEL_GTPU |
3397 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3398 RTE_PTYPE_INNER_L4_FRAG,
3399 [347] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3400 RTE_PTYPE_TUNNEL_GTPU |
3401 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3402 RTE_PTYPE_INNER_L4_NONFRAG,
3403 [348] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3404 RTE_PTYPE_TUNNEL_GTPU |
3405 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3406 RTE_PTYPE_INNER_L4_UDP,
3407 [349] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3408 RTE_PTYPE_TUNNEL_GTPU |
3409 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3410 RTE_PTYPE_INNER_L4_TCP,
3411 [350] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3412 RTE_PTYPE_TUNNEL_GTPU |
3413 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3414 RTE_PTYPE_INNER_L4_ICMP,
3416 /* IPv4 --> UDP ECPRI */
3417 [372] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3419 [373] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3421 [374] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3423 [375] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3425 [376] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3427 [377] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3429 [378] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3431 [379] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3433 [380] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3435 [381] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3438 /* IPV6 --> UDP ECPRI */
3439 [382] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3441 [383] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3443 [384] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3445 [385] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3447 [386] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3449 [387] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3451 [388] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3453 [389] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3455 [390] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3457 [391] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3459 /* All others reserved */