drivers/net/iavf/iavf_rxtx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2017 Intel Corporation
   3  */
   4
   5 #include <stdio.h>
   6 #include <stdlib.h>
   7 #include <string.h>
   8 #include <errno.h>
   9 #include <stdint.h>
  10 #include <stdarg.h>
  11 #include <unistd.h>
  12 #include <inttypes.h>
  13 #include <sys/queue.h>
  14
  15 #include <rte_string_fns.h>
  16 #include <rte_memzone.h>
  17 #include <rte_mbuf.h>
  18 #include <rte_malloc.h>
  19 #include <rte_ether.h>
  20 #include <ethdev_driver.h>
  21 #include <rte_tcp.h>
  22 #include <rte_sctp.h>
  23 #include <rte_udp.h>
  24 #include <rte_ip.h>
  25 #include <rte_net.h>
  26 #include <rte_vect.h>
  27
  28 #include "iavf.h"
  29 #include "iavf_rxtx.h"
  30 #include "rte_pmd_iavf.h"
  31
  32 /* Offset of mbuf dynamic field for protocol extraction's metadata */
  33 int rte_pmd_ifd_dynfield_proto_xtr_metadata_offs = -1;
  34
  35 /* Mask of mbuf dynamic flags for protocol extraction's type */
  36 uint64_t rte_pmd_ifd_dynflag_proto_xtr_vlan_mask;
  37 uint64_t rte_pmd_ifd_dynflag_proto_xtr_ipv4_mask;
  38 uint64_t rte_pmd_ifd_dynflag_proto_xtr_ipv6_mask;
  39 uint64_t rte_pmd_ifd_dynflag_proto_xtr_ipv6_flow_mask;
  40 uint64_t rte_pmd_ifd_dynflag_proto_xtr_tcp_mask;
  41 uint64_t rte_pmd_ifd_dynflag_proto_xtr_ip_offset_mask;
  42
  43 uint8_t
  44 iavf_proto_xtr_type_to_rxdid(uint8_t flex_type)
  45 {
  46         static uint8_t rxdid_map[] = {
  47                 [IAVF_PROTO_XTR_NONE]      = IAVF_RXDID_COMMS_OVS_1,
  48                 [IAVF_PROTO_XTR_VLAN]      = IAVF_RXDID_COMMS_AUX_VLAN,
  49                 [IAVF_PROTO_XTR_IPV4]      = IAVF_RXDID_COMMS_AUX_IPV4,
  50                 [IAVF_PROTO_XTR_IPV6]      = IAVF_RXDID_COMMS_AUX_IPV6,
  51                 [IAVF_PROTO_XTR_IPV6_FLOW] = IAVF_RXDID_COMMS_AUX_IPV6_FLOW,
  52                 [IAVF_PROTO_XTR_TCP]       = IAVF_RXDID_COMMS_AUX_TCP,
  53                 [IAVF_PROTO_XTR_IP_OFFSET] = IAVF_RXDID_COMMS_AUX_IP_OFFSET,
  54         };
  55
  56         return flex_type < RTE_DIM(rxdid_map) ?
  57                                 rxdid_map[flex_type] : IAVF_RXDID_COMMS_OVS_1;
  58 }
  59
  60 static int
  61 iavf_monitor_callback(const uint64_t value,
  62                 const uint64_t arg[RTE_POWER_MONITOR_OPAQUE_SZ] __rte_unused)
  63 {
  64         const uint64_t m = rte_cpu_to_le_64(1 << IAVF_RX_DESC_STATUS_DD_SHIFT);
  65         /*
  66          * we expect the DD bit to be set to 1 if this descriptor was already
  67          * written to.
  68          */
  69         return (value & m) == m ? -1 : 0;
  70 }
  71
  72 int
  73 iavf_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc)
  74 {
  75         struct iavf_rx_queue *rxq = rx_queue;
  76         volatile union iavf_rx_desc *rxdp;
  77         uint16_t desc;
  78
  79         desc = rxq->rx_tail;
  80         rxdp = &rxq->rx_ring[desc];
  81         /* watch for changes in status bit */
  82         pmc->addr = &rxdp->wb.qword1.status_error_len;
  83
  84         /* comparison callback */
  85         pmc->fn = iavf_monitor_callback;
  86
  87         /* registers are 64-bit */
  88         pmc->size = sizeof(uint64_t);
  89
  90         return 0;
  91 }
  92
  93 static inline int
  94 check_rx_thresh(uint16_t nb_desc, uint16_t thresh)
  95 {
  96         /* The following constraints must be satisfied:
  97          *   thresh < rxq->nb_rx_desc
  98          */
  99         if (thresh >= nb_desc) {
 100                 PMD_INIT_LOG(ERR, "rx_free_thresh (%u) must be less than %u",
 101                              thresh, nb_desc);
 102                 return -EINVAL;
 103         }
 104         return 0;
 105 }
 106
 107 static inline int
 108 check_tx_thresh(uint16_t nb_desc, uint16_t tx_rs_thresh,
 109                 uint16_t tx_free_thresh)
 110 {
 111         /* TX descriptors will have their RS bit set after tx_rs_thresh
 112          * descriptors have been used. The TX descriptor ring will be cleaned
 113          * after tx_free_thresh descriptors are used or if the number of
 114          * descriptors required to transmit a packet is greater than the
 115          * number of free TX descriptors.
 116          *
 117          * The following constraints must be satisfied:
 118          *  - tx_rs_thresh must be less than the size of the ring minus 2.
 119          *  - tx_free_thresh must be less than the size of the ring minus 3.
 120          *  - tx_rs_thresh must be less than or equal to tx_free_thresh.
 121          *  - tx_rs_thresh must be a divisor of the ring size.
 122          *
 123          * One descriptor in the TX ring is used as a sentinel to avoid a H/W
 124          * race condition, hence the maximum threshold constraints. When set
 125          * to zero use default values.
 126          */
 127         if (tx_rs_thresh >= (nb_desc - 2)) {
 128                 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be less than the "
 129                              "number of TX descriptors (%u) minus 2",
 130                              tx_rs_thresh, nb_desc);
 131                 return -EINVAL;
 132         }
 133         if (tx_free_thresh >= (nb_desc - 3)) {
 134                 PMD_INIT_LOG(ERR, "tx_free_thresh (%u) must be less than the "
 135                              "number of TX descriptors (%u) minus 3.",
 136                              tx_free_thresh, nb_desc);
 137                 return -EINVAL;
 138         }
 139         if (tx_rs_thresh > tx_free_thresh) {
 140                 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be less than or "
 141                              "equal to tx_free_thresh (%u).",
 142                              tx_rs_thresh, tx_free_thresh);
 143                 return -EINVAL;
 144         }
 145         if ((nb_desc % tx_rs_thresh) != 0) {
 146                 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be a divisor of the "
 147                              "number of TX descriptors (%u).",
 148                              tx_rs_thresh, nb_desc);
 149                 return -EINVAL;
 150         }
 151
 152         return 0;
 153 }
 154
 155 static inline bool
 156 check_rx_vec_allow(struct iavf_rx_queue *rxq)
 157 {
 158         if (rxq->rx_free_thresh >= IAVF_VPMD_RX_MAX_BURST &&
 159             rxq->nb_rx_desc % rxq->rx_free_thresh == 0) {
 160                 PMD_INIT_LOG(DEBUG, "Vector Rx can be enabled on this rxq.");
 161                 return true;
 162         }
 163
 164         PMD_INIT_LOG(DEBUG, "Vector Rx cannot be enabled on this rxq.");
 165         return false;
 166 }
 167
 168 static inline bool
 169 check_tx_vec_allow(struct iavf_tx_queue *txq)
 170 {
 171         if (!(txq->offloads & IAVF_TX_NO_VECTOR_FLAGS) &&
 172             txq->rs_thresh >= IAVF_VPMD_TX_MAX_BURST &&
 173             txq->rs_thresh <= IAVF_VPMD_TX_MAX_FREE_BUF) {
 174                 PMD_INIT_LOG(DEBUG, "Vector tx can be enabled on this txq.");
 175                 return true;
 176         }
 177         PMD_INIT_LOG(DEBUG, "Vector Tx cannot be enabled on this txq.");
 178         return false;
 179 }
 180
 181 static inline bool
 182 check_rx_bulk_allow(struct iavf_rx_queue *rxq)
 183 {
 184         int ret = true;
 185
 186         if (!(rxq->rx_free_thresh >= IAVF_RX_MAX_BURST)) {
 187                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 188                              "rxq->rx_free_thresh=%d, "
 189                              "IAVF_RX_MAX_BURST=%d",
 190                              rxq->rx_free_thresh, IAVF_RX_MAX_BURST);
 191                 ret = false;
 192         } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
 193                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 194                              "rxq->nb_rx_desc=%d, "
 195                              "rxq->rx_free_thresh=%d",
 196                              rxq->nb_rx_desc, rxq->rx_free_thresh);
 197                 ret = false;
 198         }
 199         return ret;
 200 }
 201
 202 static inline void
 203 reset_rx_queue(struct iavf_rx_queue *rxq)
 204 {
 205         uint16_t len;
 206         uint32_t i;
 207
 208         if (!rxq)
 209                 return;
 210
 211         len = rxq->nb_rx_desc + IAVF_RX_MAX_BURST;
 212
 213         for (i = 0; i < len * sizeof(union iavf_rx_desc); i++)
 214                 ((volatile char *)rxq->rx_ring)[i] = 0;
 215
 216         memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
 217
 218         for (i = 0; i < IAVF_RX_MAX_BURST; i++)
 219                 rxq->sw_ring[rxq->nb_rx_desc + i] = &rxq->fake_mbuf;
 220
 221         /* for rx bulk */
 222         rxq->rx_nb_avail = 0;
 223         rxq->rx_next_avail = 0;
 224         rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
 225
 226         rxq->rx_tail = 0;
 227         rxq->nb_rx_hold = 0;
 228
 229         if (rxq->pkt_first_seg != NULL)
 230                 rte_pktmbuf_free(rxq->pkt_first_seg);
 231
 232         rxq->pkt_first_seg = NULL;
 233         rxq->pkt_last_seg = NULL;
 234         rxq->rxrearm_nb = 0;
 235         rxq->rxrearm_start = 0;
 236 }
 237
 238 static inline void
 239 reset_tx_queue(struct iavf_tx_queue *txq)
 240 {
 241         struct iavf_tx_entry *txe;
 242         uint32_t i, size;
 243         uint16_t prev;
 244
 245         if (!txq) {
 246                 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
 247                 return;
 248         }
 249
 250         txe = txq->sw_ring;
 251         size = sizeof(struct iavf_tx_desc) * txq->nb_tx_desc;
 252         for (i = 0; i < size; i++)
 253                 ((volatile char *)txq->tx_ring)[i] = 0;
 254
 255         prev = (uint16_t)(txq->nb_tx_desc - 1);
 256         for (i = 0; i < txq->nb_tx_desc; i++) {
 257                 txq->tx_ring[i].cmd_type_offset_bsz =
 258                         rte_cpu_to_le_64(IAVF_TX_DESC_DTYPE_DESC_DONE);
 259                 txe[i].mbuf =  NULL;
 260                 txe[i].last_id = i;
 261                 txe[prev].next_id = i;
 262                 prev = i;
 263         }
 264
 265         txq->tx_tail = 0;
 266         txq->nb_used = 0;
 267
 268         txq->last_desc_cleaned = txq->nb_tx_desc - 1;
 269         txq->nb_free = txq->nb_tx_desc - 1;
 270
 271         txq->next_dd = txq->rs_thresh - 1;
 272         txq->next_rs = txq->rs_thresh - 1;
 273 }
 274
 275 static int
 276 alloc_rxq_mbufs(struct iavf_rx_queue *rxq)
 277 {
 278         volatile union iavf_rx_desc *rxd;
 279         struct rte_mbuf *mbuf = NULL;
 280         uint64_t dma_addr;
 281         uint16_t i, j;
 282
 283         for (i = 0; i < rxq->nb_rx_desc; i++) {
 284                 mbuf = rte_mbuf_raw_alloc(rxq->mp);
 285                 if (unlikely(!mbuf)) {
 286                         for (j = 0; j < i; j++) {
 287                                 rte_pktmbuf_free_seg(rxq->sw_ring[j]);
 288                                 rxq->sw_ring[j] = NULL;
 289                         }
 290                         PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
 291                         return -ENOMEM;
 292                 }
 293
 294                 rte_mbuf_refcnt_set(mbuf, 1);
 295                 mbuf->next = NULL;
 296                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
 297                 mbuf->nb_segs = 1;
 298                 mbuf->port = rxq->port_id;
 299
 300                 dma_addr =
 301                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
 302
 303                 rxd = &rxq->rx_ring[i];
 304                 rxd->read.pkt_addr = dma_addr;
 305                 rxd->read.hdr_addr = 0;
 306 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
 307                 rxd->read.rsvd1 = 0;
 308                 rxd->read.rsvd2 = 0;
 309 #endif
 310
 311                 rxq->sw_ring[i] = mbuf;
 312         }
 313
 314         return 0;
 315 }
 316
 317 static inline void
 318 release_rxq_mbufs(struct iavf_rx_queue *rxq)
 319 {
 320         uint16_t i;
 321
 322         if (!rxq->sw_ring)
 323                 return;
 324
 325         for (i = 0; i < rxq->nb_rx_desc; i++) {
 326                 if (rxq->sw_ring[i]) {
 327                         rte_pktmbuf_free_seg(rxq->sw_ring[i]);
 328                         rxq->sw_ring[i] = NULL;
 329                 }
 330         }
 331
 332         /* for rx bulk */
 333         if (rxq->rx_nb_avail == 0)
 334                 return;
 335         for (i = 0; i < rxq->rx_nb_avail; i++) {
 336                 struct rte_mbuf *mbuf;
 337
 338                 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
 339                 rte_pktmbuf_free_seg(mbuf);
 340         }
 341         rxq->rx_nb_avail = 0;
 342 }
 343
 344 static inline void
 345 release_txq_mbufs(struct iavf_tx_queue *txq)
 346 {
 347         uint16_t i;
 348
 349         if (!txq || !txq->sw_ring) {
 350                 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
 351                 return;
 352         }
 353
 354         for (i = 0; i < txq->nb_tx_desc; i++) {
 355                 if (txq->sw_ring[i].mbuf) {
 356                         rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
 357                         txq->sw_ring[i].mbuf = NULL;
 358                 }
 359         }
 360 }
 361
 362 static const struct iavf_rxq_ops def_rxq_ops = {
 363         .release_mbufs = release_rxq_mbufs,
 364 };
 365
 366 static const struct iavf_txq_ops def_txq_ops = {
 367         .release_mbufs = release_txq_mbufs,
 368 };
 369
 370 static inline void
 371 iavf_rxd_to_pkt_fields_by_comms_ovs(__rte_unused struct iavf_rx_queue *rxq,
 372                                     struct rte_mbuf *mb,
 373                                     volatile union iavf_rx_flex_desc *rxdp)
 374 {
 375         volatile struct iavf_32b_rx_flex_desc_comms_ovs *desc =
 376                         (volatile struct iavf_32b_rx_flex_desc_comms_ovs *)rxdp;
 377 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
 378         uint16_t stat_err;
 379 #endif
 380
 381         if (desc->flow_id != 0xFFFFFFFF) {
 382                 mb->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
 383                 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
 384         }
 385
 386 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
 387         stat_err = rte_le_to_cpu_16(desc->status_error0);
 388         if (likely(stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
 389                 mb->ol_flags |= PKT_RX_RSS_HASH;
 390                 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
 391         }
 392 #endif
 393 }
 394
 395 static inline void
 396 iavf_rxd_to_pkt_fields_by_comms_aux_v1(struct iavf_rx_queue *rxq,
 397                                        struct rte_mbuf *mb,
 398                                        volatile union iavf_rx_flex_desc *rxdp)
 399 {
 400         volatile struct iavf_32b_rx_flex_desc_comms *desc =
 401                         (volatile struct iavf_32b_rx_flex_desc_comms *)rxdp;
 402         uint16_t stat_err;
 403
 404         stat_err = rte_le_to_cpu_16(desc->status_error0);
 405         if (likely(stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
 406                 mb->ol_flags |= PKT_RX_RSS_HASH;
 407                 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
 408         }
 409
 410 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
 411         if (desc->flow_id != 0xFFFFFFFF) {
 412                 mb->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
 413                 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
 414         }
 415
 416         if (rxq->xtr_ol_flag) {
 417                 uint32_t metadata = 0;
 418
 419                 stat_err = rte_le_to_cpu_16(desc->status_error1);
 420
 421                 if (stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS1_XTRMD4_VALID_S))
 422                         metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux0);
 423
 424                 if (stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS1_XTRMD5_VALID_S))
 425                         metadata |=
 426                                 rte_le_to_cpu_16(desc->flex_ts.flex.aux1) << 16;
 427
 428                 if (metadata) {
 429                         mb->ol_flags |= rxq->xtr_ol_flag;
 430
 431                         *RTE_PMD_IFD_DYNF_PROTO_XTR_METADATA(mb) = metadata;
 432                 }
 433         }
 434 #endif
 435 }
 436
 437 static inline void
 438 iavf_rxd_to_pkt_fields_by_comms_aux_v2(struct iavf_rx_queue *rxq,
 439                                        struct rte_mbuf *mb,
 440                                        volatile union iavf_rx_flex_desc *rxdp)
 441 {
 442         volatile struct iavf_32b_rx_flex_desc_comms *desc =
 443                         (volatile struct iavf_32b_rx_flex_desc_comms *)rxdp;
 444         uint16_t stat_err;
 445
 446         stat_err = rte_le_to_cpu_16(desc->status_error0);
 447         if (likely(stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
 448                 mb->ol_flags |= PKT_RX_RSS_HASH;
 449                 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
 450         }
 451
 452 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
 453         if (desc->flow_id != 0xFFFFFFFF) {
 454                 mb->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
 455                 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
 456         }
 457
 458         if (rxq->xtr_ol_flag) {
 459                 uint32_t metadata = 0;
 460
 461                 if (desc->flex_ts.flex.aux0 != 0xFFFF)
 462                         metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux0);
 463                 else if (desc->flex_ts.flex.aux1 != 0xFFFF)
 464                         metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux1);
 465
 466                 if (metadata) {
 467                         mb->ol_flags |= rxq->xtr_ol_flag;
 468
 469                         *RTE_PMD_IFD_DYNF_PROTO_XTR_METADATA(mb) = metadata;
 470                 }
 471         }
 472 #endif
 473 }
 474
 475 static void
 476 iavf_select_rxd_to_pkt_fields_handler(struct iavf_rx_queue *rxq, uint32_t rxdid)
 477 {
 478         switch (rxdid) {
 479         case IAVF_RXDID_COMMS_AUX_VLAN:
 480                 rxq->xtr_ol_flag = rte_pmd_ifd_dynflag_proto_xtr_vlan_mask;
 481                 rxq->rxd_to_pkt_fields =
 482                         iavf_rxd_to_pkt_fields_by_comms_aux_v1;
 483                 break;
 484         case IAVF_RXDID_COMMS_AUX_IPV4:
 485                 rxq->xtr_ol_flag = rte_pmd_ifd_dynflag_proto_xtr_ipv4_mask;
 486                 rxq->rxd_to_pkt_fields =
 487                         iavf_rxd_to_pkt_fields_by_comms_aux_v1;
 488                 break;
 489         case IAVF_RXDID_COMMS_AUX_IPV6:
 490                 rxq->xtr_ol_flag = rte_pmd_ifd_dynflag_proto_xtr_ipv6_mask;
 491                 rxq->rxd_to_pkt_fields =
 492                         iavf_rxd_to_pkt_fields_by_comms_aux_v1;
 493                 break;
 494         case IAVF_RXDID_COMMS_AUX_IPV6_FLOW:
 495                 rxq->xtr_ol_flag =
 496                         rte_pmd_ifd_dynflag_proto_xtr_ipv6_flow_mask;
 497                 rxq->rxd_to_pkt_fields =
 498                         iavf_rxd_to_pkt_fields_by_comms_aux_v1;
 499                 break;
 500         case IAVF_RXDID_COMMS_AUX_TCP:
 501                 rxq->xtr_ol_flag = rte_pmd_ifd_dynflag_proto_xtr_tcp_mask;
 502                 rxq->rxd_to_pkt_fields =
 503                         iavf_rxd_to_pkt_fields_by_comms_aux_v1;
 504                 break;
 505         case IAVF_RXDID_COMMS_AUX_IP_OFFSET:
 506                 rxq->xtr_ol_flag =
 507                         rte_pmd_ifd_dynflag_proto_xtr_ip_offset_mask;
 508                 rxq->rxd_to_pkt_fields =
 509                         iavf_rxd_to_pkt_fields_by_comms_aux_v2;
 510                 break;
 511         case IAVF_RXDID_COMMS_OVS_1:
 512                 rxq->rxd_to_pkt_fields = iavf_rxd_to_pkt_fields_by_comms_ovs;
 513                 break;
 514         default:
 515                 /* update this according to the RXDID for FLEX_DESC_NONE */
 516                 rxq->rxd_to_pkt_fields = iavf_rxd_to_pkt_fields_by_comms_ovs;
 517                 break;
 518         }
 519
 520         if (!rte_pmd_ifd_dynf_proto_xtr_metadata_avail())
 521                 rxq->xtr_ol_flag = 0;
 522 }
 523
 524 int
 525 iavf_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 526                        uint16_t nb_desc, unsigned int socket_id,
 527                        const struct rte_eth_rxconf *rx_conf,
 528                        struct rte_mempool *mp)
 529 {
 530         struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 531         struct iavf_adapter *ad =
 532                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 533         struct iavf_info *vf =
 534                 IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 535         struct iavf_vsi *vsi = &vf->vsi;
 536         struct iavf_rx_queue *rxq;
 537         const struct rte_memzone *mz;
 538         uint32_t ring_size;
 539         uint8_t proto_xtr;
 540         uint16_t len;
 541         uint16_t rx_free_thresh;
 542         uint64_t offloads;
 543
 544         PMD_INIT_FUNC_TRACE();
 545
 546         offloads = rx_conf->offloads | dev->data->dev_conf.rxmode.offloads;
 547
 548         if (nb_desc % IAVF_ALIGN_RING_DESC != 0 ||
 549             nb_desc > IAVF_MAX_RING_DESC ||
 550             nb_desc < IAVF_MIN_RING_DESC) {
 551                 PMD_INIT_LOG(ERR, "Number (%u) of receive descriptors is "
 552                              "invalid", nb_desc);
 553                 return -EINVAL;
 554         }
 555
 556         /* Check free threshold */
 557         rx_free_thresh = (rx_conf->rx_free_thresh == 0) ?
 558                          IAVF_DEFAULT_RX_FREE_THRESH :
 559                          rx_conf->rx_free_thresh;
 560         if (check_rx_thresh(nb_desc, rx_free_thresh) != 0)
 561                 return -EINVAL;
 562
 563         /* Free memory if needed */
 564         if (dev->data->rx_queues[queue_idx]) {
 565                 iavf_dev_rx_queue_release(dev, queue_idx);
 566                 dev->data->rx_queues[queue_idx] = NULL;
 567         }
 568
 569         /* Allocate the rx queue data structure */
 570         rxq = rte_zmalloc_socket("iavf rxq",
 571                                  sizeof(struct iavf_rx_queue),
 572                                  RTE_CACHE_LINE_SIZE,
 573                                  socket_id);
 574         if (!rxq) {
 575                 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
 576                              "rx queue data structure");
 577                 return -ENOMEM;
 578         }
 579
 580         if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC) {
 581                 proto_xtr = vf->proto_xtr ? vf->proto_xtr[queue_idx] :
 582                                 IAVF_PROTO_XTR_NONE;
 583                 rxq->rxdid = iavf_proto_xtr_type_to_rxdid(proto_xtr);
 584                 rxq->proto_xtr = proto_xtr;
 585         } else {
 586                 rxq->rxdid = IAVF_RXDID_LEGACY_1;
 587                 rxq->proto_xtr = IAVF_PROTO_XTR_NONE;
 588         }
 589
 590         if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_VLAN_V2) {
 591                 struct virtchnl_vlan_supported_caps *stripping_support =
 592                                 &vf->vlan_v2_caps.offloads.stripping_support;
 593                 uint32_t stripping_cap;
 594
 595                 if (stripping_support->outer)
 596                         stripping_cap = stripping_support->outer;
 597                 else
 598                         stripping_cap = stripping_support->inner;
 599
 600                 if (stripping_cap & VIRTCHNL_VLAN_TAG_LOCATION_L2TAG1)
 601                         rxq->rx_flags = IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG1;
 602                 else if (stripping_cap & VIRTCHNL_VLAN_TAG_LOCATION_L2TAG2_2)
 603                         rxq->rx_flags = IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG2_2;
 604         } else {
 605                 rxq->rx_flags = IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG1;
 606         }
 607
 608         iavf_select_rxd_to_pkt_fields_handler(rxq, rxq->rxdid);
 609
 610         rxq->mp = mp;
 611         rxq->nb_rx_desc = nb_desc;
 612         rxq->rx_free_thresh = rx_free_thresh;
 613         rxq->queue_id = queue_idx;
 614         rxq->port_id = dev->data->port_id;
 615         rxq->rx_deferred_start = rx_conf->rx_deferred_start;
 616         rxq->rx_hdr_len = 0;
 617         rxq->vsi = vsi;
 618         rxq->offloads = offloads;
 619
 620         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
 621                 rxq->crc_len = RTE_ETHER_CRC_LEN;
 622         else
 623                 rxq->crc_len = 0;
 624
 625         len = rte_pktmbuf_data_room_size(rxq->mp) - RTE_PKTMBUF_HEADROOM;
 626         rxq->rx_buf_len = RTE_ALIGN_FLOOR(len, (1 << IAVF_RXQ_CTX_DBUFF_SHIFT));
 627
 628         /* Allocate the software ring. */
 629         len = nb_desc + IAVF_RX_MAX_BURST;
 630         rxq->sw_ring =
 631                 rte_zmalloc_socket("iavf rx sw ring",
 632                                    sizeof(struct rte_mbuf *) * len,
 633                                    RTE_CACHE_LINE_SIZE,
 634                                    socket_id);
 635         if (!rxq->sw_ring) {
 636                 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW ring");
 637                 rte_free(rxq);
 638                 return -ENOMEM;
 639         }
 640
 641         /* Allocate the maximun number of RX ring hardware descriptor with
 642          * a liitle more to support bulk allocate.
 643          */
 644         len = IAVF_MAX_RING_DESC + IAVF_RX_MAX_BURST;
 645         ring_size = RTE_ALIGN(len * sizeof(union iavf_rx_desc),
 646                               IAVF_DMA_MEM_ALIGN);
 647         mz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
 648                                       ring_size, IAVF_RING_BASE_ALIGN,
 649                                       socket_id);
 650         if (!mz) {
 651                 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for RX");
 652                 rte_free(rxq->sw_ring);
 653                 rte_free(rxq);
 654                 return -ENOMEM;
 655         }
 656         /* Zero all the descriptors in the ring. */
 657         memset(mz->addr, 0, ring_size);
 658         rxq->rx_ring_phys_addr = mz->iova;
 659         rxq->rx_ring = (union iavf_rx_desc *)mz->addr;
 660
 661         rxq->mz = mz;
 662         reset_rx_queue(rxq);
 663         rxq->q_set = true;
 664         dev->data->rx_queues[queue_idx] = rxq;
 665         rxq->qrx_tail = hw->hw_addr + IAVF_QRX_TAIL1(rxq->queue_id);
 666         rxq->ops = &def_rxq_ops;
 667
 668         if (check_rx_bulk_allow(rxq) == true) {
 669                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
 670                              "satisfied. Rx Burst Bulk Alloc function will be "
 671                              "used on port=%d, queue=%d.",
 672                              rxq->port_id, rxq->queue_id);
 673         } else {
 674                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
 675                              "not satisfied, Scattered Rx is requested "
 676                              "on port=%d, queue=%d.",
 677                              rxq->port_id, rxq->queue_id);
 678                 ad->rx_bulk_alloc_allowed = false;
 679         }
 680
 681         if (check_rx_vec_allow(rxq) == false)
 682                 ad->rx_vec_allowed = false;
 683
 684         return 0;
 685 }
 686
 687 int
 688 iavf_dev_tx_queue_setup(struct rte_eth_dev *dev,
 689                        uint16_t queue_idx,
 690                        uint16_t nb_desc,
 691                        unsigned int socket_id,
 692                        const struct rte_eth_txconf *tx_conf)
 693 {
 694         struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 695         struct iavf_info *vf =
 696                 IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 697         struct iavf_tx_queue *txq;
 698         const struct rte_memzone *mz;
 699         uint32_t ring_size;
 700         uint16_t tx_rs_thresh, tx_free_thresh;
 701         uint64_t offloads;
 702
 703         PMD_INIT_FUNC_TRACE();
 704
 705         offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
 706
 707         if (nb_desc % IAVF_ALIGN_RING_DESC != 0 ||
 708             nb_desc > IAVF_MAX_RING_DESC ||
 709             nb_desc < IAVF_MIN_RING_DESC) {
 710                 PMD_INIT_LOG(ERR, "Number (%u) of transmit descriptors is "
 711                             "invalid", nb_desc);
 712                 return -EINVAL;
 713         }
 714
 715         tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
 716                 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
 717         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
 718                 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
 719         if (check_tx_thresh(nb_desc, tx_rs_thresh, tx_free_thresh) != 0)
 720                 return -EINVAL;
 721
 722         /* Free memory if needed. */
 723         if (dev->data->tx_queues[queue_idx]) {
 724                 iavf_dev_tx_queue_release(dev, queue_idx);
 725                 dev->data->tx_queues[queue_idx] = NULL;
 726         }
 727
 728         /* Allocate the TX queue data structure. */
 729         txq = rte_zmalloc_socket("iavf txq",
 730                                  sizeof(struct iavf_tx_queue),
 731                                  RTE_CACHE_LINE_SIZE,
 732                                  socket_id);
 733         if (!txq) {
 734                 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
 735                              "tx queue structure");
 736                 return -ENOMEM;
 737         }
 738
 739         if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_VLAN_V2) {
 740                 struct virtchnl_vlan_supported_caps *insertion_support =
 741                         &vf->vlan_v2_caps.offloads.insertion_support;
 742                 uint32_t insertion_cap;
 743
 744                 if (insertion_support->outer)
 745                         insertion_cap = insertion_support->outer;
 746                 else
 747                         insertion_cap = insertion_support->inner;
 748
 749                 if (insertion_cap & VIRTCHNL_VLAN_TAG_LOCATION_L2TAG1)
 750                         txq->vlan_flag = IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG1;
 751                 else if (insertion_cap & VIRTCHNL_VLAN_TAG_LOCATION_L2TAG2)
 752                         txq->vlan_flag = IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG2;
 753         } else {
 754                 txq->vlan_flag = IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG1;
 755         }
 756
 757         txq->nb_tx_desc = nb_desc;
 758         txq->rs_thresh = tx_rs_thresh;
 759         txq->free_thresh = tx_free_thresh;
 760         txq->queue_id = queue_idx;
 761         txq->port_id = dev->data->port_id;
 762         txq->offloads = offloads;
 763         txq->tx_deferred_start = tx_conf->tx_deferred_start;
 764
 765         /* Allocate software ring */
 766         txq->sw_ring =
 767                 rte_zmalloc_socket("iavf tx sw ring",
 768                                    sizeof(struct iavf_tx_entry) * nb_desc,
 769                                    RTE_CACHE_LINE_SIZE,
 770                                    socket_id);
 771         if (!txq->sw_ring) {
 772                 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW TX ring");
 773                 rte_free(txq);
 774                 return -ENOMEM;
 775         }
 776
 777         /* Allocate TX hardware ring descriptors. */
 778         ring_size = sizeof(struct iavf_tx_desc) * IAVF_MAX_RING_DESC;
 779         ring_size = RTE_ALIGN(ring_size, IAVF_DMA_MEM_ALIGN);
 780         mz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
 781                                       ring_size, IAVF_RING_BASE_ALIGN,
 782                                       socket_id);
 783         if (!mz) {
 784                 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for TX");
 785                 rte_free(txq->sw_ring);
 786                 rte_free(txq);
 787                 return -ENOMEM;
 788         }
 789         txq->tx_ring_phys_addr = mz->iova;
 790         txq->tx_ring = (struct iavf_tx_desc *)mz->addr;
 791
 792         txq->mz = mz;
 793         reset_tx_queue(txq);
 794         txq->q_set = true;
 795         dev->data->tx_queues[queue_idx] = txq;
 796         txq->qtx_tail = hw->hw_addr + IAVF_QTX_TAIL1(queue_idx);
 797         txq->ops = &def_txq_ops;
 798
 799         if (check_tx_vec_allow(txq) == false) {
 800                 struct iavf_adapter *ad =
 801                         IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 802                 ad->tx_vec_allowed = false;
 803         }
 804
 805         if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_QOS &&
 806             vf->tm_conf.committed) {
 807                 int tc;
 808                 for (tc = 0; tc < vf->qos_cap->num_elem; tc++) {
 809                         if (txq->queue_id >= vf->qtc_map[tc].start_queue_id &&
 810                             txq->queue_id < (vf->qtc_map[tc].start_queue_id +
 811                             vf->qtc_map[tc].queue_count))
 812                                 break;
 813                 }
 814                 if (tc >= vf->qos_cap->num_elem) {
 815                         PMD_INIT_LOG(ERR, "Queue TC mapping is not correct");
 816                         return -EINVAL;
 817                 }
 818                 txq->tc = tc;
 819         }
 820
 821         return 0;
 822 }
 823
 824 int
 825 iavf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 826 {
 827         struct iavf_adapter *adapter =
 828                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 829         struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 830         struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 831         struct iavf_rx_queue *rxq;
 832         int err = 0;
 833
 834         PMD_DRV_FUNC_TRACE();
 835
 836         if (rx_queue_id >= dev->data->nb_rx_queues)
 837                 return -EINVAL;
 838
 839         rxq = dev->data->rx_queues[rx_queue_id];
 840
 841         err = alloc_rxq_mbufs(rxq);
 842         if (err) {
 843                 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
 844                 return err;
 845         }
 846
 847         rte_wmb();
 848
 849         /* Init the RX tail register. */
 850         IAVF_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 851         IAVF_WRITE_FLUSH(hw);
 852
 853         /* Ready to switch the queue on */
 854         if (!vf->lv_enabled)
 855                 err = iavf_switch_queue(adapter, rx_queue_id, true, true);
 856         else
 857                 err = iavf_switch_queue_lv(adapter, rx_queue_id, true, true);
 858
 859         if (err) {
 860                 release_rxq_mbufs(rxq);
 861                 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
 862                             rx_queue_id);
 863         } else {
 864                 dev->data->rx_queue_state[rx_queue_id] =
 865                         RTE_ETH_QUEUE_STATE_STARTED;
 866         }
 867
 868         return err;
 869 }
 870
 871 int
 872 iavf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 873 {
 874         struct iavf_adapter *adapter =
 875                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 876         struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 877         struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 878         struct iavf_tx_queue *txq;
 879         int err = 0;
 880
 881         PMD_DRV_FUNC_TRACE();
 882
 883         if (tx_queue_id >= dev->data->nb_tx_queues)
 884                 return -EINVAL;
 885
 886         txq = dev->data->tx_queues[tx_queue_id];
 887
 888         /* Init the RX tail register. */
 889         IAVF_PCI_REG_WRITE(txq->qtx_tail, 0);
 890         IAVF_WRITE_FLUSH(hw);
 891
 892         /* Ready to switch the queue on */
 893         if (!vf->lv_enabled)
 894                 err = iavf_switch_queue(adapter, tx_queue_id, false, true);
 895         else
 896                 err = iavf_switch_queue_lv(adapter, tx_queue_id, false, true);
 897
 898         if (err)
 899                 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
 900                             tx_queue_id);
 901         else
 902                 dev->data->tx_queue_state[tx_queue_id] =
 903                         RTE_ETH_QUEUE_STATE_STARTED;
 904
 905         return err;
 906 }
 907
 908 int
 909 iavf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 910 {
 911         struct iavf_adapter *adapter =
 912                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 913         struct iavf_rx_queue *rxq;
 914         int err;
 915
 916         PMD_DRV_FUNC_TRACE();
 917
 918         if (rx_queue_id >= dev->data->nb_rx_queues)
 919                 return -EINVAL;
 920
 921         err = iavf_switch_queue(adapter, rx_queue_id, true, false);
 922         if (err) {
 923                 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
 924                             rx_queue_id);
 925                 return err;
 926         }
 927
 928         rxq = dev->data->rx_queues[rx_queue_id];
 929         rxq->ops->release_mbufs(rxq);
 930         reset_rx_queue(rxq);
 931         dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 932
 933         return 0;
 934 }
 935
 936 int
 937 iavf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 938 {
 939         struct iavf_adapter *adapter =
 940                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 941         struct iavf_tx_queue *txq;
 942         int err;
 943
 944         PMD_DRV_FUNC_TRACE();
 945
 946         if (tx_queue_id >= dev->data->nb_tx_queues)
 947                 return -EINVAL;
 948
 949         err = iavf_switch_queue(adapter, tx_queue_id, false, false);
 950         if (err) {
 951                 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u off",
 952                             tx_queue_id);
 953                 return err;
 954         }
 955
 956         txq = dev->data->tx_queues[tx_queue_id];
 957         txq->ops->release_mbufs(txq);
 958         reset_tx_queue(txq);
 959         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 960
 961         return 0;
 962 }
 963
 964 void
 965 iavf_dev_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
 966 {
 967         struct iavf_rx_queue *q = dev->data->rx_queues[qid];
 968
 969         if (!q)
 970                 return;
 971
 972         q->ops->release_mbufs(q);
 973         rte_free(q->sw_ring);
 974         rte_memzone_free(q->mz);
 975         rte_free(q);
 976 }
 977
 978 void
 979 iavf_dev_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
 980 {
 981         struct iavf_tx_queue *q = dev->data->tx_queues[qid];
 982
 983         if (!q)
 984                 return;
 985
 986         q->ops->release_mbufs(q);
 987         rte_free(q->sw_ring);
 988         rte_memzone_free(q->mz);
 989         rte_free(q);
 990 }
 991
 992 void
 993 iavf_stop_queues(struct rte_eth_dev *dev)
 994 {
 995         struct iavf_adapter *adapter =
 996                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 997         struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 998         struct iavf_rx_queue *rxq;
 999         struct iavf_tx_queue *txq;
1000         int ret, i;
1001
1002         /* Stop All queues */
1003         if (!vf->lv_enabled) {
1004                 ret = iavf_disable_queues(adapter);
1005                 if (ret)
1006                         PMD_DRV_LOG(WARNING, "Fail to stop queues");
1007         } else {
1008                 ret = iavf_disable_queues_lv(adapter);
1009                 if (ret)
1010                         PMD_DRV_LOG(WARNING, "Fail to stop queues for large VF");
1011         }
1012
1013         if (ret)
1014                 PMD_DRV_LOG(WARNING, "Fail to stop queues");
1015
1016         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1017                 txq = dev->data->tx_queues[i];
1018                 if (!txq)
1019                         continue;
1020                 txq->ops->release_mbufs(txq);
1021                 reset_tx_queue(txq);
1022                 dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED;
1023         }
1024         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1025                 rxq = dev->data->rx_queues[i];
1026                 if (!rxq)
1027                         continue;
1028                 rxq->ops->release_mbufs(rxq);
1029                 reset_rx_queue(rxq);
1030                 dev->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED;
1031         }
1032 }
1033
1034 #define IAVF_RX_FLEX_ERR0_BITS  \
1035         ((1 << IAVF_RX_FLEX_DESC_STATUS0_HBO_S) |       \
1036          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_IPE_S) |  \
1037          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_L4E_S) |  \
1038          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S) | \
1039          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S) |        \
1040          (1 << IAVF_RX_FLEX_DESC_STATUS0_RXE_S))
1041
1042 static inline void
1043 iavf_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union iavf_rx_desc *rxdp)
1044 {
1045         if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1046                 (1 << IAVF_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
1047                 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1048                 mb->vlan_tci =
1049                         rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
1050         } else {
1051                 mb->vlan_tci = 0;
1052         }
1053 }
1054
1055 static inline void
1056 iavf_flex_rxd_to_vlan_tci(struct rte_mbuf *mb,
1057                           volatile union iavf_rx_flex_desc *rxdp,
1058                           uint8_t rx_flags)
1059 {
1060         uint16_t vlan_tci = 0;
1061
1062         if (rx_flags & IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG1 &&
1063             rte_le_to_cpu_64(rxdp->wb.status_error0) &
1064             (1 << IAVF_RX_FLEX_DESC_STATUS0_L2TAG1P_S))
1065                 vlan_tci = rte_le_to_cpu_16(rxdp->wb.l2tag1);
1066
1067 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
1068         if (rx_flags & IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG2_2 &&
1069             rte_le_to_cpu_16(rxdp->wb.status_error1) &
1070             (1 << IAVF_RX_FLEX_DESC_STATUS1_L2TAG2P_S))
1071                 vlan_tci = rte_le_to_cpu_16(rxdp->wb.l2tag2_2nd);
1072 #endif
1073
1074         if (vlan_tci) {
1075                 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1076                 mb->vlan_tci = vlan_tci;
1077         }
1078 }
1079
1080 /* Translate the rx descriptor status and error fields to pkt flags */
1081 static inline uint64_t
1082 iavf_rxd_to_pkt_flags(uint64_t qword)
1083 {
1084         uint64_t flags;
1085         uint64_t error_bits = (qword >> IAVF_RXD_QW1_ERROR_SHIFT);
1086
1087 #define IAVF_RX_ERR_BITS 0x3f
1088
1089         /* Check if RSS_HASH */
1090         flags = (((qword >> IAVF_RX_DESC_STATUS_FLTSTAT_SHIFT) &
1091                                         IAVF_RX_DESC_FLTSTAT_RSS_HASH) ==
1092                         IAVF_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;
1093
1094         /* Check if FDIR Match */
1095         flags |= (qword & (1 << IAVF_RX_DESC_STATUS_FLM_SHIFT) ?
1096                                 PKT_RX_FDIR : 0);
1097
1098         if (likely((error_bits & IAVF_RX_ERR_BITS) == 0)) {
1099                 flags |= (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD);
1100                 return flags;
1101         }
1102
1103         if (unlikely(error_bits & (1 << IAVF_RX_DESC_ERROR_IPE_SHIFT)))
1104                 flags |= PKT_RX_IP_CKSUM_BAD;
1105         else
1106                 flags |= PKT_RX_IP_CKSUM_GOOD;
1107
1108         if (unlikely(error_bits & (1 << IAVF_RX_DESC_ERROR_L4E_SHIFT)))
1109                 flags |= PKT_RX_L4_CKSUM_BAD;
1110         else
1111                 flags |= PKT_RX_L4_CKSUM_GOOD;
1112
1113         /* TODO: Oversize error bit is not processed here */
1114
1115         return flags;
1116 }
1117
1118 static inline uint64_t
1119 iavf_rxd_build_fdir(volatile union iavf_rx_desc *rxdp, struct rte_mbuf *mb)
1120 {
1121         uint64_t flags = 0;
1122 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
1123         uint16_t flexbh;
1124
1125         flexbh = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
1126                 IAVF_RX_DESC_EXT_STATUS_FLEXBH_SHIFT) &
1127                 IAVF_RX_DESC_EXT_STATUS_FLEXBH_MASK;
1128
1129         if (flexbh == IAVF_RX_DESC_EXT_STATUS_FLEXBH_FD_ID) {
1130                 mb->hash.fdir.hi =
1131                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.fd_id);
1132                 flags |= PKT_RX_FDIR_ID;
1133         }
1134 #else
1135         mb->hash.fdir.hi =
1136                 rte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.fd_id);
1137         flags |= PKT_RX_FDIR_ID;
1138 #endif
1139         return flags;
1140 }
1141
1142 #define IAVF_RX_FLEX_ERR0_BITS  \
1143         ((1 << IAVF_RX_FLEX_DESC_STATUS0_HBO_S) |       \
1144          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_IPE_S) |  \
1145          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_L4E_S) |  \
1146          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S) | \
1147          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S) |        \
1148          (1 << IAVF_RX_FLEX_DESC_STATUS0_RXE_S))
1149
1150 /* Rx L3/L4 checksum */
1151 static inline uint64_t
1152 iavf_flex_rxd_error_to_pkt_flags(uint16_t stat_err0)
1153 {
1154         uint64_t flags = 0;
1155
1156         /* check if HW has decoded the packet and checksum */
1157         if (unlikely(!(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_L3L4P_S))))
1158                 return 0;
1159
1160         if (likely(!(stat_err0 & IAVF_RX_FLEX_ERR0_BITS))) {
1161                 flags |= (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD);
1162                 return flags;
1163         }
1164
1165         if (unlikely(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_IPE_S)))
1166                 flags |= PKT_RX_IP_CKSUM_BAD;
1167         else
1168                 flags |= PKT_RX_IP_CKSUM_GOOD;
1169
1170         if (unlikely(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_L4E_S)))
1171                 flags |= PKT_RX_L4_CKSUM_BAD;
1172         else
1173                 flags |= PKT_RX_L4_CKSUM_GOOD;
1174
1175         if (unlikely(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S)))
1176                 flags |= PKT_RX_OUTER_IP_CKSUM_BAD;
1177
1178         return flags;
1179 }
1180
1181 /* If the number of free RX descriptors is greater than the RX free
1182  * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1183  * register. Update the RDT with the value of the last processed RX
1184  * descriptor minus 1, to guarantee that the RDT register is never
1185  * equal to the RDH register, which creates a "full" ring situation
1186  * from the hardware point of view.
1187  */
1188 static inline void
1189 iavf_update_rx_tail(struct iavf_rx_queue *rxq, uint16_t nb_hold, uint16_t rx_id)
1190 {
1191         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1192
1193         if (nb_hold > rxq->rx_free_thresh) {
1194                 PMD_RX_LOG(DEBUG,
1195                            "port_id=%u queue_id=%u rx_tail=%u nb_hold=%u",
1196                            rxq->port_id, rxq->queue_id, rx_id, nb_hold);
1197                 rx_id = (uint16_t)((rx_id == 0) ?
1198                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
1199                 IAVF_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
1200                 nb_hold = 0;
1201         }
1202         rxq->nb_rx_hold = nb_hold;
1203 }
1204
1205 /* implement recv_pkts */
1206 uint16_t
1207 iavf_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1208 {
1209         volatile union iavf_rx_desc *rx_ring;
1210         volatile union iavf_rx_desc *rxdp;
1211         struct iavf_rx_queue *rxq;
1212         union iavf_rx_desc rxd;
1213         struct rte_mbuf *rxe;
1214         struct rte_eth_dev *dev;
1215         struct rte_mbuf *rxm;
1216         struct rte_mbuf *nmb;
1217         uint16_t nb_rx;
1218         uint32_t rx_status;
1219         uint64_t qword1;
1220         uint16_t rx_packet_len;
1221         uint16_t rx_id, nb_hold;
1222         uint64_t dma_addr;
1223         uint64_t pkt_flags;
1224         const uint32_t *ptype_tbl;
1225
1226         nb_rx = 0;
1227         nb_hold = 0;
1228         rxq = rx_queue;
1229         rx_id = rxq->rx_tail;
1230         rx_ring = rxq->rx_ring;
1231         ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1232
1233         while (nb_rx < nb_pkts) {
1234                 rxdp = &rx_ring[rx_id];
1235                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1236                 rx_status = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
1237                             IAVF_RXD_QW1_STATUS_SHIFT;
1238
1239                 /* Check the DD bit first */
1240                 if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)))
1241                         break;
1242                 IAVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
1243
1244                 nmb = rte_mbuf_raw_alloc(rxq->mp);
1245                 if (unlikely(!nmb)) {
1246                         dev = &rte_eth_devices[rxq->port_id];
1247                         dev->data->rx_mbuf_alloc_failed++;
1248                         PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1249                                    "queue_id=%u", rxq->port_id, rxq->queue_id);
1250                         break;
1251                 }
1252
1253                 rxd = *rxdp;
1254                 nb_hold++;
1255                 rxe = rxq->sw_ring[rx_id];
1256                 rxq->sw_ring[rx_id] = nmb;
1257                 rx_id++;
1258                 if (unlikely(rx_id == rxq->nb_rx_desc))
1259                         rx_id = 0;
1260
1261                 /* Prefetch next mbuf */
1262                 rte_prefetch0(rxq->sw_ring[rx_id]);
1263
1264                 /* When next RX descriptor is on a cache line boundary,
1265                  * prefetch the next 4 RX descriptors and next 8 pointers
1266                  * to mbufs.
1267                  */
1268                 if ((rx_id & 0x3) == 0) {
1269                         rte_prefetch0(&rx_ring[rx_id]);
1270                         rte_prefetch0(rxq->sw_ring[rx_id]);
1271                 }
1272                 rxm = rxe;
1273                 dma_addr =
1274                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1275                 rxdp->read.hdr_addr = 0;
1276                 rxdp->read.pkt_addr = dma_addr;
1277
1278                 rx_packet_len = ((qword1 & IAVF_RXD_QW1_LENGTH_PBUF_MASK) >>
1279                                 IAVF_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
1280
1281                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1282                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
1283                 rxm->nb_segs = 1;
1284                 rxm->next = NULL;
1285                 rxm->pkt_len = rx_packet_len;
1286                 rxm->data_len = rx_packet_len;
1287                 rxm->port = rxq->port_id;
1288                 rxm->ol_flags = 0;
1289                 iavf_rxd_to_vlan_tci(rxm, &rxd);
1290                 pkt_flags = iavf_rxd_to_pkt_flags(qword1);
1291                 rxm->packet_type =
1292                         ptype_tbl[(uint8_t)((qword1 &
1293                         IAVF_RXD_QW1_PTYPE_MASK) >> IAVF_RXD_QW1_PTYPE_SHIFT)];
1294
1295                 if (pkt_flags & PKT_RX_RSS_HASH)
1296                         rxm->hash.rss =
1297                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1298
1299                 if (pkt_flags & PKT_RX_FDIR)
1300                         pkt_flags |= iavf_rxd_build_fdir(&rxd, rxm);
1301
1302                 rxm->ol_flags |= pkt_flags;
1303
1304                 rx_pkts[nb_rx++] = rxm;
1305         }
1306         rxq->rx_tail = rx_id;
1307
1308         iavf_update_rx_tail(rxq, nb_hold, rx_id);
1309
1310         return nb_rx;
1311 }
1312
1313 /* implement recv_pkts for flexible Rx descriptor */
1314 uint16_t
1315 iavf_recv_pkts_flex_rxd(void *rx_queue,
1316                         struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1317 {
1318         volatile union iavf_rx_desc *rx_ring;
1319         volatile union iavf_rx_flex_desc *rxdp;
1320         struct iavf_rx_queue *rxq;
1321         union iavf_rx_flex_desc rxd;
1322         struct rte_mbuf *rxe;
1323         struct rte_eth_dev *dev;
1324         struct rte_mbuf *rxm;
1325         struct rte_mbuf *nmb;
1326         uint16_t nb_rx;
1327         uint16_t rx_stat_err0;
1328         uint16_t rx_packet_len;
1329         uint16_t rx_id, nb_hold;
1330         uint64_t dma_addr;
1331         uint64_t pkt_flags;
1332         const uint32_t *ptype_tbl;
1333
1334         nb_rx = 0;
1335         nb_hold = 0;
1336         rxq = rx_queue;
1337         rx_id = rxq->rx_tail;
1338         rx_ring = rxq->rx_ring;
1339         ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1340
1341         while (nb_rx < nb_pkts) {
1342                 rxdp = (volatile union iavf_rx_flex_desc *)&rx_ring[rx_id];
1343                 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1344
1345                 /* Check the DD bit first */
1346                 if (!(rx_stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S)))
1347                         break;
1348                 IAVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
1349
1350                 nmb = rte_mbuf_raw_alloc(rxq->mp);
1351                 if (unlikely(!nmb)) {
1352                         dev = &rte_eth_devices[rxq->port_id];
1353                         dev->data->rx_mbuf_alloc_failed++;
1354                         PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1355                                    "queue_id=%u", rxq->port_id, rxq->queue_id);
1356                         break;
1357                 }
1358
1359                 rxd = *rxdp;
1360                 nb_hold++;
1361                 rxe = rxq->sw_ring[rx_id];
1362                 rxq->sw_ring[rx_id] = nmb;
1363                 rx_id++;
1364                 if (unlikely(rx_id == rxq->nb_rx_desc))
1365                         rx_id = 0;
1366
1367                 /* Prefetch next mbuf */
1368                 rte_prefetch0(rxq->sw_ring[rx_id]);
1369
1370                 /* When next RX descriptor is on a cache line boundary,
1371                  * prefetch the next 4 RX descriptors and next 8 pointers
1372                  * to mbufs.
1373                  */
1374                 if ((rx_id & 0x3) == 0) {
1375                         rte_prefetch0(&rx_ring[rx_id]);
1376                         rte_prefetch0(rxq->sw_ring[rx_id]);
1377                 }
1378                 rxm = rxe;
1379                 dma_addr =
1380                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1381                 rxdp->read.hdr_addr = 0;
1382                 rxdp->read.pkt_addr = dma_addr;
1383
1384                 rx_packet_len = (rte_le_to_cpu_16(rxd.wb.pkt_len) &
1385                                 IAVF_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
1386
1387                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1388                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
1389                 rxm->nb_segs = 1;
1390                 rxm->next = NULL;
1391                 rxm->pkt_len = rx_packet_len;
1392                 rxm->data_len = rx_packet_len;
1393                 rxm->port = rxq->port_id;
1394                 rxm->ol_flags = 0;
1395                 rxm->packet_type = ptype_tbl[IAVF_RX_FLEX_DESC_PTYPE_M &
1396                         rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
1397                 iavf_flex_rxd_to_vlan_tci(rxm, &rxd, rxq->rx_flags);
1398                 rxq->rxd_to_pkt_fields(rxq, rxm, &rxd);
1399                 pkt_flags = iavf_flex_rxd_error_to_pkt_flags(rx_stat_err0);
1400                 rxm->ol_flags |= pkt_flags;
1401
1402                 rx_pkts[nb_rx++] = rxm;
1403         }
1404         rxq->rx_tail = rx_id;
1405
1406         iavf_update_rx_tail(rxq, nb_hold, rx_id);
1407
1408         return nb_rx;
1409 }
1410
1411 /* implement recv_scattered_pkts for flexible Rx descriptor */
1412 uint16_t
1413 iavf_recv_scattered_pkts_flex_rxd(void *rx_queue, struct rte_mbuf **rx_pkts,
1414                                   uint16_t nb_pkts)
1415 {
1416         struct iavf_rx_queue *rxq = rx_queue;
1417         union iavf_rx_flex_desc rxd;
1418         struct rte_mbuf *rxe;
1419         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1420         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1421         struct rte_mbuf *nmb, *rxm;
1422         uint16_t rx_id = rxq->rx_tail;
1423         uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
1424         struct rte_eth_dev *dev;
1425         uint16_t rx_stat_err0;
1426         uint64_t dma_addr;
1427         uint64_t pkt_flags;
1428
1429         volatile union iavf_rx_desc *rx_ring = rxq->rx_ring;
1430         volatile union iavf_rx_flex_desc *rxdp;
1431         const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1432
1433         while (nb_rx < nb_pkts) {
1434                 rxdp = (volatile union iavf_rx_flex_desc *)&rx_ring[rx_id];
1435                 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1436
1437                 /* Check the DD bit */
1438                 if (!(rx_stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S)))
1439                         break;
1440                 IAVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
1441
1442                 nmb = rte_mbuf_raw_alloc(rxq->mp);
1443                 if (unlikely(!nmb)) {
1444                         PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1445                                    "queue_id=%u", rxq->port_id, rxq->queue_id);
1446                         dev = &rte_eth_devices[rxq->port_id];
1447                         dev->data->rx_mbuf_alloc_failed++;
1448                         break;
1449                 }
1450
1451                 rxd = *rxdp;
1452                 nb_hold++;
1453                 rxe = rxq->sw_ring[rx_id];
1454                 rxq->sw_ring[rx_id] = nmb;
1455                 rx_id++;
1456                 if (rx_id == rxq->nb_rx_desc)
1457                         rx_id = 0;
1458
1459                 /* Prefetch next mbuf */
1460                 rte_prefetch0(rxq->sw_ring[rx_id]);
1461
1462                 /* When next RX descriptor is on a cache line boundary,
1463                  * prefetch the next 4 RX descriptors and next 8 pointers
1464                  * to mbufs.
1465                  */
1466                 if ((rx_id & 0x3) == 0) {
1467                         rte_prefetch0(&rx_ring[rx_id]);
1468                         rte_prefetch0(rxq->sw_ring[rx_id]);
1469                 }
1470
1471                 rxm = rxe;
1472                 dma_addr =
1473                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1474
1475                 /* Set data buffer address and data length of the mbuf */
1476                 rxdp->read.hdr_addr = 0;
1477                 rxdp->read.pkt_addr = dma_addr;
1478                 rx_packet_len = rte_le_to_cpu_16(rxd.wb.pkt_len) &
1479                                 IAVF_RX_FLX_DESC_PKT_LEN_M;
1480                 rxm->data_len = rx_packet_len;
1481                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1482
1483                 /* If this is the first buffer of the received packet, set the
1484                  * pointer to the first mbuf of the packet and initialize its
1485                  * context. Otherwise, update the total length and the number
1486                  * of segments of the current scattered packet, and update the
1487                  * pointer to the last mbuf of the current packet.
1488                  */
1489                 if (!first_seg) {
1490                         first_seg = rxm;
1491                         first_seg->nb_segs = 1;
1492                         first_seg->pkt_len = rx_packet_len;
1493                 } else {
1494                         first_seg->pkt_len =
1495                                 (uint16_t)(first_seg->pkt_len +
1496                                                 rx_packet_len);
1497                         first_seg->nb_segs++;
1498                         last_seg->next = rxm;
1499                 }
1500
1501                 /* If this is not the last buffer of the received packet,
1502                  * update the pointer to the last mbuf of the current scattered
1503                  * packet and continue to parse the RX ring.
1504                  */
1505                 if (!(rx_stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_EOF_S))) {
1506                         last_seg = rxm;
1507                         continue;
1508                 }
1509
1510                 /* This is the last buffer of the received packet. If the CRC
1511                  * is not stripped by the hardware:
1512                  *  - Subtract the CRC length from the total packet length.
1513                  *  - If the last buffer only contains the whole CRC or a part
1514                  *  of it, free the mbuf associated to the last buffer. If part
1515                  *  of the CRC is also contained in the previous mbuf, subtract
1516                  *  the length of that CRC part from the data length of the
1517                  *  previous mbuf.
1518                  */
1519                 rxm->next = NULL;
1520                 if (unlikely(rxq->crc_len > 0)) {
1521                         first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
1522                         if (rx_packet_len <= RTE_ETHER_CRC_LEN) {
1523                                 rte_pktmbuf_free_seg(rxm);
1524                                 first_seg->nb_segs--;
1525                                 last_seg->data_len =
1526                                         (uint16_t)(last_seg->data_len -
1527                                         (RTE_ETHER_CRC_LEN - rx_packet_len));
1528                                 last_seg->next = NULL;
1529                         } else {
1530                                 rxm->data_len = (uint16_t)(rx_packet_len -
1531                                                         RTE_ETHER_CRC_LEN);
1532                         }
1533                 }
1534
1535                 first_seg->port = rxq->port_id;
1536                 first_seg->ol_flags = 0;
1537                 first_seg->packet_type = ptype_tbl[IAVF_RX_FLEX_DESC_PTYPE_M &
1538                         rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
1539                 iavf_flex_rxd_to_vlan_tci(first_seg, &rxd, rxq->rx_flags);
1540                 rxq->rxd_to_pkt_fields(rxq, first_seg, &rxd);
1541                 pkt_flags = iavf_flex_rxd_error_to_pkt_flags(rx_stat_err0);
1542
1543                 first_seg->ol_flags |= pkt_flags;
1544
1545                 /* Prefetch data of first segment, if configured to do so. */
1546                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1547                                           first_seg->data_off));
1548                 rx_pkts[nb_rx++] = first_seg;
1549                 first_seg = NULL;
1550         }
1551
1552         /* Record index of the next RX descriptor to probe. */
1553         rxq->rx_tail = rx_id;
1554         rxq->pkt_first_seg = first_seg;
1555         rxq->pkt_last_seg = last_seg;
1556
1557         iavf_update_rx_tail(rxq, nb_hold, rx_id);
1558
1559         return nb_rx;
1560 }
1561
1562 /* implement recv_scattered_pkts  */
1563 uint16_t
1564 iavf_recv_scattered_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1565                         uint16_t nb_pkts)
1566 {
1567         struct iavf_rx_queue *rxq = rx_queue;
1568         union iavf_rx_desc rxd;
1569         struct rte_mbuf *rxe;
1570         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1571         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1572         struct rte_mbuf *nmb, *rxm;
1573         uint16_t rx_id = rxq->rx_tail;
1574         uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
1575         struct rte_eth_dev *dev;
1576         uint32_t rx_status;
1577         uint64_t qword1;
1578         uint64_t dma_addr;
1579         uint64_t pkt_flags;
1580
1581         volatile union iavf_rx_desc *rx_ring = rxq->rx_ring;
1582         volatile union iavf_rx_desc *rxdp;
1583         const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1584
1585         while (nb_rx < nb_pkts) {
1586                 rxdp = &rx_ring[rx_id];
1587                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1588                 rx_status = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
1589                             IAVF_RXD_QW1_STATUS_SHIFT;
1590
1591                 /* Check the DD bit */
1592                 if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)))
1593                         break;
1594                 IAVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
1595
1596                 nmb = rte_mbuf_raw_alloc(rxq->mp);
1597                 if (unlikely(!nmb)) {
1598                         PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1599                                    "queue_id=%u", rxq->port_id, rxq->queue_id);
1600                         dev = &rte_eth_devices[rxq->port_id];
1601                         dev->data->rx_mbuf_alloc_failed++;
1602                         break;
1603                 }
1604
1605                 rxd = *rxdp;
1606                 nb_hold++;
1607                 rxe = rxq->sw_ring[rx_id];
1608                 rxq->sw_ring[rx_id] = nmb;
1609                 rx_id++;
1610                 if (rx_id == rxq->nb_rx_desc)
1611                         rx_id = 0;
1612
1613                 /* Prefetch next mbuf */
1614                 rte_prefetch0(rxq->sw_ring[rx_id]);
1615
1616                 /* When next RX descriptor is on a cache line boundary,
1617                  * prefetch the next 4 RX descriptors and next 8 pointers
1618                  * to mbufs.
1619                  */
1620                 if ((rx_id & 0x3) == 0) {
1621                         rte_prefetch0(&rx_ring[rx_id]);
1622                         rte_prefetch0(rxq->sw_ring[rx_id]);
1623                 }
1624
1625                 rxm = rxe;
1626                 dma_addr =
1627                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1628
1629                 /* Set data buffer address and data length of the mbuf */
1630                 rxdp->read.hdr_addr = 0;
1631                 rxdp->read.pkt_addr = dma_addr;
1632                 rx_packet_len = (qword1 & IAVF_RXD_QW1_LENGTH_PBUF_MASK) >>
1633                                  IAVF_RXD_QW1_LENGTH_PBUF_SHIFT;
1634                 rxm->data_len = rx_packet_len;
1635                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1636
1637                 /* If this is the first buffer of the received packet, set the
1638                  * pointer to the first mbuf of the packet and initialize its
1639                  * context. Otherwise, update the total length and the number
1640                  * of segments of the current scattered packet, and update the
1641                  * pointer to the last mbuf of the current packet.
1642                  */
1643                 if (!first_seg) {
1644                         first_seg = rxm;
1645                         first_seg->nb_segs = 1;
1646                         first_seg->pkt_len = rx_packet_len;
1647                 } else {
1648                         first_seg->pkt_len =
1649                                 (uint16_t)(first_seg->pkt_len +
1650                                                 rx_packet_len);
1651                         first_seg->nb_segs++;
1652                         last_seg->next = rxm;
1653                 }
1654
1655                 /* If this is not the last buffer of the received packet,
1656                  * update the pointer to the last mbuf of the current scattered
1657                  * packet and continue to parse the RX ring.
1658                  */
1659                 if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_EOF_SHIFT))) {
1660                         last_seg = rxm;
1661                         continue;
1662                 }
1663
1664                 /* This is the last buffer of the received packet. If the CRC
1665                  * is not stripped by the hardware:
1666                  *  - Subtract the CRC length from the total packet length.
1667                  *  - If the last buffer only contains the whole CRC or a part
1668                  *  of it, free the mbuf associated to the last buffer. If part
1669                  *  of the CRC is also contained in the previous mbuf, subtract
1670                  *  the length of that CRC part from the data length of the
1671                  *  previous mbuf.
1672                  */
1673                 rxm->next = NULL;
1674                 if (unlikely(rxq->crc_len > 0)) {
1675                         first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
1676                         if (rx_packet_len <= RTE_ETHER_CRC_LEN) {
1677                                 rte_pktmbuf_free_seg(rxm);
1678                                 first_seg->nb_segs--;
1679                                 last_seg->data_len =
1680                                         (uint16_t)(last_seg->data_len -
1681                                         (RTE_ETHER_CRC_LEN - rx_packet_len));
1682                                 last_seg->next = NULL;
1683                         } else
1684                                 rxm->data_len = (uint16_t)(rx_packet_len -
1685                                                         RTE_ETHER_CRC_LEN);
1686                 }
1687
1688                 first_seg->port = rxq->port_id;
1689                 first_seg->ol_flags = 0;
1690                 iavf_rxd_to_vlan_tci(first_seg, &rxd);
1691                 pkt_flags = iavf_rxd_to_pkt_flags(qword1);
1692                 first_seg->packet_type =
1693                         ptype_tbl[(uint8_t)((qword1 &
1694                         IAVF_RXD_QW1_PTYPE_MASK) >> IAVF_RXD_QW1_PTYPE_SHIFT)];
1695
1696                 if (pkt_flags & PKT_RX_RSS_HASH)
1697                         first_seg->hash.rss =
1698                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1699
1700                 if (pkt_flags & PKT_RX_FDIR)
1701                         pkt_flags |= iavf_rxd_build_fdir(&rxd, first_seg);
1702
1703                 first_seg->ol_flags |= pkt_flags;
1704
1705                 /* Prefetch data of first segment, if configured to do so. */
1706                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1707                                           first_seg->data_off));
1708                 rx_pkts[nb_rx++] = first_seg;
1709                 first_seg = NULL;
1710         }
1711
1712         /* Record index of the next RX descriptor to probe. */
1713         rxq->rx_tail = rx_id;
1714         rxq->pkt_first_seg = first_seg;
1715         rxq->pkt_last_seg = last_seg;
1716
1717         iavf_update_rx_tail(rxq, nb_hold, rx_id);
1718
1719         return nb_rx;
1720 }
1721
1722 #define IAVF_LOOK_AHEAD 8
1723 static inline int
1724 iavf_rx_scan_hw_ring_flex_rxd(struct iavf_rx_queue *rxq)
1725 {
1726         volatile union iavf_rx_flex_desc *rxdp;
1727         struct rte_mbuf **rxep;
1728         struct rte_mbuf *mb;
1729         uint16_t stat_err0;
1730         uint16_t pkt_len;
1731         int32_t s[IAVF_LOOK_AHEAD], nb_dd;
1732         int32_t i, j, nb_rx = 0;
1733         uint64_t pkt_flags;
1734         const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1735
1736         rxdp = (volatile union iavf_rx_flex_desc *)&rxq->rx_ring[rxq->rx_tail];
1737         rxep = &rxq->sw_ring[rxq->rx_tail];
1738
1739         stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1740
1741         /* Make sure there is at least 1 packet to receive */
1742         if (!(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S)))
1743                 return 0;
1744
1745         /* Scan LOOK_AHEAD descriptors at a time to determine which
1746          * descriptors reference packets that are ready to be received.
1747          */
1748         for (i = 0; i < IAVF_RX_MAX_BURST; i += IAVF_LOOK_AHEAD,
1749              rxdp += IAVF_LOOK_AHEAD, rxep += IAVF_LOOK_AHEAD) {
1750                 /* Read desc statuses backwards to avoid race condition */
1751                 for (j = IAVF_LOOK_AHEAD - 1; j >= 0; j--)
1752                         s[j] = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1753
1754                 rte_smp_rmb();
1755
1756                 /* Compute how many status bits were set */
1757                 for (j = 0, nb_dd = 0; j < IAVF_LOOK_AHEAD; j++)
1758                         nb_dd += s[j] & (1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S);
1759
1760                 nb_rx += nb_dd;
1761
1762                 /* Translate descriptor info to mbuf parameters */
1763                 for (j = 0; j < nb_dd; j++) {
1764                         IAVF_DUMP_RX_DESC(rxq, &rxdp[j],
1765                                           rxq->rx_tail +
1766                                           i * IAVF_LOOK_AHEAD + j);
1767
1768                         mb = rxep[j];
1769                         pkt_len = (rte_le_to_cpu_16(rxdp[j].wb.pkt_len) &
1770                                 IAVF_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
1771                         mb->data_len = pkt_len;
1772                         mb->pkt_len = pkt_len;
1773                         mb->ol_flags = 0;
1774
1775                         mb->packet_type = ptype_tbl[IAVF_RX_FLEX_DESC_PTYPE_M &
1776                                 rte_le_to_cpu_16(rxdp[j].wb.ptype_flex_flags0)];
1777                         iavf_flex_rxd_to_vlan_tci(mb, &rxdp[j], rxq->rx_flags);
1778                         rxq->rxd_to_pkt_fields(rxq, mb, &rxdp[j]);
1779                         stat_err0 = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1780                         pkt_flags = iavf_flex_rxd_error_to_pkt_flags(stat_err0);
1781
1782                         mb->ol_flags |= pkt_flags;
1783                 }
1784
1785                 for (j = 0; j < IAVF_LOOK_AHEAD; j++)
1786                         rxq->rx_stage[i + j] = rxep[j];
1787
1788                 if (nb_dd != IAVF_LOOK_AHEAD)
1789                         break;
1790         }
1791
1792         /* Clear software ring entries */
1793         for (i = 0; i < nb_rx; i++)
1794                 rxq->sw_ring[rxq->rx_tail + i] = NULL;
1795
1796         return nb_rx;
1797 }
1798
1799 static inline int
1800 iavf_rx_scan_hw_ring(struct iavf_rx_queue *rxq)
1801 {
1802         volatile union iavf_rx_desc *rxdp;
1803         struct rte_mbuf **rxep;
1804         struct rte_mbuf *mb;
1805         uint16_t pkt_len;
1806         uint64_t qword1;
1807         uint32_t rx_status;
1808         int32_t s[IAVF_LOOK_AHEAD], nb_dd;
1809         int32_t i, j, nb_rx = 0;
1810         uint64_t pkt_flags;
1811         const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1812
1813         rxdp = &rxq->rx_ring[rxq->rx_tail];
1814         rxep = &rxq->sw_ring[rxq->rx_tail];
1815
1816         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1817         rx_status = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
1818                     IAVF_RXD_QW1_STATUS_SHIFT;
1819
1820         /* Make sure there is at least 1 packet to receive */
1821         if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)))
1822                 return 0;
1823
1824         /* Scan LOOK_AHEAD descriptors at a time to determine which
1825          * descriptors reference packets that are ready to be received.
1826          */
1827         for (i = 0; i < IAVF_RX_MAX_BURST; i += IAVF_LOOK_AHEAD,
1828              rxdp += IAVF_LOOK_AHEAD, rxep += IAVF_LOOK_AHEAD) {
1829                 /* Read desc statuses backwards to avoid race condition */
1830                 for (j = IAVF_LOOK_AHEAD - 1; j >= 0; j--) {
1831                         qword1 = rte_le_to_cpu_64(
1832                                 rxdp[j].wb.qword1.status_error_len);
1833                         s[j] = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
1834                                IAVF_RXD_QW1_STATUS_SHIFT;
1835                 }
1836
1837                 rte_smp_rmb();
1838
1839                 /* Compute how many status bits were set */
1840                 for (j = 0, nb_dd = 0; j < IAVF_LOOK_AHEAD; j++)
1841                         nb_dd += s[j] & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT);
1842
1843                 nb_rx += nb_dd;
1844
1845                 /* Translate descriptor info to mbuf parameters */
1846                 for (j = 0; j < nb_dd; j++) {
1847                         IAVF_DUMP_RX_DESC(rxq, &rxdp[j],
1848                                          rxq->rx_tail + i * IAVF_LOOK_AHEAD + j);
1849
1850                         mb = rxep[j];
1851                         qword1 = rte_le_to_cpu_64
1852                                         (rxdp[j].wb.qword1.status_error_len);
1853                         pkt_len = ((qword1 & IAVF_RXD_QW1_LENGTH_PBUF_MASK) >>
1854                                   IAVF_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
1855                         mb->data_len = pkt_len;
1856                         mb->pkt_len = pkt_len;
1857                         mb->ol_flags = 0;
1858                         iavf_rxd_to_vlan_tci(mb, &rxdp[j]);
1859                         pkt_flags = iavf_rxd_to_pkt_flags(qword1);
1860                         mb->packet_type =
1861                                 ptype_tbl[(uint8_t)((qword1 &
1862                                 IAVF_RXD_QW1_PTYPE_MASK) >>
1863                                 IAVF_RXD_QW1_PTYPE_SHIFT)];
1864
1865                         if (pkt_flags & PKT_RX_RSS_HASH)
1866                                 mb->hash.rss = rte_le_to_cpu_32(
1867                                         rxdp[j].wb.qword0.hi_dword.rss);
1868
1869                         if (pkt_flags & PKT_RX_FDIR)
1870                                 pkt_flags |= iavf_rxd_build_fdir(&rxdp[j], mb);
1871
1872                         mb->ol_flags |= pkt_flags;
1873                 }
1874
1875                 for (j = 0; j < IAVF_LOOK_AHEAD; j++)
1876                         rxq->rx_stage[i + j] = rxep[j];
1877
1878                 if (nb_dd != IAVF_LOOK_AHEAD)
1879                         break;
1880         }
1881
1882         /* Clear software ring entries */
1883         for (i = 0; i < nb_rx; i++)
1884                 rxq->sw_ring[rxq->rx_tail + i] = NULL;
1885
1886         return nb_rx;
1887 }
1888
1889 static inline uint16_t
1890 iavf_rx_fill_from_stage(struct iavf_rx_queue *rxq,
1891                        struct rte_mbuf **rx_pkts,
1892                        uint16_t nb_pkts)
1893 {
1894         uint16_t i;
1895         struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1896
1897         nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1898
1899         for (i = 0; i < nb_pkts; i++)
1900                 rx_pkts[i] = stage[i];
1901
1902         rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1903         rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1904
1905         return nb_pkts;
1906 }
1907
1908 static inline int
1909 iavf_rx_alloc_bufs(struct iavf_rx_queue *rxq)
1910 {
1911         volatile union iavf_rx_desc *rxdp;
1912         struct rte_mbuf **rxep;
1913         struct rte_mbuf *mb;
1914         uint16_t alloc_idx, i;
1915         uint64_t dma_addr;
1916         int diag;
1917
1918         /* Allocate buffers in bulk */
1919         alloc_idx = (uint16_t)(rxq->rx_free_trigger -
1920                                 (rxq->rx_free_thresh - 1));
1921         rxep = &rxq->sw_ring[alloc_idx];
1922         diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
1923                                     rxq->rx_free_thresh);
1924         if (unlikely(diag != 0)) {
1925                 PMD_RX_LOG(ERR, "Failed to get mbufs in bulk");
1926                 return -ENOMEM;
1927         }
1928
1929         rxdp = &rxq->rx_ring[alloc_idx];
1930         for (i = 0; i < rxq->rx_free_thresh; i++) {
1931                 if (likely(i < (rxq->rx_free_thresh - 1)))
1932                         /* Prefetch next mbuf */
1933                         rte_prefetch0(rxep[i + 1]);
1934
1935                 mb = rxep[i];
1936                 rte_mbuf_refcnt_set(mb, 1);
1937                 mb->next = NULL;
1938                 mb->data_off = RTE_PKTMBUF_HEADROOM;
1939                 mb->nb_segs = 1;
1940                 mb->port = rxq->port_id;
1941                 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mb));
1942                 rxdp[i].read.hdr_addr = 0;
1943                 rxdp[i].read.pkt_addr = dma_addr;
1944         }
1945
1946         /* Update rx tail register */
1947         rte_wmb();
1948         IAVF_PCI_REG_WC_WRITE_RELAXED(rxq->qrx_tail, rxq->rx_free_trigger);
1949
1950         rxq->rx_free_trigger =
1951                 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
1952         if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1953                 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
1954
1955         return 0;
1956 }
1957
1958 static inline uint16_t
1959 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1960 {
1961         struct iavf_rx_queue *rxq = (struct iavf_rx_queue *)rx_queue;
1962         uint16_t nb_rx = 0;
1963
1964         if (!nb_pkts)
1965                 return 0;
1966
1967         if (rxq->rx_nb_avail)
1968                 return iavf_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1969
1970         if (rxq->rxdid >= IAVF_RXDID_FLEX_NIC && rxq->rxdid <= IAVF_RXDID_LAST)
1971                 nb_rx = (uint16_t)iavf_rx_scan_hw_ring_flex_rxd(rxq);
1972         else
1973                 nb_rx = (uint16_t)iavf_rx_scan_hw_ring(rxq);
1974         rxq->rx_next_avail = 0;
1975         rxq->rx_nb_avail = nb_rx;
1976         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1977
1978         if (rxq->rx_tail > rxq->rx_free_trigger) {
1979                 if (iavf_rx_alloc_bufs(rxq) != 0) {
1980                         uint16_t i, j;
1981
1982                         /* TODO: count rx_mbuf_alloc_failed here */
1983
1984                         rxq->rx_nb_avail = 0;
1985                         rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1986                         for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
1987                                 rxq->sw_ring[j] = rxq->rx_stage[i];
1988
1989                         return 0;
1990                 }
1991         }
1992
1993         if (rxq->rx_tail >= rxq->nb_rx_desc)
1994                 rxq->rx_tail = 0;
1995
1996         PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u, nb_rx=%u",
1997                    rxq->port_id, rxq->queue_id,
1998                    rxq->rx_tail, nb_rx);
1999
2000         if (rxq->rx_nb_avail)
2001                 return iavf_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
2002
2003         return 0;
2004 }
2005
2006 static uint16_t
2007 iavf_recv_pkts_bulk_alloc(void *rx_queue,
2008                          struct rte_mbuf **rx_pkts,
2009                          uint16_t nb_pkts)
2010 {
2011         uint16_t nb_rx = 0, n, count;
2012
2013         if (unlikely(nb_pkts == 0))
2014                 return 0;
2015
2016         if (likely(nb_pkts <= IAVF_RX_MAX_BURST))
2017                 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
2018
2019         while (nb_pkts) {
2020                 n = RTE_MIN(nb_pkts, IAVF_RX_MAX_BURST);
2021                 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
2022                 nb_rx = (uint16_t)(nb_rx + count);
2023                 nb_pkts = (uint16_t)(nb_pkts - count);
2024                 if (count < n)
2025                         break;
2026         }
2027
2028         return nb_rx;
2029 }
2030
2031 static inline int
2032 iavf_xmit_cleanup(struct iavf_tx_queue *txq)
2033 {
2034         struct iavf_tx_entry *sw_ring = txq->sw_ring;
2035         uint16_t last_desc_cleaned = txq->last_desc_cleaned;
2036         uint16_t nb_tx_desc = txq->nb_tx_desc;
2037         uint16_t desc_to_clean_to;
2038         uint16_t nb_tx_to_clean;
2039
2040         volatile struct iavf_tx_desc *txd = txq->tx_ring;
2041
2042         desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->rs_thresh);
2043         if (desc_to_clean_to >= nb_tx_desc)
2044                 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
2045
2046         desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
2047         if ((txd[desc_to_clean_to].cmd_type_offset_bsz &
2048                         rte_cpu_to_le_64(IAVF_TXD_QW1_DTYPE_MASK)) !=
2049                         rte_cpu_to_le_64(IAVF_TX_DESC_DTYPE_DESC_DONE)) {
2050                 PMD_TX_LOG(DEBUG, "TX descriptor %4u is not done "
2051                            "(port=%d queue=%d)", desc_to_clean_to,
2052                            txq->port_id, txq->queue_id);
2053                 return -1;
2054         }
2055
2056         if (last_desc_cleaned > desc_to_clean_to)
2057                 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
2058                                                         desc_to_clean_to);
2059         else
2060                 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
2061                                         last_desc_cleaned);
2062
2063         txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
2064
2065         txq->last_desc_cleaned = desc_to_clean_to;
2066         txq->nb_free = (uint16_t)(txq->nb_free + nb_tx_to_clean);
2067
2068         return 0;
2069 }
2070
2071 /* Check if the context descriptor is needed for TX offloading */
2072 static inline uint16_t
2073 iavf_calc_context_desc(uint64_t flags, uint8_t vlan_flag)
2074 {
2075         if (flags & PKT_TX_TCP_SEG)
2076                 return 1;
2077         if (flags & PKT_TX_VLAN_PKT &&
2078             vlan_flag & IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG2)
2079                 return 1;
2080         return 0;
2081 }
2082
2083 static inline void
2084 iavf_txd_enable_checksum(uint64_t ol_flags,
2085                         uint32_t *td_cmd,
2086                         uint32_t *td_offset,
2087                         union iavf_tx_offload tx_offload)
2088 {
2089         /* Set MACLEN */
2090         *td_offset |= (tx_offload.l2_len >> 1) <<
2091                       IAVF_TX_DESC_LENGTH_MACLEN_SHIFT;
2092
2093         /* Enable L3 checksum offloads */
2094         if (ol_flags & PKT_TX_IP_CKSUM) {
2095                 *td_cmd |= IAVF_TX_DESC_CMD_IIPT_IPV4_CSUM;
2096                 *td_offset |= (tx_offload.l3_len >> 2) <<
2097                               IAVF_TX_DESC_LENGTH_IPLEN_SHIFT;
2098         } else if (ol_flags & PKT_TX_IPV4) {
2099                 *td_cmd |= IAVF_TX_DESC_CMD_IIPT_IPV4;
2100                 *td_offset |= (tx_offload.l3_len >> 2) <<
2101                               IAVF_TX_DESC_LENGTH_IPLEN_SHIFT;
2102         } else if (ol_flags & PKT_TX_IPV6) {
2103                 *td_cmd |= IAVF_TX_DESC_CMD_IIPT_IPV6;
2104                 *td_offset |= (tx_offload.l3_len >> 2) <<
2105                               IAVF_TX_DESC_LENGTH_IPLEN_SHIFT;
2106         }
2107
2108         if (ol_flags & PKT_TX_TCP_SEG) {
2109                 *td_cmd |= IAVF_TX_DESC_CMD_L4T_EOFT_TCP;
2110                 *td_offset |= (tx_offload.l4_len >> 2) <<
2111                               IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2112                 return;
2113         }
2114
2115         /* Enable L4 checksum offloads */
2116         switch (ol_flags & PKT_TX_L4_MASK) {
2117         case PKT_TX_TCP_CKSUM:
2118                 *td_cmd |= IAVF_TX_DESC_CMD_L4T_EOFT_TCP;
2119                 *td_offset |= (sizeof(struct rte_tcp_hdr) >> 2) <<
2120                               IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2121                 break;
2122         case PKT_TX_SCTP_CKSUM:
2123                 *td_cmd |= IAVF_TX_DESC_CMD_L4T_EOFT_SCTP;
2124                 *td_offset |= (sizeof(struct rte_sctp_hdr) >> 2) <<
2125                               IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2126                 break;
2127         case PKT_TX_UDP_CKSUM:
2128                 *td_cmd |= IAVF_TX_DESC_CMD_L4T_EOFT_UDP;
2129                 *td_offset |= (sizeof(struct rte_udp_hdr) >> 2) <<
2130                               IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2131                 break;
2132         default:
2133                 break;
2134         }
2135 }
2136
2137 /* set TSO context descriptor
2138  * support IP -> L4 and IP -> IP -> L4
2139  */
2140 static inline uint64_t
2141 iavf_set_tso_ctx(struct rte_mbuf *mbuf, union iavf_tx_offload tx_offload)
2142 {
2143         uint64_t ctx_desc = 0;
2144         uint32_t cd_cmd, hdr_len, cd_tso_len;
2145
2146         if (!tx_offload.l4_len) {
2147                 PMD_TX_LOG(DEBUG, "L4 length set to 0");
2148                 return ctx_desc;
2149         }
2150
2151         hdr_len = tx_offload.l2_len +
2152                   tx_offload.l3_len +
2153                   tx_offload.l4_len;
2154
2155         cd_cmd = IAVF_TX_CTX_DESC_TSO;
2156         cd_tso_len = mbuf->pkt_len - hdr_len;
2157         ctx_desc |= ((uint64_t)cd_cmd << IAVF_TXD_CTX_QW1_CMD_SHIFT) |
2158                      ((uint64_t)cd_tso_len << IAVF_TXD_CTX_QW1_TSO_LEN_SHIFT) |
2159                      ((uint64_t)mbuf->tso_segsz << IAVF_TXD_CTX_QW1_MSS_SHIFT);
2160
2161         return ctx_desc;
2162 }
2163
2164 /* Construct the tx flags */
2165 static inline uint64_t
2166 iavf_build_ctob(uint32_t td_cmd, uint32_t td_offset, unsigned int size,
2167                uint32_t td_tag)
2168 {
2169         return rte_cpu_to_le_64(IAVF_TX_DESC_DTYPE_DATA |
2170                                 ((uint64_t)td_cmd  << IAVF_TXD_QW1_CMD_SHIFT) |
2171                                 ((uint64_t)td_offset <<
2172                                  IAVF_TXD_QW1_OFFSET_SHIFT) |
2173                                 ((uint64_t)size  <<
2174                                  IAVF_TXD_QW1_TX_BUF_SZ_SHIFT) |
2175                                 ((uint64_t)td_tag  <<
2176                                  IAVF_TXD_QW1_L2TAG1_SHIFT));
2177 }
2178
2179 /* TX function */
2180 uint16_t
2181 iavf_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2182 {
2183         volatile struct iavf_tx_desc *txd;
2184         volatile struct iavf_tx_desc *txr;
2185         struct iavf_tx_queue *txq;
2186         struct iavf_tx_entry *sw_ring;
2187         struct iavf_tx_entry *txe, *txn;
2188         struct rte_mbuf *tx_pkt;
2189         struct rte_mbuf *m_seg;
2190         uint16_t tx_id;
2191         uint16_t nb_tx;
2192         uint32_t td_cmd;
2193         uint32_t td_offset;
2194         uint32_t td_tag;
2195         uint64_t ol_flags;
2196         uint16_t nb_used;
2197         uint16_t nb_ctx;
2198         uint16_t tx_last;
2199         uint16_t slen;
2200         uint64_t buf_dma_addr;
2201         uint16_t cd_l2tag2 = 0;
2202         union iavf_tx_offload tx_offload = {0};
2203
2204         txq = tx_queue;
2205         sw_ring = txq->sw_ring;
2206         txr = txq->tx_ring;
2207         tx_id = txq->tx_tail;
2208         txe = &sw_ring[tx_id];
2209
2210         /* Check if the descriptor ring needs to be cleaned. */
2211         if (txq->nb_free < txq->free_thresh)
2212                 (void)iavf_xmit_cleanup(txq);
2213
2214         for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
2215                 td_cmd = 0;
2216                 td_tag = 0;
2217                 td_offset = 0;
2218
2219                 tx_pkt = *tx_pkts++;
2220                 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
2221
2222                 ol_flags = tx_pkt->ol_flags;
2223                 tx_offload.l2_len = tx_pkt->l2_len;
2224                 tx_offload.l3_len = tx_pkt->l3_len;
2225                 tx_offload.l4_len = tx_pkt->l4_len;
2226                 tx_offload.tso_segsz = tx_pkt->tso_segsz;
2227                 /* Calculate the number of context descriptors needed. */
2228                 nb_ctx = iavf_calc_context_desc(ol_flags, txq->vlan_flag);
2229
2230                 /* The number of descriptors that must be allocated for
2231                  * a packet equals to the number of the segments of that
2232                  * packet plus 1 context descriptor if needed.
2233                  */
2234                 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
2235                 tx_last = (uint16_t)(tx_id + nb_used - 1);
2236
2237                 /* Circular ring */
2238                 if (tx_last >= txq->nb_tx_desc)
2239                         tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
2240
2241                 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u"
2242                            " tx_first=%u tx_last=%u",
2243                            txq->port_id, txq->queue_id, tx_id, tx_last);
2244
2245                 if (nb_used > txq->nb_free) {
2246                         if (iavf_xmit_cleanup(txq)) {
2247                                 if (nb_tx == 0)
2248                                         return 0;
2249                                 goto end_of_tx;
2250                         }
2251                         if (unlikely(nb_used > txq->rs_thresh)) {
2252                                 while (nb_used > txq->nb_free) {
2253                                         if (iavf_xmit_cleanup(txq)) {
2254                                                 if (nb_tx == 0)
2255                                                         return 0;
2256                                                 goto end_of_tx;
2257                                         }
2258                                 }
2259                         }
2260                 }
2261
2262                 /* Descriptor based VLAN insertion */
2263                 if (ol_flags & PKT_TX_VLAN_PKT &&
2264                     txq->vlan_flag & IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG1) {
2265                         td_cmd |= IAVF_TX_DESC_CMD_IL2TAG1;
2266                         td_tag = tx_pkt->vlan_tci;
2267                 }
2268
2269                 /* According to datasheet, the bit2 is reserved and must be
2270                  * set to 1.
2271                  */
2272                 td_cmd |= 0x04;
2273
2274                 /* Enable checksum offloading */
2275                 if (ol_flags & IAVF_TX_CKSUM_OFFLOAD_MASK)
2276                         iavf_txd_enable_checksum(ol_flags, &td_cmd,
2277                                                 &td_offset, tx_offload);
2278
2279                 if (nb_ctx) {
2280                         /* Setup TX context descriptor if required */
2281                         uint64_t cd_type_cmd_tso_mss =
2282                                 IAVF_TX_DESC_DTYPE_CONTEXT;
2283                         volatile struct iavf_tx_context_desc *ctx_txd =
2284                                 (volatile struct iavf_tx_context_desc *)
2285                                                         &txr[tx_id];
2286
2287                         /* clear QW0 or the previous writeback value
2288                          * may impact next write
2289                          */
2290                         *(volatile uint64_t *)ctx_txd = 0;
2291
2292                         txn = &sw_ring[txe->next_id];
2293                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
2294                         if (txe->mbuf) {
2295                                 rte_pktmbuf_free_seg(txe->mbuf);
2296                                 txe->mbuf = NULL;
2297                         }
2298
2299                         /* TSO enabled */
2300                         if (ol_flags & PKT_TX_TCP_SEG)
2301                                 cd_type_cmd_tso_mss |=
2302                                         iavf_set_tso_ctx(tx_pkt, tx_offload);
2303
2304                         if (ol_flags & PKT_TX_VLAN_PKT &&
2305                            txq->vlan_flag & IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG2) {
2306                                 cd_type_cmd_tso_mss |= IAVF_TX_CTX_DESC_IL2TAG2
2307                                         << IAVF_TXD_CTX_QW1_CMD_SHIFT;
2308                                 cd_l2tag2 = tx_pkt->vlan_tci;
2309                         }
2310
2311                         ctx_txd->type_cmd_tso_mss =
2312                                 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
2313                         ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
2314
2315                         IAVF_DUMP_TX_DESC(txq, &txr[tx_id], tx_id);
2316                         txe->last_id = tx_last;
2317                         tx_id = txe->next_id;
2318                         txe = txn;
2319                 }
2320
2321                 m_seg = tx_pkt;
2322                 do {
2323                         txd = &txr[tx_id];
2324                         txn = &sw_ring[txe->next_id];
2325
2326                         if (txe->mbuf)
2327                                 rte_pktmbuf_free_seg(txe->mbuf);
2328                         txe->mbuf = m_seg;
2329
2330                         /* Setup TX Descriptor */
2331                         slen = m_seg->data_len;
2332                         buf_dma_addr = rte_mbuf_data_iova(m_seg);
2333                         txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
2334                         txd->cmd_type_offset_bsz = iavf_build_ctob(td_cmd,
2335                                                                   td_offset,
2336                                                                   slen,
2337                                                                   td_tag);
2338
2339                         IAVF_DUMP_TX_DESC(txq, txd, tx_id);
2340                         txe->last_id = tx_last;
2341                         tx_id = txe->next_id;
2342                         txe = txn;
2343                         m_seg = m_seg->next;
2344                 } while (m_seg);
2345
2346                 /* The last packet data descriptor needs End Of Packet (EOP) */
2347                 td_cmd |= IAVF_TX_DESC_CMD_EOP;
2348                 txq->nb_used = (uint16_t)(txq->nb_used + nb_used);
2349                 txq->nb_free = (uint16_t)(txq->nb_free - nb_used);
2350
2351                 if (txq->nb_used >= txq->rs_thresh) {
2352                         PMD_TX_LOG(DEBUG, "Setting RS bit on TXD id="
2353                                    "%4u (port=%d queue=%d)",
2354                                    tx_last, txq->port_id, txq->queue_id);
2355
2356                         td_cmd |= IAVF_TX_DESC_CMD_RS;
2357
2358                         /* Update txq RS bit counters */
2359                         txq->nb_used = 0;
2360                 }
2361
2362                 txd->cmd_type_offset_bsz |=
2363                         rte_cpu_to_le_64(((uint64_t)td_cmd) <<
2364                                          IAVF_TXD_QW1_CMD_SHIFT);
2365                 IAVF_DUMP_TX_DESC(txq, txd, tx_id);
2366         }
2367
2368 end_of_tx:
2369         rte_wmb();
2370
2371         PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
2372                    txq->port_id, txq->queue_id, tx_id, nb_tx);
2373
2374         IAVF_PCI_REG_WC_WRITE_RELAXED(txq->qtx_tail, tx_id);
2375         txq->tx_tail = tx_id;
2376
2377         return nb_tx;
2378 }
2379
2380 /* Check if the packet with vlan user priority is transmitted in the
2381  * correct queue.
2382  */
2383 static int
2384 iavf_check_vlan_up2tc(struct iavf_tx_queue *txq, struct rte_mbuf *m)
2385 {
2386         struct rte_eth_dev *dev = &rte_eth_devices[txq->port_id];
2387         struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2388         uint16_t up;
2389
2390         up = m->vlan_tci >> IAVF_VLAN_TAG_PCP_OFFSET;
2391
2392         if (!(vf->qos_cap->cap[txq->tc].tc_prio & BIT(up))) {
2393                 PMD_TX_LOG(ERR, "packet with vlan pcp %u cannot transmit in queue %u\n",
2394                         up, txq->queue_id);
2395                 return -1;
2396         } else {
2397                 return 0;
2398         }
2399 }
2400
2401 /* TX prep functions */
2402 uint16_t
2403 iavf_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
2404               uint16_t nb_pkts)
2405 {
2406         int i, ret;
2407         uint64_t ol_flags;
2408         struct rte_mbuf *m;
2409         struct iavf_tx_queue *txq = tx_queue;
2410         struct rte_eth_dev *dev = &rte_eth_devices[txq->port_id];
2411         struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2412
2413         for (i = 0; i < nb_pkts; i++) {
2414                 m = tx_pkts[i];
2415                 ol_flags = m->ol_flags;
2416
2417                 /* Check condition for nb_segs > IAVF_TX_MAX_MTU_SEG. */
2418                 if (!(ol_flags & PKT_TX_TCP_SEG)) {
2419                         if (m->nb_segs > IAVF_TX_MAX_MTU_SEG) {
2420                                 rte_errno = EINVAL;
2421                                 return i;
2422                         }
2423                 } else if ((m->tso_segsz < IAVF_MIN_TSO_MSS) ||
2424                            (m->tso_segsz > IAVF_MAX_TSO_MSS)) {
2425                         /* MSS outside the range are considered malicious */
2426                         rte_errno = EINVAL;
2427                         return i;
2428                 }
2429
2430                 if (ol_flags & IAVF_TX_OFFLOAD_NOTSUP_MASK) {
2431                         rte_errno = ENOTSUP;
2432                         return i;
2433                 }
2434
2435 #ifdef RTE_ETHDEV_DEBUG_TX
2436                 ret = rte_validate_tx_offload(m);
2437                 if (ret != 0) {
2438                         rte_errno = -ret;
2439                         return i;
2440                 }
2441 #endif
2442                 ret = rte_net_intel_cksum_prepare(m);
2443                 if (ret != 0) {
2444                         rte_errno = -ret;
2445                         return i;
2446                 }
2447
2448                 if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_QOS &&
2449                     ol_flags & (PKT_RX_VLAN_STRIPPED | PKT_RX_VLAN)) {
2450                         ret = iavf_check_vlan_up2tc(txq, m);
2451                         if (ret != 0) {
2452                                 rte_errno = -ret;
2453                                 return i;
2454                         }
2455                 }
2456         }
2457
2458         return i;
2459 }
2460
2461 /* choose rx function*/
2462 void
2463 iavf_set_rx_function(struct rte_eth_dev *dev)
2464 {
2465         struct iavf_adapter *adapter =
2466                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2467         struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2468
2469 #ifdef RTE_ARCH_X86
2470         struct iavf_rx_queue *rxq;
2471         int i;
2472         int check_ret;
2473         bool use_avx2 = false;
2474         bool use_avx512 = false;
2475         bool use_flex = false;
2476
2477         check_ret = iavf_rx_vec_dev_check(dev);
2478         if (check_ret >= 0 &&
2479             rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
2480                 if ((rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
2481                      rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) &&
2482                     rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256)
2483                         use_avx2 = true;
2484
2485 #ifdef CC_AVX512_SUPPORT
2486                 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 &&
2487                     rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1 &&
2488                     rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512)
2489                         use_avx512 = true;
2490 #endif
2491
2492                 if (vf->vf_res->vf_cap_flags &
2493                         VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC)
2494                         use_flex = true;
2495
2496                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2497                         rxq = dev->data->rx_queues[i];
2498                         (void)iavf_rxq_vec_setup(rxq);
2499                 }
2500
2501                 if (dev->data->scattered_rx) {
2502                         if (!use_avx512) {
2503                                 PMD_DRV_LOG(DEBUG,
2504                                             "Using %sVector Scattered Rx (port %d).",
2505                                             use_avx2 ? "avx2 " : "",
2506                                             dev->data->port_id);
2507                         } else {
2508                                 if (check_ret == IAVF_VECTOR_PATH)
2509                                         PMD_DRV_LOG(DEBUG,
2510                                                     "Using AVX512 Vector Scattered Rx (port %d).",
2511                                                     dev->data->port_id);
2512                                 else
2513                                         PMD_DRV_LOG(DEBUG,
2514                                                     "Using AVX512 OFFLOAD Vector Scattered Rx (port %d).",
2515                                                     dev->data->port_id);
2516                         }
2517                         if (use_flex) {
2518                                 dev->rx_pkt_burst = use_avx2 ?
2519                                         iavf_recv_scattered_pkts_vec_avx2_flex_rxd :
2520                                         iavf_recv_scattered_pkts_vec_flex_rxd;
2521 #ifdef CC_AVX512_SUPPORT
2522                                 if (use_avx512) {
2523                                         if (check_ret == IAVF_VECTOR_PATH)
2524                                                 dev->rx_pkt_burst =
2525                                                         iavf_recv_scattered_pkts_vec_avx512_flex_rxd;
2526                                         else
2527                                                 dev->rx_pkt_burst =
2528                                                         iavf_recv_scattered_pkts_vec_avx512_flex_rxd_offload;
2529                                 }
2530 #endif
2531                         } else {
2532                                 dev->rx_pkt_burst = use_avx2 ?
2533                                         iavf_recv_scattered_pkts_vec_avx2 :
2534                                         iavf_recv_scattered_pkts_vec;
2535 #ifdef CC_AVX512_SUPPORT
2536                                 if (use_avx512) {
2537                                         if (check_ret == IAVF_VECTOR_PATH)
2538                                                 dev->rx_pkt_burst =
2539                                                         iavf_recv_scattered_pkts_vec_avx512;
2540                                         else
2541                                                 dev->rx_pkt_burst =
2542                                                         iavf_recv_scattered_pkts_vec_avx512_offload;
2543                                 }
2544 #endif
2545                         }
2546                 } else {
2547                         if (!use_avx512) {
2548                                 PMD_DRV_LOG(DEBUG, "Using %sVector Rx (port %d).",
2549                                             use_avx2 ? "avx2 " : "",
2550                                             dev->data->port_id);
2551                         } else {
2552                                 if (check_ret == IAVF_VECTOR_PATH)
2553                                         PMD_DRV_LOG(DEBUG,
2554                                                     "Using AVX512 Vector Rx (port %d).",
2555                                                     dev->data->port_id);
2556                                 else
2557                                         PMD_DRV_LOG(DEBUG,
2558                                                     "Using AVX512 OFFLOAD Vector Rx (port %d).",
2559                                                     dev->data->port_id);
2560                         }
2561                         if (use_flex) {
2562                                 dev->rx_pkt_burst = use_avx2 ?
2563                                         iavf_recv_pkts_vec_avx2_flex_rxd :
2564                                         iavf_recv_pkts_vec_flex_rxd;
2565 #ifdef CC_AVX512_SUPPORT
2566                                 if (use_avx512) {
2567                                         if (check_ret == IAVF_VECTOR_PATH)
2568                                                 dev->rx_pkt_burst =
2569                                                         iavf_recv_pkts_vec_avx512_flex_rxd;
2570                                         else
2571                                                 dev->rx_pkt_burst =
2572                                                         iavf_recv_pkts_vec_avx512_flex_rxd_offload;
2573                                 }
2574 #endif
2575                         } else {
2576                                 dev->rx_pkt_burst = use_avx2 ?
2577                                         iavf_recv_pkts_vec_avx2 :
2578                                         iavf_recv_pkts_vec;
2579 #ifdef CC_AVX512_SUPPORT
2580                                 if (use_avx512) {
2581                                         if (check_ret == IAVF_VECTOR_PATH)
2582                                                 dev->rx_pkt_burst =
2583                                                         iavf_recv_pkts_vec_avx512;
2584                                         else
2585                                                 dev->rx_pkt_burst =
2586                                                         iavf_recv_pkts_vec_avx512_offload;
2587                                 }
2588 #endif
2589                         }
2590                 }
2591
2592                 return;
2593         }
2594
2595 #endif
2596         if (dev->data->scattered_rx) {
2597                 PMD_DRV_LOG(DEBUG, "Using a Scattered Rx callback (port=%d).",
2598                             dev->data->port_id);
2599                 if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC)
2600                         dev->rx_pkt_burst = iavf_recv_scattered_pkts_flex_rxd;
2601                 else
2602                         dev->rx_pkt_burst = iavf_recv_scattered_pkts;
2603         } else if (adapter->rx_bulk_alloc_allowed) {
2604                 PMD_DRV_LOG(DEBUG, "Using bulk Rx callback (port=%d).",
2605                             dev->data->port_id);
2606                 dev->rx_pkt_burst = iavf_recv_pkts_bulk_alloc;
2607         } else {
2608                 PMD_DRV_LOG(DEBUG, "Using Basic Rx callback (port=%d).",
2609                             dev->data->port_id);
2610                 if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC)
2611                         dev->rx_pkt_burst = iavf_recv_pkts_flex_rxd;
2612                 else
2613                         dev->rx_pkt_burst = iavf_recv_pkts;
2614         }
2615 }
2616
2617 /* choose tx function*/
2618 void
2619 iavf_set_tx_function(struct rte_eth_dev *dev)
2620 {
2621 #ifdef RTE_ARCH_X86
2622         struct iavf_tx_queue *txq;
2623         int i;
2624         int check_ret;
2625         bool use_sse = false;
2626         bool use_avx2 = false;
2627         bool use_avx512 = false;
2628
2629         check_ret = iavf_tx_vec_dev_check(dev);
2630
2631         if (check_ret >= 0 &&
2632             rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
2633                 /* SSE and AVX2 not support offload path yet. */
2634                 if (check_ret == IAVF_VECTOR_PATH) {
2635                         use_sse = true;
2636                         if ((rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
2637                              rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) &&
2638                             rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256)
2639                                 use_avx2 = true;
2640                 }
2641 #ifdef CC_AVX512_SUPPORT
2642                 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 &&
2643                     rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1 &&
2644                     rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512)
2645                         use_avx512 = true;
2646 #endif
2647
2648                 if (!use_sse && !use_avx2 && !use_avx512)
2649                         goto normal;
2650
2651                 if (!use_avx512) {
2652                         PMD_DRV_LOG(DEBUG, "Using %sVector Tx (port %d).",
2653                                     use_avx2 ? "avx2 " : "",
2654                                     dev->data->port_id);
2655                         dev->tx_pkt_burst = use_avx2 ?
2656                                             iavf_xmit_pkts_vec_avx2 :
2657                                             iavf_xmit_pkts_vec;
2658                 }
2659                 dev->tx_pkt_prepare = NULL;
2660 #ifdef CC_AVX512_SUPPORT
2661                 if (use_avx512) {
2662                         if (check_ret == IAVF_VECTOR_PATH) {
2663                                 dev->tx_pkt_burst = iavf_xmit_pkts_vec_avx512;
2664                                 PMD_DRV_LOG(DEBUG, "Using AVX512 Vector Tx (port %d).",
2665                                             dev->data->port_id);
2666                         } else {
2667                                 dev->tx_pkt_burst = iavf_xmit_pkts_vec_avx512_offload;
2668                                 dev->tx_pkt_prepare = iavf_prep_pkts;
2669                                 PMD_DRV_LOG(DEBUG, "Using AVX512 OFFLOAD Vector Tx (port %d).",
2670                                             dev->data->port_id);
2671                         }
2672                 }
2673 #endif
2674
2675                 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2676                         txq = dev->data->tx_queues[i];
2677                         if (!txq)
2678                                 continue;
2679 #ifdef CC_AVX512_SUPPORT
2680                         if (use_avx512)
2681                                 iavf_txq_vec_setup_avx512(txq);
2682                         else
2683                                 iavf_txq_vec_setup(txq);
2684 #else
2685                         iavf_txq_vec_setup(txq);
2686 #endif
2687                 }
2688
2689                 return;
2690         }
2691
2692 normal:
2693 #endif
2694         PMD_DRV_LOG(DEBUG, "Using Basic Tx callback (port=%d).",
2695                     dev->data->port_id);
2696         dev->tx_pkt_burst = iavf_xmit_pkts;
2697         dev->tx_pkt_prepare = iavf_prep_pkts;
2698 }
2699
2700 static int
2701 iavf_tx_done_cleanup_full(struct iavf_tx_queue *txq,
2702                         uint32_t free_cnt)
2703 {
2704         struct iavf_tx_entry *swr_ring = txq->sw_ring;
2705         uint16_t i, tx_last, tx_id;
2706         uint16_t nb_tx_free_last;
2707         uint16_t nb_tx_to_clean;
2708         uint32_t pkt_cnt;
2709
2710         /* Start free mbuf from the next of tx_tail */
2711         tx_last = txq->tx_tail;
2712         tx_id  = swr_ring[tx_last].next_id;
2713
2714         if (txq->nb_free == 0 && iavf_xmit_cleanup(txq))
2715                 return 0;
2716
2717         nb_tx_to_clean = txq->nb_free;
2718         nb_tx_free_last = txq->nb_free;
2719         if (!free_cnt)
2720                 free_cnt = txq->nb_tx_desc;
2721
2722         /* Loop through swr_ring to count the amount of
2723          * freeable mubfs and packets.
2724          */
2725         for (pkt_cnt = 0; pkt_cnt < free_cnt; ) {
2726                 for (i = 0; i < nb_tx_to_clean &&
2727                         pkt_cnt < free_cnt &&
2728                         tx_id != tx_last; i++) {
2729                         if (swr_ring[tx_id].mbuf != NULL) {
2730                                 rte_pktmbuf_free_seg(swr_ring[tx_id].mbuf);
2731                                 swr_ring[tx_id].mbuf = NULL;
2732
2733                                 /*
2734                                  * last segment in the packet,
2735                                  * increment packet count
2736                                  */
2737                                 pkt_cnt += (swr_ring[tx_id].last_id == tx_id);
2738                         }
2739
2740                         tx_id = swr_ring[tx_id].next_id;
2741                 }
2742
2743                 if (txq->rs_thresh > txq->nb_tx_desc -
2744                         txq->nb_free || tx_id == tx_last)
2745                         break;
2746
2747                 if (pkt_cnt < free_cnt) {
2748                         if (iavf_xmit_cleanup(txq))
2749                                 break;
2750
2751                         nb_tx_to_clean = txq->nb_free - nb_tx_free_last;
2752                         nb_tx_free_last = txq->nb_free;
2753                 }
2754         }
2755
2756         return (int)pkt_cnt;
2757 }
2758
2759 int
2760 iavf_dev_tx_done_cleanup(void *txq, uint32_t free_cnt)
2761 {
2762         struct iavf_tx_queue *q = (struct iavf_tx_queue *)txq;
2763
2764         return iavf_tx_done_cleanup_full(q, free_cnt);
2765 }
2766
2767 void
2768 iavf_dev_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2769                      struct rte_eth_rxq_info *qinfo)
2770 {
2771         struct iavf_rx_queue *rxq;
2772
2773         rxq = dev->data->rx_queues[queue_id];
2774
2775         qinfo->mp = rxq->mp;
2776         qinfo->scattered_rx = dev->data->scattered_rx;
2777         qinfo->nb_desc = rxq->nb_rx_desc;
2778
2779         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2780         qinfo->conf.rx_drop_en = true;
2781         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2782 }
2783
2784 void
2785 iavf_dev_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2786                      struct rte_eth_txq_info *qinfo)
2787 {
2788         struct iavf_tx_queue *txq;
2789
2790         txq = dev->data->tx_queues[queue_id];
2791
2792         qinfo->nb_desc = txq->nb_tx_desc;
2793
2794         qinfo->conf.tx_free_thresh = txq->free_thresh;
2795         qinfo->conf.tx_rs_thresh = txq->rs_thresh;
2796         qinfo->conf.offloads = txq->offloads;
2797         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2798 }
2799
2800 /* Get the number of used descriptors of a rx queue */
2801 uint32_t
2802 iavf_dev_rxq_count(struct rte_eth_dev *dev, uint16_t queue_id)
2803 {
2804 #define IAVF_RXQ_SCAN_INTERVAL 4
2805         volatile union iavf_rx_desc *rxdp;
2806         struct iavf_rx_queue *rxq;
2807         uint16_t desc = 0;
2808
2809         rxq = dev->data->rx_queues[queue_id];
2810         rxdp = &rxq->rx_ring[rxq->rx_tail];
2811
2812         while ((desc < rxq->nb_rx_desc) &&
2813                ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
2814                  IAVF_RXD_QW1_STATUS_MASK) >> IAVF_RXD_QW1_STATUS_SHIFT) &
2815                (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)) {
2816                 /* Check the DD bit of a rx descriptor of each 4 in a group,
2817                  * to avoid checking too frequently and downgrading performance
2818                  * too much.
2819                  */
2820                 desc += IAVF_RXQ_SCAN_INTERVAL;
2821                 rxdp += IAVF_RXQ_SCAN_INTERVAL;
2822                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
2823                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
2824                                         desc - rxq->nb_rx_desc]);
2825         }
2826
2827         return desc;
2828 }
2829
2830 int
2831 iavf_dev_rx_desc_status(void *rx_queue, uint16_t offset)
2832 {
2833         struct iavf_rx_queue *rxq = rx_queue;
2834         volatile uint64_t *status;
2835         uint64_t mask;
2836         uint32_t desc;
2837
2838         if (unlikely(offset >= rxq->nb_rx_desc))
2839                 return -EINVAL;
2840
2841         if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
2842                 return RTE_ETH_RX_DESC_UNAVAIL;
2843
2844         desc = rxq->rx_tail + offset;
2845         if (desc >= rxq->nb_rx_desc)
2846                 desc -= rxq->nb_rx_desc;
2847
2848         status = &rxq->rx_ring[desc].wb.qword1.status_error_len;
2849         mask = rte_le_to_cpu_64((1ULL << IAVF_RX_DESC_STATUS_DD_SHIFT)
2850                 << IAVF_RXD_QW1_STATUS_SHIFT);
2851         if (*status & mask)
2852                 return RTE_ETH_RX_DESC_DONE;
2853
2854         return RTE_ETH_RX_DESC_AVAIL;
2855 }
2856
2857 int
2858 iavf_dev_tx_desc_status(void *tx_queue, uint16_t offset)
2859 {
2860         struct iavf_tx_queue *txq = tx_queue;
2861         volatile uint64_t *status;
2862         uint64_t mask, expect;
2863         uint32_t desc;
2864
2865         if (unlikely(offset >= txq->nb_tx_desc))
2866                 return -EINVAL;
2867
2868         desc = txq->tx_tail + offset;
2869         /* go to next desc that has the RS bit */
2870         desc = ((desc + txq->rs_thresh - 1) / txq->rs_thresh) *
2871                 txq->rs_thresh;
2872         if (desc >= txq->nb_tx_desc) {
2873                 desc -= txq->nb_tx_desc;
2874                 if (desc >= txq->nb_tx_desc)
2875                         desc -= txq->nb_tx_desc;
2876         }
2877
2878         status = &txq->tx_ring[desc].cmd_type_offset_bsz;
2879         mask = rte_le_to_cpu_64(IAVF_TXD_QW1_DTYPE_MASK);
2880         expect = rte_cpu_to_le_64(
2881                  IAVF_TX_DESC_DTYPE_DESC_DONE << IAVF_TXD_QW1_DTYPE_SHIFT);
2882         if ((*status & mask) == expect)
2883                 return RTE_ETH_TX_DESC_DONE;
2884
2885         return RTE_ETH_TX_DESC_FULL;
2886 }
2887
2888 const uint32_t *
2889 iavf_get_default_ptype_table(void)
2890 {
2891         static const uint32_t ptype_tbl[IAVF_MAX_PKT_TYPE]
2892                 __rte_cache_aligned = {
2893                 /* L2 types */
2894                 /* [0] reserved */
2895                 [1] = RTE_PTYPE_L2_ETHER,
2896                 [2] = RTE_PTYPE_L2_ETHER_TIMESYNC,
2897                 /* [3] - [5] reserved */
2898                 [6] = RTE_PTYPE_L2_ETHER_LLDP,
2899                 /* [7] - [10] reserved */
2900                 [11] = RTE_PTYPE_L2_ETHER_ARP,
2901                 /* [12] - [21] reserved */
2902
2903                 /* Non tunneled IPv4 */
2904                 [22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2905                        RTE_PTYPE_L4_FRAG,
2906                 [23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2907                        RTE_PTYPE_L4_NONFRAG,
2908                 [24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2909                        RTE_PTYPE_L4_UDP,
2910                 /* [25] reserved */
2911                 [26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2912                        RTE_PTYPE_L4_TCP,
2913                 [27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2914                        RTE_PTYPE_L4_SCTP,
2915                 [28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2916                        RTE_PTYPE_L4_ICMP,
2917
2918                 /* IPv4 --> IPv4 */
2919                 [29] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2920                        RTE_PTYPE_TUNNEL_IP |
2921                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2922                        RTE_PTYPE_INNER_L4_FRAG,
2923                 [30] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2924                        RTE_PTYPE_TUNNEL_IP |
2925                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2926                        RTE_PTYPE_INNER_L4_NONFRAG,
2927                 [31] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2928                        RTE_PTYPE_TUNNEL_IP |
2929                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2930                        RTE_PTYPE_INNER_L4_UDP,
2931                 /* [32] reserved */
2932                 [33] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2933                        RTE_PTYPE_TUNNEL_IP |
2934                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2935                        RTE_PTYPE_INNER_L4_TCP,
2936                 [34] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2937                        RTE_PTYPE_TUNNEL_IP |
2938                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2939                        RTE_PTYPE_INNER_L4_SCTP,
2940                 [35] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2941                        RTE_PTYPE_TUNNEL_IP |
2942                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2943                        RTE_PTYPE_INNER_L4_ICMP,
2944
2945                 /* IPv4 --> IPv6 */
2946                 [36] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2947                        RTE_PTYPE_TUNNEL_IP |
2948                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2949                        RTE_PTYPE_INNER_L4_FRAG,
2950                 [37] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2951                        RTE_PTYPE_TUNNEL_IP |
2952                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2953                        RTE_PTYPE_INNER_L4_NONFRAG,
2954                 [38] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2955                        RTE_PTYPE_TUNNEL_IP |
2956                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2957                        RTE_PTYPE_INNER_L4_UDP,
2958                 /* [39] reserved */
2959                 [40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2960                        RTE_PTYPE_TUNNEL_IP |
2961                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2962                        RTE_PTYPE_INNER_L4_TCP,
2963                 [41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2964                        RTE_PTYPE_TUNNEL_IP |
2965                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2966                        RTE_PTYPE_INNER_L4_SCTP,
2967                 [42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2968                        RTE_PTYPE_TUNNEL_IP |
2969                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2970                        RTE_PTYPE_INNER_L4_ICMP,
2971
2972                 /* IPv4 --> GRE/Teredo/VXLAN */
2973                 [43] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2974                        RTE_PTYPE_TUNNEL_GRENAT,
2975
2976                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv4 */
2977                 [44] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2978                        RTE_PTYPE_TUNNEL_GRENAT |
2979                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2980                        RTE_PTYPE_INNER_L4_FRAG,
2981                 [45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2982                        RTE_PTYPE_TUNNEL_GRENAT |
2983                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2984                        RTE_PTYPE_INNER_L4_NONFRAG,
2985                 [46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2986                        RTE_PTYPE_TUNNEL_GRENAT |
2987                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2988                        RTE_PTYPE_INNER_L4_UDP,
2989                 /* [47] reserved */
2990                 [48] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2991                        RTE_PTYPE_TUNNEL_GRENAT |
2992                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2993                        RTE_PTYPE_INNER_L4_TCP,
2994                 [49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2995                        RTE_PTYPE_TUNNEL_GRENAT |
2996                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2997                        RTE_PTYPE_INNER_L4_SCTP,
2998                 [50] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2999                        RTE_PTYPE_TUNNEL_GRENAT |
3000                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3001                        RTE_PTYPE_INNER_L4_ICMP,
3002
3003                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv6 */
3004                 [51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3005                        RTE_PTYPE_TUNNEL_GRENAT |
3006                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3007                        RTE_PTYPE_INNER_L4_FRAG,
3008                 [52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3009                        RTE_PTYPE_TUNNEL_GRENAT |
3010                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3011                        RTE_PTYPE_INNER_L4_NONFRAG,
3012                 [53] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3013                        RTE_PTYPE_TUNNEL_GRENAT |
3014                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3015                        RTE_PTYPE_INNER_L4_UDP,
3016                 /* [54] reserved */
3017                 [55] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3018                        RTE_PTYPE_TUNNEL_GRENAT |
3019                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3020                        RTE_PTYPE_INNER_L4_TCP,
3021                 [56] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3022                        RTE_PTYPE_TUNNEL_GRENAT |
3023                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3024                        RTE_PTYPE_INNER_L4_SCTP,
3025                 [57] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3026                        RTE_PTYPE_TUNNEL_GRENAT |
3027                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3028                        RTE_PTYPE_INNER_L4_ICMP,
3029
3030                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC */
3031                 [58] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3032                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
3033
3034                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
3035                 [59] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3036                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3037                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3038                        RTE_PTYPE_INNER_L4_FRAG,
3039                 [60] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3040                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3041                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3042                        RTE_PTYPE_INNER_L4_NONFRAG,
3043                 [61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3044                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3045                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3046                        RTE_PTYPE_INNER_L4_UDP,
3047                 /* [62] reserved */
3048                 [63] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3049                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3050                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3051                        RTE_PTYPE_INNER_L4_TCP,
3052                 [64] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3053                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3054                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3055                        RTE_PTYPE_INNER_L4_SCTP,
3056                 [65] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3057                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3058                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3059                        RTE_PTYPE_INNER_L4_ICMP,
3060
3061                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
3062                 [66] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3063                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3064                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3065                        RTE_PTYPE_INNER_L4_FRAG,
3066                 [67] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3067                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3068                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3069                        RTE_PTYPE_INNER_L4_NONFRAG,
3070                 [68] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3071                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3072                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3073                        RTE_PTYPE_INNER_L4_UDP,
3074                 /* [69] reserved */
3075                 [70] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3076                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3077                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3078                        RTE_PTYPE_INNER_L4_TCP,
3079                 [71] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3080                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3081                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3082                        RTE_PTYPE_INNER_L4_SCTP,
3083                 [72] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3084                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3085                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3086                        RTE_PTYPE_INNER_L4_ICMP,
3087                 /* [73] - [87] reserved */
3088
3089                 /* Non tunneled IPv6 */
3090                 [88] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3091                        RTE_PTYPE_L4_FRAG,
3092                 [89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3093                        RTE_PTYPE_L4_NONFRAG,
3094                 [90] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3095                        RTE_PTYPE_L4_UDP,
3096                 /* [91] reserved */
3097                 [92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3098                        RTE_PTYPE_L4_TCP,
3099                 [93] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3100                        RTE_PTYPE_L4_SCTP,
3101                 [94] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3102                        RTE_PTYPE_L4_ICMP,
3103
3104                 /* IPv6 --> IPv4 */
3105                 [95] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3106                        RTE_PTYPE_TUNNEL_IP |
3107                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3108                        RTE_PTYPE_INNER_L4_FRAG,
3109                 [96] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3110                        RTE_PTYPE_TUNNEL_IP |
3111                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3112                        RTE_PTYPE_INNER_L4_NONFRAG,
3113                 [97] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3114                        RTE_PTYPE_TUNNEL_IP |
3115                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3116                        RTE_PTYPE_INNER_L4_UDP,
3117                 /* [98] reserved */
3118                 [99] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3119                        RTE_PTYPE_TUNNEL_IP |
3120                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3121                        RTE_PTYPE_INNER_L4_TCP,
3122                 [100] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3123                         RTE_PTYPE_TUNNEL_IP |
3124                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3125                         RTE_PTYPE_INNER_L4_SCTP,
3126                 [101] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3127                         RTE_PTYPE_TUNNEL_IP |
3128                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3129                         RTE_PTYPE_INNER_L4_ICMP,
3130
3131                 /* IPv6 --> IPv6 */
3132                 [102] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3133                         RTE_PTYPE_TUNNEL_IP |
3134                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3135                         RTE_PTYPE_INNER_L4_FRAG,
3136                 [103] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3137                         RTE_PTYPE_TUNNEL_IP |
3138                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3139                         RTE_PTYPE_INNER_L4_NONFRAG,
3140                 [104] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3141                         RTE_PTYPE_TUNNEL_IP |
3142                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3143                         RTE_PTYPE_INNER_L4_UDP,
3144                 /* [105] reserved */
3145                 [106] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3146                         RTE_PTYPE_TUNNEL_IP |
3147                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3148                         RTE_PTYPE_INNER_L4_TCP,
3149                 [107] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3150                         RTE_PTYPE_TUNNEL_IP |
3151                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3152                         RTE_PTYPE_INNER_L4_SCTP,
3153                 [108] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3154                         RTE_PTYPE_TUNNEL_IP |
3155                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3156                         RTE_PTYPE_INNER_L4_ICMP,
3157
3158                 /* IPv6 --> GRE/Teredo/VXLAN */
3159                 [109] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3160                         RTE_PTYPE_TUNNEL_GRENAT,
3161
3162                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv4 */
3163                 [110] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3164                         RTE_PTYPE_TUNNEL_GRENAT |
3165                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3166                         RTE_PTYPE_INNER_L4_FRAG,
3167                 [111] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3168                         RTE_PTYPE_TUNNEL_GRENAT |
3169                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3170                         RTE_PTYPE_INNER_L4_NONFRAG,
3171                 [112] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3172                         RTE_PTYPE_TUNNEL_GRENAT |
3173                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3174                         RTE_PTYPE_INNER_L4_UDP,
3175                 /* [113] reserved */
3176                 [114] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3177                         RTE_PTYPE_TUNNEL_GRENAT |
3178                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3179                         RTE_PTYPE_INNER_L4_TCP,
3180                 [115] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3181                         RTE_PTYPE_TUNNEL_GRENAT |
3182                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3183                         RTE_PTYPE_INNER_L4_SCTP,
3184                 [116] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3185                         RTE_PTYPE_TUNNEL_GRENAT |
3186                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3187                         RTE_PTYPE_INNER_L4_ICMP,
3188
3189                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv6 */
3190                 [117] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3191                         RTE_PTYPE_TUNNEL_GRENAT |
3192                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3193                         RTE_PTYPE_INNER_L4_FRAG,
3194                 [118] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3195                         RTE_PTYPE_TUNNEL_GRENAT |
3196                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3197                         RTE_PTYPE_INNER_L4_NONFRAG,
3198                 [119] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3199                         RTE_PTYPE_TUNNEL_GRENAT |
3200                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3201                         RTE_PTYPE_INNER_L4_UDP,
3202                 /* [120] reserved */
3203                 [121] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3204                         RTE_PTYPE_TUNNEL_GRENAT |
3205                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3206                         RTE_PTYPE_INNER_L4_TCP,
3207                 [122] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3208                         RTE_PTYPE_TUNNEL_GRENAT |
3209                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3210                         RTE_PTYPE_INNER_L4_SCTP,
3211                 [123] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3212                         RTE_PTYPE_TUNNEL_GRENAT |
3213                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3214                         RTE_PTYPE_INNER_L4_ICMP,
3215
3216                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC */
3217                 [124] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3218                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
3219
3220                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
3221                 [125] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3222                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3223                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3224                         RTE_PTYPE_INNER_L4_FRAG,
3225                 [126] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3226                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3227                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3228                         RTE_PTYPE_INNER_L4_NONFRAG,
3229                 [127] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3230                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3231                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3232                         RTE_PTYPE_INNER_L4_UDP,
3233                 /* [128] reserved */
3234                 [129] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3235                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3236                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3237                         RTE_PTYPE_INNER_L4_TCP,
3238                 [130] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3239                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3240                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3241                         RTE_PTYPE_INNER_L4_SCTP,
3242                 [131] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3243                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3244                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3245                         RTE_PTYPE_INNER_L4_ICMP,
3246
3247                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
3248                 [132] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3249                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3250                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3251                         RTE_PTYPE_INNER_L4_FRAG,
3252                 [133] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3253                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3254                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3255                         RTE_PTYPE_INNER_L4_NONFRAG,
3256                 [134] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3257                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3258                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3259                         RTE_PTYPE_INNER_L4_UDP,
3260                 /* [135] reserved */
3261                 [136] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3262                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3263                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3264                         RTE_PTYPE_INNER_L4_TCP,
3265                 [137] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3266                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3267                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3268                         RTE_PTYPE_INNER_L4_SCTP,
3269                 [138] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3270                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3271                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3272                         RTE_PTYPE_INNER_L4_ICMP,
3273                 /* [139] - [299] reserved */
3274
3275                 /* PPPoE */
3276                 [300] = RTE_PTYPE_L2_ETHER_PPPOE,
3277                 [301] = RTE_PTYPE_L2_ETHER_PPPOE,
3278
3279                 /* PPPoE --> IPv4 */
3280                 [302] = RTE_PTYPE_L2_ETHER_PPPOE |
3281                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3282                         RTE_PTYPE_L4_FRAG,
3283                 [303] = RTE_PTYPE_L2_ETHER_PPPOE |
3284                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3285                         RTE_PTYPE_L4_NONFRAG,
3286                 [304] = RTE_PTYPE_L2_ETHER_PPPOE |
3287                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3288                         RTE_PTYPE_L4_UDP,
3289                 [305] = RTE_PTYPE_L2_ETHER_PPPOE |
3290                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3291                         RTE_PTYPE_L4_TCP,
3292                 [306] = RTE_PTYPE_L2_ETHER_PPPOE |
3293                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3294                         RTE_PTYPE_L4_SCTP,
3295                 [307] = RTE_PTYPE_L2_ETHER_PPPOE |
3296                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3297                         RTE_PTYPE_L4_ICMP,
3298
3299                 /* PPPoE --> IPv6 */
3300                 [308] = RTE_PTYPE_L2_ETHER_PPPOE |
3301                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3302                         RTE_PTYPE_L4_FRAG,
3303                 [309] = RTE_PTYPE_L2_ETHER_PPPOE |
3304                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3305                         RTE_PTYPE_L4_NONFRAG,
3306                 [310] = RTE_PTYPE_L2_ETHER_PPPOE |
3307                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3308                         RTE_PTYPE_L4_UDP,
3309                 [311] = RTE_PTYPE_L2_ETHER_PPPOE |
3310                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3311                         RTE_PTYPE_L4_TCP,
3312                 [312] = RTE_PTYPE_L2_ETHER_PPPOE |
3313                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3314                         RTE_PTYPE_L4_SCTP,
3315                 [313] = RTE_PTYPE_L2_ETHER_PPPOE |
3316                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3317                         RTE_PTYPE_L4_ICMP,
3318                 /* [314] - [324] reserved */
3319
3320                 /* IPv4/IPv6 --> GTPC/GTPU */
3321                 [325] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3322                         RTE_PTYPE_TUNNEL_GTPC,
3323                 [326] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3324                         RTE_PTYPE_TUNNEL_GTPC,
3325                 [327] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3326                         RTE_PTYPE_TUNNEL_GTPC,
3327                 [328] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3328                         RTE_PTYPE_TUNNEL_GTPC,
3329                 [329] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3330                         RTE_PTYPE_TUNNEL_GTPU,
3331                 [330] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3332                         RTE_PTYPE_TUNNEL_GTPU,
3333
3334                 /* IPv4 --> GTPU --> IPv4 */
3335                 [331] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3336                         RTE_PTYPE_TUNNEL_GTPU |
3337                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3338                         RTE_PTYPE_INNER_L4_FRAG,
3339                 [332] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3340                         RTE_PTYPE_TUNNEL_GTPU |
3341                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3342                         RTE_PTYPE_INNER_L4_NONFRAG,
3343                 [333] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3344                         RTE_PTYPE_TUNNEL_GTPU |
3345                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3346                         RTE_PTYPE_INNER_L4_UDP,
3347                 [334] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3348                         RTE_PTYPE_TUNNEL_GTPU |
3349                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3350                         RTE_PTYPE_INNER_L4_TCP,
3351                 [335] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3352                         RTE_PTYPE_TUNNEL_GTPU |
3353                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3354                         RTE_PTYPE_INNER_L4_ICMP,
3355
3356                 /* IPv6 --> GTPU --> IPv4 */
3357                 [336] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3358                         RTE_PTYPE_TUNNEL_GTPU |
3359                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3360                         RTE_PTYPE_INNER_L4_FRAG,
3361                 [337] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3362                         RTE_PTYPE_TUNNEL_GTPU |
3363                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3364                         RTE_PTYPE_INNER_L4_NONFRAG,
3365                 [338] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3366                         RTE_PTYPE_TUNNEL_GTPU |
3367                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3368                         RTE_PTYPE_INNER_L4_UDP,
3369                 [339] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3370                         RTE_PTYPE_TUNNEL_GTPU |
3371                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3372                         RTE_PTYPE_INNER_L4_TCP,
3373                 [340] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3374                         RTE_PTYPE_TUNNEL_GTPU |
3375                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3376                         RTE_PTYPE_INNER_L4_ICMP,
3377
3378                 /* IPv4 --> GTPU --> IPv6 */
3379                 [341] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3380                         RTE_PTYPE_TUNNEL_GTPU |
3381                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3382                         RTE_PTYPE_INNER_L4_FRAG,
3383                 [342] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3384                         RTE_PTYPE_TUNNEL_GTPU |
3385                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3386                         RTE_PTYPE_INNER_L4_NONFRAG,
3387                 [343] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3388                         RTE_PTYPE_TUNNEL_GTPU |
3389                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3390                         RTE_PTYPE_INNER_L4_UDP,
3391                 [344] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3392                         RTE_PTYPE_TUNNEL_GTPU |
3393                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3394                         RTE_PTYPE_INNER_L4_TCP,
3395                 [345] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3396                         RTE_PTYPE_TUNNEL_GTPU |
3397                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3398                         RTE_PTYPE_INNER_L4_ICMP,
3399
3400                 /* IPv6 --> GTPU --> IPv6 */
3401                 [346] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3402                         RTE_PTYPE_TUNNEL_GTPU |
3403                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3404                         RTE_PTYPE_INNER_L4_FRAG,
3405                 [347] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3406                         RTE_PTYPE_TUNNEL_GTPU |
3407                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3408                         RTE_PTYPE_INNER_L4_NONFRAG,
3409                 [348] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3410                         RTE_PTYPE_TUNNEL_GTPU |
3411                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3412                         RTE_PTYPE_INNER_L4_UDP,
3413                 [349] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3414                         RTE_PTYPE_TUNNEL_GTPU |
3415                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3416                         RTE_PTYPE_INNER_L4_TCP,
3417                 [350] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3418                         RTE_PTYPE_TUNNEL_GTPU |
3419                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3420                         RTE_PTYPE_INNER_L4_ICMP,
3421
3422                 /* IPv4 --> UDP ECPRI */
3423                 [372] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3424                         RTE_PTYPE_L4_UDP,
3425                 [373] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3426                         RTE_PTYPE_L4_UDP,
3427                 [374] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3428                         RTE_PTYPE_L4_UDP,
3429                 [375] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3430                         RTE_PTYPE_L4_UDP,
3431                 [376] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3432                         RTE_PTYPE_L4_UDP,
3433                 [377] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3434                         RTE_PTYPE_L4_UDP,
3435                 [378] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3436                         RTE_PTYPE_L4_UDP,
3437                 [379] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3438                         RTE_PTYPE_L4_UDP,
3439                 [380] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3440                         RTE_PTYPE_L4_UDP,
3441                 [381] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3442                         RTE_PTYPE_L4_UDP,
3443
3444                 /* IPV6 --> UDP ECPRI */
3445                 [382] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3446                         RTE_PTYPE_L4_UDP,
3447                 [383] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3448                         RTE_PTYPE_L4_UDP,
3449                 [384] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3450                         RTE_PTYPE_L4_UDP,
3451                 [385] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3452                         RTE_PTYPE_L4_UDP,
3453                 [386] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3454                         RTE_PTYPE_L4_UDP,
3455                 [387] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3456                         RTE_PTYPE_L4_UDP,
3457                 [388] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3458                         RTE_PTYPE_L4_UDP,
3459                 [389] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3460                         RTE_PTYPE_L4_UDP,
3461                 [390] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3462                         RTE_PTYPE_L4_UDP,
3463                 [391] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3464                         RTE_PTYPE_L4_UDP,
3465                 /* All others reserved */
3466         };
3467
3468         return ptype_tbl;
3469 }