1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2017 Intel Corporation
13 #include <sys/queue.h>
15 #include <rte_string_fns.h>
16 #include <rte_memzone.h>
18 #include <rte_malloc.h>
19 #include <rte_ether.h>
20 #include <ethdev_driver.h>
29 #include "iavf_rxtx.h"
30 #include "rte_pmd_iavf.h"
32 /* Offset of mbuf dynamic field for protocol extraction's metadata */
33 int rte_pmd_ifd_dynfield_proto_xtr_metadata_offs = -1;
35 /* Mask of mbuf dynamic flags for protocol extraction's type */
36 uint64_t rte_pmd_ifd_dynflag_proto_xtr_vlan_mask;
37 uint64_t rte_pmd_ifd_dynflag_proto_xtr_ipv4_mask;
38 uint64_t rte_pmd_ifd_dynflag_proto_xtr_ipv6_mask;
39 uint64_t rte_pmd_ifd_dynflag_proto_xtr_ipv6_flow_mask;
40 uint64_t rte_pmd_ifd_dynflag_proto_xtr_tcp_mask;
41 uint64_t rte_pmd_ifd_dynflag_proto_xtr_ip_offset_mask;
44 iavf_proto_xtr_type_to_rxdid(uint8_t flex_type)
46 static uint8_t rxdid_map[] = {
47 [IAVF_PROTO_XTR_NONE] = IAVF_RXDID_COMMS_OVS_1,
48 [IAVF_PROTO_XTR_VLAN] = IAVF_RXDID_COMMS_AUX_VLAN,
49 [IAVF_PROTO_XTR_IPV4] = IAVF_RXDID_COMMS_AUX_IPV4,
50 [IAVF_PROTO_XTR_IPV6] = IAVF_RXDID_COMMS_AUX_IPV6,
51 [IAVF_PROTO_XTR_IPV6_FLOW] = IAVF_RXDID_COMMS_AUX_IPV6_FLOW,
52 [IAVF_PROTO_XTR_TCP] = IAVF_RXDID_COMMS_AUX_TCP,
53 [IAVF_PROTO_XTR_IP_OFFSET] = IAVF_RXDID_COMMS_AUX_IP_OFFSET,
56 return flex_type < RTE_DIM(rxdid_map) ?
57 rxdid_map[flex_type] : IAVF_RXDID_COMMS_OVS_1;
61 check_rx_thresh(uint16_t nb_desc, uint16_t thresh)
63 /* The following constraints must be satisfied:
64 * thresh < rxq->nb_rx_desc
66 if (thresh >= nb_desc) {
67 PMD_INIT_LOG(ERR, "rx_free_thresh (%u) must be less than %u",
75 check_tx_thresh(uint16_t nb_desc, uint16_t tx_rs_thresh,
76 uint16_t tx_free_thresh)
78 /* TX descriptors will have their RS bit set after tx_rs_thresh
79 * descriptors have been used. The TX descriptor ring will be cleaned
80 * after tx_free_thresh descriptors are used or if the number of
81 * descriptors required to transmit a packet is greater than the
82 * number of free TX descriptors.
84 * The following constraints must be satisfied:
85 * - tx_rs_thresh must be less than the size of the ring minus 2.
86 * - tx_free_thresh must be less than the size of the ring minus 3.
87 * - tx_rs_thresh must be less than or equal to tx_free_thresh.
88 * - tx_rs_thresh must be a divisor of the ring size.
90 * One descriptor in the TX ring is used as a sentinel to avoid a H/W
91 * race condition, hence the maximum threshold constraints. When set
92 * to zero use default values.
94 if (tx_rs_thresh >= (nb_desc - 2)) {
95 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be less than the "
96 "number of TX descriptors (%u) minus 2",
97 tx_rs_thresh, nb_desc);
100 if (tx_free_thresh >= (nb_desc - 3)) {
101 PMD_INIT_LOG(ERR, "tx_free_thresh (%u) must be less than the "
102 "number of TX descriptors (%u) minus 3.",
103 tx_free_thresh, nb_desc);
106 if (tx_rs_thresh > tx_free_thresh) {
107 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be less than or "
108 "equal to tx_free_thresh (%u).",
109 tx_rs_thresh, tx_free_thresh);
112 if ((nb_desc % tx_rs_thresh) != 0) {
113 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be a divisor of the "
114 "number of TX descriptors (%u).",
115 tx_rs_thresh, nb_desc);
123 check_rx_vec_allow(struct iavf_rx_queue *rxq)
125 if (rxq->rx_free_thresh >= IAVF_VPMD_RX_MAX_BURST &&
126 rxq->nb_rx_desc % rxq->rx_free_thresh == 0) {
127 PMD_INIT_LOG(DEBUG, "Vector Rx can be enabled on this rxq.");
131 PMD_INIT_LOG(DEBUG, "Vector Rx cannot be enabled on this rxq.");
136 check_tx_vec_allow(struct iavf_tx_queue *txq)
138 if (!(txq->offloads & IAVF_NO_VECTOR_FLAGS) &&
139 txq->rs_thresh >= IAVF_VPMD_TX_MAX_BURST &&
140 txq->rs_thresh <= IAVF_VPMD_TX_MAX_FREE_BUF) {
141 PMD_INIT_LOG(DEBUG, "Vector tx can be enabled on this txq.");
144 PMD_INIT_LOG(DEBUG, "Vector Tx cannot be enabled on this txq.");
149 check_rx_bulk_allow(struct iavf_rx_queue *rxq)
153 if (!(rxq->rx_free_thresh >= IAVF_RX_MAX_BURST)) {
154 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
155 "rxq->rx_free_thresh=%d, "
156 "IAVF_RX_MAX_BURST=%d",
157 rxq->rx_free_thresh, IAVF_RX_MAX_BURST);
159 } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
160 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
161 "rxq->nb_rx_desc=%d, "
162 "rxq->rx_free_thresh=%d",
163 rxq->nb_rx_desc, rxq->rx_free_thresh);
170 reset_rx_queue(struct iavf_rx_queue *rxq)
178 len = rxq->nb_rx_desc + IAVF_RX_MAX_BURST;
180 for (i = 0; i < len * sizeof(union iavf_rx_desc); i++)
181 ((volatile char *)rxq->rx_ring)[i] = 0;
183 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
185 for (i = 0; i < IAVF_RX_MAX_BURST; i++)
186 rxq->sw_ring[rxq->nb_rx_desc + i] = &rxq->fake_mbuf;
189 rxq->rx_nb_avail = 0;
190 rxq->rx_next_avail = 0;
191 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
195 rxq->pkt_first_seg = NULL;
196 rxq->pkt_last_seg = NULL;
198 rxq->rxrearm_start = 0;
202 reset_tx_queue(struct iavf_tx_queue *txq)
204 struct iavf_tx_entry *txe;
209 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
214 size = sizeof(struct iavf_tx_desc) * txq->nb_tx_desc;
215 for (i = 0; i < size; i++)
216 ((volatile char *)txq->tx_ring)[i] = 0;
218 prev = (uint16_t)(txq->nb_tx_desc - 1);
219 for (i = 0; i < txq->nb_tx_desc; i++) {
220 txq->tx_ring[i].cmd_type_offset_bsz =
221 rte_cpu_to_le_64(IAVF_TX_DESC_DTYPE_DESC_DONE);
224 txe[prev].next_id = i;
231 txq->last_desc_cleaned = txq->nb_tx_desc - 1;
232 txq->nb_free = txq->nb_tx_desc - 1;
234 txq->next_dd = txq->rs_thresh - 1;
235 txq->next_rs = txq->rs_thresh - 1;
239 alloc_rxq_mbufs(struct iavf_rx_queue *rxq)
241 volatile union iavf_rx_desc *rxd;
242 struct rte_mbuf *mbuf = NULL;
246 for (i = 0; i < rxq->nb_rx_desc; i++) {
247 mbuf = rte_mbuf_raw_alloc(rxq->mp);
248 if (unlikely(!mbuf)) {
249 PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
253 rte_mbuf_refcnt_set(mbuf, 1);
255 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
257 mbuf->port = rxq->port_id;
260 rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
262 rxd = &rxq->rx_ring[i];
263 rxd->read.pkt_addr = dma_addr;
264 rxd->read.hdr_addr = 0;
265 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
270 rxq->sw_ring[i] = mbuf;
277 release_rxq_mbufs(struct iavf_rx_queue *rxq)
284 for (i = 0; i < rxq->nb_rx_desc; i++) {
285 if (rxq->sw_ring[i]) {
286 rte_pktmbuf_free_seg(rxq->sw_ring[i]);
287 rxq->sw_ring[i] = NULL;
292 if (rxq->rx_nb_avail == 0)
294 for (i = 0; i < rxq->rx_nb_avail; i++) {
295 struct rte_mbuf *mbuf;
297 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
298 rte_pktmbuf_free_seg(mbuf);
300 rxq->rx_nb_avail = 0;
304 release_txq_mbufs(struct iavf_tx_queue *txq)
308 if (!txq || !txq->sw_ring) {
309 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
313 for (i = 0; i < txq->nb_tx_desc; i++) {
314 if (txq->sw_ring[i].mbuf) {
315 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
316 txq->sw_ring[i].mbuf = NULL;
321 static const struct iavf_rxq_ops def_rxq_ops = {
322 .release_mbufs = release_rxq_mbufs,
325 static const struct iavf_txq_ops def_txq_ops = {
326 .release_mbufs = release_txq_mbufs,
330 iavf_rxd_to_pkt_fields_by_comms_ovs(__rte_unused struct iavf_rx_queue *rxq,
332 volatile union iavf_rx_flex_desc *rxdp)
334 volatile struct iavf_32b_rx_flex_desc_comms_ovs *desc =
335 (volatile struct iavf_32b_rx_flex_desc_comms_ovs *)rxdp;
336 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
340 if (desc->flow_id != 0xFFFFFFFF) {
341 mb->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
342 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
345 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
346 stat_err = rte_le_to_cpu_16(desc->status_error0);
347 if (likely(stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
348 mb->ol_flags |= PKT_RX_RSS_HASH;
349 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
355 iavf_rxd_to_pkt_fields_by_comms_aux_v1(struct iavf_rx_queue *rxq,
357 volatile union iavf_rx_flex_desc *rxdp)
359 volatile struct iavf_32b_rx_flex_desc_comms *desc =
360 (volatile struct iavf_32b_rx_flex_desc_comms *)rxdp;
363 stat_err = rte_le_to_cpu_16(desc->status_error0);
364 if (likely(stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
365 mb->ol_flags |= PKT_RX_RSS_HASH;
366 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
369 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
370 if (desc->flow_id != 0xFFFFFFFF) {
371 mb->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
372 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
375 if (rxq->xtr_ol_flag) {
376 uint32_t metadata = 0;
378 stat_err = rte_le_to_cpu_16(desc->status_error1);
380 if (stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS1_XTRMD4_VALID_S))
381 metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux0);
383 if (stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS1_XTRMD5_VALID_S))
385 rte_le_to_cpu_16(desc->flex_ts.flex.aux1) << 16;
388 mb->ol_flags |= rxq->xtr_ol_flag;
390 *RTE_PMD_IFD_DYNF_PROTO_XTR_METADATA(mb) = metadata;
397 iavf_rxd_to_pkt_fields_by_comms_aux_v2(struct iavf_rx_queue *rxq,
399 volatile union iavf_rx_flex_desc *rxdp)
401 volatile struct iavf_32b_rx_flex_desc_comms *desc =
402 (volatile struct iavf_32b_rx_flex_desc_comms *)rxdp;
405 stat_err = rte_le_to_cpu_16(desc->status_error0);
406 if (likely(stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
407 mb->ol_flags |= PKT_RX_RSS_HASH;
408 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
411 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
412 if (desc->flow_id != 0xFFFFFFFF) {
413 mb->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
414 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
417 if (rxq->xtr_ol_flag) {
418 uint32_t metadata = 0;
420 if (desc->flex_ts.flex.aux0 != 0xFFFF)
421 metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux0);
422 else if (desc->flex_ts.flex.aux1 != 0xFFFF)
423 metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux1);
426 mb->ol_flags |= rxq->xtr_ol_flag;
428 *RTE_PMD_IFD_DYNF_PROTO_XTR_METADATA(mb) = metadata;
435 iavf_select_rxd_to_pkt_fields_handler(struct iavf_rx_queue *rxq, uint32_t rxdid)
438 case IAVF_RXDID_COMMS_AUX_VLAN:
439 rxq->xtr_ol_flag = rte_pmd_ifd_dynflag_proto_xtr_vlan_mask;
440 rxq->rxd_to_pkt_fields =
441 iavf_rxd_to_pkt_fields_by_comms_aux_v1;
443 case IAVF_RXDID_COMMS_AUX_IPV4:
444 rxq->xtr_ol_flag = rte_pmd_ifd_dynflag_proto_xtr_ipv4_mask;
445 rxq->rxd_to_pkt_fields =
446 iavf_rxd_to_pkt_fields_by_comms_aux_v1;
448 case IAVF_RXDID_COMMS_AUX_IPV6:
449 rxq->xtr_ol_flag = rte_pmd_ifd_dynflag_proto_xtr_ipv6_mask;
450 rxq->rxd_to_pkt_fields =
451 iavf_rxd_to_pkt_fields_by_comms_aux_v1;
453 case IAVF_RXDID_COMMS_AUX_IPV6_FLOW:
455 rte_pmd_ifd_dynflag_proto_xtr_ipv6_flow_mask;
456 rxq->rxd_to_pkt_fields =
457 iavf_rxd_to_pkt_fields_by_comms_aux_v1;
459 case IAVF_RXDID_COMMS_AUX_TCP:
460 rxq->xtr_ol_flag = rte_pmd_ifd_dynflag_proto_xtr_tcp_mask;
461 rxq->rxd_to_pkt_fields =
462 iavf_rxd_to_pkt_fields_by_comms_aux_v1;
464 case IAVF_RXDID_COMMS_AUX_IP_OFFSET:
466 rte_pmd_ifd_dynflag_proto_xtr_ip_offset_mask;
467 rxq->rxd_to_pkt_fields =
468 iavf_rxd_to_pkt_fields_by_comms_aux_v2;
470 case IAVF_RXDID_COMMS_OVS_1:
471 rxq->rxd_to_pkt_fields = iavf_rxd_to_pkt_fields_by_comms_ovs;
474 /* update this according to the RXDID for FLEX_DESC_NONE */
475 rxq->rxd_to_pkt_fields = iavf_rxd_to_pkt_fields_by_comms_ovs;
479 if (!rte_pmd_ifd_dynf_proto_xtr_metadata_avail())
480 rxq->xtr_ol_flag = 0;
484 iavf_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
485 uint16_t nb_desc, unsigned int socket_id,
486 const struct rte_eth_rxconf *rx_conf,
487 struct rte_mempool *mp)
489 struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
490 struct iavf_adapter *ad =
491 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
492 struct iavf_info *vf =
493 IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
494 struct iavf_vsi *vsi = &vf->vsi;
495 struct iavf_rx_queue *rxq;
496 const struct rte_memzone *mz;
500 uint16_t rx_free_thresh;
502 PMD_INIT_FUNC_TRACE();
504 if (nb_desc % IAVF_ALIGN_RING_DESC != 0 ||
505 nb_desc > IAVF_MAX_RING_DESC ||
506 nb_desc < IAVF_MIN_RING_DESC) {
507 PMD_INIT_LOG(ERR, "Number (%u) of receive descriptors is "
512 /* Check free threshold */
513 rx_free_thresh = (rx_conf->rx_free_thresh == 0) ?
514 IAVF_DEFAULT_RX_FREE_THRESH :
515 rx_conf->rx_free_thresh;
516 if (check_rx_thresh(nb_desc, rx_free_thresh) != 0)
519 /* Free memory if needed */
520 if (dev->data->rx_queues[queue_idx]) {
521 iavf_dev_rx_queue_release(dev->data->rx_queues[queue_idx]);
522 dev->data->rx_queues[queue_idx] = NULL;
525 /* Allocate the rx queue data structure */
526 rxq = rte_zmalloc_socket("iavf rxq",
527 sizeof(struct iavf_rx_queue),
531 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
532 "rx queue data structure");
536 if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC) {
537 proto_xtr = vf->proto_xtr ? vf->proto_xtr[queue_idx] :
539 rxq->rxdid = iavf_proto_xtr_type_to_rxdid(proto_xtr);
540 rxq->proto_xtr = proto_xtr;
542 rxq->rxdid = IAVF_RXDID_LEGACY_1;
543 rxq->proto_xtr = IAVF_PROTO_XTR_NONE;
546 iavf_select_rxd_to_pkt_fields_handler(rxq, rxq->rxdid);
549 rxq->nb_rx_desc = nb_desc;
550 rxq->rx_free_thresh = rx_free_thresh;
551 rxq->queue_id = queue_idx;
552 rxq->port_id = dev->data->port_id;
553 rxq->rx_deferred_start = rx_conf->rx_deferred_start;
557 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
558 rxq->crc_len = RTE_ETHER_CRC_LEN;
562 len = rte_pktmbuf_data_room_size(rxq->mp) - RTE_PKTMBUF_HEADROOM;
563 rxq->rx_buf_len = RTE_ALIGN(len, (1 << IAVF_RXQ_CTX_DBUFF_SHIFT));
565 /* Allocate the software ring. */
566 len = nb_desc + IAVF_RX_MAX_BURST;
568 rte_zmalloc_socket("iavf rx sw ring",
569 sizeof(struct rte_mbuf *) * len,
573 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW ring");
578 /* Allocate the maximun number of RX ring hardware descriptor with
579 * a liitle more to support bulk allocate.
581 len = IAVF_MAX_RING_DESC + IAVF_RX_MAX_BURST;
582 ring_size = RTE_ALIGN(len * sizeof(union iavf_rx_desc),
584 mz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
585 ring_size, IAVF_RING_BASE_ALIGN,
588 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for RX");
589 rte_free(rxq->sw_ring);
593 /* Zero all the descriptors in the ring. */
594 memset(mz->addr, 0, ring_size);
595 rxq->rx_ring_phys_addr = mz->iova;
596 rxq->rx_ring = (union iavf_rx_desc *)mz->addr;
601 dev->data->rx_queues[queue_idx] = rxq;
602 rxq->qrx_tail = hw->hw_addr + IAVF_QRX_TAIL1(rxq->queue_id);
603 rxq->ops = &def_rxq_ops;
605 if (check_rx_bulk_allow(rxq) == true) {
606 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
607 "satisfied. Rx Burst Bulk Alloc function will be "
608 "used on port=%d, queue=%d.",
609 rxq->port_id, rxq->queue_id);
611 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
612 "not satisfied, Scattered Rx is requested "
613 "on port=%d, queue=%d.",
614 rxq->port_id, rxq->queue_id);
615 ad->rx_bulk_alloc_allowed = false;
618 if (check_rx_vec_allow(rxq) == false)
619 ad->rx_vec_allowed = false;
625 iavf_dev_tx_queue_setup(struct rte_eth_dev *dev,
628 unsigned int socket_id,
629 const struct rte_eth_txconf *tx_conf)
631 struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
632 struct iavf_info *vf =
633 IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
634 struct iavf_tx_queue *txq;
635 const struct rte_memzone *mz;
637 uint16_t tx_rs_thresh, tx_free_thresh;
640 PMD_INIT_FUNC_TRACE();
642 offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
644 if (nb_desc % IAVF_ALIGN_RING_DESC != 0 ||
645 nb_desc > IAVF_MAX_RING_DESC ||
646 nb_desc < IAVF_MIN_RING_DESC) {
647 PMD_INIT_LOG(ERR, "Number (%u) of transmit descriptors is "
652 tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
653 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
654 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
655 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
656 check_tx_thresh(nb_desc, tx_rs_thresh, tx_rs_thresh);
658 /* Free memory if needed. */
659 if (dev->data->tx_queues[queue_idx]) {
660 iavf_dev_tx_queue_release(dev->data->tx_queues[queue_idx]);
661 dev->data->tx_queues[queue_idx] = NULL;
664 /* Allocate the TX queue data structure. */
665 txq = rte_zmalloc_socket("iavf txq",
666 sizeof(struct iavf_tx_queue),
670 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
671 "tx queue structure");
675 if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_VLAN_V2) {
676 struct virtchnl_vlan_supported_caps *insertion_support =
677 &vf->vlan_v2_caps.offloads.insertion_support;
678 uint32_t insertion_cap;
680 if (insertion_support->outer)
681 insertion_cap = insertion_support->outer;
683 insertion_cap = insertion_support->inner;
685 if (insertion_cap & VIRTCHNL_VLAN_TAG_LOCATION_L2TAG1)
686 txq->vlan_flag = IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG1;
687 else if (insertion_cap & VIRTCHNL_VLAN_TAG_LOCATION_L2TAG2)
688 txq->vlan_flag = IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG2;
690 txq->vlan_flag = IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG1;
693 txq->nb_tx_desc = nb_desc;
694 txq->rs_thresh = tx_rs_thresh;
695 txq->free_thresh = tx_free_thresh;
696 txq->queue_id = queue_idx;
697 txq->port_id = dev->data->port_id;
698 txq->offloads = offloads;
699 txq->tx_deferred_start = tx_conf->tx_deferred_start;
701 /* Allocate software ring */
703 rte_zmalloc_socket("iavf tx sw ring",
704 sizeof(struct iavf_tx_entry) * nb_desc,
708 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW TX ring");
713 /* Allocate TX hardware ring descriptors. */
714 ring_size = sizeof(struct iavf_tx_desc) * IAVF_MAX_RING_DESC;
715 ring_size = RTE_ALIGN(ring_size, IAVF_DMA_MEM_ALIGN);
716 mz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
717 ring_size, IAVF_RING_BASE_ALIGN,
720 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for TX");
721 rte_free(txq->sw_ring);
725 txq->tx_ring_phys_addr = mz->iova;
726 txq->tx_ring = (struct iavf_tx_desc *)mz->addr;
731 dev->data->tx_queues[queue_idx] = txq;
732 txq->qtx_tail = hw->hw_addr + IAVF_QTX_TAIL1(queue_idx);
733 txq->ops = &def_txq_ops;
735 if (check_tx_vec_allow(txq) == false) {
736 struct iavf_adapter *ad =
737 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
738 ad->tx_vec_allowed = false;
745 iavf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
747 struct iavf_adapter *adapter =
748 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
749 struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
750 struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
751 struct iavf_rx_queue *rxq;
754 PMD_DRV_FUNC_TRACE();
756 if (rx_queue_id >= dev->data->nb_rx_queues)
759 rxq = dev->data->rx_queues[rx_queue_id];
761 err = alloc_rxq_mbufs(rxq);
763 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
769 /* Init the RX tail register. */
770 IAVF_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
771 IAVF_WRITE_FLUSH(hw);
773 /* Ready to switch the queue on */
775 err = iavf_switch_queue(adapter, rx_queue_id, true, true);
777 err = iavf_switch_queue_lv(adapter, rx_queue_id, true, true);
780 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
783 dev->data->rx_queue_state[rx_queue_id] =
784 RTE_ETH_QUEUE_STATE_STARTED;
790 iavf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
792 struct iavf_adapter *adapter =
793 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
794 struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
795 struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
796 struct iavf_tx_queue *txq;
799 PMD_DRV_FUNC_TRACE();
801 if (tx_queue_id >= dev->data->nb_tx_queues)
804 txq = dev->data->tx_queues[tx_queue_id];
806 /* Init the RX tail register. */
807 IAVF_PCI_REG_WRITE(txq->qtx_tail, 0);
808 IAVF_WRITE_FLUSH(hw);
810 /* Ready to switch the queue on */
812 err = iavf_switch_queue(adapter, tx_queue_id, false, true);
814 err = iavf_switch_queue_lv(adapter, tx_queue_id, false, true);
817 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
820 dev->data->tx_queue_state[tx_queue_id] =
821 RTE_ETH_QUEUE_STATE_STARTED;
827 iavf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
829 struct iavf_adapter *adapter =
830 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
831 struct iavf_rx_queue *rxq;
834 PMD_DRV_FUNC_TRACE();
836 if (rx_queue_id >= dev->data->nb_rx_queues)
839 err = iavf_switch_queue(adapter, rx_queue_id, true, false);
841 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
846 rxq = dev->data->rx_queues[rx_queue_id];
847 rxq->ops->release_mbufs(rxq);
849 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
855 iavf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
857 struct iavf_adapter *adapter =
858 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
859 struct iavf_tx_queue *txq;
862 PMD_DRV_FUNC_TRACE();
864 if (tx_queue_id >= dev->data->nb_tx_queues)
867 err = iavf_switch_queue(adapter, tx_queue_id, false, false);
869 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u off",
874 txq = dev->data->tx_queues[tx_queue_id];
875 txq->ops->release_mbufs(txq);
877 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
883 iavf_dev_rx_queue_release(void *rxq)
885 struct iavf_rx_queue *q = (struct iavf_rx_queue *)rxq;
890 q->ops->release_mbufs(q);
891 rte_free(q->sw_ring);
892 rte_memzone_free(q->mz);
897 iavf_dev_tx_queue_release(void *txq)
899 struct iavf_tx_queue *q = (struct iavf_tx_queue *)txq;
904 q->ops->release_mbufs(q);
905 rte_free(q->sw_ring);
906 rte_memzone_free(q->mz);
911 iavf_stop_queues(struct rte_eth_dev *dev)
913 struct iavf_adapter *adapter =
914 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
915 struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
916 struct iavf_rx_queue *rxq;
917 struct iavf_tx_queue *txq;
920 /* Stop All queues */
921 if (!vf->lv_enabled) {
922 ret = iavf_disable_queues(adapter);
924 PMD_DRV_LOG(WARNING, "Fail to stop queues");
926 ret = iavf_disable_queues_lv(adapter);
928 PMD_DRV_LOG(WARNING, "Fail to stop queues for large VF");
932 PMD_DRV_LOG(WARNING, "Fail to stop queues");
934 for (i = 0; i < dev->data->nb_tx_queues; i++) {
935 txq = dev->data->tx_queues[i];
938 txq->ops->release_mbufs(txq);
940 dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED;
942 for (i = 0; i < dev->data->nb_rx_queues; i++) {
943 rxq = dev->data->rx_queues[i];
946 rxq->ops->release_mbufs(rxq);
948 dev->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED;
952 #define IAVF_RX_FLEX_ERR0_BITS \
953 ((1 << IAVF_RX_FLEX_DESC_STATUS0_HBO_S) | \
954 (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_IPE_S) | \
955 (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_L4E_S) | \
956 (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S) | \
957 (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S) | \
958 (1 << IAVF_RX_FLEX_DESC_STATUS0_RXE_S))
961 iavf_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union iavf_rx_desc *rxdp)
963 if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
964 (1 << IAVF_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
965 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
967 rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
974 iavf_flex_rxd_to_vlan_tci(struct rte_mbuf *mb,
975 volatile union iavf_rx_flex_desc *rxdp)
977 if (rte_le_to_cpu_64(rxdp->wb.status_error0) &
978 (1 << IAVF_RX_FLEX_DESC_STATUS0_L2TAG1P_S)) {
979 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
981 rte_le_to_cpu_16(rxdp->wb.l2tag1);
986 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
987 if (rte_le_to_cpu_16(rxdp->wb.status_error1) &
988 (1 << IAVF_RX_FLEX_DESC_STATUS1_L2TAG2P_S)) {
989 mb->ol_flags |= PKT_RX_QINQ_STRIPPED | PKT_RX_QINQ |
990 PKT_RX_VLAN_STRIPPED | PKT_RX_VLAN;
991 mb->vlan_tci_outer = mb->vlan_tci;
992 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.l2tag2_2nd);
993 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
994 rte_le_to_cpu_16(rxdp->wb.l2tag2_1st),
995 rte_le_to_cpu_16(rxdp->wb.l2tag2_2nd));
997 mb->vlan_tci_outer = 0;
1002 /* Translate the rx descriptor status and error fields to pkt flags */
1003 static inline uint64_t
1004 iavf_rxd_to_pkt_flags(uint64_t qword)
1007 uint64_t error_bits = (qword >> IAVF_RXD_QW1_ERROR_SHIFT);
1009 #define IAVF_RX_ERR_BITS 0x3f
1011 /* Check if RSS_HASH */
1012 flags = (((qword >> IAVF_RX_DESC_STATUS_FLTSTAT_SHIFT) &
1013 IAVF_RX_DESC_FLTSTAT_RSS_HASH) ==
1014 IAVF_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;
1016 /* Check if FDIR Match */
1017 flags |= (qword & (1 << IAVF_RX_DESC_STATUS_FLM_SHIFT) ?
1020 if (likely((error_bits & IAVF_RX_ERR_BITS) == 0)) {
1021 flags |= (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD);
1025 if (unlikely(error_bits & (1 << IAVF_RX_DESC_ERROR_IPE_SHIFT)))
1026 flags |= PKT_RX_IP_CKSUM_BAD;
1028 flags |= PKT_RX_IP_CKSUM_GOOD;
1030 if (unlikely(error_bits & (1 << IAVF_RX_DESC_ERROR_L4E_SHIFT)))
1031 flags |= PKT_RX_L4_CKSUM_BAD;
1033 flags |= PKT_RX_L4_CKSUM_GOOD;
1035 /* TODO: Oversize error bit is not processed here */
1040 static inline uint64_t
1041 iavf_rxd_build_fdir(volatile union iavf_rx_desc *rxdp, struct rte_mbuf *mb)
1044 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
1047 flexbh = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
1048 IAVF_RX_DESC_EXT_STATUS_FLEXBH_SHIFT) &
1049 IAVF_RX_DESC_EXT_STATUS_FLEXBH_MASK;
1051 if (flexbh == IAVF_RX_DESC_EXT_STATUS_FLEXBH_FD_ID) {
1053 rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.fd_id);
1054 flags |= PKT_RX_FDIR_ID;
1058 rte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.fd_id);
1059 flags |= PKT_RX_FDIR_ID;
1064 #define IAVF_RX_FLEX_ERR0_BITS \
1065 ((1 << IAVF_RX_FLEX_DESC_STATUS0_HBO_S) | \
1066 (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_IPE_S) | \
1067 (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_L4E_S) | \
1068 (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S) | \
1069 (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S) | \
1070 (1 << IAVF_RX_FLEX_DESC_STATUS0_RXE_S))
1072 /* Rx L3/L4 checksum */
1073 static inline uint64_t
1074 iavf_flex_rxd_error_to_pkt_flags(uint16_t stat_err0)
1078 /* check if HW has decoded the packet and checksum */
1079 if (unlikely(!(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_L3L4P_S))))
1082 if (likely(!(stat_err0 & IAVF_RX_FLEX_ERR0_BITS))) {
1083 flags |= (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD);
1087 if (unlikely(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_IPE_S)))
1088 flags |= PKT_RX_IP_CKSUM_BAD;
1090 flags |= PKT_RX_IP_CKSUM_GOOD;
1092 if (unlikely(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_L4E_S)))
1093 flags |= PKT_RX_L4_CKSUM_BAD;
1095 flags |= PKT_RX_L4_CKSUM_GOOD;
1097 if (unlikely(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S)))
1098 flags |= PKT_RX_EIP_CKSUM_BAD;
1103 /* If the number of free RX descriptors is greater than the RX free
1104 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1105 * register. Update the RDT with the value of the last processed RX
1106 * descriptor minus 1, to guarantee that the RDT register is never
1107 * equal to the RDH register, which creates a "full" ring situation
1108 * from the hardware point of view.
1111 iavf_update_rx_tail(struct iavf_rx_queue *rxq, uint16_t nb_hold, uint16_t rx_id)
1113 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1115 if (nb_hold > rxq->rx_free_thresh) {
1117 "port_id=%u queue_id=%u rx_tail=%u nb_hold=%u",
1118 rxq->port_id, rxq->queue_id, rx_id, nb_hold);
1119 rx_id = (uint16_t)((rx_id == 0) ?
1120 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1121 IAVF_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
1124 rxq->nb_rx_hold = nb_hold;
1127 /* implement recv_pkts */
1129 iavf_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1131 volatile union iavf_rx_desc *rx_ring;
1132 volatile union iavf_rx_desc *rxdp;
1133 struct iavf_rx_queue *rxq;
1134 union iavf_rx_desc rxd;
1135 struct rte_mbuf *rxe;
1136 struct rte_eth_dev *dev;
1137 struct rte_mbuf *rxm;
1138 struct rte_mbuf *nmb;
1142 uint16_t rx_packet_len;
1143 uint16_t rx_id, nb_hold;
1146 const uint32_t *ptype_tbl;
1151 rx_id = rxq->rx_tail;
1152 rx_ring = rxq->rx_ring;
1153 ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1155 while (nb_rx < nb_pkts) {
1156 rxdp = &rx_ring[rx_id];
1157 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1158 rx_status = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
1159 IAVF_RXD_QW1_STATUS_SHIFT;
1161 /* Check the DD bit first */
1162 if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)))
1164 IAVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
1166 nmb = rte_mbuf_raw_alloc(rxq->mp);
1167 if (unlikely(!nmb)) {
1168 dev = &rte_eth_devices[rxq->port_id];
1169 dev->data->rx_mbuf_alloc_failed++;
1170 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1171 "queue_id=%u", rxq->port_id, rxq->queue_id);
1177 rxe = rxq->sw_ring[rx_id];
1179 if (unlikely(rx_id == rxq->nb_rx_desc))
1182 /* Prefetch next mbuf */
1183 rte_prefetch0(rxq->sw_ring[rx_id]);
1185 /* When next RX descriptor is on a cache line boundary,
1186 * prefetch the next 4 RX descriptors and next 8 pointers
1189 if ((rx_id & 0x3) == 0) {
1190 rte_prefetch0(&rx_ring[rx_id]);
1191 rte_prefetch0(rxq->sw_ring[rx_id]);
1195 rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1196 rxdp->read.hdr_addr = 0;
1197 rxdp->read.pkt_addr = dma_addr;
1199 rx_packet_len = ((qword1 & IAVF_RXD_QW1_LENGTH_PBUF_MASK) >>
1200 IAVF_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
1202 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1203 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
1206 rxm->pkt_len = rx_packet_len;
1207 rxm->data_len = rx_packet_len;
1208 rxm->port = rxq->port_id;
1210 iavf_rxd_to_vlan_tci(rxm, &rxd);
1211 pkt_flags = iavf_rxd_to_pkt_flags(qword1);
1213 ptype_tbl[(uint8_t)((qword1 &
1214 IAVF_RXD_QW1_PTYPE_MASK) >> IAVF_RXD_QW1_PTYPE_SHIFT)];
1216 if (pkt_flags & PKT_RX_RSS_HASH)
1218 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1220 if (pkt_flags & PKT_RX_FDIR)
1221 pkt_flags |= iavf_rxd_build_fdir(&rxd, rxm);
1223 rxm->ol_flags |= pkt_flags;
1225 rx_pkts[nb_rx++] = rxm;
1227 rxq->rx_tail = rx_id;
1229 iavf_update_rx_tail(rxq, nb_hold, rx_id);
1234 /* implement recv_pkts for flexible Rx descriptor */
1236 iavf_recv_pkts_flex_rxd(void *rx_queue,
1237 struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1239 volatile union iavf_rx_desc *rx_ring;
1240 volatile union iavf_rx_flex_desc *rxdp;
1241 struct iavf_rx_queue *rxq;
1242 union iavf_rx_flex_desc rxd;
1243 struct rte_mbuf *rxe;
1244 struct rte_eth_dev *dev;
1245 struct rte_mbuf *rxm;
1246 struct rte_mbuf *nmb;
1248 uint16_t rx_stat_err0;
1249 uint16_t rx_packet_len;
1250 uint16_t rx_id, nb_hold;
1253 const uint32_t *ptype_tbl;
1258 rx_id = rxq->rx_tail;
1259 rx_ring = rxq->rx_ring;
1260 ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1262 while (nb_rx < nb_pkts) {
1263 rxdp = (volatile union iavf_rx_flex_desc *)&rx_ring[rx_id];
1264 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1266 /* Check the DD bit first */
1267 if (!(rx_stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S)))
1269 IAVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
1271 nmb = rte_mbuf_raw_alloc(rxq->mp);
1272 if (unlikely(!nmb)) {
1273 dev = &rte_eth_devices[rxq->port_id];
1274 dev->data->rx_mbuf_alloc_failed++;
1275 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1276 "queue_id=%u", rxq->port_id, rxq->queue_id);
1282 rxe = rxq->sw_ring[rx_id];
1284 if (unlikely(rx_id == rxq->nb_rx_desc))
1287 /* Prefetch next mbuf */
1288 rte_prefetch0(rxq->sw_ring[rx_id]);
1290 /* When next RX descriptor is on a cache line boundary,
1291 * prefetch the next 4 RX descriptors and next 8 pointers
1294 if ((rx_id & 0x3) == 0) {
1295 rte_prefetch0(&rx_ring[rx_id]);
1296 rte_prefetch0(rxq->sw_ring[rx_id]);
1300 rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1301 rxdp->read.hdr_addr = 0;
1302 rxdp->read.pkt_addr = dma_addr;
1304 rx_packet_len = (rte_le_to_cpu_16(rxd.wb.pkt_len) &
1305 IAVF_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
1307 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1308 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
1311 rxm->pkt_len = rx_packet_len;
1312 rxm->data_len = rx_packet_len;
1313 rxm->port = rxq->port_id;
1315 rxm->packet_type = ptype_tbl[IAVF_RX_FLEX_DESC_PTYPE_M &
1316 rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
1317 iavf_flex_rxd_to_vlan_tci(rxm, &rxd);
1318 rxq->rxd_to_pkt_fields(rxq, rxm, &rxd);
1319 pkt_flags = iavf_flex_rxd_error_to_pkt_flags(rx_stat_err0);
1320 rxm->ol_flags |= pkt_flags;
1322 rx_pkts[nb_rx++] = rxm;
1324 rxq->rx_tail = rx_id;
1326 iavf_update_rx_tail(rxq, nb_hold, rx_id);
1331 /* implement recv_scattered_pkts for flexible Rx descriptor */
1333 iavf_recv_scattered_pkts_flex_rxd(void *rx_queue, struct rte_mbuf **rx_pkts,
1336 struct iavf_rx_queue *rxq = rx_queue;
1337 union iavf_rx_flex_desc rxd;
1338 struct rte_mbuf *rxe;
1339 struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1340 struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1341 struct rte_mbuf *nmb, *rxm;
1342 uint16_t rx_id = rxq->rx_tail;
1343 uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
1344 struct rte_eth_dev *dev;
1345 uint16_t rx_stat_err0;
1349 volatile union iavf_rx_desc *rx_ring = rxq->rx_ring;
1350 volatile union iavf_rx_flex_desc *rxdp;
1351 const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1353 while (nb_rx < nb_pkts) {
1354 rxdp = (volatile union iavf_rx_flex_desc *)&rx_ring[rx_id];
1355 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1357 /* Check the DD bit */
1358 if (!(rx_stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S)))
1360 IAVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
1362 nmb = rte_mbuf_raw_alloc(rxq->mp);
1363 if (unlikely(!nmb)) {
1364 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1365 "queue_id=%u", rxq->port_id, rxq->queue_id);
1366 dev = &rte_eth_devices[rxq->port_id];
1367 dev->data->rx_mbuf_alloc_failed++;
1373 rxe = rxq->sw_ring[rx_id];
1375 if (rx_id == rxq->nb_rx_desc)
1378 /* Prefetch next mbuf */
1379 rte_prefetch0(rxq->sw_ring[rx_id]);
1381 /* When next RX descriptor is on a cache line boundary,
1382 * prefetch the next 4 RX descriptors and next 8 pointers
1385 if ((rx_id & 0x3) == 0) {
1386 rte_prefetch0(&rx_ring[rx_id]);
1387 rte_prefetch0(rxq->sw_ring[rx_id]);
1392 rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1394 /* Set data buffer address and data length of the mbuf */
1395 rxdp->read.hdr_addr = 0;
1396 rxdp->read.pkt_addr = dma_addr;
1397 rx_packet_len = rte_le_to_cpu_16(rxd.wb.pkt_len) &
1398 IAVF_RX_FLX_DESC_PKT_LEN_M;
1399 rxm->data_len = rx_packet_len;
1400 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1402 /* If this is the first buffer of the received packet, set the
1403 * pointer to the first mbuf of the packet and initialize its
1404 * context. Otherwise, update the total length and the number
1405 * of segments of the current scattered packet, and update the
1406 * pointer to the last mbuf of the current packet.
1410 first_seg->nb_segs = 1;
1411 first_seg->pkt_len = rx_packet_len;
1413 first_seg->pkt_len =
1414 (uint16_t)(first_seg->pkt_len +
1416 first_seg->nb_segs++;
1417 last_seg->next = rxm;
1420 /* If this is not the last buffer of the received packet,
1421 * update the pointer to the last mbuf of the current scattered
1422 * packet and continue to parse the RX ring.
1424 if (!(rx_stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_EOF_S))) {
1429 /* This is the last buffer of the received packet. If the CRC
1430 * is not stripped by the hardware:
1431 * - Subtract the CRC length from the total packet length.
1432 * - If the last buffer only contains the whole CRC or a part
1433 * of it, free the mbuf associated to the last buffer. If part
1434 * of the CRC is also contained in the previous mbuf, subtract
1435 * the length of that CRC part from the data length of the
1439 if (unlikely(rxq->crc_len > 0)) {
1440 first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
1441 if (rx_packet_len <= RTE_ETHER_CRC_LEN) {
1442 rte_pktmbuf_free_seg(rxm);
1443 first_seg->nb_segs--;
1444 last_seg->data_len =
1445 (uint16_t)(last_seg->data_len -
1446 (RTE_ETHER_CRC_LEN - rx_packet_len));
1447 last_seg->next = NULL;
1449 rxm->data_len = (uint16_t)(rx_packet_len -
1454 first_seg->port = rxq->port_id;
1455 first_seg->ol_flags = 0;
1456 first_seg->packet_type = ptype_tbl[IAVF_RX_FLEX_DESC_PTYPE_M &
1457 rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
1458 iavf_flex_rxd_to_vlan_tci(first_seg, &rxd);
1459 rxq->rxd_to_pkt_fields(rxq, first_seg, &rxd);
1460 pkt_flags = iavf_flex_rxd_error_to_pkt_flags(rx_stat_err0);
1462 first_seg->ol_flags |= pkt_flags;
1464 /* Prefetch data of first segment, if configured to do so. */
1465 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1466 first_seg->data_off));
1467 rx_pkts[nb_rx++] = first_seg;
1471 /* Record index of the next RX descriptor to probe. */
1472 rxq->rx_tail = rx_id;
1473 rxq->pkt_first_seg = first_seg;
1474 rxq->pkt_last_seg = last_seg;
1476 iavf_update_rx_tail(rxq, nb_hold, rx_id);
1481 /* implement recv_scattered_pkts */
1483 iavf_recv_scattered_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1486 struct iavf_rx_queue *rxq = rx_queue;
1487 union iavf_rx_desc rxd;
1488 struct rte_mbuf *rxe;
1489 struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1490 struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1491 struct rte_mbuf *nmb, *rxm;
1492 uint16_t rx_id = rxq->rx_tail;
1493 uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
1494 struct rte_eth_dev *dev;
1500 volatile union iavf_rx_desc *rx_ring = rxq->rx_ring;
1501 volatile union iavf_rx_desc *rxdp;
1502 const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1504 while (nb_rx < nb_pkts) {
1505 rxdp = &rx_ring[rx_id];
1506 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1507 rx_status = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
1508 IAVF_RXD_QW1_STATUS_SHIFT;
1510 /* Check the DD bit */
1511 if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)))
1513 IAVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
1515 nmb = rte_mbuf_raw_alloc(rxq->mp);
1516 if (unlikely(!nmb)) {
1517 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1518 "queue_id=%u", rxq->port_id, rxq->queue_id);
1519 dev = &rte_eth_devices[rxq->port_id];
1520 dev->data->rx_mbuf_alloc_failed++;
1526 rxe = rxq->sw_ring[rx_id];
1528 if (rx_id == rxq->nb_rx_desc)
1531 /* Prefetch next mbuf */
1532 rte_prefetch0(rxq->sw_ring[rx_id]);
1534 /* When next RX descriptor is on a cache line boundary,
1535 * prefetch the next 4 RX descriptors and next 8 pointers
1538 if ((rx_id & 0x3) == 0) {
1539 rte_prefetch0(&rx_ring[rx_id]);
1540 rte_prefetch0(rxq->sw_ring[rx_id]);
1545 rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1547 /* Set data buffer address and data length of the mbuf */
1548 rxdp->read.hdr_addr = 0;
1549 rxdp->read.pkt_addr = dma_addr;
1550 rx_packet_len = (qword1 & IAVF_RXD_QW1_LENGTH_PBUF_MASK) >>
1551 IAVF_RXD_QW1_LENGTH_PBUF_SHIFT;
1552 rxm->data_len = rx_packet_len;
1553 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1555 /* If this is the first buffer of the received packet, set the
1556 * pointer to the first mbuf of the packet and initialize its
1557 * context. Otherwise, update the total length and the number
1558 * of segments of the current scattered packet, and update the
1559 * pointer to the last mbuf of the current packet.
1563 first_seg->nb_segs = 1;
1564 first_seg->pkt_len = rx_packet_len;
1566 first_seg->pkt_len =
1567 (uint16_t)(first_seg->pkt_len +
1569 first_seg->nb_segs++;
1570 last_seg->next = rxm;
1573 /* If this is not the last buffer of the received packet,
1574 * update the pointer to the last mbuf of the current scattered
1575 * packet and continue to parse the RX ring.
1577 if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_EOF_SHIFT))) {
1582 /* This is the last buffer of the received packet. If the CRC
1583 * is not stripped by the hardware:
1584 * - Subtract the CRC length from the total packet length.
1585 * - If the last buffer only contains the whole CRC or a part
1586 * of it, free the mbuf associated to the last buffer. If part
1587 * of the CRC is also contained in the previous mbuf, subtract
1588 * the length of that CRC part from the data length of the
1592 if (unlikely(rxq->crc_len > 0)) {
1593 first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
1594 if (rx_packet_len <= RTE_ETHER_CRC_LEN) {
1595 rte_pktmbuf_free_seg(rxm);
1596 first_seg->nb_segs--;
1597 last_seg->data_len =
1598 (uint16_t)(last_seg->data_len -
1599 (RTE_ETHER_CRC_LEN - rx_packet_len));
1600 last_seg->next = NULL;
1602 rxm->data_len = (uint16_t)(rx_packet_len -
1606 first_seg->port = rxq->port_id;
1607 first_seg->ol_flags = 0;
1608 iavf_rxd_to_vlan_tci(first_seg, &rxd);
1609 pkt_flags = iavf_rxd_to_pkt_flags(qword1);
1610 first_seg->packet_type =
1611 ptype_tbl[(uint8_t)((qword1 &
1612 IAVF_RXD_QW1_PTYPE_MASK) >> IAVF_RXD_QW1_PTYPE_SHIFT)];
1614 if (pkt_flags & PKT_RX_RSS_HASH)
1615 first_seg->hash.rss =
1616 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1618 if (pkt_flags & PKT_RX_FDIR)
1619 pkt_flags |= iavf_rxd_build_fdir(&rxd, first_seg);
1621 first_seg->ol_flags |= pkt_flags;
1623 /* Prefetch data of first segment, if configured to do so. */
1624 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1625 first_seg->data_off));
1626 rx_pkts[nb_rx++] = first_seg;
1630 /* Record index of the next RX descriptor to probe. */
1631 rxq->rx_tail = rx_id;
1632 rxq->pkt_first_seg = first_seg;
1633 rxq->pkt_last_seg = last_seg;
1635 iavf_update_rx_tail(rxq, nb_hold, rx_id);
1640 #define IAVF_LOOK_AHEAD 8
1642 iavf_rx_scan_hw_ring_flex_rxd(struct iavf_rx_queue *rxq)
1644 volatile union iavf_rx_flex_desc *rxdp;
1645 struct rte_mbuf **rxep;
1646 struct rte_mbuf *mb;
1649 int32_t s[IAVF_LOOK_AHEAD], nb_dd;
1650 int32_t i, j, nb_rx = 0;
1652 const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1654 rxdp = (volatile union iavf_rx_flex_desc *)&rxq->rx_ring[rxq->rx_tail];
1655 rxep = &rxq->sw_ring[rxq->rx_tail];
1657 stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1659 /* Make sure there is at least 1 packet to receive */
1660 if (!(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S)))
1663 /* Scan LOOK_AHEAD descriptors at a time to determine which
1664 * descriptors reference packets that are ready to be received.
1666 for (i = 0; i < IAVF_RX_MAX_BURST; i += IAVF_LOOK_AHEAD,
1667 rxdp += IAVF_LOOK_AHEAD, rxep += IAVF_LOOK_AHEAD) {
1668 /* Read desc statuses backwards to avoid race condition */
1669 for (j = IAVF_LOOK_AHEAD - 1; j >= 0; j--)
1670 s[j] = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1674 /* Compute how many status bits were set */
1675 for (j = 0, nb_dd = 0; j < IAVF_LOOK_AHEAD; j++)
1676 nb_dd += s[j] & (1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S);
1680 /* Translate descriptor info to mbuf parameters */
1681 for (j = 0; j < nb_dd; j++) {
1682 IAVF_DUMP_RX_DESC(rxq, &rxdp[j],
1684 i * IAVF_LOOK_AHEAD + j);
1687 pkt_len = (rte_le_to_cpu_16(rxdp[j].wb.pkt_len) &
1688 IAVF_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
1689 mb->data_len = pkt_len;
1690 mb->pkt_len = pkt_len;
1693 mb->packet_type = ptype_tbl[IAVF_RX_FLEX_DESC_PTYPE_M &
1694 rte_le_to_cpu_16(rxdp[j].wb.ptype_flex_flags0)];
1695 iavf_flex_rxd_to_vlan_tci(mb, &rxdp[j]);
1696 rxq->rxd_to_pkt_fields(rxq, mb, &rxdp[j]);
1697 stat_err0 = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1698 pkt_flags = iavf_flex_rxd_error_to_pkt_flags(stat_err0);
1700 mb->ol_flags |= pkt_flags;
1703 for (j = 0; j < IAVF_LOOK_AHEAD; j++)
1704 rxq->rx_stage[i + j] = rxep[j];
1706 if (nb_dd != IAVF_LOOK_AHEAD)
1710 /* Clear software ring entries */
1711 for (i = 0; i < nb_rx; i++)
1712 rxq->sw_ring[rxq->rx_tail + i] = NULL;
1718 iavf_rx_scan_hw_ring(struct iavf_rx_queue *rxq)
1720 volatile union iavf_rx_desc *rxdp;
1721 struct rte_mbuf **rxep;
1722 struct rte_mbuf *mb;
1726 int32_t s[IAVF_LOOK_AHEAD], nb_dd;
1727 int32_t i, j, nb_rx = 0;
1729 const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1731 rxdp = &rxq->rx_ring[rxq->rx_tail];
1732 rxep = &rxq->sw_ring[rxq->rx_tail];
1734 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1735 rx_status = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
1736 IAVF_RXD_QW1_STATUS_SHIFT;
1738 /* Make sure there is at least 1 packet to receive */
1739 if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)))
1742 /* Scan LOOK_AHEAD descriptors at a time to determine which
1743 * descriptors reference packets that are ready to be received.
1745 for (i = 0; i < IAVF_RX_MAX_BURST; i += IAVF_LOOK_AHEAD,
1746 rxdp += IAVF_LOOK_AHEAD, rxep += IAVF_LOOK_AHEAD) {
1747 /* Read desc statuses backwards to avoid race condition */
1748 for (j = IAVF_LOOK_AHEAD - 1; j >= 0; j--) {
1749 qword1 = rte_le_to_cpu_64(
1750 rxdp[j].wb.qword1.status_error_len);
1751 s[j] = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
1752 IAVF_RXD_QW1_STATUS_SHIFT;
1757 /* Compute how many status bits were set */
1758 for (j = 0, nb_dd = 0; j < IAVF_LOOK_AHEAD; j++)
1759 nb_dd += s[j] & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT);
1763 /* Translate descriptor info to mbuf parameters */
1764 for (j = 0; j < nb_dd; j++) {
1765 IAVF_DUMP_RX_DESC(rxq, &rxdp[j],
1766 rxq->rx_tail + i * IAVF_LOOK_AHEAD + j);
1769 qword1 = rte_le_to_cpu_64
1770 (rxdp[j].wb.qword1.status_error_len);
1771 pkt_len = ((qword1 & IAVF_RXD_QW1_LENGTH_PBUF_MASK) >>
1772 IAVF_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
1773 mb->data_len = pkt_len;
1774 mb->pkt_len = pkt_len;
1776 iavf_rxd_to_vlan_tci(mb, &rxdp[j]);
1777 pkt_flags = iavf_rxd_to_pkt_flags(qword1);
1779 ptype_tbl[(uint8_t)((qword1 &
1780 IAVF_RXD_QW1_PTYPE_MASK) >>
1781 IAVF_RXD_QW1_PTYPE_SHIFT)];
1783 if (pkt_flags & PKT_RX_RSS_HASH)
1784 mb->hash.rss = rte_le_to_cpu_32(
1785 rxdp[j].wb.qword0.hi_dword.rss);
1787 if (pkt_flags & PKT_RX_FDIR)
1788 pkt_flags |= iavf_rxd_build_fdir(&rxdp[j], mb);
1790 mb->ol_flags |= pkt_flags;
1793 for (j = 0; j < IAVF_LOOK_AHEAD; j++)
1794 rxq->rx_stage[i + j] = rxep[j];
1796 if (nb_dd != IAVF_LOOK_AHEAD)
1800 /* Clear software ring entries */
1801 for (i = 0; i < nb_rx; i++)
1802 rxq->sw_ring[rxq->rx_tail + i] = NULL;
1807 static inline uint16_t
1808 iavf_rx_fill_from_stage(struct iavf_rx_queue *rxq,
1809 struct rte_mbuf **rx_pkts,
1813 struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1815 nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1817 for (i = 0; i < nb_pkts; i++)
1818 rx_pkts[i] = stage[i];
1820 rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1821 rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1827 iavf_rx_alloc_bufs(struct iavf_rx_queue *rxq)
1829 volatile union iavf_rx_desc *rxdp;
1830 struct rte_mbuf **rxep;
1831 struct rte_mbuf *mb;
1832 uint16_t alloc_idx, i;
1836 /* Allocate buffers in bulk */
1837 alloc_idx = (uint16_t)(rxq->rx_free_trigger -
1838 (rxq->rx_free_thresh - 1));
1839 rxep = &rxq->sw_ring[alloc_idx];
1840 diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
1841 rxq->rx_free_thresh);
1842 if (unlikely(diag != 0)) {
1843 PMD_RX_LOG(ERR, "Failed to get mbufs in bulk");
1847 rxdp = &rxq->rx_ring[alloc_idx];
1848 for (i = 0; i < rxq->rx_free_thresh; i++) {
1849 if (likely(i < (rxq->rx_free_thresh - 1)))
1850 /* Prefetch next mbuf */
1851 rte_prefetch0(rxep[i + 1]);
1854 rte_mbuf_refcnt_set(mb, 1);
1856 mb->data_off = RTE_PKTMBUF_HEADROOM;
1858 mb->port = rxq->port_id;
1859 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mb));
1860 rxdp[i].read.hdr_addr = 0;
1861 rxdp[i].read.pkt_addr = dma_addr;
1864 /* Update rx tail register */
1866 IAVF_PCI_REG_WRITE_RELAXED(rxq->qrx_tail, rxq->rx_free_trigger);
1868 rxq->rx_free_trigger =
1869 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
1870 if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1871 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
1876 static inline uint16_t
1877 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1879 struct iavf_rx_queue *rxq = (struct iavf_rx_queue *)rx_queue;
1885 if (rxq->rx_nb_avail)
1886 return iavf_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1888 if (rxq->rxdid >= IAVF_RXDID_FLEX_NIC && rxq->rxdid <= IAVF_RXDID_LAST)
1889 nb_rx = (uint16_t)iavf_rx_scan_hw_ring_flex_rxd(rxq);
1891 nb_rx = (uint16_t)iavf_rx_scan_hw_ring(rxq);
1892 rxq->rx_next_avail = 0;
1893 rxq->rx_nb_avail = nb_rx;
1894 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1896 if (rxq->rx_tail > rxq->rx_free_trigger) {
1897 if (iavf_rx_alloc_bufs(rxq) != 0) {
1900 /* TODO: count rx_mbuf_alloc_failed here */
1902 rxq->rx_nb_avail = 0;
1903 rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1904 for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
1905 rxq->sw_ring[j] = rxq->rx_stage[i];
1911 if (rxq->rx_tail >= rxq->nb_rx_desc)
1914 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u, nb_rx=%u",
1915 rxq->port_id, rxq->queue_id,
1916 rxq->rx_tail, nb_rx);
1918 if (rxq->rx_nb_avail)
1919 return iavf_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1925 iavf_recv_pkts_bulk_alloc(void *rx_queue,
1926 struct rte_mbuf **rx_pkts,
1929 uint16_t nb_rx = 0, n, count;
1931 if (unlikely(nb_pkts == 0))
1934 if (likely(nb_pkts <= IAVF_RX_MAX_BURST))
1935 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1938 n = RTE_MIN(nb_pkts, IAVF_RX_MAX_BURST);
1939 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1940 nb_rx = (uint16_t)(nb_rx + count);
1941 nb_pkts = (uint16_t)(nb_pkts - count);
1950 iavf_xmit_cleanup(struct iavf_tx_queue *txq)
1952 struct iavf_tx_entry *sw_ring = txq->sw_ring;
1953 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
1954 uint16_t nb_tx_desc = txq->nb_tx_desc;
1955 uint16_t desc_to_clean_to;
1956 uint16_t nb_tx_to_clean;
1958 volatile struct iavf_tx_desc *txd = txq->tx_ring;
1960 desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->rs_thresh);
1961 if (desc_to_clean_to >= nb_tx_desc)
1962 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
1964 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
1965 if ((txd[desc_to_clean_to].cmd_type_offset_bsz &
1966 rte_cpu_to_le_64(IAVF_TXD_QW1_DTYPE_MASK)) !=
1967 rte_cpu_to_le_64(IAVF_TX_DESC_DTYPE_DESC_DONE)) {
1968 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
1969 "(port=%d queue=%d)", desc_to_clean_to,
1970 txq->port_id, txq->queue_id);
1974 if (last_desc_cleaned > desc_to_clean_to)
1975 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
1978 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
1981 txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
1983 txq->last_desc_cleaned = desc_to_clean_to;
1984 txq->nb_free = (uint16_t)(txq->nb_free + nb_tx_to_clean);
1989 /* Check if the context descriptor is needed for TX offloading */
1990 static inline uint16_t
1991 iavf_calc_context_desc(uint64_t flags, uint8_t vlan_flag)
1993 if (flags & PKT_TX_TCP_SEG)
1995 if (flags & PKT_TX_VLAN_PKT &&
1996 vlan_flag & IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG2)
2002 iavf_txd_enable_checksum(uint64_t ol_flags,
2004 uint32_t *td_offset,
2005 union iavf_tx_offload tx_offload)
2008 *td_offset |= (tx_offload.l2_len >> 1) <<
2009 IAVF_TX_DESC_LENGTH_MACLEN_SHIFT;
2011 /* Enable L3 checksum offloads */
2012 if (ol_flags & PKT_TX_IP_CKSUM) {
2013 *td_cmd |= IAVF_TX_DESC_CMD_IIPT_IPV4_CSUM;
2014 *td_offset |= (tx_offload.l3_len >> 2) <<
2015 IAVF_TX_DESC_LENGTH_IPLEN_SHIFT;
2016 } else if (ol_flags & PKT_TX_IPV4) {
2017 *td_cmd |= IAVF_TX_DESC_CMD_IIPT_IPV4;
2018 *td_offset |= (tx_offload.l3_len >> 2) <<
2019 IAVF_TX_DESC_LENGTH_IPLEN_SHIFT;
2020 } else if (ol_flags & PKT_TX_IPV6) {
2021 *td_cmd |= IAVF_TX_DESC_CMD_IIPT_IPV6;
2022 *td_offset |= (tx_offload.l3_len >> 2) <<
2023 IAVF_TX_DESC_LENGTH_IPLEN_SHIFT;
2026 if (ol_flags & PKT_TX_TCP_SEG) {
2027 *td_cmd |= IAVF_TX_DESC_CMD_L4T_EOFT_TCP;
2028 *td_offset |= (tx_offload.l4_len >> 2) <<
2029 IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2033 /* Enable L4 checksum offloads */
2034 switch (ol_flags & PKT_TX_L4_MASK) {
2035 case PKT_TX_TCP_CKSUM:
2036 *td_cmd |= IAVF_TX_DESC_CMD_L4T_EOFT_TCP;
2037 *td_offset |= (sizeof(struct rte_tcp_hdr) >> 2) <<
2038 IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2040 case PKT_TX_SCTP_CKSUM:
2041 *td_cmd |= IAVF_TX_DESC_CMD_L4T_EOFT_SCTP;
2042 *td_offset |= (sizeof(struct rte_sctp_hdr) >> 2) <<
2043 IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2045 case PKT_TX_UDP_CKSUM:
2046 *td_cmd |= IAVF_TX_DESC_CMD_L4T_EOFT_UDP;
2047 *td_offset |= (sizeof(struct rte_udp_hdr) >> 2) <<
2048 IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2055 /* set TSO context descriptor
2056 * support IP -> L4 and IP -> IP -> L4
2058 static inline uint64_t
2059 iavf_set_tso_ctx(struct rte_mbuf *mbuf, union iavf_tx_offload tx_offload)
2061 uint64_t ctx_desc = 0;
2062 uint32_t cd_cmd, hdr_len, cd_tso_len;
2064 if (!tx_offload.l4_len) {
2065 PMD_TX_LOG(DEBUG, "L4 length set to 0");
2069 hdr_len = tx_offload.l2_len +
2073 cd_cmd = IAVF_TX_CTX_DESC_TSO;
2074 cd_tso_len = mbuf->pkt_len - hdr_len;
2075 ctx_desc |= ((uint64_t)cd_cmd << IAVF_TXD_CTX_QW1_CMD_SHIFT) |
2076 ((uint64_t)cd_tso_len << IAVF_TXD_CTX_QW1_TSO_LEN_SHIFT) |
2077 ((uint64_t)mbuf->tso_segsz << IAVF_TXD_CTX_QW1_MSS_SHIFT);
2082 /* Construct the tx flags */
2083 static inline uint64_t
2084 iavf_build_ctob(uint32_t td_cmd, uint32_t td_offset, unsigned int size,
2087 return rte_cpu_to_le_64(IAVF_TX_DESC_DTYPE_DATA |
2088 ((uint64_t)td_cmd << IAVF_TXD_QW1_CMD_SHIFT) |
2089 ((uint64_t)td_offset <<
2090 IAVF_TXD_QW1_OFFSET_SHIFT) |
2092 IAVF_TXD_QW1_TX_BUF_SZ_SHIFT) |
2093 ((uint64_t)td_tag <<
2094 IAVF_TXD_QW1_L2TAG1_SHIFT));
2099 iavf_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2101 volatile struct iavf_tx_desc *txd;
2102 volatile struct iavf_tx_desc *txr;
2103 struct iavf_tx_queue *txq;
2104 struct iavf_tx_entry *sw_ring;
2105 struct iavf_tx_entry *txe, *txn;
2106 struct rte_mbuf *tx_pkt;
2107 struct rte_mbuf *m_seg;
2118 uint64_t buf_dma_addr;
2119 uint16_t cd_l2tag2 = 0;
2120 union iavf_tx_offload tx_offload = {0};
2123 sw_ring = txq->sw_ring;
2125 tx_id = txq->tx_tail;
2126 txe = &sw_ring[tx_id];
2128 /* Check if the descriptor ring needs to be cleaned. */
2129 if (txq->nb_free < txq->free_thresh)
2130 (void)iavf_xmit_cleanup(txq);
2132 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
2137 tx_pkt = *tx_pkts++;
2138 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
2140 ol_flags = tx_pkt->ol_flags;
2141 tx_offload.l2_len = tx_pkt->l2_len;
2142 tx_offload.l3_len = tx_pkt->l3_len;
2143 tx_offload.l4_len = tx_pkt->l4_len;
2144 tx_offload.tso_segsz = tx_pkt->tso_segsz;
2145 /* Calculate the number of context descriptors needed. */
2146 nb_ctx = iavf_calc_context_desc(ol_flags, txq->vlan_flag);
2148 /* The number of descriptors that must be allocated for
2149 * a packet equals to the number of the segments of that
2150 * packet plus 1 context descriptor if needed.
2152 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
2153 tx_last = (uint16_t)(tx_id + nb_used - 1);
2156 if (tx_last >= txq->nb_tx_desc)
2157 tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
2159 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u"
2160 " tx_first=%u tx_last=%u",
2161 txq->port_id, txq->queue_id, tx_id, tx_last);
2163 if (nb_used > txq->nb_free) {
2164 if (iavf_xmit_cleanup(txq)) {
2169 if (unlikely(nb_used > txq->rs_thresh)) {
2170 while (nb_used > txq->nb_free) {
2171 if (iavf_xmit_cleanup(txq)) {
2180 /* Descriptor based VLAN insertion */
2181 if (ol_flags & PKT_TX_VLAN_PKT &&
2182 txq->vlan_flag & IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG1) {
2183 td_cmd |= IAVF_TX_DESC_CMD_IL2TAG1;
2184 td_tag = tx_pkt->vlan_tci;
2187 /* According to datasheet, the bit2 is reserved and must be
2192 /* Enable checksum offloading */
2193 if (ol_flags & IAVF_TX_CKSUM_OFFLOAD_MASK)
2194 iavf_txd_enable_checksum(ol_flags, &td_cmd,
2195 &td_offset, tx_offload);
2198 /* Setup TX context descriptor if required */
2199 uint64_t cd_type_cmd_tso_mss =
2200 IAVF_TX_DESC_DTYPE_CONTEXT;
2201 volatile struct iavf_tx_context_desc *ctx_txd =
2202 (volatile struct iavf_tx_context_desc *)
2205 txn = &sw_ring[txe->next_id];
2206 RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
2208 rte_pktmbuf_free_seg(txe->mbuf);
2213 if (ol_flags & PKT_TX_TCP_SEG)
2214 cd_type_cmd_tso_mss |=
2215 iavf_set_tso_ctx(tx_pkt, tx_offload);
2217 if (ol_flags & PKT_TX_VLAN_PKT &&
2218 txq->vlan_flag & IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG2) {
2219 cd_type_cmd_tso_mss |= IAVF_TX_CTX_DESC_IL2TAG2
2220 << IAVF_TXD_CTX_QW1_CMD_SHIFT;
2221 cd_l2tag2 = tx_pkt->vlan_tci;
2224 ctx_txd->type_cmd_tso_mss =
2225 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
2226 ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
2228 IAVF_DUMP_TX_DESC(txq, &txr[tx_id], tx_id);
2229 txe->last_id = tx_last;
2230 tx_id = txe->next_id;
2237 txn = &sw_ring[txe->next_id];
2240 rte_pktmbuf_free_seg(txe->mbuf);
2243 /* Setup TX Descriptor */
2244 slen = m_seg->data_len;
2245 buf_dma_addr = rte_mbuf_data_iova(m_seg);
2246 txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
2247 txd->cmd_type_offset_bsz = iavf_build_ctob(td_cmd,
2252 IAVF_DUMP_TX_DESC(txq, txd, tx_id);
2253 txe->last_id = tx_last;
2254 tx_id = txe->next_id;
2256 m_seg = m_seg->next;
2259 /* The last packet data descriptor needs End Of Packet (EOP) */
2260 td_cmd |= IAVF_TX_DESC_CMD_EOP;
2261 txq->nb_used = (uint16_t)(txq->nb_used + nb_used);
2262 txq->nb_free = (uint16_t)(txq->nb_free - nb_used);
2264 if (txq->nb_used >= txq->rs_thresh) {
2265 PMD_TX_LOG(DEBUG, "Setting RS bit on TXD id="
2266 "%4u (port=%d queue=%d)",
2267 tx_last, txq->port_id, txq->queue_id);
2269 td_cmd |= IAVF_TX_DESC_CMD_RS;
2271 /* Update txq RS bit counters */
2275 txd->cmd_type_offset_bsz |=
2276 rte_cpu_to_le_64(((uint64_t)td_cmd) <<
2277 IAVF_TXD_QW1_CMD_SHIFT);
2278 IAVF_DUMP_TX_DESC(txq, txd, tx_id);
2284 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
2285 txq->port_id, txq->queue_id, tx_id, nb_tx);
2287 IAVF_PCI_REG_WRITE_RELAXED(txq->qtx_tail, tx_id);
2288 txq->tx_tail = tx_id;
2293 /* TX prep functions */
2295 iavf_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
2302 for (i = 0; i < nb_pkts; i++) {
2304 ol_flags = m->ol_flags;
2306 /* Check condition for nb_segs > IAVF_TX_MAX_MTU_SEG. */
2307 if (!(ol_flags & PKT_TX_TCP_SEG)) {
2308 if (m->nb_segs > IAVF_TX_MAX_MTU_SEG) {
2312 } else if ((m->tso_segsz < IAVF_MIN_TSO_MSS) ||
2313 (m->tso_segsz > IAVF_MAX_TSO_MSS)) {
2314 /* MSS outside the range are considered malicious */
2319 if (ol_flags & IAVF_TX_OFFLOAD_NOTSUP_MASK) {
2320 rte_errno = ENOTSUP;
2324 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
2325 ret = rte_validate_tx_offload(m);
2331 ret = rte_net_intel_cksum_prepare(m);
2341 /* choose rx function*/
2343 iavf_set_rx_function(struct rte_eth_dev *dev)
2345 struct iavf_adapter *adapter =
2346 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2347 struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2350 struct iavf_rx_queue *rxq;
2352 bool use_avx2 = false;
2353 #ifdef CC_AVX512_SUPPORT
2354 bool use_avx512 = false;
2357 if (!iavf_rx_vec_dev_check(dev) &&
2358 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
2359 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2360 rxq = dev->data->rx_queues[i];
2361 (void)iavf_rxq_vec_setup(rxq);
2364 if ((rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
2365 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) &&
2366 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256)
2368 #ifdef CC_AVX512_SUPPORT
2369 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 &&
2370 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1 &&
2371 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512)
2375 if (dev->data->scattered_rx) {
2377 "Using %sVector Scattered Rx (port %d).",
2378 use_avx2 ? "avx2 " : "",
2379 dev->data->port_id);
2380 if (vf->vf_res->vf_cap_flags &
2381 VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC) {
2382 dev->rx_pkt_burst = use_avx2 ?
2383 iavf_recv_scattered_pkts_vec_avx2_flex_rxd :
2384 iavf_recv_scattered_pkts_vec_flex_rxd;
2385 #ifdef CC_AVX512_SUPPORT
2388 iavf_recv_scattered_pkts_vec_avx512_flex_rxd;
2391 dev->rx_pkt_burst = use_avx2 ?
2392 iavf_recv_scattered_pkts_vec_avx2 :
2393 iavf_recv_scattered_pkts_vec;
2394 #ifdef CC_AVX512_SUPPORT
2397 iavf_recv_scattered_pkts_vec_avx512;
2401 PMD_DRV_LOG(DEBUG, "Using %sVector Rx (port %d).",
2402 use_avx2 ? "avx2 " : "",
2403 dev->data->port_id);
2404 if (vf->vf_res->vf_cap_flags &
2405 VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC) {
2406 dev->rx_pkt_burst = use_avx2 ?
2407 iavf_recv_pkts_vec_avx2_flex_rxd :
2408 iavf_recv_pkts_vec_flex_rxd;
2409 #ifdef CC_AVX512_SUPPORT
2412 iavf_recv_pkts_vec_avx512_flex_rxd;
2415 dev->rx_pkt_burst = use_avx2 ?
2416 iavf_recv_pkts_vec_avx2 :
2418 #ifdef CC_AVX512_SUPPORT
2421 iavf_recv_pkts_vec_avx512;
2430 if (dev->data->scattered_rx) {
2431 PMD_DRV_LOG(DEBUG, "Using a Scattered Rx callback (port=%d).",
2432 dev->data->port_id);
2433 if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC)
2434 dev->rx_pkt_burst = iavf_recv_scattered_pkts_flex_rxd;
2436 dev->rx_pkt_burst = iavf_recv_scattered_pkts;
2437 } else if (adapter->rx_bulk_alloc_allowed) {
2438 PMD_DRV_LOG(DEBUG, "Using bulk Rx callback (port=%d).",
2439 dev->data->port_id);
2440 dev->rx_pkt_burst = iavf_recv_pkts_bulk_alloc;
2442 PMD_DRV_LOG(DEBUG, "Using Basic Rx callback (port=%d).",
2443 dev->data->port_id);
2444 if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC)
2445 dev->rx_pkt_burst = iavf_recv_pkts_flex_rxd;
2447 dev->rx_pkt_burst = iavf_recv_pkts;
2451 /* choose tx function*/
2453 iavf_set_tx_function(struct rte_eth_dev *dev)
2456 struct iavf_tx_queue *txq;
2458 bool use_avx2 = false;
2459 #ifdef CC_AVX512_SUPPORT
2460 bool use_avx512 = false;
2463 if (!iavf_tx_vec_dev_check(dev) &&
2464 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
2465 if ((rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
2466 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) &&
2467 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256)
2469 #ifdef CC_AVX512_SUPPORT
2470 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 &&
2471 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1 &&
2472 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512)
2476 PMD_DRV_LOG(DEBUG, "Using %sVector Tx (port %d).",
2477 use_avx2 ? "avx2 " : "",
2478 dev->data->port_id);
2479 dev->tx_pkt_burst = use_avx2 ?
2480 iavf_xmit_pkts_vec_avx2 :
2482 #ifdef CC_AVX512_SUPPORT
2484 dev->tx_pkt_burst = iavf_xmit_pkts_vec_avx512;
2486 dev->tx_pkt_prepare = NULL;
2488 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2489 txq = dev->data->tx_queues[i];
2492 #ifdef CC_AVX512_SUPPORT
2494 iavf_txq_vec_setup_avx512(txq);
2496 iavf_txq_vec_setup(txq);
2498 iavf_txq_vec_setup(txq);
2506 PMD_DRV_LOG(DEBUG, "Using Basic Tx callback (port=%d).",
2507 dev->data->port_id);
2508 dev->tx_pkt_burst = iavf_xmit_pkts;
2509 dev->tx_pkt_prepare = iavf_prep_pkts;
2513 iavf_tx_done_cleanup_full(struct iavf_tx_queue *txq,
2516 struct iavf_tx_entry *swr_ring = txq->sw_ring;
2517 uint16_t i, tx_last, tx_id;
2518 uint16_t nb_tx_free_last;
2519 uint16_t nb_tx_to_clean;
2522 /* Start free mbuf from the next of tx_tail */
2523 tx_last = txq->tx_tail;
2524 tx_id = swr_ring[tx_last].next_id;
2526 if (txq->nb_free == 0 && iavf_xmit_cleanup(txq))
2529 nb_tx_to_clean = txq->nb_free;
2530 nb_tx_free_last = txq->nb_free;
2532 free_cnt = txq->nb_tx_desc;
2534 /* Loop through swr_ring to count the amount of
2535 * freeable mubfs and packets.
2537 for (pkt_cnt = 0; pkt_cnt < free_cnt; ) {
2538 for (i = 0; i < nb_tx_to_clean &&
2539 pkt_cnt < free_cnt &&
2540 tx_id != tx_last; i++) {
2541 if (swr_ring[tx_id].mbuf != NULL) {
2542 rte_pktmbuf_free_seg(swr_ring[tx_id].mbuf);
2543 swr_ring[tx_id].mbuf = NULL;
2546 * last segment in the packet,
2547 * increment packet count
2549 pkt_cnt += (swr_ring[tx_id].last_id == tx_id);
2552 tx_id = swr_ring[tx_id].next_id;
2555 if (txq->rs_thresh > txq->nb_tx_desc -
2556 txq->nb_free || tx_id == tx_last)
2559 if (pkt_cnt < free_cnt) {
2560 if (iavf_xmit_cleanup(txq))
2563 nb_tx_to_clean = txq->nb_free - nb_tx_free_last;
2564 nb_tx_free_last = txq->nb_free;
2568 return (int)pkt_cnt;
2572 iavf_dev_tx_done_cleanup(void *txq, uint32_t free_cnt)
2574 struct iavf_tx_queue *q = (struct iavf_tx_queue *)txq;
2576 return iavf_tx_done_cleanup_full(q, free_cnt);
2580 iavf_dev_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2581 struct rte_eth_rxq_info *qinfo)
2583 struct iavf_rx_queue *rxq;
2585 rxq = dev->data->rx_queues[queue_id];
2587 qinfo->mp = rxq->mp;
2588 qinfo->scattered_rx = dev->data->scattered_rx;
2589 qinfo->nb_desc = rxq->nb_rx_desc;
2591 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2592 qinfo->conf.rx_drop_en = true;
2593 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2597 iavf_dev_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2598 struct rte_eth_txq_info *qinfo)
2600 struct iavf_tx_queue *txq;
2602 txq = dev->data->tx_queues[queue_id];
2604 qinfo->nb_desc = txq->nb_tx_desc;
2606 qinfo->conf.tx_free_thresh = txq->free_thresh;
2607 qinfo->conf.tx_rs_thresh = txq->rs_thresh;
2608 qinfo->conf.offloads = txq->offloads;
2609 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2612 /* Get the number of used descriptors of a rx queue */
2614 iavf_dev_rxq_count(struct rte_eth_dev *dev, uint16_t queue_id)
2616 #define IAVF_RXQ_SCAN_INTERVAL 4
2617 volatile union iavf_rx_desc *rxdp;
2618 struct iavf_rx_queue *rxq;
2621 rxq = dev->data->rx_queues[queue_id];
2622 rxdp = &rxq->rx_ring[rxq->rx_tail];
2624 while ((desc < rxq->nb_rx_desc) &&
2625 ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
2626 IAVF_RXD_QW1_STATUS_MASK) >> IAVF_RXD_QW1_STATUS_SHIFT) &
2627 (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)) {
2628 /* Check the DD bit of a rx descriptor of each 4 in a group,
2629 * to avoid checking too frequently and downgrading performance
2632 desc += IAVF_RXQ_SCAN_INTERVAL;
2633 rxdp += IAVF_RXQ_SCAN_INTERVAL;
2634 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
2635 rxdp = &(rxq->rx_ring[rxq->rx_tail +
2636 desc - rxq->nb_rx_desc]);
2643 iavf_dev_rx_desc_status(void *rx_queue, uint16_t offset)
2645 struct iavf_rx_queue *rxq = rx_queue;
2646 volatile uint64_t *status;
2650 if (unlikely(offset >= rxq->nb_rx_desc))
2653 if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
2654 return RTE_ETH_RX_DESC_UNAVAIL;
2656 desc = rxq->rx_tail + offset;
2657 if (desc >= rxq->nb_rx_desc)
2658 desc -= rxq->nb_rx_desc;
2660 status = &rxq->rx_ring[desc].wb.qword1.status_error_len;
2661 mask = rte_le_to_cpu_64((1ULL << IAVF_RX_DESC_STATUS_DD_SHIFT)
2662 << IAVF_RXD_QW1_STATUS_SHIFT);
2664 return RTE_ETH_RX_DESC_DONE;
2666 return RTE_ETH_RX_DESC_AVAIL;
2670 iavf_dev_tx_desc_status(void *tx_queue, uint16_t offset)
2672 struct iavf_tx_queue *txq = tx_queue;
2673 volatile uint64_t *status;
2674 uint64_t mask, expect;
2677 if (unlikely(offset >= txq->nb_tx_desc))
2680 desc = txq->tx_tail + offset;
2681 /* go to next desc that has the RS bit */
2682 desc = ((desc + txq->rs_thresh - 1) / txq->rs_thresh) *
2684 if (desc >= txq->nb_tx_desc) {
2685 desc -= txq->nb_tx_desc;
2686 if (desc >= txq->nb_tx_desc)
2687 desc -= txq->nb_tx_desc;
2690 status = &txq->tx_ring[desc].cmd_type_offset_bsz;
2691 mask = rte_le_to_cpu_64(IAVF_TXD_QW1_DTYPE_MASK);
2692 expect = rte_cpu_to_le_64(
2693 IAVF_TX_DESC_DTYPE_DESC_DONE << IAVF_TXD_QW1_DTYPE_SHIFT);
2694 if ((*status & mask) == expect)
2695 return RTE_ETH_TX_DESC_DONE;
2697 return RTE_ETH_TX_DESC_FULL;
2701 iavf_get_default_ptype_table(void)
2703 static const uint32_t ptype_tbl[IAVF_MAX_PKT_TYPE]
2704 __rte_cache_aligned = {
2707 [1] = RTE_PTYPE_L2_ETHER,
2708 [2] = RTE_PTYPE_L2_ETHER_TIMESYNC,
2709 /* [3] - [5] reserved */
2710 [6] = RTE_PTYPE_L2_ETHER_LLDP,
2711 /* [7] - [10] reserved */
2712 [11] = RTE_PTYPE_L2_ETHER_ARP,
2713 /* [12] - [21] reserved */
2715 /* Non tunneled IPv4 */
2716 [22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2718 [23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2719 RTE_PTYPE_L4_NONFRAG,
2720 [24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2723 [26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2725 [27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2727 [28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2731 [29] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2732 RTE_PTYPE_TUNNEL_IP |
2733 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2734 RTE_PTYPE_INNER_L4_FRAG,
2735 [30] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2736 RTE_PTYPE_TUNNEL_IP |
2737 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2738 RTE_PTYPE_INNER_L4_NONFRAG,
2739 [31] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2740 RTE_PTYPE_TUNNEL_IP |
2741 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2742 RTE_PTYPE_INNER_L4_UDP,
2744 [33] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2745 RTE_PTYPE_TUNNEL_IP |
2746 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2747 RTE_PTYPE_INNER_L4_TCP,
2748 [34] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2749 RTE_PTYPE_TUNNEL_IP |
2750 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2751 RTE_PTYPE_INNER_L4_SCTP,
2752 [35] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2753 RTE_PTYPE_TUNNEL_IP |
2754 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2755 RTE_PTYPE_INNER_L4_ICMP,
2758 [36] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2759 RTE_PTYPE_TUNNEL_IP |
2760 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2761 RTE_PTYPE_INNER_L4_FRAG,
2762 [37] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2763 RTE_PTYPE_TUNNEL_IP |
2764 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2765 RTE_PTYPE_INNER_L4_NONFRAG,
2766 [38] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2767 RTE_PTYPE_TUNNEL_IP |
2768 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2769 RTE_PTYPE_INNER_L4_UDP,
2771 [40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2772 RTE_PTYPE_TUNNEL_IP |
2773 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2774 RTE_PTYPE_INNER_L4_TCP,
2775 [41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2776 RTE_PTYPE_TUNNEL_IP |
2777 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2778 RTE_PTYPE_INNER_L4_SCTP,
2779 [42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2780 RTE_PTYPE_TUNNEL_IP |
2781 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2782 RTE_PTYPE_INNER_L4_ICMP,
2784 /* IPv4 --> GRE/Teredo/VXLAN */
2785 [43] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2786 RTE_PTYPE_TUNNEL_GRENAT,
2788 /* IPv4 --> GRE/Teredo/VXLAN --> IPv4 */
2789 [44] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2790 RTE_PTYPE_TUNNEL_GRENAT |
2791 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2792 RTE_PTYPE_INNER_L4_FRAG,
2793 [45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2794 RTE_PTYPE_TUNNEL_GRENAT |
2795 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2796 RTE_PTYPE_INNER_L4_NONFRAG,
2797 [46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2798 RTE_PTYPE_TUNNEL_GRENAT |
2799 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2800 RTE_PTYPE_INNER_L4_UDP,
2802 [48] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2803 RTE_PTYPE_TUNNEL_GRENAT |
2804 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2805 RTE_PTYPE_INNER_L4_TCP,
2806 [49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2807 RTE_PTYPE_TUNNEL_GRENAT |
2808 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2809 RTE_PTYPE_INNER_L4_SCTP,
2810 [50] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2811 RTE_PTYPE_TUNNEL_GRENAT |
2812 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2813 RTE_PTYPE_INNER_L4_ICMP,
2815 /* IPv4 --> GRE/Teredo/VXLAN --> IPv6 */
2816 [51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2817 RTE_PTYPE_TUNNEL_GRENAT |
2818 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2819 RTE_PTYPE_INNER_L4_FRAG,
2820 [52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2821 RTE_PTYPE_TUNNEL_GRENAT |
2822 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2823 RTE_PTYPE_INNER_L4_NONFRAG,
2824 [53] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2825 RTE_PTYPE_TUNNEL_GRENAT |
2826 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2827 RTE_PTYPE_INNER_L4_UDP,
2829 [55] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2830 RTE_PTYPE_TUNNEL_GRENAT |
2831 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2832 RTE_PTYPE_INNER_L4_TCP,
2833 [56] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2834 RTE_PTYPE_TUNNEL_GRENAT |
2835 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2836 RTE_PTYPE_INNER_L4_SCTP,
2837 [57] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2838 RTE_PTYPE_TUNNEL_GRENAT |
2839 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2840 RTE_PTYPE_INNER_L4_ICMP,
2842 /* IPv4 --> GRE/Teredo/VXLAN --> MAC */
2843 [58] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2844 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
2846 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
2847 [59] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2848 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2849 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2850 RTE_PTYPE_INNER_L4_FRAG,
2851 [60] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2852 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2853 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2854 RTE_PTYPE_INNER_L4_NONFRAG,
2855 [61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2856 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2857 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2858 RTE_PTYPE_INNER_L4_UDP,
2860 [63] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2861 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2862 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2863 RTE_PTYPE_INNER_L4_TCP,
2864 [64] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2865 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2866 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2867 RTE_PTYPE_INNER_L4_SCTP,
2868 [65] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2869 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2870 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2871 RTE_PTYPE_INNER_L4_ICMP,
2873 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
2874 [66] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2875 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2876 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2877 RTE_PTYPE_INNER_L4_FRAG,
2878 [67] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2879 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2880 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2881 RTE_PTYPE_INNER_L4_NONFRAG,
2882 [68] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2883 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2884 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2885 RTE_PTYPE_INNER_L4_UDP,
2887 [70] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2888 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2889 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2890 RTE_PTYPE_INNER_L4_TCP,
2891 [71] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2892 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2893 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2894 RTE_PTYPE_INNER_L4_SCTP,
2895 [72] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2896 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2897 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2898 RTE_PTYPE_INNER_L4_ICMP,
2899 /* [73] - [87] reserved */
2901 /* Non tunneled IPv6 */
2902 [88] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2904 [89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2905 RTE_PTYPE_L4_NONFRAG,
2906 [90] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2909 [92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2911 [93] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2913 [94] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2917 [95] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2918 RTE_PTYPE_TUNNEL_IP |
2919 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2920 RTE_PTYPE_INNER_L4_FRAG,
2921 [96] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2922 RTE_PTYPE_TUNNEL_IP |
2923 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2924 RTE_PTYPE_INNER_L4_NONFRAG,
2925 [97] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2926 RTE_PTYPE_TUNNEL_IP |
2927 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2928 RTE_PTYPE_INNER_L4_UDP,
2930 [99] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2931 RTE_PTYPE_TUNNEL_IP |
2932 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2933 RTE_PTYPE_INNER_L4_TCP,
2934 [100] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2935 RTE_PTYPE_TUNNEL_IP |
2936 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2937 RTE_PTYPE_INNER_L4_SCTP,
2938 [101] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2939 RTE_PTYPE_TUNNEL_IP |
2940 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2941 RTE_PTYPE_INNER_L4_ICMP,
2944 [102] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2945 RTE_PTYPE_TUNNEL_IP |
2946 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2947 RTE_PTYPE_INNER_L4_FRAG,
2948 [103] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2949 RTE_PTYPE_TUNNEL_IP |
2950 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2951 RTE_PTYPE_INNER_L4_NONFRAG,
2952 [104] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2953 RTE_PTYPE_TUNNEL_IP |
2954 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2955 RTE_PTYPE_INNER_L4_UDP,
2956 /* [105] reserved */
2957 [106] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2958 RTE_PTYPE_TUNNEL_IP |
2959 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2960 RTE_PTYPE_INNER_L4_TCP,
2961 [107] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2962 RTE_PTYPE_TUNNEL_IP |
2963 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2964 RTE_PTYPE_INNER_L4_SCTP,
2965 [108] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2966 RTE_PTYPE_TUNNEL_IP |
2967 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2968 RTE_PTYPE_INNER_L4_ICMP,
2970 /* IPv6 --> GRE/Teredo/VXLAN */
2971 [109] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2972 RTE_PTYPE_TUNNEL_GRENAT,
2974 /* IPv6 --> GRE/Teredo/VXLAN --> IPv4 */
2975 [110] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2976 RTE_PTYPE_TUNNEL_GRENAT |
2977 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2978 RTE_PTYPE_INNER_L4_FRAG,
2979 [111] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2980 RTE_PTYPE_TUNNEL_GRENAT |
2981 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2982 RTE_PTYPE_INNER_L4_NONFRAG,
2983 [112] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2984 RTE_PTYPE_TUNNEL_GRENAT |
2985 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2986 RTE_PTYPE_INNER_L4_UDP,
2987 /* [113] reserved */
2988 [114] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2989 RTE_PTYPE_TUNNEL_GRENAT |
2990 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2991 RTE_PTYPE_INNER_L4_TCP,
2992 [115] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2993 RTE_PTYPE_TUNNEL_GRENAT |
2994 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2995 RTE_PTYPE_INNER_L4_SCTP,
2996 [116] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2997 RTE_PTYPE_TUNNEL_GRENAT |
2998 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2999 RTE_PTYPE_INNER_L4_ICMP,
3001 /* IPv6 --> GRE/Teredo/VXLAN --> IPv6 */
3002 [117] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3003 RTE_PTYPE_TUNNEL_GRENAT |
3004 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3005 RTE_PTYPE_INNER_L4_FRAG,
3006 [118] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3007 RTE_PTYPE_TUNNEL_GRENAT |
3008 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3009 RTE_PTYPE_INNER_L4_NONFRAG,
3010 [119] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3011 RTE_PTYPE_TUNNEL_GRENAT |
3012 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3013 RTE_PTYPE_INNER_L4_UDP,
3014 /* [120] reserved */
3015 [121] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3016 RTE_PTYPE_TUNNEL_GRENAT |
3017 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3018 RTE_PTYPE_INNER_L4_TCP,
3019 [122] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3020 RTE_PTYPE_TUNNEL_GRENAT |
3021 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3022 RTE_PTYPE_INNER_L4_SCTP,
3023 [123] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3024 RTE_PTYPE_TUNNEL_GRENAT |
3025 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3026 RTE_PTYPE_INNER_L4_ICMP,
3028 /* IPv6 --> GRE/Teredo/VXLAN --> MAC */
3029 [124] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3030 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
3032 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
3033 [125] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3034 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3035 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3036 RTE_PTYPE_INNER_L4_FRAG,
3037 [126] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3038 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3039 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3040 RTE_PTYPE_INNER_L4_NONFRAG,
3041 [127] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3042 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3043 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3044 RTE_PTYPE_INNER_L4_UDP,
3045 /* [128] reserved */
3046 [129] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3047 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3048 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3049 RTE_PTYPE_INNER_L4_TCP,
3050 [130] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3051 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3052 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3053 RTE_PTYPE_INNER_L4_SCTP,
3054 [131] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3055 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3056 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3057 RTE_PTYPE_INNER_L4_ICMP,
3059 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
3060 [132] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3061 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3062 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3063 RTE_PTYPE_INNER_L4_FRAG,
3064 [133] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3065 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3066 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3067 RTE_PTYPE_INNER_L4_NONFRAG,
3068 [134] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3069 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3070 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3071 RTE_PTYPE_INNER_L4_UDP,
3072 /* [135] reserved */
3073 [136] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3074 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3075 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3076 RTE_PTYPE_INNER_L4_TCP,
3077 [137] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3078 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3079 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3080 RTE_PTYPE_INNER_L4_SCTP,
3081 [138] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3082 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3083 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3084 RTE_PTYPE_INNER_L4_ICMP,
3085 /* [139] - [299] reserved */
3088 [300] = RTE_PTYPE_L2_ETHER_PPPOE,
3089 [301] = RTE_PTYPE_L2_ETHER_PPPOE,
3091 /* PPPoE --> IPv4 */
3092 [302] = RTE_PTYPE_L2_ETHER_PPPOE |
3093 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3095 [303] = RTE_PTYPE_L2_ETHER_PPPOE |
3096 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3097 RTE_PTYPE_L4_NONFRAG,
3098 [304] = RTE_PTYPE_L2_ETHER_PPPOE |
3099 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3101 [305] = RTE_PTYPE_L2_ETHER_PPPOE |
3102 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3104 [306] = RTE_PTYPE_L2_ETHER_PPPOE |
3105 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3107 [307] = RTE_PTYPE_L2_ETHER_PPPOE |
3108 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3111 /* PPPoE --> IPv6 */
3112 [308] = RTE_PTYPE_L2_ETHER_PPPOE |
3113 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3115 [309] = RTE_PTYPE_L2_ETHER_PPPOE |
3116 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3117 RTE_PTYPE_L4_NONFRAG,
3118 [310] = RTE_PTYPE_L2_ETHER_PPPOE |
3119 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3121 [311] = RTE_PTYPE_L2_ETHER_PPPOE |
3122 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3124 [312] = RTE_PTYPE_L2_ETHER_PPPOE |
3125 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3127 [313] = RTE_PTYPE_L2_ETHER_PPPOE |
3128 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3130 /* [314] - [324] reserved */
3132 /* IPv4/IPv6 --> GTPC/GTPU */
3133 [325] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3134 RTE_PTYPE_TUNNEL_GTPC,
3135 [326] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3136 RTE_PTYPE_TUNNEL_GTPC,
3137 [327] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3138 RTE_PTYPE_TUNNEL_GTPC,
3139 [328] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3140 RTE_PTYPE_TUNNEL_GTPC,
3141 [329] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3142 RTE_PTYPE_TUNNEL_GTPU,
3143 [330] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3144 RTE_PTYPE_TUNNEL_GTPU,
3146 /* IPv4 --> GTPU --> IPv4 */
3147 [331] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3148 RTE_PTYPE_TUNNEL_GTPU |
3149 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3150 RTE_PTYPE_INNER_L4_FRAG,
3151 [332] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3152 RTE_PTYPE_TUNNEL_GTPU |
3153 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3154 RTE_PTYPE_INNER_L4_NONFRAG,
3155 [333] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3156 RTE_PTYPE_TUNNEL_GTPU |
3157 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3158 RTE_PTYPE_INNER_L4_UDP,
3159 [334] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3160 RTE_PTYPE_TUNNEL_GTPU |
3161 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3162 RTE_PTYPE_INNER_L4_TCP,
3163 [335] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3164 RTE_PTYPE_TUNNEL_GTPU |
3165 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3166 RTE_PTYPE_INNER_L4_ICMP,
3168 /* IPv6 --> GTPU --> IPv4 */
3169 [336] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3170 RTE_PTYPE_TUNNEL_GTPU |
3171 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3172 RTE_PTYPE_INNER_L4_FRAG,
3173 [337] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3174 RTE_PTYPE_TUNNEL_GTPU |
3175 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3176 RTE_PTYPE_INNER_L4_NONFRAG,
3177 [338] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3178 RTE_PTYPE_TUNNEL_GTPU |
3179 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3180 RTE_PTYPE_INNER_L4_UDP,
3181 [339] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3182 RTE_PTYPE_TUNNEL_GTPU |
3183 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3184 RTE_PTYPE_INNER_L4_TCP,
3185 [340] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3186 RTE_PTYPE_TUNNEL_GTPU |
3187 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3188 RTE_PTYPE_INNER_L4_ICMP,
3190 /* IPv4 --> GTPU --> IPv6 */
3191 [341] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3192 RTE_PTYPE_TUNNEL_GTPU |
3193 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3194 RTE_PTYPE_INNER_L4_FRAG,
3195 [342] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3196 RTE_PTYPE_TUNNEL_GTPU |
3197 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3198 RTE_PTYPE_INNER_L4_NONFRAG,
3199 [343] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3200 RTE_PTYPE_TUNNEL_GTPU |
3201 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3202 RTE_PTYPE_INNER_L4_UDP,
3203 [344] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3204 RTE_PTYPE_TUNNEL_GTPU |
3205 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3206 RTE_PTYPE_INNER_L4_TCP,
3207 [345] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3208 RTE_PTYPE_TUNNEL_GTPU |
3209 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3210 RTE_PTYPE_INNER_L4_ICMP,
3212 /* IPv6 --> GTPU --> IPv6 */
3213 [346] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3214 RTE_PTYPE_TUNNEL_GTPU |
3215 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3216 RTE_PTYPE_INNER_L4_FRAG,
3217 [347] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3218 RTE_PTYPE_TUNNEL_GTPU |
3219 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3220 RTE_PTYPE_INNER_L4_NONFRAG,
3221 [348] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3222 RTE_PTYPE_TUNNEL_GTPU |
3223 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3224 RTE_PTYPE_INNER_L4_UDP,
3225 [349] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3226 RTE_PTYPE_TUNNEL_GTPU |
3227 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3228 RTE_PTYPE_INNER_L4_TCP,
3229 [350] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3230 RTE_PTYPE_TUNNEL_GTPU |
3231 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3232 RTE_PTYPE_INNER_L4_ICMP,
3234 /* IPv4 --> UDP ECPRI */
3235 [372] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3237 [373] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3239 [374] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3241 [375] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3243 [376] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3245 [377] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3247 [378] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3249 [379] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3251 [380] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3253 [381] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3256 /* IPV6 --> UDP ECPRI */
3257 [382] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3259 [383] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3261 [384] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3263 [385] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3265 [386] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3267 [387] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3269 [388] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3271 [389] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3273 [390] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3275 [391] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3277 /* All others reserved */