drivers/net/iavf/iavf_rxtx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2017 Intel Corporation
   3  */
   4
   5 #include <stdio.h>
   6 #include <stdlib.h>
   7 #include <string.h>
   8 #include <errno.h>
   9 #include <stdint.h>
  10 #include <stdarg.h>
  11 #include <unistd.h>
  12 #include <inttypes.h>
  13 #include <sys/queue.h>
  14
  15 #include <rte_string_fns.h>
  16 #include <rte_memzone.h>
  17 #include <rte_mbuf.h>
  18 #include <rte_malloc.h>
  19 #include <rte_ether.h>
  20 #include <ethdev_driver.h>
  21 #include <rte_tcp.h>
  22 #include <rte_sctp.h>
  23 #include <rte_udp.h>
  24 #include <rte_ip.h>
  25 #include <rte_net.h>
  26 #include <rte_vect.h>
  27
  28 #include "iavf.h"
  29 #include "iavf_rxtx.h"
  30 #include "iavf_ipsec_crypto.h"
  31 #include "rte_pmd_iavf.h"
  32
  33 /* Offset of mbuf dynamic field for protocol extraction's metadata */
  34 int rte_pmd_ifd_dynfield_proto_xtr_metadata_offs = -1;
  35
  36 /* Mask of mbuf dynamic flags for protocol extraction's type */
  37 uint64_t rte_pmd_ifd_dynflag_proto_xtr_vlan_mask;
  38 uint64_t rte_pmd_ifd_dynflag_proto_xtr_ipv4_mask;
  39 uint64_t rte_pmd_ifd_dynflag_proto_xtr_ipv6_mask;
  40 uint64_t rte_pmd_ifd_dynflag_proto_xtr_ipv6_flow_mask;
  41 uint64_t rte_pmd_ifd_dynflag_proto_xtr_tcp_mask;
  42 uint64_t rte_pmd_ifd_dynflag_proto_xtr_ip_offset_mask;
  43 uint64_t rte_pmd_ifd_dynflag_proto_xtr_ipsec_crypto_said_mask;
  44
  45 uint8_t
  46 iavf_proto_xtr_type_to_rxdid(uint8_t flex_type)
  47 {
  48         static uint8_t rxdid_map[] = {
  49                 [IAVF_PROTO_XTR_NONE]      = IAVF_RXDID_COMMS_OVS_1,
  50                 [IAVF_PROTO_XTR_VLAN]      = IAVF_RXDID_COMMS_AUX_VLAN,
  51                 [IAVF_PROTO_XTR_IPV4]      = IAVF_RXDID_COMMS_AUX_IPV4,
  52                 [IAVF_PROTO_XTR_IPV6]      = IAVF_RXDID_COMMS_AUX_IPV6,
  53                 [IAVF_PROTO_XTR_IPV6_FLOW] = IAVF_RXDID_COMMS_AUX_IPV6_FLOW,
  54                 [IAVF_PROTO_XTR_TCP]       = IAVF_RXDID_COMMS_AUX_TCP,
  55                 [IAVF_PROTO_XTR_IP_OFFSET] = IAVF_RXDID_COMMS_AUX_IP_OFFSET,
  56                 [IAVF_PROTO_XTR_IPSEC_CRYPTO_SAID] =
  57                                 IAVF_RXDID_COMMS_IPSEC_CRYPTO,
  58         };
  59
  60         return flex_type < RTE_DIM(rxdid_map) ?
  61                                 rxdid_map[flex_type] : IAVF_RXDID_COMMS_OVS_1;
  62 }
  63
  64 static int
  65 iavf_monitor_callback(const uint64_t value,
  66                 const uint64_t arg[RTE_POWER_MONITOR_OPAQUE_SZ] __rte_unused)
  67 {
  68         const uint64_t m = rte_cpu_to_le_64(1 << IAVF_RX_DESC_STATUS_DD_SHIFT);
  69         /*
  70          * we expect the DD bit to be set to 1 if this descriptor was already
  71          * written to.
  72          */
  73         return (value & m) == m ? -1 : 0;
  74 }
  75
  76 int
  77 iavf_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc)
  78 {
  79         struct iavf_rx_queue *rxq = rx_queue;
  80         volatile union iavf_rx_desc *rxdp;
  81         uint16_t desc;
  82
  83         desc = rxq->rx_tail;
  84         rxdp = &rxq->rx_ring[desc];
  85         /* watch for changes in status bit */
  86         pmc->addr = &rxdp->wb.qword1.status_error_len;
  87
  88         /* comparison callback */
  89         pmc->fn = iavf_monitor_callback;
  90
  91         /* registers are 64-bit */
  92         pmc->size = sizeof(uint64_t);
  93
  94         return 0;
  95 }
  96
  97 static inline int
  98 check_rx_thresh(uint16_t nb_desc, uint16_t thresh)
  99 {
 100         /* The following constraints must be satisfied:
 101          *   thresh < rxq->nb_rx_desc
 102          */
 103         if (thresh >= nb_desc) {
 104                 PMD_INIT_LOG(ERR, "rx_free_thresh (%u) must be less than %u",
 105                              thresh, nb_desc);
 106                 return -EINVAL;
 107         }
 108         return 0;
 109 }
 110
 111 static inline int
 112 check_tx_thresh(uint16_t nb_desc, uint16_t tx_rs_thresh,
 113                 uint16_t tx_free_thresh)
 114 {
 115         /* TX descriptors will have their RS bit set after tx_rs_thresh
 116          * descriptors have been used. The TX descriptor ring will be cleaned
 117          * after tx_free_thresh descriptors are used or if the number of
 118          * descriptors required to transmit a packet is greater than the
 119          * number of free TX descriptors.
 120          *
 121          * The following constraints must be satisfied:
 122          *  - tx_rs_thresh must be less than the size of the ring minus 2.
 123          *  - tx_free_thresh must be less than the size of the ring minus 3.
 124          *  - tx_rs_thresh must be less than or equal to tx_free_thresh.
 125          *  - tx_rs_thresh must be a divisor of the ring size.
 126          *
 127          * One descriptor in the TX ring is used as a sentinel to avoid a H/W
 128          * race condition, hence the maximum threshold constraints. When set
 129          * to zero use default values.
 130          */
 131         if (tx_rs_thresh >= (nb_desc - 2)) {
 132                 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be less than the "
 133                              "number of TX descriptors (%u) minus 2",
 134                              tx_rs_thresh, nb_desc);
 135                 return -EINVAL;
 136         }
 137         if (tx_free_thresh >= (nb_desc - 3)) {
 138                 PMD_INIT_LOG(ERR, "tx_free_thresh (%u) must be less than the "
 139                              "number of TX descriptors (%u) minus 3.",
 140                              tx_free_thresh, nb_desc);
 141                 return -EINVAL;
 142         }
 143         if (tx_rs_thresh > tx_free_thresh) {
 144                 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be less than or "
 145                              "equal to tx_free_thresh (%u).",
 146                              tx_rs_thresh, tx_free_thresh);
 147                 return -EINVAL;
 148         }
 149         if ((nb_desc % tx_rs_thresh) != 0) {
 150                 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be a divisor of the "
 151                              "number of TX descriptors (%u).",
 152                              tx_rs_thresh, nb_desc);
 153                 return -EINVAL;
 154         }
 155
 156         return 0;
 157 }
 158
 159 static inline bool
 160 check_rx_vec_allow(struct iavf_rx_queue *rxq)
 161 {
 162         if (rxq->rx_free_thresh >= IAVF_VPMD_RX_MAX_BURST &&
 163             rxq->nb_rx_desc % rxq->rx_free_thresh == 0) {
 164                 PMD_INIT_LOG(DEBUG, "Vector Rx can be enabled on this rxq.");
 165                 return true;
 166         }
 167
 168         PMD_INIT_LOG(DEBUG, "Vector Rx cannot be enabled on this rxq.");
 169         return false;
 170 }
 171
 172 static inline bool
 173 check_tx_vec_allow(struct iavf_tx_queue *txq)
 174 {
 175         if (!(txq->offloads & IAVF_TX_NO_VECTOR_FLAGS) &&
 176             txq->rs_thresh >= IAVF_VPMD_TX_MAX_BURST &&
 177             txq->rs_thresh <= IAVF_VPMD_TX_MAX_FREE_BUF) {
 178                 PMD_INIT_LOG(DEBUG, "Vector tx can be enabled on this txq.");
 179                 return true;
 180         }
 181         PMD_INIT_LOG(DEBUG, "Vector Tx cannot be enabled on this txq.");
 182         return false;
 183 }
 184
 185 static inline bool
 186 check_rx_bulk_allow(struct iavf_rx_queue *rxq)
 187 {
 188         int ret = true;
 189
 190         if (!(rxq->rx_free_thresh >= IAVF_RX_MAX_BURST)) {
 191                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 192                              "rxq->rx_free_thresh=%d, "
 193                              "IAVF_RX_MAX_BURST=%d",
 194                              rxq->rx_free_thresh, IAVF_RX_MAX_BURST);
 195                 ret = false;
 196         } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
 197                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 198                              "rxq->nb_rx_desc=%d, "
 199                              "rxq->rx_free_thresh=%d",
 200                              rxq->nb_rx_desc, rxq->rx_free_thresh);
 201                 ret = false;
 202         }
 203         return ret;
 204 }
 205
 206 static inline void
 207 reset_rx_queue(struct iavf_rx_queue *rxq)
 208 {
 209         uint16_t len;
 210         uint32_t i;
 211
 212         if (!rxq)
 213                 return;
 214
 215         len = rxq->nb_rx_desc + IAVF_RX_MAX_BURST;
 216
 217         for (i = 0; i < len * sizeof(union iavf_rx_desc); i++)
 218                 ((volatile char *)rxq->rx_ring)[i] = 0;
 219
 220         memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
 221
 222         for (i = 0; i < IAVF_RX_MAX_BURST; i++)
 223                 rxq->sw_ring[rxq->nb_rx_desc + i] = &rxq->fake_mbuf;
 224
 225         /* for rx bulk */
 226         rxq->rx_nb_avail = 0;
 227         rxq->rx_next_avail = 0;
 228         rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
 229
 230         rxq->rx_tail = 0;
 231         rxq->nb_rx_hold = 0;
 232
 233         if (rxq->pkt_first_seg != NULL)
 234                 rte_pktmbuf_free(rxq->pkt_first_seg);
 235
 236         rxq->pkt_first_seg = NULL;
 237         rxq->pkt_last_seg = NULL;
 238         rxq->rxrearm_nb = 0;
 239         rxq->rxrearm_start = 0;
 240 }
 241
 242 static inline void
 243 reset_tx_queue(struct iavf_tx_queue *txq)
 244 {
 245         struct iavf_tx_entry *txe;
 246         uint32_t i, size;
 247         uint16_t prev;
 248
 249         if (!txq) {
 250                 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
 251                 return;
 252         }
 253
 254         txe = txq->sw_ring;
 255         size = sizeof(struct iavf_tx_desc) * txq->nb_tx_desc;
 256         for (i = 0; i < size; i++)
 257                 ((volatile char *)txq->tx_ring)[i] = 0;
 258
 259         prev = (uint16_t)(txq->nb_tx_desc - 1);
 260         for (i = 0; i < txq->nb_tx_desc; i++) {
 261                 txq->tx_ring[i].cmd_type_offset_bsz =
 262                         rte_cpu_to_le_64(IAVF_TX_DESC_DTYPE_DESC_DONE);
 263                 txe[i].mbuf =  NULL;
 264                 txe[i].last_id = i;
 265                 txe[prev].next_id = i;
 266                 prev = i;
 267         }
 268
 269         txq->tx_tail = 0;
 270         txq->nb_used = 0;
 271
 272         txq->last_desc_cleaned = txq->nb_tx_desc - 1;
 273         txq->nb_free = txq->nb_tx_desc - 1;
 274
 275         txq->next_dd = txq->rs_thresh - 1;
 276         txq->next_rs = txq->rs_thresh - 1;
 277 }
 278
 279 static int
 280 alloc_rxq_mbufs(struct iavf_rx_queue *rxq)
 281 {
 282         volatile union iavf_rx_desc *rxd;
 283         struct rte_mbuf *mbuf = NULL;
 284         uint64_t dma_addr;
 285         uint16_t i, j;
 286
 287         for (i = 0; i < rxq->nb_rx_desc; i++) {
 288                 mbuf = rte_mbuf_raw_alloc(rxq->mp);
 289                 if (unlikely(!mbuf)) {
 290                         for (j = 0; j < i; j++) {
 291                                 rte_pktmbuf_free_seg(rxq->sw_ring[j]);
 292                                 rxq->sw_ring[j] = NULL;
 293                         }
 294                         PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
 295                         return -ENOMEM;
 296                 }
 297
 298                 rte_mbuf_refcnt_set(mbuf, 1);
 299                 mbuf->next = NULL;
 300                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
 301                 mbuf->nb_segs = 1;
 302                 mbuf->port = rxq->port_id;
 303
 304                 dma_addr =
 305                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
 306
 307                 rxd = &rxq->rx_ring[i];
 308                 rxd->read.pkt_addr = dma_addr;
 309                 rxd->read.hdr_addr = 0;
 310 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
 311                 rxd->read.rsvd1 = 0;
 312                 rxd->read.rsvd2 = 0;
 313 #endif
 314
 315                 rxq->sw_ring[i] = mbuf;
 316         }
 317
 318         return 0;
 319 }
 320
 321 static inline void
 322 release_rxq_mbufs(struct iavf_rx_queue *rxq)
 323 {
 324         uint16_t i;
 325
 326         if (!rxq->sw_ring)
 327                 return;
 328
 329         for (i = 0; i < rxq->nb_rx_desc; i++) {
 330                 if (rxq->sw_ring[i]) {
 331                         rte_pktmbuf_free_seg(rxq->sw_ring[i]);
 332                         rxq->sw_ring[i] = NULL;
 333                 }
 334         }
 335
 336         /* for rx bulk */
 337         if (rxq->rx_nb_avail == 0)
 338                 return;
 339         for (i = 0; i < rxq->rx_nb_avail; i++) {
 340                 struct rte_mbuf *mbuf;
 341
 342                 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
 343                 rte_pktmbuf_free_seg(mbuf);
 344         }
 345         rxq->rx_nb_avail = 0;
 346 }
 347
 348 static inline void
 349 release_txq_mbufs(struct iavf_tx_queue *txq)
 350 {
 351         uint16_t i;
 352
 353         if (!txq || !txq->sw_ring) {
 354                 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
 355                 return;
 356         }
 357
 358         for (i = 0; i < txq->nb_tx_desc; i++) {
 359                 if (txq->sw_ring[i].mbuf) {
 360                         rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
 361                         txq->sw_ring[i].mbuf = NULL;
 362                 }
 363         }
 364 }
 365
 366 static const struct iavf_rxq_ops def_rxq_ops = {
 367         .release_mbufs = release_rxq_mbufs,
 368 };
 369
 370 static const struct iavf_txq_ops def_txq_ops = {
 371         .release_mbufs = release_txq_mbufs,
 372 };
 373
 374 static inline void
 375 iavf_rxd_to_pkt_fields_by_comms_ovs(__rte_unused struct iavf_rx_queue *rxq,
 376                                     struct rte_mbuf *mb,
 377                                     volatile union iavf_rx_flex_desc *rxdp)
 378 {
 379         volatile struct iavf_32b_rx_flex_desc_comms_ovs *desc =
 380                         (volatile struct iavf_32b_rx_flex_desc_comms_ovs *)rxdp;
 381 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
 382         uint16_t stat_err;
 383 #endif
 384
 385         if (desc->flow_id != 0xFFFFFFFF) {
 386                 mb->ol_flags |= RTE_MBUF_F_RX_FDIR | RTE_MBUF_F_RX_FDIR_ID;
 387                 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
 388         }
 389
 390 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
 391         stat_err = rte_le_to_cpu_16(desc->status_error0);
 392         if (likely(stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
 393                 mb->ol_flags |= RTE_MBUF_F_RX_RSS_HASH;
 394                 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
 395         }
 396 #endif
 397 }
 398
 399 static inline void
 400 iavf_rxd_to_pkt_fields_by_comms_aux_v1(struct iavf_rx_queue *rxq,
 401                                        struct rte_mbuf *mb,
 402                                        volatile union iavf_rx_flex_desc *rxdp)
 403 {
 404         volatile struct iavf_32b_rx_flex_desc_comms *desc =
 405                         (volatile struct iavf_32b_rx_flex_desc_comms *)rxdp;
 406         uint16_t stat_err;
 407
 408         stat_err = rte_le_to_cpu_16(desc->status_error0);
 409         if (likely(stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
 410                 mb->ol_flags |= RTE_MBUF_F_RX_RSS_HASH;
 411                 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
 412         }
 413
 414 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
 415         if (desc->flow_id != 0xFFFFFFFF) {
 416                 mb->ol_flags |= RTE_MBUF_F_RX_FDIR | RTE_MBUF_F_RX_FDIR_ID;
 417                 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
 418         }
 419
 420         if (rxq->xtr_ol_flag) {
 421                 uint32_t metadata = 0;
 422
 423                 stat_err = rte_le_to_cpu_16(desc->status_error1);
 424
 425                 if (stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS1_XTRMD4_VALID_S))
 426                         metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux0);
 427
 428                 if (stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS1_XTRMD5_VALID_S))
 429                         metadata |=
 430                                 rte_le_to_cpu_16(desc->flex_ts.flex.aux1) << 16;
 431
 432                 if (metadata) {
 433                         mb->ol_flags |= rxq->xtr_ol_flag;
 434
 435                         *RTE_PMD_IFD_DYNF_PROTO_XTR_METADATA(mb) = metadata;
 436                 }
 437         }
 438 #endif
 439 }
 440
 441 static inline void
 442 iavf_rxd_to_pkt_fields_by_comms_aux_v2(struct iavf_rx_queue *rxq,
 443                                        struct rte_mbuf *mb,
 444                                        volatile union iavf_rx_flex_desc *rxdp)
 445 {
 446         volatile struct iavf_32b_rx_flex_desc_comms *desc =
 447                         (volatile struct iavf_32b_rx_flex_desc_comms *)rxdp;
 448         uint16_t stat_err;
 449
 450         stat_err = rte_le_to_cpu_16(desc->status_error0);
 451         if (likely(stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
 452                 mb->ol_flags |= RTE_MBUF_F_RX_RSS_HASH;
 453                 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
 454         }
 455
 456 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
 457         if (desc->flow_id != 0xFFFFFFFF) {
 458                 mb->ol_flags |= RTE_MBUF_F_RX_FDIR | RTE_MBUF_F_RX_FDIR_ID;
 459                 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
 460         }
 461
 462         if (rxq->xtr_ol_flag) {
 463                 uint32_t metadata = 0;
 464
 465                 if (desc->flex_ts.flex.aux0 != 0xFFFF)
 466                         metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux0);
 467                 else if (desc->flex_ts.flex.aux1 != 0xFFFF)
 468                         metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux1);
 469
 470                 if (metadata) {
 471                         mb->ol_flags |= rxq->xtr_ol_flag;
 472
 473                         *RTE_PMD_IFD_DYNF_PROTO_XTR_METADATA(mb) = metadata;
 474                 }
 475         }
 476 #endif
 477 }
 478
 479 static void
 480 iavf_select_rxd_to_pkt_fields_handler(struct iavf_rx_queue *rxq, uint32_t rxdid)
 481 {
 482         switch (rxdid) {
 483         case IAVF_RXDID_COMMS_AUX_VLAN:
 484                 rxq->xtr_ol_flag = rte_pmd_ifd_dynflag_proto_xtr_vlan_mask;
 485                 rxq->rxd_to_pkt_fields =
 486                         iavf_rxd_to_pkt_fields_by_comms_aux_v1;
 487                 break;
 488         case IAVF_RXDID_COMMS_AUX_IPV4:
 489                 rxq->xtr_ol_flag = rte_pmd_ifd_dynflag_proto_xtr_ipv4_mask;
 490                 rxq->rxd_to_pkt_fields =
 491                         iavf_rxd_to_pkt_fields_by_comms_aux_v1;
 492                 break;
 493         case IAVF_RXDID_COMMS_AUX_IPV6:
 494                 rxq->xtr_ol_flag = rte_pmd_ifd_dynflag_proto_xtr_ipv6_mask;
 495                 rxq->rxd_to_pkt_fields =
 496                         iavf_rxd_to_pkt_fields_by_comms_aux_v1;
 497                 break;
 498         case IAVF_RXDID_COMMS_AUX_IPV6_FLOW:
 499                 rxq->xtr_ol_flag =
 500                         rte_pmd_ifd_dynflag_proto_xtr_ipv6_flow_mask;
 501                 rxq->rxd_to_pkt_fields =
 502                         iavf_rxd_to_pkt_fields_by_comms_aux_v1;
 503                 break;
 504         case IAVF_RXDID_COMMS_AUX_TCP:
 505                 rxq->xtr_ol_flag = rte_pmd_ifd_dynflag_proto_xtr_tcp_mask;
 506                 rxq->rxd_to_pkt_fields =
 507                         iavf_rxd_to_pkt_fields_by_comms_aux_v1;
 508                 break;
 509         case IAVF_RXDID_COMMS_AUX_IP_OFFSET:
 510                 rxq->xtr_ol_flag =
 511                         rte_pmd_ifd_dynflag_proto_xtr_ip_offset_mask;
 512                 rxq->rxd_to_pkt_fields =
 513                         iavf_rxd_to_pkt_fields_by_comms_aux_v2;
 514                 break;
 515         case IAVF_RXDID_COMMS_IPSEC_CRYPTO:
 516                 rxq->xtr_ol_flag =
 517                         rte_pmd_ifd_dynflag_proto_xtr_ipsec_crypto_said_mask;
 518                 rxq->rxd_to_pkt_fields =
 519                         iavf_rxd_to_pkt_fields_by_comms_aux_v2;
 520                 break;
 521         case IAVF_RXDID_COMMS_OVS_1:
 522                 rxq->rxd_to_pkt_fields = iavf_rxd_to_pkt_fields_by_comms_ovs;
 523                 break;
 524         default:
 525                 /* update this according to the RXDID for FLEX_DESC_NONE */
 526                 rxq->rxd_to_pkt_fields = iavf_rxd_to_pkt_fields_by_comms_ovs;
 527                 break;
 528         }
 529
 530         if (!rte_pmd_ifd_dynf_proto_xtr_metadata_avail())
 531                 rxq->xtr_ol_flag = 0;
 532 }
 533
 534 int
 535 iavf_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 536                        uint16_t nb_desc, unsigned int socket_id,
 537                        const struct rte_eth_rxconf *rx_conf,
 538                        struct rte_mempool *mp)
 539 {
 540         struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 541         struct iavf_adapter *ad =
 542                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 543         struct iavf_info *vf =
 544                 IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 545         struct iavf_vsi *vsi = &vf->vsi;
 546         struct iavf_rx_queue *rxq;
 547         const struct rte_memzone *mz;
 548         uint32_t ring_size;
 549         uint8_t proto_xtr;
 550         uint16_t len;
 551         uint16_t rx_free_thresh;
 552         uint64_t offloads;
 553
 554         PMD_INIT_FUNC_TRACE();
 555
 556         offloads = rx_conf->offloads | dev->data->dev_conf.rxmode.offloads;
 557
 558         if (nb_desc % IAVF_ALIGN_RING_DESC != 0 ||
 559             nb_desc > IAVF_MAX_RING_DESC ||
 560             nb_desc < IAVF_MIN_RING_DESC) {
 561                 PMD_INIT_LOG(ERR, "Number (%u) of receive descriptors is "
 562                              "invalid", nb_desc);
 563                 return -EINVAL;
 564         }
 565
 566         /* Check free threshold */
 567         rx_free_thresh = (rx_conf->rx_free_thresh == 0) ?
 568                          IAVF_DEFAULT_RX_FREE_THRESH :
 569                          rx_conf->rx_free_thresh;
 570         if (check_rx_thresh(nb_desc, rx_free_thresh) != 0)
 571                 return -EINVAL;
 572
 573         /* Free memory if needed */
 574         if (dev->data->rx_queues[queue_idx]) {
 575                 iavf_dev_rx_queue_release(dev, queue_idx);
 576                 dev->data->rx_queues[queue_idx] = NULL;
 577         }
 578
 579         /* Allocate the rx queue data structure */
 580         rxq = rte_zmalloc_socket("iavf rxq",
 581                                  sizeof(struct iavf_rx_queue),
 582                                  RTE_CACHE_LINE_SIZE,
 583                                  socket_id);
 584         if (!rxq) {
 585                 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
 586                              "rx queue data structure");
 587                 return -ENOMEM;
 588         }
 589
 590         if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC) {
 591                 proto_xtr = vf->proto_xtr ? vf->proto_xtr[queue_idx] :
 592                                 IAVF_PROTO_XTR_NONE;
 593                 rxq->rxdid = iavf_proto_xtr_type_to_rxdid(proto_xtr);
 594                 rxq->proto_xtr = proto_xtr;
 595         } else {
 596                 rxq->rxdid = IAVF_RXDID_LEGACY_1;
 597                 rxq->proto_xtr = IAVF_PROTO_XTR_NONE;
 598         }
 599
 600         if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_VLAN_V2) {
 601                 struct virtchnl_vlan_supported_caps *stripping_support =
 602                                 &vf->vlan_v2_caps.offloads.stripping_support;
 603                 uint32_t stripping_cap;
 604
 605                 if (stripping_support->outer)
 606                         stripping_cap = stripping_support->outer;
 607                 else
 608                         stripping_cap = stripping_support->inner;
 609
 610                 if (stripping_cap & VIRTCHNL_VLAN_TAG_LOCATION_L2TAG1)
 611                         rxq->rx_flags = IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG1;
 612                 else if (stripping_cap & VIRTCHNL_VLAN_TAG_LOCATION_L2TAG2_2)
 613                         rxq->rx_flags = IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG2_2;
 614         } else {
 615                 rxq->rx_flags = IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG1;
 616         }
 617
 618         iavf_select_rxd_to_pkt_fields_handler(rxq, rxq->rxdid);
 619
 620         rxq->mp = mp;
 621         rxq->nb_rx_desc = nb_desc;
 622         rxq->rx_free_thresh = rx_free_thresh;
 623         rxq->queue_id = queue_idx;
 624         rxq->port_id = dev->data->port_id;
 625         rxq->rx_deferred_start = rx_conf->rx_deferred_start;
 626         rxq->rx_hdr_len = 0;
 627         rxq->vsi = vsi;
 628         rxq->offloads = offloads;
 629
 630         if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_KEEP_CRC)
 631                 rxq->crc_len = RTE_ETHER_CRC_LEN;
 632         else
 633                 rxq->crc_len = 0;
 634
 635         len = rte_pktmbuf_data_room_size(rxq->mp) - RTE_PKTMBUF_HEADROOM;
 636         rxq->rx_buf_len = RTE_ALIGN_FLOOR(len, (1 << IAVF_RXQ_CTX_DBUFF_SHIFT));
 637
 638         /* Allocate the software ring. */
 639         len = nb_desc + IAVF_RX_MAX_BURST;
 640         rxq->sw_ring =
 641                 rte_zmalloc_socket("iavf rx sw ring",
 642                                    sizeof(struct rte_mbuf *) * len,
 643                                    RTE_CACHE_LINE_SIZE,
 644                                    socket_id);
 645         if (!rxq->sw_ring) {
 646                 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW ring");
 647                 rte_free(rxq);
 648                 return -ENOMEM;
 649         }
 650
 651         /* Allocate the maximun number of RX ring hardware descriptor with
 652          * a liitle more to support bulk allocate.
 653          */
 654         len = IAVF_MAX_RING_DESC + IAVF_RX_MAX_BURST;
 655         ring_size = RTE_ALIGN(len * sizeof(union iavf_rx_desc),
 656                               IAVF_DMA_MEM_ALIGN);
 657         mz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
 658                                       ring_size, IAVF_RING_BASE_ALIGN,
 659                                       socket_id);
 660         if (!mz) {
 661                 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for RX");
 662                 rte_free(rxq->sw_ring);
 663                 rte_free(rxq);
 664                 return -ENOMEM;
 665         }
 666         /* Zero all the descriptors in the ring. */
 667         memset(mz->addr, 0, ring_size);
 668         rxq->rx_ring_phys_addr = mz->iova;
 669         rxq->rx_ring = (union iavf_rx_desc *)mz->addr;
 670
 671         rxq->mz = mz;
 672         reset_rx_queue(rxq);
 673         rxq->q_set = true;
 674         dev->data->rx_queues[queue_idx] = rxq;
 675         rxq->qrx_tail = hw->hw_addr + IAVF_QRX_TAIL1(rxq->queue_id);
 676         rxq->ops = &def_rxq_ops;
 677
 678         if (check_rx_bulk_allow(rxq) == true) {
 679                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
 680                              "satisfied. Rx Burst Bulk Alloc function will be "
 681                              "used on port=%d, queue=%d.",
 682                              rxq->port_id, rxq->queue_id);
 683         } else {
 684                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
 685                              "not satisfied, Scattered Rx is requested "
 686                              "on port=%d, queue=%d.",
 687                              rxq->port_id, rxq->queue_id);
 688                 ad->rx_bulk_alloc_allowed = false;
 689         }
 690
 691         if (check_rx_vec_allow(rxq) == false)
 692                 ad->rx_vec_allowed = false;
 693
 694         return 0;
 695 }
 696
 697 int
 698 iavf_dev_tx_queue_setup(struct rte_eth_dev *dev,
 699                        uint16_t queue_idx,
 700                        uint16_t nb_desc,
 701                        unsigned int socket_id,
 702                        const struct rte_eth_txconf *tx_conf)
 703 {
 704         struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 705         struct iavf_adapter *adapter =
 706                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 707         struct iavf_info *vf =
 708                 IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 709         struct iavf_tx_queue *txq;
 710         const struct rte_memzone *mz;
 711         uint32_t ring_size;
 712         uint16_t tx_rs_thresh, tx_free_thresh;
 713         uint64_t offloads;
 714
 715         PMD_INIT_FUNC_TRACE();
 716
 717         offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
 718
 719         if (nb_desc % IAVF_ALIGN_RING_DESC != 0 ||
 720             nb_desc > IAVF_MAX_RING_DESC ||
 721             nb_desc < IAVF_MIN_RING_DESC) {
 722                 PMD_INIT_LOG(ERR, "Number (%u) of transmit descriptors is "
 723                             "invalid", nb_desc);
 724                 return -EINVAL;
 725         }
 726
 727         tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
 728                 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
 729         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
 730                 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
 731         if (check_tx_thresh(nb_desc, tx_rs_thresh, tx_free_thresh) != 0)
 732                 return -EINVAL;
 733
 734         /* Free memory if needed. */
 735         if (dev->data->tx_queues[queue_idx]) {
 736                 iavf_dev_tx_queue_release(dev, queue_idx);
 737                 dev->data->tx_queues[queue_idx] = NULL;
 738         }
 739
 740         /* Allocate the TX queue data structure. */
 741         txq = rte_zmalloc_socket("iavf txq",
 742                                  sizeof(struct iavf_tx_queue),
 743                                  RTE_CACHE_LINE_SIZE,
 744                                  socket_id);
 745         if (!txq) {
 746                 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
 747                              "tx queue structure");
 748                 return -ENOMEM;
 749         }
 750
 751         if (adapter->vf.vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_VLAN_V2) {
 752                 struct virtchnl_vlan_supported_caps *insertion_support =
 753                         &adapter->vf.vlan_v2_caps.offloads.insertion_support;
 754                 uint32_t insertion_cap;
 755
 756                 if (insertion_support->outer)
 757                         insertion_cap = insertion_support->outer;
 758                 else
 759                         insertion_cap = insertion_support->inner;
 760
 761                 if (insertion_cap & VIRTCHNL_VLAN_TAG_LOCATION_L2TAG1)
 762                         txq->vlan_flag = IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG1;
 763                 else if (insertion_cap & VIRTCHNL_VLAN_TAG_LOCATION_L2TAG2)
 764                         txq->vlan_flag = IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG2;
 765         } else {
 766                 txq->vlan_flag = IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG1;
 767         }
 768
 769         txq->nb_tx_desc = nb_desc;
 770         txq->rs_thresh = tx_rs_thresh;
 771         txq->free_thresh = tx_free_thresh;
 772         txq->queue_id = queue_idx;
 773         txq->port_id = dev->data->port_id;
 774         txq->offloads = offloads;
 775         txq->tx_deferred_start = tx_conf->tx_deferred_start;
 776
 777         if (iavf_ipsec_crypto_supported(adapter))
 778                 txq->ipsec_crypto_pkt_md_offset =
 779                         iavf_security_get_pkt_md_offset(adapter);
 780
 781         /* Allocate software ring */
 782         txq->sw_ring =
 783                 rte_zmalloc_socket("iavf tx sw ring",
 784                                    sizeof(struct iavf_tx_entry) * nb_desc,
 785                                    RTE_CACHE_LINE_SIZE,
 786                                    socket_id);
 787         if (!txq->sw_ring) {
 788                 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW TX ring");
 789                 rte_free(txq);
 790                 return -ENOMEM;
 791         }
 792
 793         /* Allocate TX hardware ring descriptors. */
 794         ring_size = sizeof(struct iavf_tx_desc) * IAVF_MAX_RING_DESC;
 795         ring_size = RTE_ALIGN(ring_size, IAVF_DMA_MEM_ALIGN);
 796         mz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
 797                                       ring_size, IAVF_RING_BASE_ALIGN,
 798                                       socket_id);
 799         if (!mz) {
 800                 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for TX");
 801                 rte_free(txq->sw_ring);
 802                 rte_free(txq);
 803                 return -ENOMEM;
 804         }
 805         txq->tx_ring_phys_addr = mz->iova;
 806         txq->tx_ring = (struct iavf_tx_desc *)mz->addr;
 807
 808         txq->mz = mz;
 809         reset_tx_queue(txq);
 810         txq->q_set = true;
 811         dev->data->tx_queues[queue_idx] = txq;
 812         txq->qtx_tail = hw->hw_addr + IAVF_QTX_TAIL1(queue_idx);
 813         txq->ops = &def_txq_ops;
 814
 815         if (check_tx_vec_allow(txq) == false) {
 816                 struct iavf_adapter *ad =
 817                         IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 818                 ad->tx_vec_allowed = false;
 819         }
 820
 821         if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_QOS &&
 822             vf->tm_conf.committed) {
 823                 int tc;
 824                 for (tc = 0; tc < vf->qos_cap->num_elem; tc++) {
 825                         if (txq->queue_id >= vf->qtc_map[tc].start_queue_id &&
 826                             txq->queue_id < (vf->qtc_map[tc].start_queue_id +
 827                             vf->qtc_map[tc].queue_count))
 828                                 break;
 829                 }
 830                 if (tc >= vf->qos_cap->num_elem) {
 831                         PMD_INIT_LOG(ERR, "Queue TC mapping is not correct");
 832                         return -EINVAL;
 833                 }
 834                 txq->tc = tc;
 835         }
 836
 837         return 0;
 838 }
 839
 840 int
 841 iavf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 842 {
 843         struct iavf_adapter *adapter =
 844                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 845         struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 846         struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 847         struct iavf_rx_queue *rxq;
 848         int err = 0;
 849
 850         PMD_DRV_FUNC_TRACE();
 851
 852         if (rx_queue_id >= dev->data->nb_rx_queues)
 853                 return -EINVAL;
 854
 855         rxq = dev->data->rx_queues[rx_queue_id];
 856
 857         err = alloc_rxq_mbufs(rxq);
 858         if (err) {
 859                 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
 860                 return err;
 861         }
 862
 863         rte_wmb();
 864
 865         /* Init the RX tail register. */
 866         IAVF_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 867         IAVF_WRITE_FLUSH(hw);
 868
 869         /* Ready to switch the queue on */
 870         if (!vf->lv_enabled)
 871                 err = iavf_switch_queue(adapter, rx_queue_id, true, true);
 872         else
 873                 err = iavf_switch_queue_lv(adapter, rx_queue_id, true, true);
 874
 875         if (err) {
 876                 release_rxq_mbufs(rxq);
 877                 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
 878                             rx_queue_id);
 879         } else {
 880                 dev->data->rx_queue_state[rx_queue_id] =
 881                         RTE_ETH_QUEUE_STATE_STARTED;
 882         }
 883
 884         return err;
 885 }
 886
 887 int
 888 iavf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 889 {
 890         struct iavf_adapter *adapter =
 891                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 892         struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 893         struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 894         struct iavf_tx_queue *txq;
 895         int err = 0;
 896
 897         PMD_DRV_FUNC_TRACE();
 898
 899         if (tx_queue_id >= dev->data->nb_tx_queues)
 900                 return -EINVAL;
 901
 902         txq = dev->data->tx_queues[tx_queue_id];
 903
 904         /* Init the RX tail register. */
 905         IAVF_PCI_REG_WRITE(txq->qtx_tail, 0);
 906         IAVF_WRITE_FLUSH(hw);
 907
 908         /* Ready to switch the queue on */
 909         if (!vf->lv_enabled)
 910                 err = iavf_switch_queue(adapter, tx_queue_id, false, true);
 911         else
 912                 err = iavf_switch_queue_lv(adapter, tx_queue_id, false, true);
 913
 914         if (err)
 915                 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
 916                             tx_queue_id);
 917         else
 918                 dev->data->tx_queue_state[tx_queue_id] =
 919                         RTE_ETH_QUEUE_STATE_STARTED;
 920
 921         return err;
 922 }
 923
 924 int
 925 iavf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 926 {
 927         struct iavf_adapter *adapter =
 928                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 929         struct iavf_rx_queue *rxq;
 930         int err;
 931
 932         PMD_DRV_FUNC_TRACE();
 933
 934         if (rx_queue_id >= dev->data->nb_rx_queues)
 935                 return -EINVAL;
 936
 937         err = iavf_switch_queue(adapter, rx_queue_id, true, false);
 938         if (err) {
 939                 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
 940                             rx_queue_id);
 941                 return err;
 942         }
 943
 944         rxq = dev->data->rx_queues[rx_queue_id];
 945         rxq->ops->release_mbufs(rxq);
 946         reset_rx_queue(rxq);
 947         dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 948
 949         return 0;
 950 }
 951
 952 int
 953 iavf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 954 {
 955         struct iavf_adapter *adapter =
 956                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 957         struct iavf_tx_queue *txq;
 958         int err;
 959
 960         PMD_DRV_FUNC_TRACE();
 961
 962         if (tx_queue_id >= dev->data->nb_tx_queues)
 963                 return -EINVAL;
 964
 965         err = iavf_switch_queue(adapter, tx_queue_id, false, false);
 966         if (err) {
 967                 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u off",
 968                             tx_queue_id);
 969                 return err;
 970         }
 971
 972         txq = dev->data->tx_queues[tx_queue_id];
 973         txq->ops->release_mbufs(txq);
 974         reset_tx_queue(txq);
 975         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 976
 977         return 0;
 978 }
 979
 980 void
 981 iavf_dev_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
 982 {
 983         struct iavf_rx_queue *q = dev->data->rx_queues[qid];
 984
 985         if (!q)
 986                 return;
 987
 988         q->ops->release_mbufs(q);
 989         rte_free(q->sw_ring);
 990         rte_memzone_free(q->mz);
 991         rte_free(q);
 992 }
 993
 994 void
 995 iavf_dev_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
 996 {
 997         struct iavf_tx_queue *q = dev->data->tx_queues[qid];
 998
 999         if (!q)
1000                 return;
1001
1002         q->ops->release_mbufs(q);
1003         rte_free(q->sw_ring);
1004         rte_memzone_free(q->mz);
1005         rte_free(q);
1006 }
1007
1008 void
1009 iavf_stop_queues(struct rte_eth_dev *dev)
1010 {
1011         struct iavf_adapter *adapter =
1012                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1013         struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1014         struct iavf_rx_queue *rxq;
1015         struct iavf_tx_queue *txq;
1016         int ret, i;
1017
1018         /* Stop All queues */
1019         if (!vf->lv_enabled) {
1020                 ret = iavf_disable_queues(adapter);
1021                 if (ret)
1022                         PMD_DRV_LOG(WARNING, "Fail to stop queues");
1023         } else {
1024                 ret = iavf_disable_queues_lv(adapter);
1025                 if (ret)
1026                         PMD_DRV_LOG(WARNING, "Fail to stop queues for large VF");
1027         }
1028
1029         if (ret)
1030                 PMD_DRV_LOG(WARNING, "Fail to stop queues");
1031
1032         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1033                 txq = dev->data->tx_queues[i];
1034                 if (!txq)
1035                         continue;
1036                 txq->ops->release_mbufs(txq);
1037                 reset_tx_queue(txq);
1038                 dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED;
1039         }
1040         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1041                 rxq = dev->data->rx_queues[i];
1042                 if (!rxq)
1043                         continue;
1044                 rxq->ops->release_mbufs(rxq);
1045                 reset_rx_queue(rxq);
1046                 dev->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED;
1047         }
1048 }
1049
1050 #define IAVF_RX_FLEX_ERR0_BITS  \
1051         ((1 << IAVF_RX_FLEX_DESC_STATUS0_HBO_S) |       \
1052          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_IPE_S) |  \
1053          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_L4E_S) |  \
1054          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S) | \
1055          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S) |        \
1056          (1 << IAVF_RX_FLEX_DESC_STATUS0_RXE_S))
1057
1058 static inline void
1059 iavf_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union iavf_rx_desc *rxdp)
1060 {
1061         if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1062                 (1 << IAVF_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
1063                 mb->ol_flags |= RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED;
1064                 mb->vlan_tci =
1065                         rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
1066         } else {
1067                 mb->vlan_tci = 0;
1068         }
1069 }
1070
1071 static inline void
1072 iavf_flex_rxd_to_vlan_tci(struct rte_mbuf *mb,
1073                           volatile union iavf_rx_flex_desc *rxdp)
1074 {
1075         if (rte_le_to_cpu_64(rxdp->wb.status_error0) &
1076                 (1 << IAVF_RX_FLEX_DESC_STATUS0_L2TAG1P_S)) {
1077                 mb->ol_flags |= RTE_MBUF_F_RX_VLAN |
1078                                 RTE_MBUF_F_RX_VLAN_STRIPPED;
1079                 mb->vlan_tci =
1080                         rte_le_to_cpu_16(rxdp->wb.l2tag1);
1081         } else {
1082                 mb->vlan_tci = 0;
1083         }
1084
1085 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
1086         if (rte_le_to_cpu_16(rxdp->wb.status_error1) &
1087             (1 << IAVF_RX_FLEX_DESC_STATUS1_L2TAG2P_S)) {
1088                 mb->ol_flags |= RTE_MBUF_F_RX_QINQ_STRIPPED |
1089                                 RTE_MBUF_F_RX_QINQ |
1090                                 RTE_MBUF_F_RX_VLAN_STRIPPED |
1091                                 RTE_MBUF_F_RX_VLAN;
1092                 mb->vlan_tci_outer = mb->vlan_tci;
1093                 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.l2tag2_2nd);
1094                 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
1095                            rte_le_to_cpu_16(rxdp->wb.l2tag2_1st),
1096                            rte_le_to_cpu_16(rxdp->wb.l2tag2_2nd));
1097         } else {
1098                 mb->vlan_tci_outer = 0;
1099         }
1100 #endif
1101 }
1102
1103 static inline void
1104 iavf_flex_rxd_to_ipsec_crypto_said_get(struct rte_mbuf *mb,
1105                           volatile union iavf_rx_flex_desc *rxdp)
1106 {
1107         volatile struct iavf_32b_rx_flex_desc_comms_ipsec *desc =
1108                 (volatile struct iavf_32b_rx_flex_desc_comms_ipsec *)rxdp;
1109
1110         mb->dynfield1[0] = desc->ipsec_said &
1111                          IAVF_RX_FLEX_DESC_IPSEC_CRYPTO_SAID_MASK;
1112         }
1113
1114 static inline void
1115 iavf_flex_rxd_to_ipsec_crypto_status(struct rte_mbuf *mb,
1116                           volatile union iavf_rx_flex_desc *rxdp,
1117                           struct iavf_ipsec_crypto_stats *stats)
1118 {
1119         uint16_t status1 = rte_le_to_cpu_64(rxdp->wb.status_error1);
1120
1121         if (status1 & BIT(IAVF_RX_FLEX_DESC_STATUS1_IPSEC_CRYPTO_PROCESSED)) {
1122                 uint16_t ipsec_status;
1123
1124                 mb->ol_flags |= RTE_MBUF_F_RX_SEC_OFFLOAD;
1125
1126                 ipsec_status = status1 &
1127                         IAVF_RX_FLEX_DESC_IPSEC_CRYPTO_STATUS_MASK;
1128
1129
1130                 if (unlikely(ipsec_status !=
1131                         IAVF_IPSEC_CRYPTO_STATUS_SUCCESS)) {
1132                         mb->ol_flags |= RTE_MBUF_F_RX_SEC_OFFLOAD_FAILED;
1133
1134                         switch (ipsec_status) {
1135                         case IAVF_IPSEC_CRYPTO_STATUS_SAD_MISS:
1136                                 stats->ierrors.sad_miss++;
1137                                 break;
1138                         case IAVF_IPSEC_CRYPTO_STATUS_NOT_PROCESSED:
1139                                 stats->ierrors.not_processed++;
1140                                 break;
1141                         case IAVF_IPSEC_CRYPTO_STATUS_ICV_CHECK_FAIL:
1142                                 stats->ierrors.icv_check++;
1143                                 break;
1144                         case IAVF_IPSEC_CRYPTO_STATUS_LENGTH_ERR:
1145                                 stats->ierrors.ipsec_length++;
1146                                 break;
1147                         case IAVF_IPSEC_CRYPTO_STATUS_MISC_ERR:
1148                                 stats->ierrors.misc++;
1149                                 break;
1150 }
1151
1152                         stats->ierrors.count++;
1153                         return;
1154                 }
1155
1156                 stats->icount++;
1157                 stats->ibytes += rxdp->wb.pkt_len & 0x3FFF;
1158
1159                 if (rxdp->wb.rxdid == IAVF_RXDID_COMMS_IPSEC_CRYPTO &&
1160                         ipsec_status !=
1161                                 IAVF_IPSEC_CRYPTO_STATUS_SAD_MISS)
1162                         iavf_flex_rxd_to_ipsec_crypto_said_get(mb, rxdp);
1163         }
1164 }
1165
1166
1167 /* Translate the rx descriptor status and error fields to pkt flags */
1168 static inline uint64_t
1169 iavf_rxd_to_pkt_flags(uint64_t qword)
1170 {
1171         uint64_t flags;
1172         uint64_t error_bits = (qword >> IAVF_RXD_QW1_ERROR_SHIFT);
1173
1174 #define IAVF_RX_ERR_BITS 0x3f
1175
1176         /* Check if RSS_HASH */
1177         flags = (((qword >> IAVF_RX_DESC_STATUS_FLTSTAT_SHIFT) &
1178                                         IAVF_RX_DESC_FLTSTAT_RSS_HASH) ==
1179                         IAVF_RX_DESC_FLTSTAT_RSS_HASH) ? RTE_MBUF_F_RX_RSS_HASH : 0;
1180
1181         /* Check if FDIR Match */
1182         flags |= (qword & (1 << IAVF_RX_DESC_STATUS_FLM_SHIFT) ?
1183                                 RTE_MBUF_F_RX_FDIR : 0);
1184
1185         if (likely((error_bits & IAVF_RX_ERR_BITS) == 0)) {
1186                 flags |= (RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_GOOD);
1187                 return flags;
1188         }
1189
1190         if (unlikely(error_bits & (1 << IAVF_RX_DESC_ERROR_IPE_SHIFT)))
1191                 flags |= RTE_MBUF_F_RX_IP_CKSUM_BAD;
1192         else
1193                 flags |= RTE_MBUF_F_RX_IP_CKSUM_GOOD;
1194
1195         if (unlikely(error_bits & (1 << IAVF_RX_DESC_ERROR_L4E_SHIFT)))
1196                 flags |= RTE_MBUF_F_RX_L4_CKSUM_BAD;
1197         else
1198                 flags |= RTE_MBUF_F_RX_L4_CKSUM_GOOD;
1199
1200         /* TODO: Oversize error bit is not processed here */
1201
1202         return flags;
1203 }
1204
1205 static inline uint64_t
1206 iavf_rxd_build_fdir(volatile union iavf_rx_desc *rxdp, struct rte_mbuf *mb)
1207 {
1208         uint64_t flags = 0;
1209 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
1210         uint16_t flexbh;
1211
1212         flexbh = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
1213                 IAVF_RX_DESC_EXT_STATUS_FLEXBH_SHIFT) &
1214                 IAVF_RX_DESC_EXT_STATUS_FLEXBH_MASK;
1215
1216         if (flexbh == IAVF_RX_DESC_EXT_STATUS_FLEXBH_FD_ID) {
1217                 mb->hash.fdir.hi =
1218                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.fd_id);
1219                 flags |= RTE_MBUF_F_RX_FDIR_ID;
1220         }
1221 #else
1222         mb->hash.fdir.hi =
1223                 rte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.fd_id);
1224         flags |= RTE_MBUF_F_RX_FDIR_ID;
1225 #endif
1226         return flags;
1227 }
1228
1229 #define IAVF_RX_FLEX_ERR0_BITS  \
1230         ((1 << IAVF_RX_FLEX_DESC_STATUS0_HBO_S) |       \
1231          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_IPE_S) |  \
1232          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_L4E_S) |  \
1233          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S) | \
1234          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S) |        \
1235          (1 << IAVF_RX_FLEX_DESC_STATUS0_RXE_S))
1236
1237 /* Rx L3/L4 checksum */
1238 static inline uint64_t
1239 iavf_flex_rxd_error_to_pkt_flags(uint16_t stat_err0)
1240 {
1241         uint64_t flags = 0;
1242
1243         /* check if HW has decoded the packet and checksum */
1244         if (unlikely(!(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_L3L4P_S))))
1245                 return 0;
1246
1247         if (likely(!(stat_err0 & IAVF_RX_FLEX_ERR0_BITS))) {
1248                 flags |= (RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_GOOD);
1249                 return flags;
1250         }
1251
1252         if (unlikely(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_IPE_S)))
1253                 flags |= RTE_MBUF_F_RX_IP_CKSUM_BAD;
1254         else
1255                 flags |= RTE_MBUF_F_RX_IP_CKSUM_GOOD;
1256
1257         if (unlikely(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_L4E_S)))
1258                 flags |= RTE_MBUF_F_RX_L4_CKSUM_BAD;
1259         else
1260                 flags |= RTE_MBUF_F_RX_L4_CKSUM_GOOD;
1261
1262         if (unlikely(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S)))
1263                 flags |= RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD;
1264
1265         return flags;
1266 }
1267
1268 /* If the number of free RX descriptors is greater than the RX free
1269  * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1270  * register. Update the RDT with the value of the last processed RX
1271  * descriptor minus 1, to guarantee that the RDT register is never
1272  * equal to the RDH register, which creates a "full" ring situation
1273  * from the hardware point of view.
1274  */
1275 static inline void
1276 iavf_update_rx_tail(struct iavf_rx_queue *rxq, uint16_t nb_hold, uint16_t rx_id)
1277 {
1278         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1279
1280         if (nb_hold > rxq->rx_free_thresh) {
1281                 PMD_RX_LOG(DEBUG,
1282                            "port_id=%u queue_id=%u rx_tail=%u nb_hold=%u",
1283                            rxq->port_id, rxq->queue_id, rx_id, nb_hold);
1284                 rx_id = (uint16_t)((rx_id == 0) ?
1285                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
1286                 IAVF_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
1287                 nb_hold = 0;
1288         }
1289         rxq->nb_rx_hold = nb_hold;
1290 }
1291
1292 /* implement recv_pkts */
1293 uint16_t
1294 iavf_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1295 {
1296         volatile union iavf_rx_desc *rx_ring;
1297         volatile union iavf_rx_desc *rxdp;
1298         struct iavf_rx_queue *rxq;
1299         union iavf_rx_desc rxd;
1300         struct rte_mbuf *rxe;
1301         struct rte_eth_dev *dev;
1302         struct rte_mbuf *rxm;
1303         struct rte_mbuf *nmb;
1304         uint16_t nb_rx;
1305         uint32_t rx_status;
1306         uint64_t qword1;
1307         uint16_t rx_packet_len;
1308         uint16_t rx_id, nb_hold;
1309         uint64_t dma_addr;
1310         uint64_t pkt_flags;
1311         const uint32_t *ptype_tbl;
1312
1313         nb_rx = 0;
1314         nb_hold = 0;
1315         rxq = rx_queue;
1316         rx_id = rxq->rx_tail;
1317         rx_ring = rxq->rx_ring;
1318         ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1319
1320         while (nb_rx < nb_pkts) {
1321                 rxdp = &rx_ring[rx_id];
1322                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1323                 rx_status = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
1324                             IAVF_RXD_QW1_STATUS_SHIFT;
1325
1326                 /* Check the DD bit first */
1327                 if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)))
1328                         break;
1329                 IAVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
1330
1331                 nmb = rte_mbuf_raw_alloc(rxq->mp);
1332                 if (unlikely(!nmb)) {
1333                         dev = &rte_eth_devices[rxq->port_id];
1334                         dev->data->rx_mbuf_alloc_failed++;
1335                         PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1336                                    "queue_id=%u", rxq->port_id, rxq->queue_id);
1337                         break;
1338                 }
1339
1340                 rxd = *rxdp;
1341                 nb_hold++;
1342                 rxe = rxq->sw_ring[rx_id];
1343                 rxq->sw_ring[rx_id] = nmb;
1344                 rx_id++;
1345                 if (unlikely(rx_id == rxq->nb_rx_desc))
1346                         rx_id = 0;
1347
1348                 /* Prefetch next mbuf */
1349                 rte_prefetch0(rxq->sw_ring[rx_id]);
1350
1351                 /* When next RX descriptor is on a cache line boundary,
1352                  * prefetch the next 4 RX descriptors and next 8 pointers
1353                  * to mbufs.
1354                  */
1355                 if ((rx_id & 0x3) == 0) {
1356                         rte_prefetch0(&rx_ring[rx_id]);
1357                         rte_prefetch0(rxq->sw_ring[rx_id]);
1358                 }
1359                 rxm = rxe;
1360                 dma_addr =
1361                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1362                 rxdp->read.hdr_addr = 0;
1363                 rxdp->read.pkt_addr = dma_addr;
1364
1365                 rx_packet_len = ((qword1 & IAVF_RXD_QW1_LENGTH_PBUF_MASK) >>
1366                                 IAVF_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
1367
1368                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1369                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
1370                 rxm->nb_segs = 1;
1371                 rxm->next = NULL;
1372                 rxm->pkt_len = rx_packet_len;
1373                 rxm->data_len = rx_packet_len;
1374                 rxm->port = rxq->port_id;
1375                 rxm->ol_flags = 0;
1376                 iavf_rxd_to_vlan_tci(rxm, &rxd);
1377                 pkt_flags = iavf_rxd_to_pkt_flags(qword1);
1378                 rxm->packet_type =
1379                         ptype_tbl[(uint8_t)((qword1 &
1380                         IAVF_RXD_QW1_PTYPE_MASK) >> IAVF_RXD_QW1_PTYPE_SHIFT)];
1381
1382                 if (pkt_flags & RTE_MBUF_F_RX_RSS_HASH)
1383                         rxm->hash.rss =
1384                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1385
1386                 if (pkt_flags & RTE_MBUF_F_RX_FDIR)
1387                         pkt_flags |= iavf_rxd_build_fdir(&rxd, rxm);
1388
1389                 rxm->ol_flags |= pkt_flags;
1390
1391                 rx_pkts[nb_rx++] = rxm;
1392         }
1393         rxq->rx_tail = rx_id;
1394
1395         iavf_update_rx_tail(rxq, nb_hold, rx_id);
1396
1397         return nb_rx;
1398 }
1399
1400 /* implement recv_pkts for flexible Rx descriptor */
1401 uint16_t
1402 iavf_recv_pkts_flex_rxd(void *rx_queue,
1403                         struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1404 {
1405         volatile union iavf_rx_desc *rx_ring;
1406         volatile union iavf_rx_flex_desc *rxdp;
1407         struct iavf_rx_queue *rxq;
1408         union iavf_rx_flex_desc rxd;
1409         struct rte_mbuf *rxe;
1410         struct rte_eth_dev *dev;
1411         struct rte_mbuf *rxm;
1412         struct rte_mbuf *nmb;
1413         uint16_t nb_rx;
1414         uint16_t rx_stat_err0;
1415         uint16_t rx_packet_len;
1416         uint16_t rx_id, nb_hold;
1417         uint64_t dma_addr;
1418         uint64_t pkt_flags;
1419         const uint32_t *ptype_tbl;
1420
1421         nb_rx = 0;
1422         nb_hold = 0;
1423         rxq = rx_queue;
1424         rx_id = rxq->rx_tail;
1425         rx_ring = rxq->rx_ring;
1426         ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1427
1428         while (nb_rx < nb_pkts) {
1429                 rxdp = (volatile union iavf_rx_flex_desc *)&rx_ring[rx_id];
1430                 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1431
1432                 /* Check the DD bit first */
1433                 if (!(rx_stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S)))
1434                         break;
1435                 IAVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
1436
1437                 nmb = rte_mbuf_raw_alloc(rxq->mp);
1438                 if (unlikely(!nmb)) {
1439                         dev = &rte_eth_devices[rxq->port_id];
1440                         dev->data->rx_mbuf_alloc_failed++;
1441                         PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1442                                    "queue_id=%u", rxq->port_id, rxq->queue_id);
1443                         break;
1444                 }
1445
1446                 rxd = *rxdp;
1447                 nb_hold++;
1448                 rxe = rxq->sw_ring[rx_id];
1449                 rxq->sw_ring[rx_id] = nmb;
1450                 rx_id++;
1451                 if (unlikely(rx_id == rxq->nb_rx_desc))
1452                         rx_id = 0;
1453
1454                 /* Prefetch next mbuf */
1455                 rte_prefetch0(rxq->sw_ring[rx_id]);
1456
1457                 /* When next RX descriptor is on a cache line boundary,
1458                  * prefetch the next 4 RX descriptors and next 8 pointers
1459                  * to mbufs.
1460                  */
1461                 if ((rx_id & 0x3) == 0) {
1462                         rte_prefetch0(&rx_ring[rx_id]);
1463                         rte_prefetch0(rxq->sw_ring[rx_id]);
1464                 }
1465                 rxm = rxe;
1466                 dma_addr =
1467                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1468                 rxdp->read.hdr_addr = 0;
1469                 rxdp->read.pkt_addr = dma_addr;
1470
1471                 rx_packet_len = (rte_le_to_cpu_16(rxd.wb.pkt_len) &
1472                                 IAVF_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
1473
1474                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1475                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
1476                 rxm->nb_segs = 1;
1477                 rxm->next = NULL;
1478                 rxm->pkt_len = rx_packet_len;
1479                 rxm->data_len = rx_packet_len;
1480                 rxm->port = rxq->port_id;
1481                 rxm->ol_flags = 0;
1482                 rxm->packet_type = ptype_tbl[IAVF_RX_FLEX_DESC_PTYPE_M &
1483                         rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
1484                 iavf_flex_rxd_to_vlan_tci(rxm, &rxd);
1485                 iavf_flex_rxd_to_ipsec_crypto_status(rxm, &rxd,
1486                                 &rxq->stats.ipsec_crypto);
1487                 rxq->rxd_to_pkt_fields(rxq, rxm, &rxd);
1488                 pkt_flags = iavf_flex_rxd_error_to_pkt_flags(rx_stat_err0);
1489                 rxm->ol_flags |= pkt_flags;
1490
1491                 rx_pkts[nb_rx++] = rxm;
1492         }
1493         rxq->rx_tail = rx_id;
1494
1495         iavf_update_rx_tail(rxq, nb_hold, rx_id);
1496
1497         return nb_rx;
1498 }
1499
1500 /* implement recv_scattered_pkts for flexible Rx descriptor */
1501 uint16_t
1502 iavf_recv_scattered_pkts_flex_rxd(void *rx_queue, struct rte_mbuf **rx_pkts,
1503                                   uint16_t nb_pkts)
1504 {
1505         struct iavf_rx_queue *rxq = rx_queue;
1506         union iavf_rx_flex_desc rxd;
1507         struct rte_mbuf *rxe;
1508         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1509         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1510         struct rte_mbuf *nmb, *rxm;
1511         uint16_t rx_id = rxq->rx_tail;
1512         uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
1513         struct rte_eth_dev *dev;
1514         uint16_t rx_stat_err0;
1515         uint64_t dma_addr;
1516         uint64_t pkt_flags;
1517
1518         volatile union iavf_rx_desc *rx_ring = rxq->rx_ring;
1519         volatile union iavf_rx_flex_desc *rxdp;
1520         const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1521
1522         while (nb_rx < nb_pkts) {
1523                 rxdp = (volatile union iavf_rx_flex_desc *)&rx_ring[rx_id];
1524                 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1525
1526                 /* Check the DD bit */
1527                 if (!(rx_stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S)))
1528                         break;
1529                 IAVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
1530
1531                 nmb = rte_mbuf_raw_alloc(rxq->mp);
1532                 if (unlikely(!nmb)) {
1533                         PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1534                                    "queue_id=%u", rxq->port_id, rxq->queue_id);
1535                         dev = &rte_eth_devices[rxq->port_id];
1536                         dev->data->rx_mbuf_alloc_failed++;
1537                         break;
1538                 }
1539
1540                 rxd = *rxdp;
1541                 nb_hold++;
1542                 rxe = rxq->sw_ring[rx_id];
1543                 rxq->sw_ring[rx_id] = nmb;
1544                 rx_id++;
1545                 if (rx_id == rxq->nb_rx_desc)
1546                         rx_id = 0;
1547
1548                 /* Prefetch next mbuf */
1549                 rte_prefetch0(rxq->sw_ring[rx_id]);
1550
1551                 /* When next RX descriptor is on a cache line boundary,
1552                  * prefetch the next 4 RX descriptors and next 8 pointers
1553                  * to mbufs.
1554                  */
1555                 if ((rx_id & 0x3) == 0) {
1556                         rte_prefetch0(&rx_ring[rx_id]);
1557                         rte_prefetch0(rxq->sw_ring[rx_id]);
1558                 }
1559
1560                 rxm = rxe;
1561                 dma_addr =
1562                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1563
1564                 /* Set data buffer address and data length of the mbuf */
1565                 rxdp->read.hdr_addr = 0;
1566                 rxdp->read.pkt_addr = dma_addr;
1567                 rx_packet_len = rte_le_to_cpu_16(rxd.wb.pkt_len) &
1568                                 IAVF_RX_FLX_DESC_PKT_LEN_M;
1569                 rxm->data_len = rx_packet_len;
1570                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1571
1572                 /* If this is the first buffer of the received packet, set the
1573                  * pointer to the first mbuf of the packet and initialize its
1574                  * context. Otherwise, update the total length and the number
1575                  * of segments of the current scattered packet, and update the
1576                  * pointer to the last mbuf of the current packet.
1577                  */
1578                 if (!first_seg) {
1579                         first_seg = rxm;
1580                         first_seg->nb_segs = 1;
1581                         first_seg->pkt_len = rx_packet_len;
1582                 } else {
1583                         first_seg->pkt_len =
1584                                 (uint16_t)(first_seg->pkt_len +
1585                                                 rx_packet_len);
1586                         first_seg->nb_segs++;
1587                         last_seg->next = rxm;
1588                 }
1589
1590                 /* If this is not the last buffer of the received packet,
1591                  * update the pointer to the last mbuf of the current scattered
1592                  * packet and continue to parse the RX ring.
1593                  */
1594                 if (!(rx_stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_EOF_S))) {
1595                         last_seg = rxm;
1596                         continue;
1597                 }
1598
1599                 /* This is the last buffer of the received packet. If the CRC
1600                  * is not stripped by the hardware:
1601                  *  - Subtract the CRC length from the total packet length.
1602                  *  - If the last buffer only contains the whole CRC or a part
1603                  *  of it, free the mbuf associated to the last buffer. If part
1604                  *  of the CRC is also contained in the previous mbuf, subtract
1605                  *  the length of that CRC part from the data length of the
1606                  *  previous mbuf.
1607                  */
1608                 rxm->next = NULL;
1609                 if (unlikely(rxq->crc_len > 0)) {
1610                         first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
1611                         if (rx_packet_len <= RTE_ETHER_CRC_LEN) {
1612                                 rte_pktmbuf_free_seg(rxm);
1613                                 first_seg->nb_segs--;
1614                                 last_seg->data_len =
1615                                         (uint16_t)(last_seg->data_len -
1616                                         (RTE_ETHER_CRC_LEN - rx_packet_len));
1617                                 last_seg->next = NULL;
1618                         } else {
1619                                 rxm->data_len = (uint16_t)(rx_packet_len -
1620                                                         RTE_ETHER_CRC_LEN);
1621                         }
1622                 }
1623
1624                 first_seg->port = rxq->port_id;
1625                 first_seg->ol_flags = 0;
1626                 first_seg->packet_type = ptype_tbl[IAVF_RX_FLEX_DESC_PTYPE_M &
1627                         rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
1628                 iavf_flex_rxd_to_vlan_tci(first_seg, &rxd);
1629                 iavf_flex_rxd_to_ipsec_crypto_status(first_seg, &rxd,
1630                                 &rxq->stats.ipsec_crypto);
1631                 rxq->rxd_to_pkt_fields(rxq, first_seg, &rxd);
1632                 pkt_flags = iavf_flex_rxd_error_to_pkt_flags(rx_stat_err0);
1633
1634                 first_seg->ol_flags |= pkt_flags;
1635
1636                 /* Prefetch data of first segment, if configured to do so. */
1637                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1638                                           first_seg->data_off));
1639                 rx_pkts[nb_rx++] = first_seg;
1640                 first_seg = NULL;
1641         }
1642
1643         /* Record index of the next RX descriptor to probe. */
1644         rxq->rx_tail = rx_id;
1645         rxq->pkt_first_seg = first_seg;
1646         rxq->pkt_last_seg = last_seg;
1647
1648         iavf_update_rx_tail(rxq, nb_hold, rx_id);
1649
1650         return nb_rx;
1651 }
1652
1653 /* implement recv_scattered_pkts  */
1654 uint16_t
1655 iavf_recv_scattered_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1656                         uint16_t nb_pkts)
1657 {
1658         struct iavf_rx_queue *rxq = rx_queue;
1659         union iavf_rx_desc rxd;
1660         struct rte_mbuf *rxe;
1661         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1662         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1663         struct rte_mbuf *nmb, *rxm;
1664         uint16_t rx_id = rxq->rx_tail;
1665         uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
1666         struct rte_eth_dev *dev;
1667         uint32_t rx_status;
1668         uint64_t qword1;
1669         uint64_t dma_addr;
1670         uint64_t pkt_flags;
1671
1672         volatile union iavf_rx_desc *rx_ring = rxq->rx_ring;
1673         volatile union iavf_rx_desc *rxdp;
1674         const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1675
1676         while (nb_rx < nb_pkts) {
1677                 rxdp = &rx_ring[rx_id];
1678                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1679                 rx_status = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
1680                             IAVF_RXD_QW1_STATUS_SHIFT;
1681
1682                 /* Check the DD bit */
1683                 if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)))
1684                         break;
1685                 IAVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
1686
1687                 nmb = rte_mbuf_raw_alloc(rxq->mp);
1688                 if (unlikely(!nmb)) {
1689                         PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1690                                    "queue_id=%u", rxq->port_id, rxq->queue_id);
1691                         dev = &rte_eth_devices[rxq->port_id];
1692                         dev->data->rx_mbuf_alloc_failed++;
1693                         break;
1694                 }
1695
1696                 rxd = *rxdp;
1697                 nb_hold++;
1698                 rxe = rxq->sw_ring[rx_id];
1699                 rxq->sw_ring[rx_id] = nmb;
1700                 rx_id++;
1701                 if (rx_id == rxq->nb_rx_desc)
1702                         rx_id = 0;
1703
1704                 /* Prefetch next mbuf */
1705                 rte_prefetch0(rxq->sw_ring[rx_id]);
1706
1707                 /* When next RX descriptor is on a cache line boundary,
1708                  * prefetch the next 4 RX descriptors and next 8 pointers
1709                  * to mbufs.
1710                  */
1711                 if ((rx_id & 0x3) == 0) {
1712                         rte_prefetch0(&rx_ring[rx_id]);
1713                         rte_prefetch0(rxq->sw_ring[rx_id]);
1714                 }
1715
1716                 rxm = rxe;
1717                 dma_addr =
1718                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1719
1720                 /* Set data buffer address and data length of the mbuf */
1721                 rxdp->read.hdr_addr = 0;
1722                 rxdp->read.pkt_addr = dma_addr;
1723                 rx_packet_len = (qword1 & IAVF_RXD_QW1_LENGTH_PBUF_MASK) >>
1724                                  IAVF_RXD_QW1_LENGTH_PBUF_SHIFT;
1725                 rxm->data_len = rx_packet_len;
1726                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1727
1728                 /* If this is the first buffer of the received packet, set the
1729                  * pointer to the first mbuf of the packet and initialize its
1730                  * context. Otherwise, update the total length and the number
1731                  * of segments of the current scattered packet, and update the
1732                  * pointer to the last mbuf of the current packet.
1733                  */
1734                 if (!first_seg) {
1735                         first_seg = rxm;
1736                         first_seg->nb_segs = 1;
1737                         first_seg->pkt_len = rx_packet_len;
1738                 } else {
1739                         first_seg->pkt_len =
1740                                 (uint16_t)(first_seg->pkt_len +
1741                                                 rx_packet_len);
1742                         first_seg->nb_segs++;
1743                         last_seg->next = rxm;
1744                 }
1745
1746                 /* If this is not the last buffer of the received packet,
1747                  * update the pointer to the last mbuf of the current scattered
1748                  * packet and continue to parse the RX ring.
1749                  */
1750                 if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_EOF_SHIFT))) {
1751                         last_seg = rxm;
1752                         continue;
1753                 }
1754
1755                 /* This is the last buffer of the received packet. If the CRC
1756                  * is not stripped by the hardware:
1757                  *  - Subtract the CRC length from the total packet length.
1758                  *  - If the last buffer only contains the whole CRC or a part
1759                  *  of it, free the mbuf associated to the last buffer. If part
1760                  *  of the CRC is also contained in the previous mbuf, subtract
1761                  *  the length of that CRC part from the data length of the
1762                  *  previous mbuf.
1763                  */
1764                 rxm->next = NULL;
1765                 if (unlikely(rxq->crc_len > 0)) {
1766                         first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
1767                         if (rx_packet_len <= RTE_ETHER_CRC_LEN) {
1768                                 rte_pktmbuf_free_seg(rxm);
1769                                 first_seg->nb_segs--;
1770                                 last_seg->data_len =
1771                                         (uint16_t)(last_seg->data_len -
1772                                         (RTE_ETHER_CRC_LEN - rx_packet_len));
1773                                 last_seg->next = NULL;
1774                         } else
1775                                 rxm->data_len = (uint16_t)(rx_packet_len -
1776                                                         RTE_ETHER_CRC_LEN);
1777                 }
1778
1779                 first_seg->port = rxq->port_id;
1780                 first_seg->ol_flags = 0;
1781                 iavf_rxd_to_vlan_tci(first_seg, &rxd);
1782                 pkt_flags = iavf_rxd_to_pkt_flags(qword1);
1783                 first_seg->packet_type =
1784                         ptype_tbl[(uint8_t)((qword1 &
1785                         IAVF_RXD_QW1_PTYPE_MASK) >> IAVF_RXD_QW1_PTYPE_SHIFT)];
1786
1787                 if (pkt_flags & RTE_MBUF_F_RX_RSS_HASH)
1788                         first_seg->hash.rss =
1789                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1790
1791                 if (pkt_flags & RTE_MBUF_F_RX_FDIR)
1792                         pkt_flags |= iavf_rxd_build_fdir(&rxd, first_seg);
1793
1794                 first_seg->ol_flags |= pkt_flags;
1795
1796                 /* Prefetch data of first segment, if configured to do so. */
1797                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1798                                           first_seg->data_off));
1799                 rx_pkts[nb_rx++] = first_seg;
1800                 first_seg = NULL;
1801         }
1802
1803         /* Record index of the next RX descriptor to probe. */
1804         rxq->rx_tail = rx_id;
1805         rxq->pkt_first_seg = first_seg;
1806         rxq->pkt_last_seg = last_seg;
1807
1808         iavf_update_rx_tail(rxq, nb_hold, rx_id);
1809
1810         return nb_rx;
1811 }
1812
1813 #define IAVF_LOOK_AHEAD 8
1814 static inline int
1815 iavf_rx_scan_hw_ring_flex_rxd(struct iavf_rx_queue *rxq)
1816 {
1817         volatile union iavf_rx_flex_desc *rxdp;
1818         struct rte_mbuf **rxep;
1819         struct rte_mbuf *mb;
1820         uint16_t stat_err0;
1821         uint16_t pkt_len;
1822         int32_t s[IAVF_LOOK_AHEAD], nb_dd;
1823         int32_t i, j, nb_rx = 0;
1824         uint64_t pkt_flags;
1825         const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1826
1827         rxdp = (volatile union iavf_rx_flex_desc *)&rxq->rx_ring[rxq->rx_tail];
1828         rxep = &rxq->sw_ring[rxq->rx_tail];
1829
1830         stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1831
1832         /* Make sure there is at least 1 packet to receive */
1833         if (!(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S)))
1834                 return 0;
1835
1836         /* Scan LOOK_AHEAD descriptors at a time to determine which
1837          * descriptors reference packets that are ready to be received.
1838          */
1839         for (i = 0; i < IAVF_RX_MAX_BURST; i += IAVF_LOOK_AHEAD,
1840              rxdp += IAVF_LOOK_AHEAD, rxep += IAVF_LOOK_AHEAD) {
1841                 /* Read desc statuses backwards to avoid race condition */
1842                 for (j = IAVF_LOOK_AHEAD - 1; j >= 0; j--)
1843                         s[j] = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1844
1845                 rte_smp_rmb();
1846
1847                 /* Compute how many status bits were set */
1848                 for (j = 0, nb_dd = 0; j < IAVF_LOOK_AHEAD; j++)
1849                         nb_dd += s[j] & (1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S);
1850
1851                 nb_rx += nb_dd;
1852
1853                 /* Translate descriptor info to mbuf parameters */
1854                 for (j = 0; j < nb_dd; j++) {
1855                         IAVF_DUMP_RX_DESC(rxq, &rxdp[j],
1856                                           rxq->rx_tail +
1857                                           i * IAVF_LOOK_AHEAD + j);
1858
1859                         mb = rxep[j];
1860                         pkt_len = (rte_le_to_cpu_16(rxdp[j].wb.pkt_len) &
1861                                 IAVF_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
1862                         mb->data_len = pkt_len;
1863                         mb->pkt_len = pkt_len;
1864                         mb->ol_flags = 0;
1865
1866                         mb->packet_type = ptype_tbl[IAVF_RX_FLEX_DESC_PTYPE_M &
1867                                 rte_le_to_cpu_16(rxdp[j].wb.ptype_flex_flags0)];
1868                         iavf_flex_rxd_to_vlan_tci(mb, &rxdp[j]);
1869                         iavf_flex_rxd_to_ipsec_crypto_status(mb, &rxdp[j],
1870                                 &rxq->stats.ipsec_crypto);
1871                         rxq->rxd_to_pkt_fields(rxq, mb, &rxdp[j]);
1872                         stat_err0 = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1873                         pkt_flags = iavf_flex_rxd_error_to_pkt_flags(stat_err0);
1874
1875                         mb->ol_flags |= pkt_flags;
1876                 }
1877
1878                 for (j = 0; j < IAVF_LOOK_AHEAD; j++)
1879                         rxq->rx_stage[i + j] = rxep[j];
1880
1881                 if (nb_dd != IAVF_LOOK_AHEAD)
1882                         break;
1883         }
1884
1885         /* Clear software ring entries */
1886         for (i = 0; i < nb_rx; i++)
1887                 rxq->sw_ring[rxq->rx_tail + i] = NULL;
1888
1889         return nb_rx;
1890 }
1891
1892 static inline int
1893 iavf_rx_scan_hw_ring(struct iavf_rx_queue *rxq)
1894 {
1895         volatile union iavf_rx_desc *rxdp;
1896         struct rte_mbuf **rxep;
1897         struct rte_mbuf *mb;
1898         uint16_t pkt_len;
1899         uint64_t qword1;
1900         uint32_t rx_status;
1901         int32_t s[IAVF_LOOK_AHEAD], nb_dd;
1902         int32_t i, j, nb_rx = 0;
1903         uint64_t pkt_flags;
1904         const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1905
1906         rxdp = &rxq->rx_ring[rxq->rx_tail];
1907         rxep = &rxq->sw_ring[rxq->rx_tail];
1908
1909         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1910         rx_status = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
1911                     IAVF_RXD_QW1_STATUS_SHIFT;
1912
1913         /* Make sure there is at least 1 packet to receive */
1914         if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)))
1915                 return 0;
1916
1917         /* Scan LOOK_AHEAD descriptors at a time to determine which
1918          * descriptors reference packets that are ready to be received.
1919          */
1920         for (i = 0; i < IAVF_RX_MAX_BURST; i += IAVF_LOOK_AHEAD,
1921              rxdp += IAVF_LOOK_AHEAD, rxep += IAVF_LOOK_AHEAD) {
1922                 /* Read desc statuses backwards to avoid race condition */
1923                 for (j = IAVF_LOOK_AHEAD - 1; j >= 0; j--) {
1924                         qword1 = rte_le_to_cpu_64(
1925                                 rxdp[j].wb.qword1.status_error_len);
1926                         s[j] = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
1927                                IAVF_RXD_QW1_STATUS_SHIFT;
1928                 }
1929
1930                 rte_smp_rmb();
1931
1932                 /* Compute how many status bits were set */
1933                 for (j = 0, nb_dd = 0; j < IAVF_LOOK_AHEAD; j++)
1934                         nb_dd += s[j] & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT);
1935
1936                 nb_rx += nb_dd;
1937
1938                 /* Translate descriptor info to mbuf parameters */
1939                 for (j = 0; j < nb_dd; j++) {
1940                         IAVF_DUMP_RX_DESC(rxq, &rxdp[j],
1941                                          rxq->rx_tail + i * IAVF_LOOK_AHEAD + j);
1942
1943                         mb = rxep[j];
1944                         qword1 = rte_le_to_cpu_64
1945                                         (rxdp[j].wb.qword1.status_error_len);
1946                         pkt_len = ((qword1 & IAVF_RXD_QW1_LENGTH_PBUF_MASK) >>
1947                                   IAVF_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
1948                         mb->data_len = pkt_len;
1949                         mb->pkt_len = pkt_len;
1950                         mb->ol_flags = 0;
1951                         iavf_rxd_to_vlan_tci(mb, &rxdp[j]);
1952                         pkt_flags = iavf_rxd_to_pkt_flags(qword1);
1953                         mb->packet_type =
1954                                 ptype_tbl[(uint8_t)((qword1 &
1955                                 IAVF_RXD_QW1_PTYPE_MASK) >>
1956                                 IAVF_RXD_QW1_PTYPE_SHIFT)];
1957
1958                         if (pkt_flags & RTE_MBUF_F_RX_RSS_HASH)
1959                                 mb->hash.rss = rte_le_to_cpu_32(
1960                                         rxdp[j].wb.qword0.hi_dword.rss);
1961
1962                         if (pkt_flags & RTE_MBUF_F_RX_FDIR)
1963                                 pkt_flags |= iavf_rxd_build_fdir(&rxdp[j], mb);
1964
1965                         mb->ol_flags |= pkt_flags;
1966                 }
1967
1968                 for (j = 0; j < IAVF_LOOK_AHEAD; j++)
1969                         rxq->rx_stage[i + j] = rxep[j];
1970
1971                 if (nb_dd != IAVF_LOOK_AHEAD)
1972                         break;
1973         }
1974
1975         /* Clear software ring entries */
1976         for (i = 0; i < nb_rx; i++)
1977                 rxq->sw_ring[rxq->rx_tail + i] = NULL;
1978
1979         return nb_rx;
1980 }
1981
1982 static inline uint16_t
1983 iavf_rx_fill_from_stage(struct iavf_rx_queue *rxq,
1984                        struct rte_mbuf **rx_pkts,
1985                        uint16_t nb_pkts)
1986 {
1987         uint16_t i;
1988         struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1989
1990         nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1991
1992         for (i = 0; i < nb_pkts; i++)
1993                 rx_pkts[i] = stage[i];
1994
1995         rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1996         rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1997
1998         return nb_pkts;
1999 }
2000
2001 static inline int
2002 iavf_rx_alloc_bufs(struct iavf_rx_queue *rxq)
2003 {
2004         volatile union iavf_rx_desc *rxdp;
2005         struct rte_mbuf **rxep;
2006         struct rte_mbuf *mb;
2007         uint16_t alloc_idx, i;
2008         uint64_t dma_addr;
2009         int diag;
2010
2011         /* Allocate buffers in bulk */
2012         alloc_idx = (uint16_t)(rxq->rx_free_trigger -
2013                                 (rxq->rx_free_thresh - 1));
2014         rxep = &rxq->sw_ring[alloc_idx];
2015         diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
2016                                     rxq->rx_free_thresh);
2017         if (unlikely(diag != 0)) {
2018                 PMD_RX_LOG(ERR, "Failed to get mbufs in bulk");
2019                 return -ENOMEM;
2020         }
2021
2022         rxdp = &rxq->rx_ring[alloc_idx];
2023         for (i = 0; i < rxq->rx_free_thresh; i++) {
2024                 if (likely(i < (rxq->rx_free_thresh - 1)))
2025                         /* Prefetch next mbuf */
2026                         rte_prefetch0(rxep[i + 1]);
2027
2028                 mb = rxep[i];
2029                 rte_mbuf_refcnt_set(mb, 1);
2030                 mb->next = NULL;
2031                 mb->data_off = RTE_PKTMBUF_HEADROOM;
2032                 mb->nb_segs = 1;
2033                 mb->port = rxq->port_id;
2034                 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mb));
2035                 rxdp[i].read.hdr_addr = 0;
2036                 rxdp[i].read.pkt_addr = dma_addr;
2037         }
2038
2039         /* Update rx tail register */
2040         rte_wmb();
2041         IAVF_PCI_REG_WC_WRITE_RELAXED(rxq->qrx_tail, rxq->rx_free_trigger);
2042
2043         rxq->rx_free_trigger =
2044                 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
2045         if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
2046                 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2047
2048         return 0;
2049 }
2050
2051 static inline uint16_t
2052 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
2053 {
2054         struct iavf_rx_queue *rxq = (struct iavf_rx_queue *)rx_queue;
2055         uint16_t nb_rx = 0;
2056
2057         if (!nb_pkts)
2058                 return 0;
2059
2060         if (rxq->rx_nb_avail)
2061                 return iavf_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
2062
2063         if (rxq->rxdid >= IAVF_RXDID_FLEX_NIC && rxq->rxdid <= IAVF_RXDID_LAST)
2064                 nb_rx = (uint16_t)iavf_rx_scan_hw_ring_flex_rxd(rxq);
2065         else
2066                 nb_rx = (uint16_t)iavf_rx_scan_hw_ring(rxq);
2067         rxq->rx_next_avail = 0;
2068         rxq->rx_nb_avail = nb_rx;
2069         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
2070
2071         if (rxq->rx_tail > rxq->rx_free_trigger) {
2072                 if (iavf_rx_alloc_bufs(rxq) != 0) {
2073                         uint16_t i, j;
2074
2075                         /* TODO: count rx_mbuf_alloc_failed here */
2076
2077                         rxq->rx_nb_avail = 0;
2078                         rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
2079                         for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
2080                                 rxq->sw_ring[j] = rxq->rx_stage[i];
2081
2082                         return 0;
2083                 }
2084         }
2085
2086         if (rxq->rx_tail >= rxq->nb_rx_desc)
2087                 rxq->rx_tail = 0;
2088
2089         PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u, nb_rx=%u",
2090                    rxq->port_id, rxq->queue_id,
2091                    rxq->rx_tail, nb_rx);
2092
2093         if (rxq->rx_nb_avail)
2094                 return iavf_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
2095
2096         return 0;
2097 }
2098
2099 static uint16_t
2100 iavf_recv_pkts_bulk_alloc(void *rx_queue,
2101                          struct rte_mbuf **rx_pkts,
2102                          uint16_t nb_pkts)
2103 {
2104         uint16_t nb_rx = 0, n, count;
2105
2106         if (unlikely(nb_pkts == 0))
2107                 return 0;
2108
2109         if (likely(nb_pkts <= IAVF_RX_MAX_BURST))
2110                 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
2111
2112         while (nb_pkts) {
2113                 n = RTE_MIN(nb_pkts, IAVF_RX_MAX_BURST);
2114                 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
2115                 nb_rx = (uint16_t)(nb_rx + count);
2116                 nb_pkts = (uint16_t)(nb_pkts - count);
2117                 if (count < n)
2118                         break;
2119         }
2120
2121         return nb_rx;
2122 }
2123
2124 static inline int
2125 iavf_xmit_cleanup(struct iavf_tx_queue *txq)
2126 {
2127         struct iavf_tx_entry *sw_ring = txq->sw_ring;
2128         uint16_t last_desc_cleaned = txq->last_desc_cleaned;
2129         uint16_t nb_tx_desc = txq->nb_tx_desc;
2130         uint16_t desc_to_clean_to;
2131         uint16_t nb_tx_to_clean;
2132
2133         volatile struct iavf_tx_desc *txd = txq->tx_ring;
2134
2135         desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->rs_thresh);
2136         if (desc_to_clean_to >= nb_tx_desc)
2137                 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
2138
2139         desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
2140         if ((txd[desc_to_clean_to].cmd_type_offset_bsz &
2141                         rte_cpu_to_le_64(IAVF_TXD_QW1_DTYPE_MASK)) !=
2142                         rte_cpu_to_le_64(IAVF_TX_DESC_DTYPE_DESC_DONE)) {
2143                 PMD_TX_LOG(DEBUG, "TX descriptor %4u is not done "
2144                            "(port=%d queue=%d)", desc_to_clean_to,
2145                            txq->port_id, txq->queue_id);
2146                 return -1;
2147         }
2148
2149         if (last_desc_cleaned > desc_to_clean_to)
2150                 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
2151                                                         desc_to_clean_to);
2152         else
2153                 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
2154                                         last_desc_cleaned);
2155
2156         txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
2157
2158         txq->last_desc_cleaned = desc_to_clean_to;
2159         txq->nb_free = (uint16_t)(txq->nb_free + nb_tx_to_clean);
2160
2161         return 0;
2162 }
2163
2164
2165
2166 static inline void
2167 iavf_fill_ctx_desc_cmd_field(volatile uint64_t *field, struct rte_mbuf *m)
2168 {
2169         uint64_t cmd = 0;
2170
2171         /* TSO enabled */
2172         if (m->ol_flags & (RTE_MBUF_F_TX_TCP_SEG | RTE_MBUF_F_TX_UDP_SEG))
2173                 cmd = IAVF_TX_CTX_DESC_TSO << IAVF_TXD_DATA_QW1_CMD_SHIFT;
2174
2175         /* Time Sync - Currently not supported */
2176
2177         /* Outer L2 TAG 2 Insertion - Currently not supported */
2178         /* Inner L2 TAG 2 Insertion - Currently not supported */
2179
2180         *field |= cmd;
2181 }
2182
2183 static inline void
2184 iavf_fill_ctx_desc_ipsec_field(volatile uint64_t *field,
2185         struct iavf_ipsec_crypto_pkt_metadata *ipsec_md)
2186 {
2187         uint64_t ipsec_field =
2188                 (uint64_t)ipsec_md->ctx_desc_ipsec_params <<
2189                         IAVF_TXD_CTX_QW1_IPSEC_PARAMS_CIPHERBLK_SHIFT;
2190
2191         *field |= ipsec_field;
2192 }
2193
2194
2195 static inline void
2196 iavf_fill_ctx_desc_tunnelling_field(volatile uint64_t *qw0,
2197                 const struct rte_mbuf *m)
2198 {
2199         uint64_t eip_typ = IAVF_TX_CTX_DESC_EIPT_NONE;
2200         uint64_t eip_len = 0;
2201         uint64_t eip_noinc = 0;
2202         /* Default - IP_ID is increment in each segment of LSO */
2203
2204         switch (m->ol_flags & (RTE_MBUF_F_TX_OUTER_IPV4 |
2205                         RTE_MBUF_F_TX_OUTER_IPV6 |
2206                         RTE_MBUF_F_TX_OUTER_IP_CKSUM)) {
2207         case RTE_MBUF_F_TX_OUTER_IPV4:
2208                 eip_typ = IAVF_TX_CTX_DESC_EIPT_IPV4_NO_CHECKSUM_OFFLOAD;
2209                 eip_len = m->outer_l3_len >> 2;
2210         break;
2211         case RTE_MBUF_F_TX_OUTER_IPV4 | RTE_MBUF_F_TX_OUTER_IP_CKSUM:
2212                 eip_typ = IAVF_TX_CTX_DESC_EIPT_IPV4_CHECKSUM_OFFLOAD;
2213                 eip_len = m->outer_l3_len >> 2;
2214         break;
2215         case RTE_MBUF_F_TX_OUTER_IPV6:
2216                 eip_typ = IAVF_TX_CTX_DESC_EIPT_IPV6;
2217                 eip_len = m->outer_l3_len >> 2;
2218         break;
2219         }
2220
2221         *qw0 = eip_typ << IAVF_TXD_CTX_QW0_TUN_PARAMS_EIPT_SHIFT |
2222                 eip_len << IAVF_TXD_CTX_QW0_TUN_PARAMS_EIPLEN_SHIFT |
2223                 eip_noinc << IAVF_TXD_CTX_QW0_TUN_PARAMS_EIP_NOINC_SHIFT;
2224 }
2225
2226 static inline uint16_t
2227 iavf_fill_ctx_desc_segmentation_field(volatile uint64_t *field,
2228         struct rte_mbuf *m, struct iavf_ipsec_crypto_pkt_metadata *ipsec_md)
2229 {
2230         uint64_t segmentation_field = 0;
2231         uint64_t total_length = 0;
2232
2233         if (m->ol_flags & RTE_MBUF_F_TX_SEC_OFFLOAD) {
2234                 total_length = ipsec_md->l4_payload_len;
2235         } else {
2236                 total_length = m->pkt_len - (m->l2_len + m->l3_len + m->l4_len);
2237
2238                 if (m->ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK)
2239                         total_length -= m->outer_l3_len;
2240         }
2241
2242 #ifdef RTE_LIBRTE_IAVF_DEBUG_TX
2243         if (!m->l4_len || !m->tso_segsz)
2244                 PMD_TX_LOG(DEBUG, "L4 length %d, LSO Segment size %d",
2245                          m->l4_len, m->tso_segsz);
2246         if (m->tso_segsz < 88)
2247                 PMD_TX_LOG(DEBUG, "LSO Segment size %d is less than minimum %d",
2248                         m->tso_segsz, 88);
2249 #endif
2250         segmentation_field =
2251                 (((uint64_t)total_length << IAVF_TXD_CTX_QW1_TSO_LEN_SHIFT) &
2252                                 IAVF_TXD_CTX_QW1_TSO_LEN_MASK) |
2253                 (((uint64_t)m->tso_segsz << IAVF_TXD_CTX_QW1_MSS_SHIFT) &
2254                                 IAVF_TXD_CTX_QW1_MSS_MASK);
2255
2256         *field |= segmentation_field;
2257
2258         return total_length;
2259 }
2260
2261
2262 struct iavf_tx_context_desc_qws {
2263         __le64 qw0;
2264         __le64 qw1;
2265 };
2266
2267 static inline void
2268 iavf_fill_context_desc(volatile struct iavf_tx_context_desc *desc,
2269         struct rte_mbuf *m, struct iavf_ipsec_crypto_pkt_metadata *ipsec_md,
2270         uint16_t *tlen)
2271 {
2272         volatile struct iavf_tx_context_desc_qws *desc_qws =
2273                         (volatile struct iavf_tx_context_desc_qws *)desc;
2274         /* fill descriptor type field */
2275         desc_qws->qw1 = IAVF_TX_DESC_DTYPE_CONTEXT;
2276
2277         /* fill command field */
2278         iavf_fill_ctx_desc_cmd_field(&desc_qws->qw1, m);
2279
2280         /* fill segmentation field */
2281         if (m->ol_flags & (RTE_MBUF_F_TX_TCP_SEG | RTE_MBUF_F_TX_UDP_SEG)) {
2282                 /* fill IPsec field */
2283                 if (m->ol_flags & RTE_MBUF_F_TX_SEC_OFFLOAD)
2284                         iavf_fill_ctx_desc_ipsec_field(&desc_qws->qw1,
2285                                 ipsec_md);
2286
2287                 *tlen = iavf_fill_ctx_desc_segmentation_field(&desc_qws->qw1,
2288                                 m, ipsec_md);
2289         }
2290
2291         /* fill tunnelling field */
2292         if (m->ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK)
2293                 iavf_fill_ctx_desc_tunnelling_field(&desc_qws->qw0, m);
2294         else
2295                 desc_qws->qw0 = 0;
2296
2297         desc_qws->qw0 = rte_cpu_to_le_64(desc_qws->qw0);
2298         desc_qws->qw1 = rte_cpu_to_le_64(desc_qws->qw1);
2299 }
2300
2301
2302 static inline void
2303 iavf_fill_ipsec_desc(volatile struct iavf_tx_ipsec_desc *desc,
2304         const struct iavf_ipsec_crypto_pkt_metadata *md, uint16_t *ipsec_len)
2305 {
2306         desc->qw0 = rte_cpu_to_le_64(((uint64_t)md->l4_payload_len <<
2307                 IAVF_IPSEC_TX_DESC_QW0_L4PAYLEN_SHIFT) |
2308                 ((uint64_t)md->esn << IAVF_IPSEC_TX_DESC_QW0_IPSECESN_SHIFT) |
2309                 ((uint64_t)md->esp_trailer_len <<
2310                                 IAVF_IPSEC_TX_DESC_QW0_TRAILERLEN_SHIFT));
2311
2312         desc->qw1 = rte_cpu_to_le_64(((uint64_t)md->sa_idx <<
2313                 IAVF_IPSEC_TX_DESC_QW1_IPSECSA_SHIFT) |
2314                 ((uint64_t)md->next_proto <<
2315                                 IAVF_IPSEC_TX_DESC_QW1_IPSECNH_SHIFT) |
2316                 ((uint64_t)(md->len_iv & 0x3) <<
2317                                 IAVF_IPSEC_TX_DESC_QW1_IVLEN_SHIFT) |
2318                 ((uint64_t)(md->ol_flags & IAVF_IPSEC_CRYPTO_OL_FLAGS_NATT ?
2319                                 1ULL : 0ULL) <<
2320                                 IAVF_IPSEC_TX_DESC_QW1_UDP_SHIFT) |
2321                 (uint64_t)IAVF_TX_DESC_DTYPE_IPSEC);
2322
2323         /**
2324          * TODO: Pre-calculate this in the Session initialization
2325          *
2326          * Calculate IPsec length required in data descriptor func when TSO
2327          * offload is enabled
2328          */
2329         *ipsec_len = sizeof(struct rte_esp_hdr) + (md->len_iv >> 2) +
2330                         (md->ol_flags & IAVF_IPSEC_CRYPTO_OL_FLAGS_NATT ?
2331                         sizeof(struct rte_udp_hdr) : 0);
2332 }
2333
2334 static inline void
2335 iavf_build_data_desc_cmd_offset_fields(volatile uint64_t *qw1,
2336                 struct rte_mbuf *m)
2337 {
2338         uint64_t command = 0;
2339         uint64_t offset = 0;
2340         uint64_t l2tag1 = 0;
2341
2342         *qw1 = IAVF_TX_DESC_DTYPE_DATA;
2343
2344         command = (uint64_t)IAVF_TX_DESC_CMD_ICRC;
2345
2346         /* Descriptor based VLAN insertion */
2347         if (m->ol_flags & RTE_MBUF_F_TX_VLAN) {
2348                 command |= (uint64_t)IAVF_TX_DESC_CMD_IL2TAG1;
2349                 l2tag1 |= m->vlan_tci;
2350         }
2351
2352         /* Set MACLEN */
2353         offset |= (m->l2_len >> 1) << IAVF_TX_DESC_LENGTH_MACLEN_SHIFT;
2354
2355         /* Enable L3 checksum offloading inner */
2356         if (m->ol_flags & (RTE_MBUF_F_TX_IP_CKSUM | RTE_MBUF_F_TX_IPV4)) {
2357                 command |= IAVF_TX_DESC_CMD_IIPT_IPV4_CSUM;
2358                 offset |= (m->l3_len >> 2) << IAVF_TX_DESC_LENGTH_IPLEN_SHIFT;
2359         } else if (m->ol_flags & RTE_MBUF_F_TX_IPV4) {
2360                 command |= IAVF_TX_DESC_CMD_IIPT_IPV4;
2361                 offset |= (m->l3_len >> 2) << IAVF_TX_DESC_LENGTH_IPLEN_SHIFT;
2362         } else if (m->ol_flags & RTE_MBUF_F_TX_IPV6) {
2363                 command |= IAVF_TX_DESC_CMD_IIPT_IPV6;
2364                 offset |= (m->l3_len >> 2) << IAVF_TX_DESC_LENGTH_IPLEN_SHIFT;
2365         }
2366
2367         if (m->ol_flags & RTE_MBUF_F_TX_TCP_SEG) {
2368                 command |= IAVF_TX_DESC_CMD_L4T_EOFT_TCP;
2369                 offset |= (m->l4_len >> 2) <<
2370                               IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2371         }
2372
2373         /* Enable L4 checksum offloads */
2374         switch (m->ol_flags & RTE_MBUF_F_TX_L4_MASK) {
2375         case RTE_MBUF_F_TX_TCP_CKSUM:
2376                 command |= IAVF_TX_DESC_CMD_L4T_EOFT_TCP;
2377                 offset |= (sizeof(struct rte_tcp_hdr) >> 2) <<
2378                                 IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2379                 break;
2380         case RTE_MBUF_F_TX_SCTP_CKSUM:
2381                 command |= IAVF_TX_DESC_CMD_L4T_EOFT_SCTP;
2382                 offset |= (sizeof(struct rte_sctp_hdr) >> 2) <<
2383                                 IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2384                 break;
2385         case RTE_MBUF_F_TX_UDP_CKSUM:
2386                 command |= IAVF_TX_DESC_CMD_L4T_EOFT_UDP;
2387                 offset |= (sizeof(struct rte_udp_hdr) >> 2) <<
2388                                 IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2389                 break;
2390         }
2391
2392         *qw1 = rte_cpu_to_le_64((((uint64_t)command <<
2393                 IAVF_TXD_DATA_QW1_CMD_SHIFT) & IAVF_TXD_DATA_QW1_CMD_MASK) |
2394                 (((uint64_t)offset << IAVF_TXD_DATA_QW1_OFFSET_SHIFT) &
2395                 IAVF_TXD_DATA_QW1_OFFSET_MASK) |
2396                 ((uint64_t)l2tag1 << IAVF_TXD_DATA_QW1_L2TAG1_SHIFT));
2397 }
2398
2399 static inline void
2400 iavf_fill_data_desc(volatile struct iavf_tx_desc *desc,
2401         struct rte_mbuf *m, uint64_t desc_template,
2402         uint16_t tlen, uint16_t ipseclen)
2403 {
2404         uint32_t hdrlen = m->l2_len;
2405         uint32_t bufsz = 0;
2406
2407         /* fill data descriptor qw1 from template */
2408         desc->cmd_type_offset_bsz = desc_template;
2409
2410         /* set data buffer address */
2411         desc->buffer_addr = rte_mbuf_data_iova(m);
2412
2413         /* calculate data buffer size less set header lengths */
2414         if ((m->ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK) &&
2415                         (m->ol_flags & (RTE_MBUF_F_TX_TCP_SEG |
2416                                         RTE_MBUF_F_TX_UDP_SEG))) {
2417                 hdrlen += m->outer_l3_len;
2418                 if (m->ol_flags & RTE_MBUF_F_TX_L4_MASK)
2419                         hdrlen += m->l3_len + m->l4_len;
2420                 else
2421                         hdrlen += m->l3_len;
2422                 if (m->ol_flags & RTE_MBUF_F_TX_SEC_OFFLOAD)
2423                         hdrlen += ipseclen;
2424                 bufsz = hdrlen + tlen;
2425         } else {
2426                 bufsz = m->data_len;
2427         }
2428
2429         /* set data buffer size */
2430         desc->cmd_type_offset_bsz |=
2431                 (((uint64_t)bufsz << IAVF_TXD_DATA_QW1_TX_BUF_SZ_SHIFT) &
2432                 IAVF_TXD_DATA_QW1_TX_BUF_SZ_MASK);
2433
2434         desc->buffer_addr = rte_cpu_to_le_64(desc->buffer_addr);
2435         desc->cmd_type_offset_bsz = rte_cpu_to_le_64(desc->cmd_type_offset_bsz);
2436 }
2437
2438
2439 static struct iavf_ipsec_crypto_pkt_metadata *
2440 iavf_ipsec_crypto_get_pkt_metadata(const struct iavf_tx_queue *txq,
2441                 struct rte_mbuf *m)
2442 {
2443         if (m->ol_flags & RTE_MBUF_F_TX_SEC_OFFLOAD)
2444                 return RTE_MBUF_DYNFIELD(m, txq->ipsec_crypto_pkt_md_offset,
2445                                 struct iavf_ipsec_crypto_pkt_metadata *);
2446
2447         return NULL;
2448 }
2449
2450 /* TX function */
2451 uint16_t
2452 iavf_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2453 {
2454         struct iavf_tx_queue *txq = tx_queue;
2455         volatile struct iavf_tx_desc *txr = txq->tx_ring;
2456         struct iavf_tx_entry *txe_ring = txq->sw_ring;
2457         struct iavf_tx_entry *txe, *txn;
2458         struct rte_mbuf *mb, *mb_seg;
2459         uint16_t desc_idx, desc_idx_last;
2460         uint16_t idx;
2461
2462
2463         /* Check if the descriptor ring needs to be cleaned. */
2464         if (txq->nb_free < txq->free_thresh)
2465                 iavf_xmit_cleanup(txq);
2466
2467         desc_idx = txq->tx_tail;
2468         txe = &txe_ring[desc_idx];
2469
2470 #ifdef RTE_LIBRTE_IAVF_DEBUG_TX_DESC_RING
2471                 iavf_dump_tx_entry_ring(txq);
2472                 iavf_dump_tx_desc_ring(txq);
2473 #endif
2474
2475
2476         for (idx = 0; idx < nb_pkts; idx++) {
2477                 volatile struct iavf_tx_desc *ddesc;
2478                 struct iavf_ipsec_crypto_pkt_metadata *ipsec_md;
2479
2480                 uint16_t nb_desc_ctx, nb_desc_ipsec;
2481                 uint16_t nb_desc_data, nb_desc_required;
2482                 uint16_t tlen = 0, ipseclen = 0;
2483                 uint64_t ddesc_template = 0;
2484                 uint64_t ddesc_cmd = 0;
2485
2486                 mb = tx_pkts[idx];
2487
2488                 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
2489
2490                 /**
2491                  * Get metadata for ipsec crypto from mbuf dynamic fields if
2492                  * security offload is specified.
2493                  */
2494                 ipsec_md = iavf_ipsec_crypto_get_pkt_metadata(txq, mb);
2495
2496                 nb_desc_data = mb->nb_segs;
2497                 nb_desc_ctx = !!(mb->ol_flags &
2498                         (RTE_MBUF_F_TX_TCP_SEG | RTE_MBUF_F_TX_UDP_SEG |
2499                                         RTE_MBUF_F_TX_TUNNEL_MASK));
2500                 nb_desc_ipsec = !!(mb->ol_flags & RTE_MBUF_F_TX_SEC_OFFLOAD);
2501
2502                 /**
2503                  * The number of descriptors that must be allocated for
2504                  * a packet equals to the number of the segments of that
2505                  * packet plus the context and ipsec descriptors if needed.
2506                  */
2507                 nb_desc_required = nb_desc_data + nb_desc_ctx + nb_desc_ipsec;
2508
2509                 desc_idx_last = (uint16_t)(desc_idx + nb_desc_required - 1);
2510
2511                 /* wrap descriptor ring */
2512                 if (desc_idx_last >= txq->nb_tx_desc)
2513                         desc_idx_last =
2514                                 (uint16_t)(desc_idx_last - txq->nb_tx_desc);
2515
2516                 PMD_TX_LOG(DEBUG,
2517                         "port_id=%u queue_id=%u tx_first=%u tx_last=%u",
2518                         txq->port_id, txq->queue_id, desc_idx, desc_idx_last);
2519
2520                 if (nb_desc_required > txq->nb_free) {
2521                         if (iavf_xmit_cleanup(txq)) {
2522                                 if (idx == 0)
2523                                         return 0;
2524                                 goto end_of_tx;
2525                         }
2526                         if (unlikely(nb_desc_required > txq->rs_thresh)) {
2527                                 while (nb_desc_required > txq->nb_free) {
2528                                         if (iavf_xmit_cleanup(txq)) {
2529                                                 if (idx == 0)
2530                                                         return 0;
2531                                                 goto end_of_tx;
2532                                         }
2533                                 }
2534                         }
2535                 }
2536
2537                 iavf_build_data_desc_cmd_offset_fields(&ddesc_template, mb);
2538
2539                         /* Setup TX context descriptor if required */
2540                 if (nb_desc_ctx) {
2541                         volatile struct iavf_tx_context_desc *ctx_desc =
2542                                 (volatile struct iavf_tx_context_desc *)
2543                                         &txr[desc_idx];
2544
2545                         /* clear QW0 or the previous writeback value
2546                          * may impact next write
2547                          */
2548                         *(volatile uint64_t *)ctx_desc = 0;
2549
2550                         txn = &txe_ring[txe->next_id];
2551                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
2552
2553                         if (txe->mbuf) {
2554                                 rte_pktmbuf_free_seg(txe->mbuf);
2555                                 txe->mbuf = NULL;
2556                         }
2557
2558                         iavf_fill_context_desc(ctx_desc, mb, ipsec_md, &tlen);
2559                         IAVF_DUMP_TX_DESC(txq, ctx_desc, desc_idx);
2560
2561                         txe->last_id = desc_idx_last;
2562                         desc_idx = txe->next_id;
2563                         txe = txn;
2564                         }
2565
2566                 if (nb_desc_ipsec) {
2567                         volatile struct iavf_tx_ipsec_desc *ipsec_desc =
2568                                 (volatile struct iavf_tx_ipsec_desc *)
2569                                         &txr[desc_idx];
2570
2571                         txn = &txe_ring[txe->next_id];
2572                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
2573
2574                         if (txe->mbuf) {
2575                                 rte_pktmbuf_free_seg(txe->mbuf);
2576                                 txe->mbuf = NULL;
2577                 }
2578
2579                         iavf_fill_ipsec_desc(ipsec_desc, ipsec_md, &ipseclen);
2580
2581                         IAVF_DUMP_TX_DESC(txq, ipsec_desc, desc_idx);
2582
2583                         txe->last_id = desc_idx_last;
2584                         desc_idx = txe->next_id;
2585                         txe = txn;
2586                 }
2587
2588                 mb_seg = mb;
2589
2590                 do {
2591                         ddesc = (volatile struct iavf_tx_desc *)
2592                                         &txr[desc_idx];
2593
2594                         txn = &txe_ring[txe->next_id];
2595                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
2596
2597                         if (txe->mbuf)
2598                                 rte_pktmbuf_free_seg(txe->mbuf);
2599
2600                         txe->mbuf = mb_seg;
2601                         iavf_fill_data_desc(ddesc, mb_seg,
2602                                         ddesc_template, tlen, ipseclen);
2603
2604                         IAVF_DUMP_TX_DESC(txq, ddesc, desc_idx);
2605
2606                         txe->last_id = desc_idx_last;
2607                         desc_idx = txe->next_id;
2608                         txe = txn;
2609                         mb_seg = mb_seg->next;
2610                 } while (mb_seg);
2611
2612                 /* The last packet data descriptor needs End Of Packet (EOP) */
2613                 ddesc_cmd = IAVF_TX_DESC_CMD_EOP;
2614
2615                 txq->nb_used = (uint16_t)(txq->nb_used + nb_desc_required);
2616                 txq->nb_free = (uint16_t)(txq->nb_free - nb_desc_required);
2617
2618                 if (txq->nb_used >= txq->rs_thresh) {
2619                         PMD_TX_LOG(DEBUG, "Setting RS bit on TXD id="
2620                                    "%4u (port=%d queue=%d)",
2621                                    desc_idx_last, txq->port_id, txq->queue_id);
2622
2623                         ddesc_cmd |= IAVF_TX_DESC_CMD_RS;
2624
2625                         /* Update txq RS bit counters */
2626                         txq->nb_used = 0;
2627                 }
2628
2629                 ddesc->cmd_type_offset_bsz |= rte_cpu_to_le_64(ddesc_cmd <<
2630                                 IAVF_TXD_DATA_QW1_CMD_SHIFT);
2631
2632                 IAVF_DUMP_TX_DESC(txq, ddesc, desc_idx - 1);
2633         }
2634
2635 end_of_tx:
2636         rte_wmb();
2637
2638         PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
2639                    txq->port_id, txq->queue_id, desc_idx, idx);
2640
2641         IAVF_PCI_REG_WRITE_RELAXED(txq->qtx_tail, desc_idx);
2642         txq->tx_tail = desc_idx;
2643
2644         return idx;
2645 }
2646
2647 /* Check if the packet with vlan user priority is transmitted in the
2648  * correct queue.
2649  */
2650 static int
2651 iavf_check_vlan_up2tc(struct iavf_tx_queue *txq, struct rte_mbuf *m)
2652 {
2653         struct rte_eth_dev *dev = &rte_eth_devices[txq->port_id];
2654         struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2655         uint16_t up;
2656
2657         up = m->vlan_tci >> IAVF_VLAN_TAG_PCP_OFFSET;
2658
2659         if (!(vf->qos_cap->cap[txq->tc].tc_prio & BIT(up))) {
2660                 PMD_TX_LOG(ERR, "packet with vlan pcp %u cannot transmit in queue %u\n",
2661                         up, txq->queue_id);
2662                 return -1;
2663         } else {
2664                 return 0;
2665         }
2666 }
2667
2668 /* TX prep functions */
2669 uint16_t
2670 iavf_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
2671               uint16_t nb_pkts)
2672 {
2673         int i, ret;
2674         uint64_t ol_flags;
2675         struct rte_mbuf *m;
2676         struct iavf_tx_queue *txq = tx_queue;
2677         struct rte_eth_dev *dev = &rte_eth_devices[txq->port_id];
2678         struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2679
2680         for (i = 0; i < nb_pkts; i++) {
2681                 m = tx_pkts[i];
2682                 ol_flags = m->ol_flags;
2683
2684                 /* Check condition for nb_segs > IAVF_TX_MAX_MTU_SEG. */
2685                 if (!(ol_flags & RTE_MBUF_F_TX_TCP_SEG)) {
2686                         if (m->nb_segs > IAVF_TX_MAX_MTU_SEG) {
2687                                 rte_errno = EINVAL;
2688                                 return i;
2689                         }
2690                 } else if ((m->tso_segsz < IAVF_MIN_TSO_MSS) ||
2691                            (m->tso_segsz > IAVF_MAX_TSO_MSS)) {
2692                         /* MSS outside the range are considered malicious */
2693                         rte_errno = EINVAL;
2694                         return i;
2695                 }
2696
2697                 if (ol_flags & IAVF_TX_OFFLOAD_NOTSUP_MASK) {
2698                         rte_errno = ENOTSUP;
2699                         return i;
2700                 }
2701
2702 #ifdef RTE_ETHDEV_DEBUG_TX
2703                 ret = rte_validate_tx_offload(m);
2704                 if (ret != 0) {
2705                         rte_errno = -ret;
2706                         return i;
2707                 }
2708 #endif
2709                 ret = rte_net_intel_cksum_prepare(m);
2710                 if (ret != 0) {
2711                         rte_errno = -ret;
2712                         return i;
2713                 }
2714
2715                 if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_QOS &&
2716                     ol_flags & (RTE_MBUF_F_RX_VLAN_STRIPPED | RTE_MBUF_F_RX_VLAN)) {
2717                         ret = iavf_check_vlan_up2tc(txq, m);
2718                         if (ret != 0) {
2719                                 rte_errno = -ret;
2720                                 return i;
2721                         }
2722                 }
2723         }
2724
2725         return i;
2726 }
2727
2728 /* choose rx function*/
2729 void
2730 iavf_set_rx_function(struct rte_eth_dev *dev)
2731 {
2732         struct iavf_adapter *adapter =
2733                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2734         struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2735
2736 #ifdef RTE_ARCH_X86
2737         struct iavf_rx_queue *rxq;
2738         int i;
2739         int check_ret;
2740         bool use_avx2 = false;
2741         bool use_avx512 = false;
2742         bool use_flex = false;
2743
2744         check_ret = iavf_rx_vec_dev_check(dev);
2745         if (check_ret >= 0 &&
2746             rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
2747                 if ((rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
2748                      rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) &&
2749                     rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256)
2750                         use_avx2 = true;
2751
2752 #ifdef CC_AVX512_SUPPORT
2753                 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 &&
2754                     rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1 &&
2755                     rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512)
2756                         use_avx512 = true;
2757 #endif
2758
2759                 if (vf->vf_res->vf_cap_flags &
2760                         VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC)
2761                         use_flex = true;
2762
2763                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2764                         rxq = dev->data->rx_queues[i];
2765                         (void)iavf_rxq_vec_setup(rxq);
2766                 }
2767
2768                 if (dev->data->scattered_rx) {
2769                         if (!use_avx512) {
2770                                 PMD_DRV_LOG(DEBUG,
2771                                             "Using %sVector Scattered Rx (port %d).",
2772                                             use_avx2 ? "avx2 " : "",
2773                                             dev->data->port_id);
2774                         } else {
2775                                 if (check_ret == IAVF_VECTOR_PATH)
2776                                         PMD_DRV_LOG(DEBUG,
2777                                                     "Using AVX512 Vector Scattered Rx (port %d).",
2778                                                     dev->data->port_id);
2779                                 else
2780                                         PMD_DRV_LOG(DEBUG,
2781                                                     "Using AVX512 OFFLOAD Vector Scattered Rx (port %d).",
2782                                                     dev->data->port_id);
2783                         }
2784                         if (use_flex) {
2785                                 dev->rx_pkt_burst = use_avx2 ?
2786                                         iavf_recv_scattered_pkts_vec_avx2_flex_rxd :
2787                                         iavf_recv_scattered_pkts_vec_flex_rxd;
2788 #ifdef CC_AVX512_SUPPORT
2789                                 if (use_avx512) {
2790                                         if (check_ret == IAVF_VECTOR_PATH)
2791                                                 dev->rx_pkt_burst =
2792                                                         iavf_recv_scattered_pkts_vec_avx512_flex_rxd;
2793                                         else
2794                                                 dev->rx_pkt_burst =
2795                                                         iavf_recv_scattered_pkts_vec_avx512_flex_rxd_offload;
2796                                 }
2797 #endif
2798                         } else {
2799                                 dev->rx_pkt_burst = use_avx2 ?
2800                                         iavf_recv_scattered_pkts_vec_avx2 :
2801                                         iavf_recv_scattered_pkts_vec;
2802 #ifdef CC_AVX512_SUPPORT
2803                                 if (use_avx512) {
2804                                         if (check_ret == IAVF_VECTOR_PATH)
2805                                                 dev->rx_pkt_burst =
2806                                                         iavf_recv_scattered_pkts_vec_avx512;
2807                                         else
2808                                                 dev->rx_pkt_burst =
2809                                                         iavf_recv_scattered_pkts_vec_avx512_offload;
2810                                 }
2811 #endif
2812                         }
2813                 } else {
2814                         if (!use_avx512) {
2815                                 PMD_DRV_LOG(DEBUG, "Using %sVector Rx (port %d).",
2816                                             use_avx2 ? "avx2 " : "",
2817                                             dev->data->port_id);
2818                         } else {
2819                                 if (check_ret == IAVF_VECTOR_PATH)
2820                                         PMD_DRV_LOG(DEBUG,
2821                                                     "Using AVX512 Vector Rx (port %d).",
2822                                                     dev->data->port_id);
2823                                 else
2824                                         PMD_DRV_LOG(DEBUG,
2825                                                     "Using AVX512 OFFLOAD Vector Rx (port %d).",
2826                                                     dev->data->port_id);
2827                         }
2828                         if (use_flex) {
2829                                 dev->rx_pkt_burst = use_avx2 ?
2830                                         iavf_recv_pkts_vec_avx2_flex_rxd :
2831                                         iavf_recv_pkts_vec_flex_rxd;
2832 #ifdef CC_AVX512_SUPPORT
2833                                 if (use_avx512) {
2834                                         if (check_ret == IAVF_VECTOR_PATH)
2835                                                 dev->rx_pkt_burst =
2836                                                         iavf_recv_pkts_vec_avx512_flex_rxd;
2837                                         else
2838                                                 dev->rx_pkt_burst =
2839                                                         iavf_recv_pkts_vec_avx512_flex_rxd_offload;
2840                                 }
2841 #endif
2842                         } else {
2843                                 dev->rx_pkt_burst = use_avx2 ?
2844                                         iavf_recv_pkts_vec_avx2 :
2845                                         iavf_recv_pkts_vec;
2846 #ifdef CC_AVX512_SUPPORT
2847                                 if (use_avx512) {
2848                                         if (check_ret == IAVF_VECTOR_PATH)
2849                                                 dev->rx_pkt_burst =
2850                                                         iavf_recv_pkts_vec_avx512;
2851                                         else
2852                                                 dev->rx_pkt_burst =
2853                                                         iavf_recv_pkts_vec_avx512_offload;
2854                                 }
2855 #endif
2856                         }
2857                 }
2858
2859                 return;
2860         }
2861
2862 #endif
2863         if (dev->data->scattered_rx) {
2864                 PMD_DRV_LOG(DEBUG, "Using a Scattered Rx callback (port=%d).",
2865                             dev->data->port_id);
2866                 if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC)
2867                         dev->rx_pkt_burst = iavf_recv_scattered_pkts_flex_rxd;
2868                 else
2869                         dev->rx_pkt_burst = iavf_recv_scattered_pkts;
2870         } else if (adapter->rx_bulk_alloc_allowed) {
2871                 PMD_DRV_LOG(DEBUG, "Using bulk Rx callback (port=%d).",
2872                             dev->data->port_id);
2873                 dev->rx_pkt_burst = iavf_recv_pkts_bulk_alloc;
2874         } else {
2875                 PMD_DRV_LOG(DEBUG, "Using Basic Rx callback (port=%d).",
2876                             dev->data->port_id);
2877                 if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC)
2878                         dev->rx_pkt_burst = iavf_recv_pkts_flex_rxd;
2879                 else
2880                         dev->rx_pkt_burst = iavf_recv_pkts;
2881         }
2882 }
2883
2884 /* choose tx function*/
2885 void
2886 iavf_set_tx_function(struct rte_eth_dev *dev)
2887 {
2888 #ifdef RTE_ARCH_X86
2889         struct iavf_tx_queue *txq;
2890         int i;
2891         int check_ret;
2892         bool use_sse = false;
2893         bool use_avx2 = false;
2894         bool use_avx512 = false;
2895
2896         check_ret = iavf_tx_vec_dev_check(dev);
2897
2898         if (check_ret >= 0 &&
2899             rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
2900                 /* SSE and AVX2 not support offload path yet. */
2901                 if (check_ret == IAVF_VECTOR_PATH) {
2902                         use_sse = true;
2903                         if ((rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
2904                              rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) &&
2905                             rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256)
2906                                 use_avx2 = true;
2907                 }
2908 #ifdef CC_AVX512_SUPPORT
2909                 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 &&
2910                     rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1 &&
2911                     rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512)
2912                         use_avx512 = true;
2913 #endif
2914
2915                 if (!use_sse && !use_avx2 && !use_avx512)
2916                         goto normal;
2917
2918                 if (!use_avx512) {
2919                         PMD_DRV_LOG(DEBUG, "Using %sVector Tx (port %d).",
2920                                     use_avx2 ? "avx2 " : "",
2921                                     dev->data->port_id);
2922                         dev->tx_pkt_burst = use_avx2 ?
2923                                             iavf_xmit_pkts_vec_avx2 :
2924                                             iavf_xmit_pkts_vec;
2925                 }
2926                 dev->tx_pkt_prepare = NULL;
2927 #ifdef CC_AVX512_SUPPORT
2928                 if (use_avx512) {
2929                         if (check_ret == IAVF_VECTOR_PATH) {
2930                                 dev->tx_pkt_burst = iavf_xmit_pkts_vec_avx512;
2931                                 PMD_DRV_LOG(DEBUG, "Using AVX512 Vector Tx (port %d).",
2932                                             dev->data->port_id);
2933                         } else {
2934                                 dev->tx_pkt_burst = iavf_xmit_pkts_vec_avx512_offload;
2935                                 dev->tx_pkt_prepare = iavf_prep_pkts;
2936                                 PMD_DRV_LOG(DEBUG, "Using AVX512 OFFLOAD Vector Tx (port %d).",
2937                                             dev->data->port_id);
2938                         }
2939                 }
2940 #endif
2941
2942                 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2943                         txq = dev->data->tx_queues[i];
2944                         if (!txq)
2945                                 continue;
2946 #ifdef CC_AVX512_SUPPORT
2947                         if (use_avx512)
2948                                 iavf_txq_vec_setup_avx512(txq);
2949                         else
2950                                 iavf_txq_vec_setup(txq);
2951 #else
2952                         iavf_txq_vec_setup(txq);
2953 #endif
2954                 }
2955
2956                 return;
2957         }
2958
2959 normal:
2960 #endif
2961         PMD_DRV_LOG(DEBUG, "Using Basic Tx callback (port=%d).",
2962                     dev->data->port_id);
2963         dev->tx_pkt_burst = iavf_xmit_pkts;
2964         dev->tx_pkt_prepare = iavf_prep_pkts;
2965 }
2966
2967 static int
2968 iavf_tx_done_cleanup_full(struct iavf_tx_queue *txq,
2969                         uint32_t free_cnt)
2970 {
2971         struct iavf_tx_entry *swr_ring = txq->sw_ring;
2972         uint16_t i, tx_last, tx_id;
2973         uint16_t nb_tx_free_last;
2974         uint16_t nb_tx_to_clean;
2975         uint32_t pkt_cnt;
2976
2977         /* Start free mbuf from the next of tx_tail */
2978         tx_last = txq->tx_tail;
2979         tx_id  = swr_ring[tx_last].next_id;
2980
2981         if (txq->nb_free == 0 && iavf_xmit_cleanup(txq))
2982                 return 0;
2983
2984         nb_tx_to_clean = txq->nb_free;
2985         nb_tx_free_last = txq->nb_free;
2986         if (!free_cnt)
2987                 free_cnt = txq->nb_tx_desc;
2988
2989         /* Loop through swr_ring to count the amount of
2990          * freeable mubfs and packets.
2991          */
2992         for (pkt_cnt = 0; pkt_cnt < free_cnt; ) {
2993                 for (i = 0; i < nb_tx_to_clean &&
2994                         pkt_cnt < free_cnt &&
2995                         tx_id != tx_last; i++) {
2996                         if (swr_ring[tx_id].mbuf != NULL) {
2997                                 rte_pktmbuf_free_seg(swr_ring[tx_id].mbuf);
2998                                 swr_ring[tx_id].mbuf = NULL;
2999
3000                                 /*
3001                                  * last segment in the packet,
3002                                  * increment packet count
3003                                  */
3004                                 pkt_cnt += (swr_ring[tx_id].last_id == tx_id);
3005                         }
3006
3007                         tx_id = swr_ring[tx_id].next_id;
3008                 }
3009
3010                 if (txq->rs_thresh > txq->nb_tx_desc -
3011                         txq->nb_free || tx_id == tx_last)
3012                         break;
3013
3014                 if (pkt_cnt < free_cnt) {
3015                         if (iavf_xmit_cleanup(txq))
3016                                 break;
3017
3018                         nb_tx_to_clean = txq->nb_free - nb_tx_free_last;
3019                         nb_tx_free_last = txq->nb_free;
3020                 }
3021         }
3022
3023         return (int)pkt_cnt;
3024 }
3025
3026 int
3027 iavf_dev_tx_done_cleanup(void *txq, uint32_t free_cnt)
3028 {
3029         struct iavf_tx_queue *q = (struct iavf_tx_queue *)txq;
3030
3031         return iavf_tx_done_cleanup_full(q, free_cnt);
3032 }
3033
3034 void
3035 iavf_dev_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
3036                      struct rte_eth_rxq_info *qinfo)
3037 {
3038         struct iavf_rx_queue *rxq;
3039
3040         rxq = dev->data->rx_queues[queue_id];
3041
3042         qinfo->mp = rxq->mp;
3043         qinfo->scattered_rx = dev->data->scattered_rx;
3044         qinfo->nb_desc = rxq->nb_rx_desc;
3045
3046         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
3047         qinfo->conf.rx_drop_en = true;
3048         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
3049 }
3050
3051 void
3052 iavf_dev_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
3053                      struct rte_eth_txq_info *qinfo)
3054 {
3055         struct iavf_tx_queue *txq;
3056
3057         txq = dev->data->tx_queues[queue_id];
3058
3059         qinfo->nb_desc = txq->nb_tx_desc;
3060
3061         qinfo->conf.tx_free_thresh = txq->free_thresh;
3062         qinfo->conf.tx_rs_thresh = txq->rs_thresh;
3063         qinfo->conf.offloads = txq->offloads;
3064         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
3065 }
3066
3067 /* Get the number of used descriptors of a rx queue */
3068 uint32_t
3069 iavf_dev_rxq_count(void *rx_queue)
3070 {
3071 #define IAVF_RXQ_SCAN_INTERVAL 4
3072         volatile union iavf_rx_desc *rxdp;
3073         struct iavf_rx_queue *rxq;
3074         uint16_t desc = 0;
3075
3076         rxq = rx_queue;
3077         rxdp = &rxq->rx_ring[rxq->rx_tail];
3078
3079         while ((desc < rxq->nb_rx_desc) &&
3080                ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
3081                  IAVF_RXD_QW1_STATUS_MASK) >> IAVF_RXD_QW1_STATUS_SHIFT) &
3082                (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)) {
3083                 /* Check the DD bit of a rx descriptor of each 4 in a group,
3084                  * to avoid checking too frequently and downgrading performance
3085                  * too much.
3086                  */
3087                 desc += IAVF_RXQ_SCAN_INTERVAL;
3088                 rxdp += IAVF_RXQ_SCAN_INTERVAL;
3089                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
3090                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
3091                                         desc - rxq->nb_rx_desc]);
3092         }
3093
3094         return desc;
3095 }
3096
3097 int
3098 iavf_dev_rx_desc_status(void *rx_queue, uint16_t offset)
3099 {
3100         struct iavf_rx_queue *rxq = rx_queue;
3101         volatile uint64_t *status;
3102         uint64_t mask;
3103         uint32_t desc;
3104
3105         if (unlikely(offset >= rxq->nb_rx_desc))
3106                 return -EINVAL;
3107
3108         if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
3109                 return RTE_ETH_RX_DESC_UNAVAIL;
3110
3111         desc = rxq->rx_tail + offset;
3112         if (desc >= rxq->nb_rx_desc)
3113                 desc -= rxq->nb_rx_desc;
3114
3115         status = &rxq->rx_ring[desc].wb.qword1.status_error_len;
3116         mask = rte_le_to_cpu_64((1ULL << IAVF_RX_DESC_STATUS_DD_SHIFT)
3117                 << IAVF_RXD_QW1_STATUS_SHIFT);
3118         if (*status & mask)
3119                 return RTE_ETH_RX_DESC_DONE;
3120
3121         return RTE_ETH_RX_DESC_AVAIL;
3122 }
3123
3124 int
3125 iavf_dev_tx_desc_status(void *tx_queue, uint16_t offset)
3126 {
3127         struct iavf_tx_queue *txq = tx_queue;
3128         volatile uint64_t *status;
3129         uint64_t mask, expect;
3130         uint32_t desc;
3131
3132         if (unlikely(offset >= txq->nb_tx_desc))
3133                 return -EINVAL;
3134
3135         desc = txq->tx_tail + offset;
3136         /* go to next desc that has the RS bit */
3137         desc = ((desc + txq->rs_thresh - 1) / txq->rs_thresh) *
3138                 txq->rs_thresh;
3139         if (desc >= txq->nb_tx_desc) {
3140                 desc -= txq->nb_tx_desc;
3141                 if (desc >= txq->nb_tx_desc)
3142                         desc -= txq->nb_tx_desc;
3143         }
3144
3145         status = &txq->tx_ring[desc].cmd_type_offset_bsz;
3146         mask = rte_le_to_cpu_64(IAVF_TXD_QW1_DTYPE_MASK);
3147         expect = rte_cpu_to_le_64(
3148                  IAVF_TX_DESC_DTYPE_DESC_DONE << IAVF_TXD_QW1_DTYPE_SHIFT);
3149         if ((*status & mask) == expect)
3150                 return RTE_ETH_TX_DESC_DONE;
3151
3152         return RTE_ETH_TX_DESC_FULL;
3153 }
3154
3155 static inline uint32_t
3156 iavf_get_default_ptype(uint16_t ptype)
3157 {
3158         static const uint32_t ptype_tbl[IAVF_MAX_PKT_TYPE]
3159                 __rte_cache_aligned = {
3160                 /* L2 types */
3161                 /* [0] reserved */
3162                 [1] = RTE_PTYPE_L2_ETHER,
3163                 [2] = RTE_PTYPE_L2_ETHER_TIMESYNC,
3164                 /* [3] - [5] reserved */
3165                 [6] = RTE_PTYPE_L2_ETHER_LLDP,
3166                 /* [7] - [10] reserved */
3167                 [11] = RTE_PTYPE_L2_ETHER_ARP,
3168                 /* [12] - [21] reserved */
3169
3170                 /* Non tunneled IPv4 */
3171                 [22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3172                        RTE_PTYPE_L4_FRAG,
3173                 [23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3174                        RTE_PTYPE_L4_NONFRAG,
3175                 [24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3176                        RTE_PTYPE_L4_UDP,
3177                 /* [25] reserved */
3178                 [26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3179                        RTE_PTYPE_L4_TCP,
3180                 [27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3181                        RTE_PTYPE_L4_SCTP,
3182                 [28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3183                        RTE_PTYPE_L4_ICMP,
3184
3185                 /* IPv4 --> IPv4 */
3186                 [29] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3187                        RTE_PTYPE_TUNNEL_IP |
3188                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3189                        RTE_PTYPE_INNER_L4_FRAG,
3190                 [30] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3191                        RTE_PTYPE_TUNNEL_IP |
3192                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3193                        RTE_PTYPE_INNER_L4_NONFRAG,
3194                 [31] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3195                        RTE_PTYPE_TUNNEL_IP |
3196                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3197                        RTE_PTYPE_INNER_L4_UDP,
3198                 /* [32] reserved */
3199                 [33] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3200                        RTE_PTYPE_TUNNEL_IP |
3201                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3202                        RTE_PTYPE_INNER_L4_TCP,
3203                 [34] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3204                        RTE_PTYPE_TUNNEL_IP |
3205                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3206                        RTE_PTYPE_INNER_L4_SCTP,
3207                 [35] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3208                        RTE_PTYPE_TUNNEL_IP |
3209                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3210                        RTE_PTYPE_INNER_L4_ICMP,
3211
3212                 /* IPv4 --> IPv6 */
3213                 [36] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3214                        RTE_PTYPE_TUNNEL_IP |
3215                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3216                        RTE_PTYPE_INNER_L4_FRAG,
3217                 [37] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3218                        RTE_PTYPE_TUNNEL_IP |
3219                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3220                        RTE_PTYPE_INNER_L4_NONFRAG,
3221                 [38] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3222                        RTE_PTYPE_TUNNEL_IP |
3223                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3224                        RTE_PTYPE_INNER_L4_UDP,
3225                 /* [39] reserved */
3226                 [40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3227                        RTE_PTYPE_TUNNEL_IP |
3228                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3229                        RTE_PTYPE_INNER_L4_TCP,
3230                 [41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3231                        RTE_PTYPE_TUNNEL_IP |
3232                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3233                        RTE_PTYPE_INNER_L4_SCTP,
3234                 [42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3235                        RTE_PTYPE_TUNNEL_IP |
3236                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3237                        RTE_PTYPE_INNER_L4_ICMP,
3238
3239                 /* IPv4 --> GRE/Teredo/VXLAN */
3240                 [43] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3241                        RTE_PTYPE_TUNNEL_GRENAT,
3242
3243                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv4 */
3244                 [44] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3245                        RTE_PTYPE_TUNNEL_GRENAT |
3246                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3247                        RTE_PTYPE_INNER_L4_FRAG,
3248                 [45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3249                        RTE_PTYPE_TUNNEL_GRENAT |
3250                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3251                        RTE_PTYPE_INNER_L4_NONFRAG,
3252                 [46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3253                        RTE_PTYPE_TUNNEL_GRENAT |
3254                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3255                        RTE_PTYPE_INNER_L4_UDP,
3256                 /* [47] reserved */
3257                 [48] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3258                        RTE_PTYPE_TUNNEL_GRENAT |
3259                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3260                        RTE_PTYPE_INNER_L4_TCP,
3261                 [49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3262                        RTE_PTYPE_TUNNEL_GRENAT |
3263                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3264                        RTE_PTYPE_INNER_L4_SCTP,
3265                 [50] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3266                        RTE_PTYPE_TUNNEL_GRENAT |
3267                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3268                        RTE_PTYPE_INNER_L4_ICMP,
3269
3270                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv6 */
3271                 [51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3272                        RTE_PTYPE_TUNNEL_GRENAT |
3273                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3274                        RTE_PTYPE_INNER_L4_FRAG,
3275                 [52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3276                        RTE_PTYPE_TUNNEL_GRENAT |
3277                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3278                        RTE_PTYPE_INNER_L4_NONFRAG,
3279                 [53] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3280                        RTE_PTYPE_TUNNEL_GRENAT |
3281                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3282                        RTE_PTYPE_INNER_L4_UDP,
3283                 /* [54] reserved */
3284                 [55] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3285                        RTE_PTYPE_TUNNEL_GRENAT |
3286                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3287                        RTE_PTYPE_INNER_L4_TCP,
3288                 [56] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3289                        RTE_PTYPE_TUNNEL_GRENAT |
3290                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3291                        RTE_PTYPE_INNER_L4_SCTP,
3292                 [57] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3293                        RTE_PTYPE_TUNNEL_GRENAT |
3294                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3295                        RTE_PTYPE_INNER_L4_ICMP,
3296
3297                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC */
3298                 [58] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3299                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
3300
3301                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
3302                 [59] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3303                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3304                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3305                        RTE_PTYPE_INNER_L4_FRAG,
3306                 [60] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3307                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3308                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3309                        RTE_PTYPE_INNER_L4_NONFRAG,
3310                 [61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3311                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3312                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3313                        RTE_PTYPE_INNER_L4_UDP,
3314                 /* [62] reserved */
3315                 [63] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3316                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3317                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3318                        RTE_PTYPE_INNER_L4_TCP,
3319                 [64] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3320                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3321                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3322                        RTE_PTYPE_INNER_L4_SCTP,
3323                 [65] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3324                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3325                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3326                        RTE_PTYPE_INNER_L4_ICMP,
3327
3328                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
3329                 [66] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3330                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3331                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3332                        RTE_PTYPE_INNER_L4_FRAG,
3333                 [67] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3334                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3335                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3336                        RTE_PTYPE_INNER_L4_NONFRAG,
3337                 [68] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3338                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3339                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3340                        RTE_PTYPE_INNER_L4_UDP,
3341                 /* [69] reserved */
3342                 [70] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3343                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3344                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3345                        RTE_PTYPE_INNER_L4_TCP,
3346                 [71] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3347                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3348                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3349                        RTE_PTYPE_INNER_L4_SCTP,
3350                 [72] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3351                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3352                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3353                        RTE_PTYPE_INNER_L4_ICMP,
3354                 /* [73] - [87] reserved */
3355
3356                 /* Non tunneled IPv6 */
3357                 [88] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3358                        RTE_PTYPE_L4_FRAG,
3359                 [89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3360                        RTE_PTYPE_L4_NONFRAG,
3361                 [90] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3362                        RTE_PTYPE_L4_UDP,
3363                 /* [91] reserved */
3364                 [92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3365                        RTE_PTYPE_L4_TCP,
3366                 [93] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3367                        RTE_PTYPE_L4_SCTP,
3368                 [94] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3369                        RTE_PTYPE_L4_ICMP,
3370
3371                 /* IPv6 --> IPv4 */
3372                 [95] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3373                        RTE_PTYPE_TUNNEL_IP |
3374                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3375                        RTE_PTYPE_INNER_L4_FRAG,
3376                 [96] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3377                        RTE_PTYPE_TUNNEL_IP |
3378                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3379                        RTE_PTYPE_INNER_L4_NONFRAG,
3380                 [97] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3381                        RTE_PTYPE_TUNNEL_IP |
3382                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3383                        RTE_PTYPE_INNER_L4_UDP,
3384                 /* [98] reserved */
3385                 [99] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3386                        RTE_PTYPE_TUNNEL_IP |
3387                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3388                        RTE_PTYPE_INNER_L4_TCP,
3389                 [100] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3390                         RTE_PTYPE_TUNNEL_IP |
3391                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3392                         RTE_PTYPE_INNER_L4_SCTP,
3393                 [101] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3394                         RTE_PTYPE_TUNNEL_IP |
3395                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3396                         RTE_PTYPE_INNER_L4_ICMP,
3397
3398                 /* IPv6 --> IPv6 */
3399                 [102] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3400                         RTE_PTYPE_TUNNEL_IP |
3401                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3402                         RTE_PTYPE_INNER_L4_FRAG,
3403                 [103] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3404                         RTE_PTYPE_TUNNEL_IP |
3405                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3406                         RTE_PTYPE_INNER_L4_NONFRAG,
3407                 [104] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3408                         RTE_PTYPE_TUNNEL_IP |
3409                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3410                         RTE_PTYPE_INNER_L4_UDP,
3411                 /* [105] reserved */
3412                 [106] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3413                         RTE_PTYPE_TUNNEL_IP |
3414                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3415                         RTE_PTYPE_INNER_L4_TCP,
3416                 [107] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3417                         RTE_PTYPE_TUNNEL_IP |
3418                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3419                         RTE_PTYPE_INNER_L4_SCTP,
3420                 [108] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3421                         RTE_PTYPE_TUNNEL_IP |
3422                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3423                         RTE_PTYPE_INNER_L4_ICMP,
3424
3425                 /* IPv6 --> GRE/Teredo/VXLAN */
3426                 [109] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3427                         RTE_PTYPE_TUNNEL_GRENAT,
3428
3429                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv4 */
3430                 [110] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3431                         RTE_PTYPE_TUNNEL_GRENAT |
3432                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3433                         RTE_PTYPE_INNER_L4_FRAG,
3434                 [111] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3435                         RTE_PTYPE_TUNNEL_GRENAT |
3436                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3437                         RTE_PTYPE_INNER_L4_NONFRAG,
3438                 [112] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3439                         RTE_PTYPE_TUNNEL_GRENAT |
3440                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3441                         RTE_PTYPE_INNER_L4_UDP,
3442                 /* [113] reserved */
3443                 [114] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3444                         RTE_PTYPE_TUNNEL_GRENAT |
3445                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3446                         RTE_PTYPE_INNER_L4_TCP,
3447                 [115] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3448                         RTE_PTYPE_TUNNEL_GRENAT |
3449                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3450                         RTE_PTYPE_INNER_L4_SCTP,
3451                 [116] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3452                         RTE_PTYPE_TUNNEL_GRENAT |
3453                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3454                         RTE_PTYPE_INNER_L4_ICMP,
3455
3456                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv6 */
3457                 [117] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3458                         RTE_PTYPE_TUNNEL_GRENAT |
3459                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3460                         RTE_PTYPE_INNER_L4_FRAG,
3461                 [118] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3462                         RTE_PTYPE_TUNNEL_GRENAT |
3463                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3464                         RTE_PTYPE_INNER_L4_NONFRAG,
3465                 [119] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3466                         RTE_PTYPE_TUNNEL_GRENAT |
3467                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3468                         RTE_PTYPE_INNER_L4_UDP,
3469                 /* [120] reserved */
3470                 [121] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3471                         RTE_PTYPE_TUNNEL_GRENAT |
3472                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3473                         RTE_PTYPE_INNER_L4_TCP,
3474                 [122] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3475                         RTE_PTYPE_TUNNEL_GRENAT |
3476                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3477                         RTE_PTYPE_INNER_L4_SCTP,
3478                 [123] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3479                         RTE_PTYPE_TUNNEL_GRENAT |
3480                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3481                         RTE_PTYPE_INNER_L4_ICMP,
3482
3483                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC */
3484                 [124] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3485                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
3486
3487                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
3488                 [125] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3489                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3490                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3491                         RTE_PTYPE_INNER_L4_FRAG,
3492                 [126] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3493                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3494                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3495                         RTE_PTYPE_INNER_L4_NONFRAG,
3496                 [127] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3497                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3498                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3499                         RTE_PTYPE_INNER_L4_UDP,
3500                 /* [128] reserved */
3501                 [129] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3502                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3503                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3504                         RTE_PTYPE_INNER_L4_TCP,
3505                 [130] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3506                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3507                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3508                         RTE_PTYPE_INNER_L4_SCTP,
3509                 [131] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3510                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3511                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3512                         RTE_PTYPE_INNER_L4_ICMP,
3513
3514                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
3515                 [132] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3516                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3517                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3518                         RTE_PTYPE_INNER_L4_FRAG,
3519                 [133] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3520                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3521                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3522                         RTE_PTYPE_INNER_L4_NONFRAG,
3523                 [134] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3524                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3525                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3526                         RTE_PTYPE_INNER_L4_UDP,
3527                 /* [135] reserved */
3528                 [136] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3529                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3530                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3531                         RTE_PTYPE_INNER_L4_TCP,
3532                 [137] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3533                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3534                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3535                         RTE_PTYPE_INNER_L4_SCTP,
3536                 [138] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3537                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3538                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3539                         RTE_PTYPE_INNER_L4_ICMP,
3540                 /* [139] - [299] reserved */
3541
3542                 /* PPPoE */
3543                 [300] = RTE_PTYPE_L2_ETHER_PPPOE,
3544                 [301] = RTE_PTYPE_L2_ETHER_PPPOE,
3545
3546                 /* PPPoE --> IPv4 */
3547                 [302] = RTE_PTYPE_L2_ETHER_PPPOE |
3548                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3549                         RTE_PTYPE_L4_FRAG,
3550                 [303] = RTE_PTYPE_L2_ETHER_PPPOE |
3551                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3552                         RTE_PTYPE_L4_NONFRAG,
3553                 [304] = RTE_PTYPE_L2_ETHER_PPPOE |
3554                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3555                         RTE_PTYPE_L4_UDP,
3556                 [305] = RTE_PTYPE_L2_ETHER_PPPOE |
3557                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3558                         RTE_PTYPE_L4_TCP,
3559                 [306] = RTE_PTYPE_L2_ETHER_PPPOE |
3560                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3561                         RTE_PTYPE_L4_SCTP,
3562                 [307] = RTE_PTYPE_L2_ETHER_PPPOE |
3563                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3564                         RTE_PTYPE_L4_ICMP,
3565
3566                 /* PPPoE --> IPv6 */
3567                 [308] = RTE_PTYPE_L2_ETHER_PPPOE |
3568                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3569                         RTE_PTYPE_L4_FRAG,
3570                 [309] = RTE_PTYPE_L2_ETHER_PPPOE |
3571                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3572                         RTE_PTYPE_L4_NONFRAG,
3573                 [310] = RTE_PTYPE_L2_ETHER_PPPOE |
3574                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3575                         RTE_PTYPE_L4_UDP,
3576                 [311] = RTE_PTYPE_L2_ETHER_PPPOE |
3577                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3578                         RTE_PTYPE_L4_TCP,
3579                 [312] = RTE_PTYPE_L2_ETHER_PPPOE |
3580                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3581                         RTE_PTYPE_L4_SCTP,
3582                 [313] = RTE_PTYPE_L2_ETHER_PPPOE |
3583                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3584                         RTE_PTYPE_L4_ICMP,
3585                 /* [314] - [324] reserved */
3586
3587                 /* IPv4/IPv6 --> GTPC/GTPU */
3588                 [325] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3589                         RTE_PTYPE_TUNNEL_GTPC,
3590                 [326] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3591                         RTE_PTYPE_TUNNEL_GTPC,
3592                 [327] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3593                         RTE_PTYPE_TUNNEL_GTPC,
3594                 [328] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3595                         RTE_PTYPE_TUNNEL_GTPC,
3596                 [329] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3597                         RTE_PTYPE_TUNNEL_GTPU,
3598                 [330] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3599                         RTE_PTYPE_TUNNEL_GTPU,
3600
3601                 /* IPv4 --> GTPU --> IPv4 */
3602                 [331] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3603                         RTE_PTYPE_TUNNEL_GTPU |
3604                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3605                         RTE_PTYPE_INNER_L4_FRAG,
3606                 [332] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3607                         RTE_PTYPE_TUNNEL_GTPU |
3608                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3609                         RTE_PTYPE_INNER_L4_NONFRAG,
3610                 [333] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3611                         RTE_PTYPE_TUNNEL_GTPU |
3612                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3613                         RTE_PTYPE_INNER_L4_UDP,
3614                 [334] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3615                         RTE_PTYPE_TUNNEL_GTPU |
3616                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3617                         RTE_PTYPE_INNER_L4_TCP,
3618                 [335] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3619                         RTE_PTYPE_TUNNEL_GTPU |
3620                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3621                         RTE_PTYPE_INNER_L4_ICMP,
3622
3623                 /* IPv6 --> GTPU --> IPv4 */
3624                 [336] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3625                         RTE_PTYPE_TUNNEL_GTPU |
3626                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3627                         RTE_PTYPE_INNER_L4_FRAG,
3628                 [337] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3629                         RTE_PTYPE_TUNNEL_GTPU |
3630                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3631                         RTE_PTYPE_INNER_L4_NONFRAG,
3632                 [338] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3633                         RTE_PTYPE_TUNNEL_GTPU |
3634                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3635                         RTE_PTYPE_INNER_L4_UDP,
3636                 [339] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3637                         RTE_PTYPE_TUNNEL_GTPU |
3638                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3639                         RTE_PTYPE_INNER_L4_TCP,
3640                 [340] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3641                         RTE_PTYPE_TUNNEL_GTPU |
3642                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3643                         RTE_PTYPE_INNER_L4_ICMP,
3644
3645                 /* IPv4 --> GTPU --> IPv6 */
3646                 [341] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3647                         RTE_PTYPE_TUNNEL_GTPU |
3648                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3649                         RTE_PTYPE_INNER_L4_FRAG,
3650                 [342] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3651                         RTE_PTYPE_TUNNEL_GTPU |
3652                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3653                         RTE_PTYPE_INNER_L4_NONFRAG,
3654                 [343] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3655                         RTE_PTYPE_TUNNEL_GTPU |
3656                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3657                         RTE_PTYPE_INNER_L4_UDP,
3658                 [344] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3659                         RTE_PTYPE_TUNNEL_GTPU |
3660                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3661                         RTE_PTYPE_INNER_L4_TCP,
3662                 [345] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3663                         RTE_PTYPE_TUNNEL_GTPU |
3664                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3665                         RTE_PTYPE_INNER_L4_ICMP,
3666
3667                 /* IPv6 --> GTPU --> IPv6 */
3668                 [346] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3669                         RTE_PTYPE_TUNNEL_GTPU |
3670                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3671                         RTE_PTYPE_INNER_L4_FRAG,
3672                 [347] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3673                         RTE_PTYPE_TUNNEL_GTPU |
3674                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3675                         RTE_PTYPE_INNER_L4_NONFRAG,
3676                 [348] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3677                         RTE_PTYPE_TUNNEL_GTPU |
3678                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3679                         RTE_PTYPE_INNER_L4_UDP,
3680                 [349] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3681                         RTE_PTYPE_TUNNEL_GTPU |
3682                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3683                         RTE_PTYPE_INNER_L4_TCP,
3684                 [350] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3685                         RTE_PTYPE_TUNNEL_GTPU |
3686                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3687                         RTE_PTYPE_INNER_L4_ICMP,
3688
3689                 /* IPv4 --> UDP ECPRI */
3690                 [372] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3691                         RTE_PTYPE_L4_UDP,
3692                 [373] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3693                         RTE_PTYPE_L4_UDP,
3694                 [374] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3695                         RTE_PTYPE_L4_UDP,
3696                 [375] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3697                         RTE_PTYPE_L4_UDP,
3698                 [376] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3699                         RTE_PTYPE_L4_UDP,
3700                 [377] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3701                         RTE_PTYPE_L4_UDP,
3702                 [378] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3703                         RTE_PTYPE_L4_UDP,
3704                 [379] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3705                         RTE_PTYPE_L4_UDP,
3706                 [380] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3707                         RTE_PTYPE_L4_UDP,
3708                 [381] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3709                         RTE_PTYPE_L4_UDP,
3710
3711                 /* IPV6 --> UDP ECPRI */
3712                 [382] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3713                         RTE_PTYPE_L4_UDP,
3714                 [383] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3715                         RTE_PTYPE_L4_UDP,
3716                 [384] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3717                         RTE_PTYPE_L4_UDP,
3718                 [385] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3719                         RTE_PTYPE_L4_UDP,
3720                 [386] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3721                         RTE_PTYPE_L4_UDP,
3722                 [387] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3723                         RTE_PTYPE_L4_UDP,
3724                 [388] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3725                         RTE_PTYPE_L4_UDP,
3726                 [389] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3727                         RTE_PTYPE_L4_UDP,
3728                 [390] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3729                         RTE_PTYPE_L4_UDP,
3730                 [391] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3731                         RTE_PTYPE_L4_UDP,
3732                 /* All others reserved */
3733         };
3734
3735         return ptype_tbl[ptype];
3736 }
3737
3738 void __rte_cold
3739 iavf_set_default_ptype_table(struct rte_eth_dev *dev)
3740 {
3741         struct iavf_adapter *ad =
3742                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3743         int i;
3744
3745         for (i = 0; i < IAVF_MAX_PKT_TYPE; i++)
3746                 ad->ptype_tbl[i] = iavf_get_default_ptype(i);
3747 }