1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2017 Intel Corporation
13 #include <sys/queue.h>
15 #include <rte_string_fns.h>
16 #include <rte_memzone.h>
18 #include <rte_malloc.h>
19 #include <rte_ether.h>
20 #include <ethdev_driver.h>
29 #include "iavf_rxtx.h"
30 #include "iavf_ipsec_crypto.h"
31 #include "rte_pmd_iavf.h"
33 /* Offset of mbuf dynamic field for protocol extraction's metadata */
34 int rte_pmd_ifd_dynfield_proto_xtr_metadata_offs = -1;
36 /* Mask of mbuf dynamic flags for protocol extraction's type */
37 uint64_t rte_pmd_ifd_dynflag_proto_xtr_vlan_mask;
38 uint64_t rte_pmd_ifd_dynflag_proto_xtr_ipv4_mask;
39 uint64_t rte_pmd_ifd_dynflag_proto_xtr_ipv6_mask;
40 uint64_t rte_pmd_ifd_dynflag_proto_xtr_ipv6_flow_mask;
41 uint64_t rte_pmd_ifd_dynflag_proto_xtr_tcp_mask;
42 uint64_t rte_pmd_ifd_dynflag_proto_xtr_ip_offset_mask;
43 uint64_t rte_pmd_ifd_dynflag_proto_xtr_ipsec_crypto_said_mask;
46 iavf_proto_xtr_type_to_rxdid(uint8_t flex_type)
48 static uint8_t rxdid_map[] = {
49 [IAVF_PROTO_XTR_NONE] = IAVF_RXDID_COMMS_OVS_1,
50 [IAVF_PROTO_XTR_VLAN] = IAVF_RXDID_COMMS_AUX_VLAN,
51 [IAVF_PROTO_XTR_IPV4] = IAVF_RXDID_COMMS_AUX_IPV4,
52 [IAVF_PROTO_XTR_IPV6] = IAVF_RXDID_COMMS_AUX_IPV6,
53 [IAVF_PROTO_XTR_IPV6_FLOW] = IAVF_RXDID_COMMS_AUX_IPV6_FLOW,
54 [IAVF_PROTO_XTR_TCP] = IAVF_RXDID_COMMS_AUX_TCP,
55 [IAVF_PROTO_XTR_IP_OFFSET] = IAVF_RXDID_COMMS_AUX_IP_OFFSET,
56 [IAVF_PROTO_XTR_IPSEC_CRYPTO_SAID] =
57 IAVF_RXDID_COMMS_IPSEC_CRYPTO,
60 return flex_type < RTE_DIM(rxdid_map) ?
61 rxdid_map[flex_type] : IAVF_RXDID_COMMS_OVS_1;
65 iavf_monitor_callback(const uint64_t value,
66 const uint64_t arg[RTE_POWER_MONITOR_OPAQUE_SZ] __rte_unused)
68 const uint64_t m = rte_cpu_to_le_64(1 << IAVF_RX_DESC_STATUS_DD_SHIFT);
70 * we expect the DD bit to be set to 1 if this descriptor was already
73 return (value & m) == m ? -1 : 0;
77 iavf_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc)
79 struct iavf_rx_queue *rxq = rx_queue;
80 volatile union iavf_rx_desc *rxdp;
84 rxdp = &rxq->rx_ring[desc];
85 /* watch for changes in status bit */
86 pmc->addr = &rxdp->wb.qword1.status_error_len;
88 /* comparison callback */
89 pmc->fn = iavf_monitor_callback;
91 /* registers are 64-bit */
92 pmc->size = sizeof(uint64_t);
98 check_rx_thresh(uint16_t nb_desc, uint16_t thresh)
100 /* The following constraints must be satisfied:
101 * thresh < rxq->nb_rx_desc
103 if (thresh >= nb_desc) {
104 PMD_INIT_LOG(ERR, "rx_free_thresh (%u) must be less than %u",
112 check_tx_thresh(uint16_t nb_desc, uint16_t tx_rs_thresh,
113 uint16_t tx_free_thresh)
115 /* TX descriptors will have their RS bit set after tx_rs_thresh
116 * descriptors have been used. The TX descriptor ring will be cleaned
117 * after tx_free_thresh descriptors are used or if the number of
118 * descriptors required to transmit a packet is greater than the
119 * number of free TX descriptors.
121 * The following constraints must be satisfied:
122 * - tx_rs_thresh must be less than the size of the ring minus 2.
123 * - tx_free_thresh must be less than the size of the ring minus 3.
124 * - tx_rs_thresh must be less than or equal to tx_free_thresh.
125 * - tx_rs_thresh must be a divisor of the ring size.
127 * One descriptor in the TX ring is used as a sentinel to avoid a H/W
128 * race condition, hence the maximum threshold constraints. When set
129 * to zero use default values.
131 if (tx_rs_thresh >= (nb_desc - 2)) {
132 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be less than the "
133 "number of TX descriptors (%u) minus 2",
134 tx_rs_thresh, nb_desc);
137 if (tx_free_thresh >= (nb_desc - 3)) {
138 PMD_INIT_LOG(ERR, "tx_free_thresh (%u) must be less than the "
139 "number of TX descriptors (%u) minus 3.",
140 tx_free_thresh, nb_desc);
143 if (tx_rs_thresh > tx_free_thresh) {
144 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be less than or "
145 "equal to tx_free_thresh (%u).",
146 tx_rs_thresh, tx_free_thresh);
149 if ((nb_desc % tx_rs_thresh) != 0) {
150 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be a divisor of the "
151 "number of TX descriptors (%u).",
152 tx_rs_thresh, nb_desc);
160 check_rx_vec_allow(struct iavf_rx_queue *rxq)
162 if (rxq->rx_free_thresh >= IAVF_VPMD_RX_MAX_BURST &&
163 rxq->nb_rx_desc % rxq->rx_free_thresh == 0) {
164 PMD_INIT_LOG(DEBUG, "Vector Rx can be enabled on this rxq.");
168 PMD_INIT_LOG(DEBUG, "Vector Rx cannot be enabled on this rxq.");
173 check_tx_vec_allow(struct iavf_tx_queue *txq)
175 if (!(txq->offloads & IAVF_TX_NO_VECTOR_FLAGS) &&
176 txq->rs_thresh >= IAVF_VPMD_TX_MAX_BURST &&
177 txq->rs_thresh <= IAVF_VPMD_TX_MAX_FREE_BUF) {
178 PMD_INIT_LOG(DEBUG, "Vector tx can be enabled on this txq.");
181 PMD_INIT_LOG(DEBUG, "Vector Tx cannot be enabled on this txq.");
186 check_rx_bulk_allow(struct iavf_rx_queue *rxq)
190 if (!(rxq->rx_free_thresh >= IAVF_RX_MAX_BURST)) {
191 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
192 "rxq->rx_free_thresh=%d, "
193 "IAVF_RX_MAX_BURST=%d",
194 rxq->rx_free_thresh, IAVF_RX_MAX_BURST);
196 } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
197 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
198 "rxq->nb_rx_desc=%d, "
199 "rxq->rx_free_thresh=%d",
200 rxq->nb_rx_desc, rxq->rx_free_thresh);
207 reset_rx_queue(struct iavf_rx_queue *rxq)
215 len = rxq->nb_rx_desc + IAVF_RX_MAX_BURST;
217 for (i = 0; i < len * sizeof(union iavf_rx_desc); i++)
218 ((volatile char *)rxq->rx_ring)[i] = 0;
220 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
222 for (i = 0; i < IAVF_RX_MAX_BURST; i++)
223 rxq->sw_ring[rxq->nb_rx_desc + i] = &rxq->fake_mbuf;
226 rxq->rx_nb_avail = 0;
227 rxq->rx_next_avail = 0;
228 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
233 rte_pktmbuf_free(rxq->pkt_first_seg);
235 rxq->pkt_first_seg = NULL;
236 rxq->pkt_last_seg = NULL;
238 rxq->rxrearm_start = 0;
242 reset_tx_queue(struct iavf_tx_queue *txq)
244 struct iavf_tx_entry *txe;
249 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
254 size = sizeof(struct iavf_tx_desc) * txq->nb_tx_desc;
255 for (i = 0; i < size; i++)
256 ((volatile char *)txq->tx_ring)[i] = 0;
258 prev = (uint16_t)(txq->nb_tx_desc - 1);
259 for (i = 0; i < txq->nb_tx_desc; i++) {
260 txq->tx_ring[i].cmd_type_offset_bsz =
261 rte_cpu_to_le_64(IAVF_TX_DESC_DTYPE_DESC_DONE);
264 txe[prev].next_id = i;
271 txq->last_desc_cleaned = txq->nb_tx_desc - 1;
272 txq->nb_free = txq->nb_tx_desc - 1;
274 txq->next_dd = txq->rs_thresh - 1;
275 txq->next_rs = txq->rs_thresh - 1;
279 alloc_rxq_mbufs(struct iavf_rx_queue *rxq)
281 volatile union iavf_rx_desc *rxd;
282 struct rte_mbuf *mbuf = NULL;
286 for (i = 0; i < rxq->nb_rx_desc; i++) {
287 mbuf = rte_mbuf_raw_alloc(rxq->mp);
288 if (unlikely(!mbuf)) {
289 for (j = 0; j < i; j++) {
290 rte_pktmbuf_free_seg(rxq->sw_ring[j]);
291 rxq->sw_ring[j] = NULL;
293 PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
297 rte_mbuf_refcnt_set(mbuf, 1);
299 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
301 mbuf->port = rxq->port_id;
304 rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
306 rxd = &rxq->rx_ring[i];
307 rxd->read.pkt_addr = dma_addr;
308 rxd->read.hdr_addr = 0;
309 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
314 rxq->sw_ring[i] = mbuf;
321 release_rxq_mbufs(struct iavf_rx_queue *rxq)
328 for (i = 0; i < rxq->nb_rx_desc; i++) {
329 if (rxq->sw_ring[i]) {
330 rte_pktmbuf_free_seg(rxq->sw_ring[i]);
331 rxq->sw_ring[i] = NULL;
336 if (rxq->rx_nb_avail == 0)
338 for (i = 0; i < rxq->rx_nb_avail; i++) {
339 struct rte_mbuf *mbuf;
341 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
342 rte_pktmbuf_free_seg(mbuf);
344 rxq->rx_nb_avail = 0;
348 release_txq_mbufs(struct iavf_tx_queue *txq)
352 if (!txq || !txq->sw_ring) {
353 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
357 for (i = 0; i < txq->nb_tx_desc; i++) {
358 if (txq->sw_ring[i].mbuf) {
359 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
360 txq->sw_ring[i].mbuf = NULL;
365 static const struct iavf_rxq_ops def_rxq_ops = {
366 .release_mbufs = release_rxq_mbufs,
369 static const struct iavf_txq_ops def_txq_ops = {
370 .release_mbufs = release_txq_mbufs,
374 iavf_rxd_to_pkt_fields_by_comms_ovs(__rte_unused struct iavf_rx_queue *rxq,
376 volatile union iavf_rx_flex_desc *rxdp)
378 volatile struct iavf_32b_rx_flex_desc_comms_ovs *desc =
379 (volatile struct iavf_32b_rx_flex_desc_comms_ovs *)rxdp;
380 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
384 if (desc->flow_id != 0xFFFFFFFF) {
385 mb->ol_flags |= RTE_MBUF_F_RX_FDIR | RTE_MBUF_F_RX_FDIR_ID;
386 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
389 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
390 stat_err = rte_le_to_cpu_16(desc->status_error0);
391 if (likely(stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
392 mb->ol_flags |= RTE_MBUF_F_RX_RSS_HASH;
393 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
399 iavf_rxd_to_pkt_fields_by_comms_aux_v1(struct iavf_rx_queue *rxq,
401 volatile union iavf_rx_flex_desc *rxdp)
403 volatile struct iavf_32b_rx_flex_desc_comms *desc =
404 (volatile struct iavf_32b_rx_flex_desc_comms *)rxdp;
407 stat_err = rte_le_to_cpu_16(desc->status_error0);
408 if (likely(stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
409 mb->ol_flags |= RTE_MBUF_F_RX_RSS_HASH;
410 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
413 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
414 if (desc->flow_id != 0xFFFFFFFF) {
415 mb->ol_flags |= RTE_MBUF_F_RX_FDIR | RTE_MBUF_F_RX_FDIR_ID;
416 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
419 if (rxq->xtr_ol_flag) {
420 uint32_t metadata = 0;
422 stat_err = rte_le_to_cpu_16(desc->status_error1);
424 if (stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS1_XTRMD4_VALID_S))
425 metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux0);
427 if (stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS1_XTRMD5_VALID_S))
429 rte_le_to_cpu_16(desc->flex_ts.flex.aux1) << 16;
432 mb->ol_flags |= rxq->xtr_ol_flag;
434 *RTE_PMD_IFD_DYNF_PROTO_XTR_METADATA(mb) = metadata;
441 iavf_rxd_to_pkt_fields_by_comms_aux_v2(struct iavf_rx_queue *rxq,
443 volatile union iavf_rx_flex_desc *rxdp)
445 volatile struct iavf_32b_rx_flex_desc_comms *desc =
446 (volatile struct iavf_32b_rx_flex_desc_comms *)rxdp;
449 stat_err = rte_le_to_cpu_16(desc->status_error0);
450 if (likely(stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
451 mb->ol_flags |= RTE_MBUF_F_RX_RSS_HASH;
452 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
455 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
456 if (desc->flow_id != 0xFFFFFFFF) {
457 mb->ol_flags |= RTE_MBUF_F_RX_FDIR | RTE_MBUF_F_RX_FDIR_ID;
458 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
461 if (rxq->xtr_ol_flag) {
462 uint32_t metadata = 0;
464 if (desc->flex_ts.flex.aux0 != 0xFFFF)
465 metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux0);
466 else if (desc->flex_ts.flex.aux1 != 0xFFFF)
467 metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux1);
470 mb->ol_flags |= rxq->xtr_ol_flag;
472 *RTE_PMD_IFD_DYNF_PROTO_XTR_METADATA(mb) = metadata;
479 iavf_rxd_to_pkt_fields_t rxd_to_pkt_fields_ops[IAVF_RXDID_LAST + 1] = {
480 [IAVF_RXDID_LEGACY_0] = iavf_rxd_to_pkt_fields_by_comms_ovs,
481 [IAVF_RXDID_LEGACY_1] = iavf_rxd_to_pkt_fields_by_comms_ovs,
482 [IAVF_RXDID_COMMS_AUX_VLAN] = iavf_rxd_to_pkt_fields_by_comms_aux_v1,
483 [IAVF_RXDID_COMMS_AUX_IPV4] = iavf_rxd_to_pkt_fields_by_comms_aux_v1,
484 [IAVF_RXDID_COMMS_AUX_IPV6] = iavf_rxd_to_pkt_fields_by_comms_aux_v1,
485 [IAVF_RXDID_COMMS_AUX_IPV6_FLOW] =
486 iavf_rxd_to_pkt_fields_by_comms_aux_v1,
487 [IAVF_RXDID_COMMS_AUX_TCP] = iavf_rxd_to_pkt_fields_by_comms_aux_v1,
488 [IAVF_RXDID_COMMS_AUX_IP_OFFSET] =
489 iavf_rxd_to_pkt_fields_by_comms_aux_v2,
490 [IAVF_RXDID_COMMS_IPSEC_CRYPTO] =
491 iavf_rxd_to_pkt_fields_by_comms_aux_v2,
492 [IAVF_RXDID_COMMS_OVS_1] = iavf_rxd_to_pkt_fields_by_comms_ovs,
496 iavf_select_rxd_to_pkt_fields_handler(struct iavf_rx_queue *rxq, uint32_t rxdid)
501 case IAVF_RXDID_COMMS_AUX_VLAN:
502 rxq->xtr_ol_flag = rte_pmd_ifd_dynflag_proto_xtr_vlan_mask;
504 case IAVF_RXDID_COMMS_AUX_IPV4:
505 rxq->xtr_ol_flag = rte_pmd_ifd_dynflag_proto_xtr_ipv4_mask;
507 case IAVF_RXDID_COMMS_AUX_IPV6:
508 rxq->xtr_ol_flag = rte_pmd_ifd_dynflag_proto_xtr_ipv6_mask;
510 case IAVF_RXDID_COMMS_AUX_IPV6_FLOW:
512 rte_pmd_ifd_dynflag_proto_xtr_ipv6_flow_mask;
514 case IAVF_RXDID_COMMS_AUX_TCP:
515 rxq->xtr_ol_flag = rte_pmd_ifd_dynflag_proto_xtr_tcp_mask;
517 case IAVF_RXDID_COMMS_AUX_IP_OFFSET:
519 rte_pmd_ifd_dynflag_proto_xtr_ip_offset_mask;
521 case IAVF_RXDID_COMMS_IPSEC_CRYPTO:
523 rte_pmd_ifd_dynflag_proto_xtr_ipsec_crypto_said_mask;
525 case IAVF_RXDID_COMMS_OVS_1:
526 case IAVF_RXDID_LEGACY_0:
527 case IAVF_RXDID_LEGACY_1:
530 /* update this according to the RXDID for FLEX_DESC_NONE */
531 rxq->rxdid = IAVF_RXDID_COMMS_OVS_1;
535 if (!rte_pmd_ifd_dynf_proto_xtr_metadata_avail())
536 rxq->xtr_ol_flag = 0;
540 iavf_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
541 uint16_t nb_desc, unsigned int socket_id,
542 const struct rte_eth_rxconf *rx_conf,
543 struct rte_mempool *mp)
545 struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
546 struct iavf_adapter *ad =
547 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
548 struct iavf_info *vf =
549 IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
550 struct iavf_vsi *vsi = &vf->vsi;
551 struct iavf_rx_queue *rxq;
552 const struct rte_memzone *mz;
556 uint16_t rx_free_thresh;
559 PMD_INIT_FUNC_TRACE();
561 offloads = rx_conf->offloads | dev->data->dev_conf.rxmode.offloads;
563 if (nb_desc % IAVF_ALIGN_RING_DESC != 0 ||
564 nb_desc > IAVF_MAX_RING_DESC ||
565 nb_desc < IAVF_MIN_RING_DESC) {
566 PMD_INIT_LOG(ERR, "Number (%u) of receive descriptors is "
571 /* Check free threshold */
572 rx_free_thresh = (rx_conf->rx_free_thresh == 0) ?
573 IAVF_DEFAULT_RX_FREE_THRESH :
574 rx_conf->rx_free_thresh;
575 if (check_rx_thresh(nb_desc, rx_free_thresh) != 0)
578 /* Free memory if needed */
579 if (dev->data->rx_queues[queue_idx]) {
580 iavf_dev_rx_queue_release(dev, queue_idx);
581 dev->data->rx_queues[queue_idx] = NULL;
584 /* Allocate the rx queue data structure */
585 rxq = rte_zmalloc_socket("iavf rxq",
586 sizeof(struct iavf_rx_queue),
590 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
591 "rx queue data structure");
595 if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC) {
596 proto_xtr = vf->proto_xtr ? vf->proto_xtr[queue_idx] :
598 rxq->rxdid = iavf_proto_xtr_type_to_rxdid(proto_xtr);
599 rxq->proto_xtr = proto_xtr;
601 rxq->rxdid = IAVF_RXDID_LEGACY_1;
602 rxq->proto_xtr = IAVF_PROTO_XTR_NONE;
605 if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_VLAN_V2) {
606 struct virtchnl_vlan_supported_caps *stripping_support =
607 &vf->vlan_v2_caps.offloads.stripping_support;
608 uint32_t stripping_cap;
610 if (stripping_support->outer)
611 stripping_cap = stripping_support->outer;
613 stripping_cap = stripping_support->inner;
615 if (stripping_cap & VIRTCHNL_VLAN_TAG_LOCATION_L2TAG1)
616 rxq->rx_flags = IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG1;
617 else if (stripping_cap & VIRTCHNL_VLAN_TAG_LOCATION_L2TAG2_2)
618 rxq->rx_flags = IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG2_2;
620 rxq->rx_flags = IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG1;
623 iavf_select_rxd_to_pkt_fields_handler(rxq, rxq->rxdid);
626 rxq->nb_rx_desc = nb_desc;
627 rxq->rx_free_thresh = rx_free_thresh;
628 rxq->queue_id = queue_idx;
629 rxq->port_id = dev->data->port_id;
630 rxq->rx_deferred_start = rx_conf->rx_deferred_start;
633 rxq->offloads = offloads;
635 if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_KEEP_CRC)
636 rxq->crc_len = RTE_ETHER_CRC_LEN;
640 len = rte_pktmbuf_data_room_size(rxq->mp) - RTE_PKTMBUF_HEADROOM;
641 rxq->rx_buf_len = RTE_ALIGN_FLOOR(len, (1 << IAVF_RXQ_CTX_DBUFF_SHIFT));
643 /* Allocate the software ring. */
644 len = nb_desc + IAVF_RX_MAX_BURST;
646 rte_zmalloc_socket("iavf rx sw ring",
647 sizeof(struct rte_mbuf *) * len,
651 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW ring");
656 /* Allocate the maximum number of RX ring hardware descriptor with
657 * a little more to support bulk allocate.
659 len = IAVF_MAX_RING_DESC + IAVF_RX_MAX_BURST;
660 ring_size = RTE_ALIGN(len * sizeof(union iavf_rx_desc),
662 mz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
663 ring_size, IAVF_RING_BASE_ALIGN,
666 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for RX");
667 rte_free(rxq->sw_ring);
671 /* Zero all the descriptors in the ring. */
672 memset(mz->addr, 0, ring_size);
673 rxq->rx_ring_phys_addr = mz->iova;
674 rxq->rx_ring = (union iavf_rx_desc *)mz->addr;
679 dev->data->rx_queues[queue_idx] = rxq;
680 rxq->qrx_tail = hw->hw_addr + IAVF_QRX_TAIL1(rxq->queue_id);
681 rxq->ops = &def_rxq_ops;
683 if (check_rx_bulk_allow(rxq) == true) {
684 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
685 "satisfied. Rx Burst Bulk Alloc function will be "
686 "used on port=%d, queue=%d.",
687 rxq->port_id, rxq->queue_id);
689 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
690 "not satisfied, Scattered Rx is requested "
691 "on port=%d, queue=%d.",
692 rxq->port_id, rxq->queue_id);
693 ad->rx_bulk_alloc_allowed = false;
696 if (check_rx_vec_allow(rxq) == false)
697 ad->rx_vec_allowed = false;
703 iavf_dev_tx_queue_setup(struct rte_eth_dev *dev,
706 unsigned int socket_id,
707 const struct rte_eth_txconf *tx_conf)
709 struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
710 struct iavf_adapter *adapter =
711 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
712 struct iavf_info *vf =
713 IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
714 struct iavf_tx_queue *txq;
715 const struct rte_memzone *mz;
717 uint16_t tx_rs_thresh, tx_free_thresh;
720 PMD_INIT_FUNC_TRACE();
722 offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
724 if (nb_desc % IAVF_ALIGN_RING_DESC != 0 ||
725 nb_desc > IAVF_MAX_RING_DESC ||
726 nb_desc < IAVF_MIN_RING_DESC) {
727 PMD_INIT_LOG(ERR, "Number (%u) of transmit descriptors is "
732 tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
733 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
734 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
735 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
736 if (check_tx_thresh(nb_desc, tx_rs_thresh, tx_free_thresh) != 0)
739 /* Free memory if needed. */
740 if (dev->data->tx_queues[queue_idx]) {
741 iavf_dev_tx_queue_release(dev, queue_idx);
742 dev->data->tx_queues[queue_idx] = NULL;
745 /* Allocate the TX queue data structure. */
746 txq = rte_zmalloc_socket("iavf txq",
747 sizeof(struct iavf_tx_queue),
751 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
752 "tx queue structure");
756 if (adapter->vf.vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_VLAN_V2) {
757 struct virtchnl_vlan_supported_caps *insertion_support =
758 &adapter->vf.vlan_v2_caps.offloads.insertion_support;
759 uint32_t insertion_cap;
761 if (insertion_support->outer)
762 insertion_cap = insertion_support->outer;
764 insertion_cap = insertion_support->inner;
766 if (insertion_cap & VIRTCHNL_VLAN_TAG_LOCATION_L2TAG1)
767 txq->vlan_flag = IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG1;
768 else if (insertion_cap & VIRTCHNL_VLAN_TAG_LOCATION_L2TAG2)
769 txq->vlan_flag = IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG2;
771 txq->vlan_flag = IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG1;
774 txq->nb_tx_desc = nb_desc;
775 txq->rs_thresh = tx_rs_thresh;
776 txq->free_thresh = tx_free_thresh;
777 txq->queue_id = queue_idx;
778 txq->port_id = dev->data->port_id;
779 txq->offloads = offloads;
780 txq->tx_deferred_start = tx_conf->tx_deferred_start;
782 if (iavf_ipsec_crypto_supported(adapter))
783 txq->ipsec_crypto_pkt_md_offset =
784 iavf_security_get_pkt_md_offset(adapter);
786 /* Allocate software ring */
788 rte_zmalloc_socket("iavf tx sw ring",
789 sizeof(struct iavf_tx_entry) * nb_desc,
793 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW TX ring");
798 /* Allocate TX hardware ring descriptors. */
799 ring_size = sizeof(struct iavf_tx_desc) * IAVF_MAX_RING_DESC;
800 ring_size = RTE_ALIGN(ring_size, IAVF_DMA_MEM_ALIGN);
801 mz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
802 ring_size, IAVF_RING_BASE_ALIGN,
805 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for TX");
806 rte_free(txq->sw_ring);
810 txq->tx_ring_phys_addr = mz->iova;
811 txq->tx_ring = (struct iavf_tx_desc *)mz->addr;
816 dev->data->tx_queues[queue_idx] = txq;
817 txq->qtx_tail = hw->hw_addr + IAVF_QTX_TAIL1(queue_idx);
818 txq->ops = &def_txq_ops;
820 if (check_tx_vec_allow(txq) == false) {
821 struct iavf_adapter *ad =
822 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
823 ad->tx_vec_allowed = false;
826 if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_QOS &&
827 vf->tm_conf.committed) {
829 for (tc = 0; tc < vf->qos_cap->num_elem; tc++) {
830 if (txq->queue_id >= vf->qtc_map[tc].start_queue_id &&
831 txq->queue_id < (vf->qtc_map[tc].start_queue_id +
832 vf->qtc_map[tc].queue_count))
835 if (tc >= vf->qos_cap->num_elem) {
836 PMD_INIT_LOG(ERR, "Queue TC mapping is not correct");
846 iavf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
848 struct iavf_adapter *adapter =
849 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
850 struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
851 struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
852 struct iavf_rx_queue *rxq;
855 PMD_DRV_FUNC_TRACE();
857 if (rx_queue_id >= dev->data->nb_rx_queues)
860 rxq = dev->data->rx_queues[rx_queue_id];
862 err = alloc_rxq_mbufs(rxq);
864 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
870 /* Init the RX tail register. */
871 IAVF_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
872 IAVF_WRITE_FLUSH(hw);
874 /* Ready to switch the queue on */
876 err = iavf_switch_queue(adapter, rx_queue_id, true, true);
878 err = iavf_switch_queue_lv(adapter, rx_queue_id, true, true);
881 release_rxq_mbufs(rxq);
882 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
885 dev->data->rx_queue_state[rx_queue_id] =
886 RTE_ETH_QUEUE_STATE_STARTED;
893 iavf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
895 struct iavf_adapter *adapter =
896 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
897 struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
898 struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
899 struct iavf_tx_queue *txq;
902 PMD_DRV_FUNC_TRACE();
904 if (tx_queue_id >= dev->data->nb_tx_queues)
907 txq = dev->data->tx_queues[tx_queue_id];
909 /* Init the RX tail register. */
910 IAVF_PCI_REG_WRITE(txq->qtx_tail, 0);
911 IAVF_WRITE_FLUSH(hw);
913 /* Ready to switch the queue on */
915 err = iavf_switch_queue(adapter, tx_queue_id, false, true);
917 err = iavf_switch_queue_lv(adapter, tx_queue_id, false, true);
920 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
923 dev->data->tx_queue_state[tx_queue_id] =
924 RTE_ETH_QUEUE_STATE_STARTED;
930 iavf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
932 struct iavf_adapter *adapter =
933 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
934 struct iavf_rx_queue *rxq;
937 PMD_DRV_FUNC_TRACE();
939 if (rx_queue_id >= dev->data->nb_rx_queues)
942 err = iavf_switch_queue(adapter, rx_queue_id, true, false);
944 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
949 rxq = dev->data->rx_queues[rx_queue_id];
950 rxq->ops->release_mbufs(rxq);
952 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
958 iavf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
960 struct iavf_adapter *adapter =
961 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
962 struct iavf_tx_queue *txq;
965 PMD_DRV_FUNC_TRACE();
967 if (tx_queue_id >= dev->data->nb_tx_queues)
970 err = iavf_switch_queue(adapter, tx_queue_id, false, false);
972 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u off",
977 txq = dev->data->tx_queues[tx_queue_id];
978 txq->ops->release_mbufs(txq);
980 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
986 iavf_dev_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
988 struct iavf_rx_queue *q = dev->data->rx_queues[qid];
993 q->ops->release_mbufs(q);
994 rte_free(q->sw_ring);
995 rte_memzone_free(q->mz);
1000 iavf_dev_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
1002 struct iavf_tx_queue *q = dev->data->tx_queues[qid];
1007 q->ops->release_mbufs(q);
1008 rte_free(q->sw_ring);
1009 rte_memzone_free(q->mz);
1014 iavf_stop_queues(struct rte_eth_dev *dev)
1016 struct iavf_adapter *adapter =
1017 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1018 struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1019 struct iavf_rx_queue *rxq;
1020 struct iavf_tx_queue *txq;
1023 /* Stop All queues */
1024 if (!vf->lv_enabled) {
1025 ret = iavf_disable_queues(adapter);
1027 PMD_DRV_LOG(WARNING, "Fail to stop queues");
1029 ret = iavf_disable_queues_lv(adapter);
1031 PMD_DRV_LOG(WARNING, "Fail to stop queues for large VF");
1035 PMD_DRV_LOG(WARNING, "Fail to stop queues");
1037 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1038 txq = dev->data->tx_queues[i];
1041 txq->ops->release_mbufs(txq);
1042 reset_tx_queue(txq);
1043 dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED;
1045 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1046 rxq = dev->data->rx_queues[i];
1049 rxq->ops->release_mbufs(rxq);
1050 reset_rx_queue(rxq);
1051 dev->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED;
1055 #define IAVF_RX_FLEX_ERR0_BITS \
1056 ((1 << IAVF_RX_FLEX_DESC_STATUS0_HBO_S) | \
1057 (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_IPE_S) | \
1058 (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_L4E_S) | \
1059 (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S) | \
1060 (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S) | \
1061 (1 << IAVF_RX_FLEX_DESC_STATUS0_RXE_S))
1064 iavf_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union iavf_rx_desc *rxdp)
1066 if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1067 (1 << IAVF_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
1068 mb->ol_flags |= RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED;
1070 rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
1077 iavf_flex_rxd_to_vlan_tci(struct rte_mbuf *mb,
1078 volatile union iavf_rx_flex_desc *rxdp)
1080 if (rte_le_to_cpu_64(rxdp->wb.status_error0) &
1081 (1 << IAVF_RX_FLEX_DESC_STATUS0_L2TAG1P_S)) {
1082 mb->ol_flags |= RTE_MBUF_F_RX_VLAN |
1083 RTE_MBUF_F_RX_VLAN_STRIPPED;
1085 rte_le_to_cpu_16(rxdp->wb.l2tag1);
1090 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
1091 if (rte_le_to_cpu_16(rxdp->wb.status_error1) &
1092 (1 << IAVF_RX_FLEX_DESC_STATUS1_L2TAG2P_S)) {
1093 mb->ol_flags |= RTE_MBUF_F_RX_QINQ_STRIPPED |
1094 RTE_MBUF_F_RX_QINQ |
1095 RTE_MBUF_F_RX_VLAN_STRIPPED |
1097 mb->vlan_tci_outer = mb->vlan_tci;
1098 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.l2tag2_2nd);
1099 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
1100 rte_le_to_cpu_16(rxdp->wb.l2tag2_1st),
1101 rte_le_to_cpu_16(rxdp->wb.l2tag2_2nd));
1103 mb->vlan_tci_outer = 0;
1109 iavf_flex_rxd_to_ipsec_crypto_said_get(struct rte_mbuf *mb,
1110 volatile union iavf_rx_flex_desc *rxdp)
1112 volatile struct iavf_32b_rx_flex_desc_comms_ipsec *desc =
1113 (volatile struct iavf_32b_rx_flex_desc_comms_ipsec *)rxdp;
1115 mb->dynfield1[0] = desc->ipsec_said &
1116 IAVF_RX_FLEX_DESC_IPSEC_CRYPTO_SAID_MASK;
1120 iavf_flex_rxd_to_ipsec_crypto_status(struct rte_mbuf *mb,
1121 volatile union iavf_rx_flex_desc *rxdp,
1122 struct iavf_ipsec_crypto_stats *stats)
1124 uint16_t status1 = rte_le_to_cpu_64(rxdp->wb.status_error1);
1126 if (status1 & BIT(IAVF_RX_FLEX_DESC_STATUS1_IPSEC_CRYPTO_PROCESSED)) {
1127 uint16_t ipsec_status;
1129 mb->ol_flags |= RTE_MBUF_F_RX_SEC_OFFLOAD;
1131 ipsec_status = status1 &
1132 IAVF_RX_FLEX_DESC_IPSEC_CRYPTO_STATUS_MASK;
1135 if (unlikely(ipsec_status !=
1136 IAVF_IPSEC_CRYPTO_STATUS_SUCCESS)) {
1137 mb->ol_flags |= RTE_MBUF_F_RX_SEC_OFFLOAD_FAILED;
1139 switch (ipsec_status) {
1140 case IAVF_IPSEC_CRYPTO_STATUS_SAD_MISS:
1141 stats->ierrors.sad_miss++;
1143 case IAVF_IPSEC_CRYPTO_STATUS_NOT_PROCESSED:
1144 stats->ierrors.not_processed++;
1146 case IAVF_IPSEC_CRYPTO_STATUS_ICV_CHECK_FAIL:
1147 stats->ierrors.icv_check++;
1149 case IAVF_IPSEC_CRYPTO_STATUS_LENGTH_ERR:
1150 stats->ierrors.ipsec_length++;
1152 case IAVF_IPSEC_CRYPTO_STATUS_MISC_ERR:
1153 stats->ierrors.misc++;
1157 stats->ierrors.count++;
1162 stats->ibytes += rxdp->wb.pkt_len & 0x3FFF;
1164 if (rxdp->wb.rxdid == IAVF_RXDID_COMMS_IPSEC_CRYPTO &&
1166 IAVF_IPSEC_CRYPTO_STATUS_SAD_MISS)
1167 iavf_flex_rxd_to_ipsec_crypto_said_get(mb, rxdp);
1172 /* Translate the rx descriptor status and error fields to pkt flags */
1173 static inline uint64_t
1174 iavf_rxd_to_pkt_flags(uint64_t qword)
1177 uint64_t error_bits = (qword >> IAVF_RXD_QW1_ERROR_SHIFT);
1179 #define IAVF_RX_ERR_BITS 0x3f
1181 /* Check if RSS_HASH */
1182 flags = (((qword >> IAVF_RX_DESC_STATUS_FLTSTAT_SHIFT) &
1183 IAVF_RX_DESC_FLTSTAT_RSS_HASH) ==
1184 IAVF_RX_DESC_FLTSTAT_RSS_HASH) ? RTE_MBUF_F_RX_RSS_HASH : 0;
1186 /* Check if FDIR Match */
1187 flags |= (qword & (1 << IAVF_RX_DESC_STATUS_FLM_SHIFT) ?
1188 RTE_MBUF_F_RX_FDIR : 0);
1190 if (likely((error_bits & IAVF_RX_ERR_BITS) == 0)) {
1191 flags |= (RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_GOOD);
1195 if (unlikely(error_bits & (1 << IAVF_RX_DESC_ERROR_IPE_SHIFT)))
1196 flags |= RTE_MBUF_F_RX_IP_CKSUM_BAD;
1198 flags |= RTE_MBUF_F_RX_IP_CKSUM_GOOD;
1200 if (unlikely(error_bits & (1 << IAVF_RX_DESC_ERROR_L4E_SHIFT)))
1201 flags |= RTE_MBUF_F_RX_L4_CKSUM_BAD;
1203 flags |= RTE_MBUF_F_RX_L4_CKSUM_GOOD;
1205 /* TODO: Oversize error bit is not processed here */
1210 static inline uint64_t
1211 iavf_rxd_build_fdir(volatile union iavf_rx_desc *rxdp, struct rte_mbuf *mb)
1214 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
1217 flexbh = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
1218 IAVF_RX_DESC_EXT_STATUS_FLEXBH_SHIFT) &
1219 IAVF_RX_DESC_EXT_STATUS_FLEXBH_MASK;
1221 if (flexbh == IAVF_RX_DESC_EXT_STATUS_FLEXBH_FD_ID) {
1223 rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.fd_id);
1224 flags |= RTE_MBUF_F_RX_FDIR_ID;
1228 rte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.fd_id);
1229 flags |= RTE_MBUF_F_RX_FDIR_ID;
1234 #define IAVF_RX_FLEX_ERR0_BITS \
1235 ((1 << IAVF_RX_FLEX_DESC_STATUS0_HBO_S) | \
1236 (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_IPE_S) | \
1237 (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_L4E_S) | \
1238 (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S) | \
1239 (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S) | \
1240 (1 << IAVF_RX_FLEX_DESC_STATUS0_RXE_S))
1242 /* Rx L3/L4 checksum */
1243 static inline uint64_t
1244 iavf_flex_rxd_error_to_pkt_flags(uint16_t stat_err0)
1248 /* check if HW has decoded the packet and checksum */
1249 if (unlikely(!(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_L3L4P_S))))
1252 if (likely(!(stat_err0 & IAVF_RX_FLEX_ERR0_BITS))) {
1253 flags |= (RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_GOOD);
1257 if (unlikely(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_IPE_S)))
1258 flags |= RTE_MBUF_F_RX_IP_CKSUM_BAD;
1260 flags |= RTE_MBUF_F_RX_IP_CKSUM_GOOD;
1262 if (unlikely(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_L4E_S)))
1263 flags |= RTE_MBUF_F_RX_L4_CKSUM_BAD;
1265 flags |= RTE_MBUF_F_RX_L4_CKSUM_GOOD;
1267 if (unlikely(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S)))
1268 flags |= RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD;
1273 /* If the number of free RX descriptors is greater than the RX free
1274 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1275 * register. Update the RDT with the value of the last processed RX
1276 * descriptor minus 1, to guarantee that the RDT register is never
1277 * equal to the RDH register, which creates a "full" ring situation
1278 * from the hardware point of view.
1281 iavf_update_rx_tail(struct iavf_rx_queue *rxq, uint16_t nb_hold, uint16_t rx_id)
1283 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1285 if (nb_hold > rxq->rx_free_thresh) {
1287 "port_id=%u queue_id=%u rx_tail=%u nb_hold=%u",
1288 rxq->port_id, rxq->queue_id, rx_id, nb_hold);
1289 rx_id = (uint16_t)((rx_id == 0) ?
1290 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1291 IAVF_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
1294 rxq->nb_rx_hold = nb_hold;
1297 /* implement recv_pkts */
1299 iavf_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1301 volatile union iavf_rx_desc *rx_ring;
1302 volatile union iavf_rx_desc *rxdp;
1303 struct iavf_rx_queue *rxq;
1304 union iavf_rx_desc rxd;
1305 struct rte_mbuf *rxe;
1306 struct rte_eth_dev *dev;
1307 struct rte_mbuf *rxm;
1308 struct rte_mbuf *nmb;
1312 uint16_t rx_packet_len;
1313 uint16_t rx_id, nb_hold;
1316 const uint32_t *ptype_tbl;
1321 rx_id = rxq->rx_tail;
1322 rx_ring = rxq->rx_ring;
1323 ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1325 while (nb_rx < nb_pkts) {
1326 rxdp = &rx_ring[rx_id];
1327 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1328 rx_status = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
1329 IAVF_RXD_QW1_STATUS_SHIFT;
1331 /* Check the DD bit first */
1332 if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)))
1334 IAVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
1336 nmb = rte_mbuf_raw_alloc(rxq->mp);
1337 if (unlikely(!nmb)) {
1338 dev = &rte_eth_devices[rxq->port_id];
1339 dev->data->rx_mbuf_alloc_failed++;
1340 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1341 "queue_id=%u", rxq->port_id, rxq->queue_id);
1347 rxe = rxq->sw_ring[rx_id];
1348 rxq->sw_ring[rx_id] = nmb;
1350 if (unlikely(rx_id == rxq->nb_rx_desc))
1353 /* Prefetch next mbuf */
1354 rte_prefetch0(rxq->sw_ring[rx_id]);
1356 /* When next RX descriptor is on a cache line boundary,
1357 * prefetch the next 4 RX descriptors and next 8 pointers
1360 if ((rx_id & 0x3) == 0) {
1361 rte_prefetch0(&rx_ring[rx_id]);
1362 rte_prefetch0(rxq->sw_ring[rx_id]);
1366 rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1367 rxdp->read.hdr_addr = 0;
1368 rxdp->read.pkt_addr = dma_addr;
1370 rx_packet_len = ((qword1 & IAVF_RXD_QW1_LENGTH_PBUF_MASK) >>
1371 IAVF_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
1373 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1374 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
1377 rxm->pkt_len = rx_packet_len;
1378 rxm->data_len = rx_packet_len;
1379 rxm->port = rxq->port_id;
1381 iavf_rxd_to_vlan_tci(rxm, &rxd);
1382 pkt_flags = iavf_rxd_to_pkt_flags(qword1);
1384 ptype_tbl[(uint8_t)((qword1 &
1385 IAVF_RXD_QW1_PTYPE_MASK) >> IAVF_RXD_QW1_PTYPE_SHIFT)];
1387 if (pkt_flags & RTE_MBUF_F_RX_RSS_HASH)
1389 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1391 if (pkt_flags & RTE_MBUF_F_RX_FDIR)
1392 pkt_flags |= iavf_rxd_build_fdir(&rxd, rxm);
1394 rxm->ol_flags |= pkt_flags;
1396 rx_pkts[nb_rx++] = rxm;
1398 rxq->rx_tail = rx_id;
1400 iavf_update_rx_tail(rxq, nb_hold, rx_id);
1405 /* implement recv_pkts for flexible Rx descriptor */
1407 iavf_recv_pkts_flex_rxd(void *rx_queue,
1408 struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1410 volatile union iavf_rx_desc *rx_ring;
1411 volatile union iavf_rx_flex_desc *rxdp;
1412 struct iavf_rx_queue *rxq;
1413 union iavf_rx_flex_desc rxd;
1414 struct rte_mbuf *rxe;
1415 struct rte_eth_dev *dev;
1416 struct rte_mbuf *rxm;
1417 struct rte_mbuf *nmb;
1419 uint16_t rx_stat_err0;
1420 uint16_t rx_packet_len;
1421 uint16_t rx_id, nb_hold;
1424 const uint32_t *ptype_tbl;
1429 rx_id = rxq->rx_tail;
1430 rx_ring = rxq->rx_ring;
1431 ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1433 while (nb_rx < nb_pkts) {
1434 rxdp = (volatile union iavf_rx_flex_desc *)&rx_ring[rx_id];
1435 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1437 /* Check the DD bit first */
1438 if (!(rx_stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S)))
1440 IAVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
1442 nmb = rte_mbuf_raw_alloc(rxq->mp);
1443 if (unlikely(!nmb)) {
1444 dev = &rte_eth_devices[rxq->port_id];
1445 dev->data->rx_mbuf_alloc_failed++;
1446 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1447 "queue_id=%u", rxq->port_id, rxq->queue_id);
1453 rxe = rxq->sw_ring[rx_id];
1454 rxq->sw_ring[rx_id] = nmb;
1456 if (unlikely(rx_id == rxq->nb_rx_desc))
1459 /* Prefetch next mbuf */
1460 rte_prefetch0(rxq->sw_ring[rx_id]);
1462 /* When next RX descriptor is on a cache line boundary,
1463 * prefetch the next 4 RX descriptors and next 8 pointers
1466 if ((rx_id & 0x3) == 0) {
1467 rte_prefetch0(&rx_ring[rx_id]);
1468 rte_prefetch0(rxq->sw_ring[rx_id]);
1472 rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1473 rxdp->read.hdr_addr = 0;
1474 rxdp->read.pkt_addr = dma_addr;
1476 rx_packet_len = (rte_le_to_cpu_16(rxd.wb.pkt_len) &
1477 IAVF_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
1479 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1480 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
1483 rxm->pkt_len = rx_packet_len;
1484 rxm->data_len = rx_packet_len;
1485 rxm->port = rxq->port_id;
1487 rxm->packet_type = ptype_tbl[IAVF_RX_FLEX_DESC_PTYPE_M &
1488 rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
1489 iavf_flex_rxd_to_vlan_tci(rxm, &rxd);
1490 iavf_flex_rxd_to_ipsec_crypto_status(rxm, &rxd,
1491 &rxq->stats.ipsec_crypto);
1492 rxd_to_pkt_fields_ops[rxq->rxdid](rxq, rxm, &rxd);
1493 pkt_flags = iavf_flex_rxd_error_to_pkt_flags(rx_stat_err0);
1494 rxm->ol_flags |= pkt_flags;
1496 rx_pkts[nb_rx++] = rxm;
1498 rxq->rx_tail = rx_id;
1500 iavf_update_rx_tail(rxq, nb_hold, rx_id);
1505 /* implement recv_scattered_pkts for flexible Rx descriptor */
1507 iavf_recv_scattered_pkts_flex_rxd(void *rx_queue, struct rte_mbuf **rx_pkts,
1510 struct iavf_rx_queue *rxq = rx_queue;
1511 union iavf_rx_flex_desc rxd;
1512 struct rte_mbuf *rxe;
1513 struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1514 struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1515 struct rte_mbuf *nmb, *rxm;
1516 uint16_t rx_id = rxq->rx_tail;
1517 uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
1518 struct rte_eth_dev *dev;
1519 uint16_t rx_stat_err0;
1523 volatile union iavf_rx_desc *rx_ring = rxq->rx_ring;
1524 volatile union iavf_rx_flex_desc *rxdp;
1525 const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1527 while (nb_rx < nb_pkts) {
1528 rxdp = (volatile union iavf_rx_flex_desc *)&rx_ring[rx_id];
1529 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1531 /* Check the DD bit */
1532 if (!(rx_stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S)))
1534 IAVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
1536 nmb = rte_mbuf_raw_alloc(rxq->mp);
1537 if (unlikely(!nmb)) {
1538 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1539 "queue_id=%u", rxq->port_id, rxq->queue_id);
1540 dev = &rte_eth_devices[rxq->port_id];
1541 dev->data->rx_mbuf_alloc_failed++;
1547 rxe = rxq->sw_ring[rx_id];
1548 rxq->sw_ring[rx_id] = nmb;
1550 if (rx_id == rxq->nb_rx_desc)
1553 /* Prefetch next mbuf */
1554 rte_prefetch0(rxq->sw_ring[rx_id]);
1556 /* When next RX descriptor is on a cache line boundary,
1557 * prefetch the next 4 RX descriptors and next 8 pointers
1560 if ((rx_id & 0x3) == 0) {
1561 rte_prefetch0(&rx_ring[rx_id]);
1562 rte_prefetch0(rxq->sw_ring[rx_id]);
1567 rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1569 /* Set data buffer address and data length of the mbuf */
1570 rxdp->read.hdr_addr = 0;
1571 rxdp->read.pkt_addr = dma_addr;
1572 rx_packet_len = rte_le_to_cpu_16(rxd.wb.pkt_len) &
1573 IAVF_RX_FLX_DESC_PKT_LEN_M;
1574 rxm->data_len = rx_packet_len;
1575 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1577 /* If this is the first buffer of the received packet, set the
1578 * pointer to the first mbuf of the packet and initialize its
1579 * context. Otherwise, update the total length and the number
1580 * of segments of the current scattered packet, and update the
1581 * pointer to the last mbuf of the current packet.
1585 first_seg->nb_segs = 1;
1586 first_seg->pkt_len = rx_packet_len;
1588 first_seg->pkt_len =
1589 (uint16_t)(first_seg->pkt_len +
1591 first_seg->nb_segs++;
1592 last_seg->next = rxm;
1595 /* If this is not the last buffer of the received packet,
1596 * update the pointer to the last mbuf of the current scattered
1597 * packet and continue to parse the RX ring.
1599 if (!(rx_stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_EOF_S))) {
1604 /* This is the last buffer of the received packet. If the CRC
1605 * is not stripped by the hardware:
1606 * - Subtract the CRC length from the total packet length.
1607 * - If the last buffer only contains the whole CRC or a part
1608 * of it, free the mbuf associated to the last buffer. If part
1609 * of the CRC is also contained in the previous mbuf, subtract
1610 * the length of that CRC part from the data length of the
1614 if (unlikely(rxq->crc_len > 0)) {
1615 first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
1616 if (rx_packet_len <= RTE_ETHER_CRC_LEN) {
1617 rte_pktmbuf_free_seg(rxm);
1618 first_seg->nb_segs--;
1619 last_seg->data_len =
1620 (uint16_t)(last_seg->data_len -
1621 (RTE_ETHER_CRC_LEN - rx_packet_len));
1622 last_seg->next = NULL;
1624 rxm->data_len = (uint16_t)(rx_packet_len -
1629 first_seg->port = rxq->port_id;
1630 first_seg->ol_flags = 0;
1631 first_seg->packet_type = ptype_tbl[IAVF_RX_FLEX_DESC_PTYPE_M &
1632 rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
1633 iavf_flex_rxd_to_vlan_tci(first_seg, &rxd);
1634 iavf_flex_rxd_to_ipsec_crypto_status(first_seg, &rxd,
1635 &rxq->stats.ipsec_crypto);
1636 rxd_to_pkt_fields_ops[rxq->rxdid](rxq, first_seg, &rxd);
1637 pkt_flags = iavf_flex_rxd_error_to_pkt_flags(rx_stat_err0);
1639 first_seg->ol_flags |= pkt_flags;
1641 /* Prefetch data of first segment, if configured to do so. */
1642 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1643 first_seg->data_off));
1644 rx_pkts[nb_rx++] = first_seg;
1648 /* Record index of the next RX descriptor to probe. */
1649 rxq->rx_tail = rx_id;
1650 rxq->pkt_first_seg = first_seg;
1651 rxq->pkt_last_seg = last_seg;
1653 iavf_update_rx_tail(rxq, nb_hold, rx_id);
1658 /* implement recv_scattered_pkts */
1660 iavf_recv_scattered_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1663 struct iavf_rx_queue *rxq = rx_queue;
1664 union iavf_rx_desc rxd;
1665 struct rte_mbuf *rxe;
1666 struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1667 struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1668 struct rte_mbuf *nmb, *rxm;
1669 uint16_t rx_id = rxq->rx_tail;
1670 uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
1671 struct rte_eth_dev *dev;
1677 volatile union iavf_rx_desc *rx_ring = rxq->rx_ring;
1678 volatile union iavf_rx_desc *rxdp;
1679 const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1681 while (nb_rx < nb_pkts) {
1682 rxdp = &rx_ring[rx_id];
1683 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1684 rx_status = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
1685 IAVF_RXD_QW1_STATUS_SHIFT;
1687 /* Check the DD bit */
1688 if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)))
1690 IAVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
1692 nmb = rte_mbuf_raw_alloc(rxq->mp);
1693 if (unlikely(!nmb)) {
1694 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1695 "queue_id=%u", rxq->port_id, rxq->queue_id);
1696 dev = &rte_eth_devices[rxq->port_id];
1697 dev->data->rx_mbuf_alloc_failed++;
1703 rxe = rxq->sw_ring[rx_id];
1704 rxq->sw_ring[rx_id] = nmb;
1706 if (rx_id == rxq->nb_rx_desc)
1709 /* Prefetch next mbuf */
1710 rte_prefetch0(rxq->sw_ring[rx_id]);
1712 /* When next RX descriptor is on a cache line boundary,
1713 * prefetch the next 4 RX descriptors and next 8 pointers
1716 if ((rx_id & 0x3) == 0) {
1717 rte_prefetch0(&rx_ring[rx_id]);
1718 rte_prefetch0(rxq->sw_ring[rx_id]);
1723 rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1725 /* Set data buffer address and data length of the mbuf */
1726 rxdp->read.hdr_addr = 0;
1727 rxdp->read.pkt_addr = dma_addr;
1728 rx_packet_len = (qword1 & IAVF_RXD_QW1_LENGTH_PBUF_MASK) >>
1729 IAVF_RXD_QW1_LENGTH_PBUF_SHIFT;
1730 rxm->data_len = rx_packet_len;
1731 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1733 /* If this is the first buffer of the received packet, set the
1734 * pointer to the first mbuf of the packet and initialize its
1735 * context. Otherwise, update the total length and the number
1736 * of segments of the current scattered packet, and update the
1737 * pointer to the last mbuf of the current packet.
1741 first_seg->nb_segs = 1;
1742 first_seg->pkt_len = rx_packet_len;
1744 first_seg->pkt_len =
1745 (uint16_t)(first_seg->pkt_len +
1747 first_seg->nb_segs++;
1748 last_seg->next = rxm;
1751 /* If this is not the last buffer of the received packet,
1752 * update the pointer to the last mbuf of the current scattered
1753 * packet and continue to parse the RX ring.
1755 if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_EOF_SHIFT))) {
1760 /* This is the last buffer of the received packet. If the CRC
1761 * is not stripped by the hardware:
1762 * - Subtract the CRC length from the total packet length.
1763 * - If the last buffer only contains the whole CRC or a part
1764 * of it, free the mbuf associated to the last buffer. If part
1765 * of the CRC is also contained in the previous mbuf, subtract
1766 * the length of that CRC part from the data length of the
1770 if (unlikely(rxq->crc_len > 0)) {
1771 first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
1772 if (rx_packet_len <= RTE_ETHER_CRC_LEN) {
1773 rte_pktmbuf_free_seg(rxm);
1774 first_seg->nb_segs--;
1775 last_seg->data_len =
1776 (uint16_t)(last_seg->data_len -
1777 (RTE_ETHER_CRC_LEN - rx_packet_len));
1778 last_seg->next = NULL;
1780 rxm->data_len = (uint16_t)(rx_packet_len -
1784 first_seg->port = rxq->port_id;
1785 first_seg->ol_flags = 0;
1786 iavf_rxd_to_vlan_tci(first_seg, &rxd);
1787 pkt_flags = iavf_rxd_to_pkt_flags(qword1);
1788 first_seg->packet_type =
1789 ptype_tbl[(uint8_t)((qword1 &
1790 IAVF_RXD_QW1_PTYPE_MASK) >> IAVF_RXD_QW1_PTYPE_SHIFT)];
1792 if (pkt_flags & RTE_MBUF_F_RX_RSS_HASH)
1793 first_seg->hash.rss =
1794 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1796 if (pkt_flags & RTE_MBUF_F_RX_FDIR)
1797 pkt_flags |= iavf_rxd_build_fdir(&rxd, first_seg);
1799 first_seg->ol_flags |= pkt_flags;
1801 /* Prefetch data of first segment, if configured to do so. */
1802 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1803 first_seg->data_off));
1804 rx_pkts[nb_rx++] = first_seg;
1808 /* Record index of the next RX descriptor to probe. */
1809 rxq->rx_tail = rx_id;
1810 rxq->pkt_first_seg = first_seg;
1811 rxq->pkt_last_seg = last_seg;
1813 iavf_update_rx_tail(rxq, nb_hold, rx_id);
1818 #define IAVF_LOOK_AHEAD 8
1820 iavf_rx_scan_hw_ring_flex_rxd(struct iavf_rx_queue *rxq,
1821 struct rte_mbuf **rx_pkts,
1824 volatile union iavf_rx_flex_desc *rxdp;
1825 struct rte_mbuf **rxep;
1826 struct rte_mbuf *mb;
1829 int32_t s[IAVF_LOOK_AHEAD], var, nb_dd;
1830 int32_t i, j, nb_rx = 0;
1831 int32_t nb_staged = 0;
1833 const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1835 rxdp = (volatile union iavf_rx_flex_desc *)&rxq->rx_ring[rxq->rx_tail];
1836 rxep = &rxq->sw_ring[rxq->rx_tail];
1838 stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1840 /* Make sure there is at least 1 packet to receive */
1841 if (!(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S)))
1844 /* Scan LOOK_AHEAD descriptors at a time to determine which
1845 * descriptors reference packets that are ready to be received.
1847 for (i = 0; i < IAVF_RX_MAX_BURST; i += IAVF_LOOK_AHEAD,
1848 rxdp += IAVF_LOOK_AHEAD, rxep += IAVF_LOOK_AHEAD) {
1849 /* Read desc statuses backwards to avoid race condition */
1850 for (j = IAVF_LOOK_AHEAD - 1; j >= 0; j--)
1851 s[j] = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1853 /* This barrier is to order loads of different words in the descriptor */
1854 rte_atomic_thread_fence(__ATOMIC_ACQUIRE);
1856 /* Compute how many contiguous DD bits were set */
1857 for (j = 0, nb_dd = 0; j < IAVF_LOOK_AHEAD; j++) {
1858 var = s[j] & (1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S);
1860 /* For Arm platforms, count only contiguous descriptors
1861 * whose DD bit is set to 1. On Arm platforms, reads of
1862 * descriptors can be reordered. Since the CPU may
1863 * be reading the descriptors as the NIC updates them
1864 * in memory, it is possbile that the DD bit for a
1865 * descriptor earlier in the queue is read as not set
1866 * while the DD bit for a descriptor later in the queue
1878 /* Translate descriptor info to mbuf parameters */
1879 for (j = 0; j < nb_dd; j++) {
1880 IAVF_DUMP_RX_DESC(rxq, &rxdp[j],
1882 i * IAVF_LOOK_AHEAD + j);
1885 pkt_len = (rte_le_to_cpu_16(rxdp[j].wb.pkt_len) &
1886 IAVF_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
1887 mb->data_len = pkt_len;
1888 mb->pkt_len = pkt_len;
1891 mb->packet_type = ptype_tbl[IAVF_RX_FLEX_DESC_PTYPE_M &
1892 rte_le_to_cpu_16(rxdp[j].wb.ptype_flex_flags0)];
1893 iavf_flex_rxd_to_vlan_tci(mb, &rxdp[j]);
1894 iavf_flex_rxd_to_ipsec_crypto_status(mb, &rxdp[j],
1895 &rxq->stats.ipsec_crypto);
1896 rxd_to_pkt_fields_ops[rxq->rxdid](rxq, mb, &rxdp[j]);
1897 stat_err0 = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1898 pkt_flags = iavf_flex_rxd_error_to_pkt_flags(stat_err0);
1900 mb->ol_flags |= pkt_flags;
1902 /* Put up to nb_pkts directly into buffers */
1903 if ((i + j) < nb_pkts) {
1904 rx_pkts[i + j] = rxep[j];
1907 /* Stage excess pkts received */
1908 rxq->rx_stage[nb_staged] = rxep[j];
1913 if (nb_dd != IAVF_LOOK_AHEAD)
1917 /* Update rxq->rx_nb_avail to reflect number of staged pkts */
1918 rxq->rx_nb_avail = nb_staged;
1920 /* Clear software ring entries */
1921 for (i = 0; i < (nb_rx + nb_staged); i++)
1922 rxq->sw_ring[rxq->rx_tail + i] = NULL;
1928 iavf_rx_scan_hw_ring(struct iavf_rx_queue *rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1930 volatile union iavf_rx_desc *rxdp;
1931 struct rte_mbuf **rxep;
1932 struct rte_mbuf *mb;
1936 int32_t s[IAVF_LOOK_AHEAD], var, nb_dd;
1937 int32_t i, j, nb_rx = 0;
1938 int32_t nb_staged = 0;
1940 const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1942 rxdp = &rxq->rx_ring[rxq->rx_tail];
1943 rxep = &rxq->sw_ring[rxq->rx_tail];
1945 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1946 rx_status = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
1947 IAVF_RXD_QW1_STATUS_SHIFT;
1949 /* Make sure there is at least 1 packet to receive */
1950 if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)))
1953 /* Scan LOOK_AHEAD descriptors at a time to determine which
1954 * descriptors reference packets that are ready to be received.
1956 for (i = 0; i < IAVF_RX_MAX_BURST; i += IAVF_LOOK_AHEAD,
1957 rxdp += IAVF_LOOK_AHEAD, rxep += IAVF_LOOK_AHEAD) {
1958 /* Read desc statuses backwards to avoid race condition */
1959 for (j = IAVF_LOOK_AHEAD - 1; j >= 0; j--) {
1960 qword1 = rte_le_to_cpu_64(
1961 rxdp[j].wb.qword1.status_error_len);
1962 s[j] = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
1963 IAVF_RXD_QW1_STATUS_SHIFT;
1966 /* This barrier is to order loads of different words in the descriptor */
1967 rte_atomic_thread_fence(__ATOMIC_ACQUIRE);
1969 /* Compute how many contiguous DD bits were set */
1970 for (j = 0, nb_dd = 0; j < IAVF_LOOK_AHEAD; j++) {
1971 var = s[j] & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT);
1973 /* For Arm platforms, count only contiguous descriptors
1974 * whose DD bit is set to 1. On Arm platforms, reads of
1975 * descriptors can be reordered. Since the CPU may
1976 * be reading the descriptors as the NIC updates them
1977 * in memory, it is possbile that the DD bit for a
1978 * descriptor earlier in the queue is read as not set
1979 * while the DD bit for a descriptor later in the queue
1991 /* Translate descriptor info to mbuf parameters */
1992 for (j = 0; j < nb_dd; j++) {
1993 IAVF_DUMP_RX_DESC(rxq, &rxdp[j],
1994 rxq->rx_tail + i * IAVF_LOOK_AHEAD + j);
1997 qword1 = rte_le_to_cpu_64
1998 (rxdp[j].wb.qword1.status_error_len);
1999 pkt_len = ((qword1 & IAVF_RXD_QW1_LENGTH_PBUF_MASK) >>
2000 IAVF_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
2001 mb->data_len = pkt_len;
2002 mb->pkt_len = pkt_len;
2004 iavf_rxd_to_vlan_tci(mb, &rxdp[j]);
2005 pkt_flags = iavf_rxd_to_pkt_flags(qword1);
2007 ptype_tbl[(uint8_t)((qword1 &
2008 IAVF_RXD_QW1_PTYPE_MASK) >>
2009 IAVF_RXD_QW1_PTYPE_SHIFT)];
2011 if (pkt_flags & RTE_MBUF_F_RX_RSS_HASH)
2012 mb->hash.rss = rte_le_to_cpu_32(
2013 rxdp[j].wb.qword0.hi_dword.rss);
2015 if (pkt_flags & RTE_MBUF_F_RX_FDIR)
2016 pkt_flags |= iavf_rxd_build_fdir(&rxdp[j], mb);
2018 mb->ol_flags |= pkt_flags;
2020 /* Put up to nb_pkts directly into buffers */
2021 if ((i + j) < nb_pkts) {
2022 rx_pkts[i + j] = rxep[j];
2024 } else { /* Stage excess pkts received */
2025 rxq->rx_stage[nb_staged] = rxep[j];
2030 if (nb_dd != IAVF_LOOK_AHEAD)
2034 /* Update rxq->rx_nb_avail to reflect number of staged pkts */
2035 rxq->rx_nb_avail = nb_staged;
2037 /* Clear software ring entries */
2038 for (i = 0; i < (nb_rx + nb_staged); i++)
2039 rxq->sw_ring[rxq->rx_tail + i] = NULL;
2044 static inline uint16_t
2045 iavf_rx_fill_from_stage(struct iavf_rx_queue *rxq,
2046 struct rte_mbuf **rx_pkts,
2050 struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
2052 nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
2054 for (i = 0; i < nb_pkts; i++)
2055 rx_pkts[i] = stage[i];
2057 rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
2058 rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
2064 iavf_rx_alloc_bufs(struct iavf_rx_queue *rxq)
2066 volatile union iavf_rx_desc *rxdp;
2067 struct rte_mbuf **rxep;
2068 struct rte_mbuf *mb;
2069 uint16_t alloc_idx, i;
2073 /* Allocate buffers in bulk */
2074 alloc_idx = (uint16_t)(rxq->rx_free_trigger -
2075 (rxq->rx_free_thresh - 1));
2076 rxep = &rxq->sw_ring[alloc_idx];
2077 diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
2078 rxq->rx_free_thresh);
2079 if (unlikely(diag != 0)) {
2080 PMD_RX_LOG(ERR, "Failed to get mbufs in bulk");
2084 rxdp = &rxq->rx_ring[alloc_idx];
2085 for (i = 0; i < rxq->rx_free_thresh; i++) {
2086 if (likely(i < (rxq->rx_free_thresh - 1)))
2087 /* Prefetch next mbuf */
2088 rte_prefetch0(rxep[i + 1]);
2091 rte_mbuf_refcnt_set(mb, 1);
2093 mb->data_off = RTE_PKTMBUF_HEADROOM;
2095 mb->port = rxq->port_id;
2096 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mb));
2097 rxdp[i].read.hdr_addr = 0;
2098 rxdp[i].read.pkt_addr = dma_addr;
2101 /* Update rx tail register */
2103 IAVF_PCI_REG_WC_WRITE_RELAXED(rxq->qrx_tail, rxq->rx_free_trigger);
2105 rxq->rx_free_trigger =
2106 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
2107 if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
2108 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2113 static inline uint16_t
2114 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
2116 struct iavf_rx_queue *rxq = (struct iavf_rx_queue *)rx_queue;
2122 if (rxq->rx_nb_avail)
2123 return iavf_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
2125 if (rxq->rxdid >= IAVF_RXDID_FLEX_NIC && rxq->rxdid <= IAVF_RXDID_LAST)
2126 nb_rx = (uint16_t)iavf_rx_scan_hw_ring_flex_rxd(rxq, rx_pkts, nb_pkts);
2128 nb_rx = (uint16_t)iavf_rx_scan_hw_ring(rxq, rx_pkts, nb_pkts);
2130 rxq->rx_next_avail = 0;
2131 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx + rxq->rx_nb_avail);
2133 if (rxq->rx_tail > rxq->rx_free_trigger) {
2134 if (iavf_rx_alloc_bufs(rxq) != 0) {
2135 uint16_t i, j, nb_staged;
2137 /* TODO: count rx_mbuf_alloc_failed here */
2139 nb_staged = rxq->rx_nb_avail;
2140 rxq->rx_nb_avail = 0;
2142 rxq->rx_tail = (uint16_t)(rxq->rx_tail - (nb_rx + nb_staged));
2143 for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++) {
2144 rxq->sw_ring[j] = rx_pkts[i];
2147 for (i = 0, j = rxq->rx_tail + nb_rx; i < nb_staged; i++, j++) {
2148 rxq->sw_ring[j] = rxq->rx_stage[i];
2156 if (rxq->rx_tail >= rxq->nb_rx_desc)
2159 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u, nb_rx=%u",
2160 rxq->port_id, rxq->queue_id,
2161 rxq->rx_tail, nb_rx);
2167 iavf_recv_pkts_bulk_alloc(void *rx_queue,
2168 struct rte_mbuf **rx_pkts,
2171 uint16_t nb_rx = 0, n, count;
2173 if (unlikely(nb_pkts == 0))
2176 if (likely(nb_pkts <= IAVF_RX_MAX_BURST))
2177 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
2180 n = RTE_MIN(nb_pkts, IAVF_RX_MAX_BURST);
2181 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
2182 nb_rx = (uint16_t)(nb_rx + count);
2183 nb_pkts = (uint16_t)(nb_pkts - count);
2192 iavf_xmit_cleanup(struct iavf_tx_queue *txq)
2194 struct iavf_tx_entry *sw_ring = txq->sw_ring;
2195 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
2196 uint16_t nb_tx_desc = txq->nb_tx_desc;
2197 uint16_t desc_to_clean_to;
2198 uint16_t nb_tx_to_clean;
2200 volatile struct iavf_tx_desc *txd = txq->tx_ring;
2202 desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->rs_thresh);
2203 if (desc_to_clean_to >= nb_tx_desc)
2204 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
2206 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
2207 if ((txd[desc_to_clean_to].cmd_type_offset_bsz &
2208 rte_cpu_to_le_64(IAVF_TXD_QW1_DTYPE_MASK)) !=
2209 rte_cpu_to_le_64(IAVF_TX_DESC_DTYPE_DESC_DONE)) {
2210 PMD_TX_LOG(DEBUG, "TX descriptor %4u is not done "
2211 "(port=%d queue=%d)", desc_to_clean_to,
2212 txq->port_id, txq->queue_id);
2216 if (last_desc_cleaned > desc_to_clean_to)
2217 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
2220 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
2223 txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
2225 txq->last_desc_cleaned = desc_to_clean_to;
2226 txq->nb_free = (uint16_t)(txq->nb_free + nb_tx_to_clean);
2231 /* Check if the context descriptor is needed for TX offloading */
2232 static inline uint16_t
2233 iavf_calc_context_desc(uint64_t flags, uint8_t vlan_flag)
2235 if (flags & (RTE_MBUF_F_TX_TCP_SEG | RTE_MBUF_F_TX_UDP_SEG |
2236 RTE_MBUF_F_TX_TUNNEL_MASK))
2238 if (flags & RTE_MBUF_F_TX_VLAN &&
2239 vlan_flag & IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG2)
2245 iavf_fill_ctx_desc_cmd_field(volatile uint64_t *field, struct rte_mbuf *m,
2251 if (m->ol_flags & (RTE_MBUF_F_TX_TCP_SEG | RTE_MBUF_F_TX_UDP_SEG))
2252 cmd = IAVF_TX_CTX_DESC_TSO << IAVF_TXD_CTX_QW1_CMD_SHIFT;
2254 if (m->ol_flags & RTE_MBUF_F_TX_VLAN &&
2255 vlan_flag & IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG2) {
2256 cmd |= IAVF_TX_CTX_DESC_IL2TAG2
2257 << IAVF_TXD_CTX_QW1_CMD_SHIFT;
2264 iavf_fill_ctx_desc_ipsec_field(volatile uint64_t *field,
2265 struct iavf_ipsec_crypto_pkt_metadata *ipsec_md)
2267 uint64_t ipsec_field =
2268 (uint64_t)ipsec_md->ctx_desc_ipsec_params <<
2269 IAVF_TXD_CTX_QW1_IPSEC_PARAMS_CIPHERBLK_SHIFT;
2271 *field |= ipsec_field;
2276 iavf_fill_ctx_desc_tunnelling_field(volatile uint64_t *qw0,
2277 const struct rte_mbuf *m)
2279 uint64_t eip_typ = IAVF_TX_CTX_DESC_EIPT_NONE;
2280 uint64_t eip_len = 0;
2281 uint64_t eip_noinc = 0;
2282 /* Default - IP_ID is increment in each segment of LSO */
2284 switch (m->ol_flags & (RTE_MBUF_F_TX_OUTER_IPV4 |
2285 RTE_MBUF_F_TX_OUTER_IPV6 |
2286 RTE_MBUF_F_TX_OUTER_IP_CKSUM)) {
2287 case RTE_MBUF_F_TX_OUTER_IPV4:
2288 eip_typ = IAVF_TX_CTX_DESC_EIPT_IPV4_NO_CHECKSUM_OFFLOAD;
2289 eip_len = m->outer_l3_len >> 2;
2291 case RTE_MBUF_F_TX_OUTER_IPV4 | RTE_MBUF_F_TX_OUTER_IP_CKSUM:
2292 eip_typ = IAVF_TX_CTX_DESC_EIPT_IPV4_CHECKSUM_OFFLOAD;
2293 eip_len = m->outer_l3_len >> 2;
2295 case RTE_MBUF_F_TX_OUTER_IPV6:
2296 eip_typ = IAVF_TX_CTX_DESC_EIPT_IPV6;
2297 eip_len = m->outer_l3_len >> 2;
2301 *qw0 = eip_typ << IAVF_TXD_CTX_QW0_TUN_PARAMS_EIPT_SHIFT |
2302 eip_len << IAVF_TXD_CTX_QW0_TUN_PARAMS_EIPLEN_SHIFT |
2303 eip_noinc << IAVF_TXD_CTX_QW0_TUN_PARAMS_EIP_NOINC_SHIFT;
2306 static inline uint16_t
2307 iavf_fill_ctx_desc_segmentation_field(volatile uint64_t *field,
2308 struct rte_mbuf *m, struct iavf_ipsec_crypto_pkt_metadata *ipsec_md)
2310 uint64_t segmentation_field = 0;
2311 uint64_t total_length = 0;
2313 if (m->ol_flags & RTE_MBUF_F_TX_SEC_OFFLOAD) {
2314 total_length = ipsec_md->l4_payload_len;
2316 total_length = m->pkt_len - (m->l2_len + m->l3_len + m->l4_len);
2318 if (m->ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK)
2319 total_length -= m->outer_l3_len;
2322 #ifdef RTE_LIBRTE_IAVF_DEBUG_TX
2323 if (!m->l4_len || !m->tso_segsz)
2324 PMD_TX_LOG(DEBUG, "L4 length %d, LSO Segment size %d",
2325 m->l4_len, m->tso_segsz);
2326 if (m->tso_segsz < 88)
2327 PMD_TX_LOG(DEBUG, "LSO Segment size %d is less than minimum %d",
2330 segmentation_field =
2331 (((uint64_t)total_length << IAVF_TXD_CTX_QW1_TSO_LEN_SHIFT) &
2332 IAVF_TXD_CTX_QW1_TSO_LEN_MASK) |
2333 (((uint64_t)m->tso_segsz << IAVF_TXD_CTX_QW1_MSS_SHIFT) &
2334 IAVF_TXD_CTX_QW1_MSS_MASK);
2336 *field |= segmentation_field;
2338 return total_length;
2342 struct iavf_tx_context_desc_qws {
2348 iavf_fill_context_desc(volatile struct iavf_tx_context_desc *desc,
2349 struct rte_mbuf *m, struct iavf_ipsec_crypto_pkt_metadata *ipsec_md,
2350 uint16_t *tlen, uint8_t vlan_flag)
2352 volatile struct iavf_tx_context_desc_qws *desc_qws =
2353 (volatile struct iavf_tx_context_desc_qws *)desc;
2354 /* fill descriptor type field */
2355 desc_qws->qw1 = IAVF_TX_DESC_DTYPE_CONTEXT;
2357 /* fill command field */
2358 iavf_fill_ctx_desc_cmd_field(&desc_qws->qw1, m, vlan_flag);
2360 /* fill segmentation field */
2361 if (m->ol_flags & (RTE_MBUF_F_TX_TCP_SEG | RTE_MBUF_F_TX_UDP_SEG)) {
2362 /* fill IPsec field */
2363 if (m->ol_flags & RTE_MBUF_F_TX_SEC_OFFLOAD)
2364 iavf_fill_ctx_desc_ipsec_field(&desc_qws->qw1,
2367 *tlen = iavf_fill_ctx_desc_segmentation_field(&desc_qws->qw1,
2371 /* fill tunnelling field */
2372 if (m->ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK)
2373 iavf_fill_ctx_desc_tunnelling_field(&desc_qws->qw0, m);
2377 desc_qws->qw0 = rte_cpu_to_le_64(desc_qws->qw0);
2378 desc_qws->qw1 = rte_cpu_to_le_64(desc_qws->qw1);
2380 if (vlan_flag & IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG2)
2381 desc->l2tag2 = m->vlan_tci;
2386 iavf_fill_ipsec_desc(volatile struct iavf_tx_ipsec_desc *desc,
2387 const struct iavf_ipsec_crypto_pkt_metadata *md, uint16_t *ipsec_len)
2389 desc->qw0 = rte_cpu_to_le_64(((uint64_t)md->l4_payload_len <<
2390 IAVF_IPSEC_TX_DESC_QW0_L4PAYLEN_SHIFT) |
2391 ((uint64_t)md->esn << IAVF_IPSEC_TX_DESC_QW0_IPSECESN_SHIFT) |
2392 ((uint64_t)md->esp_trailer_len <<
2393 IAVF_IPSEC_TX_DESC_QW0_TRAILERLEN_SHIFT));
2395 desc->qw1 = rte_cpu_to_le_64(((uint64_t)md->sa_idx <<
2396 IAVF_IPSEC_TX_DESC_QW1_IPSECSA_SHIFT) |
2397 ((uint64_t)md->next_proto <<
2398 IAVF_IPSEC_TX_DESC_QW1_IPSECNH_SHIFT) |
2399 ((uint64_t)(md->len_iv & 0x3) <<
2400 IAVF_IPSEC_TX_DESC_QW1_IVLEN_SHIFT) |
2401 ((uint64_t)(md->ol_flags & IAVF_IPSEC_CRYPTO_OL_FLAGS_NATT ?
2403 IAVF_IPSEC_TX_DESC_QW1_UDP_SHIFT) |
2404 (uint64_t)IAVF_TX_DESC_DTYPE_IPSEC);
2407 * TODO: Pre-calculate this in the Session initialization
2409 * Calculate IPsec length required in data descriptor func when TSO
2410 * offload is enabled
2412 *ipsec_len = sizeof(struct rte_esp_hdr) + (md->len_iv >> 2) +
2413 (md->ol_flags & IAVF_IPSEC_CRYPTO_OL_FLAGS_NATT ?
2414 sizeof(struct rte_udp_hdr) : 0);
2418 iavf_build_data_desc_cmd_offset_fields(volatile uint64_t *qw1,
2419 struct rte_mbuf *m, uint8_t vlan_flag)
2421 uint64_t command = 0;
2422 uint64_t offset = 0;
2423 uint64_t l2tag1 = 0;
2425 *qw1 = IAVF_TX_DESC_DTYPE_DATA;
2427 command = (uint64_t)IAVF_TX_DESC_CMD_ICRC;
2429 /* Descriptor based VLAN insertion */
2430 if ((vlan_flag & IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG1) &&
2431 m->ol_flags & RTE_MBUF_F_TX_VLAN) {
2432 command |= (uint64_t)IAVF_TX_DESC_CMD_IL2TAG1;
2433 l2tag1 |= m->vlan_tci;
2437 offset |= (m->l2_len >> 1) << IAVF_TX_DESC_LENGTH_MACLEN_SHIFT;
2439 /* Enable L3 checksum offloading inner */
2440 if (m->ol_flags & (RTE_MBUF_F_TX_IP_CKSUM | RTE_MBUF_F_TX_IPV4)) {
2441 command |= IAVF_TX_DESC_CMD_IIPT_IPV4_CSUM;
2442 offset |= (m->l3_len >> 2) << IAVF_TX_DESC_LENGTH_IPLEN_SHIFT;
2443 } else if (m->ol_flags & RTE_MBUF_F_TX_IPV4) {
2444 command |= IAVF_TX_DESC_CMD_IIPT_IPV4;
2445 offset |= (m->l3_len >> 2) << IAVF_TX_DESC_LENGTH_IPLEN_SHIFT;
2446 } else if (m->ol_flags & RTE_MBUF_F_TX_IPV6) {
2447 command |= IAVF_TX_DESC_CMD_IIPT_IPV6;
2448 offset |= (m->l3_len >> 2) << IAVF_TX_DESC_LENGTH_IPLEN_SHIFT;
2451 if (m->ol_flags & RTE_MBUF_F_TX_TCP_SEG) {
2452 command |= IAVF_TX_DESC_CMD_L4T_EOFT_TCP;
2453 offset |= (m->l4_len >> 2) <<
2454 IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2457 /* Enable L4 checksum offloads */
2458 switch (m->ol_flags & RTE_MBUF_F_TX_L4_MASK) {
2459 case RTE_MBUF_F_TX_TCP_CKSUM:
2460 command |= IAVF_TX_DESC_CMD_L4T_EOFT_TCP;
2461 offset |= (sizeof(struct rte_tcp_hdr) >> 2) <<
2462 IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2464 case RTE_MBUF_F_TX_SCTP_CKSUM:
2465 command |= IAVF_TX_DESC_CMD_L4T_EOFT_SCTP;
2466 offset |= (sizeof(struct rte_sctp_hdr) >> 2) <<
2467 IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2469 case RTE_MBUF_F_TX_UDP_CKSUM:
2470 command |= IAVF_TX_DESC_CMD_L4T_EOFT_UDP;
2471 offset |= (sizeof(struct rte_udp_hdr) >> 2) <<
2472 IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2476 *qw1 = rte_cpu_to_le_64((((uint64_t)command <<
2477 IAVF_TXD_DATA_QW1_CMD_SHIFT) & IAVF_TXD_DATA_QW1_CMD_MASK) |
2478 (((uint64_t)offset << IAVF_TXD_DATA_QW1_OFFSET_SHIFT) &
2479 IAVF_TXD_DATA_QW1_OFFSET_MASK) |
2480 ((uint64_t)l2tag1 << IAVF_TXD_DATA_QW1_L2TAG1_SHIFT));
2484 iavf_fill_data_desc(volatile struct iavf_tx_desc *desc,
2485 struct rte_mbuf *m, uint64_t desc_template,
2486 uint16_t tlen, uint16_t ipseclen)
2488 uint32_t hdrlen = m->l2_len;
2491 /* fill data descriptor qw1 from template */
2492 desc->cmd_type_offset_bsz = desc_template;
2494 /* set data buffer address */
2495 desc->buffer_addr = rte_mbuf_data_iova(m);
2497 /* calculate data buffer size less set header lengths */
2498 if ((m->ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK) &&
2499 (m->ol_flags & (RTE_MBUF_F_TX_TCP_SEG |
2500 RTE_MBUF_F_TX_UDP_SEG))) {
2501 hdrlen += m->outer_l3_len;
2502 if (m->ol_flags & RTE_MBUF_F_TX_L4_MASK)
2503 hdrlen += m->l3_len + m->l4_len;
2505 hdrlen += m->l3_len;
2506 if (m->ol_flags & RTE_MBUF_F_TX_SEC_OFFLOAD)
2508 bufsz = hdrlen + tlen;
2509 } else if ((m->ol_flags & RTE_MBUF_F_TX_SEC_OFFLOAD) &&
2510 (m->ol_flags & (RTE_MBUF_F_TX_TCP_SEG |
2511 RTE_MBUF_F_TX_UDP_SEG))) {
2512 hdrlen += m->outer_l3_len + m->l3_len + ipseclen;
2513 if (m->ol_flags & RTE_MBUF_F_TX_L4_MASK)
2514 hdrlen += m->l4_len;
2515 bufsz = hdrlen + tlen;
2518 bufsz = m->data_len;
2521 /* set data buffer size */
2522 desc->cmd_type_offset_bsz |=
2523 (((uint64_t)bufsz << IAVF_TXD_DATA_QW1_TX_BUF_SZ_SHIFT) &
2524 IAVF_TXD_DATA_QW1_TX_BUF_SZ_MASK);
2526 desc->buffer_addr = rte_cpu_to_le_64(desc->buffer_addr);
2527 desc->cmd_type_offset_bsz = rte_cpu_to_le_64(desc->cmd_type_offset_bsz);
2531 static struct iavf_ipsec_crypto_pkt_metadata *
2532 iavf_ipsec_crypto_get_pkt_metadata(const struct iavf_tx_queue *txq,
2535 if (m->ol_flags & RTE_MBUF_F_TX_SEC_OFFLOAD)
2536 return RTE_MBUF_DYNFIELD(m, txq->ipsec_crypto_pkt_md_offset,
2537 struct iavf_ipsec_crypto_pkt_metadata *);
2544 iavf_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2546 struct iavf_tx_queue *txq = tx_queue;
2547 volatile struct iavf_tx_desc *txr = txq->tx_ring;
2548 struct iavf_tx_entry *txe_ring = txq->sw_ring;
2549 struct iavf_tx_entry *txe, *txn;
2550 struct rte_mbuf *mb, *mb_seg;
2551 uint16_t desc_idx, desc_idx_last;
2555 /* Check if the descriptor ring needs to be cleaned. */
2556 if (txq->nb_free < txq->free_thresh)
2557 iavf_xmit_cleanup(txq);
2559 desc_idx = txq->tx_tail;
2560 txe = &txe_ring[desc_idx];
2562 #ifdef RTE_LIBRTE_IAVF_DEBUG_TX_DESC_RING
2563 iavf_dump_tx_entry_ring(txq);
2564 iavf_dump_tx_desc_ring(txq);
2568 for (idx = 0; idx < nb_pkts; idx++) {
2569 volatile struct iavf_tx_desc *ddesc;
2570 struct iavf_ipsec_crypto_pkt_metadata *ipsec_md;
2572 uint16_t nb_desc_ctx, nb_desc_ipsec;
2573 uint16_t nb_desc_data, nb_desc_required;
2574 uint16_t tlen = 0, ipseclen = 0;
2575 uint64_t ddesc_template = 0;
2576 uint64_t ddesc_cmd = 0;
2580 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
2583 * Get metadata for ipsec crypto from mbuf dynamic fields if
2584 * security offload is specified.
2586 ipsec_md = iavf_ipsec_crypto_get_pkt_metadata(txq, mb);
2588 nb_desc_data = mb->nb_segs;
2590 iavf_calc_context_desc(mb->ol_flags, txq->vlan_flag);
2591 nb_desc_ipsec = !!(mb->ol_flags & RTE_MBUF_F_TX_SEC_OFFLOAD);
2594 * The number of descriptors that must be allocated for
2595 * a packet equals to the number of the segments of that
2596 * packet plus the context and ipsec descriptors if needed.
2598 nb_desc_required = nb_desc_data + nb_desc_ctx + nb_desc_ipsec;
2600 desc_idx_last = (uint16_t)(desc_idx + nb_desc_required - 1);
2602 /* wrap descriptor ring */
2603 if (desc_idx_last >= txq->nb_tx_desc)
2605 (uint16_t)(desc_idx_last - txq->nb_tx_desc);
2608 "port_id=%u queue_id=%u tx_first=%u tx_last=%u",
2609 txq->port_id, txq->queue_id, desc_idx, desc_idx_last);
2611 if (nb_desc_required > txq->nb_free) {
2612 if (iavf_xmit_cleanup(txq)) {
2617 if (unlikely(nb_desc_required > txq->rs_thresh)) {
2618 while (nb_desc_required > txq->nb_free) {
2619 if (iavf_xmit_cleanup(txq)) {
2628 iavf_build_data_desc_cmd_offset_fields(&ddesc_template, mb,
2631 /* Setup TX context descriptor if required */
2633 volatile struct iavf_tx_context_desc *ctx_desc =
2634 (volatile struct iavf_tx_context_desc *)
2637 /* clear QW0 or the previous writeback value
2638 * may impact next write
2640 *(volatile uint64_t *)ctx_desc = 0;
2642 txn = &txe_ring[txe->next_id];
2643 RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
2646 rte_pktmbuf_free_seg(txe->mbuf);
2650 iavf_fill_context_desc(ctx_desc, mb, ipsec_md, &tlen,
2652 IAVF_DUMP_TX_DESC(txq, ctx_desc, desc_idx);
2654 txe->last_id = desc_idx_last;
2655 desc_idx = txe->next_id;
2659 if (nb_desc_ipsec) {
2660 volatile struct iavf_tx_ipsec_desc *ipsec_desc =
2661 (volatile struct iavf_tx_ipsec_desc *)
2664 txn = &txe_ring[txe->next_id];
2665 RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
2668 rte_pktmbuf_free_seg(txe->mbuf);
2672 iavf_fill_ipsec_desc(ipsec_desc, ipsec_md, &ipseclen);
2674 IAVF_DUMP_TX_DESC(txq, ipsec_desc, desc_idx);
2676 txe->last_id = desc_idx_last;
2677 desc_idx = txe->next_id;
2684 ddesc = (volatile struct iavf_tx_desc *)
2687 txn = &txe_ring[txe->next_id];
2688 RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
2691 rte_pktmbuf_free_seg(txe->mbuf);
2694 iavf_fill_data_desc(ddesc, mb_seg,
2695 ddesc_template, tlen, ipseclen);
2697 IAVF_DUMP_TX_DESC(txq, ddesc, desc_idx);
2699 txe->last_id = desc_idx_last;
2700 desc_idx = txe->next_id;
2702 mb_seg = mb_seg->next;
2705 /* The last packet data descriptor needs End Of Packet (EOP) */
2706 ddesc_cmd = IAVF_TX_DESC_CMD_EOP;
2708 txq->nb_used = (uint16_t)(txq->nb_used + nb_desc_required);
2709 txq->nb_free = (uint16_t)(txq->nb_free - nb_desc_required);
2711 if (txq->nb_used >= txq->rs_thresh) {
2712 PMD_TX_LOG(DEBUG, "Setting RS bit on TXD id="
2713 "%4u (port=%d queue=%d)",
2714 desc_idx_last, txq->port_id, txq->queue_id);
2716 ddesc_cmd |= IAVF_TX_DESC_CMD_RS;
2718 /* Update txq RS bit counters */
2722 ddesc->cmd_type_offset_bsz |= rte_cpu_to_le_64(ddesc_cmd <<
2723 IAVF_TXD_DATA_QW1_CMD_SHIFT);
2725 IAVF_DUMP_TX_DESC(txq, ddesc, desc_idx - 1);
2731 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
2732 txq->port_id, txq->queue_id, desc_idx, idx);
2734 IAVF_PCI_REG_WRITE_RELAXED(txq->qtx_tail, desc_idx);
2735 txq->tx_tail = desc_idx;
2740 /* Check if the packet with vlan user priority is transmitted in the
2744 iavf_check_vlan_up2tc(struct iavf_tx_queue *txq, struct rte_mbuf *m)
2746 struct rte_eth_dev *dev = &rte_eth_devices[txq->port_id];
2747 struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2750 up = m->vlan_tci >> IAVF_VLAN_TAG_PCP_OFFSET;
2752 if (!(vf->qos_cap->cap[txq->tc].tc_prio & BIT(up))) {
2753 PMD_TX_LOG(ERR, "packet with vlan pcp %u cannot transmit in queue %u\n",
2761 /* TX prep functions */
2763 iavf_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
2769 struct iavf_tx_queue *txq = tx_queue;
2770 struct rte_eth_dev *dev = &rte_eth_devices[txq->port_id];
2771 struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2773 for (i = 0; i < nb_pkts; i++) {
2775 ol_flags = m->ol_flags;
2777 /* Check condition for nb_segs > IAVF_TX_MAX_MTU_SEG. */
2778 if (!(ol_flags & RTE_MBUF_F_TX_TCP_SEG)) {
2779 if (m->nb_segs > IAVF_TX_MAX_MTU_SEG) {
2783 } else if ((m->tso_segsz < IAVF_MIN_TSO_MSS) ||
2784 (m->tso_segsz > IAVF_MAX_TSO_MSS)) {
2785 /* MSS outside the range are considered malicious */
2790 if (ol_flags & IAVF_TX_OFFLOAD_NOTSUP_MASK) {
2791 rte_errno = ENOTSUP;
2795 #ifdef RTE_ETHDEV_DEBUG_TX
2796 ret = rte_validate_tx_offload(m);
2802 ret = rte_net_intel_cksum_prepare(m);
2808 if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_QOS &&
2809 ol_flags & (RTE_MBUF_F_RX_VLAN_STRIPPED | RTE_MBUF_F_RX_VLAN)) {
2810 ret = iavf_check_vlan_up2tc(txq, m);
2821 /* choose rx function*/
2823 iavf_set_rx_function(struct rte_eth_dev *dev)
2825 struct iavf_adapter *adapter =
2826 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2827 struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2830 struct iavf_rx_queue *rxq;
2833 bool use_avx2 = false;
2834 bool use_avx512 = false;
2835 bool use_flex = false;
2837 check_ret = iavf_rx_vec_dev_check(dev);
2838 if (check_ret >= 0 &&
2839 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
2840 if ((rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
2841 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) &&
2842 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256)
2845 #ifdef CC_AVX512_SUPPORT
2846 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 &&
2847 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1 &&
2848 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512)
2852 if (vf->vf_res->vf_cap_flags &
2853 VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC)
2856 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2857 rxq = dev->data->rx_queues[i];
2858 (void)iavf_rxq_vec_setup(rxq);
2861 if (dev->data->scattered_rx) {
2864 "Using %sVector Scattered Rx (port %d).",
2865 use_avx2 ? "avx2 " : "",
2866 dev->data->port_id);
2868 if (check_ret == IAVF_VECTOR_PATH)
2870 "Using AVX512 Vector Scattered Rx (port %d).",
2871 dev->data->port_id);
2874 "Using AVX512 OFFLOAD Vector Scattered Rx (port %d).",
2875 dev->data->port_id);
2878 dev->rx_pkt_burst = use_avx2 ?
2879 iavf_recv_scattered_pkts_vec_avx2_flex_rxd :
2880 iavf_recv_scattered_pkts_vec_flex_rxd;
2881 #ifdef CC_AVX512_SUPPORT
2883 if (check_ret == IAVF_VECTOR_PATH)
2885 iavf_recv_scattered_pkts_vec_avx512_flex_rxd;
2888 iavf_recv_scattered_pkts_vec_avx512_flex_rxd_offload;
2892 dev->rx_pkt_burst = use_avx2 ?
2893 iavf_recv_scattered_pkts_vec_avx2 :
2894 iavf_recv_scattered_pkts_vec;
2895 #ifdef CC_AVX512_SUPPORT
2897 if (check_ret == IAVF_VECTOR_PATH)
2899 iavf_recv_scattered_pkts_vec_avx512;
2902 iavf_recv_scattered_pkts_vec_avx512_offload;
2908 PMD_DRV_LOG(DEBUG, "Using %sVector Rx (port %d).",
2909 use_avx2 ? "avx2 " : "",
2910 dev->data->port_id);
2912 if (check_ret == IAVF_VECTOR_PATH)
2914 "Using AVX512 Vector Rx (port %d).",
2915 dev->data->port_id);
2918 "Using AVX512 OFFLOAD Vector Rx (port %d).",
2919 dev->data->port_id);
2922 dev->rx_pkt_burst = use_avx2 ?
2923 iavf_recv_pkts_vec_avx2_flex_rxd :
2924 iavf_recv_pkts_vec_flex_rxd;
2925 #ifdef CC_AVX512_SUPPORT
2927 if (check_ret == IAVF_VECTOR_PATH)
2929 iavf_recv_pkts_vec_avx512_flex_rxd;
2932 iavf_recv_pkts_vec_avx512_flex_rxd_offload;
2936 dev->rx_pkt_burst = use_avx2 ?
2937 iavf_recv_pkts_vec_avx2 :
2939 #ifdef CC_AVX512_SUPPORT
2941 if (check_ret == IAVF_VECTOR_PATH)
2943 iavf_recv_pkts_vec_avx512;
2946 iavf_recv_pkts_vec_avx512_offload;
2956 if (dev->data->scattered_rx) {
2957 PMD_DRV_LOG(DEBUG, "Using a Scattered Rx callback (port=%d).",
2958 dev->data->port_id);
2959 if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC)
2960 dev->rx_pkt_burst = iavf_recv_scattered_pkts_flex_rxd;
2962 dev->rx_pkt_burst = iavf_recv_scattered_pkts;
2963 } else if (adapter->rx_bulk_alloc_allowed) {
2964 PMD_DRV_LOG(DEBUG, "Using bulk Rx callback (port=%d).",
2965 dev->data->port_id);
2966 dev->rx_pkt_burst = iavf_recv_pkts_bulk_alloc;
2968 PMD_DRV_LOG(DEBUG, "Using Basic Rx callback (port=%d).",
2969 dev->data->port_id);
2970 if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC)
2971 dev->rx_pkt_burst = iavf_recv_pkts_flex_rxd;
2973 dev->rx_pkt_burst = iavf_recv_pkts;
2977 /* choose tx function*/
2979 iavf_set_tx_function(struct rte_eth_dev *dev)
2982 struct iavf_tx_queue *txq;
2985 bool use_sse = false;
2986 bool use_avx2 = false;
2987 bool use_avx512 = false;
2989 check_ret = iavf_tx_vec_dev_check(dev);
2991 if (check_ret >= 0 &&
2992 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
2993 /* SSE and AVX2 not support offload path yet. */
2994 if (check_ret == IAVF_VECTOR_PATH) {
2996 if ((rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
2997 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) &&
2998 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256)
3001 #ifdef CC_AVX512_SUPPORT
3002 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 &&
3003 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1 &&
3004 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512)
3008 if (!use_sse && !use_avx2 && !use_avx512)
3012 PMD_DRV_LOG(DEBUG, "Using %sVector Tx (port %d).",
3013 use_avx2 ? "avx2 " : "",
3014 dev->data->port_id);
3015 dev->tx_pkt_burst = use_avx2 ?
3016 iavf_xmit_pkts_vec_avx2 :
3019 dev->tx_pkt_prepare = NULL;
3020 #ifdef CC_AVX512_SUPPORT
3022 if (check_ret == IAVF_VECTOR_PATH) {
3023 dev->tx_pkt_burst = iavf_xmit_pkts_vec_avx512;
3024 PMD_DRV_LOG(DEBUG, "Using AVX512 Vector Tx (port %d).",
3025 dev->data->port_id);
3027 dev->tx_pkt_burst = iavf_xmit_pkts_vec_avx512_offload;
3028 dev->tx_pkt_prepare = iavf_prep_pkts;
3029 PMD_DRV_LOG(DEBUG, "Using AVX512 OFFLOAD Vector Tx (port %d).",
3030 dev->data->port_id);
3035 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3036 txq = dev->data->tx_queues[i];
3039 #ifdef CC_AVX512_SUPPORT
3041 iavf_txq_vec_setup_avx512(txq);
3043 iavf_txq_vec_setup(txq);
3045 iavf_txq_vec_setup(txq);
3054 PMD_DRV_LOG(DEBUG, "Using Basic Tx callback (port=%d).",
3055 dev->data->port_id);
3056 dev->tx_pkt_burst = iavf_xmit_pkts;
3057 dev->tx_pkt_prepare = iavf_prep_pkts;
3061 iavf_tx_done_cleanup_full(struct iavf_tx_queue *txq,
3064 struct iavf_tx_entry *swr_ring = txq->sw_ring;
3065 uint16_t i, tx_last, tx_id;
3066 uint16_t nb_tx_free_last;
3067 uint16_t nb_tx_to_clean;
3070 /* Start free mbuf from the next of tx_tail */
3071 tx_last = txq->tx_tail;
3072 tx_id = swr_ring[tx_last].next_id;
3074 if (txq->nb_free == 0 && iavf_xmit_cleanup(txq))
3077 nb_tx_to_clean = txq->nb_free;
3078 nb_tx_free_last = txq->nb_free;
3080 free_cnt = txq->nb_tx_desc;
3082 /* Loop through swr_ring to count the amount of
3083 * freeable mubfs and packets.
3085 for (pkt_cnt = 0; pkt_cnt < free_cnt; ) {
3086 for (i = 0; i < nb_tx_to_clean &&
3087 pkt_cnt < free_cnt &&
3088 tx_id != tx_last; i++) {
3089 if (swr_ring[tx_id].mbuf != NULL) {
3090 rte_pktmbuf_free_seg(swr_ring[tx_id].mbuf);
3091 swr_ring[tx_id].mbuf = NULL;
3094 * last segment in the packet,
3095 * increment packet count
3097 pkt_cnt += (swr_ring[tx_id].last_id == tx_id);
3100 tx_id = swr_ring[tx_id].next_id;
3103 if (txq->rs_thresh > txq->nb_tx_desc -
3104 txq->nb_free || tx_id == tx_last)
3107 if (pkt_cnt < free_cnt) {
3108 if (iavf_xmit_cleanup(txq))
3111 nb_tx_to_clean = txq->nb_free - nb_tx_free_last;
3112 nb_tx_free_last = txq->nb_free;
3116 return (int)pkt_cnt;
3120 iavf_dev_tx_done_cleanup(void *txq, uint32_t free_cnt)
3122 struct iavf_tx_queue *q = (struct iavf_tx_queue *)txq;
3124 return iavf_tx_done_cleanup_full(q, free_cnt);
3128 iavf_dev_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
3129 struct rte_eth_rxq_info *qinfo)
3131 struct iavf_rx_queue *rxq;
3133 rxq = dev->data->rx_queues[queue_id];
3135 qinfo->mp = rxq->mp;
3136 qinfo->scattered_rx = dev->data->scattered_rx;
3137 qinfo->nb_desc = rxq->nb_rx_desc;
3139 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
3140 qinfo->conf.rx_drop_en = true;
3141 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
3145 iavf_dev_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
3146 struct rte_eth_txq_info *qinfo)
3148 struct iavf_tx_queue *txq;
3150 txq = dev->data->tx_queues[queue_id];
3152 qinfo->nb_desc = txq->nb_tx_desc;
3154 qinfo->conf.tx_free_thresh = txq->free_thresh;
3155 qinfo->conf.tx_rs_thresh = txq->rs_thresh;
3156 qinfo->conf.offloads = txq->offloads;
3157 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
3160 /* Get the number of used descriptors of a rx queue */
3162 iavf_dev_rxq_count(void *rx_queue)
3164 #define IAVF_RXQ_SCAN_INTERVAL 4
3165 volatile union iavf_rx_desc *rxdp;
3166 struct iavf_rx_queue *rxq;
3170 rxdp = &rxq->rx_ring[rxq->rx_tail];
3172 while ((desc < rxq->nb_rx_desc) &&
3173 ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
3174 IAVF_RXD_QW1_STATUS_MASK) >> IAVF_RXD_QW1_STATUS_SHIFT) &
3175 (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)) {
3176 /* Check the DD bit of a rx descriptor of each 4 in a group,
3177 * to avoid checking too frequently and downgrading performance
3180 desc += IAVF_RXQ_SCAN_INTERVAL;
3181 rxdp += IAVF_RXQ_SCAN_INTERVAL;
3182 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
3183 rxdp = &(rxq->rx_ring[rxq->rx_tail +
3184 desc - rxq->nb_rx_desc]);
3191 iavf_dev_rx_desc_status(void *rx_queue, uint16_t offset)
3193 struct iavf_rx_queue *rxq = rx_queue;
3194 volatile uint64_t *status;
3198 if (unlikely(offset >= rxq->nb_rx_desc))
3201 if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
3202 return RTE_ETH_RX_DESC_UNAVAIL;
3204 desc = rxq->rx_tail + offset;
3205 if (desc >= rxq->nb_rx_desc)
3206 desc -= rxq->nb_rx_desc;
3208 status = &rxq->rx_ring[desc].wb.qword1.status_error_len;
3209 mask = rte_le_to_cpu_64((1ULL << IAVF_RX_DESC_STATUS_DD_SHIFT)
3210 << IAVF_RXD_QW1_STATUS_SHIFT);
3212 return RTE_ETH_RX_DESC_DONE;
3214 return RTE_ETH_RX_DESC_AVAIL;
3218 iavf_dev_tx_desc_status(void *tx_queue, uint16_t offset)
3220 struct iavf_tx_queue *txq = tx_queue;
3221 volatile uint64_t *status;
3222 uint64_t mask, expect;
3225 if (unlikely(offset >= txq->nb_tx_desc))
3228 desc = txq->tx_tail + offset;
3229 /* go to next desc that has the RS bit */
3230 desc = ((desc + txq->rs_thresh - 1) / txq->rs_thresh) *
3232 if (desc >= txq->nb_tx_desc) {
3233 desc -= txq->nb_tx_desc;
3234 if (desc >= txq->nb_tx_desc)
3235 desc -= txq->nb_tx_desc;
3238 status = &txq->tx_ring[desc].cmd_type_offset_bsz;
3239 mask = rte_le_to_cpu_64(IAVF_TXD_QW1_DTYPE_MASK);
3240 expect = rte_cpu_to_le_64(
3241 IAVF_TX_DESC_DTYPE_DESC_DONE << IAVF_TXD_QW1_DTYPE_SHIFT);
3242 if ((*status & mask) == expect)
3243 return RTE_ETH_TX_DESC_DONE;
3245 return RTE_ETH_TX_DESC_FULL;
3248 static inline uint32_t
3249 iavf_get_default_ptype(uint16_t ptype)
3251 static const uint32_t ptype_tbl[IAVF_MAX_PKT_TYPE]
3252 __rte_cache_aligned = {
3255 [1] = RTE_PTYPE_L2_ETHER,
3256 [2] = RTE_PTYPE_L2_ETHER_TIMESYNC,
3257 /* [3] - [5] reserved */
3258 [6] = RTE_PTYPE_L2_ETHER_LLDP,
3259 /* [7] - [10] reserved */
3260 [11] = RTE_PTYPE_L2_ETHER_ARP,
3261 /* [12] - [21] reserved */
3263 /* Non tunneled IPv4 */
3264 [22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3266 [23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3267 RTE_PTYPE_L4_NONFRAG,
3268 [24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3271 [26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3273 [27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3275 [28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3279 [29] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3280 RTE_PTYPE_TUNNEL_IP |
3281 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3282 RTE_PTYPE_INNER_L4_FRAG,
3283 [30] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3284 RTE_PTYPE_TUNNEL_IP |
3285 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3286 RTE_PTYPE_INNER_L4_NONFRAG,
3287 [31] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3288 RTE_PTYPE_TUNNEL_IP |
3289 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3290 RTE_PTYPE_INNER_L4_UDP,
3292 [33] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3293 RTE_PTYPE_TUNNEL_IP |
3294 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3295 RTE_PTYPE_INNER_L4_TCP,
3296 [34] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3297 RTE_PTYPE_TUNNEL_IP |
3298 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3299 RTE_PTYPE_INNER_L4_SCTP,
3300 [35] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3301 RTE_PTYPE_TUNNEL_IP |
3302 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3303 RTE_PTYPE_INNER_L4_ICMP,
3306 [36] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3307 RTE_PTYPE_TUNNEL_IP |
3308 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3309 RTE_PTYPE_INNER_L4_FRAG,
3310 [37] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3311 RTE_PTYPE_TUNNEL_IP |
3312 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3313 RTE_PTYPE_INNER_L4_NONFRAG,
3314 [38] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3315 RTE_PTYPE_TUNNEL_IP |
3316 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3317 RTE_PTYPE_INNER_L4_UDP,
3319 [40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3320 RTE_PTYPE_TUNNEL_IP |
3321 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3322 RTE_PTYPE_INNER_L4_TCP,
3323 [41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3324 RTE_PTYPE_TUNNEL_IP |
3325 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3326 RTE_PTYPE_INNER_L4_SCTP,
3327 [42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3328 RTE_PTYPE_TUNNEL_IP |
3329 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3330 RTE_PTYPE_INNER_L4_ICMP,
3332 /* IPv4 --> GRE/Teredo/VXLAN */
3333 [43] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3334 RTE_PTYPE_TUNNEL_GRENAT,
3336 /* IPv4 --> GRE/Teredo/VXLAN --> IPv4 */
3337 [44] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3338 RTE_PTYPE_TUNNEL_GRENAT |
3339 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3340 RTE_PTYPE_INNER_L4_FRAG,
3341 [45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3342 RTE_PTYPE_TUNNEL_GRENAT |
3343 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3344 RTE_PTYPE_INNER_L4_NONFRAG,
3345 [46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3346 RTE_PTYPE_TUNNEL_GRENAT |
3347 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3348 RTE_PTYPE_INNER_L4_UDP,
3350 [48] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3351 RTE_PTYPE_TUNNEL_GRENAT |
3352 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3353 RTE_PTYPE_INNER_L4_TCP,
3354 [49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3355 RTE_PTYPE_TUNNEL_GRENAT |
3356 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3357 RTE_PTYPE_INNER_L4_SCTP,
3358 [50] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3359 RTE_PTYPE_TUNNEL_GRENAT |
3360 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3361 RTE_PTYPE_INNER_L4_ICMP,
3363 /* IPv4 --> GRE/Teredo/VXLAN --> IPv6 */
3364 [51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3365 RTE_PTYPE_TUNNEL_GRENAT |
3366 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3367 RTE_PTYPE_INNER_L4_FRAG,
3368 [52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3369 RTE_PTYPE_TUNNEL_GRENAT |
3370 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3371 RTE_PTYPE_INNER_L4_NONFRAG,
3372 [53] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3373 RTE_PTYPE_TUNNEL_GRENAT |
3374 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3375 RTE_PTYPE_INNER_L4_UDP,
3377 [55] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3378 RTE_PTYPE_TUNNEL_GRENAT |
3379 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3380 RTE_PTYPE_INNER_L4_TCP,
3381 [56] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3382 RTE_PTYPE_TUNNEL_GRENAT |
3383 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3384 RTE_PTYPE_INNER_L4_SCTP,
3385 [57] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3386 RTE_PTYPE_TUNNEL_GRENAT |
3387 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3388 RTE_PTYPE_INNER_L4_ICMP,
3390 /* IPv4 --> GRE/Teredo/VXLAN --> MAC */
3391 [58] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3392 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
3394 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
3395 [59] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3396 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3397 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3398 RTE_PTYPE_INNER_L4_FRAG,
3399 [60] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3400 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3401 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3402 RTE_PTYPE_INNER_L4_NONFRAG,
3403 [61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3404 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3405 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3406 RTE_PTYPE_INNER_L4_UDP,
3408 [63] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3409 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3410 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3411 RTE_PTYPE_INNER_L4_TCP,
3412 [64] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3413 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3414 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3415 RTE_PTYPE_INNER_L4_SCTP,
3416 [65] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3417 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3418 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3419 RTE_PTYPE_INNER_L4_ICMP,
3421 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
3422 [66] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3423 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3424 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3425 RTE_PTYPE_INNER_L4_FRAG,
3426 [67] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3427 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3428 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3429 RTE_PTYPE_INNER_L4_NONFRAG,
3430 [68] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3431 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3432 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3433 RTE_PTYPE_INNER_L4_UDP,
3435 [70] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3436 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3437 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3438 RTE_PTYPE_INNER_L4_TCP,
3439 [71] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3440 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3441 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3442 RTE_PTYPE_INNER_L4_SCTP,
3443 [72] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3444 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3445 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3446 RTE_PTYPE_INNER_L4_ICMP,
3447 /* [73] - [87] reserved */
3449 /* Non tunneled IPv6 */
3450 [88] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3452 [89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3453 RTE_PTYPE_L4_NONFRAG,
3454 [90] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3457 [92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3459 [93] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3461 [94] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3465 [95] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3466 RTE_PTYPE_TUNNEL_IP |
3467 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3468 RTE_PTYPE_INNER_L4_FRAG,
3469 [96] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3470 RTE_PTYPE_TUNNEL_IP |
3471 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3472 RTE_PTYPE_INNER_L4_NONFRAG,
3473 [97] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3474 RTE_PTYPE_TUNNEL_IP |
3475 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3476 RTE_PTYPE_INNER_L4_UDP,
3478 [99] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3479 RTE_PTYPE_TUNNEL_IP |
3480 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3481 RTE_PTYPE_INNER_L4_TCP,
3482 [100] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3483 RTE_PTYPE_TUNNEL_IP |
3484 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3485 RTE_PTYPE_INNER_L4_SCTP,
3486 [101] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3487 RTE_PTYPE_TUNNEL_IP |
3488 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3489 RTE_PTYPE_INNER_L4_ICMP,
3492 [102] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3493 RTE_PTYPE_TUNNEL_IP |
3494 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3495 RTE_PTYPE_INNER_L4_FRAG,
3496 [103] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3497 RTE_PTYPE_TUNNEL_IP |
3498 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3499 RTE_PTYPE_INNER_L4_NONFRAG,
3500 [104] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3501 RTE_PTYPE_TUNNEL_IP |
3502 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3503 RTE_PTYPE_INNER_L4_UDP,
3504 /* [105] reserved */
3505 [106] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3506 RTE_PTYPE_TUNNEL_IP |
3507 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3508 RTE_PTYPE_INNER_L4_TCP,
3509 [107] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3510 RTE_PTYPE_TUNNEL_IP |
3511 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3512 RTE_PTYPE_INNER_L4_SCTP,
3513 [108] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3514 RTE_PTYPE_TUNNEL_IP |
3515 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3516 RTE_PTYPE_INNER_L4_ICMP,
3518 /* IPv6 --> GRE/Teredo/VXLAN */
3519 [109] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3520 RTE_PTYPE_TUNNEL_GRENAT,
3522 /* IPv6 --> GRE/Teredo/VXLAN --> IPv4 */
3523 [110] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3524 RTE_PTYPE_TUNNEL_GRENAT |
3525 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3526 RTE_PTYPE_INNER_L4_FRAG,
3527 [111] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3528 RTE_PTYPE_TUNNEL_GRENAT |
3529 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3530 RTE_PTYPE_INNER_L4_NONFRAG,
3531 [112] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3532 RTE_PTYPE_TUNNEL_GRENAT |
3533 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3534 RTE_PTYPE_INNER_L4_UDP,
3535 /* [113] reserved */
3536 [114] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3537 RTE_PTYPE_TUNNEL_GRENAT |
3538 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3539 RTE_PTYPE_INNER_L4_TCP,
3540 [115] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3541 RTE_PTYPE_TUNNEL_GRENAT |
3542 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3543 RTE_PTYPE_INNER_L4_SCTP,
3544 [116] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3545 RTE_PTYPE_TUNNEL_GRENAT |
3546 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3547 RTE_PTYPE_INNER_L4_ICMP,
3549 /* IPv6 --> GRE/Teredo/VXLAN --> IPv6 */
3550 [117] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3551 RTE_PTYPE_TUNNEL_GRENAT |
3552 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3553 RTE_PTYPE_INNER_L4_FRAG,
3554 [118] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3555 RTE_PTYPE_TUNNEL_GRENAT |
3556 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3557 RTE_PTYPE_INNER_L4_NONFRAG,
3558 [119] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3559 RTE_PTYPE_TUNNEL_GRENAT |
3560 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3561 RTE_PTYPE_INNER_L4_UDP,
3562 /* [120] reserved */
3563 [121] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3564 RTE_PTYPE_TUNNEL_GRENAT |
3565 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3566 RTE_PTYPE_INNER_L4_TCP,
3567 [122] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3568 RTE_PTYPE_TUNNEL_GRENAT |
3569 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3570 RTE_PTYPE_INNER_L4_SCTP,
3571 [123] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3572 RTE_PTYPE_TUNNEL_GRENAT |
3573 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3574 RTE_PTYPE_INNER_L4_ICMP,
3576 /* IPv6 --> GRE/Teredo/VXLAN --> MAC */
3577 [124] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3578 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
3580 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
3581 [125] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3582 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3583 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3584 RTE_PTYPE_INNER_L4_FRAG,
3585 [126] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3586 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3587 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3588 RTE_PTYPE_INNER_L4_NONFRAG,
3589 [127] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3590 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3591 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3592 RTE_PTYPE_INNER_L4_UDP,
3593 /* [128] reserved */
3594 [129] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3595 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3596 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3597 RTE_PTYPE_INNER_L4_TCP,
3598 [130] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3599 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3600 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3601 RTE_PTYPE_INNER_L4_SCTP,
3602 [131] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3603 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3604 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3605 RTE_PTYPE_INNER_L4_ICMP,
3607 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
3608 [132] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3609 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3610 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3611 RTE_PTYPE_INNER_L4_FRAG,
3612 [133] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3613 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3614 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3615 RTE_PTYPE_INNER_L4_NONFRAG,
3616 [134] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3617 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3618 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3619 RTE_PTYPE_INNER_L4_UDP,
3620 /* [135] reserved */
3621 [136] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3622 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3623 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3624 RTE_PTYPE_INNER_L4_TCP,
3625 [137] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3626 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3627 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3628 RTE_PTYPE_INNER_L4_SCTP,
3629 [138] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3630 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3631 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3632 RTE_PTYPE_INNER_L4_ICMP,
3633 /* [139] - [299] reserved */
3636 [300] = RTE_PTYPE_L2_ETHER_PPPOE,
3637 [301] = RTE_PTYPE_L2_ETHER_PPPOE,
3639 /* PPPoE --> IPv4 */
3640 [302] = RTE_PTYPE_L2_ETHER_PPPOE |
3641 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3643 [303] = RTE_PTYPE_L2_ETHER_PPPOE |
3644 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3645 RTE_PTYPE_L4_NONFRAG,
3646 [304] = RTE_PTYPE_L2_ETHER_PPPOE |
3647 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3649 [305] = RTE_PTYPE_L2_ETHER_PPPOE |
3650 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3652 [306] = RTE_PTYPE_L2_ETHER_PPPOE |
3653 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3655 [307] = RTE_PTYPE_L2_ETHER_PPPOE |
3656 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3659 /* PPPoE --> IPv6 */
3660 [308] = RTE_PTYPE_L2_ETHER_PPPOE |
3661 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3663 [309] = RTE_PTYPE_L2_ETHER_PPPOE |
3664 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3665 RTE_PTYPE_L4_NONFRAG,
3666 [310] = RTE_PTYPE_L2_ETHER_PPPOE |
3667 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3669 [311] = RTE_PTYPE_L2_ETHER_PPPOE |
3670 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3672 [312] = RTE_PTYPE_L2_ETHER_PPPOE |
3673 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3675 [313] = RTE_PTYPE_L2_ETHER_PPPOE |
3676 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3678 /* [314] - [324] reserved */
3680 /* IPv4/IPv6 --> GTPC/GTPU */
3681 [325] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3682 RTE_PTYPE_TUNNEL_GTPC,
3683 [326] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3684 RTE_PTYPE_TUNNEL_GTPC,
3685 [327] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3686 RTE_PTYPE_TUNNEL_GTPC,
3687 [328] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3688 RTE_PTYPE_TUNNEL_GTPC,
3689 [329] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3690 RTE_PTYPE_TUNNEL_GTPU,
3691 [330] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3692 RTE_PTYPE_TUNNEL_GTPU,
3694 /* IPv4 --> GTPU --> IPv4 */
3695 [331] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3696 RTE_PTYPE_TUNNEL_GTPU |
3697 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3698 RTE_PTYPE_INNER_L4_FRAG,
3699 [332] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3700 RTE_PTYPE_TUNNEL_GTPU |
3701 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3702 RTE_PTYPE_INNER_L4_NONFRAG,
3703 [333] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3704 RTE_PTYPE_TUNNEL_GTPU |
3705 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3706 RTE_PTYPE_INNER_L4_UDP,
3707 [334] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3708 RTE_PTYPE_TUNNEL_GTPU |
3709 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3710 RTE_PTYPE_INNER_L4_TCP,
3711 [335] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3712 RTE_PTYPE_TUNNEL_GTPU |
3713 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3714 RTE_PTYPE_INNER_L4_ICMP,
3716 /* IPv6 --> GTPU --> IPv4 */
3717 [336] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3718 RTE_PTYPE_TUNNEL_GTPU |
3719 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3720 RTE_PTYPE_INNER_L4_FRAG,
3721 [337] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3722 RTE_PTYPE_TUNNEL_GTPU |
3723 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3724 RTE_PTYPE_INNER_L4_NONFRAG,
3725 [338] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3726 RTE_PTYPE_TUNNEL_GTPU |
3727 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3728 RTE_PTYPE_INNER_L4_UDP,
3729 [339] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3730 RTE_PTYPE_TUNNEL_GTPU |
3731 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3732 RTE_PTYPE_INNER_L4_TCP,
3733 [340] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3734 RTE_PTYPE_TUNNEL_GTPU |
3735 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3736 RTE_PTYPE_INNER_L4_ICMP,
3738 /* IPv4 --> GTPU --> IPv6 */
3739 [341] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3740 RTE_PTYPE_TUNNEL_GTPU |
3741 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3742 RTE_PTYPE_INNER_L4_FRAG,
3743 [342] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3744 RTE_PTYPE_TUNNEL_GTPU |
3745 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3746 RTE_PTYPE_INNER_L4_NONFRAG,
3747 [343] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3748 RTE_PTYPE_TUNNEL_GTPU |
3749 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3750 RTE_PTYPE_INNER_L4_UDP,
3751 [344] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3752 RTE_PTYPE_TUNNEL_GTPU |
3753 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3754 RTE_PTYPE_INNER_L4_TCP,
3755 [345] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3756 RTE_PTYPE_TUNNEL_GTPU |
3757 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3758 RTE_PTYPE_INNER_L4_ICMP,
3760 /* IPv6 --> GTPU --> IPv6 */
3761 [346] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3762 RTE_PTYPE_TUNNEL_GTPU |
3763 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3764 RTE_PTYPE_INNER_L4_FRAG,
3765 [347] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3766 RTE_PTYPE_TUNNEL_GTPU |
3767 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3768 RTE_PTYPE_INNER_L4_NONFRAG,
3769 [348] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3770 RTE_PTYPE_TUNNEL_GTPU |
3771 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3772 RTE_PTYPE_INNER_L4_UDP,
3773 [349] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3774 RTE_PTYPE_TUNNEL_GTPU |
3775 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3776 RTE_PTYPE_INNER_L4_TCP,
3777 [350] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3778 RTE_PTYPE_TUNNEL_GTPU |
3779 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3780 RTE_PTYPE_INNER_L4_ICMP,
3782 /* IPv4 --> UDP ECPRI */
3783 [372] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3785 [373] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3787 [374] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3789 [375] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3791 [376] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3793 [377] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3795 [378] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3797 [379] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3799 [380] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3801 [381] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3804 /* IPV6 --> UDP ECPRI */
3805 [382] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3807 [383] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3809 [384] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3811 [385] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3813 [386] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3815 [387] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3817 [388] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3819 [389] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3821 [390] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3823 [391] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3825 /* All others reserved */
3828 return ptype_tbl[ptype];
3832 iavf_set_default_ptype_table(struct rte_eth_dev *dev)
3834 struct iavf_adapter *ad =
3835 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3838 for (i = 0; i < IAVF_MAX_PKT_TYPE; i++)
3839 ad->ptype_tbl[i] = iavf_get_default_ptype(i);