drivers/net/iavf/iavf_rxtx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2017 Intel Corporation
   3  */
   4
   5 #include <stdio.h>
   6 #include <stdlib.h>
   7 #include <string.h>
   8 #include <errno.h>
   9 #include <stdint.h>
  10 #include <stdarg.h>
  11 #include <unistd.h>
  12 #include <inttypes.h>
  13 #include <sys/queue.h>
  14
  15 #include <rte_string_fns.h>
  16 #include <rte_memzone.h>
  17 #include <rte_mbuf.h>
  18 #include <rte_malloc.h>
  19 #include <rte_ether.h>
  20 #include <ethdev_driver.h>
  21 #include <rte_tcp.h>
  22 #include <rte_sctp.h>
  23 #include <rte_udp.h>
  24 #include <rte_ip.h>
  25 #include <rte_net.h>
  26 #include <rte_vect.h>
  27
  28 #include "iavf.h"
  29 #include "iavf_rxtx.h"
  30 #include "iavf_ipsec_crypto.h"
  31 #include "rte_pmd_iavf.h"
  32
  33 /* Offset of mbuf dynamic field for protocol extraction's metadata */
  34 int rte_pmd_ifd_dynfield_proto_xtr_metadata_offs = -1;
  35
  36 /* Mask of mbuf dynamic flags for protocol extraction's type */
  37 uint64_t rte_pmd_ifd_dynflag_proto_xtr_vlan_mask;
  38 uint64_t rte_pmd_ifd_dynflag_proto_xtr_ipv4_mask;
  39 uint64_t rte_pmd_ifd_dynflag_proto_xtr_ipv6_mask;
  40 uint64_t rte_pmd_ifd_dynflag_proto_xtr_ipv6_flow_mask;
  41 uint64_t rte_pmd_ifd_dynflag_proto_xtr_tcp_mask;
  42 uint64_t rte_pmd_ifd_dynflag_proto_xtr_ip_offset_mask;
  43 uint64_t rte_pmd_ifd_dynflag_proto_xtr_ipsec_crypto_said_mask;
  44
  45 uint8_t
  46 iavf_proto_xtr_type_to_rxdid(uint8_t flex_type)
  47 {
  48         static uint8_t rxdid_map[] = {
  49                 [IAVF_PROTO_XTR_NONE]      = IAVF_RXDID_COMMS_OVS_1,
  50                 [IAVF_PROTO_XTR_VLAN]      = IAVF_RXDID_COMMS_AUX_VLAN,
  51                 [IAVF_PROTO_XTR_IPV4]      = IAVF_RXDID_COMMS_AUX_IPV4,
  52                 [IAVF_PROTO_XTR_IPV6]      = IAVF_RXDID_COMMS_AUX_IPV6,
  53                 [IAVF_PROTO_XTR_IPV6_FLOW] = IAVF_RXDID_COMMS_AUX_IPV6_FLOW,
  54                 [IAVF_PROTO_XTR_TCP]       = IAVF_RXDID_COMMS_AUX_TCP,
  55                 [IAVF_PROTO_XTR_IP_OFFSET] = IAVF_RXDID_COMMS_AUX_IP_OFFSET,
  56                 [IAVF_PROTO_XTR_IPSEC_CRYPTO_SAID] =
  57                                 IAVF_RXDID_COMMS_IPSEC_CRYPTO,
  58         };
  59
  60         return flex_type < RTE_DIM(rxdid_map) ?
  61                                 rxdid_map[flex_type] : IAVF_RXDID_COMMS_OVS_1;
  62 }
  63
  64 static int
  65 iavf_monitor_callback(const uint64_t value,
  66                 const uint64_t arg[RTE_POWER_MONITOR_OPAQUE_SZ] __rte_unused)
  67 {
  68         const uint64_t m = rte_cpu_to_le_64(1 << IAVF_RX_DESC_STATUS_DD_SHIFT);
  69         /*
  70          * we expect the DD bit to be set to 1 if this descriptor was already
  71          * written to.
  72          */
  73         return (value & m) == m ? -1 : 0;
  74 }
  75
  76 int
  77 iavf_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc)
  78 {
  79         struct iavf_rx_queue *rxq = rx_queue;
  80         volatile union iavf_rx_desc *rxdp;
  81         uint16_t desc;
  82
  83         desc = rxq->rx_tail;
  84         rxdp = &rxq->rx_ring[desc];
  85         /* watch for changes in status bit */
  86         pmc->addr = &rxdp->wb.qword1.status_error_len;
  87
  88         /* comparison callback */
  89         pmc->fn = iavf_monitor_callback;
  90
  91         /* registers are 64-bit */
  92         pmc->size = sizeof(uint64_t);
  93
  94         return 0;
  95 }
  96
  97 static inline int
  98 check_rx_thresh(uint16_t nb_desc, uint16_t thresh)
  99 {
 100         /* The following constraints must be satisfied:
 101          *   thresh < rxq->nb_rx_desc
 102          */
 103         if (thresh >= nb_desc) {
 104                 PMD_INIT_LOG(ERR, "rx_free_thresh (%u) must be less than %u",
 105                              thresh, nb_desc);
 106                 return -EINVAL;
 107         }
 108         return 0;
 109 }
 110
 111 static inline int
 112 check_tx_thresh(uint16_t nb_desc, uint16_t tx_rs_thresh,
 113                 uint16_t tx_free_thresh)
 114 {
 115         /* TX descriptors will have their RS bit set after tx_rs_thresh
 116          * descriptors have been used. The TX descriptor ring will be cleaned
 117          * after tx_free_thresh descriptors are used or if the number of
 118          * descriptors required to transmit a packet is greater than the
 119          * number of free TX descriptors.
 120          *
 121          * The following constraints must be satisfied:
 122          *  - tx_rs_thresh must be less than the size of the ring minus 2.
 123          *  - tx_free_thresh must be less than the size of the ring minus 3.
 124          *  - tx_rs_thresh must be less than or equal to tx_free_thresh.
 125          *  - tx_rs_thresh must be a divisor of the ring size.
 126          *
 127          * One descriptor in the TX ring is used as a sentinel to avoid a H/W
 128          * race condition, hence the maximum threshold constraints. When set
 129          * to zero use default values.
 130          */
 131         if (tx_rs_thresh >= (nb_desc - 2)) {
 132                 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be less than the "
 133                              "number of TX descriptors (%u) minus 2",
 134                              tx_rs_thresh, nb_desc);
 135                 return -EINVAL;
 136         }
 137         if (tx_free_thresh >= (nb_desc - 3)) {
 138                 PMD_INIT_LOG(ERR, "tx_free_thresh (%u) must be less than the "
 139                              "number of TX descriptors (%u) minus 3.",
 140                              tx_free_thresh, nb_desc);
 141                 return -EINVAL;
 142         }
 143         if (tx_rs_thresh > tx_free_thresh) {
 144                 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be less than or "
 145                              "equal to tx_free_thresh (%u).",
 146                              tx_rs_thresh, tx_free_thresh);
 147                 return -EINVAL;
 148         }
 149         if ((nb_desc % tx_rs_thresh) != 0) {
 150                 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be a divisor of the "
 151                              "number of TX descriptors (%u).",
 152                              tx_rs_thresh, nb_desc);
 153                 return -EINVAL;
 154         }
 155
 156         return 0;
 157 }
 158
 159 static inline bool
 160 check_rx_vec_allow(struct iavf_rx_queue *rxq)
 161 {
 162         if (rxq->rx_free_thresh >= IAVF_VPMD_RX_MAX_BURST &&
 163             rxq->nb_rx_desc % rxq->rx_free_thresh == 0) {
 164                 PMD_INIT_LOG(DEBUG, "Vector Rx can be enabled on this rxq.");
 165                 return true;
 166         }
 167
 168         PMD_INIT_LOG(DEBUG, "Vector Rx cannot be enabled on this rxq.");
 169         return false;
 170 }
 171
 172 static inline bool
 173 check_tx_vec_allow(struct iavf_tx_queue *txq)
 174 {
 175         if (!(txq->offloads & IAVF_TX_NO_VECTOR_FLAGS) &&
 176             txq->rs_thresh >= IAVF_VPMD_TX_MAX_BURST &&
 177             txq->rs_thresh <= IAVF_VPMD_TX_MAX_FREE_BUF) {
 178                 PMD_INIT_LOG(DEBUG, "Vector tx can be enabled on this txq.");
 179                 return true;
 180         }
 181         PMD_INIT_LOG(DEBUG, "Vector Tx cannot be enabled on this txq.");
 182         return false;
 183 }
 184
 185 static inline bool
 186 check_rx_bulk_allow(struct iavf_rx_queue *rxq)
 187 {
 188         int ret = true;
 189
 190         if (!(rxq->rx_free_thresh >= IAVF_RX_MAX_BURST)) {
 191                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 192                              "rxq->rx_free_thresh=%d, "
 193                              "IAVF_RX_MAX_BURST=%d",
 194                              rxq->rx_free_thresh, IAVF_RX_MAX_BURST);
 195                 ret = false;
 196         } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
 197                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 198                              "rxq->nb_rx_desc=%d, "
 199                              "rxq->rx_free_thresh=%d",
 200                              rxq->nb_rx_desc, rxq->rx_free_thresh);
 201                 ret = false;
 202         }
 203         return ret;
 204 }
 205
 206 static inline void
 207 reset_rx_queue(struct iavf_rx_queue *rxq)
 208 {
 209         uint16_t len;
 210         uint32_t i;
 211
 212         if (!rxq)
 213                 return;
 214
 215         len = rxq->nb_rx_desc + IAVF_RX_MAX_BURST;
 216
 217         for (i = 0; i < len * sizeof(union iavf_rx_desc); i++)
 218                 ((volatile char *)rxq->rx_ring)[i] = 0;
 219
 220         memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
 221
 222         for (i = 0; i < IAVF_RX_MAX_BURST; i++)
 223                 rxq->sw_ring[rxq->nb_rx_desc + i] = &rxq->fake_mbuf;
 224
 225         /* for rx bulk */
 226         rxq->rx_nb_avail = 0;
 227         rxq->rx_next_avail = 0;
 228         rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
 229
 230         rxq->rx_tail = 0;
 231         rxq->nb_rx_hold = 0;
 232
 233         rte_pktmbuf_free(rxq->pkt_first_seg);
 234
 235         rxq->pkt_first_seg = NULL;
 236         rxq->pkt_last_seg = NULL;
 237         rxq->rxrearm_nb = 0;
 238         rxq->rxrearm_start = 0;
 239 }
 240
 241 static inline void
 242 reset_tx_queue(struct iavf_tx_queue *txq)
 243 {
 244         struct iavf_tx_entry *txe;
 245         uint32_t i, size;
 246         uint16_t prev;
 247
 248         if (!txq) {
 249                 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
 250                 return;
 251         }
 252
 253         txe = txq->sw_ring;
 254         size = sizeof(struct iavf_tx_desc) * txq->nb_tx_desc;
 255         for (i = 0; i < size; i++)
 256                 ((volatile char *)txq->tx_ring)[i] = 0;
 257
 258         prev = (uint16_t)(txq->nb_tx_desc - 1);
 259         for (i = 0; i < txq->nb_tx_desc; i++) {
 260                 txq->tx_ring[i].cmd_type_offset_bsz =
 261                         rte_cpu_to_le_64(IAVF_TX_DESC_DTYPE_DESC_DONE);
 262                 txe[i].mbuf =  NULL;
 263                 txe[i].last_id = i;
 264                 txe[prev].next_id = i;
 265                 prev = i;
 266         }
 267
 268         txq->tx_tail = 0;
 269         txq->nb_used = 0;
 270
 271         txq->last_desc_cleaned = txq->nb_tx_desc - 1;
 272         txq->nb_free = txq->nb_tx_desc - 1;
 273
 274         txq->next_dd = txq->rs_thresh - 1;
 275         txq->next_rs = txq->rs_thresh - 1;
 276 }
 277
 278 static int
 279 alloc_rxq_mbufs(struct iavf_rx_queue *rxq)
 280 {
 281         volatile union iavf_rx_desc *rxd;
 282         struct rte_mbuf *mbuf = NULL;
 283         uint64_t dma_addr;
 284         uint16_t i, j;
 285
 286         for (i = 0; i < rxq->nb_rx_desc; i++) {
 287                 mbuf = rte_mbuf_raw_alloc(rxq->mp);
 288                 if (unlikely(!mbuf)) {
 289                         for (j = 0; j < i; j++) {
 290                                 rte_pktmbuf_free_seg(rxq->sw_ring[j]);
 291                                 rxq->sw_ring[j] = NULL;
 292                         }
 293                         PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
 294                         return -ENOMEM;
 295                 }
 296
 297                 rte_mbuf_refcnt_set(mbuf, 1);
 298                 mbuf->next = NULL;
 299                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
 300                 mbuf->nb_segs = 1;
 301                 mbuf->port = rxq->port_id;
 302
 303                 dma_addr =
 304                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
 305
 306                 rxd = &rxq->rx_ring[i];
 307                 rxd->read.pkt_addr = dma_addr;
 308                 rxd->read.hdr_addr = 0;
 309 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
 310                 rxd->read.rsvd1 = 0;
 311                 rxd->read.rsvd2 = 0;
 312 #endif
 313
 314                 rxq->sw_ring[i] = mbuf;
 315         }
 316
 317         return 0;
 318 }
 319
 320 static inline void
 321 release_rxq_mbufs(struct iavf_rx_queue *rxq)
 322 {
 323         uint16_t i;
 324
 325         if (!rxq->sw_ring)
 326                 return;
 327
 328         for (i = 0; i < rxq->nb_rx_desc; i++) {
 329                 if (rxq->sw_ring[i]) {
 330                         rte_pktmbuf_free_seg(rxq->sw_ring[i]);
 331                         rxq->sw_ring[i] = NULL;
 332                 }
 333         }
 334
 335         /* for rx bulk */
 336         if (rxq->rx_nb_avail == 0)
 337                 return;
 338         for (i = 0; i < rxq->rx_nb_avail; i++) {
 339                 struct rte_mbuf *mbuf;
 340
 341                 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
 342                 rte_pktmbuf_free_seg(mbuf);
 343         }
 344         rxq->rx_nb_avail = 0;
 345 }
 346
 347 static inline void
 348 release_txq_mbufs(struct iavf_tx_queue *txq)
 349 {
 350         uint16_t i;
 351
 352         if (!txq || !txq->sw_ring) {
 353                 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
 354                 return;
 355         }
 356
 357         for (i = 0; i < txq->nb_tx_desc; i++) {
 358                 if (txq->sw_ring[i].mbuf) {
 359                         rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
 360                         txq->sw_ring[i].mbuf = NULL;
 361                 }
 362         }
 363 }
 364
 365 static const struct iavf_rxq_ops def_rxq_ops = {
 366         .release_mbufs = release_rxq_mbufs,
 367 };
 368
 369 static const struct iavf_txq_ops def_txq_ops = {
 370         .release_mbufs = release_txq_mbufs,
 371 };
 372
 373 static inline void
 374 iavf_rxd_to_pkt_fields_by_comms_ovs(__rte_unused struct iavf_rx_queue *rxq,
 375                                     struct rte_mbuf *mb,
 376                                     volatile union iavf_rx_flex_desc *rxdp)
 377 {
 378         volatile struct iavf_32b_rx_flex_desc_comms_ovs *desc =
 379                         (volatile struct iavf_32b_rx_flex_desc_comms_ovs *)rxdp;
 380 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
 381         uint16_t stat_err;
 382 #endif
 383
 384         if (desc->flow_id != 0xFFFFFFFF) {
 385                 mb->ol_flags |= RTE_MBUF_F_RX_FDIR | RTE_MBUF_F_RX_FDIR_ID;
 386                 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
 387         }
 388
 389 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
 390         stat_err = rte_le_to_cpu_16(desc->status_error0);
 391         if (likely(stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
 392                 mb->ol_flags |= RTE_MBUF_F_RX_RSS_HASH;
 393                 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
 394         }
 395 #endif
 396 }
 397
 398 static inline void
 399 iavf_rxd_to_pkt_fields_by_comms_aux_v1(struct iavf_rx_queue *rxq,
 400                                        struct rte_mbuf *mb,
 401                                        volatile union iavf_rx_flex_desc *rxdp)
 402 {
 403         volatile struct iavf_32b_rx_flex_desc_comms *desc =
 404                         (volatile struct iavf_32b_rx_flex_desc_comms *)rxdp;
 405         uint16_t stat_err;
 406
 407         stat_err = rte_le_to_cpu_16(desc->status_error0);
 408         if (likely(stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
 409                 mb->ol_flags |= RTE_MBUF_F_RX_RSS_HASH;
 410                 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
 411         }
 412
 413 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
 414         if (desc->flow_id != 0xFFFFFFFF) {
 415                 mb->ol_flags |= RTE_MBUF_F_RX_FDIR | RTE_MBUF_F_RX_FDIR_ID;
 416                 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
 417         }
 418
 419         if (rxq->xtr_ol_flag) {
 420                 uint32_t metadata = 0;
 421
 422                 stat_err = rte_le_to_cpu_16(desc->status_error1);
 423
 424                 if (stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS1_XTRMD4_VALID_S))
 425                         metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux0);
 426
 427                 if (stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS1_XTRMD5_VALID_S))
 428                         metadata |=
 429                                 rte_le_to_cpu_16(desc->flex_ts.flex.aux1) << 16;
 430
 431                 if (metadata) {
 432                         mb->ol_flags |= rxq->xtr_ol_flag;
 433
 434                         *RTE_PMD_IFD_DYNF_PROTO_XTR_METADATA(mb) = metadata;
 435                 }
 436         }
 437 #endif
 438 }
 439
 440 static inline void
 441 iavf_rxd_to_pkt_fields_by_comms_aux_v2(struct iavf_rx_queue *rxq,
 442                                        struct rte_mbuf *mb,
 443                                        volatile union iavf_rx_flex_desc *rxdp)
 444 {
 445         volatile struct iavf_32b_rx_flex_desc_comms *desc =
 446                         (volatile struct iavf_32b_rx_flex_desc_comms *)rxdp;
 447         uint16_t stat_err;
 448
 449         stat_err = rte_le_to_cpu_16(desc->status_error0);
 450         if (likely(stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
 451                 mb->ol_flags |= RTE_MBUF_F_RX_RSS_HASH;
 452                 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
 453         }
 454
 455 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
 456         if (desc->flow_id != 0xFFFFFFFF) {
 457                 mb->ol_flags |= RTE_MBUF_F_RX_FDIR | RTE_MBUF_F_RX_FDIR_ID;
 458                 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
 459         }
 460
 461         if (rxq->xtr_ol_flag) {
 462                 uint32_t metadata = 0;
 463
 464                 if (desc->flex_ts.flex.aux0 != 0xFFFF)
 465                         metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux0);
 466                 else if (desc->flex_ts.flex.aux1 != 0xFFFF)
 467                         metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux1);
 468
 469                 if (metadata) {
 470                         mb->ol_flags |= rxq->xtr_ol_flag;
 471
 472                         *RTE_PMD_IFD_DYNF_PROTO_XTR_METADATA(mb) = metadata;
 473                 }
 474         }
 475 #endif
 476 }
 477
 478 static const
 479 iavf_rxd_to_pkt_fields_t rxd_to_pkt_fields_ops[IAVF_RXDID_LAST + 1] = {
 480         [IAVF_RXDID_LEGACY_0] = iavf_rxd_to_pkt_fields_by_comms_ovs,
 481         [IAVF_RXDID_LEGACY_1] = iavf_rxd_to_pkt_fields_by_comms_ovs,
 482         [IAVF_RXDID_COMMS_AUX_VLAN] = iavf_rxd_to_pkt_fields_by_comms_aux_v1,
 483         [IAVF_RXDID_COMMS_AUX_IPV4] = iavf_rxd_to_pkt_fields_by_comms_aux_v1,
 484         [IAVF_RXDID_COMMS_AUX_IPV6] = iavf_rxd_to_pkt_fields_by_comms_aux_v1,
 485         [IAVF_RXDID_COMMS_AUX_IPV6_FLOW] =
 486                 iavf_rxd_to_pkt_fields_by_comms_aux_v1,
 487         [IAVF_RXDID_COMMS_AUX_TCP] = iavf_rxd_to_pkt_fields_by_comms_aux_v1,
 488         [IAVF_RXDID_COMMS_AUX_IP_OFFSET] =
 489                 iavf_rxd_to_pkt_fields_by_comms_aux_v2,
 490         [IAVF_RXDID_COMMS_IPSEC_CRYPTO] =
 491                 iavf_rxd_to_pkt_fields_by_comms_aux_v2,
 492         [IAVF_RXDID_COMMS_OVS_1] = iavf_rxd_to_pkt_fields_by_comms_ovs,
 493 };
 494
 495 static void
 496 iavf_select_rxd_to_pkt_fields_handler(struct iavf_rx_queue *rxq, uint32_t rxdid)
 497 {
 498         rxq->rxdid = rxdid;
 499
 500         switch (rxdid) {
 501         case IAVF_RXDID_COMMS_AUX_VLAN:
 502                 rxq->xtr_ol_flag = rte_pmd_ifd_dynflag_proto_xtr_vlan_mask;
 503                 break;
 504         case IAVF_RXDID_COMMS_AUX_IPV4:
 505                 rxq->xtr_ol_flag = rte_pmd_ifd_dynflag_proto_xtr_ipv4_mask;
 506                 break;
 507         case IAVF_RXDID_COMMS_AUX_IPV6:
 508                 rxq->xtr_ol_flag = rte_pmd_ifd_dynflag_proto_xtr_ipv6_mask;
 509                 break;
 510         case IAVF_RXDID_COMMS_AUX_IPV6_FLOW:
 511                 rxq->xtr_ol_flag =
 512                         rte_pmd_ifd_dynflag_proto_xtr_ipv6_flow_mask;
 513                 break;
 514         case IAVF_RXDID_COMMS_AUX_TCP:
 515                 rxq->xtr_ol_flag = rte_pmd_ifd_dynflag_proto_xtr_tcp_mask;
 516                 break;
 517         case IAVF_RXDID_COMMS_AUX_IP_OFFSET:
 518                 rxq->xtr_ol_flag =
 519                         rte_pmd_ifd_dynflag_proto_xtr_ip_offset_mask;
 520                 break;
 521         case IAVF_RXDID_COMMS_IPSEC_CRYPTO:
 522                 rxq->xtr_ol_flag =
 523                         rte_pmd_ifd_dynflag_proto_xtr_ipsec_crypto_said_mask;
 524                 break;
 525         case IAVF_RXDID_COMMS_OVS_1:
 526         case IAVF_RXDID_LEGACY_0:
 527         case IAVF_RXDID_LEGACY_1:
 528                 break;
 529         default:
 530                 /* update this according to the RXDID for FLEX_DESC_NONE */
 531                 rxq->rxdid = IAVF_RXDID_COMMS_OVS_1;
 532                 break;
 533         }
 534
 535         if (!rte_pmd_ifd_dynf_proto_xtr_metadata_avail())
 536                 rxq->xtr_ol_flag = 0;
 537 }
 538
 539 int
 540 iavf_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 541                        uint16_t nb_desc, unsigned int socket_id,
 542                        const struct rte_eth_rxconf *rx_conf,
 543                        struct rte_mempool *mp)
 544 {
 545         struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 546         struct iavf_adapter *ad =
 547                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 548         struct iavf_info *vf =
 549                 IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 550         struct iavf_vsi *vsi = &vf->vsi;
 551         struct iavf_rx_queue *rxq;
 552         const struct rte_memzone *mz;
 553         uint32_t ring_size;
 554         uint8_t proto_xtr;
 555         uint16_t len;
 556         uint16_t rx_free_thresh;
 557         uint64_t offloads;
 558
 559         PMD_INIT_FUNC_TRACE();
 560
 561         offloads = rx_conf->offloads | dev->data->dev_conf.rxmode.offloads;
 562
 563         if (nb_desc % IAVF_ALIGN_RING_DESC != 0 ||
 564             nb_desc > IAVF_MAX_RING_DESC ||
 565             nb_desc < IAVF_MIN_RING_DESC) {
 566                 PMD_INIT_LOG(ERR, "Number (%u) of receive descriptors is "
 567                              "invalid", nb_desc);
 568                 return -EINVAL;
 569         }
 570
 571         /* Check free threshold */
 572         rx_free_thresh = (rx_conf->rx_free_thresh == 0) ?
 573                          IAVF_DEFAULT_RX_FREE_THRESH :
 574                          rx_conf->rx_free_thresh;
 575         if (check_rx_thresh(nb_desc, rx_free_thresh) != 0)
 576                 return -EINVAL;
 577
 578         /* Free memory if needed */
 579         if (dev->data->rx_queues[queue_idx]) {
 580                 iavf_dev_rx_queue_release(dev, queue_idx);
 581                 dev->data->rx_queues[queue_idx] = NULL;
 582         }
 583
 584         /* Allocate the rx queue data structure */
 585         rxq = rte_zmalloc_socket("iavf rxq",
 586                                  sizeof(struct iavf_rx_queue),
 587                                  RTE_CACHE_LINE_SIZE,
 588                                  socket_id);
 589         if (!rxq) {
 590                 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
 591                              "rx queue data structure");
 592                 return -ENOMEM;
 593         }
 594
 595         if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC) {
 596                 proto_xtr = vf->proto_xtr ? vf->proto_xtr[queue_idx] :
 597                                 IAVF_PROTO_XTR_NONE;
 598                 rxq->rxdid = iavf_proto_xtr_type_to_rxdid(proto_xtr);
 599                 rxq->proto_xtr = proto_xtr;
 600         } else {
 601                 rxq->rxdid = IAVF_RXDID_LEGACY_1;
 602                 rxq->proto_xtr = IAVF_PROTO_XTR_NONE;
 603         }
 604
 605         if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_VLAN_V2) {
 606                 struct virtchnl_vlan_supported_caps *stripping_support =
 607                                 &vf->vlan_v2_caps.offloads.stripping_support;
 608                 uint32_t stripping_cap;
 609
 610                 if (stripping_support->outer)
 611                         stripping_cap = stripping_support->outer;
 612                 else
 613                         stripping_cap = stripping_support->inner;
 614
 615                 if (stripping_cap & VIRTCHNL_VLAN_TAG_LOCATION_L2TAG1)
 616                         rxq->rx_flags = IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG1;
 617                 else if (stripping_cap & VIRTCHNL_VLAN_TAG_LOCATION_L2TAG2_2)
 618                         rxq->rx_flags = IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG2_2;
 619         } else {
 620                 rxq->rx_flags = IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG1;
 621         }
 622
 623         iavf_select_rxd_to_pkt_fields_handler(rxq, rxq->rxdid);
 624
 625         rxq->mp = mp;
 626         rxq->nb_rx_desc = nb_desc;
 627         rxq->rx_free_thresh = rx_free_thresh;
 628         rxq->queue_id = queue_idx;
 629         rxq->port_id = dev->data->port_id;
 630         rxq->rx_deferred_start = rx_conf->rx_deferred_start;
 631         rxq->rx_hdr_len = 0;
 632         rxq->vsi = vsi;
 633         rxq->offloads = offloads;
 634
 635         if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_KEEP_CRC)
 636                 rxq->crc_len = RTE_ETHER_CRC_LEN;
 637         else
 638                 rxq->crc_len = 0;
 639
 640         len = rte_pktmbuf_data_room_size(rxq->mp) - RTE_PKTMBUF_HEADROOM;
 641         rxq->rx_buf_len = RTE_ALIGN_FLOOR(len, (1 << IAVF_RXQ_CTX_DBUFF_SHIFT));
 642
 643         /* Allocate the software ring. */
 644         len = nb_desc + IAVF_RX_MAX_BURST;
 645         rxq->sw_ring =
 646                 rte_zmalloc_socket("iavf rx sw ring",
 647                                    sizeof(struct rte_mbuf *) * len,
 648                                    RTE_CACHE_LINE_SIZE,
 649                                    socket_id);
 650         if (!rxq->sw_ring) {
 651                 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW ring");
 652                 rte_free(rxq);
 653                 return -ENOMEM;
 654         }
 655
 656         /* Allocate the maximum number of RX ring hardware descriptor with
 657          * a little more to support bulk allocate.
 658          */
 659         len = IAVF_MAX_RING_DESC + IAVF_RX_MAX_BURST;
 660         ring_size = RTE_ALIGN(len * sizeof(union iavf_rx_desc),
 661                               IAVF_DMA_MEM_ALIGN);
 662         mz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
 663                                       ring_size, IAVF_RING_BASE_ALIGN,
 664                                       socket_id);
 665         if (!mz) {
 666                 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for RX");
 667                 rte_free(rxq->sw_ring);
 668                 rte_free(rxq);
 669                 return -ENOMEM;
 670         }
 671         /* Zero all the descriptors in the ring. */
 672         memset(mz->addr, 0, ring_size);
 673         rxq->rx_ring_phys_addr = mz->iova;
 674         rxq->rx_ring = (union iavf_rx_desc *)mz->addr;
 675
 676         rxq->mz = mz;
 677         reset_rx_queue(rxq);
 678         rxq->q_set = true;
 679         dev->data->rx_queues[queue_idx] = rxq;
 680         rxq->qrx_tail = hw->hw_addr + IAVF_QRX_TAIL1(rxq->queue_id);
 681         rxq->ops = &def_rxq_ops;
 682
 683         if (check_rx_bulk_allow(rxq) == true) {
 684                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
 685                              "satisfied. Rx Burst Bulk Alloc function will be "
 686                              "used on port=%d, queue=%d.",
 687                              rxq->port_id, rxq->queue_id);
 688         } else {
 689                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
 690                              "not satisfied, Scattered Rx is requested "
 691                              "on port=%d, queue=%d.",
 692                              rxq->port_id, rxq->queue_id);
 693                 ad->rx_bulk_alloc_allowed = false;
 694         }
 695
 696         if (check_rx_vec_allow(rxq) == false)
 697                 ad->rx_vec_allowed = false;
 698
 699         return 0;
 700 }
 701
 702 int
 703 iavf_dev_tx_queue_setup(struct rte_eth_dev *dev,
 704                        uint16_t queue_idx,
 705                        uint16_t nb_desc,
 706                        unsigned int socket_id,
 707                        const struct rte_eth_txconf *tx_conf)
 708 {
 709         struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 710         struct iavf_adapter *adapter =
 711                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 712         struct iavf_info *vf =
 713                 IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 714         struct iavf_tx_queue *txq;
 715         const struct rte_memzone *mz;
 716         uint32_t ring_size;
 717         uint16_t tx_rs_thresh, tx_free_thresh;
 718         uint64_t offloads;
 719
 720         PMD_INIT_FUNC_TRACE();
 721
 722         offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
 723
 724         if (nb_desc % IAVF_ALIGN_RING_DESC != 0 ||
 725             nb_desc > IAVF_MAX_RING_DESC ||
 726             nb_desc < IAVF_MIN_RING_DESC) {
 727                 PMD_INIT_LOG(ERR, "Number (%u) of transmit descriptors is "
 728                             "invalid", nb_desc);
 729                 return -EINVAL;
 730         }
 731
 732         tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
 733                 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
 734         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
 735                 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
 736         if (check_tx_thresh(nb_desc, tx_rs_thresh, tx_free_thresh) != 0)
 737                 return -EINVAL;
 738
 739         /* Free memory if needed. */
 740         if (dev->data->tx_queues[queue_idx]) {
 741                 iavf_dev_tx_queue_release(dev, queue_idx);
 742                 dev->data->tx_queues[queue_idx] = NULL;
 743         }
 744
 745         /* Allocate the TX queue data structure. */
 746         txq = rte_zmalloc_socket("iavf txq",
 747                                  sizeof(struct iavf_tx_queue),
 748                                  RTE_CACHE_LINE_SIZE,
 749                                  socket_id);
 750         if (!txq) {
 751                 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
 752                              "tx queue structure");
 753                 return -ENOMEM;
 754         }
 755
 756         if (adapter->vf.vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_VLAN_V2) {
 757                 struct virtchnl_vlan_supported_caps *insertion_support =
 758                         &adapter->vf.vlan_v2_caps.offloads.insertion_support;
 759                 uint32_t insertion_cap;
 760
 761                 if (insertion_support->outer)
 762                         insertion_cap = insertion_support->outer;
 763                 else
 764                         insertion_cap = insertion_support->inner;
 765
 766                 if (insertion_cap & VIRTCHNL_VLAN_TAG_LOCATION_L2TAG1)
 767                         txq->vlan_flag = IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG1;
 768                 else if (insertion_cap & VIRTCHNL_VLAN_TAG_LOCATION_L2TAG2)
 769                         txq->vlan_flag = IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG2;
 770         } else {
 771                 txq->vlan_flag = IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG1;
 772         }
 773
 774         txq->nb_tx_desc = nb_desc;
 775         txq->rs_thresh = tx_rs_thresh;
 776         txq->free_thresh = tx_free_thresh;
 777         txq->queue_id = queue_idx;
 778         txq->port_id = dev->data->port_id;
 779         txq->offloads = offloads;
 780         txq->tx_deferred_start = tx_conf->tx_deferred_start;
 781
 782         if (iavf_ipsec_crypto_supported(adapter))
 783                 txq->ipsec_crypto_pkt_md_offset =
 784                         iavf_security_get_pkt_md_offset(adapter);
 785
 786         /* Allocate software ring */
 787         txq->sw_ring =
 788                 rte_zmalloc_socket("iavf tx sw ring",
 789                                    sizeof(struct iavf_tx_entry) * nb_desc,
 790                                    RTE_CACHE_LINE_SIZE,
 791                                    socket_id);
 792         if (!txq->sw_ring) {
 793                 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW TX ring");
 794                 rte_free(txq);
 795                 return -ENOMEM;
 796         }
 797
 798         /* Allocate TX hardware ring descriptors. */
 799         ring_size = sizeof(struct iavf_tx_desc) * IAVF_MAX_RING_DESC;
 800         ring_size = RTE_ALIGN(ring_size, IAVF_DMA_MEM_ALIGN);
 801         mz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
 802                                       ring_size, IAVF_RING_BASE_ALIGN,
 803                                       socket_id);
 804         if (!mz) {
 805                 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for TX");
 806                 rte_free(txq->sw_ring);
 807                 rte_free(txq);
 808                 return -ENOMEM;
 809         }
 810         txq->tx_ring_phys_addr = mz->iova;
 811         txq->tx_ring = (struct iavf_tx_desc *)mz->addr;
 812
 813         txq->mz = mz;
 814         reset_tx_queue(txq);
 815         txq->q_set = true;
 816         dev->data->tx_queues[queue_idx] = txq;
 817         txq->qtx_tail = hw->hw_addr + IAVF_QTX_TAIL1(queue_idx);
 818         txq->ops = &def_txq_ops;
 819
 820         if (check_tx_vec_allow(txq) == false) {
 821                 struct iavf_adapter *ad =
 822                         IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 823                 ad->tx_vec_allowed = false;
 824         }
 825
 826         if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_QOS &&
 827             vf->tm_conf.committed) {
 828                 int tc;
 829                 for (tc = 0; tc < vf->qos_cap->num_elem; tc++) {
 830                         if (txq->queue_id >= vf->qtc_map[tc].start_queue_id &&
 831                             txq->queue_id < (vf->qtc_map[tc].start_queue_id +
 832                             vf->qtc_map[tc].queue_count))
 833                                 break;
 834                 }
 835                 if (tc >= vf->qos_cap->num_elem) {
 836                         PMD_INIT_LOG(ERR, "Queue TC mapping is not correct");
 837                         return -EINVAL;
 838                 }
 839                 txq->tc = tc;
 840         }
 841
 842         return 0;
 843 }
 844
 845 int
 846 iavf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 847 {
 848         struct iavf_adapter *adapter =
 849                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 850         struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 851         struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 852         struct iavf_rx_queue *rxq;
 853         int err = 0;
 854
 855         PMD_DRV_FUNC_TRACE();
 856
 857         if (rx_queue_id >= dev->data->nb_rx_queues)
 858                 return -EINVAL;
 859
 860         rxq = dev->data->rx_queues[rx_queue_id];
 861
 862         err = alloc_rxq_mbufs(rxq);
 863         if (err) {
 864                 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
 865                 return err;
 866         }
 867
 868         rte_wmb();
 869
 870         /* Init the RX tail register. */
 871         IAVF_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 872         IAVF_WRITE_FLUSH(hw);
 873
 874         /* Ready to switch the queue on */
 875         if (!vf->lv_enabled)
 876                 err = iavf_switch_queue(adapter, rx_queue_id, true, true);
 877         else
 878                 err = iavf_switch_queue_lv(adapter, rx_queue_id, true, true);
 879
 880         if (err) {
 881                 release_rxq_mbufs(rxq);
 882                 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
 883                             rx_queue_id);
 884         } else {
 885                 dev->data->rx_queue_state[rx_queue_id] =
 886                         RTE_ETH_QUEUE_STATE_STARTED;
 887         }
 888
 889         return err;
 890 }
 891
 892 int
 893 iavf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 894 {
 895         struct iavf_adapter *adapter =
 896                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 897         struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 898         struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 899         struct iavf_tx_queue *txq;
 900         int err = 0;
 901
 902         PMD_DRV_FUNC_TRACE();
 903
 904         if (tx_queue_id >= dev->data->nb_tx_queues)
 905                 return -EINVAL;
 906
 907         txq = dev->data->tx_queues[tx_queue_id];
 908
 909         /* Init the RX tail register. */
 910         IAVF_PCI_REG_WRITE(txq->qtx_tail, 0);
 911         IAVF_WRITE_FLUSH(hw);
 912
 913         /* Ready to switch the queue on */
 914         if (!vf->lv_enabled)
 915                 err = iavf_switch_queue(adapter, tx_queue_id, false, true);
 916         else
 917                 err = iavf_switch_queue_lv(adapter, tx_queue_id, false, true);
 918
 919         if (err)
 920                 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
 921                             tx_queue_id);
 922         else
 923                 dev->data->tx_queue_state[tx_queue_id] =
 924                         RTE_ETH_QUEUE_STATE_STARTED;
 925
 926         return err;
 927 }
 928
 929 int
 930 iavf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 931 {
 932         struct iavf_adapter *adapter =
 933                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 934         struct iavf_rx_queue *rxq;
 935         int err;
 936
 937         PMD_DRV_FUNC_TRACE();
 938
 939         if (rx_queue_id >= dev->data->nb_rx_queues)
 940                 return -EINVAL;
 941
 942         err = iavf_switch_queue(adapter, rx_queue_id, true, false);
 943         if (err) {
 944                 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
 945                             rx_queue_id);
 946                 return err;
 947         }
 948
 949         rxq = dev->data->rx_queues[rx_queue_id];
 950         rxq->ops->release_mbufs(rxq);
 951         reset_rx_queue(rxq);
 952         dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 953
 954         return 0;
 955 }
 956
 957 int
 958 iavf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 959 {
 960         struct iavf_adapter *adapter =
 961                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 962         struct iavf_tx_queue *txq;
 963         int err;
 964
 965         PMD_DRV_FUNC_TRACE();
 966
 967         if (tx_queue_id >= dev->data->nb_tx_queues)
 968                 return -EINVAL;
 969
 970         err = iavf_switch_queue(adapter, tx_queue_id, false, false);
 971         if (err) {
 972                 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u off",
 973                             tx_queue_id);
 974                 return err;
 975         }
 976
 977         txq = dev->data->tx_queues[tx_queue_id];
 978         txq->ops->release_mbufs(txq);
 979         reset_tx_queue(txq);
 980         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 981
 982         return 0;
 983 }
 984
 985 void
 986 iavf_dev_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
 987 {
 988         struct iavf_rx_queue *q = dev->data->rx_queues[qid];
 989
 990         if (!q)
 991                 return;
 992
 993         q->ops->release_mbufs(q);
 994         rte_free(q->sw_ring);
 995         rte_memzone_free(q->mz);
 996         rte_free(q);
 997 }
 998
 999 void
1000 iavf_dev_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
1001 {
1002         struct iavf_tx_queue *q = dev->data->tx_queues[qid];
1003
1004         if (!q)
1005                 return;
1006
1007         q->ops->release_mbufs(q);
1008         rte_free(q->sw_ring);
1009         rte_memzone_free(q->mz);
1010         rte_free(q);
1011 }
1012
1013 void
1014 iavf_stop_queues(struct rte_eth_dev *dev)
1015 {
1016         struct iavf_adapter *adapter =
1017                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1018         struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1019         struct iavf_rx_queue *rxq;
1020         struct iavf_tx_queue *txq;
1021         int ret, i;
1022
1023         /* Stop All queues */
1024         if (!vf->lv_enabled) {
1025                 ret = iavf_disable_queues(adapter);
1026                 if (ret)
1027                         PMD_DRV_LOG(WARNING, "Fail to stop queues");
1028         } else {
1029                 ret = iavf_disable_queues_lv(adapter);
1030                 if (ret)
1031                         PMD_DRV_LOG(WARNING, "Fail to stop queues for large VF");
1032         }
1033
1034         if (ret)
1035                 PMD_DRV_LOG(WARNING, "Fail to stop queues");
1036
1037         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1038                 txq = dev->data->tx_queues[i];
1039                 if (!txq)
1040                         continue;
1041                 txq->ops->release_mbufs(txq);
1042                 reset_tx_queue(txq);
1043                 dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED;
1044         }
1045         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1046                 rxq = dev->data->rx_queues[i];
1047                 if (!rxq)
1048                         continue;
1049                 rxq->ops->release_mbufs(rxq);
1050                 reset_rx_queue(rxq);
1051                 dev->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED;
1052         }
1053 }
1054
1055 #define IAVF_RX_FLEX_ERR0_BITS  \
1056         ((1 << IAVF_RX_FLEX_DESC_STATUS0_HBO_S) |       \
1057          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_IPE_S) |  \
1058          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_L4E_S) |  \
1059          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S) | \
1060          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S) |        \
1061          (1 << IAVF_RX_FLEX_DESC_STATUS0_RXE_S))
1062
1063 static inline void
1064 iavf_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union iavf_rx_desc *rxdp)
1065 {
1066         if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1067                 (1 << IAVF_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
1068                 mb->ol_flags |= RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED;
1069                 mb->vlan_tci =
1070                         rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
1071         } else {
1072                 mb->vlan_tci = 0;
1073         }
1074 }
1075
1076 static inline void
1077 iavf_flex_rxd_to_vlan_tci(struct rte_mbuf *mb,
1078                           volatile union iavf_rx_flex_desc *rxdp)
1079 {
1080         if (rte_le_to_cpu_64(rxdp->wb.status_error0) &
1081                 (1 << IAVF_RX_FLEX_DESC_STATUS0_L2TAG1P_S)) {
1082                 mb->ol_flags |= RTE_MBUF_F_RX_VLAN |
1083                                 RTE_MBUF_F_RX_VLAN_STRIPPED;
1084                 mb->vlan_tci =
1085                         rte_le_to_cpu_16(rxdp->wb.l2tag1);
1086         } else {
1087                 mb->vlan_tci = 0;
1088         }
1089
1090 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
1091         if (rte_le_to_cpu_16(rxdp->wb.status_error1) &
1092             (1 << IAVF_RX_FLEX_DESC_STATUS1_L2TAG2P_S)) {
1093                 mb->ol_flags |= RTE_MBUF_F_RX_QINQ_STRIPPED |
1094                                 RTE_MBUF_F_RX_QINQ |
1095                                 RTE_MBUF_F_RX_VLAN_STRIPPED |
1096                                 RTE_MBUF_F_RX_VLAN;
1097                 mb->vlan_tci_outer = mb->vlan_tci;
1098                 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.l2tag2_2nd);
1099                 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
1100                            rte_le_to_cpu_16(rxdp->wb.l2tag2_1st),
1101                            rte_le_to_cpu_16(rxdp->wb.l2tag2_2nd));
1102         } else {
1103                 mb->vlan_tci_outer = 0;
1104         }
1105 #endif
1106 }
1107
1108 static inline void
1109 iavf_flex_rxd_to_ipsec_crypto_said_get(struct rte_mbuf *mb,
1110                           volatile union iavf_rx_flex_desc *rxdp)
1111 {
1112         volatile struct iavf_32b_rx_flex_desc_comms_ipsec *desc =
1113                 (volatile struct iavf_32b_rx_flex_desc_comms_ipsec *)rxdp;
1114
1115         mb->dynfield1[0] = desc->ipsec_said &
1116                          IAVF_RX_FLEX_DESC_IPSEC_CRYPTO_SAID_MASK;
1117         }
1118
1119 static inline void
1120 iavf_flex_rxd_to_ipsec_crypto_status(struct rte_mbuf *mb,
1121                           volatile union iavf_rx_flex_desc *rxdp,
1122                           struct iavf_ipsec_crypto_stats *stats)
1123 {
1124         uint16_t status1 = rte_le_to_cpu_64(rxdp->wb.status_error1);
1125
1126         if (status1 & BIT(IAVF_RX_FLEX_DESC_STATUS1_IPSEC_CRYPTO_PROCESSED)) {
1127                 uint16_t ipsec_status;
1128
1129                 mb->ol_flags |= RTE_MBUF_F_RX_SEC_OFFLOAD;
1130
1131                 ipsec_status = status1 &
1132                         IAVF_RX_FLEX_DESC_IPSEC_CRYPTO_STATUS_MASK;
1133
1134
1135                 if (unlikely(ipsec_status !=
1136                         IAVF_IPSEC_CRYPTO_STATUS_SUCCESS)) {
1137                         mb->ol_flags |= RTE_MBUF_F_RX_SEC_OFFLOAD_FAILED;
1138
1139                         switch (ipsec_status) {
1140                         case IAVF_IPSEC_CRYPTO_STATUS_SAD_MISS:
1141                                 stats->ierrors.sad_miss++;
1142                                 break;
1143                         case IAVF_IPSEC_CRYPTO_STATUS_NOT_PROCESSED:
1144                                 stats->ierrors.not_processed++;
1145                                 break;
1146                         case IAVF_IPSEC_CRYPTO_STATUS_ICV_CHECK_FAIL:
1147                                 stats->ierrors.icv_check++;
1148                                 break;
1149                         case IAVF_IPSEC_CRYPTO_STATUS_LENGTH_ERR:
1150                                 stats->ierrors.ipsec_length++;
1151                                 break;
1152                         case IAVF_IPSEC_CRYPTO_STATUS_MISC_ERR:
1153                                 stats->ierrors.misc++;
1154                                 break;
1155 }
1156
1157                         stats->ierrors.count++;
1158                         return;
1159                 }
1160
1161                 stats->icount++;
1162                 stats->ibytes += rxdp->wb.pkt_len & 0x3FFF;
1163
1164                 if (rxdp->wb.rxdid == IAVF_RXDID_COMMS_IPSEC_CRYPTO &&
1165                         ipsec_status !=
1166                                 IAVF_IPSEC_CRYPTO_STATUS_SAD_MISS)
1167                         iavf_flex_rxd_to_ipsec_crypto_said_get(mb, rxdp);
1168         }
1169 }
1170
1171
1172 /* Translate the rx descriptor status and error fields to pkt flags */
1173 static inline uint64_t
1174 iavf_rxd_to_pkt_flags(uint64_t qword)
1175 {
1176         uint64_t flags;
1177         uint64_t error_bits = (qword >> IAVF_RXD_QW1_ERROR_SHIFT);
1178
1179 #define IAVF_RX_ERR_BITS 0x3f
1180
1181         /* Check if RSS_HASH */
1182         flags = (((qword >> IAVF_RX_DESC_STATUS_FLTSTAT_SHIFT) &
1183                                         IAVF_RX_DESC_FLTSTAT_RSS_HASH) ==
1184                         IAVF_RX_DESC_FLTSTAT_RSS_HASH) ? RTE_MBUF_F_RX_RSS_HASH : 0;
1185
1186         /* Check if FDIR Match */
1187         flags |= (qword & (1 << IAVF_RX_DESC_STATUS_FLM_SHIFT) ?
1188                                 RTE_MBUF_F_RX_FDIR : 0);
1189
1190         if (likely((error_bits & IAVF_RX_ERR_BITS) == 0)) {
1191                 flags |= (RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_GOOD);
1192                 return flags;
1193         }
1194
1195         if (unlikely(error_bits & (1 << IAVF_RX_DESC_ERROR_IPE_SHIFT)))
1196                 flags |= RTE_MBUF_F_RX_IP_CKSUM_BAD;
1197         else
1198                 flags |= RTE_MBUF_F_RX_IP_CKSUM_GOOD;
1199
1200         if (unlikely(error_bits & (1 << IAVF_RX_DESC_ERROR_L4E_SHIFT)))
1201                 flags |= RTE_MBUF_F_RX_L4_CKSUM_BAD;
1202         else
1203                 flags |= RTE_MBUF_F_RX_L4_CKSUM_GOOD;
1204
1205         /* TODO: Oversize error bit is not processed here */
1206
1207         return flags;
1208 }
1209
1210 static inline uint64_t
1211 iavf_rxd_build_fdir(volatile union iavf_rx_desc *rxdp, struct rte_mbuf *mb)
1212 {
1213         uint64_t flags = 0;
1214 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
1215         uint16_t flexbh;
1216
1217         flexbh = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
1218                 IAVF_RX_DESC_EXT_STATUS_FLEXBH_SHIFT) &
1219                 IAVF_RX_DESC_EXT_STATUS_FLEXBH_MASK;
1220
1221         if (flexbh == IAVF_RX_DESC_EXT_STATUS_FLEXBH_FD_ID) {
1222                 mb->hash.fdir.hi =
1223                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.fd_id);
1224                 flags |= RTE_MBUF_F_RX_FDIR_ID;
1225         }
1226 #else
1227         mb->hash.fdir.hi =
1228                 rte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.fd_id);
1229         flags |= RTE_MBUF_F_RX_FDIR_ID;
1230 #endif
1231         return flags;
1232 }
1233
1234 #define IAVF_RX_FLEX_ERR0_BITS  \
1235         ((1 << IAVF_RX_FLEX_DESC_STATUS0_HBO_S) |       \
1236          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_IPE_S) |  \
1237          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_L4E_S) |  \
1238          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S) | \
1239          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S) |        \
1240          (1 << IAVF_RX_FLEX_DESC_STATUS0_RXE_S))
1241
1242 /* Rx L3/L4 checksum */
1243 static inline uint64_t
1244 iavf_flex_rxd_error_to_pkt_flags(uint16_t stat_err0)
1245 {
1246         uint64_t flags = 0;
1247
1248         /* check if HW has decoded the packet and checksum */
1249         if (unlikely(!(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_L3L4P_S))))
1250                 return 0;
1251
1252         if (likely(!(stat_err0 & IAVF_RX_FLEX_ERR0_BITS))) {
1253                 flags |= (RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_GOOD);
1254                 return flags;
1255         }
1256
1257         if (unlikely(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_IPE_S)))
1258                 flags |= RTE_MBUF_F_RX_IP_CKSUM_BAD;
1259         else
1260                 flags |= RTE_MBUF_F_RX_IP_CKSUM_GOOD;
1261
1262         if (unlikely(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_L4E_S)))
1263                 flags |= RTE_MBUF_F_RX_L4_CKSUM_BAD;
1264         else
1265                 flags |= RTE_MBUF_F_RX_L4_CKSUM_GOOD;
1266
1267         if (unlikely(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S)))
1268                 flags |= RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD;
1269
1270         return flags;
1271 }
1272
1273 /* If the number of free RX descriptors is greater than the RX free
1274  * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1275  * register. Update the RDT with the value of the last processed RX
1276  * descriptor minus 1, to guarantee that the RDT register is never
1277  * equal to the RDH register, which creates a "full" ring situation
1278  * from the hardware point of view.
1279  */
1280 static inline void
1281 iavf_update_rx_tail(struct iavf_rx_queue *rxq, uint16_t nb_hold, uint16_t rx_id)
1282 {
1283         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1284
1285         if (nb_hold > rxq->rx_free_thresh) {
1286                 PMD_RX_LOG(DEBUG,
1287                            "port_id=%u queue_id=%u rx_tail=%u nb_hold=%u",
1288                            rxq->port_id, rxq->queue_id, rx_id, nb_hold);
1289                 rx_id = (uint16_t)((rx_id == 0) ?
1290                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
1291                 IAVF_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
1292                 nb_hold = 0;
1293         }
1294         rxq->nb_rx_hold = nb_hold;
1295 }
1296
1297 /* implement recv_pkts */
1298 uint16_t
1299 iavf_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1300 {
1301         volatile union iavf_rx_desc *rx_ring;
1302         volatile union iavf_rx_desc *rxdp;
1303         struct iavf_rx_queue *rxq;
1304         union iavf_rx_desc rxd;
1305         struct rte_mbuf *rxe;
1306         struct rte_eth_dev *dev;
1307         struct rte_mbuf *rxm;
1308         struct rte_mbuf *nmb;
1309         uint16_t nb_rx;
1310         uint32_t rx_status;
1311         uint64_t qword1;
1312         uint16_t rx_packet_len;
1313         uint16_t rx_id, nb_hold;
1314         uint64_t dma_addr;
1315         uint64_t pkt_flags;
1316         const uint32_t *ptype_tbl;
1317
1318         nb_rx = 0;
1319         nb_hold = 0;
1320         rxq = rx_queue;
1321         rx_id = rxq->rx_tail;
1322         rx_ring = rxq->rx_ring;
1323         ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1324
1325         while (nb_rx < nb_pkts) {
1326                 rxdp = &rx_ring[rx_id];
1327                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1328                 rx_status = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
1329                             IAVF_RXD_QW1_STATUS_SHIFT;
1330
1331                 /* Check the DD bit first */
1332                 if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)))
1333                         break;
1334                 IAVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
1335
1336                 nmb = rte_mbuf_raw_alloc(rxq->mp);
1337                 if (unlikely(!nmb)) {
1338                         dev = &rte_eth_devices[rxq->port_id];
1339                         dev->data->rx_mbuf_alloc_failed++;
1340                         PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1341                                    "queue_id=%u", rxq->port_id, rxq->queue_id);
1342                         break;
1343                 }
1344
1345                 rxd = *rxdp;
1346                 nb_hold++;
1347                 rxe = rxq->sw_ring[rx_id];
1348                 rxq->sw_ring[rx_id] = nmb;
1349                 rx_id++;
1350                 if (unlikely(rx_id == rxq->nb_rx_desc))
1351                         rx_id = 0;
1352
1353                 /* Prefetch next mbuf */
1354                 rte_prefetch0(rxq->sw_ring[rx_id]);
1355
1356                 /* When next RX descriptor is on a cache line boundary,
1357                  * prefetch the next 4 RX descriptors and next 8 pointers
1358                  * to mbufs.
1359                  */
1360                 if ((rx_id & 0x3) == 0) {
1361                         rte_prefetch0(&rx_ring[rx_id]);
1362                         rte_prefetch0(rxq->sw_ring[rx_id]);
1363                 }
1364                 rxm = rxe;
1365                 dma_addr =
1366                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1367                 rxdp->read.hdr_addr = 0;
1368                 rxdp->read.pkt_addr = dma_addr;
1369
1370                 rx_packet_len = ((qword1 & IAVF_RXD_QW1_LENGTH_PBUF_MASK) >>
1371                                 IAVF_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
1372
1373                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1374                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
1375                 rxm->nb_segs = 1;
1376                 rxm->next = NULL;
1377                 rxm->pkt_len = rx_packet_len;
1378                 rxm->data_len = rx_packet_len;
1379                 rxm->port = rxq->port_id;
1380                 rxm->ol_flags = 0;
1381                 iavf_rxd_to_vlan_tci(rxm, &rxd);
1382                 pkt_flags = iavf_rxd_to_pkt_flags(qword1);
1383                 rxm->packet_type =
1384                         ptype_tbl[(uint8_t)((qword1 &
1385                         IAVF_RXD_QW1_PTYPE_MASK) >> IAVF_RXD_QW1_PTYPE_SHIFT)];
1386
1387                 if (pkt_flags & RTE_MBUF_F_RX_RSS_HASH)
1388                         rxm->hash.rss =
1389                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1390
1391                 if (pkt_flags & RTE_MBUF_F_RX_FDIR)
1392                         pkt_flags |= iavf_rxd_build_fdir(&rxd, rxm);
1393
1394                 rxm->ol_flags |= pkt_flags;
1395
1396                 rx_pkts[nb_rx++] = rxm;
1397         }
1398         rxq->rx_tail = rx_id;
1399
1400         iavf_update_rx_tail(rxq, nb_hold, rx_id);
1401
1402         return nb_rx;
1403 }
1404
1405 /* implement recv_pkts for flexible Rx descriptor */
1406 uint16_t
1407 iavf_recv_pkts_flex_rxd(void *rx_queue,
1408                         struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1409 {
1410         volatile union iavf_rx_desc *rx_ring;
1411         volatile union iavf_rx_flex_desc *rxdp;
1412         struct iavf_rx_queue *rxq;
1413         union iavf_rx_flex_desc rxd;
1414         struct rte_mbuf *rxe;
1415         struct rte_eth_dev *dev;
1416         struct rte_mbuf *rxm;
1417         struct rte_mbuf *nmb;
1418         uint16_t nb_rx;
1419         uint16_t rx_stat_err0;
1420         uint16_t rx_packet_len;
1421         uint16_t rx_id, nb_hold;
1422         uint64_t dma_addr;
1423         uint64_t pkt_flags;
1424         const uint32_t *ptype_tbl;
1425
1426         nb_rx = 0;
1427         nb_hold = 0;
1428         rxq = rx_queue;
1429         rx_id = rxq->rx_tail;
1430         rx_ring = rxq->rx_ring;
1431         ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1432
1433         struct iavf_adapter *ad = rxq->vsi->adapter;
1434         uint64_t ts_ns;
1435
1436         if (rxq->offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) {
1437                 uint64_t sw_cur_time = rte_get_timer_cycles() / (rte_get_timer_hz() / 1000);
1438                 if (sw_cur_time - ad->hw_time_update > 4) {
1439                         if (iavf_get_phc_time(ad))
1440                                 PMD_DRV_LOG(ERR, "get physical time failed");
1441                         ad->hw_time_update = sw_cur_time;
1442                 }
1443         }
1444
1445         while (nb_rx < nb_pkts) {
1446                 rxdp = (volatile union iavf_rx_flex_desc *)&rx_ring[rx_id];
1447                 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1448
1449                 /* Check the DD bit first */
1450                 if (!(rx_stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S)))
1451                         break;
1452                 IAVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
1453
1454                 nmb = rte_mbuf_raw_alloc(rxq->mp);
1455                 if (unlikely(!nmb)) {
1456                         dev = &rte_eth_devices[rxq->port_id];
1457                         dev->data->rx_mbuf_alloc_failed++;
1458                         PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1459                                    "queue_id=%u", rxq->port_id, rxq->queue_id);
1460                         break;
1461                 }
1462
1463                 rxd = *rxdp;
1464                 nb_hold++;
1465                 rxe = rxq->sw_ring[rx_id];
1466                 rxq->sw_ring[rx_id] = nmb;
1467                 rx_id++;
1468                 if (unlikely(rx_id == rxq->nb_rx_desc))
1469                         rx_id = 0;
1470
1471                 /* Prefetch next mbuf */
1472                 rte_prefetch0(rxq->sw_ring[rx_id]);
1473
1474                 /* When next RX descriptor is on a cache line boundary,
1475                  * prefetch the next 4 RX descriptors and next 8 pointers
1476                  * to mbufs.
1477                  */
1478                 if ((rx_id & 0x3) == 0) {
1479                         rte_prefetch0(&rx_ring[rx_id]);
1480                         rte_prefetch0(rxq->sw_ring[rx_id]);
1481                 }
1482                 rxm = rxe;
1483                 dma_addr =
1484                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1485                 rxdp->read.hdr_addr = 0;
1486                 rxdp->read.pkt_addr = dma_addr;
1487
1488                 rx_packet_len = (rte_le_to_cpu_16(rxd.wb.pkt_len) &
1489                                 IAVF_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
1490
1491                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1492                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
1493                 rxm->nb_segs = 1;
1494                 rxm->next = NULL;
1495                 rxm->pkt_len = rx_packet_len;
1496                 rxm->data_len = rx_packet_len;
1497                 rxm->port = rxq->port_id;
1498                 rxm->ol_flags = 0;
1499                 rxm->packet_type = ptype_tbl[IAVF_RX_FLEX_DESC_PTYPE_M &
1500                         rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
1501                 iavf_flex_rxd_to_vlan_tci(rxm, &rxd);
1502                 iavf_flex_rxd_to_ipsec_crypto_status(rxm, &rxd,
1503                                 &rxq->stats.ipsec_crypto);
1504                 rxd_to_pkt_fields_ops[rxq->rxdid](rxq, rxm, &rxd);
1505                 pkt_flags = iavf_flex_rxd_error_to_pkt_flags(rx_stat_err0);
1506
1507                 if (iavf_timestamp_dynflag > 0) {
1508                         ts_ns = iavf_tstamp_convert_32b_64b(ad->phc_time,
1509                                 rte_le_to_cpu_32(rxd.wb.flex_ts.ts_high));
1510
1511                         ad->phc_time = ts_ns;
1512                         ad->hw_time_update = rte_get_timer_cycles() / (rte_get_timer_hz() / 1000);
1513
1514                         *RTE_MBUF_DYNFIELD(rxm,
1515                                 iavf_timestamp_dynfield_offset,
1516                                 rte_mbuf_timestamp_t *) = ts_ns;
1517                         rxm->ol_flags |= iavf_timestamp_dynflag;
1518                 }
1519
1520                 rxm->ol_flags |= pkt_flags;
1521
1522                 rx_pkts[nb_rx++] = rxm;
1523         }
1524         rxq->rx_tail = rx_id;
1525
1526         iavf_update_rx_tail(rxq, nb_hold, rx_id);
1527
1528         return nb_rx;
1529 }
1530
1531 /* implement recv_scattered_pkts for flexible Rx descriptor */
1532 uint16_t
1533 iavf_recv_scattered_pkts_flex_rxd(void *rx_queue, struct rte_mbuf **rx_pkts,
1534                                   uint16_t nb_pkts)
1535 {
1536         struct iavf_rx_queue *rxq = rx_queue;
1537         union iavf_rx_flex_desc rxd;
1538         struct rte_mbuf *rxe;
1539         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1540         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1541         struct rte_mbuf *nmb, *rxm;
1542         uint16_t rx_id = rxq->rx_tail;
1543         uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
1544         struct rte_eth_dev *dev;
1545         uint16_t rx_stat_err0;
1546         uint64_t dma_addr;
1547         uint64_t pkt_flags;
1548         struct iavf_adapter *ad = rxq->vsi->adapter;
1549         uint64_t ts_ns;
1550
1551         volatile union iavf_rx_desc *rx_ring = rxq->rx_ring;
1552         volatile union iavf_rx_flex_desc *rxdp;
1553         const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1554
1555         if (rxq->offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) {
1556                 uint64_t sw_cur_time = rte_get_timer_cycles() / (rte_get_timer_hz() / 1000);
1557                 if (sw_cur_time - ad->hw_time_update > 4) {
1558                         if (iavf_get_phc_time(ad))
1559                                 PMD_DRV_LOG(ERR, "get physical time failed");
1560                         ad->hw_time_update = sw_cur_time;
1561                 }
1562         }
1563
1564         while (nb_rx < nb_pkts) {
1565                 rxdp = (volatile union iavf_rx_flex_desc *)&rx_ring[rx_id];
1566                 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1567
1568                 /* Check the DD bit */
1569                 if (!(rx_stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S)))
1570                         break;
1571                 IAVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
1572
1573                 nmb = rte_mbuf_raw_alloc(rxq->mp);
1574                 if (unlikely(!nmb)) {
1575                         PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1576                                    "queue_id=%u", rxq->port_id, rxq->queue_id);
1577                         dev = &rte_eth_devices[rxq->port_id];
1578                         dev->data->rx_mbuf_alloc_failed++;
1579                         break;
1580                 }
1581
1582                 rxd = *rxdp;
1583                 nb_hold++;
1584                 rxe = rxq->sw_ring[rx_id];
1585                 rxq->sw_ring[rx_id] = nmb;
1586                 rx_id++;
1587                 if (rx_id == rxq->nb_rx_desc)
1588                         rx_id = 0;
1589
1590                 /* Prefetch next mbuf */
1591                 rte_prefetch0(rxq->sw_ring[rx_id]);
1592
1593                 /* When next RX descriptor is on a cache line boundary,
1594                  * prefetch the next 4 RX descriptors and next 8 pointers
1595                  * to mbufs.
1596                  */
1597                 if ((rx_id & 0x3) == 0) {
1598                         rte_prefetch0(&rx_ring[rx_id]);
1599                         rte_prefetch0(rxq->sw_ring[rx_id]);
1600                 }
1601
1602                 rxm = rxe;
1603                 dma_addr =
1604                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1605
1606                 /* Set data buffer address and data length of the mbuf */
1607                 rxdp->read.hdr_addr = 0;
1608                 rxdp->read.pkt_addr = dma_addr;
1609                 rx_packet_len = rte_le_to_cpu_16(rxd.wb.pkt_len) &
1610                                 IAVF_RX_FLX_DESC_PKT_LEN_M;
1611                 rxm->data_len = rx_packet_len;
1612                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1613
1614                 /* If this is the first buffer of the received packet, set the
1615                  * pointer to the first mbuf of the packet and initialize its
1616                  * context. Otherwise, update the total length and the number
1617                  * of segments of the current scattered packet, and update the
1618                  * pointer to the last mbuf of the current packet.
1619                  */
1620                 if (!first_seg) {
1621                         first_seg = rxm;
1622                         first_seg->nb_segs = 1;
1623                         first_seg->pkt_len = rx_packet_len;
1624                 } else {
1625                         first_seg->pkt_len =
1626                                 (uint16_t)(first_seg->pkt_len +
1627                                                 rx_packet_len);
1628                         first_seg->nb_segs++;
1629                         last_seg->next = rxm;
1630                 }
1631
1632                 /* If this is not the last buffer of the received packet,
1633                  * update the pointer to the last mbuf of the current scattered
1634                  * packet and continue to parse the RX ring.
1635                  */
1636                 if (!(rx_stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_EOF_S))) {
1637                         last_seg = rxm;
1638                         continue;
1639                 }
1640
1641                 /* This is the last buffer of the received packet. If the CRC
1642                  * is not stripped by the hardware:
1643                  *  - Subtract the CRC length from the total packet length.
1644                  *  - If the last buffer only contains the whole CRC or a part
1645                  *  of it, free the mbuf associated to the last buffer. If part
1646                  *  of the CRC is also contained in the previous mbuf, subtract
1647                  *  the length of that CRC part from the data length of the
1648                  *  previous mbuf.
1649                  */
1650                 rxm->next = NULL;
1651                 if (unlikely(rxq->crc_len > 0)) {
1652                         first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
1653                         if (rx_packet_len <= RTE_ETHER_CRC_LEN) {
1654                                 rte_pktmbuf_free_seg(rxm);
1655                                 first_seg->nb_segs--;
1656                                 last_seg->data_len =
1657                                         (uint16_t)(last_seg->data_len -
1658                                         (RTE_ETHER_CRC_LEN - rx_packet_len));
1659                                 last_seg->next = NULL;
1660                         } else {
1661                                 rxm->data_len = (uint16_t)(rx_packet_len -
1662                                                         RTE_ETHER_CRC_LEN);
1663                         }
1664                 }
1665
1666                 first_seg->port = rxq->port_id;
1667                 first_seg->ol_flags = 0;
1668                 first_seg->packet_type = ptype_tbl[IAVF_RX_FLEX_DESC_PTYPE_M &
1669                         rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
1670                 iavf_flex_rxd_to_vlan_tci(first_seg, &rxd);
1671                 iavf_flex_rxd_to_ipsec_crypto_status(first_seg, &rxd,
1672                                 &rxq->stats.ipsec_crypto);
1673                 rxd_to_pkt_fields_ops[rxq->rxdid](rxq, first_seg, &rxd);
1674                 pkt_flags = iavf_flex_rxd_error_to_pkt_flags(rx_stat_err0);
1675
1676                 if (iavf_timestamp_dynflag > 0) {
1677                         ts_ns = iavf_tstamp_convert_32b_64b(ad->phc_time,
1678                                 rte_le_to_cpu_32(rxd.wb.flex_ts.ts_high));
1679
1680                         ad->phc_time = ts_ns;
1681                         ad->hw_time_update = rte_get_timer_cycles() / (rte_get_timer_hz() / 1000);
1682
1683                         *RTE_MBUF_DYNFIELD(first_seg,
1684                                 iavf_timestamp_dynfield_offset,
1685                                 rte_mbuf_timestamp_t *) = ts_ns;
1686                         first_seg->ol_flags |= iavf_timestamp_dynflag;
1687                 }
1688
1689                 first_seg->ol_flags |= pkt_flags;
1690
1691                 /* Prefetch data of first segment, if configured to do so. */
1692                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1693                                           first_seg->data_off));
1694                 rx_pkts[nb_rx++] = first_seg;
1695                 first_seg = NULL;
1696         }
1697
1698         /* Record index of the next RX descriptor to probe. */
1699         rxq->rx_tail = rx_id;
1700         rxq->pkt_first_seg = first_seg;
1701         rxq->pkt_last_seg = last_seg;
1702
1703         iavf_update_rx_tail(rxq, nb_hold, rx_id);
1704
1705         return nb_rx;
1706 }
1707
1708 /* implement recv_scattered_pkts  */
1709 uint16_t
1710 iavf_recv_scattered_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1711                         uint16_t nb_pkts)
1712 {
1713         struct iavf_rx_queue *rxq = rx_queue;
1714         union iavf_rx_desc rxd;
1715         struct rte_mbuf *rxe;
1716         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1717         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1718         struct rte_mbuf *nmb, *rxm;
1719         uint16_t rx_id = rxq->rx_tail;
1720         uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
1721         struct rte_eth_dev *dev;
1722         uint32_t rx_status;
1723         uint64_t qword1;
1724         uint64_t dma_addr;
1725         uint64_t pkt_flags;
1726
1727         volatile union iavf_rx_desc *rx_ring = rxq->rx_ring;
1728         volatile union iavf_rx_desc *rxdp;
1729         const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1730
1731         while (nb_rx < nb_pkts) {
1732                 rxdp = &rx_ring[rx_id];
1733                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1734                 rx_status = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
1735                             IAVF_RXD_QW1_STATUS_SHIFT;
1736
1737                 /* Check the DD bit */
1738                 if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)))
1739                         break;
1740                 IAVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
1741
1742                 nmb = rte_mbuf_raw_alloc(rxq->mp);
1743                 if (unlikely(!nmb)) {
1744                         PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1745                                    "queue_id=%u", rxq->port_id, rxq->queue_id);
1746                         dev = &rte_eth_devices[rxq->port_id];
1747                         dev->data->rx_mbuf_alloc_failed++;
1748                         break;
1749                 }
1750
1751                 rxd = *rxdp;
1752                 nb_hold++;
1753                 rxe = rxq->sw_ring[rx_id];
1754                 rxq->sw_ring[rx_id] = nmb;
1755                 rx_id++;
1756                 if (rx_id == rxq->nb_rx_desc)
1757                         rx_id = 0;
1758
1759                 /* Prefetch next mbuf */
1760                 rte_prefetch0(rxq->sw_ring[rx_id]);
1761
1762                 /* When next RX descriptor is on a cache line boundary,
1763                  * prefetch the next 4 RX descriptors and next 8 pointers
1764                  * to mbufs.
1765                  */
1766                 if ((rx_id & 0x3) == 0) {
1767                         rte_prefetch0(&rx_ring[rx_id]);
1768                         rte_prefetch0(rxq->sw_ring[rx_id]);
1769                 }
1770
1771                 rxm = rxe;
1772                 dma_addr =
1773                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1774
1775                 /* Set data buffer address and data length of the mbuf */
1776                 rxdp->read.hdr_addr = 0;
1777                 rxdp->read.pkt_addr = dma_addr;
1778                 rx_packet_len = (qword1 & IAVF_RXD_QW1_LENGTH_PBUF_MASK) >>
1779                                  IAVF_RXD_QW1_LENGTH_PBUF_SHIFT;
1780                 rxm->data_len = rx_packet_len;
1781                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1782
1783                 /* If this is the first buffer of the received packet, set the
1784                  * pointer to the first mbuf of the packet and initialize its
1785                  * context. Otherwise, update the total length and the number
1786                  * of segments of the current scattered packet, and update the
1787                  * pointer to the last mbuf of the current packet.
1788                  */
1789                 if (!first_seg) {
1790                         first_seg = rxm;
1791                         first_seg->nb_segs = 1;
1792                         first_seg->pkt_len = rx_packet_len;
1793                 } else {
1794                         first_seg->pkt_len =
1795                                 (uint16_t)(first_seg->pkt_len +
1796                                                 rx_packet_len);
1797                         first_seg->nb_segs++;
1798                         last_seg->next = rxm;
1799                 }
1800
1801                 /* If this is not the last buffer of the received packet,
1802                  * update the pointer to the last mbuf of the current scattered
1803                  * packet and continue to parse the RX ring.
1804                  */
1805                 if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_EOF_SHIFT))) {
1806                         last_seg = rxm;
1807                         continue;
1808                 }
1809
1810                 /* This is the last buffer of the received packet. If the CRC
1811                  * is not stripped by the hardware:
1812                  *  - Subtract the CRC length from the total packet length.
1813                  *  - If the last buffer only contains the whole CRC or a part
1814                  *  of it, free the mbuf associated to the last buffer. If part
1815                  *  of the CRC is also contained in the previous mbuf, subtract
1816                  *  the length of that CRC part from the data length of the
1817                  *  previous mbuf.
1818                  */
1819                 rxm->next = NULL;
1820                 if (unlikely(rxq->crc_len > 0)) {
1821                         first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
1822                         if (rx_packet_len <= RTE_ETHER_CRC_LEN) {
1823                                 rte_pktmbuf_free_seg(rxm);
1824                                 first_seg->nb_segs--;
1825                                 last_seg->data_len =
1826                                         (uint16_t)(last_seg->data_len -
1827                                         (RTE_ETHER_CRC_LEN - rx_packet_len));
1828                                 last_seg->next = NULL;
1829                         } else
1830                                 rxm->data_len = (uint16_t)(rx_packet_len -
1831                                                         RTE_ETHER_CRC_LEN);
1832                 }
1833
1834                 first_seg->port = rxq->port_id;
1835                 first_seg->ol_flags = 0;
1836                 iavf_rxd_to_vlan_tci(first_seg, &rxd);
1837                 pkt_flags = iavf_rxd_to_pkt_flags(qword1);
1838                 first_seg->packet_type =
1839                         ptype_tbl[(uint8_t)((qword1 &
1840                         IAVF_RXD_QW1_PTYPE_MASK) >> IAVF_RXD_QW1_PTYPE_SHIFT)];
1841
1842                 if (pkt_flags & RTE_MBUF_F_RX_RSS_HASH)
1843                         first_seg->hash.rss =
1844                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1845
1846                 if (pkt_flags & RTE_MBUF_F_RX_FDIR)
1847                         pkt_flags |= iavf_rxd_build_fdir(&rxd, first_seg);
1848
1849                 first_seg->ol_flags |= pkt_flags;
1850
1851                 /* Prefetch data of first segment, if configured to do so. */
1852                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1853                                           first_seg->data_off));
1854                 rx_pkts[nb_rx++] = first_seg;
1855                 first_seg = NULL;
1856         }
1857
1858         /* Record index of the next RX descriptor to probe. */
1859         rxq->rx_tail = rx_id;
1860         rxq->pkt_first_seg = first_seg;
1861         rxq->pkt_last_seg = last_seg;
1862
1863         iavf_update_rx_tail(rxq, nb_hold, rx_id);
1864
1865         return nb_rx;
1866 }
1867
1868 #define IAVF_LOOK_AHEAD 8
1869 static inline int
1870 iavf_rx_scan_hw_ring_flex_rxd(struct iavf_rx_queue *rxq,
1871                             struct rte_mbuf **rx_pkts,
1872                             uint16_t nb_pkts)
1873 {
1874         volatile union iavf_rx_flex_desc *rxdp;
1875         struct rte_mbuf **rxep;
1876         struct rte_mbuf *mb;
1877         uint16_t stat_err0;
1878         uint16_t pkt_len;
1879         int32_t s[IAVF_LOOK_AHEAD], var, nb_dd;
1880         int32_t i, j, nb_rx = 0;
1881         int32_t nb_staged = 0;
1882         uint64_t pkt_flags;
1883         const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1884         struct iavf_adapter *ad = rxq->vsi->adapter;
1885         uint64_t ts_ns;
1886
1887         rxdp = (volatile union iavf_rx_flex_desc *)&rxq->rx_ring[rxq->rx_tail];
1888         rxep = &rxq->sw_ring[rxq->rx_tail];
1889
1890         stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1891
1892         /* Make sure there is at least 1 packet to receive */
1893         if (!(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S)))
1894                 return 0;
1895
1896         if (rxq->offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) {
1897                 uint64_t sw_cur_time = rte_get_timer_cycles() / (rte_get_timer_hz() / 1000);
1898                 if (sw_cur_time - ad->hw_time_update > 4) {
1899                         if (iavf_get_phc_time(ad))
1900                                 PMD_DRV_LOG(ERR, "get physical time failed");
1901                         ad->hw_time_update = sw_cur_time;
1902                 }
1903         }
1904
1905         /* Scan LOOK_AHEAD descriptors at a time to determine which
1906          * descriptors reference packets that are ready to be received.
1907          */
1908         for (i = 0; i < IAVF_RX_MAX_BURST; i += IAVF_LOOK_AHEAD,
1909              rxdp += IAVF_LOOK_AHEAD, rxep += IAVF_LOOK_AHEAD) {
1910                 /* Read desc statuses backwards to avoid race condition */
1911                 for (j = IAVF_LOOK_AHEAD - 1; j >= 0; j--)
1912                         s[j] = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1913
1914                 /* This barrier is to order loads of different words in the descriptor */
1915                 rte_atomic_thread_fence(__ATOMIC_ACQUIRE);
1916
1917                 /* Compute how many contiguous DD bits were set */
1918                 for (j = 0, nb_dd = 0; j < IAVF_LOOK_AHEAD; j++) {
1919                         var = s[j] & (1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S);
1920 #ifdef RTE_ARCH_ARM
1921                         /* For Arm platforms, count only contiguous descriptors
1922                          * whose DD bit is set to 1. On Arm platforms, reads of
1923                          * descriptors can be reordered. Since the CPU may
1924                          * be reading the descriptors as the NIC updates them
1925                          * in memory, it is possbile that the DD bit for a
1926                          * descriptor earlier in the queue is read as not set
1927                          * while the DD bit for a descriptor later in the queue
1928                          * is read as set.
1929                          */
1930                         if (var)
1931                                 nb_dd += 1;
1932                         else
1933                                 break;
1934 #else
1935                         nb_dd += var;
1936 #endif
1937                 }
1938
1939                 /* Translate descriptor info to mbuf parameters */
1940                 for (j = 0; j < nb_dd; j++) {
1941                         IAVF_DUMP_RX_DESC(rxq, &rxdp[j],
1942                                           rxq->rx_tail +
1943                                           i * IAVF_LOOK_AHEAD + j);
1944
1945                         mb = rxep[j];
1946                         pkt_len = (rte_le_to_cpu_16(rxdp[j].wb.pkt_len) &
1947                                 IAVF_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
1948                         mb->data_len = pkt_len;
1949                         mb->pkt_len = pkt_len;
1950                         mb->ol_flags = 0;
1951
1952                         mb->packet_type = ptype_tbl[IAVF_RX_FLEX_DESC_PTYPE_M &
1953                                 rte_le_to_cpu_16(rxdp[j].wb.ptype_flex_flags0)];
1954                         iavf_flex_rxd_to_vlan_tci(mb, &rxdp[j]);
1955                         iavf_flex_rxd_to_ipsec_crypto_status(mb, &rxdp[j],
1956                                 &rxq->stats.ipsec_crypto);
1957                         rxd_to_pkt_fields_ops[rxq->rxdid](rxq, mb, &rxdp[j]);
1958                         stat_err0 = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1959                         pkt_flags = iavf_flex_rxd_error_to_pkt_flags(stat_err0);
1960
1961                         if (iavf_timestamp_dynflag > 0) {
1962                                 ts_ns = iavf_tstamp_convert_32b_64b(ad->phc_time,
1963                                         rte_le_to_cpu_32(rxdp[j].wb.flex_ts.ts_high));
1964
1965                                 ad->phc_time = ts_ns;
1966                                 ad->hw_time_update = rte_get_timer_cycles() / (rte_get_timer_hz() / 1000);
1967
1968                                 *RTE_MBUF_DYNFIELD(mb,
1969                                         iavf_timestamp_dynfield_offset,
1970                                         rte_mbuf_timestamp_t *) = ts_ns;
1971                                 mb->ol_flags |= iavf_timestamp_dynflag;
1972                         }
1973
1974                         mb->ol_flags |= pkt_flags;
1975
1976                         /* Put up to nb_pkts directly into buffers */
1977                         if ((i + j) < nb_pkts) {
1978                                 rx_pkts[i + j] = rxep[j];
1979                                 nb_rx++;
1980                         } else {
1981                                 /* Stage excess pkts received */
1982                                 rxq->rx_stage[nb_staged] = rxep[j];
1983                                 nb_staged++;
1984                         }
1985                 }
1986
1987                 if (nb_dd != IAVF_LOOK_AHEAD)
1988                         break;
1989         }
1990
1991         /* Update rxq->rx_nb_avail to reflect number of staged pkts */
1992         rxq->rx_nb_avail = nb_staged;
1993
1994         /* Clear software ring entries */
1995         for (i = 0; i < (nb_rx + nb_staged); i++)
1996                 rxq->sw_ring[rxq->rx_tail + i] = NULL;
1997
1998         return nb_rx;
1999 }
2000
2001 static inline int
2002 iavf_rx_scan_hw_ring(struct iavf_rx_queue *rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
2003 {
2004         volatile union iavf_rx_desc *rxdp;
2005         struct rte_mbuf **rxep;
2006         struct rte_mbuf *mb;
2007         uint16_t pkt_len;
2008         uint64_t qword1;
2009         uint32_t rx_status;
2010         int32_t s[IAVF_LOOK_AHEAD], var, nb_dd;
2011         int32_t i, j, nb_rx = 0;
2012         int32_t nb_staged = 0;
2013         uint64_t pkt_flags;
2014         const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
2015
2016         rxdp = &rxq->rx_ring[rxq->rx_tail];
2017         rxep = &rxq->sw_ring[rxq->rx_tail];
2018
2019         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
2020         rx_status = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
2021                     IAVF_RXD_QW1_STATUS_SHIFT;
2022
2023         /* Make sure there is at least 1 packet to receive */
2024         if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)))
2025                 return 0;
2026
2027         /* Scan LOOK_AHEAD descriptors at a time to determine which
2028          * descriptors reference packets that are ready to be received.
2029          */
2030         for (i = 0; i < IAVF_RX_MAX_BURST; i += IAVF_LOOK_AHEAD,
2031              rxdp += IAVF_LOOK_AHEAD, rxep += IAVF_LOOK_AHEAD) {
2032                 /* Read desc statuses backwards to avoid race condition */
2033                 for (j = IAVF_LOOK_AHEAD - 1; j >= 0; j--) {
2034                         qword1 = rte_le_to_cpu_64(
2035                                 rxdp[j].wb.qword1.status_error_len);
2036                         s[j] = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
2037                                IAVF_RXD_QW1_STATUS_SHIFT;
2038                 }
2039
2040                 /* This barrier is to order loads of different words in the descriptor */
2041                 rte_atomic_thread_fence(__ATOMIC_ACQUIRE);
2042
2043                 /* Compute how many contiguous DD bits were set */
2044                 for (j = 0, nb_dd = 0; j < IAVF_LOOK_AHEAD; j++) {
2045                         var = s[j] & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT);
2046 #ifdef RTE_ARCH_ARM
2047                         /* For Arm platforms, count only contiguous descriptors
2048                          * whose DD bit is set to 1. On Arm platforms, reads of
2049                          * descriptors can be reordered. Since the CPU may
2050                          * be reading the descriptors as the NIC updates them
2051                          * in memory, it is possbile that the DD bit for a
2052                          * descriptor earlier in the queue is read as not set
2053                          * while the DD bit for a descriptor later in the queue
2054                          * is read as set.
2055                          */
2056                         if (var)
2057                                 nb_dd += 1;
2058                         else
2059                                 break;
2060 #else
2061                         nb_dd += var;
2062 #endif
2063                 }
2064
2065                 /* Translate descriptor info to mbuf parameters */
2066                 for (j = 0; j < nb_dd; j++) {
2067                         IAVF_DUMP_RX_DESC(rxq, &rxdp[j],
2068                                          rxq->rx_tail + i * IAVF_LOOK_AHEAD + j);
2069
2070                         mb = rxep[j];
2071                         qword1 = rte_le_to_cpu_64
2072                                         (rxdp[j].wb.qword1.status_error_len);
2073                         pkt_len = ((qword1 & IAVF_RXD_QW1_LENGTH_PBUF_MASK) >>
2074                                   IAVF_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
2075                         mb->data_len = pkt_len;
2076                         mb->pkt_len = pkt_len;
2077                         mb->ol_flags = 0;
2078                         iavf_rxd_to_vlan_tci(mb, &rxdp[j]);
2079                         pkt_flags = iavf_rxd_to_pkt_flags(qword1);
2080                         mb->packet_type =
2081                                 ptype_tbl[(uint8_t)((qword1 &
2082                                 IAVF_RXD_QW1_PTYPE_MASK) >>
2083                                 IAVF_RXD_QW1_PTYPE_SHIFT)];
2084
2085                         if (pkt_flags & RTE_MBUF_F_RX_RSS_HASH)
2086                                 mb->hash.rss = rte_le_to_cpu_32(
2087                                         rxdp[j].wb.qword0.hi_dword.rss);
2088
2089                         if (pkt_flags & RTE_MBUF_F_RX_FDIR)
2090                                 pkt_flags |= iavf_rxd_build_fdir(&rxdp[j], mb);
2091
2092                         mb->ol_flags |= pkt_flags;
2093
2094                         /* Put up to nb_pkts directly into buffers */
2095                         if ((i + j) < nb_pkts) {
2096                                 rx_pkts[i + j] = rxep[j];
2097                                 nb_rx++;
2098                         } else { /* Stage excess pkts received */
2099                                 rxq->rx_stage[nb_staged] = rxep[j];
2100                                 nb_staged++;
2101                         }
2102                 }
2103
2104                 if (nb_dd != IAVF_LOOK_AHEAD)
2105                         break;
2106         }
2107
2108         /* Update rxq->rx_nb_avail to reflect number of staged pkts */
2109         rxq->rx_nb_avail = nb_staged;
2110
2111         /* Clear software ring entries */
2112         for (i = 0; i < (nb_rx + nb_staged); i++)
2113                 rxq->sw_ring[rxq->rx_tail + i] = NULL;
2114
2115         return nb_rx;
2116 }
2117
2118 static inline uint16_t
2119 iavf_rx_fill_from_stage(struct iavf_rx_queue *rxq,
2120                        struct rte_mbuf **rx_pkts,
2121                        uint16_t nb_pkts)
2122 {
2123         uint16_t i;
2124         struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
2125
2126         nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
2127
2128         for (i = 0; i < nb_pkts; i++)
2129                 rx_pkts[i] = stage[i];
2130
2131         rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
2132         rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
2133
2134         return nb_pkts;
2135 }
2136
2137 static inline int
2138 iavf_rx_alloc_bufs(struct iavf_rx_queue *rxq)
2139 {
2140         volatile union iavf_rx_desc *rxdp;
2141         struct rte_mbuf **rxep;
2142         struct rte_mbuf *mb;
2143         uint16_t alloc_idx, i;
2144         uint64_t dma_addr;
2145         int diag;
2146
2147         /* Allocate buffers in bulk */
2148         alloc_idx = (uint16_t)(rxq->rx_free_trigger -
2149                                 (rxq->rx_free_thresh - 1));
2150         rxep = &rxq->sw_ring[alloc_idx];
2151         diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
2152                                     rxq->rx_free_thresh);
2153         if (unlikely(diag != 0)) {
2154                 PMD_RX_LOG(ERR, "Failed to get mbufs in bulk");
2155                 return -ENOMEM;
2156         }
2157
2158         rxdp = &rxq->rx_ring[alloc_idx];
2159         for (i = 0; i < rxq->rx_free_thresh; i++) {
2160                 if (likely(i < (rxq->rx_free_thresh - 1)))
2161                         /* Prefetch next mbuf */
2162                         rte_prefetch0(rxep[i + 1]);
2163
2164                 mb = rxep[i];
2165                 rte_mbuf_refcnt_set(mb, 1);
2166                 mb->next = NULL;
2167                 mb->data_off = RTE_PKTMBUF_HEADROOM;
2168                 mb->nb_segs = 1;
2169                 mb->port = rxq->port_id;
2170                 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mb));
2171                 rxdp[i].read.hdr_addr = 0;
2172                 rxdp[i].read.pkt_addr = dma_addr;
2173         }
2174
2175         /* Update rx tail register */
2176         rte_wmb();
2177         IAVF_PCI_REG_WC_WRITE_RELAXED(rxq->qrx_tail, rxq->rx_free_trigger);
2178
2179         rxq->rx_free_trigger =
2180                 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
2181         if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
2182                 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2183
2184         return 0;
2185 }
2186
2187 static inline uint16_t
2188 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
2189 {
2190         struct iavf_rx_queue *rxq = (struct iavf_rx_queue *)rx_queue;
2191         uint16_t nb_rx = 0;
2192
2193         if (!nb_pkts)
2194                 return 0;
2195
2196         if (rxq->rx_nb_avail)
2197                 return iavf_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
2198
2199         if (rxq->rxdid >= IAVF_RXDID_FLEX_NIC && rxq->rxdid <= IAVF_RXDID_LAST)
2200                 nb_rx = (uint16_t)iavf_rx_scan_hw_ring_flex_rxd(rxq, rx_pkts, nb_pkts);
2201         else
2202                 nb_rx = (uint16_t)iavf_rx_scan_hw_ring(rxq, rx_pkts, nb_pkts);
2203
2204         rxq->rx_next_avail = 0;
2205         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx + rxq->rx_nb_avail);
2206
2207         if (rxq->rx_tail > rxq->rx_free_trigger) {
2208                 if (iavf_rx_alloc_bufs(rxq) != 0) {
2209                         uint16_t i, j, nb_staged;
2210
2211                         /* TODO: count rx_mbuf_alloc_failed here */
2212
2213                         nb_staged = rxq->rx_nb_avail;
2214                         rxq->rx_nb_avail = 0;
2215
2216                         rxq->rx_tail = (uint16_t)(rxq->rx_tail - (nb_rx + nb_staged));
2217                         for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++) {
2218                                 rxq->sw_ring[j] = rx_pkts[i];
2219                                 rx_pkts[i] = NULL;
2220                         }
2221                         for (i = 0, j = rxq->rx_tail + nb_rx; i < nb_staged; i++, j++) {
2222                                 rxq->sw_ring[j] = rxq->rx_stage[i];
2223                                 rx_pkts[i] = NULL;
2224                         }
2225
2226                         return 0;
2227                 }
2228         }
2229
2230         if (rxq->rx_tail >= rxq->nb_rx_desc)
2231                 rxq->rx_tail = 0;
2232
2233         PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u, nb_rx=%u",
2234                    rxq->port_id, rxq->queue_id,
2235                    rxq->rx_tail, nb_rx);
2236
2237         return nb_rx;
2238 }
2239
2240 static uint16_t
2241 iavf_recv_pkts_bulk_alloc(void *rx_queue,
2242                          struct rte_mbuf **rx_pkts,
2243                          uint16_t nb_pkts)
2244 {
2245         uint16_t nb_rx = 0, n, count;
2246
2247         if (unlikely(nb_pkts == 0))
2248                 return 0;
2249
2250         if (likely(nb_pkts <= IAVF_RX_MAX_BURST))
2251                 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
2252
2253         while (nb_pkts) {
2254                 n = RTE_MIN(nb_pkts, IAVF_RX_MAX_BURST);
2255                 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
2256                 nb_rx = (uint16_t)(nb_rx + count);
2257                 nb_pkts = (uint16_t)(nb_pkts - count);
2258                 if (count < n)
2259                         break;
2260         }
2261
2262         return nb_rx;
2263 }
2264
2265 static inline int
2266 iavf_xmit_cleanup(struct iavf_tx_queue *txq)
2267 {
2268         struct iavf_tx_entry *sw_ring = txq->sw_ring;
2269         uint16_t last_desc_cleaned = txq->last_desc_cleaned;
2270         uint16_t nb_tx_desc = txq->nb_tx_desc;
2271         uint16_t desc_to_clean_to;
2272         uint16_t nb_tx_to_clean;
2273
2274         volatile struct iavf_tx_desc *txd = txq->tx_ring;
2275
2276         desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->rs_thresh);
2277         if (desc_to_clean_to >= nb_tx_desc)
2278                 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
2279
2280         desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
2281         if ((txd[desc_to_clean_to].cmd_type_offset_bsz &
2282                         rte_cpu_to_le_64(IAVF_TXD_QW1_DTYPE_MASK)) !=
2283                         rte_cpu_to_le_64(IAVF_TX_DESC_DTYPE_DESC_DONE)) {
2284                 PMD_TX_LOG(DEBUG, "TX descriptor %4u is not done "
2285                            "(port=%d queue=%d)", desc_to_clean_to,
2286                            txq->port_id, txq->queue_id);
2287                 return -1;
2288         }
2289
2290         if (last_desc_cleaned > desc_to_clean_to)
2291                 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
2292                                                         desc_to_clean_to);
2293         else
2294                 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
2295                                         last_desc_cleaned);
2296
2297         txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
2298
2299         txq->last_desc_cleaned = desc_to_clean_to;
2300         txq->nb_free = (uint16_t)(txq->nb_free + nb_tx_to_clean);
2301
2302         return 0;
2303 }
2304
2305 /* Check if the context descriptor is needed for TX offloading */
2306 static inline uint16_t
2307 iavf_calc_context_desc(uint64_t flags, uint8_t vlan_flag)
2308 {
2309         if (flags & (RTE_MBUF_F_TX_TCP_SEG | RTE_MBUF_F_TX_UDP_SEG |
2310                         RTE_MBUF_F_TX_TUNNEL_MASK))
2311                 return 1;
2312         if (flags & RTE_MBUF_F_TX_VLAN &&
2313             vlan_flag & IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG2)
2314                 return 1;
2315         return 0;
2316 }
2317
2318 static inline void
2319 iavf_fill_ctx_desc_cmd_field(volatile uint64_t *field, struct rte_mbuf *m,
2320                 uint8_t vlan_flag)
2321 {
2322         uint64_t cmd = 0;
2323
2324         /* TSO enabled */
2325         if (m->ol_flags & (RTE_MBUF_F_TX_TCP_SEG | RTE_MBUF_F_TX_UDP_SEG))
2326                 cmd = IAVF_TX_CTX_DESC_TSO << IAVF_TXD_CTX_QW1_CMD_SHIFT;
2327
2328         if (m->ol_flags & RTE_MBUF_F_TX_VLAN &&
2329                         vlan_flag & IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG2) {
2330                 cmd |= IAVF_TX_CTX_DESC_IL2TAG2
2331                         << IAVF_TXD_CTX_QW1_CMD_SHIFT;
2332         }
2333
2334         *field |= cmd;
2335 }
2336
2337 static inline void
2338 iavf_fill_ctx_desc_ipsec_field(volatile uint64_t *field,
2339         struct iavf_ipsec_crypto_pkt_metadata *ipsec_md)
2340 {
2341         uint64_t ipsec_field =
2342                 (uint64_t)ipsec_md->ctx_desc_ipsec_params <<
2343                         IAVF_TXD_CTX_QW1_IPSEC_PARAMS_CIPHERBLK_SHIFT;
2344
2345         *field |= ipsec_field;
2346 }
2347
2348
2349 static inline void
2350 iavf_fill_ctx_desc_tunnelling_field(volatile uint64_t *qw0,
2351                 const struct rte_mbuf *m)
2352 {
2353         uint64_t eip_typ = IAVF_TX_CTX_DESC_EIPT_NONE;
2354         uint64_t eip_len = 0;
2355         uint64_t eip_noinc = 0;
2356         /* Default - IP_ID is increment in each segment of LSO */
2357
2358         switch (m->ol_flags & (RTE_MBUF_F_TX_OUTER_IPV4 |
2359                         RTE_MBUF_F_TX_OUTER_IPV6 |
2360                         RTE_MBUF_F_TX_OUTER_IP_CKSUM)) {
2361         case RTE_MBUF_F_TX_OUTER_IPV4:
2362                 eip_typ = IAVF_TX_CTX_DESC_EIPT_IPV4_NO_CHECKSUM_OFFLOAD;
2363                 eip_len = m->outer_l3_len >> 2;
2364         break;
2365         case RTE_MBUF_F_TX_OUTER_IPV4 | RTE_MBUF_F_TX_OUTER_IP_CKSUM:
2366                 eip_typ = IAVF_TX_CTX_DESC_EIPT_IPV4_CHECKSUM_OFFLOAD;
2367                 eip_len = m->outer_l3_len >> 2;
2368         break;
2369         case RTE_MBUF_F_TX_OUTER_IPV6:
2370                 eip_typ = IAVF_TX_CTX_DESC_EIPT_IPV6;
2371                 eip_len = m->outer_l3_len >> 2;
2372         break;
2373         }
2374
2375         *qw0 = eip_typ << IAVF_TXD_CTX_QW0_TUN_PARAMS_EIPT_SHIFT |
2376                 eip_len << IAVF_TXD_CTX_QW0_TUN_PARAMS_EIPLEN_SHIFT |
2377                 eip_noinc << IAVF_TXD_CTX_QW0_TUN_PARAMS_EIP_NOINC_SHIFT;
2378 }
2379
2380 static inline uint16_t
2381 iavf_fill_ctx_desc_segmentation_field(volatile uint64_t *field,
2382         struct rte_mbuf *m, struct iavf_ipsec_crypto_pkt_metadata *ipsec_md)
2383 {
2384         uint64_t segmentation_field = 0;
2385         uint64_t total_length = 0;
2386
2387         if (m->ol_flags & RTE_MBUF_F_TX_SEC_OFFLOAD) {
2388                 total_length = ipsec_md->l4_payload_len;
2389         } else {
2390                 total_length = m->pkt_len - (m->l2_len + m->l3_len + m->l4_len);
2391
2392                 if (m->ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK)
2393                         total_length -= m->outer_l3_len;
2394         }
2395
2396 #ifdef RTE_LIBRTE_IAVF_DEBUG_TX
2397         if (!m->l4_len || !m->tso_segsz)
2398                 PMD_TX_LOG(DEBUG, "L4 length %d, LSO Segment size %d",
2399                          m->l4_len, m->tso_segsz);
2400         if (m->tso_segsz < 88)
2401                 PMD_TX_LOG(DEBUG, "LSO Segment size %d is less than minimum %d",
2402                         m->tso_segsz, 88);
2403 #endif
2404         segmentation_field =
2405                 (((uint64_t)total_length << IAVF_TXD_CTX_QW1_TSO_LEN_SHIFT) &
2406                                 IAVF_TXD_CTX_QW1_TSO_LEN_MASK) |
2407                 (((uint64_t)m->tso_segsz << IAVF_TXD_CTX_QW1_MSS_SHIFT) &
2408                                 IAVF_TXD_CTX_QW1_MSS_MASK);
2409
2410         *field |= segmentation_field;
2411
2412         return total_length;
2413 }
2414
2415
2416 struct iavf_tx_context_desc_qws {
2417         __le64 qw0;
2418         __le64 qw1;
2419 };
2420
2421 static inline void
2422 iavf_fill_context_desc(volatile struct iavf_tx_context_desc *desc,
2423         struct rte_mbuf *m, struct iavf_ipsec_crypto_pkt_metadata *ipsec_md,
2424         uint16_t *tlen, uint8_t vlan_flag)
2425 {
2426         volatile struct iavf_tx_context_desc_qws *desc_qws =
2427                         (volatile struct iavf_tx_context_desc_qws *)desc;
2428         /* fill descriptor type field */
2429         desc_qws->qw1 = IAVF_TX_DESC_DTYPE_CONTEXT;
2430
2431         /* fill command field */
2432         iavf_fill_ctx_desc_cmd_field(&desc_qws->qw1, m, vlan_flag);
2433
2434         /* fill segmentation field */
2435         if (m->ol_flags & (RTE_MBUF_F_TX_TCP_SEG | RTE_MBUF_F_TX_UDP_SEG)) {
2436                 /* fill IPsec field */
2437                 if (m->ol_flags & RTE_MBUF_F_TX_SEC_OFFLOAD)
2438                         iavf_fill_ctx_desc_ipsec_field(&desc_qws->qw1,
2439                                 ipsec_md);
2440
2441                 *tlen = iavf_fill_ctx_desc_segmentation_field(&desc_qws->qw1,
2442                                 m, ipsec_md);
2443         }
2444
2445         /* fill tunnelling field */
2446         if (m->ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK)
2447                 iavf_fill_ctx_desc_tunnelling_field(&desc_qws->qw0, m);
2448         else
2449                 desc_qws->qw0 = 0;
2450
2451         desc_qws->qw0 = rte_cpu_to_le_64(desc_qws->qw0);
2452         desc_qws->qw1 = rte_cpu_to_le_64(desc_qws->qw1);
2453
2454         if (vlan_flag & IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG2)
2455                 desc->l2tag2 = m->vlan_tci;
2456 }
2457
2458
2459 static inline void
2460 iavf_fill_ipsec_desc(volatile struct iavf_tx_ipsec_desc *desc,
2461         const struct iavf_ipsec_crypto_pkt_metadata *md, uint16_t *ipsec_len)
2462 {
2463         desc->qw0 = rte_cpu_to_le_64(((uint64_t)md->l4_payload_len <<
2464                 IAVF_IPSEC_TX_DESC_QW0_L4PAYLEN_SHIFT) |
2465                 ((uint64_t)md->esn << IAVF_IPSEC_TX_DESC_QW0_IPSECESN_SHIFT) |
2466                 ((uint64_t)md->esp_trailer_len <<
2467                                 IAVF_IPSEC_TX_DESC_QW0_TRAILERLEN_SHIFT));
2468
2469         desc->qw1 = rte_cpu_to_le_64(((uint64_t)md->sa_idx <<
2470                 IAVF_IPSEC_TX_DESC_QW1_IPSECSA_SHIFT) |
2471                 ((uint64_t)md->next_proto <<
2472                                 IAVF_IPSEC_TX_DESC_QW1_IPSECNH_SHIFT) |
2473                 ((uint64_t)(md->len_iv & 0x3) <<
2474                                 IAVF_IPSEC_TX_DESC_QW1_IVLEN_SHIFT) |
2475                 ((uint64_t)(md->ol_flags & IAVF_IPSEC_CRYPTO_OL_FLAGS_NATT ?
2476                                 1ULL : 0ULL) <<
2477                                 IAVF_IPSEC_TX_DESC_QW1_UDP_SHIFT) |
2478                 (uint64_t)IAVF_TX_DESC_DTYPE_IPSEC);
2479
2480         /**
2481          * TODO: Pre-calculate this in the Session initialization
2482          *
2483          * Calculate IPsec length required in data descriptor func when TSO
2484          * offload is enabled
2485          */
2486         *ipsec_len = sizeof(struct rte_esp_hdr) + (md->len_iv >> 2) +
2487                         (md->ol_flags & IAVF_IPSEC_CRYPTO_OL_FLAGS_NATT ?
2488                         sizeof(struct rte_udp_hdr) : 0);
2489 }
2490
2491 static inline void
2492 iavf_build_data_desc_cmd_offset_fields(volatile uint64_t *qw1,
2493                 struct rte_mbuf *m, uint8_t vlan_flag)
2494 {
2495         uint64_t command = 0;
2496         uint64_t offset = 0;
2497         uint64_t l2tag1 = 0;
2498
2499         *qw1 = IAVF_TX_DESC_DTYPE_DATA;
2500
2501         command = (uint64_t)IAVF_TX_DESC_CMD_ICRC;
2502
2503         /* Descriptor based VLAN insertion */
2504         if ((vlan_flag & IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG1) &&
2505                         m->ol_flags & RTE_MBUF_F_TX_VLAN) {
2506                 command |= (uint64_t)IAVF_TX_DESC_CMD_IL2TAG1;
2507                 l2tag1 |= m->vlan_tci;
2508         }
2509
2510         /* Set MACLEN */
2511         offset |= (m->l2_len >> 1) << IAVF_TX_DESC_LENGTH_MACLEN_SHIFT;
2512
2513         /* Enable L3 checksum offloading inner */
2514         if (m->ol_flags & (RTE_MBUF_F_TX_IP_CKSUM | RTE_MBUF_F_TX_IPV4)) {
2515                 command |= IAVF_TX_DESC_CMD_IIPT_IPV4_CSUM;
2516                 offset |= (m->l3_len >> 2) << IAVF_TX_DESC_LENGTH_IPLEN_SHIFT;
2517         } else if (m->ol_flags & RTE_MBUF_F_TX_IPV4) {
2518                 command |= IAVF_TX_DESC_CMD_IIPT_IPV4;
2519                 offset |= (m->l3_len >> 2) << IAVF_TX_DESC_LENGTH_IPLEN_SHIFT;
2520         } else if (m->ol_flags & RTE_MBUF_F_TX_IPV6) {
2521                 command |= IAVF_TX_DESC_CMD_IIPT_IPV6;
2522                 offset |= (m->l3_len >> 2) << IAVF_TX_DESC_LENGTH_IPLEN_SHIFT;
2523         }
2524
2525         if (m->ol_flags & RTE_MBUF_F_TX_TCP_SEG) {
2526                 command |= IAVF_TX_DESC_CMD_L4T_EOFT_TCP;
2527                 offset |= (m->l4_len >> 2) <<
2528                               IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2529         }
2530
2531         /* Enable L4 checksum offloads */
2532         switch (m->ol_flags & RTE_MBUF_F_TX_L4_MASK) {
2533         case RTE_MBUF_F_TX_TCP_CKSUM:
2534                 command |= IAVF_TX_DESC_CMD_L4T_EOFT_TCP;
2535                 offset |= (sizeof(struct rte_tcp_hdr) >> 2) <<
2536                                 IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2537                 break;
2538         case RTE_MBUF_F_TX_SCTP_CKSUM:
2539                 command |= IAVF_TX_DESC_CMD_L4T_EOFT_SCTP;
2540                 offset |= (sizeof(struct rte_sctp_hdr) >> 2) <<
2541                                 IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2542                 break;
2543         case RTE_MBUF_F_TX_UDP_CKSUM:
2544                 command |= IAVF_TX_DESC_CMD_L4T_EOFT_UDP;
2545                 offset |= (sizeof(struct rte_udp_hdr) >> 2) <<
2546                                 IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2547                 break;
2548         }
2549
2550         *qw1 = rte_cpu_to_le_64((((uint64_t)command <<
2551                 IAVF_TXD_DATA_QW1_CMD_SHIFT) & IAVF_TXD_DATA_QW1_CMD_MASK) |
2552                 (((uint64_t)offset << IAVF_TXD_DATA_QW1_OFFSET_SHIFT) &
2553                 IAVF_TXD_DATA_QW1_OFFSET_MASK) |
2554                 ((uint64_t)l2tag1 << IAVF_TXD_DATA_QW1_L2TAG1_SHIFT));
2555 }
2556
2557 static inline void
2558 iavf_fill_data_desc(volatile struct iavf_tx_desc *desc,
2559         struct rte_mbuf *m, uint64_t desc_template,
2560         uint16_t tlen, uint16_t ipseclen)
2561 {
2562         uint32_t hdrlen = m->l2_len;
2563         uint32_t bufsz = 0;
2564
2565         /* fill data descriptor qw1 from template */
2566         desc->cmd_type_offset_bsz = desc_template;
2567
2568         /* set data buffer address */
2569         desc->buffer_addr = rte_mbuf_data_iova(m);
2570
2571         /* calculate data buffer size less set header lengths */
2572         if ((m->ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK) &&
2573                         (m->ol_flags & (RTE_MBUF_F_TX_TCP_SEG |
2574                                         RTE_MBUF_F_TX_UDP_SEG))) {
2575                 hdrlen += m->outer_l3_len;
2576                 if (m->ol_flags & RTE_MBUF_F_TX_L4_MASK)
2577                         hdrlen += m->l3_len + m->l4_len;
2578                 else
2579                         hdrlen += m->l3_len;
2580                 if (m->ol_flags & RTE_MBUF_F_TX_SEC_OFFLOAD)
2581                         hdrlen += ipseclen;
2582                 bufsz = hdrlen + tlen;
2583         } else if ((m->ol_flags & RTE_MBUF_F_TX_SEC_OFFLOAD) &&
2584                         (m->ol_flags & (RTE_MBUF_F_TX_TCP_SEG |
2585                                         RTE_MBUF_F_TX_UDP_SEG))) {
2586                 hdrlen += m->outer_l3_len + m->l3_len + ipseclen;
2587                 if (m->ol_flags & RTE_MBUF_F_TX_L4_MASK)
2588                         hdrlen += m->l4_len;
2589                 bufsz = hdrlen + tlen;
2590
2591         } else {
2592                 bufsz = m->data_len;
2593         }
2594
2595         /* set data buffer size */
2596         desc->cmd_type_offset_bsz |=
2597                 (((uint64_t)bufsz << IAVF_TXD_DATA_QW1_TX_BUF_SZ_SHIFT) &
2598                 IAVF_TXD_DATA_QW1_TX_BUF_SZ_MASK);
2599
2600         desc->buffer_addr = rte_cpu_to_le_64(desc->buffer_addr);
2601         desc->cmd_type_offset_bsz = rte_cpu_to_le_64(desc->cmd_type_offset_bsz);
2602 }
2603
2604
2605 static struct iavf_ipsec_crypto_pkt_metadata *
2606 iavf_ipsec_crypto_get_pkt_metadata(const struct iavf_tx_queue *txq,
2607                 struct rte_mbuf *m)
2608 {
2609         if (m->ol_flags & RTE_MBUF_F_TX_SEC_OFFLOAD)
2610                 return RTE_MBUF_DYNFIELD(m, txq->ipsec_crypto_pkt_md_offset,
2611                                 struct iavf_ipsec_crypto_pkt_metadata *);
2612
2613         return NULL;
2614 }
2615
2616 /* TX function */
2617 uint16_t
2618 iavf_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2619 {
2620         struct iavf_tx_queue *txq = tx_queue;
2621         volatile struct iavf_tx_desc *txr = txq->tx_ring;
2622         struct iavf_tx_entry *txe_ring = txq->sw_ring;
2623         struct iavf_tx_entry *txe, *txn;
2624         struct rte_mbuf *mb, *mb_seg;
2625         uint16_t desc_idx, desc_idx_last;
2626         uint16_t idx;
2627
2628
2629         /* Check if the descriptor ring needs to be cleaned. */
2630         if (txq->nb_free < txq->free_thresh)
2631                 iavf_xmit_cleanup(txq);
2632
2633         desc_idx = txq->tx_tail;
2634         txe = &txe_ring[desc_idx];
2635
2636 #ifdef RTE_LIBRTE_IAVF_DEBUG_TX_DESC_RING
2637                 iavf_dump_tx_entry_ring(txq);
2638                 iavf_dump_tx_desc_ring(txq);
2639 #endif
2640
2641
2642         for (idx = 0; idx < nb_pkts; idx++) {
2643                 volatile struct iavf_tx_desc *ddesc;
2644                 struct iavf_ipsec_crypto_pkt_metadata *ipsec_md;
2645
2646                 uint16_t nb_desc_ctx, nb_desc_ipsec;
2647                 uint16_t nb_desc_data, nb_desc_required;
2648                 uint16_t tlen = 0, ipseclen = 0;
2649                 uint64_t ddesc_template = 0;
2650                 uint64_t ddesc_cmd = 0;
2651
2652                 mb = tx_pkts[idx];
2653
2654                 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
2655
2656                 /**
2657                  * Get metadata for ipsec crypto from mbuf dynamic fields if
2658                  * security offload is specified.
2659                  */
2660                 ipsec_md = iavf_ipsec_crypto_get_pkt_metadata(txq, mb);
2661
2662                 nb_desc_data = mb->nb_segs;
2663                 nb_desc_ctx =
2664                         iavf_calc_context_desc(mb->ol_flags, txq->vlan_flag);
2665                 nb_desc_ipsec = !!(mb->ol_flags & RTE_MBUF_F_TX_SEC_OFFLOAD);
2666
2667                 /**
2668                  * The number of descriptors that must be allocated for
2669                  * a packet equals to the number of the segments of that
2670                  * packet plus the context and ipsec descriptors if needed.
2671                  */
2672                 nb_desc_required = nb_desc_data + nb_desc_ctx + nb_desc_ipsec;
2673
2674                 desc_idx_last = (uint16_t)(desc_idx + nb_desc_required - 1);
2675
2676                 /* wrap descriptor ring */
2677                 if (desc_idx_last >= txq->nb_tx_desc)
2678                         desc_idx_last =
2679                                 (uint16_t)(desc_idx_last - txq->nb_tx_desc);
2680
2681                 PMD_TX_LOG(DEBUG,
2682                         "port_id=%u queue_id=%u tx_first=%u tx_last=%u",
2683                         txq->port_id, txq->queue_id, desc_idx, desc_idx_last);
2684
2685                 if (nb_desc_required > txq->nb_free) {
2686                         if (iavf_xmit_cleanup(txq)) {
2687                                 if (idx == 0)
2688                                         return 0;
2689                                 goto end_of_tx;
2690                         }
2691                         if (unlikely(nb_desc_required > txq->rs_thresh)) {
2692                                 while (nb_desc_required > txq->nb_free) {
2693                                         if (iavf_xmit_cleanup(txq)) {
2694                                                 if (idx == 0)
2695                                                         return 0;
2696                                                 goto end_of_tx;
2697                                         }
2698                                 }
2699                         }
2700                 }
2701
2702                 iavf_build_data_desc_cmd_offset_fields(&ddesc_template, mb,
2703                         txq->vlan_flag);
2704
2705                         /* Setup TX context descriptor if required */
2706                 if (nb_desc_ctx) {
2707                         volatile struct iavf_tx_context_desc *ctx_desc =
2708                                 (volatile struct iavf_tx_context_desc *)
2709                                         &txr[desc_idx];
2710
2711                         /* clear QW0 or the previous writeback value
2712                          * may impact next write
2713                          */
2714                         *(volatile uint64_t *)ctx_desc = 0;
2715
2716                         txn = &txe_ring[txe->next_id];
2717                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
2718
2719                         if (txe->mbuf) {
2720                                 rte_pktmbuf_free_seg(txe->mbuf);
2721                                 txe->mbuf = NULL;
2722                         }
2723
2724                         iavf_fill_context_desc(ctx_desc, mb, ipsec_md, &tlen,
2725                                 txq->vlan_flag);
2726                         IAVF_DUMP_TX_DESC(txq, ctx_desc, desc_idx);
2727
2728                         txe->last_id = desc_idx_last;
2729                         desc_idx = txe->next_id;
2730                         txe = txn;
2731                         }
2732
2733                 if (nb_desc_ipsec) {
2734                         volatile struct iavf_tx_ipsec_desc *ipsec_desc =
2735                                 (volatile struct iavf_tx_ipsec_desc *)
2736                                         &txr[desc_idx];
2737
2738                         txn = &txe_ring[txe->next_id];
2739                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
2740
2741                         if (txe->mbuf) {
2742                                 rte_pktmbuf_free_seg(txe->mbuf);
2743                                 txe->mbuf = NULL;
2744                 }
2745
2746                         iavf_fill_ipsec_desc(ipsec_desc, ipsec_md, &ipseclen);
2747
2748                         IAVF_DUMP_TX_DESC(txq, ipsec_desc, desc_idx);
2749
2750                         txe->last_id = desc_idx_last;
2751                         desc_idx = txe->next_id;
2752                         txe = txn;
2753                 }
2754
2755                 mb_seg = mb;
2756
2757                 do {
2758                         ddesc = (volatile struct iavf_tx_desc *)
2759                                         &txr[desc_idx];
2760
2761                         txn = &txe_ring[txe->next_id];
2762                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
2763
2764                         if (txe->mbuf)
2765                                 rte_pktmbuf_free_seg(txe->mbuf);
2766
2767                         txe->mbuf = mb_seg;
2768                         iavf_fill_data_desc(ddesc, mb_seg,
2769                                         ddesc_template, tlen, ipseclen);
2770
2771                         IAVF_DUMP_TX_DESC(txq, ddesc, desc_idx);
2772
2773                         txe->last_id = desc_idx_last;
2774                         desc_idx = txe->next_id;
2775                         txe = txn;
2776                         mb_seg = mb_seg->next;
2777                 } while (mb_seg);
2778
2779                 /* The last packet data descriptor needs End Of Packet (EOP) */
2780                 ddesc_cmd = IAVF_TX_DESC_CMD_EOP;
2781
2782                 txq->nb_used = (uint16_t)(txq->nb_used + nb_desc_required);
2783                 txq->nb_free = (uint16_t)(txq->nb_free - nb_desc_required);
2784
2785                 if (txq->nb_used >= txq->rs_thresh) {
2786                         PMD_TX_LOG(DEBUG, "Setting RS bit on TXD id="
2787                                    "%4u (port=%d queue=%d)",
2788                                    desc_idx_last, txq->port_id, txq->queue_id);
2789
2790                         ddesc_cmd |= IAVF_TX_DESC_CMD_RS;
2791
2792                         /* Update txq RS bit counters */
2793                         txq->nb_used = 0;
2794                 }
2795
2796                 ddesc->cmd_type_offset_bsz |= rte_cpu_to_le_64(ddesc_cmd <<
2797                                 IAVF_TXD_DATA_QW1_CMD_SHIFT);
2798
2799                 IAVF_DUMP_TX_DESC(txq, ddesc, desc_idx - 1);
2800         }
2801
2802 end_of_tx:
2803         rte_wmb();
2804
2805         PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
2806                    txq->port_id, txq->queue_id, desc_idx, idx);
2807
2808         IAVF_PCI_REG_WRITE_RELAXED(txq->qtx_tail, desc_idx);
2809         txq->tx_tail = desc_idx;
2810
2811         return idx;
2812 }
2813
2814 /* Check if the packet with vlan user priority is transmitted in the
2815  * correct queue.
2816  */
2817 static int
2818 iavf_check_vlan_up2tc(struct iavf_tx_queue *txq, struct rte_mbuf *m)
2819 {
2820         struct rte_eth_dev *dev = &rte_eth_devices[txq->port_id];
2821         struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2822         uint16_t up;
2823
2824         up = m->vlan_tci >> IAVF_VLAN_TAG_PCP_OFFSET;
2825
2826         if (!(vf->qos_cap->cap[txq->tc].tc_prio & BIT(up))) {
2827                 PMD_TX_LOG(ERR, "packet with vlan pcp %u cannot transmit in queue %u\n",
2828                         up, txq->queue_id);
2829                 return -1;
2830         } else {
2831                 return 0;
2832         }
2833 }
2834
2835 /* TX prep functions */
2836 uint16_t
2837 iavf_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
2838               uint16_t nb_pkts)
2839 {
2840         int i, ret;
2841         uint64_t ol_flags;
2842         struct rte_mbuf *m;
2843         struct iavf_tx_queue *txq = tx_queue;
2844         struct rte_eth_dev *dev = &rte_eth_devices[txq->port_id];
2845         struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2846
2847         for (i = 0; i < nb_pkts; i++) {
2848                 m = tx_pkts[i];
2849                 ol_flags = m->ol_flags;
2850
2851                 /* Check condition for nb_segs > IAVF_TX_MAX_MTU_SEG. */
2852                 if (!(ol_flags & RTE_MBUF_F_TX_TCP_SEG)) {
2853                         if (m->nb_segs > IAVF_TX_MAX_MTU_SEG) {
2854                                 rte_errno = EINVAL;
2855                                 return i;
2856                         }
2857                 } else if ((m->tso_segsz < IAVF_MIN_TSO_MSS) ||
2858                            (m->tso_segsz > IAVF_MAX_TSO_MSS)) {
2859                         /* MSS outside the range are considered malicious */
2860                         rte_errno = EINVAL;
2861                         return i;
2862                 }
2863
2864                 if (ol_flags & IAVF_TX_OFFLOAD_NOTSUP_MASK) {
2865                         rte_errno = ENOTSUP;
2866                         return i;
2867                 }
2868
2869 #ifdef RTE_ETHDEV_DEBUG_TX
2870                 ret = rte_validate_tx_offload(m);
2871                 if (ret != 0) {
2872                         rte_errno = -ret;
2873                         return i;
2874                 }
2875 #endif
2876                 ret = rte_net_intel_cksum_prepare(m);
2877                 if (ret != 0) {
2878                         rte_errno = -ret;
2879                         return i;
2880                 }
2881
2882                 if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_QOS &&
2883                     ol_flags & (RTE_MBUF_F_RX_VLAN_STRIPPED | RTE_MBUF_F_RX_VLAN)) {
2884                         ret = iavf_check_vlan_up2tc(txq, m);
2885                         if (ret != 0) {
2886                                 rte_errno = -ret;
2887                                 return i;
2888                         }
2889                 }
2890         }
2891
2892         return i;
2893 }
2894
2895 /* choose rx function*/
2896 void
2897 iavf_set_rx_function(struct rte_eth_dev *dev)
2898 {
2899         struct iavf_adapter *adapter =
2900                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2901         struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2902         int i;
2903         struct iavf_rx_queue *rxq;
2904         bool use_flex = true;
2905
2906         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2907                 rxq = dev->data->rx_queues[i];
2908                 if (rxq->rxdid <= IAVF_RXDID_LEGACY_1) {
2909                         PMD_DRV_LOG(NOTICE, "request RXDID[%d] in Queue[%d] is legacy, "
2910                                 "set rx_pkt_burst as legacy for all queues", rxq->rxdid, i);
2911                         use_flex = false;
2912                 } else if (!(vf->supported_rxdid & BIT(rxq->rxdid))) {
2913                         PMD_DRV_LOG(NOTICE, "request RXDID[%d] in Queue[%d] is not supported, "
2914                                 "set rx_pkt_burst as legacy for all queues", rxq->rxdid, i);
2915                         use_flex = false;
2916                 }
2917         }
2918
2919 #ifdef RTE_ARCH_X86
2920         int check_ret;
2921         bool use_avx2 = false;
2922         bool use_avx512 = false;
2923
2924         check_ret = iavf_rx_vec_dev_check(dev);
2925         if (check_ret >= 0 &&
2926             rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
2927                 if ((rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
2928                      rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) &&
2929                     rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256)
2930                         use_avx2 = true;
2931
2932 #ifdef CC_AVX512_SUPPORT
2933                 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 &&
2934                     rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1 &&
2935                     rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512)
2936                         use_avx512 = true;
2937 #endif
2938
2939                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2940                         rxq = dev->data->rx_queues[i];
2941                         (void)iavf_rxq_vec_setup(rxq);
2942                 }
2943
2944                 if (dev->data->scattered_rx) {
2945                         if (!use_avx512) {
2946                                 PMD_DRV_LOG(DEBUG,
2947                                             "Using %sVector Scattered Rx (port %d).",
2948                                             use_avx2 ? "avx2 " : "",
2949                                             dev->data->port_id);
2950                         } else {
2951                                 if (check_ret == IAVF_VECTOR_PATH)
2952                                         PMD_DRV_LOG(DEBUG,
2953                                                     "Using AVX512 Vector Scattered Rx (port %d).",
2954                                                     dev->data->port_id);
2955                                 else
2956                                         PMD_DRV_LOG(DEBUG,
2957                                                     "Using AVX512 OFFLOAD Vector Scattered Rx (port %d).",
2958                                                     dev->data->port_id);
2959                         }
2960                         if (use_flex) {
2961                                 dev->rx_pkt_burst = use_avx2 ?
2962                                         iavf_recv_scattered_pkts_vec_avx2_flex_rxd :
2963                                         iavf_recv_scattered_pkts_vec_flex_rxd;
2964 #ifdef CC_AVX512_SUPPORT
2965                                 if (use_avx512) {
2966                                         if (check_ret == IAVF_VECTOR_PATH)
2967                                                 dev->rx_pkt_burst =
2968                                                         iavf_recv_scattered_pkts_vec_avx512_flex_rxd;
2969                                         else
2970                                                 dev->rx_pkt_burst =
2971                                                         iavf_recv_scattered_pkts_vec_avx512_flex_rxd_offload;
2972                                 }
2973 #endif
2974                         } else {
2975                                 dev->rx_pkt_burst = use_avx2 ?
2976                                         iavf_recv_scattered_pkts_vec_avx2 :
2977                                         iavf_recv_scattered_pkts_vec;
2978 #ifdef CC_AVX512_SUPPORT
2979                                 if (use_avx512) {
2980                                         if (check_ret == IAVF_VECTOR_PATH)
2981                                                 dev->rx_pkt_burst =
2982                                                         iavf_recv_scattered_pkts_vec_avx512;
2983                                         else
2984                                                 dev->rx_pkt_burst =
2985                                                         iavf_recv_scattered_pkts_vec_avx512_offload;
2986                                 }
2987 #endif
2988                         }
2989                 } else {
2990                         if (!use_avx512) {
2991                                 PMD_DRV_LOG(DEBUG, "Using %sVector Rx (port %d).",
2992                                             use_avx2 ? "avx2 " : "",
2993                                             dev->data->port_id);
2994                         } else {
2995                                 if (check_ret == IAVF_VECTOR_PATH)
2996                                         PMD_DRV_LOG(DEBUG,
2997                                                     "Using AVX512 Vector Rx (port %d).",
2998                                                     dev->data->port_id);
2999                                 else
3000                                         PMD_DRV_LOG(DEBUG,
3001                                                     "Using AVX512 OFFLOAD Vector Rx (port %d).",
3002                                                     dev->data->port_id);
3003                         }
3004                         if (use_flex) {
3005                                 dev->rx_pkt_burst = use_avx2 ?
3006                                         iavf_recv_pkts_vec_avx2_flex_rxd :
3007                                         iavf_recv_pkts_vec_flex_rxd;
3008 #ifdef CC_AVX512_SUPPORT
3009                                 if (use_avx512) {
3010                                         if (check_ret == IAVF_VECTOR_PATH)
3011                                                 dev->rx_pkt_burst =
3012                                                         iavf_recv_pkts_vec_avx512_flex_rxd;
3013                                         else
3014                                                 dev->rx_pkt_burst =
3015                                                         iavf_recv_pkts_vec_avx512_flex_rxd_offload;
3016                                 }
3017 #endif
3018                         } else {
3019                                 dev->rx_pkt_burst = use_avx2 ?
3020                                         iavf_recv_pkts_vec_avx2 :
3021                                         iavf_recv_pkts_vec;
3022 #ifdef CC_AVX512_SUPPORT
3023                                 if (use_avx512) {
3024                                         if (check_ret == IAVF_VECTOR_PATH)
3025                                                 dev->rx_pkt_burst =
3026                                                         iavf_recv_pkts_vec_avx512;
3027                                         else
3028                                                 dev->rx_pkt_burst =
3029                                                         iavf_recv_pkts_vec_avx512_offload;
3030                                 }
3031 #endif
3032                         }
3033                 }
3034
3035                 return;
3036         }
3037
3038 #endif
3039         if (dev->data->scattered_rx) {
3040                 PMD_DRV_LOG(DEBUG, "Using a Scattered Rx callback (port=%d).",
3041                             dev->data->port_id);
3042                 if (use_flex)
3043                         dev->rx_pkt_burst = iavf_recv_scattered_pkts_flex_rxd;
3044                 else
3045                         dev->rx_pkt_burst = iavf_recv_scattered_pkts;
3046         } else if (adapter->rx_bulk_alloc_allowed) {
3047                 PMD_DRV_LOG(DEBUG, "Using bulk Rx callback (port=%d).",
3048                             dev->data->port_id);
3049                 dev->rx_pkt_burst = iavf_recv_pkts_bulk_alloc;
3050         } else {
3051                 PMD_DRV_LOG(DEBUG, "Using Basic Rx callback (port=%d).",
3052                             dev->data->port_id);
3053                 if (use_flex)
3054                         dev->rx_pkt_burst = iavf_recv_pkts_flex_rxd;
3055                 else
3056                         dev->rx_pkt_burst = iavf_recv_pkts;
3057         }
3058 }
3059
3060 /* choose tx function*/
3061 void
3062 iavf_set_tx_function(struct rte_eth_dev *dev)
3063 {
3064 #ifdef RTE_ARCH_X86
3065         struct iavf_tx_queue *txq;
3066         int i;
3067         int check_ret;
3068         bool use_sse = false;
3069         bool use_avx2 = false;
3070         bool use_avx512 = false;
3071
3072         check_ret = iavf_tx_vec_dev_check(dev);
3073
3074         if (check_ret >= 0 &&
3075             rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
3076                 /* SSE and AVX2 not support offload path yet. */
3077                 if (check_ret == IAVF_VECTOR_PATH) {
3078                         use_sse = true;
3079                         if ((rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
3080                              rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) &&
3081                             rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256)
3082                                 use_avx2 = true;
3083                 }
3084 #ifdef CC_AVX512_SUPPORT
3085                 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 &&
3086                     rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1 &&
3087                     rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512)
3088                         use_avx512 = true;
3089 #endif
3090
3091                 if (!use_sse && !use_avx2 && !use_avx512)
3092                         goto normal;
3093
3094                 if (!use_avx512) {
3095                         PMD_DRV_LOG(DEBUG, "Using %sVector Tx (port %d).",
3096                                     use_avx2 ? "avx2 " : "",
3097                                     dev->data->port_id);
3098                         dev->tx_pkt_burst = use_avx2 ?
3099                                             iavf_xmit_pkts_vec_avx2 :
3100                                             iavf_xmit_pkts_vec;
3101                 }
3102                 dev->tx_pkt_prepare = NULL;
3103 #ifdef CC_AVX512_SUPPORT
3104                 if (use_avx512) {
3105                         if (check_ret == IAVF_VECTOR_PATH) {
3106                                 dev->tx_pkt_burst = iavf_xmit_pkts_vec_avx512;
3107                                 PMD_DRV_LOG(DEBUG, "Using AVX512 Vector Tx (port %d).",
3108                                             dev->data->port_id);
3109                         } else {
3110                                 dev->tx_pkt_burst = iavf_xmit_pkts_vec_avx512_offload;
3111                                 dev->tx_pkt_prepare = iavf_prep_pkts;
3112                                 PMD_DRV_LOG(DEBUG, "Using AVX512 OFFLOAD Vector Tx (port %d).",
3113                                             dev->data->port_id);
3114                         }
3115                 }
3116 #endif
3117
3118                 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3119                         txq = dev->data->tx_queues[i];
3120                         if (!txq)
3121                                 continue;
3122 #ifdef CC_AVX512_SUPPORT
3123                         if (use_avx512)
3124                                 iavf_txq_vec_setup_avx512(txq);
3125                         else
3126                                 iavf_txq_vec_setup(txq);
3127 #else
3128                         iavf_txq_vec_setup(txq);
3129 #endif
3130                 }
3131
3132                 return;
3133         }
3134
3135 normal:
3136 #endif
3137         PMD_DRV_LOG(DEBUG, "Using Basic Tx callback (port=%d).",
3138                     dev->data->port_id);
3139         dev->tx_pkt_burst = iavf_xmit_pkts;
3140         dev->tx_pkt_prepare = iavf_prep_pkts;
3141 }
3142
3143 static int
3144 iavf_tx_done_cleanup_full(struct iavf_tx_queue *txq,
3145                         uint32_t free_cnt)
3146 {
3147         struct iavf_tx_entry *swr_ring = txq->sw_ring;
3148         uint16_t i, tx_last, tx_id;
3149         uint16_t nb_tx_free_last;
3150         uint16_t nb_tx_to_clean;
3151         uint32_t pkt_cnt;
3152
3153         /* Start free mbuf from the next of tx_tail */
3154         tx_last = txq->tx_tail;
3155         tx_id  = swr_ring[tx_last].next_id;
3156
3157         if (txq->nb_free == 0 && iavf_xmit_cleanup(txq))
3158                 return 0;
3159
3160         nb_tx_to_clean = txq->nb_free;
3161         nb_tx_free_last = txq->nb_free;
3162         if (!free_cnt)
3163                 free_cnt = txq->nb_tx_desc;
3164
3165         /* Loop through swr_ring to count the amount of
3166          * freeable mubfs and packets.
3167          */
3168         for (pkt_cnt = 0; pkt_cnt < free_cnt; ) {
3169                 for (i = 0; i < nb_tx_to_clean &&
3170                         pkt_cnt < free_cnt &&
3171                         tx_id != tx_last; i++) {
3172                         if (swr_ring[tx_id].mbuf != NULL) {
3173                                 rte_pktmbuf_free_seg(swr_ring[tx_id].mbuf);
3174                                 swr_ring[tx_id].mbuf = NULL;
3175
3176                                 /*
3177                                  * last segment in the packet,
3178                                  * increment packet count
3179                                  */
3180                                 pkt_cnt += (swr_ring[tx_id].last_id == tx_id);
3181                         }
3182
3183                         tx_id = swr_ring[tx_id].next_id;
3184                 }
3185
3186                 if (txq->rs_thresh > txq->nb_tx_desc -
3187                         txq->nb_free || tx_id == tx_last)
3188                         break;
3189
3190                 if (pkt_cnt < free_cnt) {
3191                         if (iavf_xmit_cleanup(txq))
3192                                 break;
3193
3194                         nb_tx_to_clean = txq->nb_free - nb_tx_free_last;
3195                         nb_tx_free_last = txq->nb_free;
3196                 }
3197         }
3198
3199         return (int)pkt_cnt;
3200 }
3201
3202 int
3203 iavf_dev_tx_done_cleanup(void *txq, uint32_t free_cnt)
3204 {
3205         struct iavf_tx_queue *q = (struct iavf_tx_queue *)txq;
3206
3207         return iavf_tx_done_cleanup_full(q, free_cnt);
3208 }
3209
3210 void
3211 iavf_dev_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
3212                      struct rte_eth_rxq_info *qinfo)
3213 {
3214         struct iavf_rx_queue *rxq;
3215
3216         rxq = dev->data->rx_queues[queue_id];
3217
3218         qinfo->mp = rxq->mp;
3219         qinfo->scattered_rx = dev->data->scattered_rx;
3220         qinfo->nb_desc = rxq->nb_rx_desc;
3221
3222         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
3223         qinfo->conf.rx_drop_en = true;
3224         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
3225 }
3226
3227 void
3228 iavf_dev_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
3229                      struct rte_eth_txq_info *qinfo)
3230 {
3231         struct iavf_tx_queue *txq;
3232
3233         txq = dev->data->tx_queues[queue_id];
3234
3235         qinfo->nb_desc = txq->nb_tx_desc;
3236
3237         qinfo->conf.tx_free_thresh = txq->free_thresh;
3238         qinfo->conf.tx_rs_thresh = txq->rs_thresh;
3239         qinfo->conf.offloads = txq->offloads;
3240         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
3241 }
3242
3243 /* Get the number of used descriptors of a rx queue */
3244 uint32_t
3245 iavf_dev_rxq_count(void *rx_queue)
3246 {
3247 #define IAVF_RXQ_SCAN_INTERVAL 4
3248         volatile union iavf_rx_desc *rxdp;
3249         struct iavf_rx_queue *rxq;
3250         uint16_t desc = 0;
3251
3252         rxq = rx_queue;
3253         rxdp = &rxq->rx_ring[rxq->rx_tail];
3254
3255         while ((desc < rxq->nb_rx_desc) &&
3256                ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
3257                  IAVF_RXD_QW1_STATUS_MASK) >> IAVF_RXD_QW1_STATUS_SHIFT) &
3258                (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)) {
3259                 /* Check the DD bit of a rx descriptor of each 4 in a group,
3260                  * to avoid checking too frequently and downgrading performance
3261                  * too much.
3262                  */
3263                 desc += IAVF_RXQ_SCAN_INTERVAL;
3264                 rxdp += IAVF_RXQ_SCAN_INTERVAL;
3265                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
3266                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
3267                                         desc - rxq->nb_rx_desc]);
3268         }
3269
3270         return desc;
3271 }
3272
3273 int
3274 iavf_dev_rx_desc_status(void *rx_queue, uint16_t offset)
3275 {
3276         struct iavf_rx_queue *rxq = rx_queue;
3277         volatile uint64_t *status;
3278         uint64_t mask;
3279         uint32_t desc;
3280
3281         if (unlikely(offset >= rxq->nb_rx_desc))
3282                 return -EINVAL;
3283
3284         if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
3285                 return RTE_ETH_RX_DESC_UNAVAIL;
3286
3287         desc = rxq->rx_tail + offset;
3288         if (desc >= rxq->nb_rx_desc)
3289                 desc -= rxq->nb_rx_desc;
3290
3291         status = &rxq->rx_ring[desc].wb.qword1.status_error_len;
3292         mask = rte_le_to_cpu_64((1ULL << IAVF_RX_DESC_STATUS_DD_SHIFT)
3293                 << IAVF_RXD_QW1_STATUS_SHIFT);
3294         if (*status & mask)
3295                 return RTE_ETH_RX_DESC_DONE;
3296
3297         return RTE_ETH_RX_DESC_AVAIL;
3298 }
3299
3300 int
3301 iavf_dev_tx_desc_status(void *tx_queue, uint16_t offset)
3302 {
3303         struct iavf_tx_queue *txq = tx_queue;
3304         volatile uint64_t *status;
3305         uint64_t mask, expect;
3306         uint32_t desc;
3307
3308         if (unlikely(offset >= txq->nb_tx_desc))
3309                 return -EINVAL;
3310
3311         desc = txq->tx_tail + offset;
3312         /* go to next desc that has the RS bit */
3313         desc = ((desc + txq->rs_thresh - 1) / txq->rs_thresh) *
3314                 txq->rs_thresh;
3315         if (desc >= txq->nb_tx_desc) {
3316                 desc -= txq->nb_tx_desc;
3317                 if (desc >= txq->nb_tx_desc)
3318                         desc -= txq->nb_tx_desc;
3319         }
3320
3321         status = &txq->tx_ring[desc].cmd_type_offset_bsz;
3322         mask = rte_le_to_cpu_64(IAVF_TXD_QW1_DTYPE_MASK);
3323         expect = rte_cpu_to_le_64(
3324                  IAVF_TX_DESC_DTYPE_DESC_DONE << IAVF_TXD_QW1_DTYPE_SHIFT);
3325         if ((*status & mask) == expect)
3326                 return RTE_ETH_TX_DESC_DONE;
3327
3328         return RTE_ETH_TX_DESC_FULL;
3329 }
3330
3331 static inline uint32_t
3332 iavf_get_default_ptype(uint16_t ptype)
3333 {
3334         static const uint32_t ptype_tbl[IAVF_MAX_PKT_TYPE]
3335                 __rte_cache_aligned = {
3336                 /* L2 types */
3337                 /* [0] reserved */
3338                 [1] = RTE_PTYPE_L2_ETHER,
3339                 [2] = RTE_PTYPE_L2_ETHER_TIMESYNC,
3340                 /* [3] - [5] reserved */
3341                 [6] = RTE_PTYPE_L2_ETHER_LLDP,
3342                 /* [7] - [10] reserved */
3343                 [11] = RTE_PTYPE_L2_ETHER_ARP,
3344                 /* [12] - [21] reserved */
3345
3346                 /* Non tunneled IPv4 */
3347                 [22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3348                        RTE_PTYPE_L4_FRAG,
3349                 [23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3350                        RTE_PTYPE_L4_NONFRAG,
3351                 [24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3352                        RTE_PTYPE_L4_UDP,
3353                 /* [25] reserved */
3354                 [26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3355                        RTE_PTYPE_L4_TCP,
3356                 [27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3357                        RTE_PTYPE_L4_SCTP,
3358                 [28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3359                        RTE_PTYPE_L4_ICMP,
3360
3361                 /* IPv4 --> IPv4 */
3362                 [29] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3363                        RTE_PTYPE_TUNNEL_IP |
3364                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3365                        RTE_PTYPE_INNER_L4_FRAG,
3366                 [30] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3367                        RTE_PTYPE_TUNNEL_IP |
3368                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3369                        RTE_PTYPE_INNER_L4_NONFRAG,
3370                 [31] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3371                        RTE_PTYPE_TUNNEL_IP |
3372                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3373                        RTE_PTYPE_INNER_L4_UDP,
3374                 /* [32] reserved */
3375                 [33] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3376                        RTE_PTYPE_TUNNEL_IP |
3377                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3378                        RTE_PTYPE_INNER_L4_TCP,
3379                 [34] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3380                        RTE_PTYPE_TUNNEL_IP |
3381                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3382                        RTE_PTYPE_INNER_L4_SCTP,
3383                 [35] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3384                        RTE_PTYPE_TUNNEL_IP |
3385                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3386                        RTE_PTYPE_INNER_L4_ICMP,
3387
3388                 /* IPv4 --> IPv6 */
3389                 [36] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3390                        RTE_PTYPE_TUNNEL_IP |
3391                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3392                        RTE_PTYPE_INNER_L4_FRAG,
3393                 [37] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3394                        RTE_PTYPE_TUNNEL_IP |
3395                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3396                        RTE_PTYPE_INNER_L4_NONFRAG,
3397                 [38] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3398                        RTE_PTYPE_TUNNEL_IP |
3399                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3400                        RTE_PTYPE_INNER_L4_UDP,
3401                 /* [39] reserved */
3402                 [40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3403                        RTE_PTYPE_TUNNEL_IP |
3404                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3405                        RTE_PTYPE_INNER_L4_TCP,
3406                 [41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3407                        RTE_PTYPE_TUNNEL_IP |
3408                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3409                        RTE_PTYPE_INNER_L4_SCTP,
3410                 [42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3411                        RTE_PTYPE_TUNNEL_IP |
3412                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3413                        RTE_PTYPE_INNER_L4_ICMP,
3414
3415                 /* IPv4 --> GRE/Teredo/VXLAN */
3416                 [43] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3417                        RTE_PTYPE_TUNNEL_GRENAT,
3418
3419                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv4 */
3420                 [44] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3421                        RTE_PTYPE_TUNNEL_GRENAT |
3422                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3423                        RTE_PTYPE_INNER_L4_FRAG,
3424                 [45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3425                        RTE_PTYPE_TUNNEL_GRENAT |
3426                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3427                        RTE_PTYPE_INNER_L4_NONFRAG,
3428                 [46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3429                        RTE_PTYPE_TUNNEL_GRENAT |
3430                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3431                        RTE_PTYPE_INNER_L4_UDP,
3432                 /* [47] reserved */
3433                 [48] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3434                        RTE_PTYPE_TUNNEL_GRENAT |
3435                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3436                        RTE_PTYPE_INNER_L4_TCP,
3437                 [49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3438                        RTE_PTYPE_TUNNEL_GRENAT |
3439                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3440                        RTE_PTYPE_INNER_L4_SCTP,
3441                 [50] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3442                        RTE_PTYPE_TUNNEL_GRENAT |
3443                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3444                        RTE_PTYPE_INNER_L4_ICMP,
3445
3446                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv6 */
3447                 [51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3448                        RTE_PTYPE_TUNNEL_GRENAT |
3449                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3450                        RTE_PTYPE_INNER_L4_FRAG,
3451                 [52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3452                        RTE_PTYPE_TUNNEL_GRENAT |
3453                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3454                        RTE_PTYPE_INNER_L4_NONFRAG,
3455                 [53] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3456                        RTE_PTYPE_TUNNEL_GRENAT |
3457                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3458                        RTE_PTYPE_INNER_L4_UDP,
3459                 /* [54] reserved */
3460                 [55] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3461                        RTE_PTYPE_TUNNEL_GRENAT |
3462                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3463                        RTE_PTYPE_INNER_L4_TCP,
3464                 [56] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3465                        RTE_PTYPE_TUNNEL_GRENAT |
3466                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3467                        RTE_PTYPE_INNER_L4_SCTP,
3468                 [57] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3469                        RTE_PTYPE_TUNNEL_GRENAT |
3470                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3471                        RTE_PTYPE_INNER_L4_ICMP,
3472
3473                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC */
3474                 [58] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3475                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
3476
3477                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
3478                 [59] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3479                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3480                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3481                        RTE_PTYPE_INNER_L4_FRAG,
3482                 [60] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3483                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3484                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3485                        RTE_PTYPE_INNER_L4_NONFRAG,
3486                 [61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3487                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3488                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3489                        RTE_PTYPE_INNER_L4_UDP,
3490                 /* [62] reserved */
3491                 [63] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3492                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3493                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3494                        RTE_PTYPE_INNER_L4_TCP,
3495                 [64] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3496                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3497                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3498                        RTE_PTYPE_INNER_L4_SCTP,
3499                 [65] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3500                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3501                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3502                        RTE_PTYPE_INNER_L4_ICMP,
3503
3504                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
3505                 [66] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3506                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3507                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3508                        RTE_PTYPE_INNER_L4_FRAG,
3509                 [67] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3510                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3511                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3512                        RTE_PTYPE_INNER_L4_NONFRAG,
3513                 [68] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3514                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3515                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3516                        RTE_PTYPE_INNER_L4_UDP,
3517                 /* [69] reserved */
3518                 [70] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3519                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3520                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3521                        RTE_PTYPE_INNER_L4_TCP,
3522                 [71] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3523                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3524                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3525                        RTE_PTYPE_INNER_L4_SCTP,
3526                 [72] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3527                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3528                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3529                        RTE_PTYPE_INNER_L4_ICMP,
3530                 /* [73] - [87] reserved */
3531
3532                 /* Non tunneled IPv6 */
3533                 [88] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3534                        RTE_PTYPE_L4_FRAG,
3535                 [89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3536                        RTE_PTYPE_L4_NONFRAG,
3537                 [90] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3538                        RTE_PTYPE_L4_UDP,
3539                 /* [91] reserved */
3540                 [92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3541                        RTE_PTYPE_L4_TCP,
3542                 [93] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3543                        RTE_PTYPE_L4_SCTP,
3544                 [94] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3545                        RTE_PTYPE_L4_ICMP,
3546
3547                 /* IPv6 --> IPv4 */
3548                 [95] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3549                        RTE_PTYPE_TUNNEL_IP |
3550                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3551                        RTE_PTYPE_INNER_L4_FRAG,
3552                 [96] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3553                        RTE_PTYPE_TUNNEL_IP |
3554                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3555                        RTE_PTYPE_INNER_L4_NONFRAG,
3556                 [97] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3557                        RTE_PTYPE_TUNNEL_IP |
3558                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3559                        RTE_PTYPE_INNER_L4_UDP,
3560                 /* [98] reserved */
3561                 [99] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3562                        RTE_PTYPE_TUNNEL_IP |
3563                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3564                        RTE_PTYPE_INNER_L4_TCP,
3565                 [100] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3566                         RTE_PTYPE_TUNNEL_IP |
3567                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3568                         RTE_PTYPE_INNER_L4_SCTP,
3569                 [101] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3570                         RTE_PTYPE_TUNNEL_IP |
3571                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3572                         RTE_PTYPE_INNER_L4_ICMP,
3573
3574                 /* IPv6 --> IPv6 */
3575                 [102] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3576                         RTE_PTYPE_TUNNEL_IP |
3577                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3578                         RTE_PTYPE_INNER_L4_FRAG,
3579                 [103] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3580                         RTE_PTYPE_TUNNEL_IP |
3581                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3582                         RTE_PTYPE_INNER_L4_NONFRAG,
3583                 [104] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3584                         RTE_PTYPE_TUNNEL_IP |
3585                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3586                         RTE_PTYPE_INNER_L4_UDP,
3587                 /* [105] reserved */
3588                 [106] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3589                         RTE_PTYPE_TUNNEL_IP |
3590                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3591                         RTE_PTYPE_INNER_L4_TCP,
3592                 [107] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3593                         RTE_PTYPE_TUNNEL_IP |
3594                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3595                         RTE_PTYPE_INNER_L4_SCTP,
3596                 [108] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3597                         RTE_PTYPE_TUNNEL_IP |
3598                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3599                         RTE_PTYPE_INNER_L4_ICMP,
3600
3601                 /* IPv6 --> GRE/Teredo/VXLAN */
3602                 [109] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3603                         RTE_PTYPE_TUNNEL_GRENAT,
3604
3605                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv4 */
3606                 [110] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3607                         RTE_PTYPE_TUNNEL_GRENAT |
3608                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3609                         RTE_PTYPE_INNER_L4_FRAG,
3610                 [111] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3611                         RTE_PTYPE_TUNNEL_GRENAT |
3612                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3613                         RTE_PTYPE_INNER_L4_NONFRAG,
3614                 [112] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3615                         RTE_PTYPE_TUNNEL_GRENAT |
3616                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3617                         RTE_PTYPE_INNER_L4_UDP,
3618                 /* [113] reserved */
3619                 [114] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3620                         RTE_PTYPE_TUNNEL_GRENAT |
3621                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3622                         RTE_PTYPE_INNER_L4_TCP,
3623                 [115] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3624                         RTE_PTYPE_TUNNEL_GRENAT |
3625                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3626                         RTE_PTYPE_INNER_L4_SCTP,
3627                 [116] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3628                         RTE_PTYPE_TUNNEL_GRENAT |
3629                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3630                         RTE_PTYPE_INNER_L4_ICMP,
3631
3632                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv6 */
3633                 [117] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3634                         RTE_PTYPE_TUNNEL_GRENAT |
3635                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3636                         RTE_PTYPE_INNER_L4_FRAG,
3637                 [118] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3638                         RTE_PTYPE_TUNNEL_GRENAT |
3639                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3640                         RTE_PTYPE_INNER_L4_NONFRAG,
3641                 [119] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3642                         RTE_PTYPE_TUNNEL_GRENAT |
3643                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3644                         RTE_PTYPE_INNER_L4_UDP,
3645                 /* [120] reserved */
3646                 [121] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3647                         RTE_PTYPE_TUNNEL_GRENAT |
3648                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3649                         RTE_PTYPE_INNER_L4_TCP,
3650                 [122] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3651                         RTE_PTYPE_TUNNEL_GRENAT |
3652                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3653                         RTE_PTYPE_INNER_L4_SCTP,
3654                 [123] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3655                         RTE_PTYPE_TUNNEL_GRENAT |
3656                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3657                         RTE_PTYPE_INNER_L4_ICMP,
3658
3659                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC */
3660                 [124] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3661                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
3662
3663                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
3664                 [125] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3665                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3666                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3667                         RTE_PTYPE_INNER_L4_FRAG,
3668                 [126] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3669                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3670                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3671                         RTE_PTYPE_INNER_L4_NONFRAG,
3672                 [127] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3673                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3674                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3675                         RTE_PTYPE_INNER_L4_UDP,
3676                 /* [128] reserved */
3677                 [129] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3678                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3679                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3680                         RTE_PTYPE_INNER_L4_TCP,
3681                 [130] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3682                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3683                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3684                         RTE_PTYPE_INNER_L4_SCTP,
3685                 [131] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3686                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3687                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3688                         RTE_PTYPE_INNER_L4_ICMP,
3689
3690                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
3691                 [132] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3692                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3693                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3694                         RTE_PTYPE_INNER_L4_FRAG,
3695                 [133] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3696                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3697                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3698                         RTE_PTYPE_INNER_L4_NONFRAG,
3699                 [134] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3700                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3701                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3702                         RTE_PTYPE_INNER_L4_UDP,
3703                 /* [135] reserved */
3704                 [136] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3705                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3706                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3707                         RTE_PTYPE_INNER_L4_TCP,
3708                 [137] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3709                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3710                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3711                         RTE_PTYPE_INNER_L4_SCTP,
3712                 [138] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3713                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3714                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3715                         RTE_PTYPE_INNER_L4_ICMP,
3716                 /* [139] - [299] reserved */
3717
3718                 /* PPPoE */
3719                 [300] = RTE_PTYPE_L2_ETHER_PPPOE,
3720                 [301] = RTE_PTYPE_L2_ETHER_PPPOE,
3721
3722                 /* PPPoE --> IPv4 */
3723                 [302] = RTE_PTYPE_L2_ETHER_PPPOE |
3724                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3725                         RTE_PTYPE_L4_FRAG,
3726                 [303] = RTE_PTYPE_L2_ETHER_PPPOE |
3727                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3728                         RTE_PTYPE_L4_NONFRAG,
3729                 [304] = RTE_PTYPE_L2_ETHER_PPPOE |
3730                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3731                         RTE_PTYPE_L4_UDP,
3732                 [305] = RTE_PTYPE_L2_ETHER_PPPOE |
3733                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3734                         RTE_PTYPE_L4_TCP,
3735                 [306] = RTE_PTYPE_L2_ETHER_PPPOE |
3736                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3737                         RTE_PTYPE_L4_SCTP,
3738                 [307] = RTE_PTYPE_L2_ETHER_PPPOE |
3739                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3740                         RTE_PTYPE_L4_ICMP,
3741
3742                 /* PPPoE --> IPv6 */
3743                 [308] = RTE_PTYPE_L2_ETHER_PPPOE |
3744                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3745                         RTE_PTYPE_L4_FRAG,
3746                 [309] = RTE_PTYPE_L2_ETHER_PPPOE |
3747                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3748                         RTE_PTYPE_L4_NONFRAG,
3749                 [310] = RTE_PTYPE_L2_ETHER_PPPOE |
3750                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3751                         RTE_PTYPE_L4_UDP,
3752                 [311] = RTE_PTYPE_L2_ETHER_PPPOE |
3753                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3754                         RTE_PTYPE_L4_TCP,
3755                 [312] = RTE_PTYPE_L2_ETHER_PPPOE |
3756                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3757                         RTE_PTYPE_L4_SCTP,
3758                 [313] = RTE_PTYPE_L2_ETHER_PPPOE |
3759                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3760                         RTE_PTYPE_L4_ICMP,
3761                 /* [314] - [324] reserved */
3762
3763                 /* IPv4/IPv6 --> GTPC/GTPU */
3764                 [325] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3765                         RTE_PTYPE_TUNNEL_GTPC,
3766                 [326] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3767                         RTE_PTYPE_TUNNEL_GTPC,
3768                 [327] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3769                         RTE_PTYPE_TUNNEL_GTPC,
3770                 [328] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3771                         RTE_PTYPE_TUNNEL_GTPC,
3772                 [329] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3773                         RTE_PTYPE_TUNNEL_GTPU,
3774                 [330] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3775                         RTE_PTYPE_TUNNEL_GTPU,
3776
3777                 /* IPv4 --> GTPU --> IPv4 */
3778                 [331] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3779                         RTE_PTYPE_TUNNEL_GTPU |
3780                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3781                         RTE_PTYPE_INNER_L4_FRAG,
3782                 [332] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3783                         RTE_PTYPE_TUNNEL_GTPU |
3784                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3785                         RTE_PTYPE_INNER_L4_NONFRAG,
3786                 [333] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3787                         RTE_PTYPE_TUNNEL_GTPU |
3788                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3789                         RTE_PTYPE_INNER_L4_UDP,
3790                 [334] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3791                         RTE_PTYPE_TUNNEL_GTPU |
3792                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3793                         RTE_PTYPE_INNER_L4_TCP,
3794                 [335] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3795                         RTE_PTYPE_TUNNEL_GTPU |
3796                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3797                         RTE_PTYPE_INNER_L4_ICMP,
3798
3799                 /* IPv6 --> GTPU --> IPv4 */
3800                 [336] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3801                         RTE_PTYPE_TUNNEL_GTPU |
3802                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3803                         RTE_PTYPE_INNER_L4_FRAG,
3804                 [337] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3805                         RTE_PTYPE_TUNNEL_GTPU |
3806                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3807                         RTE_PTYPE_INNER_L4_NONFRAG,
3808                 [338] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3809                         RTE_PTYPE_TUNNEL_GTPU |
3810                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3811                         RTE_PTYPE_INNER_L4_UDP,
3812                 [339] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3813                         RTE_PTYPE_TUNNEL_GTPU |
3814                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3815                         RTE_PTYPE_INNER_L4_TCP,
3816                 [340] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3817                         RTE_PTYPE_TUNNEL_GTPU |
3818                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3819                         RTE_PTYPE_INNER_L4_ICMP,
3820
3821                 /* IPv4 --> GTPU --> IPv6 */
3822                 [341] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3823                         RTE_PTYPE_TUNNEL_GTPU |
3824                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3825                         RTE_PTYPE_INNER_L4_FRAG,
3826                 [342] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3827                         RTE_PTYPE_TUNNEL_GTPU |
3828                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3829                         RTE_PTYPE_INNER_L4_NONFRAG,
3830                 [343] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3831                         RTE_PTYPE_TUNNEL_GTPU |
3832                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3833                         RTE_PTYPE_INNER_L4_UDP,
3834                 [344] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3835                         RTE_PTYPE_TUNNEL_GTPU |
3836                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3837                         RTE_PTYPE_INNER_L4_TCP,
3838                 [345] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3839                         RTE_PTYPE_TUNNEL_GTPU |
3840                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3841                         RTE_PTYPE_INNER_L4_ICMP,
3842
3843                 /* IPv6 --> GTPU --> IPv6 */
3844                 [346] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3845                         RTE_PTYPE_TUNNEL_GTPU |
3846                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3847                         RTE_PTYPE_INNER_L4_FRAG,
3848                 [347] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3849                         RTE_PTYPE_TUNNEL_GTPU |
3850                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3851                         RTE_PTYPE_INNER_L4_NONFRAG,
3852                 [348] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3853                         RTE_PTYPE_TUNNEL_GTPU |
3854                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3855                         RTE_PTYPE_INNER_L4_UDP,
3856                 [349] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3857                         RTE_PTYPE_TUNNEL_GTPU |
3858                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3859                         RTE_PTYPE_INNER_L4_TCP,
3860                 [350] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3861                         RTE_PTYPE_TUNNEL_GTPU |
3862                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3863                         RTE_PTYPE_INNER_L4_ICMP,
3864
3865                 /* IPv4 --> UDP ECPRI */
3866                 [372] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3867                         RTE_PTYPE_L4_UDP,
3868                 [373] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3869                         RTE_PTYPE_L4_UDP,
3870                 [374] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3871                         RTE_PTYPE_L4_UDP,
3872                 [375] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3873                         RTE_PTYPE_L4_UDP,
3874                 [376] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3875                         RTE_PTYPE_L4_UDP,
3876                 [377] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3877                         RTE_PTYPE_L4_UDP,
3878                 [378] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3879                         RTE_PTYPE_L4_UDP,
3880                 [379] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3881                         RTE_PTYPE_L4_UDP,
3882                 [380] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3883                         RTE_PTYPE_L4_UDP,
3884                 [381] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3885                         RTE_PTYPE_L4_UDP,
3886
3887                 /* IPV6 --> UDP ECPRI */
3888                 [382] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3889                         RTE_PTYPE_L4_UDP,
3890                 [383] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3891                         RTE_PTYPE_L4_UDP,
3892                 [384] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3893                         RTE_PTYPE_L4_UDP,
3894                 [385] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3895                         RTE_PTYPE_L4_UDP,
3896                 [386] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3897                         RTE_PTYPE_L4_UDP,
3898                 [387] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3899                         RTE_PTYPE_L4_UDP,
3900                 [388] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3901                         RTE_PTYPE_L4_UDP,
3902                 [389] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3903                         RTE_PTYPE_L4_UDP,
3904                 [390] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3905                         RTE_PTYPE_L4_UDP,
3906                 [391] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3907                         RTE_PTYPE_L4_UDP,
3908                 /* All others reserved */
3909         };
3910
3911         return ptype_tbl[ptype];
3912 }
3913
3914 void __rte_cold
3915 iavf_set_default_ptype_table(struct rte_eth_dev *dev)
3916 {
3917         struct iavf_adapter *ad =
3918                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3919         int i;
3920
3921         for (i = 0; i < IAVF_MAX_PKT_TYPE; i++)
3922                 ad->ptype_tbl[i] = iavf_get_default_ptype(i);
3923 }