drivers/net/iavf/iavf_rxtx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2017 Intel Corporation
   3  */
   4
   5 #include <stdio.h>
   6 #include <stdlib.h>
   7 #include <string.h>
   8 #include <errno.h>
   9 #include <stdint.h>
  10 #include <stdarg.h>
  11 #include <unistd.h>
  12 #include <inttypes.h>
  13 #include <sys/queue.h>
  14
  15 #include <rte_string_fns.h>
  16 #include <rte_memzone.h>
  17 #include <rte_mbuf.h>
  18 #include <rte_malloc.h>
  19 #include <rte_ether.h>
  20 #include <ethdev_driver.h>
  21 #include <rte_tcp.h>
  22 #include <rte_sctp.h>
  23 #include <rte_udp.h>
  24 #include <rte_ip.h>
  25 #include <rte_net.h>
  26 #include <rte_vect.h>
  27
  28 #include "iavf.h"
  29 #include "iavf_rxtx.h"
  30 #include "rte_pmd_iavf.h"
  31
  32 /* Offset of mbuf dynamic field for protocol extraction's metadata */
  33 int rte_pmd_ifd_dynfield_proto_xtr_metadata_offs = -1;
  34
  35 /* Mask of mbuf dynamic flags for protocol extraction's type */
  36 uint64_t rte_pmd_ifd_dynflag_proto_xtr_vlan_mask;
  37 uint64_t rte_pmd_ifd_dynflag_proto_xtr_ipv4_mask;
  38 uint64_t rte_pmd_ifd_dynflag_proto_xtr_ipv6_mask;
  39 uint64_t rte_pmd_ifd_dynflag_proto_xtr_ipv6_flow_mask;
  40 uint64_t rte_pmd_ifd_dynflag_proto_xtr_tcp_mask;
  41 uint64_t rte_pmd_ifd_dynflag_proto_xtr_ip_offset_mask;
  42
  43 uint8_t
  44 iavf_proto_xtr_type_to_rxdid(uint8_t flex_type)
  45 {
  46         static uint8_t rxdid_map[] = {
  47                 [IAVF_PROTO_XTR_NONE]      = IAVF_RXDID_COMMS_OVS_1,
  48                 [IAVF_PROTO_XTR_VLAN]      = IAVF_RXDID_COMMS_AUX_VLAN,
  49                 [IAVF_PROTO_XTR_IPV4]      = IAVF_RXDID_COMMS_AUX_IPV4,
  50                 [IAVF_PROTO_XTR_IPV6]      = IAVF_RXDID_COMMS_AUX_IPV6,
  51                 [IAVF_PROTO_XTR_IPV6_FLOW] = IAVF_RXDID_COMMS_AUX_IPV6_FLOW,
  52                 [IAVF_PROTO_XTR_TCP]       = IAVF_RXDID_COMMS_AUX_TCP,
  53                 [IAVF_PROTO_XTR_IP_OFFSET] = IAVF_RXDID_COMMS_AUX_IP_OFFSET,
  54         };
  55
  56         return flex_type < RTE_DIM(rxdid_map) ?
  57                                 rxdid_map[flex_type] : IAVF_RXDID_COMMS_OVS_1;
  58 }
  59
  60 static int
  61 iavf_monitor_callback(const uint64_t value,
  62                 const uint64_t arg[RTE_POWER_MONITOR_OPAQUE_SZ] __rte_unused)
  63 {
  64         const uint64_t m = rte_cpu_to_le_64(1 << IAVF_RX_DESC_STATUS_DD_SHIFT);
  65         /*
  66          * we expect the DD bit to be set to 1 if this descriptor was already
  67          * written to.
  68          */
  69         return (value & m) == m ? -1 : 0;
  70 }
  71
  72 int
  73 iavf_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc)
  74 {
  75         struct iavf_rx_queue *rxq = rx_queue;
  76         volatile union iavf_rx_desc *rxdp;
  77         uint16_t desc;
  78
  79         desc = rxq->rx_tail;
  80         rxdp = &rxq->rx_ring[desc];
  81         /* watch for changes in status bit */
  82         pmc->addr = &rxdp->wb.qword1.status_error_len;
  83
  84         /* comparison callback */
  85         pmc->fn = iavf_monitor_callback;
  86
  87         /* registers are 64-bit */
  88         pmc->size = sizeof(uint64_t);
  89
  90         return 0;
  91 }
  92
  93 static inline int
  94 check_rx_thresh(uint16_t nb_desc, uint16_t thresh)
  95 {
  96         /* The following constraints must be satisfied:
  97          *   thresh < rxq->nb_rx_desc
  98          */
  99         if (thresh >= nb_desc) {
 100                 PMD_INIT_LOG(ERR, "rx_free_thresh (%u) must be less than %u",
 101                              thresh, nb_desc);
 102                 return -EINVAL;
 103         }
 104         return 0;
 105 }
 106
 107 static inline int
 108 check_tx_thresh(uint16_t nb_desc, uint16_t tx_rs_thresh,
 109                 uint16_t tx_free_thresh)
 110 {
 111         /* TX descriptors will have their RS bit set after tx_rs_thresh
 112          * descriptors have been used. The TX descriptor ring will be cleaned
 113          * after tx_free_thresh descriptors are used or if the number of
 114          * descriptors required to transmit a packet is greater than the
 115          * number of free TX descriptors.
 116          *
 117          * The following constraints must be satisfied:
 118          *  - tx_rs_thresh must be less than the size of the ring minus 2.
 119          *  - tx_free_thresh must be less than the size of the ring minus 3.
 120          *  - tx_rs_thresh must be less than or equal to tx_free_thresh.
 121          *  - tx_rs_thresh must be a divisor of the ring size.
 122          *
 123          * One descriptor in the TX ring is used as a sentinel to avoid a H/W
 124          * race condition, hence the maximum threshold constraints. When set
 125          * to zero use default values.
 126          */
 127         if (tx_rs_thresh >= (nb_desc - 2)) {
 128                 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be less than the "
 129                              "number of TX descriptors (%u) minus 2",
 130                              tx_rs_thresh, nb_desc);
 131                 return -EINVAL;
 132         }
 133         if (tx_free_thresh >= (nb_desc - 3)) {
 134                 PMD_INIT_LOG(ERR, "tx_free_thresh (%u) must be less than the "
 135                              "number of TX descriptors (%u) minus 3.",
 136                              tx_free_thresh, nb_desc);
 137                 return -EINVAL;
 138         }
 139         if (tx_rs_thresh > tx_free_thresh) {
 140                 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be less than or "
 141                              "equal to tx_free_thresh (%u).",
 142                              tx_rs_thresh, tx_free_thresh);
 143                 return -EINVAL;
 144         }
 145         if ((nb_desc % tx_rs_thresh) != 0) {
 146                 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be a divisor of the "
 147                              "number of TX descriptors (%u).",
 148                              tx_rs_thresh, nb_desc);
 149                 return -EINVAL;
 150         }
 151
 152         return 0;
 153 }
 154
 155 static inline bool
 156 check_rx_vec_allow(struct iavf_rx_queue *rxq)
 157 {
 158         if (rxq->rx_free_thresh >= IAVF_VPMD_RX_MAX_BURST &&
 159             rxq->nb_rx_desc % rxq->rx_free_thresh == 0) {
 160                 PMD_INIT_LOG(DEBUG, "Vector Rx can be enabled on this rxq.");
 161                 return true;
 162         }
 163
 164         PMD_INIT_LOG(DEBUG, "Vector Rx cannot be enabled on this rxq.");
 165         return false;
 166 }
 167
 168 static inline bool
 169 check_tx_vec_allow(struct iavf_tx_queue *txq)
 170 {
 171         if (!(txq->offloads & IAVF_TX_NO_VECTOR_FLAGS) &&
 172             txq->rs_thresh >= IAVF_VPMD_TX_MAX_BURST &&
 173             txq->rs_thresh <= IAVF_VPMD_TX_MAX_FREE_BUF) {
 174                 PMD_INIT_LOG(DEBUG, "Vector tx can be enabled on this txq.");
 175                 return true;
 176         }
 177         PMD_INIT_LOG(DEBUG, "Vector Tx cannot be enabled on this txq.");
 178         return false;
 179 }
 180
 181 static inline bool
 182 check_rx_bulk_allow(struct iavf_rx_queue *rxq)
 183 {
 184         int ret = true;
 185
 186         if (!(rxq->rx_free_thresh >= IAVF_RX_MAX_BURST)) {
 187                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 188                              "rxq->rx_free_thresh=%d, "
 189                              "IAVF_RX_MAX_BURST=%d",
 190                              rxq->rx_free_thresh, IAVF_RX_MAX_BURST);
 191                 ret = false;
 192         } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
 193                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 194                              "rxq->nb_rx_desc=%d, "
 195                              "rxq->rx_free_thresh=%d",
 196                              rxq->nb_rx_desc, rxq->rx_free_thresh);
 197                 ret = false;
 198         }
 199         return ret;
 200 }
 201
 202 static inline void
 203 reset_rx_queue(struct iavf_rx_queue *rxq)
 204 {
 205         uint16_t len;
 206         uint32_t i;
 207
 208         if (!rxq)
 209                 return;
 210
 211         len = rxq->nb_rx_desc + IAVF_RX_MAX_BURST;
 212
 213         for (i = 0; i < len * sizeof(union iavf_rx_desc); i++)
 214                 ((volatile char *)rxq->rx_ring)[i] = 0;
 215
 216         memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
 217
 218         for (i = 0; i < IAVF_RX_MAX_BURST; i++)
 219                 rxq->sw_ring[rxq->nb_rx_desc + i] = &rxq->fake_mbuf;
 220
 221         /* for rx bulk */
 222         rxq->rx_nb_avail = 0;
 223         rxq->rx_next_avail = 0;
 224         rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
 225
 226         rxq->rx_tail = 0;
 227         rxq->nb_rx_hold = 0;
 228         rxq->pkt_first_seg = NULL;
 229         rxq->pkt_last_seg = NULL;
 230         rxq->rxrearm_nb = 0;
 231         rxq->rxrearm_start = 0;
 232 }
 233
 234 static inline void
 235 reset_tx_queue(struct iavf_tx_queue *txq)
 236 {
 237         struct iavf_tx_entry *txe;
 238         uint32_t i, size;
 239         uint16_t prev;
 240
 241         if (!txq) {
 242                 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
 243                 return;
 244         }
 245
 246         txe = txq->sw_ring;
 247         size = sizeof(struct iavf_tx_desc) * txq->nb_tx_desc;
 248         for (i = 0; i < size; i++)
 249                 ((volatile char *)txq->tx_ring)[i] = 0;
 250
 251         prev = (uint16_t)(txq->nb_tx_desc - 1);
 252         for (i = 0; i < txq->nb_tx_desc; i++) {
 253                 txq->tx_ring[i].cmd_type_offset_bsz =
 254                         rte_cpu_to_le_64(IAVF_TX_DESC_DTYPE_DESC_DONE);
 255                 txe[i].mbuf =  NULL;
 256                 txe[i].last_id = i;
 257                 txe[prev].next_id = i;
 258                 prev = i;
 259         }
 260
 261         txq->tx_tail = 0;
 262         txq->nb_used = 0;
 263
 264         txq->last_desc_cleaned = txq->nb_tx_desc - 1;
 265         txq->nb_free = txq->nb_tx_desc - 1;
 266
 267         txq->next_dd = txq->rs_thresh - 1;
 268         txq->next_rs = txq->rs_thresh - 1;
 269 }
 270
 271 static int
 272 alloc_rxq_mbufs(struct iavf_rx_queue *rxq)
 273 {
 274         volatile union iavf_rx_desc *rxd;
 275         struct rte_mbuf *mbuf = NULL;
 276         uint64_t dma_addr;
 277         uint16_t i;
 278
 279         for (i = 0; i < rxq->nb_rx_desc; i++) {
 280                 mbuf = rte_mbuf_raw_alloc(rxq->mp);
 281                 if (unlikely(!mbuf)) {
 282                         PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
 283                         return -ENOMEM;
 284                 }
 285
 286                 rte_mbuf_refcnt_set(mbuf, 1);
 287                 mbuf->next = NULL;
 288                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
 289                 mbuf->nb_segs = 1;
 290                 mbuf->port = rxq->port_id;
 291
 292                 dma_addr =
 293                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
 294
 295                 rxd = &rxq->rx_ring[i];
 296                 rxd->read.pkt_addr = dma_addr;
 297                 rxd->read.hdr_addr = 0;
 298 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
 299                 rxd->read.rsvd1 = 0;
 300                 rxd->read.rsvd2 = 0;
 301 #endif
 302
 303                 rxq->sw_ring[i] = mbuf;
 304         }
 305
 306         return 0;
 307 }
 308
 309 static inline void
 310 release_rxq_mbufs(struct iavf_rx_queue *rxq)
 311 {
 312         uint16_t i;
 313
 314         if (!rxq->sw_ring)
 315                 return;
 316
 317         for (i = 0; i < rxq->nb_rx_desc; i++) {
 318                 if (rxq->sw_ring[i]) {
 319                         rte_pktmbuf_free_seg(rxq->sw_ring[i]);
 320                         rxq->sw_ring[i] = NULL;
 321                 }
 322         }
 323
 324         /* for rx bulk */
 325         if (rxq->rx_nb_avail == 0)
 326                 return;
 327         for (i = 0; i < rxq->rx_nb_avail; i++) {
 328                 struct rte_mbuf *mbuf;
 329
 330                 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
 331                 rte_pktmbuf_free_seg(mbuf);
 332         }
 333         rxq->rx_nb_avail = 0;
 334 }
 335
 336 static inline void
 337 release_txq_mbufs(struct iavf_tx_queue *txq)
 338 {
 339         uint16_t i;
 340
 341         if (!txq || !txq->sw_ring) {
 342                 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
 343                 return;
 344         }
 345
 346         for (i = 0; i < txq->nb_tx_desc; i++) {
 347                 if (txq->sw_ring[i].mbuf) {
 348                         rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
 349                         txq->sw_ring[i].mbuf = NULL;
 350                 }
 351         }
 352 }
 353
 354 static const struct iavf_rxq_ops def_rxq_ops = {
 355         .release_mbufs = release_rxq_mbufs,
 356 };
 357
 358 static const struct iavf_txq_ops def_txq_ops = {
 359         .release_mbufs = release_txq_mbufs,
 360 };
 361
 362 static inline void
 363 iavf_rxd_to_pkt_fields_by_comms_ovs(__rte_unused struct iavf_rx_queue *rxq,
 364                                     struct rte_mbuf *mb,
 365                                     volatile union iavf_rx_flex_desc *rxdp)
 366 {
 367         volatile struct iavf_32b_rx_flex_desc_comms_ovs *desc =
 368                         (volatile struct iavf_32b_rx_flex_desc_comms_ovs *)rxdp;
 369 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
 370         uint16_t stat_err;
 371 #endif
 372
 373         if (desc->flow_id != 0xFFFFFFFF) {
 374                 mb->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
 375                 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
 376         }
 377
 378 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
 379         stat_err = rte_le_to_cpu_16(desc->status_error0);
 380         if (likely(stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
 381                 mb->ol_flags |= PKT_RX_RSS_HASH;
 382                 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
 383         }
 384 #endif
 385 }
 386
 387 static inline void
 388 iavf_rxd_to_pkt_fields_by_comms_aux_v1(struct iavf_rx_queue *rxq,
 389                                        struct rte_mbuf *mb,
 390                                        volatile union iavf_rx_flex_desc *rxdp)
 391 {
 392         volatile struct iavf_32b_rx_flex_desc_comms *desc =
 393                         (volatile struct iavf_32b_rx_flex_desc_comms *)rxdp;
 394         uint16_t stat_err;
 395
 396         stat_err = rte_le_to_cpu_16(desc->status_error0);
 397         if (likely(stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
 398                 mb->ol_flags |= PKT_RX_RSS_HASH;
 399                 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
 400         }
 401
 402 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
 403         if (desc->flow_id != 0xFFFFFFFF) {
 404                 mb->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
 405                 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
 406         }
 407
 408         if (rxq->xtr_ol_flag) {
 409                 uint32_t metadata = 0;
 410
 411                 stat_err = rte_le_to_cpu_16(desc->status_error1);
 412
 413                 if (stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS1_XTRMD4_VALID_S))
 414                         metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux0);
 415
 416                 if (stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS1_XTRMD5_VALID_S))
 417                         metadata |=
 418                                 rte_le_to_cpu_16(desc->flex_ts.flex.aux1) << 16;
 419
 420                 if (metadata) {
 421                         mb->ol_flags |= rxq->xtr_ol_flag;
 422
 423                         *RTE_PMD_IFD_DYNF_PROTO_XTR_METADATA(mb) = metadata;
 424                 }
 425         }
 426 #endif
 427 }
 428
 429 static inline void
 430 iavf_rxd_to_pkt_fields_by_comms_aux_v2(struct iavf_rx_queue *rxq,
 431                                        struct rte_mbuf *mb,
 432                                        volatile union iavf_rx_flex_desc *rxdp)
 433 {
 434         volatile struct iavf_32b_rx_flex_desc_comms *desc =
 435                         (volatile struct iavf_32b_rx_flex_desc_comms *)rxdp;
 436         uint16_t stat_err;
 437
 438         stat_err = rte_le_to_cpu_16(desc->status_error0);
 439         if (likely(stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
 440                 mb->ol_flags |= PKT_RX_RSS_HASH;
 441                 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
 442         }
 443
 444 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
 445         if (desc->flow_id != 0xFFFFFFFF) {
 446                 mb->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
 447                 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
 448         }
 449
 450         if (rxq->xtr_ol_flag) {
 451                 uint32_t metadata = 0;
 452
 453                 if (desc->flex_ts.flex.aux0 != 0xFFFF)
 454                         metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux0);
 455                 else if (desc->flex_ts.flex.aux1 != 0xFFFF)
 456                         metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux1);
 457
 458                 if (metadata) {
 459                         mb->ol_flags |= rxq->xtr_ol_flag;
 460
 461                         *RTE_PMD_IFD_DYNF_PROTO_XTR_METADATA(mb) = metadata;
 462                 }
 463         }
 464 #endif
 465 }
 466
 467 static void
 468 iavf_select_rxd_to_pkt_fields_handler(struct iavf_rx_queue *rxq, uint32_t rxdid)
 469 {
 470         switch (rxdid) {
 471         case IAVF_RXDID_COMMS_AUX_VLAN:
 472                 rxq->xtr_ol_flag = rte_pmd_ifd_dynflag_proto_xtr_vlan_mask;
 473                 rxq->rxd_to_pkt_fields =
 474                         iavf_rxd_to_pkt_fields_by_comms_aux_v1;
 475                 break;
 476         case IAVF_RXDID_COMMS_AUX_IPV4:
 477                 rxq->xtr_ol_flag = rte_pmd_ifd_dynflag_proto_xtr_ipv4_mask;
 478                 rxq->rxd_to_pkt_fields =
 479                         iavf_rxd_to_pkt_fields_by_comms_aux_v1;
 480                 break;
 481         case IAVF_RXDID_COMMS_AUX_IPV6:
 482                 rxq->xtr_ol_flag = rte_pmd_ifd_dynflag_proto_xtr_ipv6_mask;
 483                 rxq->rxd_to_pkt_fields =
 484                         iavf_rxd_to_pkt_fields_by_comms_aux_v1;
 485                 break;
 486         case IAVF_RXDID_COMMS_AUX_IPV6_FLOW:
 487                 rxq->xtr_ol_flag =
 488                         rte_pmd_ifd_dynflag_proto_xtr_ipv6_flow_mask;
 489                 rxq->rxd_to_pkt_fields =
 490                         iavf_rxd_to_pkt_fields_by_comms_aux_v1;
 491                 break;
 492         case IAVF_RXDID_COMMS_AUX_TCP:
 493                 rxq->xtr_ol_flag = rte_pmd_ifd_dynflag_proto_xtr_tcp_mask;
 494                 rxq->rxd_to_pkt_fields =
 495                         iavf_rxd_to_pkt_fields_by_comms_aux_v1;
 496                 break;
 497         case IAVF_RXDID_COMMS_AUX_IP_OFFSET:
 498                 rxq->xtr_ol_flag =
 499                         rte_pmd_ifd_dynflag_proto_xtr_ip_offset_mask;
 500                 rxq->rxd_to_pkt_fields =
 501                         iavf_rxd_to_pkt_fields_by_comms_aux_v2;
 502                 break;
 503         case IAVF_RXDID_COMMS_OVS_1:
 504                 rxq->rxd_to_pkt_fields = iavf_rxd_to_pkt_fields_by_comms_ovs;
 505                 break;
 506         default:
 507                 /* update this according to the RXDID for FLEX_DESC_NONE */
 508                 rxq->rxd_to_pkt_fields = iavf_rxd_to_pkt_fields_by_comms_ovs;
 509                 break;
 510         }
 511
 512         if (!rte_pmd_ifd_dynf_proto_xtr_metadata_avail())
 513                 rxq->xtr_ol_flag = 0;
 514 }
 515
 516 int
 517 iavf_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 518                        uint16_t nb_desc, unsigned int socket_id,
 519                        const struct rte_eth_rxconf *rx_conf,
 520                        struct rte_mempool *mp)
 521 {
 522         struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 523         struct iavf_adapter *ad =
 524                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 525         struct iavf_info *vf =
 526                 IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 527         struct iavf_vsi *vsi = &vf->vsi;
 528         struct iavf_rx_queue *rxq;
 529         const struct rte_memzone *mz;
 530         uint32_t ring_size;
 531         uint8_t proto_xtr;
 532         uint16_t len;
 533         uint16_t rx_free_thresh;
 534         uint64_t offloads;
 535
 536         PMD_INIT_FUNC_TRACE();
 537
 538         offloads = rx_conf->offloads | dev->data->dev_conf.rxmode.offloads;
 539
 540         if (nb_desc % IAVF_ALIGN_RING_DESC != 0 ||
 541             nb_desc > IAVF_MAX_RING_DESC ||
 542             nb_desc < IAVF_MIN_RING_DESC) {
 543                 PMD_INIT_LOG(ERR, "Number (%u) of receive descriptors is "
 544                              "invalid", nb_desc);
 545                 return -EINVAL;
 546         }
 547
 548         /* Check free threshold */
 549         rx_free_thresh = (rx_conf->rx_free_thresh == 0) ?
 550                          IAVF_DEFAULT_RX_FREE_THRESH :
 551                          rx_conf->rx_free_thresh;
 552         if (check_rx_thresh(nb_desc, rx_free_thresh) != 0)
 553                 return -EINVAL;
 554
 555         /* Free memory if needed */
 556         if (dev->data->rx_queues[queue_idx]) {
 557                 iavf_dev_rx_queue_release(dev->data->rx_queues[queue_idx]);
 558                 dev->data->rx_queues[queue_idx] = NULL;
 559         }
 560
 561         /* Allocate the rx queue data structure */
 562         rxq = rte_zmalloc_socket("iavf rxq",
 563                                  sizeof(struct iavf_rx_queue),
 564                                  RTE_CACHE_LINE_SIZE,
 565                                  socket_id);
 566         if (!rxq) {
 567                 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
 568                              "rx queue data structure");
 569                 return -ENOMEM;
 570         }
 571
 572         if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC) {
 573                 proto_xtr = vf->proto_xtr ? vf->proto_xtr[queue_idx] :
 574                                 IAVF_PROTO_XTR_NONE;
 575                 rxq->rxdid = iavf_proto_xtr_type_to_rxdid(proto_xtr);
 576                 rxq->proto_xtr = proto_xtr;
 577         } else {
 578                 rxq->rxdid = IAVF_RXDID_LEGACY_1;
 579                 rxq->proto_xtr = IAVF_PROTO_XTR_NONE;
 580         }
 581
 582         if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_VLAN_V2) {
 583                 struct virtchnl_vlan_supported_caps *stripping_support =
 584                                 &vf->vlan_v2_caps.offloads.stripping_support;
 585                 uint32_t stripping_cap;
 586
 587                 if (stripping_support->outer)
 588                         stripping_cap = stripping_support->outer;
 589                 else
 590                         stripping_cap = stripping_support->inner;
 591
 592                 if (stripping_cap & VIRTCHNL_VLAN_TAG_LOCATION_L2TAG1)
 593                         rxq->rx_flags = IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG1;
 594                 else if (stripping_cap & VIRTCHNL_VLAN_TAG_LOCATION_L2TAG2_2)
 595                         rxq->rx_flags = IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG2_2;
 596         } else {
 597                 rxq->rx_flags = IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG1;
 598         }
 599
 600         iavf_select_rxd_to_pkt_fields_handler(rxq, rxq->rxdid);
 601
 602         rxq->mp = mp;
 603         rxq->nb_rx_desc = nb_desc;
 604         rxq->rx_free_thresh = rx_free_thresh;
 605         rxq->queue_id = queue_idx;
 606         rxq->port_id = dev->data->port_id;
 607         rxq->rx_deferred_start = rx_conf->rx_deferred_start;
 608         rxq->rx_hdr_len = 0;
 609         rxq->vsi = vsi;
 610         rxq->offloads = offloads;
 611
 612         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
 613                 rxq->crc_len = RTE_ETHER_CRC_LEN;
 614         else
 615                 rxq->crc_len = 0;
 616
 617         len = rte_pktmbuf_data_room_size(rxq->mp) - RTE_PKTMBUF_HEADROOM;
 618         rxq->rx_buf_len = RTE_ALIGN(len, (1 << IAVF_RXQ_CTX_DBUFF_SHIFT));
 619
 620         /* Allocate the software ring. */
 621         len = nb_desc + IAVF_RX_MAX_BURST;
 622         rxq->sw_ring =
 623                 rte_zmalloc_socket("iavf rx sw ring",
 624                                    sizeof(struct rte_mbuf *) * len,
 625                                    RTE_CACHE_LINE_SIZE,
 626                                    socket_id);
 627         if (!rxq->sw_ring) {
 628                 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW ring");
 629                 rte_free(rxq);
 630                 return -ENOMEM;
 631         }
 632
 633         /* Allocate the maximun number of RX ring hardware descriptor with
 634          * a liitle more to support bulk allocate.
 635          */
 636         len = IAVF_MAX_RING_DESC + IAVF_RX_MAX_BURST;
 637         ring_size = RTE_ALIGN(len * sizeof(union iavf_rx_desc),
 638                               IAVF_DMA_MEM_ALIGN);
 639         mz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
 640                                       ring_size, IAVF_RING_BASE_ALIGN,
 641                                       socket_id);
 642         if (!mz) {
 643                 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for RX");
 644                 rte_free(rxq->sw_ring);
 645                 rte_free(rxq);
 646                 return -ENOMEM;
 647         }
 648         /* Zero all the descriptors in the ring. */
 649         memset(mz->addr, 0, ring_size);
 650         rxq->rx_ring_phys_addr = mz->iova;
 651         rxq->rx_ring = (union iavf_rx_desc *)mz->addr;
 652
 653         rxq->mz = mz;
 654         reset_rx_queue(rxq);
 655         rxq->q_set = true;
 656         dev->data->rx_queues[queue_idx] = rxq;
 657         rxq->qrx_tail = hw->hw_addr + IAVF_QRX_TAIL1(rxq->queue_id);
 658         rxq->ops = &def_rxq_ops;
 659
 660         if (check_rx_bulk_allow(rxq) == true) {
 661                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
 662                              "satisfied. Rx Burst Bulk Alloc function will be "
 663                              "used on port=%d, queue=%d.",
 664                              rxq->port_id, rxq->queue_id);
 665         } else {
 666                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
 667                              "not satisfied, Scattered Rx is requested "
 668                              "on port=%d, queue=%d.",
 669                              rxq->port_id, rxq->queue_id);
 670                 ad->rx_bulk_alloc_allowed = false;
 671         }
 672
 673         if (check_rx_vec_allow(rxq) == false)
 674                 ad->rx_vec_allowed = false;
 675
 676         return 0;
 677 }
 678
 679 int
 680 iavf_dev_tx_queue_setup(struct rte_eth_dev *dev,
 681                        uint16_t queue_idx,
 682                        uint16_t nb_desc,
 683                        unsigned int socket_id,
 684                        const struct rte_eth_txconf *tx_conf)
 685 {
 686         struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 687         struct iavf_info *vf =
 688                 IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 689         struct iavf_tx_queue *txq;
 690         const struct rte_memzone *mz;
 691         uint32_t ring_size;
 692         uint16_t tx_rs_thresh, tx_free_thresh;
 693         uint64_t offloads;
 694
 695         PMD_INIT_FUNC_TRACE();
 696
 697         offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
 698
 699         if (nb_desc % IAVF_ALIGN_RING_DESC != 0 ||
 700             nb_desc > IAVF_MAX_RING_DESC ||
 701             nb_desc < IAVF_MIN_RING_DESC) {
 702                 PMD_INIT_LOG(ERR, "Number (%u) of transmit descriptors is "
 703                             "invalid", nb_desc);
 704                 return -EINVAL;
 705         }
 706
 707         tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
 708                 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
 709         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
 710                 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
 711         check_tx_thresh(nb_desc, tx_rs_thresh, tx_rs_thresh);
 712
 713         /* Free memory if needed. */
 714         if (dev->data->tx_queues[queue_idx]) {
 715                 iavf_dev_tx_queue_release(dev->data->tx_queues[queue_idx]);
 716                 dev->data->tx_queues[queue_idx] = NULL;
 717         }
 718
 719         /* Allocate the TX queue data structure. */
 720         txq = rte_zmalloc_socket("iavf txq",
 721                                  sizeof(struct iavf_tx_queue),
 722                                  RTE_CACHE_LINE_SIZE,
 723                                  socket_id);
 724         if (!txq) {
 725                 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
 726                              "tx queue structure");
 727                 return -ENOMEM;
 728         }
 729
 730         if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_VLAN_V2) {
 731                 struct virtchnl_vlan_supported_caps *insertion_support =
 732                         &vf->vlan_v2_caps.offloads.insertion_support;
 733                 uint32_t insertion_cap;
 734
 735                 if (insertion_support->outer)
 736                         insertion_cap = insertion_support->outer;
 737                 else
 738                         insertion_cap = insertion_support->inner;
 739
 740                 if (insertion_cap & VIRTCHNL_VLAN_TAG_LOCATION_L2TAG1)
 741                         txq->vlan_flag = IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG1;
 742                 else if (insertion_cap & VIRTCHNL_VLAN_TAG_LOCATION_L2TAG2)
 743                         txq->vlan_flag = IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG2;
 744         } else {
 745                 txq->vlan_flag = IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG1;
 746         }
 747
 748         txq->nb_tx_desc = nb_desc;
 749         txq->rs_thresh = tx_rs_thresh;
 750         txq->free_thresh = tx_free_thresh;
 751         txq->queue_id = queue_idx;
 752         txq->port_id = dev->data->port_id;
 753         txq->offloads = offloads;
 754         txq->tx_deferred_start = tx_conf->tx_deferred_start;
 755
 756         /* Allocate software ring */
 757         txq->sw_ring =
 758                 rte_zmalloc_socket("iavf tx sw ring",
 759                                    sizeof(struct iavf_tx_entry) * nb_desc,
 760                                    RTE_CACHE_LINE_SIZE,
 761                                    socket_id);
 762         if (!txq->sw_ring) {
 763                 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW TX ring");
 764                 rte_free(txq);
 765                 return -ENOMEM;
 766         }
 767
 768         /* Allocate TX hardware ring descriptors. */
 769         ring_size = sizeof(struct iavf_tx_desc) * IAVF_MAX_RING_DESC;
 770         ring_size = RTE_ALIGN(ring_size, IAVF_DMA_MEM_ALIGN);
 771         mz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
 772                                       ring_size, IAVF_RING_BASE_ALIGN,
 773                                       socket_id);
 774         if (!mz) {
 775                 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for TX");
 776                 rte_free(txq->sw_ring);
 777                 rte_free(txq);
 778                 return -ENOMEM;
 779         }
 780         txq->tx_ring_phys_addr = mz->iova;
 781         txq->tx_ring = (struct iavf_tx_desc *)mz->addr;
 782
 783         txq->mz = mz;
 784         reset_tx_queue(txq);
 785         txq->q_set = true;
 786         dev->data->tx_queues[queue_idx] = txq;
 787         txq->qtx_tail = hw->hw_addr + IAVF_QTX_TAIL1(queue_idx);
 788         txq->ops = &def_txq_ops;
 789
 790         if (check_tx_vec_allow(txq) == false) {
 791                 struct iavf_adapter *ad =
 792                         IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 793                 ad->tx_vec_allowed = false;
 794         }
 795
 796         if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_QOS &&
 797             vf->tm_conf.committed) {
 798                 int tc;
 799                 for (tc = 0; tc < vf->qos_cap->num_elem; tc++) {
 800                         if (txq->queue_id >= vf->qtc_map[tc].start_queue_id &&
 801                             txq->queue_id < (vf->qtc_map[tc].start_queue_id +
 802                             vf->qtc_map[tc].queue_count))
 803                                 break;
 804                 }
 805                 if (tc >= vf->qos_cap->num_elem) {
 806                         PMD_INIT_LOG(ERR, "Queue TC mapping is not correct");
 807                         return -EINVAL;
 808                 }
 809                 txq->tc = tc;
 810         }
 811
 812         return 0;
 813 }
 814
 815 int
 816 iavf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 817 {
 818         struct iavf_adapter *adapter =
 819                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 820         struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 821         struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 822         struct iavf_rx_queue *rxq;
 823         int err = 0;
 824
 825         PMD_DRV_FUNC_TRACE();
 826
 827         if (rx_queue_id >= dev->data->nb_rx_queues)
 828                 return -EINVAL;
 829
 830         rxq = dev->data->rx_queues[rx_queue_id];
 831
 832         err = alloc_rxq_mbufs(rxq);
 833         if (err) {
 834                 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
 835                 return err;
 836         }
 837
 838         rte_wmb();
 839
 840         /* Init the RX tail register. */
 841         IAVF_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 842         IAVF_WRITE_FLUSH(hw);
 843
 844         /* Ready to switch the queue on */
 845         if (!vf->lv_enabled)
 846                 err = iavf_switch_queue(adapter, rx_queue_id, true, true);
 847         else
 848                 err = iavf_switch_queue_lv(adapter, rx_queue_id, true, true);
 849
 850         if (err)
 851                 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
 852                             rx_queue_id);
 853         else
 854                 dev->data->rx_queue_state[rx_queue_id] =
 855                         RTE_ETH_QUEUE_STATE_STARTED;
 856
 857         return err;
 858 }
 859
 860 int
 861 iavf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 862 {
 863         struct iavf_adapter *adapter =
 864                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 865         struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 866         struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 867         struct iavf_tx_queue *txq;
 868         int err = 0;
 869
 870         PMD_DRV_FUNC_TRACE();
 871
 872         if (tx_queue_id >= dev->data->nb_tx_queues)
 873                 return -EINVAL;
 874
 875         txq = dev->data->tx_queues[tx_queue_id];
 876
 877         /* Init the RX tail register. */
 878         IAVF_PCI_REG_WRITE(txq->qtx_tail, 0);
 879         IAVF_WRITE_FLUSH(hw);
 880
 881         /* Ready to switch the queue on */
 882         if (!vf->lv_enabled)
 883                 err = iavf_switch_queue(adapter, tx_queue_id, false, true);
 884         else
 885                 err = iavf_switch_queue_lv(adapter, tx_queue_id, false, true);
 886
 887         if (err)
 888                 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
 889                             tx_queue_id);
 890         else
 891                 dev->data->tx_queue_state[tx_queue_id] =
 892                         RTE_ETH_QUEUE_STATE_STARTED;
 893
 894         return err;
 895 }
 896
 897 int
 898 iavf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 899 {
 900         struct iavf_adapter *adapter =
 901                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 902         struct iavf_rx_queue *rxq;
 903         int err;
 904
 905         PMD_DRV_FUNC_TRACE();
 906
 907         if (rx_queue_id >= dev->data->nb_rx_queues)
 908                 return -EINVAL;
 909
 910         err = iavf_switch_queue(adapter, rx_queue_id, true, false);
 911         if (err) {
 912                 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
 913                             rx_queue_id);
 914                 return err;
 915         }
 916
 917         rxq = dev->data->rx_queues[rx_queue_id];
 918         rxq->ops->release_mbufs(rxq);
 919         reset_rx_queue(rxq);
 920         dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 921
 922         return 0;
 923 }
 924
 925 int
 926 iavf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 927 {
 928         struct iavf_adapter *adapter =
 929                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 930         struct iavf_tx_queue *txq;
 931         int err;
 932
 933         PMD_DRV_FUNC_TRACE();
 934
 935         if (tx_queue_id >= dev->data->nb_tx_queues)
 936                 return -EINVAL;
 937
 938         err = iavf_switch_queue(adapter, tx_queue_id, false, false);
 939         if (err) {
 940                 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u off",
 941                             tx_queue_id);
 942                 return err;
 943         }
 944
 945         txq = dev->data->tx_queues[tx_queue_id];
 946         txq->ops->release_mbufs(txq);
 947         reset_tx_queue(txq);
 948         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 949
 950         return 0;
 951 }
 952
 953 void
 954 iavf_dev_rx_queue_release(void *rxq)
 955 {
 956         struct iavf_rx_queue *q = (struct iavf_rx_queue *)rxq;
 957
 958         if (!q)
 959                 return;
 960
 961         q->ops->release_mbufs(q);
 962         rte_free(q->sw_ring);
 963         rte_memzone_free(q->mz);
 964         rte_free(q);
 965 }
 966
 967 void
 968 iavf_dev_tx_queue_release(void *txq)
 969 {
 970         struct iavf_tx_queue *q = (struct iavf_tx_queue *)txq;
 971
 972         if (!q)
 973                 return;
 974
 975         q->ops->release_mbufs(q);
 976         rte_free(q->sw_ring);
 977         rte_memzone_free(q->mz);
 978         rte_free(q);
 979 }
 980
 981 void
 982 iavf_stop_queues(struct rte_eth_dev *dev)
 983 {
 984         struct iavf_adapter *adapter =
 985                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 986         struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 987         struct iavf_rx_queue *rxq;
 988         struct iavf_tx_queue *txq;
 989         int ret, i;
 990
 991         /* Stop All queues */
 992         if (!vf->lv_enabled) {
 993                 ret = iavf_disable_queues(adapter);
 994                 if (ret)
 995                         PMD_DRV_LOG(WARNING, "Fail to stop queues");
 996         } else {
 997                 ret = iavf_disable_queues_lv(adapter);
 998                 if (ret)
 999                         PMD_DRV_LOG(WARNING, "Fail to stop queues for large VF");
1000         }
1001
1002         if (ret)
1003                 PMD_DRV_LOG(WARNING, "Fail to stop queues");
1004
1005         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1006                 txq = dev->data->tx_queues[i];
1007                 if (!txq)
1008                         continue;
1009                 txq->ops->release_mbufs(txq);
1010                 reset_tx_queue(txq);
1011                 dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED;
1012         }
1013         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1014                 rxq = dev->data->rx_queues[i];
1015                 if (!rxq)
1016                         continue;
1017                 rxq->ops->release_mbufs(rxq);
1018                 reset_rx_queue(rxq);
1019                 dev->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED;
1020         }
1021 }
1022
1023 #define IAVF_RX_FLEX_ERR0_BITS  \
1024         ((1 << IAVF_RX_FLEX_DESC_STATUS0_HBO_S) |       \
1025          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_IPE_S) |  \
1026          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_L4E_S) |  \
1027          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S) | \
1028          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S) |        \
1029          (1 << IAVF_RX_FLEX_DESC_STATUS0_RXE_S))
1030
1031 static inline void
1032 iavf_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union iavf_rx_desc *rxdp)
1033 {
1034         if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1035                 (1 << IAVF_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
1036                 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1037                 mb->vlan_tci =
1038                         rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
1039         } else {
1040                 mb->vlan_tci = 0;
1041         }
1042 }
1043
1044 static inline void
1045 iavf_flex_rxd_to_vlan_tci(struct rte_mbuf *mb,
1046                           volatile union iavf_rx_flex_desc *rxdp,
1047                           uint8_t rx_flags)
1048 {
1049         uint16_t vlan_tci = 0;
1050
1051         if (rx_flags & IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG1 &&
1052             rte_le_to_cpu_64(rxdp->wb.status_error0) &
1053             (1 << IAVF_RX_FLEX_DESC_STATUS0_L2TAG1P_S))
1054                 vlan_tci = rte_le_to_cpu_16(rxdp->wb.l2tag1);
1055
1056 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
1057         if (rx_flags & IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG2_2 &&
1058             rte_le_to_cpu_16(rxdp->wb.status_error1) &
1059             (1 << IAVF_RX_FLEX_DESC_STATUS1_L2TAG2P_S))
1060                 vlan_tci = rte_le_to_cpu_16(rxdp->wb.l2tag2_2nd);
1061 #endif
1062
1063         if (vlan_tci) {
1064                 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1065                 mb->vlan_tci = vlan_tci;
1066         }
1067 }
1068
1069 /* Translate the rx descriptor status and error fields to pkt flags */
1070 static inline uint64_t
1071 iavf_rxd_to_pkt_flags(uint64_t qword)
1072 {
1073         uint64_t flags;
1074         uint64_t error_bits = (qword >> IAVF_RXD_QW1_ERROR_SHIFT);
1075
1076 #define IAVF_RX_ERR_BITS 0x3f
1077
1078         /* Check if RSS_HASH */
1079         flags = (((qword >> IAVF_RX_DESC_STATUS_FLTSTAT_SHIFT) &
1080                                         IAVF_RX_DESC_FLTSTAT_RSS_HASH) ==
1081                         IAVF_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;
1082
1083         /* Check if FDIR Match */
1084         flags |= (qword & (1 << IAVF_RX_DESC_STATUS_FLM_SHIFT) ?
1085                                 PKT_RX_FDIR : 0);
1086
1087         if (likely((error_bits & IAVF_RX_ERR_BITS) == 0)) {
1088                 flags |= (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD);
1089                 return flags;
1090         }
1091
1092         if (unlikely(error_bits & (1 << IAVF_RX_DESC_ERROR_IPE_SHIFT)))
1093                 flags |= PKT_RX_IP_CKSUM_BAD;
1094         else
1095                 flags |= PKT_RX_IP_CKSUM_GOOD;
1096
1097         if (unlikely(error_bits & (1 << IAVF_RX_DESC_ERROR_L4E_SHIFT)))
1098                 flags |= PKT_RX_L4_CKSUM_BAD;
1099         else
1100                 flags |= PKT_RX_L4_CKSUM_GOOD;
1101
1102         /* TODO: Oversize error bit is not processed here */
1103
1104         return flags;
1105 }
1106
1107 static inline uint64_t
1108 iavf_rxd_build_fdir(volatile union iavf_rx_desc *rxdp, struct rte_mbuf *mb)
1109 {
1110         uint64_t flags = 0;
1111 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
1112         uint16_t flexbh;
1113
1114         flexbh = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
1115                 IAVF_RX_DESC_EXT_STATUS_FLEXBH_SHIFT) &
1116                 IAVF_RX_DESC_EXT_STATUS_FLEXBH_MASK;
1117
1118         if (flexbh == IAVF_RX_DESC_EXT_STATUS_FLEXBH_FD_ID) {
1119                 mb->hash.fdir.hi =
1120                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.fd_id);
1121                 flags |= PKT_RX_FDIR_ID;
1122         }
1123 #else
1124         mb->hash.fdir.hi =
1125                 rte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.fd_id);
1126         flags |= PKT_RX_FDIR_ID;
1127 #endif
1128         return flags;
1129 }
1130
1131 #define IAVF_RX_FLEX_ERR0_BITS  \
1132         ((1 << IAVF_RX_FLEX_DESC_STATUS0_HBO_S) |       \
1133          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_IPE_S) |  \
1134          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_L4E_S) |  \
1135          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S) | \
1136          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S) |        \
1137          (1 << IAVF_RX_FLEX_DESC_STATUS0_RXE_S))
1138
1139 /* Rx L3/L4 checksum */
1140 static inline uint64_t
1141 iavf_flex_rxd_error_to_pkt_flags(uint16_t stat_err0)
1142 {
1143         uint64_t flags = 0;
1144
1145         /* check if HW has decoded the packet and checksum */
1146         if (unlikely(!(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_L3L4P_S))))
1147                 return 0;
1148
1149         if (likely(!(stat_err0 & IAVF_RX_FLEX_ERR0_BITS))) {
1150                 flags |= (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD);
1151                 return flags;
1152         }
1153
1154         if (unlikely(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_IPE_S)))
1155                 flags |= PKT_RX_IP_CKSUM_BAD;
1156         else
1157                 flags |= PKT_RX_IP_CKSUM_GOOD;
1158
1159         if (unlikely(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_L4E_S)))
1160                 flags |= PKT_RX_L4_CKSUM_BAD;
1161         else
1162                 flags |= PKT_RX_L4_CKSUM_GOOD;
1163
1164         if (unlikely(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S)))
1165                 flags |= PKT_RX_OUTER_IP_CKSUM_BAD;
1166
1167         return flags;
1168 }
1169
1170 /* If the number of free RX descriptors is greater than the RX free
1171  * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1172  * register. Update the RDT with the value of the last processed RX
1173  * descriptor minus 1, to guarantee that the RDT register is never
1174  * equal to the RDH register, which creates a "full" ring situation
1175  * from the hardware point of view.
1176  */
1177 static inline void
1178 iavf_update_rx_tail(struct iavf_rx_queue *rxq, uint16_t nb_hold, uint16_t rx_id)
1179 {
1180         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1181
1182         if (nb_hold > rxq->rx_free_thresh) {
1183                 PMD_RX_LOG(DEBUG,
1184                            "port_id=%u queue_id=%u rx_tail=%u nb_hold=%u",
1185                            rxq->port_id, rxq->queue_id, rx_id, nb_hold);
1186                 rx_id = (uint16_t)((rx_id == 0) ?
1187                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
1188                 IAVF_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
1189                 nb_hold = 0;
1190         }
1191         rxq->nb_rx_hold = nb_hold;
1192 }
1193
1194 /* implement recv_pkts */
1195 uint16_t
1196 iavf_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1197 {
1198         volatile union iavf_rx_desc *rx_ring;
1199         volatile union iavf_rx_desc *rxdp;
1200         struct iavf_rx_queue *rxq;
1201         union iavf_rx_desc rxd;
1202         struct rte_mbuf *rxe;
1203         struct rte_eth_dev *dev;
1204         struct rte_mbuf *rxm;
1205         struct rte_mbuf *nmb;
1206         uint16_t nb_rx;
1207         uint32_t rx_status;
1208         uint64_t qword1;
1209         uint16_t rx_packet_len;
1210         uint16_t rx_id, nb_hold;
1211         uint64_t dma_addr;
1212         uint64_t pkt_flags;
1213         const uint32_t *ptype_tbl;
1214
1215         nb_rx = 0;
1216         nb_hold = 0;
1217         rxq = rx_queue;
1218         rx_id = rxq->rx_tail;
1219         rx_ring = rxq->rx_ring;
1220         ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1221
1222         while (nb_rx < nb_pkts) {
1223                 rxdp = &rx_ring[rx_id];
1224                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1225                 rx_status = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
1226                             IAVF_RXD_QW1_STATUS_SHIFT;
1227
1228                 /* Check the DD bit first */
1229                 if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)))
1230                         break;
1231                 IAVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
1232
1233                 nmb = rte_mbuf_raw_alloc(rxq->mp);
1234                 if (unlikely(!nmb)) {
1235                         dev = &rte_eth_devices[rxq->port_id];
1236                         dev->data->rx_mbuf_alloc_failed++;
1237                         PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1238                                    "queue_id=%u", rxq->port_id, rxq->queue_id);
1239                         break;
1240                 }
1241
1242                 rxd = *rxdp;
1243                 nb_hold++;
1244                 rxe = rxq->sw_ring[rx_id];
1245                 rxq->sw_ring[rx_id] = nmb;
1246                 rx_id++;
1247                 if (unlikely(rx_id == rxq->nb_rx_desc))
1248                         rx_id = 0;
1249
1250                 /* Prefetch next mbuf */
1251                 rte_prefetch0(rxq->sw_ring[rx_id]);
1252
1253                 /* When next RX descriptor is on a cache line boundary,
1254                  * prefetch the next 4 RX descriptors and next 8 pointers
1255                  * to mbufs.
1256                  */
1257                 if ((rx_id & 0x3) == 0) {
1258                         rte_prefetch0(&rx_ring[rx_id]);
1259                         rte_prefetch0(rxq->sw_ring[rx_id]);
1260                 }
1261                 rxm = rxe;
1262                 dma_addr =
1263                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1264                 rxdp->read.hdr_addr = 0;
1265                 rxdp->read.pkt_addr = dma_addr;
1266
1267                 rx_packet_len = ((qword1 & IAVF_RXD_QW1_LENGTH_PBUF_MASK) >>
1268                                 IAVF_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
1269
1270                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1271                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
1272                 rxm->nb_segs = 1;
1273                 rxm->next = NULL;
1274                 rxm->pkt_len = rx_packet_len;
1275                 rxm->data_len = rx_packet_len;
1276                 rxm->port = rxq->port_id;
1277                 rxm->ol_flags = 0;
1278                 iavf_rxd_to_vlan_tci(rxm, &rxd);
1279                 pkt_flags = iavf_rxd_to_pkt_flags(qword1);
1280                 rxm->packet_type =
1281                         ptype_tbl[(uint8_t)((qword1 &
1282                         IAVF_RXD_QW1_PTYPE_MASK) >> IAVF_RXD_QW1_PTYPE_SHIFT)];
1283
1284                 if (pkt_flags & PKT_RX_RSS_HASH)
1285                         rxm->hash.rss =
1286                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1287
1288                 if (pkt_flags & PKT_RX_FDIR)
1289                         pkt_flags |= iavf_rxd_build_fdir(&rxd, rxm);
1290
1291                 rxm->ol_flags |= pkt_flags;
1292
1293                 rx_pkts[nb_rx++] = rxm;
1294         }
1295         rxq->rx_tail = rx_id;
1296
1297         iavf_update_rx_tail(rxq, nb_hold, rx_id);
1298
1299         return nb_rx;
1300 }
1301
1302 /* implement recv_pkts for flexible Rx descriptor */
1303 uint16_t
1304 iavf_recv_pkts_flex_rxd(void *rx_queue,
1305                         struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1306 {
1307         volatile union iavf_rx_desc *rx_ring;
1308         volatile union iavf_rx_flex_desc *rxdp;
1309         struct iavf_rx_queue *rxq;
1310         union iavf_rx_flex_desc rxd;
1311         struct rte_mbuf *rxe;
1312         struct rte_eth_dev *dev;
1313         struct rte_mbuf *rxm;
1314         struct rte_mbuf *nmb;
1315         uint16_t nb_rx;
1316         uint16_t rx_stat_err0;
1317         uint16_t rx_packet_len;
1318         uint16_t rx_id, nb_hold;
1319         uint64_t dma_addr;
1320         uint64_t pkt_flags;
1321         const uint32_t *ptype_tbl;
1322
1323         nb_rx = 0;
1324         nb_hold = 0;
1325         rxq = rx_queue;
1326         rx_id = rxq->rx_tail;
1327         rx_ring = rxq->rx_ring;
1328         ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1329
1330         while (nb_rx < nb_pkts) {
1331                 rxdp = (volatile union iavf_rx_flex_desc *)&rx_ring[rx_id];
1332                 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1333
1334                 /* Check the DD bit first */
1335                 if (!(rx_stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S)))
1336                         break;
1337                 IAVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
1338
1339                 nmb = rte_mbuf_raw_alloc(rxq->mp);
1340                 if (unlikely(!nmb)) {
1341                         dev = &rte_eth_devices[rxq->port_id];
1342                         dev->data->rx_mbuf_alloc_failed++;
1343                         PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1344                                    "queue_id=%u", rxq->port_id, rxq->queue_id);
1345                         break;
1346                 }
1347
1348                 rxd = *rxdp;
1349                 nb_hold++;
1350                 rxe = rxq->sw_ring[rx_id];
1351                 rxq->sw_ring[rx_id] = nmb;
1352                 rx_id++;
1353                 if (unlikely(rx_id == rxq->nb_rx_desc))
1354                         rx_id = 0;
1355
1356                 /* Prefetch next mbuf */
1357                 rte_prefetch0(rxq->sw_ring[rx_id]);
1358
1359                 /* When next RX descriptor is on a cache line boundary,
1360                  * prefetch the next 4 RX descriptors and next 8 pointers
1361                  * to mbufs.
1362                  */
1363                 if ((rx_id & 0x3) == 0) {
1364                         rte_prefetch0(&rx_ring[rx_id]);
1365                         rte_prefetch0(rxq->sw_ring[rx_id]);
1366                 }
1367                 rxm = rxe;
1368                 dma_addr =
1369                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1370                 rxdp->read.hdr_addr = 0;
1371                 rxdp->read.pkt_addr = dma_addr;
1372
1373                 rx_packet_len = (rte_le_to_cpu_16(rxd.wb.pkt_len) &
1374                                 IAVF_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
1375
1376                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1377                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
1378                 rxm->nb_segs = 1;
1379                 rxm->next = NULL;
1380                 rxm->pkt_len = rx_packet_len;
1381                 rxm->data_len = rx_packet_len;
1382                 rxm->port = rxq->port_id;
1383                 rxm->ol_flags = 0;
1384                 rxm->packet_type = ptype_tbl[IAVF_RX_FLEX_DESC_PTYPE_M &
1385                         rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
1386                 iavf_flex_rxd_to_vlan_tci(rxm, &rxd, rxq->rx_flags);
1387                 rxq->rxd_to_pkt_fields(rxq, rxm, &rxd);
1388                 pkt_flags = iavf_flex_rxd_error_to_pkt_flags(rx_stat_err0);
1389                 rxm->ol_flags |= pkt_flags;
1390
1391                 rx_pkts[nb_rx++] = rxm;
1392         }
1393         rxq->rx_tail = rx_id;
1394
1395         iavf_update_rx_tail(rxq, nb_hold, rx_id);
1396
1397         return nb_rx;
1398 }
1399
1400 /* implement recv_scattered_pkts for flexible Rx descriptor */
1401 uint16_t
1402 iavf_recv_scattered_pkts_flex_rxd(void *rx_queue, struct rte_mbuf **rx_pkts,
1403                                   uint16_t nb_pkts)
1404 {
1405         struct iavf_rx_queue *rxq = rx_queue;
1406         union iavf_rx_flex_desc rxd;
1407         struct rte_mbuf *rxe;
1408         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1409         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1410         struct rte_mbuf *nmb, *rxm;
1411         uint16_t rx_id = rxq->rx_tail;
1412         uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
1413         struct rte_eth_dev *dev;
1414         uint16_t rx_stat_err0;
1415         uint64_t dma_addr;
1416         uint64_t pkt_flags;
1417
1418         volatile union iavf_rx_desc *rx_ring = rxq->rx_ring;
1419         volatile union iavf_rx_flex_desc *rxdp;
1420         const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1421
1422         while (nb_rx < nb_pkts) {
1423                 rxdp = (volatile union iavf_rx_flex_desc *)&rx_ring[rx_id];
1424                 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1425
1426                 /* Check the DD bit */
1427                 if (!(rx_stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S)))
1428                         break;
1429                 IAVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
1430
1431                 nmb = rte_mbuf_raw_alloc(rxq->mp);
1432                 if (unlikely(!nmb)) {
1433                         PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1434                                    "queue_id=%u", rxq->port_id, rxq->queue_id);
1435                         dev = &rte_eth_devices[rxq->port_id];
1436                         dev->data->rx_mbuf_alloc_failed++;
1437                         break;
1438                 }
1439
1440                 rxd = *rxdp;
1441                 nb_hold++;
1442                 rxe = rxq->sw_ring[rx_id];
1443                 rxq->sw_ring[rx_id] = nmb;
1444                 rx_id++;
1445                 if (rx_id == rxq->nb_rx_desc)
1446                         rx_id = 0;
1447
1448                 /* Prefetch next mbuf */
1449                 rte_prefetch0(rxq->sw_ring[rx_id]);
1450
1451                 /* When next RX descriptor is on a cache line boundary,
1452                  * prefetch the next 4 RX descriptors and next 8 pointers
1453                  * to mbufs.
1454                  */
1455                 if ((rx_id & 0x3) == 0) {
1456                         rte_prefetch0(&rx_ring[rx_id]);
1457                         rte_prefetch0(rxq->sw_ring[rx_id]);
1458                 }
1459
1460                 rxm = rxe;
1461                 dma_addr =
1462                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1463
1464                 /* Set data buffer address and data length of the mbuf */
1465                 rxdp->read.hdr_addr = 0;
1466                 rxdp->read.pkt_addr = dma_addr;
1467                 rx_packet_len = rte_le_to_cpu_16(rxd.wb.pkt_len) &
1468                                 IAVF_RX_FLX_DESC_PKT_LEN_M;
1469                 rxm->data_len = rx_packet_len;
1470                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1471
1472                 /* If this is the first buffer of the received packet, set the
1473                  * pointer to the first mbuf of the packet and initialize its
1474                  * context. Otherwise, update the total length and the number
1475                  * of segments of the current scattered packet, and update the
1476                  * pointer to the last mbuf of the current packet.
1477                  */
1478                 if (!first_seg) {
1479                         first_seg = rxm;
1480                         first_seg->nb_segs = 1;
1481                         first_seg->pkt_len = rx_packet_len;
1482                 } else {
1483                         first_seg->pkt_len =
1484                                 (uint16_t)(first_seg->pkt_len +
1485                                                 rx_packet_len);
1486                         first_seg->nb_segs++;
1487                         last_seg->next = rxm;
1488                 }
1489
1490                 /* If this is not the last buffer of the received packet,
1491                  * update the pointer to the last mbuf of the current scattered
1492                  * packet and continue to parse the RX ring.
1493                  */
1494                 if (!(rx_stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_EOF_S))) {
1495                         last_seg = rxm;
1496                         continue;
1497                 }
1498
1499                 /* This is the last buffer of the received packet. If the CRC
1500                  * is not stripped by the hardware:
1501                  *  - Subtract the CRC length from the total packet length.
1502                  *  - If the last buffer only contains the whole CRC or a part
1503                  *  of it, free the mbuf associated to the last buffer. If part
1504                  *  of the CRC is also contained in the previous mbuf, subtract
1505                  *  the length of that CRC part from the data length of the
1506                  *  previous mbuf.
1507                  */
1508                 rxm->next = NULL;
1509                 if (unlikely(rxq->crc_len > 0)) {
1510                         first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
1511                         if (rx_packet_len <= RTE_ETHER_CRC_LEN) {
1512                                 rte_pktmbuf_free_seg(rxm);
1513                                 first_seg->nb_segs--;
1514                                 last_seg->data_len =
1515                                         (uint16_t)(last_seg->data_len -
1516                                         (RTE_ETHER_CRC_LEN - rx_packet_len));
1517                                 last_seg->next = NULL;
1518                         } else {
1519                                 rxm->data_len = (uint16_t)(rx_packet_len -
1520                                                         RTE_ETHER_CRC_LEN);
1521                         }
1522                 }
1523
1524                 first_seg->port = rxq->port_id;
1525                 first_seg->ol_flags = 0;
1526                 first_seg->packet_type = ptype_tbl[IAVF_RX_FLEX_DESC_PTYPE_M &
1527                         rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
1528                 iavf_flex_rxd_to_vlan_tci(first_seg, &rxd, rxq->rx_flags);
1529                 rxq->rxd_to_pkt_fields(rxq, first_seg, &rxd);
1530                 pkt_flags = iavf_flex_rxd_error_to_pkt_flags(rx_stat_err0);
1531
1532                 first_seg->ol_flags |= pkt_flags;
1533
1534                 /* Prefetch data of first segment, if configured to do so. */
1535                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1536                                           first_seg->data_off));
1537                 rx_pkts[nb_rx++] = first_seg;
1538                 first_seg = NULL;
1539         }
1540
1541         /* Record index of the next RX descriptor to probe. */
1542         rxq->rx_tail = rx_id;
1543         rxq->pkt_first_seg = first_seg;
1544         rxq->pkt_last_seg = last_seg;
1545
1546         iavf_update_rx_tail(rxq, nb_hold, rx_id);
1547
1548         return nb_rx;
1549 }
1550
1551 /* implement recv_scattered_pkts  */
1552 uint16_t
1553 iavf_recv_scattered_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1554                         uint16_t nb_pkts)
1555 {
1556         struct iavf_rx_queue *rxq = rx_queue;
1557         union iavf_rx_desc rxd;
1558         struct rte_mbuf *rxe;
1559         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1560         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1561         struct rte_mbuf *nmb, *rxm;
1562         uint16_t rx_id = rxq->rx_tail;
1563         uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
1564         struct rte_eth_dev *dev;
1565         uint32_t rx_status;
1566         uint64_t qword1;
1567         uint64_t dma_addr;
1568         uint64_t pkt_flags;
1569
1570         volatile union iavf_rx_desc *rx_ring = rxq->rx_ring;
1571         volatile union iavf_rx_desc *rxdp;
1572         const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1573
1574         while (nb_rx < nb_pkts) {
1575                 rxdp = &rx_ring[rx_id];
1576                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1577                 rx_status = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
1578                             IAVF_RXD_QW1_STATUS_SHIFT;
1579
1580                 /* Check the DD bit */
1581                 if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)))
1582                         break;
1583                 IAVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
1584
1585                 nmb = rte_mbuf_raw_alloc(rxq->mp);
1586                 if (unlikely(!nmb)) {
1587                         PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1588                                    "queue_id=%u", rxq->port_id, rxq->queue_id);
1589                         dev = &rte_eth_devices[rxq->port_id];
1590                         dev->data->rx_mbuf_alloc_failed++;
1591                         break;
1592                 }
1593
1594                 rxd = *rxdp;
1595                 nb_hold++;
1596                 rxe = rxq->sw_ring[rx_id];
1597                 rxq->sw_ring[rx_id] = nmb;
1598                 rx_id++;
1599                 if (rx_id == rxq->nb_rx_desc)
1600                         rx_id = 0;
1601
1602                 /* Prefetch next mbuf */
1603                 rte_prefetch0(rxq->sw_ring[rx_id]);
1604
1605                 /* When next RX descriptor is on a cache line boundary,
1606                  * prefetch the next 4 RX descriptors and next 8 pointers
1607                  * to mbufs.
1608                  */
1609                 if ((rx_id & 0x3) == 0) {
1610                         rte_prefetch0(&rx_ring[rx_id]);
1611                         rte_prefetch0(rxq->sw_ring[rx_id]);
1612                 }
1613
1614                 rxm = rxe;
1615                 dma_addr =
1616                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1617
1618                 /* Set data buffer address and data length of the mbuf */
1619                 rxdp->read.hdr_addr = 0;
1620                 rxdp->read.pkt_addr = dma_addr;
1621                 rx_packet_len = (qword1 & IAVF_RXD_QW1_LENGTH_PBUF_MASK) >>
1622                                  IAVF_RXD_QW1_LENGTH_PBUF_SHIFT;
1623                 rxm->data_len = rx_packet_len;
1624                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1625
1626                 /* If this is the first buffer of the received packet, set the
1627                  * pointer to the first mbuf of the packet and initialize its
1628                  * context. Otherwise, update the total length and the number
1629                  * of segments of the current scattered packet, and update the
1630                  * pointer to the last mbuf of the current packet.
1631                  */
1632                 if (!first_seg) {
1633                         first_seg = rxm;
1634                         first_seg->nb_segs = 1;
1635                         first_seg->pkt_len = rx_packet_len;
1636                 } else {
1637                         first_seg->pkt_len =
1638                                 (uint16_t)(first_seg->pkt_len +
1639                                                 rx_packet_len);
1640                         first_seg->nb_segs++;
1641                         last_seg->next = rxm;
1642                 }
1643
1644                 /* If this is not the last buffer of the received packet,
1645                  * update the pointer to the last mbuf of the current scattered
1646                  * packet and continue to parse the RX ring.
1647                  */
1648                 if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_EOF_SHIFT))) {
1649                         last_seg = rxm;
1650                         continue;
1651                 }
1652
1653                 /* This is the last buffer of the received packet. If the CRC
1654                  * is not stripped by the hardware:
1655                  *  - Subtract the CRC length from the total packet length.
1656                  *  - If the last buffer only contains the whole CRC or a part
1657                  *  of it, free the mbuf associated to the last buffer. If part
1658                  *  of the CRC is also contained in the previous mbuf, subtract
1659                  *  the length of that CRC part from the data length of the
1660                  *  previous mbuf.
1661                  */
1662                 rxm->next = NULL;
1663                 if (unlikely(rxq->crc_len > 0)) {
1664                         first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
1665                         if (rx_packet_len <= RTE_ETHER_CRC_LEN) {
1666                                 rte_pktmbuf_free_seg(rxm);
1667                                 first_seg->nb_segs--;
1668                                 last_seg->data_len =
1669                                         (uint16_t)(last_seg->data_len -
1670                                         (RTE_ETHER_CRC_LEN - rx_packet_len));
1671                                 last_seg->next = NULL;
1672                         } else
1673                                 rxm->data_len = (uint16_t)(rx_packet_len -
1674                                                         RTE_ETHER_CRC_LEN);
1675                 }
1676
1677                 first_seg->port = rxq->port_id;
1678                 first_seg->ol_flags = 0;
1679                 iavf_rxd_to_vlan_tci(first_seg, &rxd);
1680                 pkt_flags = iavf_rxd_to_pkt_flags(qword1);
1681                 first_seg->packet_type =
1682                         ptype_tbl[(uint8_t)((qword1 &
1683                         IAVF_RXD_QW1_PTYPE_MASK) >> IAVF_RXD_QW1_PTYPE_SHIFT)];
1684
1685                 if (pkt_flags & PKT_RX_RSS_HASH)
1686                         first_seg->hash.rss =
1687                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1688
1689                 if (pkt_flags & PKT_RX_FDIR)
1690                         pkt_flags |= iavf_rxd_build_fdir(&rxd, first_seg);
1691
1692                 first_seg->ol_flags |= pkt_flags;
1693
1694                 /* Prefetch data of first segment, if configured to do so. */
1695                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1696                                           first_seg->data_off));
1697                 rx_pkts[nb_rx++] = first_seg;
1698                 first_seg = NULL;
1699         }
1700
1701         /* Record index of the next RX descriptor to probe. */
1702         rxq->rx_tail = rx_id;
1703         rxq->pkt_first_seg = first_seg;
1704         rxq->pkt_last_seg = last_seg;
1705
1706         iavf_update_rx_tail(rxq, nb_hold, rx_id);
1707
1708         return nb_rx;
1709 }
1710
1711 #define IAVF_LOOK_AHEAD 8
1712 static inline int
1713 iavf_rx_scan_hw_ring_flex_rxd(struct iavf_rx_queue *rxq)
1714 {
1715         volatile union iavf_rx_flex_desc *rxdp;
1716         struct rte_mbuf **rxep;
1717         struct rte_mbuf *mb;
1718         uint16_t stat_err0;
1719         uint16_t pkt_len;
1720         int32_t s[IAVF_LOOK_AHEAD], nb_dd;
1721         int32_t i, j, nb_rx = 0;
1722         uint64_t pkt_flags;
1723         const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1724
1725         rxdp = (volatile union iavf_rx_flex_desc *)&rxq->rx_ring[rxq->rx_tail];
1726         rxep = &rxq->sw_ring[rxq->rx_tail];
1727
1728         stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1729
1730         /* Make sure there is at least 1 packet to receive */
1731         if (!(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S)))
1732                 return 0;
1733
1734         /* Scan LOOK_AHEAD descriptors at a time to determine which
1735          * descriptors reference packets that are ready to be received.
1736          */
1737         for (i = 0; i < IAVF_RX_MAX_BURST; i += IAVF_LOOK_AHEAD,
1738              rxdp += IAVF_LOOK_AHEAD, rxep += IAVF_LOOK_AHEAD) {
1739                 /* Read desc statuses backwards to avoid race condition */
1740                 for (j = IAVF_LOOK_AHEAD - 1; j >= 0; j--)
1741                         s[j] = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1742
1743                 rte_smp_rmb();
1744
1745                 /* Compute how many status bits were set */
1746                 for (j = 0, nb_dd = 0; j < IAVF_LOOK_AHEAD; j++)
1747                         nb_dd += s[j] & (1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S);
1748
1749                 nb_rx += nb_dd;
1750
1751                 /* Translate descriptor info to mbuf parameters */
1752                 for (j = 0; j < nb_dd; j++) {
1753                         IAVF_DUMP_RX_DESC(rxq, &rxdp[j],
1754                                           rxq->rx_tail +
1755                                           i * IAVF_LOOK_AHEAD + j);
1756
1757                         mb = rxep[j];
1758                         pkt_len = (rte_le_to_cpu_16(rxdp[j].wb.pkt_len) &
1759                                 IAVF_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
1760                         mb->data_len = pkt_len;
1761                         mb->pkt_len = pkt_len;
1762                         mb->ol_flags = 0;
1763
1764                         mb->packet_type = ptype_tbl[IAVF_RX_FLEX_DESC_PTYPE_M &
1765                                 rte_le_to_cpu_16(rxdp[j].wb.ptype_flex_flags0)];
1766                         iavf_flex_rxd_to_vlan_tci(mb, &rxdp[j], rxq->rx_flags);
1767                         rxq->rxd_to_pkt_fields(rxq, mb, &rxdp[j]);
1768                         stat_err0 = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1769                         pkt_flags = iavf_flex_rxd_error_to_pkt_flags(stat_err0);
1770
1771                         mb->ol_flags |= pkt_flags;
1772                 }
1773
1774                 for (j = 0; j < IAVF_LOOK_AHEAD; j++)
1775                         rxq->rx_stage[i + j] = rxep[j];
1776
1777                 if (nb_dd != IAVF_LOOK_AHEAD)
1778                         break;
1779         }
1780
1781         /* Clear software ring entries */
1782         for (i = 0; i < nb_rx; i++)
1783                 rxq->sw_ring[rxq->rx_tail + i] = NULL;
1784
1785         return nb_rx;
1786 }
1787
1788 static inline int
1789 iavf_rx_scan_hw_ring(struct iavf_rx_queue *rxq)
1790 {
1791         volatile union iavf_rx_desc *rxdp;
1792         struct rte_mbuf **rxep;
1793         struct rte_mbuf *mb;
1794         uint16_t pkt_len;
1795         uint64_t qword1;
1796         uint32_t rx_status;
1797         int32_t s[IAVF_LOOK_AHEAD], nb_dd;
1798         int32_t i, j, nb_rx = 0;
1799         uint64_t pkt_flags;
1800         const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1801
1802         rxdp = &rxq->rx_ring[rxq->rx_tail];
1803         rxep = &rxq->sw_ring[rxq->rx_tail];
1804
1805         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1806         rx_status = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
1807                     IAVF_RXD_QW1_STATUS_SHIFT;
1808
1809         /* Make sure there is at least 1 packet to receive */
1810         if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)))
1811                 return 0;
1812
1813         /* Scan LOOK_AHEAD descriptors at a time to determine which
1814          * descriptors reference packets that are ready to be received.
1815          */
1816         for (i = 0; i < IAVF_RX_MAX_BURST; i += IAVF_LOOK_AHEAD,
1817              rxdp += IAVF_LOOK_AHEAD, rxep += IAVF_LOOK_AHEAD) {
1818                 /* Read desc statuses backwards to avoid race condition */
1819                 for (j = IAVF_LOOK_AHEAD - 1; j >= 0; j--) {
1820                         qword1 = rte_le_to_cpu_64(
1821                                 rxdp[j].wb.qword1.status_error_len);
1822                         s[j] = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
1823                                IAVF_RXD_QW1_STATUS_SHIFT;
1824                 }
1825
1826                 rte_smp_rmb();
1827
1828                 /* Compute how many status bits were set */
1829                 for (j = 0, nb_dd = 0; j < IAVF_LOOK_AHEAD; j++)
1830                         nb_dd += s[j] & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT);
1831
1832                 nb_rx += nb_dd;
1833
1834                 /* Translate descriptor info to mbuf parameters */
1835                 for (j = 0; j < nb_dd; j++) {
1836                         IAVF_DUMP_RX_DESC(rxq, &rxdp[j],
1837                                          rxq->rx_tail + i * IAVF_LOOK_AHEAD + j);
1838
1839                         mb = rxep[j];
1840                         qword1 = rte_le_to_cpu_64
1841                                         (rxdp[j].wb.qword1.status_error_len);
1842                         pkt_len = ((qword1 & IAVF_RXD_QW1_LENGTH_PBUF_MASK) >>
1843                                   IAVF_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
1844                         mb->data_len = pkt_len;
1845                         mb->pkt_len = pkt_len;
1846                         mb->ol_flags = 0;
1847                         iavf_rxd_to_vlan_tci(mb, &rxdp[j]);
1848                         pkt_flags = iavf_rxd_to_pkt_flags(qword1);
1849                         mb->packet_type =
1850                                 ptype_tbl[(uint8_t)((qword1 &
1851                                 IAVF_RXD_QW1_PTYPE_MASK) >>
1852                                 IAVF_RXD_QW1_PTYPE_SHIFT)];
1853
1854                         if (pkt_flags & PKT_RX_RSS_HASH)
1855                                 mb->hash.rss = rte_le_to_cpu_32(
1856                                         rxdp[j].wb.qword0.hi_dword.rss);
1857
1858                         if (pkt_flags & PKT_RX_FDIR)
1859                                 pkt_flags |= iavf_rxd_build_fdir(&rxdp[j], mb);
1860
1861                         mb->ol_flags |= pkt_flags;
1862                 }
1863
1864                 for (j = 0; j < IAVF_LOOK_AHEAD; j++)
1865                         rxq->rx_stage[i + j] = rxep[j];
1866
1867                 if (nb_dd != IAVF_LOOK_AHEAD)
1868                         break;
1869         }
1870
1871         /* Clear software ring entries */
1872         for (i = 0; i < nb_rx; i++)
1873                 rxq->sw_ring[rxq->rx_tail + i] = NULL;
1874
1875         return nb_rx;
1876 }
1877
1878 static inline uint16_t
1879 iavf_rx_fill_from_stage(struct iavf_rx_queue *rxq,
1880                        struct rte_mbuf **rx_pkts,
1881                        uint16_t nb_pkts)
1882 {
1883         uint16_t i;
1884         struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1885
1886         nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1887
1888         for (i = 0; i < nb_pkts; i++)
1889                 rx_pkts[i] = stage[i];
1890
1891         rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1892         rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1893
1894         return nb_pkts;
1895 }
1896
1897 static inline int
1898 iavf_rx_alloc_bufs(struct iavf_rx_queue *rxq)
1899 {
1900         volatile union iavf_rx_desc *rxdp;
1901         struct rte_mbuf **rxep;
1902         struct rte_mbuf *mb;
1903         uint16_t alloc_idx, i;
1904         uint64_t dma_addr;
1905         int diag;
1906
1907         /* Allocate buffers in bulk */
1908         alloc_idx = (uint16_t)(rxq->rx_free_trigger -
1909                                 (rxq->rx_free_thresh - 1));
1910         rxep = &rxq->sw_ring[alloc_idx];
1911         diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
1912                                     rxq->rx_free_thresh);
1913         if (unlikely(diag != 0)) {
1914                 PMD_RX_LOG(ERR, "Failed to get mbufs in bulk");
1915                 return -ENOMEM;
1916         }
1917
1918         rxdp = &rxq->rx_ring[alloc_idx];
1919         for (i = 0; i < rxq->rx_free_thresh; i++) {
1920                 if (likely(i < (rxq->rx_free_thresh - 1)))
1921                         /* Prefetch next mbuf */
1922                         rte_prefetch0(rxep[i + 1]);
1923
1924                 mb = rxep[i];
1925                 rte_mbuf_refcnt_set(mb, 1);
1926                 mb->next = NULL;
1927                 mb->data_off = RTE_PKTMBUF_HEADROOM;
1928                 mb->nb_segs = 1;
1929                 mb->port = rxq->port_id;
1930                 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mb));
1931                 rxdp[i].read.hdr_addr = 0;
1932                 rxdp[i].read.pkt_addr = dma_addr;
1933         }
1934
1935         /* Update rx tail register */
1936         rte_wmb();
1937         IAVF_PCI_REG_WC_WRITE_RELAXED(rxq->qrx_tail, rxq->rx_free_trigger);
1938
1939         rxq->rx_free_trigger =
1940                 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
1941         if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1942                 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
1943
1944         return 0;
1945 }
1946
1947 static inline uint16_t
1948 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1949 {
1950         struct iavf_rx_queue *rxq = (struct iavf_rx_queue *)rx_queue;
1951         uint16_t nb_rx = 0;
1952
1953         if (!nb_pkts)
1954                 return 0;
1955
1956         if (rxq->rx_nb_avail)
1957                 return iavf_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1958
1959         if (rxq->rxdid >= IAVF_RXDID_FLEX_NIC && rxq->rxdid <= IAVF_RXDID_LAST)
1960                 nb_rx = (uint16_t)iavf_rx_scan_hw_ring_flex_rxd(rxq);
1961         else
1962                 nb_rx = (uint16_t)iavf_rx_scan_hw_ring(rxq);
1963         rxq->rx_next_avail = 0;
1964         rxq->rx_nb_avail = nb_rx;
1965         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1966
1967         if (rxq->rx_tail > rxq->rx_free_trigger) {
1968                 if (iavf_rx_alloc_bufs(rxq) != 0) {
1969                         uint16_t i, j;
1970
1971                         /* TODO: count rx_mbuf_alloc_failed here */
1972
1973                         rxq->rx_nb_avail = 0;
1974                         rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1975                         for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
1976                                 rxq->sw_ring[j] = rxq->rx_stage[i];
1977
1978                         return 0;
1979                 }
1980         }
1981
1982         if (rxq->rx_tail >= rxq->nb_rx_desc)
1983                 rxq->rx_tail = 0;
1984
1985         PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u, nb_rx=%u",
1986                    rxq->port_id, rxq->queue_id,
1987                    rxq->rx_tail, nb_rx);
1988
1989         if (rxq->rx_nb_avail)
1990                 return iavf_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1991
1992         return 0;
1993 }
1994
1995 static uint16_t
1996 iavf_recv_pkts_bulk_alloc(void *rx_queue,
1997                          struct rte_mbuf **rx_pkts,
1998                          uint16_t nb_pkts)
1999 {
2000         uint16_t nb_rx = 0, n, count;
2001
2002         if (unlikely(nb_pkts == 0))
2003                 return 0;
2004
2005         if (likely(nb_pkts <= IAVF_RX_MAX_BURST))
2006                 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
2007
2008         while (nb_pkts) {
2009                 n = RTE_MIN(nb_pkts, IAVF_RX_MAX_BURST);
2010                 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
2011                 nb_rx = (uint16_t)(nb_rx + count);
2012                 nb_pkts = (uint16_t)(nb_pkts - count);
2013                 if (count < n)
2014                         break;
2015         }
2016
2017         return nb_rx;
2018 }
2019
2020 static inline int
2021 iavf_xmit_cleanup(struct iavf_tx_queue *txq)
2022 {
2023         struct iavf_tx_entry *sw_ring = txq->sw_ring;
2024         uint16_t last_desc_cleaned = txq->last_desc_cleaned;
2025         uint16_t nb_tx_desc = txq->nb_tx_desc;
2026         uint16_t desc_to_clean_to;
2027         uint16_t nb_tx_to_clean;
2028
2029         volatile struct iavf_tx_desc *txd = txq->tx_ring;
2030
2031         desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->rs_thresh);
2032         if (desc_to_clean_to >= nb_tx_desc)
2033                 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
2034
2035         desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
2036         if ((txd[desc_to_clean_to].cmd_type_offset_bsz &
2037                         rte_cpu_to_le_64(IAVF_TXD_QW1_DTYPE_MASK)) !=
2038                         rte_cpu_to_le_64(IAVF_TX_DESC_DTYPE_DESC_DONE)) {
2039                 PMD_TX_LOG(DEBUG, "TX descriptor %4u is not done "
2040                            "(port=%d queue=%d)", desc_to_clean_to,
2041                            txq->port_id, txq->queue_id);
2042                 return -1;
2043         }
2044
2045         if (last_desc_cleaned > desc_to_clean_to)
2046                 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
2047                                                         desc_to_clean_to);
2048         else
2049                 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
2050                                         last_desc_cleaned);
2051
2052         txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
2053
2054         txq->last_desc_cleaned = desc_to_clean_to;
2055         txq->nb_free = (uint16_t)(txq->nb_free + nb_tx_to_clean);
2056
2057         return 0;
2058 }
2059
2060 /* Check if the context descriptor is needed for TX offloading */
2061 static inline uint16_t
2062 iavf_calc_context_desc(uint64_t flags, uint8_t vlan_flag)
2063 {
2064         if (flags & PKT_TX_TCP_SEG)
2065                 return 1;
2066         if (flags & PKT_TX_VLAN_PKT &&
2067             vlan_flag & IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG2)
2068                 return 1;
2069         return 0;
2070 }
2071
2072 static inline void
2073 iavf_txd_enable_checksum(uint64_t ol_flags,
2074                         uint32_t *td_cmd,
2075                         uint32_t *td_offset,
2076                         union iavf_tx_offload tx_offload)
2077 {
2078         /* Set MACLEN */
2079         *td_offset |= (tx_offload.l2_len >> 1) <<
2080                       IAVF_TX_DESC_LENGTH_MACLEN_SHIFT;
2081
2082         /* Enable L3 checksum offloads */
2083         if (ol_flags & PKT_TX_IP_CKSUM) {
2084                 *td_cmd |= IAVF_TX_DESC_CMD_IIPT_IPV4_CSUM;
2085                 *td_offset |= (tx_offload.l3_len >> 2) <<
2086                               IAVF_TX_DESC_LENGTH_IPLEN_SHIFT;
2087         } else if (ol_flags & PKT_TX_IPV4) {
2088                 *td_cmd |= IAVF_TX_DESC_CMD_IIPT_IPV4;
2089                 *td_offset |= (tx_offload.l3_len >> 2) <<
2090                               IAVF_TX_DESC_LENGTH_IPLEN_SHIFT;
2091         } else if (ol_flags & PKT_TX_IPV6) {
2092                 *td_cmd |= IAVF_TX_DESC_CMD_IIPT_IPV6;
2093                 *td_offset |= (tx_offload.l3_len >> 2) <<
2094                               IAVF_TX_DESC_LENGTH_IPLEN_SHIFT;
2095         }
2096
2097         if (ol_flags & PKT_TX_TCP_SEG) {
2098                 *td_cmd |= IAVF_TX_DESC_CMD_L4T_EOFT_TCP;
2099                 *td_offset |= (tx_offload.l4_len >> 2) <<
2100                               IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2101                 return;
2102         }
2103
2104         /* Enable L4 checksum offloads */
2105         switch (ol_flags & PKT_TX_L4_MASK) {
2106         case PKT_TX_TCP_CKSUM:
2107                 *td_cmd |= IAVF_TX_DESC_CMD_L4T_EOFT_TCP;
2108                 *td_offset |= (sizeof(struct rte_tcp_hdr) >> 2) <<
2109                               IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2110                 break;
2111         case PKT_TX_SCTP_CKSUM:
2112                 *td_cmd |= IAVF_TX_DESC_CMD_L4T_EOFT_SCTP;
2113                 *td_offset |= (sizeof(struct rte_sctp_hdr) >> 2) <<
2114                               IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2115                 break;
2116         case PKT_TX_UDP_CKSUM:
2117                 *td_cmd |= IAVF_TX_DESC_CMD_L4T_EOFT_UDP;
2118                 *td_offset |= (sizeof(struct rte_udp_hdr) >> 2) <<
2119                               IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2120                 break;
2121         default:
2122                 break;
2123         }
2124 }
2125
2126 /* set TSO context descriptor
2127  * support IP -> L4 and IP -> IP -> L4
2128  */
2129 static inline uint64_t
2130 iavf_set_tso_ctx(struct rte_mbuf *mbuf, union iavf_tx_offload tx_offload)
2131 {
2132         uint64_t ctx_desc = 0;
2133         uint32_t cd_cmd, hdr_len, cd_tso_len;
2134
2135         if (!tx_offload.l4_len) {
2136                 PMD_TX_LOG(DEBUG, "L4 length set to 0");
2137                 return ctx_desc;
2138         }
2139
2140         hdr_len = tx_offload.l2_len +
2141                   tx_offload.l3_len +
2142                   tx_offload.l4_len;
2143
2144         cd_cmd = IAVF_TX_CTX_DESC_TSO;
2145         cd_tso_len = mbuf->pkt_len - hdr_len;
2146         ctx_desc |= ((uint64_t)cd_cmd << IAVF_TXD_CTX_QW1_CMD_SHIFT) |
2147                      ((uint64_t)cd_tso_len << IAVF_TXD_CTX_QW1_TSO_LEN_SHIFT) |
2148                      ((uint64_t)mbuf->tso_segsz << IAVF_TXD_CTX_QW1_MSS_SHIFT);
2149
2150         return ctx_desc;
2151 }
2152
2153 /* Construct the tx flags */
2154 static inline uint64_t
2155 iavf_build_ctob(uint32_t td_cmd, uint32_t td_offset, unsigned int size,
2156                uint32_t td_tag)
2157 {
2158         return rte_cpu_to_le_64(IAVF_TX_DESC_DTYPE_DATA |
2159                                 ((uint64_t)td_cmd  << IAVF_TXD_QW1_CMD_SHIFT) |
2160                                 ((uint64_t)td_offset <<
2161                                  IAVF_TXD_QW1_OFFSET_SHIFT) |
2162                                 ((uint64_t)size  <<
2163                                  IAVF_TXD_QW1_TX_BUF_SZ_SHIFT) |
2164                                 ((uint64_t)td_tag  <<
2165                                  IAVF_TXD_QW1_L2TAG1_SHIFT));
2166 }
2167
2168 /* TX function */
2169 uint16_t
2170 iavf_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2171 {
2172         volatile struct iavf_tx_desc *txd;
2173         volatile struct iavf_tx_desc *txr;
2174         struct iavf_tx_queue *txq;
2175         struct iavf_tx_entry *sw_ring;
2176         struct iavf_tx_entry *txe, *txn;
2177         struct rte_mbuf *tx_pkt;
2178         struct rte_mbuf *m_seg;
2179         uint16_t tx_id;
2180         uint16_t nb_tx;
2181         uint32_t td_cmd;
2182         uint32_t td_offset;
2183         uint32_t td_tag;
2184         uint64_t ol_flags;
2185         uint16_t nb_used;
2186         uint16_t nb_ctx;
2187         uint16_t tx_last;
2188         uint16_t slen;
2189         uint64_t buf_dma_addr;
2190         uint16_t cd_l2tag2 = 0;
2191         union iavf_tx_offload tx_offload = {0};
2192
2193         txq = tx_queue;
2194         sw_ring = txq->sw_ring;
2195         txr = txq->tx_ring;
2196         tx_id = txq->tx_tail;
2197         txe = &sw_ring[tx_id];
2198
2199         /* Check if the descriptor ring needs to be cleaned. */
2200         if (txq->nb_free < txq->free_thresh)
2201                 (void)iavf_xmit_cleanup(txq);
2202
2203         for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
2204                 td_cmd = 0;
2205                 td_tag = 0;
2206                 td_offset = 0;
2207
2208                 tx_pkt = *tx_pkts++;
2209                 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
2210
2211                 ol_flags = tx_pkt->ol_flags;
2212                 tx_offload.l2_len = tx_pkt->l2_len;
2213                 tx_offload.l3_len = tx_pkt->l3_len;
2214                 tx_offload.l4_len = tx_pkt->l4_len;
2215                 tx_offload.tso_segsz = tx_pkt->tso_segsz;
2216                 /* Calculate the number of context descriptors needed. */
2217                 nb_ctx = iavf_calc_context_desc(ol_flags, txq->vlan_flag);
2218
2219                 /* The number of descriptors that must be allocated for
2220                  * a packet equals to the number of the segments of that
2221                  * packet plus 1 context descriptor if needed.
2222                  */
2223                 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
2224                 tx_last = (uint16_t)(tx_id + nb_used - 1);
2225
2226                 /* Circular ring */
2227                 if (tx_last >= txq->nb_tx_desc)
2228                         tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
2229
2230                 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u"
2231                            " tx_first=%u tx_last=%u",
2232                            txq->port_id, txq->queue_id, tx_id, tx_last);
2233
2234                 if (nb_used > txq->nb_free) {
2235                         if (iavf_xmit_cleanup(txq)) {
2236                                 if (nb_tx == 0)
2237                                         return 0;
2238                                 goto end_of_tx;
2239                         }
2240                         if (unlikely(nb_used > txq->rs_thresh)) {
2241                                 while (nb_used > txq->nb_free) {
2242                                         if (iavf_xmit_cleanup(txq)) {
2243                                                 if (nb_tx == 0)
2244                                                         return 0;
2245                                                 goto end_of_tx;
2246                                         }
2247                                 }
2248                         }
2249                 }
2250
2251                 /* Descriptor based VLAN insertion */
2252                 if (ol_flags & PKT_TX_VLAN_PKT &&
2253                     txq->vlan_flag & IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG1) {
2254                         td_cmd |= IAVF_TX_DESC_CMD_IL2TAG1;
2255                         td_tag = tx_pkt->vlan_tci;
2256                 }
2257
2258                 /* According to datasheet, the bit2 is reserved and must be
2259                  * set to 1.
2260                  */
2261                 td_cmd |= 0x04;
2262
2263                 /* Enable checksum offloading */
2264                 if (ol_flags & IAVF_TX_CKSUM_OFFLOAD_MASK)
2265                         iavf_txd_enable_checksum(ol_flags, &td_cmd,
2266                                                 &td_offset, tx_offload);
2267
2268                 if (nb_ctx) {
2269                         /* Setup TX context descriptor if required */
2270                         uint64_t cd_type_cmd_tso_mss =
2271                                 IAVF_TX_DESC_DTYPE_CONTEXT;
2272                         volatile struct iavf_tx_context_desc *ctx_txd =
2273                                 (volatile struct iavf_tx_context_desc *)
2274                                                         &txr[tx_id];
2275
2276                         /* clear QW0 or the previous writeback value
2277                          * may impact next write
2278                          */
2279                         *(volatile uint64_t *)ctx_txd = 0;
2280
2281                         txn = &sw_ring[txe->next_id];
2282                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
2283                         if (txe->mbuf) {
2284                                 rte_pktmbuf_free_seg(txe->mbuf);
2285                                 txe->mbuf = NULL;
2286                         }
2287
2288                         /* TSO enabled */
2289                         if (ol_flags & PKT_TX_TCP_SEG)
2290                                 cd_type_cmd_tso_mss |=
2291                                         iavf_set_tso_ctx(tx_pkt, tx_offload);
2292
2293                         if (ol_flags & PKT_TX_VLAN_PKT &&
2294                            txq->vlan_flag & IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG2) {
2295                                 cd_type_cmd_tso_mss |= IAVF_TX_CTX_DESC_IL2TAG2
2296                                         << IAVF_TXD_CTX_QW1_CMD_SHIFT;
2297                                 cd_l2tag2 = tx_pkt->vlan_tci;
2298                         }
2299
2300                         ctx_txd->type_cmd_tso_mss =
2301                                 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
2302                         ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
2303
2304                         IAVF_DUMP_TX_DESC(txq, &txr[tx_id], tx_id);
2305                         txe->last_id = tx_last;
2306                         tx_id = txe->next_id;
2307                         txe = txn;
2308                 }
2309
2310                 m_seg = tx_pkt;
2311                 do {
2312                         txd = &txr[tx_id];
2313                         txn = &sw_ring[txe->next_id];
2314
2315                         if (txe->mbuf)
2316                                 rte_pktmbuf_free_seg(txe->mbuf);
2317                         txe->mbuf = m_seg;
2318
2319                         /* Setup TX Descriptor */
2320                         slen = m_seg->data_len;
2321                         buf_dma_addr = rte_mbuf_data_iova(m_seg);
2322                         txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
2323                         txd->cmd_type_offset_bsz = iavf_build_ctob(td_cmd,
2324                                                                   td_offset,
2325                                                                   slen,
2326                                                                   td_tag);
2327
2328                         IAVF_DUMP_TX_DESC(txq, txd, tx_id);
2329                         txe->last_id = tx_last;
2330                         tx_id = txe->next_id;
2331                         txe = txn;
2332                         m_seg = m_seg->next;
2333                 } while (m_seg);
2334
2335                 /* The last packet data descriptor needs End Of Packet (EOP) */
2336                 td_cmd |= IAVF_TX_DESC_CMD_EOP;
2337                 txq->nb_used = (uint16_t)(txq->nb_used + nb_used);
2338                 txq->nb_free = (uint16_t)(txq->nb_free - nb_used);
2339
2340                 if (txq->nb_used >= txq->rs_thresh) {
2341                         PMD_TX_LOG(DEBUG, "Setting RS bit on TXD id="
2342                                    "%4u (port=%d queue=%d)",
2343                                    tx_last, txq->port_id, txq->queue_id);
2344
2345                         td_cmd |= IAVF_TX_DESC_CMD_RS;
2346
2347                         /* Update txq RS bit counters */
2348                         txq->nb_used = 0;
2349                 }
2350
2351                 txd->cmd_type_offset_bsz |=
2352                         rte_cpu_to_le_64(((uint64_t)td_cmd) <<
2353                                          IAVF_TXD_QW1_CMD_SHIFT);
2354                 IAVF_DUMP_TX_DESC(txq, txd, tx_id);
2355         }
2356
2357 end_of_tx:
2358         rte_wmb();
2359
2360         PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
2361                    txq->port_id, txq->queue_id, tx_id, nb_tx);
2362
2363         IAVF_PCI_REG_WC_WRITE_RELAXED(txq->qtx_tail, tx_id);
2364         txq->tx_tail = tx_id;
2365
2366         return nb_tx;
2367 }
2368
2369 /* Check if the packet with vlan user priority is transmitted in the
2370  * correct queue.
2371  */
2372 static int
2373 iavf_check_vlan_up2tc(struct iavf_tx_queue *txq, struct rte_mbuf *m)
2374 {
2375         struct rte_eth_dev *dev = &rte_eth_devices[txq->port_id];
2376         struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2377         uint16_t up;
2378
2379         up = m->vlan_tci >> IAVF_VLAN_TAG_PCP_OFFSET;
2380
2381         if (!(vf->qos_cap->cap[txq->tc].tc_prio & BIT(up))) {
2382                 PMD_TX_LOG(ERR, "packet with vlan pcp %u cannot transmit in queue %u\n",
2383                         up, txq->queue_id);
2384                 return -1;
2385         } else {
2386                 return 0;
2387         }
2388 }
2389
2390 /* TX prep functions */
2391 uint16_t
2392 iavf_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
2393               uint16_t nb_pkts)
2394 {
2395         int i, ret;
2396         uint64_t ol_flags;
2397         struct rte_mbuf *m;
2398         struct iavf_tx_queue *txq = tx_queue;
2399         struct rte_eth_dev *dev = &rte_eth_devices[txq->port_id];
2400         struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2401
2402         for (i = 0; i < nb_pkts; i++) {
2403                 m = tx_pkts[i];
2404                 ol_flags = m->ol_flags;
2405
2406                 /* Check condition for nb_segs > IAVF_TX_MAX_MTU_SEG. */
2407                 if (!(ol_flags & PKT_TX_TCP_SEG)) {
2408                         if (m->nb_segs > IAVF_TX_MAX_MTU_SEG) {
2409                                 rte_errno = EINVAL;
2410                                 return i;
2411                         }
2412                 } else if ((m->tso_segsz < IAVF_MIN_TSO_MSS) ||
2413                            (m->tso_segsz > IAVF_MAX_TSO_MSS)) {
2414                         /* MSS outside the range are considered malicious */
2415                         rte_errno = EINVAL;
2416                         return i;
2417                 }
2418
2419                 if (ol_flags & IAVF_TX_OFFLOAD_NOTSUP_MASK) {
2420                         rte_errno = ENOTSUP;
2421                         return i;
2422                 }
2423
2424 #ifdef RTE_ETHDEV_DEBUG_TX
2425                 ret = rte_validate_tx_offload(m);
2426                 if (ret != 0) {
2427                         rte_errno = -ret;
2428                         return i;
2429                 }
2430 #endif
2431                 ret = rte_net_intel_cksum_prepare(m);
2432                 if (ret != 0) {
2433                         rte_errno = -ret;
2434                         return i;
2435                 }
2436
2437                 if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_QOS &&
2438                     ol_flags & (PKT_RX_VLAN_STRIPPED | PKT_RX_VLAN)) {
2439                         ret = iavf_check_vlan_up2tc(txq, m);
2440                         if (ret != 0) {
2441                                 rte_errno = -ret;
2442                                 return i;
2443                         }
2444                 }
2445         }
2446
2447         return i;
2448 }
2449
2450 /* choose rx function*/
2451 void
2452 iavf_set_rx_function(struct rte_eth_dev *dev)
2453 {
2454         struct iavf_adapter *adapter =
2455                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2456         struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2457
2458 #ifdef RTE_ARCH_X86
2459         struct iavf_rx_queue *rxq;
2460         int i;
2461         int check_ret;
2462         bool use_avx2 = false;
2463         bool use_avx512 = false;
2464         bool use_flex = false;
2465
2466         check_ret = iavf_rx_vec_dev_check(dev);
2467         if (check_ret >= 0 &&
2468             rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
2469                 if ((rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
2470                      rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) &&
2471                     rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256)
2472                         use_avx2 = true;
2473
2474 #ifdef CC_AVX512_SUPPORT
2475                 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 &&
2476                     rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1 &&
2477                     rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512)
2478                         use_avx512 = true;
2479 #endif
2480
2481                 if (vf->vf_res->vf_cap_flags &
2482                         VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC)
2483                         use_flex = true;
2484
2485                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2486                         rxq = dev->data->rx_queues[i];
2487                         (void)iavf_rxq_vec_setup(rxq);
2488                 }
2489
2490                 if (dev->data->scattered_rx) {
2491                         if (!use_avx512) {
2492                                 PMD_DRV_LOG(DEBUG,
2493                                             "Using %sVector Scattered Rx (port %d).",
2494                                             use_avx2 ? "avx2 " : "",
2495                                             dev->data->port_id);
2496                         } else {
2497                                 if (check_ret == IAVF_VECTOR_PATH)
2498                                         PMD_DRV_LOG(DEBUG,
2499                                                     "Using AVX512 Vector Scattered Rx (port %d).",
2500                                                     dev->data->port_id);
2501                                 else
2502                                         PMD_DRV_LOG(DEBUG,
2503                                                     "Using AVX512 OFFLOAD Vector Scattered Rx (port %d).",
2504                                                     dev->data->port_id);
2505                         }
2506                         if (use_flex) {
2507                                 dev->rx_pkt_burst = use_avx2 ?
2508                                         iavf_recv_scattered_pkts_vec_avx2_flex_rxd :
2509                                         iavf_recv_scattered_pkts_vec_flex_rxd;
2510 #ifdef CC_AVX512_SUPPORT
2511                                 if (use_avx512) {
2512                                         if (check_ret == IAVF_VECTOR_PATH)
2513                                                 dev->rx_pkt_burst =
2514                                                         iavf_recv_scattered_pkts_vec_avx512_flex_rxd;
2515                                         else
2516                                                 dev->rx_pkt_burst =
2517                                                         iavf_recv_scattered_pkts_vec_avx512_flex_rxd_offload;
2518                                 }
2519 #endif
2520                         } else {
2521                                 dev->rx_pkt_burst = use_avx2 ?
2522                                         iavf_recv_scattered_pkts_vec_avx2 :
2523                                         iavf_recv_scattered_pkts_vec;
2524 #ifdef CC_AVX512_SUPPORT
2525                                 if (use_avx512) {
2526                                         if (check_ret == IAVF_VECTOR_PATH)
2527                                                 dev->rx_pkt_burst =
2528                                                         iavf_recv_scattered_pkts_vec_avx512;
2529                                         else
2530                                                 dev->rx_pkt_burst =
2531                                                         iavf_recv_scattered_pkts_vec_avx512_offload;
2532                                 }
2533 #endif
2534                         }
2535                 } else {
2536                         if (!use_avx512) {
2537                                 PMD_DRV_LOG(DEBUG, "Using %sVector Rx (port %d).",
2538                                             use_avx2 ? "avx2 " : "",
2539                                             dev->data->port_id);
2540                         } else {
2541                                 if (check_ret == IAVF_VECTOR_PATH)
2542                                         PMD_DRV_LOG(DEBUG,
2543                                                     "Using AVX512 Vector Rx (port %d).",
2544                                                     dev->data->port_id);
2545                                 else
2546                                         PMD_DRV_LOG(DEBUG,
2547                                                     "Using AVX512 OFFLOAD Vector Rx (port %d).",
2548                                                     dev->data->port_id);
2549                         }
2550                         if (use_flex) {
2551                                 dev->rx_pkt_burst = use_avx2 ?
2552                                         iavf_recv_pkts_vec_avx2_flex_rxd :
2553                                         iavf_recv_pkts_vec_flex_rxd;
2554 #ifdef CC_AVX512_SUPPORT
2555                                 if (use_avx512) {
2556                                         if (check_ret == IAVF_VECTOR_PATH)
2557                                                 dev->rx_pkt_burst =
2558                                                         iavf_recv_pkts_vec_avx512_flex_rxd;
2559                                         else
2560                                                 dev->rx_pkt_burst =
2561                                                         iavf_recv_pkts_vec_avx512_flex_rxd_offload;
2562                                 }
2563 #endif
2564                         } else {
2565                                 dev->rx_pkt_burst = use_avx2 ?
2566                                         iavf_recv_pkts_vec_avx2 :
2567                                         iavf_recv_pkts_vec;
2568 #ifdef CC_AVX512_SUPPORT
2569                                 if (use_avx512) {
2570                                         if (check_ret == IAVF_VECTOR_PATH)
2571                                                 dev->rx_pkt_burst =
2572                                                         iavf_recv_pkts_vec_avx512;
2573                                         else
2574                                                 dev->rx_pkt_burst =
2575                                                         iavf_recv_pkts_vec_avx512_offload;
2576                                 }
2577 #endif
2578                         }
2579                 }
2580
2581                 return;
2582         }
2583
2584 #endif
2585         if (dev->data->scattered_rx) {
2586                 PMD_DRV_LOG(DEBUG, "Using a Scattered Rx callback (port=%d).",
2587                             dev->data->port_id);
2588                 if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC)
2589                         dev->rx_pkt_burst = iavf_recv_scattered_pkts_flex_rxd;
2590                 else
2591                         dev->rx_pkt_burst = iavf_recv_scattered_pkts;
2592         } else if (adapter->rx_bulk_alloc_allowed) {
2593                 PMD_DRV_LOG(DEBUG, "Using bulk Rx callback (port=%d).",
2594                             dev->data->port_id);
2595                 dev->rx_pkt_burst = iavf_recv_pkts_bulk_alloc;
2596         } else {
2597                 PMD_DRV_LOG(DEBUG, "Using Basic Rx callback (port=%d).",
2598                             dev->data->port_id);
2599                 if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC)
2600                         dev->rx_pkt_burst = iavf_recv_pkts_flex_rxd;
2601                 else
2602                         dev->rx_pkt_burst = iavf_recv_pkts;
2603         }
2604 }
2605
2606 /* choose tx function*/
2607 void
2608 iavf_set_tx_function(struct rte_eth_dev *dev)
2609 {
2610 #ifdef RTE_ARCH_X86
2611         struct iavf_tx_queue *txq;
2612         int i;
2613         int check_ret;
2614         bool use_sse = false;
2615         bool use_avx2 = false;
2616         bool use_avx512 = false;
2617
2618         check_ret = iavf_tx_vec_dev_check(dev);
2619
2620         if (check_ret >= 0 &&
2621             rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
2622                 /* SSE and AVX2 not support offload path yet. */
2623                 if (check_ret == IAVF_VECTOR_PATH) {
2624                         use_sse = true;
2625                         if ((rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
2626                              rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) &&
2627                             rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256)
2628                                 use_avx2 = true;
2629                 }
2630 #ifdef CC_AVX512_SUPPORT
2631                 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 &&
2632                     rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1 &&
2633                     rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512)
2634                         use_avx512 = true;
2635 #endif
2636
2637                 if (!use_sse && !use_avx2 && !use_avx512)
2638                         goto normal;
2639
2640                 if (!use_avx512) {
2641                         PMD_DRV_LOG(DEBUG, "Using %sVector Tx (port %d).",
2642                                     use_avx2 ? "avx2 " : "",
2643                                     dev->data->port_id);
2644                         dev->tx_pkt_burst = use_avx2 ?
2645                                             iavf_xmit_pkts_vec_avx2 :
2646                                             iavf_xmit_pkts_vec;
2647                 }
2648                 dev->tx_pkt_prepare = NULL;
2649 #ifdef CC_AVX512_SUPPORT
2650                 if (use_avx512) {
2651                         if (check_ret == IAVF_VECTOR_PATH) {
2652                                 dev->tx_pkt_burst = iavf_xmit_pkts_vec_avx512;
2653                                 PMD_DRV_LOG(DEBUG, "Using AVX512 Vector Tx (port %d).",
2654                                             dev->data->port_id);
2655                         } else {
2656                                 dev->tx_pkt_burst = iavf_xmit_pkts_vec_avx512_offload;
2657                                 dev->tx_pkt_prepare = iavf_prep_pkts;
2658                                 PMD_DRV_LOG(DEBUG, "Using AVX512 OFFLOAD Vector Tx (port %d).",
2659                                             dev->data->port_id);
2660                         }
2661                 }
2662 #endif
2663
2664                 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2665                         txq = dev->data->tx_queues[i];
2666                         if (!txq)
2667                                 continue;
2668 #ifdef CC_AVX512_SUPPORT
2669                         if (use_avx512)
2670                                 iavf_txq_vec_setup_avx512(txq);
2671                         else
2672                                 iavf_txq_vec_setup(txq);
2673 #else
2674                         iavf_txq_vec_setup(txq);
2675 #endif
2676                 }
2677
2678                 return;
2679         }
2680
2681 normal:
2682 #endif
2683         PMD_DRV_LOG(DEBUG, "Using Basic Tx callback (port=%d).",
2684                     dev->data->port_id);
2685         dev->tx_pkt_burst = iavf_xmit_pkts;
2686         dev->tx_pkt_prepare = iavf_prep_pkts;
2687 }
2688
2689 static int
2690 iavf_tx_done_cleanup_full(struct iavf_tx_queue *txq,
2691                         uint32_t free_cnt)
2692 {
2693         struct iavf_tx_entry *swr_ring = txq->sw_ring;
2694         uint16_t i, tx_last, tx_id;
2695         uint16_t nb_tx_free_last;
2696         uint16_t nb_tx_to_clean;
2697         uint32_t pkt_cnt;
2698
2699         /* Start free mbuf from the next of tx_tail */
2700         tx_last = txq->tx_tail;
2701         tx_id  = swr_ring[tx_last].next_id;
2702
2703         if (txq->nb_free == 0 && iavf_xmit_cleanup(txq))
2704                 return 0;
2705
2706         nb_tx_to_clean = txq->nb_free;
2707         nb_tx_free_last = txq->nb_free;
2708         if (!free_cnt)
2709                 free_cnt = txq->nb_tx_desc;
2710
2711         /* Loop through swr_ring to count the amount of
2712          * freeable mubfs and packets.
2713          */
2714         for (pkt_cnt = 0; pkt_cnt < free_cnt; ) {
2715                 for (i = 0; i < nb_tx_to_clean &&
2716                         pkt_cnt < free_cnt &&
2717                         tx_id != tx_last; i++) {
2718                         if (swr_ring[tx_id].mbuf != NULL) {
2719                                 rte_pktmbuf_free_seg(swr_ring[tx_id].mbuf);
2720                                 swr_ring[tx_id].mbuf = NULL;
2721
2722                                 /*
2723                                  * last segment in the packet,
2724                                  * increment packet count
2725                                  */
2726                                 pkt_cnt += (swr_ring[tx_id].last_id == tx_id);
2727                         }
2728
2729                         tx_id = swr_ring[tx_id].next_id;
2730                 }
2731
2732                 if (txq->rs_thresh > txq->nb_tx_desc -
2733                         txq->nb_free || tx_id == tx_last)
2734                         break;
2735
2736                 if (pkt_cnt < free_cnt) {
2737                         if (iavf_xmit_cleanup(txq))
2738                                 break;
2739
2740                         nb_tx_to_clean = txq->nb_free - nb_tx_free_last;
2741                         nb_tx_free_last = txq->nb_free;
2742                 }
2743         }
2744
2745         return (int)pkt_cnt;
2746 }
2747
2748 int
2749 iavf_dev_tx_done_cleanup(void *txq, uint32_t free_cnt)
2750 {
2751         struct iavf_tx_queue *q = (struct iavf_tx_queue *)txq;
2752
2753         return iavf_tx_done_cleanup_full(q, free_cnt);
2754 }
2755
2756 void
2757 iavf_dev_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2758                      struct rte_eth_rxq_info *qinfo)
2759 {
2760         struct iavf_rx_queue *rxq;
2761
2762         rxq = dev->data->rx_queues[queue_id];
2763
2764         qinfo->mp = rxq->mp;
2765         qinfo->scattered_rx = dev->data->scattered_rx;
2766         qinfo->nb_desc = rxq->nb_rx_desc;
2767
2768         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2769         qinfo->conf.rx_drop_en = true;
2770         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2771 }
2772
2773 void
2774 iavf_dev_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2775                      struct rte_eth_txq_info *qinfo)
2776 {
2777         struct iavf_tx_queue *txq;
2778
2779         txq = dev->data->tx_queues[queue_id];
2780
2781         qinfo->nb_desc = txq->nb_tx_desc;
2782
2783         qinfo->conf.tx_free_thresh = txq->free_thresh;
2784         qinfo->conf.tx_rs_thresh = txq->rs_thresh;
2785         qinfo->conf.offloads = txq->offloads;
2786         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2787 }
2788
2789 /* Get the number of used descriptors of a rx queue */
2790 uint32_t
2791 iavf_dev_rxq_count(struct rte_eth_dev *dev, uint16_t queue_id)
2792 {
2793 #define IAVF_RXQ_SCAN_INTERVAL 4
2794         volatile union iavf_rx_desc *rxdp;
2795         struct iavf_rx_queue *rxq;
2796         uint16_t desc = 0;
2797
2798         rxq = dev->data->rx_queues[queue_id];
2799         rxdp = &rxq->rx_ring[rxq->rx_tail];
2800
2801         while ((desc < rxq->nb_rx_desc) &&
2802                ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
2803                  IAVF_RXD_QW1_STATUS_MASK) >> IAVF_RXD_QW1_STATUS_SHIFT) &
2804                (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)) {
2805                 /* Check the DD bit of a rx descriptor of each 4 in a group,
2806                  * to avoid checking too frequently and downgrading performance
2807                  * too much.
2808                  */
2809                 desc += IAVF_RXQ_SCAN_INTERVAL;
2810                 rxdp += IAVF_RXQ_SCAN_INTERVAL;
2811                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
2812                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
2813                                         desc - rxq->nb_rx_desc]);
2814         }
2815
2816         return desc;
2817 }
2818
2819 int
2820 iavf_dev_rx_desc_status(void *rx_queue, uint16_t offset)
2821 {
2822         struct iavf_rx_queue *rxq = rx_queue;
2823         volatile uint64_t *status;
2824         uint64_t mask;
2825         uint32_t desc;
2826
2827         if (unlikely(offset >= rxq->nb_rx_desc))
2828                 return -EINVAL;
2829
2830         if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
2831                 return RTE_ETH_RX_DESC_UNAVAIL;
2832
2833         desc = rxq->rx_tail + offset;
2834         if (desc >= rxq->nb_rx_desc)
2835                 desc -= rxq->nb_rx_desc;
2836
2837         status = &rxq->rx_ring[desc].wb.qword1.status_error_len;
2838         mask = rte_le_to_cpu_64((1ULL << IAVF_RX_DESC_STATUS_DD_SHIFT)
2839                 << IAVF_RXD_QW1_STATUS_SHIFT);
2840         if (*status & mask)
2841                 return RTE_ETH_RX_DESC_DONE;
2842
2843         return RTE_ETH_RX_DESC_AVAIL;
2844 }
2845
2846 int
2847 iavf_dev_tx_desc_status(void *tx_queue, uint16_t offset)
2848 {
2849         struct iavf_tx_queue *txq = tx_queue;
2850         volatile uint64_t *status;
2851         uint64_t mask, expect;
2852         uint32_t desc;
2853
2854         if (unlikely(offset >= txq->nb_tx_desc))
2855                 return -EINVAL;
2856
2857         desc = txq->tx_tail + offset;
2858         /* go to next desc that has the RS bit */
2859         desc = ((desc + txq->rs_thresh - 1) / txq->rs_thresh) *
2860                 txq->rs_thresh;
2861         if (desc >= txq->nb_tx_desc) {
2862                 desc -= txq->nb_tx_desc;
2863                 if (desc >= txq->nb_tx_desc)
2864                         desc -= txq->nb_tx_desc;
2865         }
2866
2867         status = &txq->tx_ring[desc].cmd_type_offset_bsz;
2868         mask = rte_le_to_cpu_64(IAVF_TXD_QW1_DTYPE_MASK);
2869         expect = rte_cpu_to_le_64(
2870                  IAVF_TX_DESC_DTYPE_DESC_DONE << IAVF_TXD_QW1_DTYPE_SHIFT);
2871         if ((*status & mask) == expect)
2872                 return RTE_ETH_TX_DESC_DONE;
2873
2874         return RTE_ETH_TX_DESC_FULL;
2875 }
2876
2877 const uint32_t *
2878 iavf_get_default_ptype_table(void)
2879 {
2880         static const uint32_t ptype_tbl[IAVF_MAX_PKT_TYPE]
2881                 __rte_cache_aligned = {
2882                 /* L2 types */
2883                 /* [0] reserved */
2884                 [1] = RTE_PTYPE_L2_ETHER,
2885                 [2] = RTE_PTYPE_L2_ETHER_TIMESYNC,
2886                 /* [3] - [5] reserved */
2887                 [6] = RTE_PTYPE_L2_ETHER_LLDP,
2888                 /* [7] - [10] reserved */
2889                 [11] = RTE_PTYPE_L2_ETHER_ARP,
2890                 /* [12] - [21] reserved */
2891
2892                 /* Non tunneled IPv4 */
2893                 [22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2894                        RTE_PTYPE_L4_FRAG,
2895                 [23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2896                        RTE_PTYPE_L4_NONFRAG,
2897                 [24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2898                        RTE_PTYPE_L4_UDP,
2899                 /* [25] reserved */
2900                 [26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2901                        RTE_PTYPE_L4_TCP,
2902                 [27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2903                        RTE_PTYPE_L4_SCTP,
2904                 [28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2905                        RTE_PTYPE_L4_ICMP,
2906
2907                 /* IPv4 --> IPv4 */
2908                 [29] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2909                        RTE_PTYPE_TUNNEL_IP |
2910                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2911                        RTE_PTYPE_INNER_L4_FRAG,
2912                 [30] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2913                        RTE_PTYPE_TUNNEL_IP |
2914                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2915                        RTE_PTYPE_INNER_L4_NONFRAG,
2916                 [31] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2917                        RTE_PTYPE_TUNNEL_IP |
2918                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2919                        RTE_PTYPE_INNER_L4_UDP,
2920                 /* [32] reserved */
2921                 [33] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2922                        RTE_PTYPE_TUNNEL_IP |
2923                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2924                        RTE_PTYPE_INNER_L4_TCP,
2925                 [34] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2926                        RTE_PTYPE_TUNNEL_IP |
2927                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2928                        RTE_PTYPE_INNER_L4_SCTP,
2929                 [35] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2930                        RTE_PTYPE_TUNNEL_IP |
2931                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2932                        RTE_PTYPE_INNER_L4_ICMP,
2933
2934                 /* IPv4 --> IPv6 */
2935                 [36] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2936                        RTE_PTYPE_TUNNEL_IP |
2937                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2938                        RTE_PTYPE_INNER_L4_FRAG,
2939                 [37] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2940                        RTE_PTYPE_TUNNEL_IP |
2941                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2942                        RTE_PTYPE_INNER_L4_NONFRAG,
2943                 [38] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2944                        RTE_PTYPE_TUNNEL_IP |
2945                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2946                        RTE_PTYPE_INNER_L4_UDP,
2947                 /* [39] reserved */
2948                 [40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2949                        RTE_PTYPE_TUNNEL_IP |
2950                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2951                        RTE_PTYPE_INNER_L4_TCP,
2952                 [41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2953                        RTE_PTYPE_TUNNEL_IP |
2954                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2955                        RTE_PTYPE_INNER_L4_SCTP,
2956                 [42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2957                        RTE_PTYPE_TUNNEL_IP |
2958                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2959                        RTE_PTYPE_INNER_L4_ICMP,
2960
2961                 /* IPv4 --> GRE/Teredo/VXLAN */
2962                 [43] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2963                        RTE_PTYPE_TUNNEL_GRENAT,
2964
2965                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv4 */
2966                 [44] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2967                        RTE_PTYPE_TUNNEL_GRENAT |
2968                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2969                        RTE_PTYPE_INNER_L4_FRAG,
2970                 [45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2971                        RTE_PTYPE_TUNNEL_GRENAT |
2972                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2973                        RTE_PTYPE_INNER_L4_NONFRAG,
2974                 [46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2975                        RTE_PTYPE_TUNNEL_GRENAT |
2976                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2977                        RTE_PTYPE_INNER_L4_UDP,
2978                 /* [47] reserved */
2979                 [48] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2980                        RTE_PTYPE_TUNNEL_GRENAT |
2981                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2982                        RTE_PTYPE_INNER_L4_TCP,
2983                 [49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2984                        RTE_PTYPE_TUNNEL_GRENAT |
2985                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2986                        RTE_PTYPE_INNER_L4_SCTP,
2987                 [50] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2988                        RTE_PTYPE_TUNNEL_GRENAT |
2989                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2990                        RTE_PTYPE_INNER_L4_ICMP,
2991
2992                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv6 */
2993                 [51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2994                        RTE_PTYPE_TUNNEL_GRENAT |
2995                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2996                        RTE_PTYPE_INNER_L4_FRAG,
2997                 [52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2998                        RTE_PTYPE_TUNNEL_GRENAT |
2999                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3000                        RTE_PTYPE_INNER_L4_NONFRAG,
3001                 [53] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3002                        RTE_PTYPE_TUNNEL_GRENAT |
3003                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3004                        RTE_PTYPE_INNER_L4_UDP,
3005                 /* [54] reserved */
3006                 [55] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3007                        RTE_PTYPE_TUNNEL_GRENAT |
3008                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3009                        RTE_PTYPE_INNER_L4_TCP,
3010                 [56] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3011                        RTE_PTYPE_TUNNEL_GRENAT |
3012                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3013                        RTE_PTYPE_INNER_L4_SCTP,
3014                 [57] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3015                        RTE_PTYPE_TUNNEL_GRENAT |
3016                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3017                        RTE_PTYPE_INNER_L4_ICMP,
3018
3019                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC */
3020                 [58] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3021                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
3022
3023                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
3024                 [59] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3025                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3026                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3027                        RTE_PTYPE_INNER_L4_FRAG,
3028                 [60] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3029                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3030                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3031                        RTE_PTYPE_INNER_L4_NONFRAG,
3032                 [61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3033                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3034                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3035                        RTE_PTYPE_INNER_L4_UDP,
3036                 /* [62] reserved */
3037                 [63] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3038                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3039                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3040                        RTE_PTYPE_INNER_L4_TCP,
3041                 [64] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3042                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3043                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3044                        RTE_PTYPE_INNER_L4_SCTP,
3045                 [65] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3046                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3047                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3048                        RTE_PTYPE_INNER_L4_ICMP,
3049
3050                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
3051                 [66] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3052                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3053                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3054                        RTE_PTYPE_INNER_L4_FRAG,
3055                 [67] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3056                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3057                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3058                        RTE_PTYPE_INNER_L4_NONFRAG,
3059                 [68] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3060                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3061                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3062                        RTE_PTYPE_INNER_L4_UDP,
3063                 /* [69] reserved */
3064                 [70] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3065                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3066                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3067                        RTE_PTYPE_INNER_L4_TCP,
3068                 [71] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3069                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3070                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3071                        RTE_PTYPE_INNER_L4_SCTP,
3072                 [72] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3073                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3074                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3075                        RTE_PTYPE_INNER_L4_ICMP,
3076                 /* [73] - [87] reserved */
3077
3078                 /* Non tunneled IPv6 */
3079                 [88] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3080                        RTE_PTYPE_L4_FRAG,
3081                 [89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3082                        RTE_PTYPE_L4_NONFRAG,
3083                 [90] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3084                        RTE_PTYPE_L4_UDP,
3085                 /* [91] reserved */
3086                 [92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3087                        RTE_PTYPE_L4_TCP,
3088                 [93] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3089                        RTE_PTYPE_L4_SCTP,
3090                 [94] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3091                        RTE_PTYPE_L4_ICMP,
3092
3093                 /* IPv6 --> IPv4 */
3094                 [95] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3095                        RTE_PTYPE_TUNNEL_IP |
3096                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3097                        RTE_PTYPE_INNER_L4_FRAG,
3098                 [96] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3099                        RTE_PTYPE_TUNNEL_IP |
3100                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3101                        RTE_PTYPE_INNER_L4_NONFRAG,
3102                 [97] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3103                        RTE_PTYPE_TUNNEL_IP |
3104                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3105                        RTE_PTYPE_INNER_L4_UDP,
3106                 /* [98] reserved */
3107                 [99] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3108                        RTE_PTYPE_TUNNEL_IP |
3109                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3110                        RTE_PTYPE_INNER_L4_TCP,
3111                 [100] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3112                         RTE_PTYPE_TUNNEL_IP |
3113                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3114                         RTE_PTYPE_INNER_L4_SCTP,
3115                 [101] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3116                         RTE_PTYPE_TUNNEL_IP |
3117                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3118                         RTE_PTYPE_INNER_L4_ICMP,
3119
3120                 /* IPv6 --> IPv6 */
3121                 [102] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3122                         RTE_PTYPE_TUNNEL_IP |
3123                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3124                         RTE_PTYPE_INNER_L4_FRAG,
3125                 [103] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3126                         RTE_PTYPE_TUNNEL_IP |
3127                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3128                         RTE_PTYPE_INNER_L4_NONFRAG,
3129                 [104] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3130                         RTE_PTYPE_TUNNEL_IP |
3131                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3132                         RTE_PTYPE_INNER_L4_UDP,
3133                 /* [105] reserved */
3134                 [106] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3135                         RTE_PTYPE_TUNNEL_IP |
3136                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3137                         RTE_PTYPE_INNER_L4_TCP,
3138                 [107] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3139                         RTE_PTYPE_TUNNEL_IP |
3140                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3141                         RTE_PTYPE_INNER_L4_SCTP,
3142                 [108] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3143                         RTE_PTYPE_TUNNEL_IP |
3144                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3145                         RTE_PTYPE_INNER_L4_ICMP,
3146
3147                 /* IPv6 --> GRE/Teredo/VXLAN */
3148                 [109] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3149                         RTE_PTYPE_TUNNEL_GRENAT,
3150
3151                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv4 */
3152                 [110] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3153                         RTE_PTYPE_TUNNEL_GRENAT |
3154                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3155                         RTE_PTYPE_INNER_L4_FRAG,
3156                 [111] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3157                         RTE_PTYPE_TUNNEL_GRENAT |
3158                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3159                         RTE_PTYPE_INNER_L4_NONFRAG,
3160                 [112] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3161                         RTE_PTYPE_TUNNEL_GRENAT |
3162                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3163                         RTE_PTYPE_INNER_L4_UDP,
3164                 /* [113] reserved */
3165                 [114] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3166                         RTE_PTYPE_TUNNEL_GRENAT |
3167                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3168                         RTE_PTYPE_INNER_L4_TCP,
3169                 [115] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3170                         RTE_PTYPE_TUNNEL_GRENAT |
3171                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3172                         RTE_PTYPE_INNER_L4_SCTP,
3173                 [116] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3174                         RTE_PTYPE_TUNNEL_GRENAT |
3175                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3176                         RTE_PTYPE_INNER_L4_ICMP,
3177
3178                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv6 */
3179                 [117] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3180                         RTE_PTYPE_TUNNEL_GRENAT |
3181                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3182                         RTE_PTYPE_INNER_L4_FRAG,
3183                 [118] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3184                         RTE_PTYPE_TUNNEL_GRENAT |
3185                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3186                         RTE_PTYPE_INNER_L4_NONFRAG,
3187                 [119] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3188                         RTE_PTYPE_TUNNEL_GRENAT |
3189                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3190                         RTE_PTYPE_INNER_L4_UDP,
3191                 /* [120] reserved */
3192                 [121] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3193                         RTE_PTYPE_TUNNEL_GRENAT |
3194                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3195                         RTE_PTYPE_INNER_L4_TCP,
3196                 [122] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3197                         RTE_PTYPE_TUNNEL_GRENAT |
3198                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3199                         RTE_PTYPE_INNER_L4_SCTP,
3200                 [123] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3201                         RTE_PTYPE_TUNNEL_GRENAT |
3202                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3203                         RTE_PTYPE_INNER_L4_ICMP,
3204
3205                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC */
3206                 [124] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3207                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
3208
3209                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
3210                 [125] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3211                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3212                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3213                         RTE_PTYPE_INNER_L4_FRAG,
3214                 [126] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3215                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3216                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3217                         RTE_PTYPE_INNER_L4_NONFRAG,
3218                 [127] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3219                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3220                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3221                         RTE_PTYPE_INNER_L4_UDP,
3222                 /* [128] reserved */
3223                 [129] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3224                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3225                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3226                         RTE_PTYPE_INNER_L4_TCP,
3227                 [130] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3228                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3229                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3230                         RTE_PTYPE_INNER_L4_SCTP,
3231                 [131] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3232                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3233                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3234                         RTE_PTYPE_INNER_L4_ICMP,
3235
3236                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
3237                 [132] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3238                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3239                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3240                         RTE_PTYPE_INNER_L4_FRAG,
3241                 [133] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3242                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3243                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3244                         RTE_PTYPE_INNER_L4_NONFRAG,
3245                 [134] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3246                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3247                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3248                         RTE_PTYPE_INNER_L4_UDP,
3249                 /* [135] reserved */
3250                 [136] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3251                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3252                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3253                         RTE_PTYPE_INNER_L4_TCP,
3254                 [137] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3255                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3256                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3257                         RTE_PTYPE_INNER_L4_SCTP,
3258                 [138] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3259                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3260                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3261                         RTE_PTYPE_INNER_L4_ICMP,
3262                 /* [139] - [299] reserved */
3263
3264                 /* PPPoE */
3265                 [300] = RTE_PTYPE_L2_ETHER_PPPOE,
3266                 [301] = RTE_PTYPE_L2_ETHER_PPPOE,
3267
3268                 /* PPPoE --> IPv4 */
3269                 [302] = RTE_PTYPE_L2_ETHER_PPPOE |
3270                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3271                         RTE_PTYPE_L4_FRAG,
3272                 [303] = RTE_PTYPE_L2_ETHER_PPPOE |
3273                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3274                         RTE_PTYPE_L4_NONFRAG,
3275                 [304] = RTE_PTYPE_L2_ETHER_PPPOE |
3276                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3277                         RTE_PTYPE_L4_UDP,
3278                 [305] = RTE_PTYPE_L2_ETHER_PPPOE |
3279                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3280                         RTE_PTYPE_L4_TCP,
3281                 [306] = RTE_PTYPE_L2_ETHER_PPPOE |
3282                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3283                         RTE_PTYPE_L4_SCTP,
3284                 [307] = RTE_PTYPE_L2_ETHER_PPPOE |
3285                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3286                         RTE_PTYPE_L4_ICMP,
3287
3288                 /* PPPoE --> IPv6 */
3289                 [308] = RTE_PTYPE_L2_ETHER_PPPOE |
3290                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3291                         RTE_PTYPE_L4_FRAG,
3292                 [309] = RTE_PTYPE_L2_ETHER_PPPOE |
3293                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3294                         RTE_PTYPE_L4_NONFRAG,
3295                 [310] = RTE_PTYPE_L2_ETHER_PPPOE |
3296                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3297                         RTE_PTYPE_L4_UDP,
3298                 [311] = RTE_PTYPE_L2_ETHER_PPPOE |
3299                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3300                         RTE_PTYPE_L4_TCP,
3301                 [312] = RTE_PTYPE_L2_ETHER_PPPOE |
3302                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3303                         RTE_PTYPE_L4_SCTP,
3304                 [313] = RTE_PTYPE_L2_ETHER_PPPOE |
3305                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3306                         RTE_PTYPE_L4_ICMP,
3307                 /* [314] - [324] reserved */
3308
3309                 /* IPv4/IPv6 --> GTPC/GTPU */
3310                 [325] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3311                         RTE_PTYPE_TUNNEL_GTPC,
3312                 [326] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3313                         RTE_PTYPE_TUNNEL_GTPC,
3314                 [327] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3315                         RTE_PTYPE_TUNNEL_GTPC,
3316                 [328] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3317                         RTE_PTYPE_TUNNEL_GTPC,
3318                 [329] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3319                         RTE_PTYPE_TUNNEL_GTPU,
3320                 [330] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3321                         RTE_PTYPE_TUNNEL_GTPU,
3322
3323                 /* IPv4 --> GTPU --> IPv4 */
3324                 [331] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3325                         RTE_PTYPE_TUNNEL_GTPU |
3326                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3327                         RTE_PTYPE_INNER_L4_FRAG,
3328                 [332] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3329                         RTE_PTYPE_TUNNEL_GTPU |
3330                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3331                         RTE_PTYPE_INNER_L4_NONFRAG,
3332                 [333] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3333                         RTE_PTYPE_TUNNEL_GTPU |
3334                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3335                         RTE_PTYPE_INNER_L4_UDP,
3336                 [334] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3337                         RTE_PTYPE_TUNNEL_GTPU |
3338                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3339                         RTE_PTYPE_INNER_L4_TCP,
3340                 [335] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3341                         RTE_PTYPE_TUNNEL_GTPU |
3342                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3343                         RTE_PTYPE_INNER_L4_ICMP,
3344
3345                 /* IPv6 --> GTPU --> IPv4 */
3346                 [336] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3347                         RTE_PTYPE_TUNNEL_GTPU |
3348                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3349                         RTE_PTYPE_INNER_L4_FRAG,
3350                 [337] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3351                         RTE_PTYPE_TUNNEL_GTPU |
3352                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3353                         RTE_PTYPE_INNER_L4_NONFRAG,
3354                 [338] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3355                         RTE_PTYPE_TUNNEL_GTPU |
3356                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3357                         RTE_PTYPE_INNER_L4_UDP,
3358                 [339] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3359                         RTE_PTYPE_TUNNEL_GTPU |
3360                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3361                         RTE_PTYPE_INNER_L4_TCP,
3362                 [340] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3363                         RTE_PTYPE_TUNNEL_GTPU |
3364                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3365                         RTE_PTYPE_INNER_L4_ICMP,
3366
3367                 /* IPv4 --> GTPU --> IPv6 */
3368                 [341] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3369                         RTE_PTYPE_TUNNEL_GTPU |
3370                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3371                         RTE_PTYPE_INNER_L4_FRAG,
3372                 [342] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3373                         RTE_PTYPE_TUNNEL_GTPU |
3374                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3375                         RTE_PTYPE_INNER_L4_NONFRAG,
3376                 [343] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3377                         RTE_PTYPE_TUNNEL_GTPU |
3378                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3379                         RTE_PTYPE_INNER_L4_UDP,
3380                 [344] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3381                         RTE_PTYPE_TUNNEL_GTPU |
3382                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3383                         RTE_PTYPE_INNER_L4_TCP,
3384                 [345] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3385                         RTE_PTYPE_TUNNEL_GTPU |
3386                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3387                         RTE_PTYPE_INNER_L4_ICMP,
3388
3389                 /* IPv6 --> GTPU --> IPv6 */
3390                 [346] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3391                         RTE_PTYPE_TUNNEL_GTPU |
3392                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3393                         RTE_PTYPE_INNER_L4_FRAG,
3394                 [347] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3395                         RTE_PTYPE_TUNNEL_GTPU |
3396                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3397                         RTE_PTYPE_INNER_L4_NONFRAG,
3398                 [348] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3399                         RTE_PTYPE_TUNNEL_GTPU |
3400                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3401                         RTE_PTYPE_INNER_L4_UDP,
3402                 [349] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3403                         RTE_PTYPE_TUNNEL_GTPU |
3404                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3405                         RTE_PTYPE_INNER_L4_TCP,
3406                 [350] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3407                         RTE_PTYPE_TUNNEL_GTPU |
3408                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3409                         RTE_PTYPE_INNER_L4_ICMP,
3410
3411                 /* IPv4 --> UDP ECPRI */
3412                 [372] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3413                         RTE_PTYPE_L4_UDP,
3414                 [373] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3415                         RTE_PTYPE_L4_UDP,
3416                 [374] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3417                         RTE_PTYPE_L4_UDP,
3418                 [375] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3419                         RTE_PTYPE_L4_UDP,
3420                 [376] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3421                         RTE_PTYPE_L4_UDP,
3422                 [377] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3423                         RTE_PTYPE_L4_UDP,
3424                 [378] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3425                         RTE_PTYPE_L4_UDP,
3426                 [379] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3427                         RTE_PTYPE_L4_UDP,
3428                 [380] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3429                         RTE_PTYPE_L4_UDP,
3430                 [381] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3431                         RTE_PTYPE_L4_UDP,
3432
3433                 /* IPV6 --> UDP ECPRI */
3434                 [382] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3435                         RTE_PTYPE_L4_UDP,
3436                 [383] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3437                         RTE_PTYPE_L4_UDP,
3438                 [384] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3439                         RTE_PTYPE_L4_UDP,
3440                 [385] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3441                         RTE_PTYPE_L4_UDP,
3442                 [386] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3443                         RTE_PTYPE_L4_UDP,
3444                 [387] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3445                         RTE_PTYPE_L4_UDP,
3446                 [388] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3447                         RTE_PTYPE_L4_UDP,
3448                 [389] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3449                         RTE_PTYPE_L4_UDP,
3450                 [390] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3451                         RTE_PTYPE_L4_UDP,
3452                 [391] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3453                         RTE_PTYPE_L4_UDP,
3454                 /* All others reserved */
3455         };
3456
3457         return ptype_tbl;
3458 }