drivers/net/iavf/iavf_rxtx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2017 Intel Corporation
   3  */
   4
   5 #include <stdio.h>
   6 #include <stdlib.h>
   7 #include <string.h>
   8 #include <errno.h>
   9 #include <stdint.h>
  10 #include <stdarg.h>
  11 #include <unistd.h>
  12 #include <inttypes.h>
  13 #include <sys/queue.h>
  14
  15 #include <rte_string_fns.h>
  16 #include <rte_memzone.h>
  17 #include <rte_mbuf.h>
  18 #include <rte_malloc.h>
  19 #include <rte_ether.h>
  20 #include <ethdev_driver.h>
  21 #include <rte_tcp.h>
  22 #include <rte_sctp.h>
  23 #include <rte_udp.h>
  24 #include <rte_ip.h>
  25 #include <rte_net.h>
  26 #include <rte_vect.h>
  27
  28 #include "iavf.h"
  29 #include "iavf_rxtx.h"
  30 #include "rte_pmd_iavf.h"
  31
  32 /* Offset of mbuf dynamic field for protocol extraction's metadata */
  33 int rte_pmd_ifd_dynfield_proto_xtr_metadata_offs = -1;
  34
  35 /* Mask of mbuf dynamic flags for protocol extraction's type */
  36 uint64_t rte_pmd_ifd_dynflag_proto_xtr_vlan_mask;
  37 uint64_t rte_pmd_ifd_dynflag_proto_xtr_ipv4_mask;
  38 uint64_t rte_pmd_ifd_dynflag_proto_xtr_ipv6_mask;
  39 uint64_t rte_pmd_ifd_dynflag_proto_xtr_ipv6_flow_mask;
  40 uint64_t rte_pmd_ifd_dynflag_proto_xtr_tcp_mask;
  41 uint64_t rte_pmd_ifd_dynflag_proto_xtr_ip_offset_mask;
  42
  43 uint8_t
  44 iavf_proto_xtr_type_to_rxdid(uint8_t flex_type)
  45 {
  46         static uint8_t rxdid_map[] = {
  47                 [IAVF_PROTO_XTR_NONE]      = IAVF_RXDID_COMMS_OVS_1,
  48                 [IAVF_PROTO_XTR_VLAN]      = IAVF_RXDID_COMMS_AUX_VLAN,
  49                 [IAVF_PROTO_XTR_IPV4]      = IAVF_RXDID_COMMS_AUX_IPV4,
  50                 [IAVF_PROTO_XTR_IPV6]      = IAVF_RXDID_COMMS_AUX_IPV6,
  51                 [IAVF_PROTO_XTR_IPV6_FLOW] = IAVF_RXDID_COMMS_AUX_IPV6_FLOW,
  52                 [IAVF_PROTO_XTR_TCP]       = IAVF_RXDID_COMMS_AUX_TCP,
  53                 [IAVF_PROTO_XTR_IP_OFFSET] = IAVF_RXDID_COMMS_AUX_IP_OFFSET,
  54         };
  55
  56         return flex_type < RTE_DIM(rxdid_map) ?
  57                                 rxdid_map[flex_type] : IAVF_RXDID_COMMS_OVS_1;
  58 }
  59
  60 static int
  61 iavf_monitor_callback(const uint64_t value,
  62                 const uint64_t arg[RTE_POWER_MONITOR_OPAQUE_SZ] __rte_unused)
  63 {
  64         const uint64_t m = rte_cpu_to_le_64(1 << IAVF_RX_DESC_STATUS_DD_SHIFT);
  65         /*
  66          * we expect the DD bit to be set to 1 if this descriptor was already
  67          * written to.
  68          */
  69         return (value & m) == m ? -1 : 0;
  70 }
  71
  72 int
  73 iavf_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc)
  74 {
  75         struct iavf_rx_queue *rxq = rx_queue;
  76         volatile union iavf_rx_desc *rxdp;
  77         uint16_t desc;
  78
  79         desc = rxq->rx_tail;
  80         rxdp = &rxq->rx_ring[desc];
  81         /* watch for changes in status bit */
  82         pmc->addr = &rxdp->wb.qword1.status_error_len;
  83
  84         /* comparison callback */
  85         pmc->fn = iavf_monitor_callback;
  86
  87         /* registers are 64-bit */
  88         pmc->size = sizeof(uint64_t);
  89
  90         return 0;
  91 }
  92
  93 static inline int
  94 check_rx_thresh(uint16_t nb_desc, uint16_t thresh)
  95 {
  96         /* The following constraints must be satisfied:
  97          *   thresh < rxq->nb_rx_desc
  98          */
  99         if (thresh >= nb_desc) {
 100                 PMD_INIT_LOG(ERR, "rx_free_thresh (%u) must be less than %u",
 101                              thresh, nb_desc);
 102                 return -EINVAL;
 103         }
 104         return 0;
 105 }
 106
 107 static inline int
 108 check_tx_thresh(uint16_t nb_desc, uint16_t tx_rs_thresh,
 109                 uint16_t tx_free_thresh)
 110 {
 111         /* TX descriptors will have their RS bit set after tx_rs_thresh
 112          * descriptors have been used. The TX descriptor ring will be cleaned
 113          * after tx_free_thresh descriptors are used or if the number of
 114          * descriptors required to transmit a packet is greater than the
 115          * number of free TX descriptors.
 116          *
 117          * The following constraints must be satisfied:
 118          *  - tx_rs_thresh must be less than the size of the ring minus 2.
 119          *  - tx_free_thresh must be less than the size of the ring minus 3.
 120          *  - tx_rs_thresh must be less than or equal to tx_free_thresh.
 121          *  - tx_rs_thresh must be a divisor of the ring size.
 122          *
 123          * One descriptor in the TX ring is used as a sentinel to avoid a H/W
 124          * race condition, hence the maximum threshold constraints. When set
 125          * to zero use default values.
 126          */
 127         if (tx_rs_thresh >= (nb_desc - 2)) {
 128                 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be less than the "
 129                              "number of TX descriptors (%u) minus 2",
 130                              tx_rs_thresh, nb_desc);
 131                 return -EINVAL;
 132         }
 133         if (tx_free_thresh >= (nb_desc - 3)) {
 134                 PMD_INIT_LOG(ERR, "tx_free_thresh (%u) must be less than the "
 135                              "number of TX descriptors (%u) minus 3.",
 136                              tx_free_thresh, nb_desc);
 137                 return -EINVAL;
 138         }
 139         if (tx_rs_thresh > tx_free_thresh) {
 140                 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be less than or "
 141                              "equal to tx_free_thresh (%u).",
 142                              tx_rs_thresh, tx_free_thresh);
 143                 return -EINVAL;
 144         }
 145         if ((nb_desc % tx_rs_thresh) != 0) {
 146                 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be a divisor of the "
 147                              "number of TX descriptors (%u).",
 148                              tx_rs_thresh, nb_desc);
 149                 return -EINVAL;
 150         }
 151
 152         return 0;
 153 }
 154
 155 static inline bool
 156 check_rx_vec_allow(struct iavf_rx_queue *rxq)
 157 {
 158         if (rxq->rx_free_thresh >= IAVF_VPMD_RX_MAX_BURST &&
 159             rxq->nb_rx_desc % rxq->rx_free_thresh == 0) {
 160                 PMD_INIT_LOG(DEBUG, "Vector Rx can be enabled on this rxq.");
 161                 return true;
 162         }
 163
 164         PMD_INIT_LOG(DEBUG, "Vector Rx cannot be enabled on this rxq.");
 165         return false;
 166 }
 167
 168 static inline bool
 169 check_tx_vec_allow(struct iavf_tx_queue *txq)
 170 {
 171         if (!(txq->offloads & IAVF_TX_NO_VECTOR_FLAGS) &&
 172             txq->rs_thresh >= IAVF_VPMD_TX_MAX_BURST &&
 173             txq->rs_thresh <= IAVF_VPMD_TX_MAX_FREE_BUF) {
 174                 PMD_INIT_LOG(DEBUG, "Vector tx can be enabled on this txq.");
 175                 return true;
 176         }
 177         PMD_INIT_LOG(DEBUG, "Vector Tx cannot be enabled on this txq.");
 178         return false;
 179 }
 180
 181 static inline bool
 182 check_rx_bulk_allow(struct iavf_rx_queue *rxq)
 183 {
 184         int ret = true;
 185
 186         if (!(rxq->rx_free_thresh >= IAVF_RX_MAX_BURST)) {
 187                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 188                              "rxq->rx_free_thresh=%d, "
 189                              "IAVF_RX_MAX_BURST=%d",
 190                              rxq->rx_free_thresh, IAVF_RX_MAX_BURST);
 191                 ret = false;
 192         } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
 193                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 194                              "rxq->nb_rx_desc=%d, "
 195                              "rxq->rx_free_thresh=%d",
 196                              rxq->nb_rx_desc, rxq->rx_free_thresh);
 197                 ret = false;
 198         }
 199         return ret;
 200 }
 201
 202 static inline void
 203 reset_rx_queue(struct iavf_rx_queue *rxq)
 204 {
 205         uint16_t len;
 206         uint32_t i;
 207
 208         if (!rxq)
 209                 return;
 210
 211         len = rxq->nb_rx_desc + IAVF_RX_MAX_BURST;
 212
 213         for (i = 0; i < len * sizeof(union iavf_rx_desc); i++)
 214                 ((volatile char *)rxq->rx_ring)[i] = 0;
 215
 216         memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
 217
 218         for (i = 0; i < IAVF_RX_MAX_BURST; i++)
 219                 rxq->sw_ring[rxq->nb_rx_desc + i] = &rxq->fake_mbuf;
 220
 221         /* for rx bulk */
 222         rxq->rx_nb_avail = 0;
 223         rxq->rx_next_avail = 0;
 224         rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
 225
 226         rxq->rx_tail = 0;
 227         rxq->nb_rx_hold = 0;
 228
 229         if (rxq->pkt_first_seg != NULL)
 230                 rte_pktmbuf_free(rxq->pkt_first_seg);
 231
 232         rxq->pkt_first_seg = NULL;
 233         rxq->pkt_last_seg = NULL;
 234         rxq->rxrearm_nb = 0;
 235         rxq->rxrearm_start = 0;
 236 }
 237
 238 static inline void
 239 reset_tx_queue(struct iavf_tx_queue *txq)
 240 {
 241         struct iavf_tx_entry *txe;
 242         uint32_t i, size;
 243         uint16_t prev;
 244
 245         if (!txq) {
 246                 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
 247                 return;
 248         }
 249
 250         txe = txq->sw_ring;
 251         size = sizeof(struct iavf_tx_desc) * txq->nb_tx_desc;
 252         for (i = 0; i < size; i++)
 253                 ((volatile char *)txq->tx_ring)[i] = 0;
 254
 255         prev = (uint16_t)(txq->nb_tx_desc - 1);
 256         for (i = 0; i < txq->nb_tx_desc; i++) {
 257                 txq->tx_ring[i].cmd_type_offset_bsz =
 258                         rte_cpu_to_le_64(IAVF_TX_DESC_DTYPE_DESC_DONE);
 259                 txe[i].mbuf =  NULL;
 260                 txe[i].last_id = i;
 261                 txe[prev].next_id = i;
 262                 prev = i;
 263         }
 264
 265         txq->tx_tail = 0;
 266         txq->nb_used = 0;
 267
 268         txq->last_desc_cleaned = txq->nb_tx_desc - 1;
 269         txq->nb_free = txq->nb_tx_desc - 1;
 270
 271         txq->next_dd = txq->rs_thresh - 1;
 272         txq->next_rs = txq->rs_thresh - 1;
 273 }
 274
 275 static int
 276 alloc_rxq_mbufs(struct iavf_rx_queue *rxq)
 277 {
 278         volatile union iavf_rx_desc *rxd;
 279         struct rte_mbuf *mbuf = NULL;
 280         uint64_t dma_addr;
 281         uint16_t i, j;
 282
 283         for (i = 0; i < rxq->nb_rx_desc; i++) {
 284                 mbuf = rte_mbuf_raw_alloc(rxq->mp);
 285                 if (unlikely(!mbuf)) {
 286                         for (j = 0; j < i; j++) {
 287                                 rte_pktmbuf_free_seg(rxq->sw_ring[j]);
 288                                 rxq->sw_ring[j] = NULL;
 289                         }
 290                         PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
 291                         return -ENOMEM;
 292                 }
 293
 294                 rte_mbuf_refcnt_set(mbuf, 1);
 295                 mbuf->next = NULL;
 296                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
 297                 mbuf->nb_segs = 1;
 298                 mbuf->port = rxq->port_id;
 299
 300                 dma_addr =
 301                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
 302
 303                 rxd = &rxq->rx_ring[i];
 304                 rxd->read.pkt_addr = dma_addr;
 305                 rxd->read.hdr_addr = 0;
 306 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
 307                 rxd->read.rsvd1 = 0;
 308                 rxd->read.rsvd2 = 0;
 309 #endif
 310
 311                 rxq->sw_ring[i] = mbuf;
 312         }
 313
 314         return 0;
 315 }
 316
 317 static inline void
 318 release_rxq_mbufs(struct iavf_rx_queue *rxq)
 319 {
 320         uint16_t i;
 321
 322         if (!rxq->sw_ring)
 323                 return;
 324
 325         for (i = 0; i < rxq->nb_rx_desc; i++) {
 326                 if (rxq->sw_ring[i]) {
 327                         rte_pktmbuf_free_seg(rxq->sw_ring[i]);
 328                         rxq->sw_ring[i] = NULL;
 329                 }
 330         }
 331
 332         /* for rx bulk */
 333         if (rxq->rx_nb_avail == 0)
 334                 return;
 335         for (i = 0; i < rxq->rx_nb_avail; i++) {
 336                 struct rte_mbuf *mbuf;
 337
 338                 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
 339                 rte_pktmbuf_free_seg(mbuf);
 340         }
 341         rxq->rx_nb_avail = 0;
 342 }
 343
 344 static inline void
 345 release_txq_mbufs(struct iavf_tx_queue *txq)
 346 {
 347         uint16_t i;
 348
 349         if (!txq || !txq->sw_ring) {
 350                 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
 351                 return;
 352         }
 353
 354         for (i = 0; i < txq->nb_tx_desc; i++) {
 355                 if (txq->sw_ring[i].mbuf) {
 356                         rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
 357                         txq->sw_ring[i].mbuf = NULL;
 358                 }
 359         }
 360 }
 361
 362 static const struct iavf_rxq_ops def_rxq_ops = {
 363         .release_mbufs = release_rxq_mbufs,
 364 };
 365
 366 static const struct iavf_txq_ops def_txq_ops = {
 367         .release_mbufs = release_txq_mbufs,
 368 };
 369
 370 static inline void
 371 iavf_rxd_to_pkt_fields_by_comms_ovs(__rte_unused struct iavf_rx_queue *rxq,
 372                                     struct rte_mbuf *mb,
 373                                     volatile union iavf_rx_flex_desc *rxdp)
 374 {
 375         volatile struct iavf_32b_rx_flex_desc_comms_ovs *desc =
 376                         (volatile struct iavf_32b_rx_flex_desc_comms_ovs *)rxdp;
 377 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
 378         uint16_t stat_err;
 379 #endif
 380
 381         if (desc->flow_id != 0xFFFFFFFF) {
 382                 mb->ol_flags |= RTE_MBUF_F_RX_FDIR | RTE_MBUF_F_RX_FDIR_ID;
 383                 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
 384         }
 385
 386 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
 387         stat_err = rte_le_to_cpu_16(desc->status_error0);
 388         if (likely(stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
 389                 mb->ol_flags |= RTE_MBUF_F_RX_RSS_HASH;
 390                 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
 391         }
 392 #endif
 393 }
 394
 395 static inline void
 396 iavf_rxd_to_pkt_fields_by_comms_aux_v1(struct iavf_rx_queue *rxq,
 397                                        struct rte_mbuf *mb,
 398                                        volatile union iavf_rx_flex_desc *rxdp)
 399 {
 400         volatile struct iavf_32b_rx_flex_desc_comms *desc =
 401                         (volatile struct iavf_32b_rx_flex_desc_comms *)rxdp;
 402         uint16_t stat_err;
 403
 404         stat_err = rte_le_to_cpu_16(desc->status_error0);
 405         if (likely(stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
 406                 mb->ol_flags |= RTE_MBUF_F_RX_RSS_HASH;
 407                 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
 408         }
 409
 410 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
 411         if (desc->flow_id != 0xFFFFFFFF) {
 412                 mb->ol_flags |= RTE_MBUF_F_RX_FDIR | RTE_MBUF_F_RX_FDIR_ID;
 413                 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
 414         }
 415
 416         if (rxq->xtr_ol_flag) {
 417                 uint32_t metadata = 0;
 418
 419                 stat_err = rte_le_to_cpu_16(desc->status_error1);
 420
 421                 if (stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS1_XTRMD4_VALID_S))
 422                         metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux0);
 423
 424                 if (stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS1_XTRMD5_VALID_S))
 425                         metadata |=
 426                                 rte_le_to_cpu_16(desc->flex_ts.flex.aux1) << 16;
 427
 428                 if (metadata) {
 429                         mb->ol_flags |= rxq->xtr_ol_flag;
 430
 431                         *RTE_PMD_IFD_DYNF_PROTO_XTR_METADATA(mb) = metadata;
 432                 }
 433         }
 434 #endif
 435 }
 436
 437 static inline void
 438 iavf_rxd_to_pkt_fields_by_comms_aux_v2(struct iavf_rx_queue *rxq,
 439                                        struct rte_mbuf *mb,
 440                                        volatile union iavf_rx_flex_desc *rxdp)
 441 {
 442         volatile struct iavf_32b_rx_flex_desc_comms *desc =
 443                         (volatile struct iavf_32b_rx_flex_desc_comms *)rxdp;
 444         uint16_t stat_err;
 445
 446         stat_err = rte_le_to_cpu_16(desc->status_error0);
 447         if (likely(stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
 448                 mb->ol_flags |= RTE_MBUF_F_RX_RSS_HASH;
 449                 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
 450         }
 451
 452 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
 453         if (desc->flow_id != 0xFFFFFFFF) {
 454                 mb->ol_flags |= RTE_MBUF_F_RX_FDIR | RTE_MBUF_F_RX_FDIR_ID;
 455                 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
 456         }
 457
 458         if (rxq->xtr_ol_flag) {
 459                 uint32_t metadata = 0;
 460
 461                 if (desc->flex_ts.flex.aux0 != 0xFFFF)
 462                         metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux0);
 463                 else if (desc->flex_ts.flex.aux1 != 0xFFFF)
 464                         metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux1);
 465
 466                 if (metadata) {
 467                         mb->ol_flags |= rxq->xtr_ol_flag;
 468
 469                         *RTE_PMD_IFD_DYNF_PROTO_XTR_METADATA(mb) = metadata;
 470                 }
 471         }
 472 #endif
 473 }
 474
 475 static void
 476 iavf_select_rxd_to_pkt_fields_handler(struct iavf_rx_queue *rxq, uint32_t rxdid)
 477 {
 478         switch (rxdid) {
 479         case IAVF_RXDID_COMMS_AUX_VLAN:
 480                 rxq->xtr_ol_flag = rte_pmd_ifd_dynflag_proto_xtr_vlan_mask;
 481                 rxq->rxd_to_pkt_fields =
 482                         iavf_rxd_to_pkt_fields_by_comms_aux_v1;
 483                 break;
 484         case IAVF_RXDID_COMMS_AUX_IPV4:
 485                 rxq->xtr_ol_flag = rte_pmd_ifd_dynflag_proto_xtr_ipv4_mask;
 486                 rxq->rxd_to_pkt_fields =
 487                         iavf_rxd_to_pkt_fields_by_comms_aux_v1;
 488                 break;
 489         case IAVF_RXDID_COMMS_AUX_IPV6:
 490                 rxq->xtr_ol_flag = rte_pmd_ifd_dynflag_proto_xtr_ipv6_mask;
 491                 rxq->rxd_to_pkt_fields =
 492                         iavf_rxd_to_pkt_fields_by_comms_aux_v1;
 493                 break;
 494         case IAVF_RXDID_COMMS_AUX_IPV6_FLOW:
 495                 rxq->xtr_ol_flag =
 496                         rte_pmd_ifd_dynflag_proto_xtr_ipv6_flow_mask;
 497                 rxq->rxd_to_pkt_fields =
 498                         iavf_rxd_to_pkt_fields_by_comms_aux_v1;
 499                 break;
 500         case IAVF_RXDID_COMMS_AUX_TCP:
 501                 rxq->xtr_ol_flag = rte_pmd_ifd_dynflag_proto_xtr_tcp_mask;
 502                 rxq->rxd_to_pkt_fields =
 503                         iavf_rxd_to_pkt_fields_by_comms_aux_v1;
 504                 break;
 505         case IAVF_RXDID_COMMS_AUX_IP_OFFSET:
 506                 rxq->xtr_ol_flag =
 507                         rte_pmd_ifd_dynflag_proto_xtr_ip_offset_mask;
 508                 rxq->rxd_to_pkt_fields =
 509                         iavf_rxd_to_pkt_fields_by_comms_aux_v2;
 510                 break;
 511         case IAVF_RXDID_COMMS_OVS_1:
 512                 rxq->rxd_to_pkt_fields = iavf_rxd_to_pkt_fields_by_comms_ovs;
 513                 break;
 514         default:
 515                 /* update this according to the RXDID for FLEX_DESC_NONE */
 516                 rxq->rxd_to_pkt_fields = iavf_rxd_to_pkt_fields_by_comms_ovs;
 517                 break;
 518         }
 519
 520         if (!rte_pmd_ifd_dynf_proto_xtr_metadata_avail())
 521                 rxq->xtr_ol_flag = 0;
 522 }
 523
 524 int
 525 iavf_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 526                        uint16_t nb_desc, unsigned int socket_id,
 527                        const struct rte_eth_rxconf *rx_conf,
 528                        struct rte_mempool *mp)
 529 {
 530         struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 531         struct iavf_adapter *ad =
 532                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 533         struct iavf_info *vf =
 534                 IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 535         struct iavf_vsi *vsi = &vf->vsi;
 536         struct iavf_rx_queue *rxq;
 537         const struct rte_memzone *mz;
 538         uint32_t ring_size;
 539         uint8_t proto_xtr;
 540         uint16_t len;
 541         uint16_t rx_free_thresh;
 542         uint64_t offloads;
 543
 544         PMD_INIT_FUNC_TRACE();
 545
 546         offloads = rx_conf->offloads | dev->data->dev_conf.rxmode.offloads;
 547
 548         if (nb_desc % IAVF_ALIGN_RING_DESC != 0 ||
 549             nb_desc > IAVF_MAX_RING_DESC ||
 550             nb_desc < IAVF_MIN_RING_DESC) {
 551                 PMD_INIT_LOG(ERR, "Number (%u) of receive descriptors is "
 552                              "invalid", nb_desc);
 553                 return -EINVAL;
 554         }
 555
 556         /* Check free threshold */
 557         rx_free_thresh = (rx_conf->rx_free_thresh == 0) ?
 558                          IAVF_DEFAULT_RX_FREE_THRESH :
 559                          rx_conf->rx_free_thresh;
 560         if (check_rx_thresh(nb_desc, rx_free_thresh) != 0)
 561                 return -EINVAL;
 562
 563         /* Free memory if needed */
 564         if (dev->data->rx_queues[queue_idx]) {
 565                 iavf_dev_rx_queue_release(dev, queue_idx);
 566                 dev->data->rx_queues[queue_idx] = NULL;
 567         }
 568
 569         /* Allocate the rx queue data structure */
 570         rxq = rte_zmalloc_socket("iavf rxq",
 571                                  sizeof(struct iavf_rx_queue),
 572                                  RTE_CACHE_LINE_SIZE,
 573                                  socket_id);
 574         if (!rxq) {
 575                 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
 576                              "rx queue data structure");
 577                 return -ENOMEM;
 578         }
 579
 580         if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC) {
 581                 proto_xtr = vf->proto_xtr ? vf->proto_xtr[queue_idx] :
 582                                 IAVF_PROTO_XTR_NONE;
 583                 rxq->rxdid = iavf_proto_xtr_type_to_rxdid(proto_xtr);
 584                 rxq->proto_xtr = proto_xtr;
 585         } else {
 586                 rxq->rxdid = IAVF_RXDID_LEGACY_1;
 587                 rxq->proto_xtr = IAVF_PROTO_XTR_NONE;
 588         }
 589
 590         if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_VLAN_V2) {
 591                 struct virtchnl_vlan_supported_caps *stripping_support =
 592                                 &vf->vlan_v2_caps.offloads.stripping_support;
 593                 uint32_t stripping_cap;
 594
 595                 if (stripping_support->outer)
 596                         stripping_cap = stripping_support->outer;
 597                 else
 598                         stripping_cap = stripping_support->inner;
 599
 600                 if (stripping_cap & VIRTCHNL_VLAN_TAG_LOCATION_L2TAG1)
 601                         rxq->rx_flags = IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG1;
 602                 else if (stripping_cap & VIRTCHNL_VLAN_TAG_LOCATION_L2TAG2_2)
 603                         rxq->rx_flags = IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG2_2;
 604         } else {
 605                 rxq->rx_flags = IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG1;
 606         }
 607
 608         iavf_select_rxd_to_pkt_fields_handler(rxq, rxq->rxdid);
 609
 610         rxq->mp = mp;
 611         rxq->nb_rx_desc = nb_desc;
 612         rxq->rx_free_thresh = rx_free_thresh;
 613         rxq->queue_id = queue_idx;
 614         rxq->port_id = dev->data->port_id;
 615         rxq->rx_deferred_start = rx_conf->rx_deferred_start;
 616         rxq->rx_hdr_len = 0;
 617         rxq->vsi = vsi;
 618         rxq->offloads = offloads;
 619
 620         if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_KEEP_CRC)
 621                 rxq->crc_len = RTE_ETHER_CRC_LEN;
 622         else
 623                 rxq->crc_len = 0;
 624
 625         len = rte_pktmbuf_data_room_size(rxq->mp) - RTE_PKTMBUF_HEADROOM;
 626         rxq->rx_buf_len = RTE_ALIGN_FLOOR(len, (1 << IAVF_RXQ_CTX_DBUFF_SHIFT));
 627
 628         /* Allocate the software ring. */
 629         len = nb_desc + IAVF_RX_MAX_BURST;
 630         rxq->sw_ring =
 631                 rte_zmalloc_socket("iavf rx sw ring",
 632                                    sizeof(struct rte_mbuf *) * len,
 633                                    RTE_CACHE_LINE_SIZE,
 634                                    socket_id);
 635         if (!rxq->sw_ring) {
 636                 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW ring");
 637                 rte_free(rxq);
 638                 return -ENOMEM;
 639         }
 640
 641         /* Allocate the maximun number of RX ring hardware descriptor with
 642          * a liitle more to support bulk allocate.
 643          */
 644         len = IAVF_MAX_RING_DESC + IAVF_RX_MAX_BURST;
 645         ring_size = RTE_ALIGN(len * sizeof(union iavf_rx_desc),
 646                               IAVF_DMA_MEM_ALIGN);
 647         mz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
 648                                       ring_size, IAVF_RING_BASE_ALIGN,
 649                                       socket_id);
 650         if (!mz) {
 651                 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for RX");
 652                 rte_free(rxq->sw_ring);
 653                 rte_free(rxq);
 654                 return -ENOMEM;
 655         }
 656         /* Zero all the descriptors in the ring. */
 657         memset(mz->addr, 0, ring_size);
 658         rxq->rx_ring_phys_addr = mz->iova;
 659         rxq->rx_ring = (union iavf_rx_desc *)mz->addr;
 660
 661         rxq->mz = mz;
 662         reset_rx_queue(rxq);
 663         rxq->q_set = true;
 664         dev->data->rx_queues[queue_idx] = rxq;
 665         rxq->qrx_tail = hw->hw_addr + IAVF_QRX_TAIL1(rxq->queue_id);
 666         rxq->ops = &def_rxq_ops;
 667
 668         if (check_rx_bulk_allow(rxq) == true) {
 669                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
 670                              "satisfied. Rx Burst Bulk Alloc function will be "
 671                              "used on port=%d, queue=%d.",
 672                              rxq->port_id, rxq->queue_id);
 673         } else {
 674                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
 675                              "not satisfied, Scattered Rx is requested "
 676                              "on port=%d, queue=%d.",
 677                              rxq->port_id, rxq->queue_id);
 678                 ad->rx_bulk_alloc_allowed = false;
 679         }
 680
 681         if (check_rx_vec_allow(rxq) == false)
 682                 ad->rx_vec_allowed = false;
 683
 684         return 0;
 685 }
 686
 687 int
 688 iavf_dev_tx_queue_setup(struct rte_eth_dev *dev,
 689                        uint16_t queue_idx,
 690                        uint16_t nb_desc,
 691                        unsigned int socket_id,
 692                        const struct rte_eth_txconf *tx_conf)
 693 {
 694         struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 695         struct iavf_info *vf =
 696                 IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 697         struct iavf_tx_queue *txq;
 698         const struct rte_memzone *mz;
 699         uint32_t ring_size;
 700         uint16_t tx_rs_thresh, tx_free_thresh;
 701         uint64_t offloads;
 702
 703         PMD_INIT_FUNC_TRACE();
 704
 705         offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
 706
 707         if (nb_desc % IAVF_ALIGN_RING_DESC != 0 ||
 708             nb_desc > IAVF_MAX_RING_DESC ||
 709             nb_desc < IAVF_MIN_RING_DESC) {
 710                 PMD_INIT_LOG(ERR, "Number (%u) of transmit descriptors is "
 711                             "invalid", nb_desc);
 712                 return -EINVAL;
 713         }
 714
 715         tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
 716                 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
 717         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
 718                 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
 719         if (check_tx_thresh(nb_desc, tx_rs_thresh, tx_free_thresh) != 0)
 720                 return -EINVAL;
 721
 722         /* Free memory if needed. */
 723         if (dev->data->tx_queues[queue_idx]) {
 724                 iavf_dev_tx_queue_release(dev, queue_idx);
 725                 dev->data->tx_queues[queue_idx] = NULL;
 726         }
 727
 728         /* Allocate the TX queue data structure. */
 729         txq = rte_zmalloc_socket("iavf txq",
 730                                  sizeof(struct iavf_tx_queue),
 731                                  RTE_CACHE_LINE_SIZE,
 732                                  socket_id);
 733         if (!txq) {
 734                 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
 735                              "tx queue structure");
 736                 return -ENOMEM;
 737         }
 738
 739         if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_VLAN_V2) {
 740                 struct virtchnl_vlan_supported_caps *insertion_support =
 741                         &vf->vlan_v2_caps.offloads.insertion_support;
 742                 uint32_t insertion_cap;
 743
 744                 if (insertion_support->outer)
 745                         insertion_cap = insertion_support->outer;
 746                 else
 747                         insertion_cap = insertion_support->inner;
 748
 749                 if (insertion_cap & VIRTCHNL_VLAN_TAG_LOCATION_L2TAG1)
 750                         txq->vlan_flag = IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG1;
 751                 else if (insertion_cap & VIRTCHNL_VLAN_TAG_LOCATION_L2TAG2)
 752                         txq->vlan_flag = IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG2;
 753         } else {
 754                 txq->vlan_flag = IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG1;
 755         }
 756
 757         txq->nb_tx_desc = nb_desc;
 758         txq->rs_thresh = tx_rs_thresh;
 759         txq->free_thresh = tx_free_thresh;
 760         txq->queue_id = queue_idx;
 761         txq->port_id = dev->data->port_id;
 762         txq->offloads = offloads;
 763         txq->tx_deferred_start = tx_conf->tx_deferred_start;
 764
 765         /* Allocate software ring */
 766         txq->sw_ring =
 767                 rte_zmalloc_socket("iavf tx sw ring",
 768                                    sizeof(struct iavf_tx_entry) * nb_desc,
 769                                    RTE_CACHE_LINE_SIZE,
 770                                    socket_id);
 771         if (!txq->sw_ring) {
 772                 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW TX ring");
 773                 rte_free(txq);
 774                 return -ENOMEM;
 775         }
 776
 777         /* Allocate TX hardware ring descriptors. */
 778         ring_size = sizeof(struct iavf_tx_desc) * IAVF_MAX_RING_DESC;
 779         ring_size = RTE_ALIGN(ring_size, IAVF_DMA_MEM_ALIGN);
 780         mz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
 781                                       ring_size, IAVF_RING_BASE_ALIGN,
 782                                       socket_id);
 783         if (!mz) {
 784                 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for TX");
 785                 rte_free(txq->sw_ring);
 786                 rte_free(txq);
 787                 return -ENOMEM;
 788         }
 789         txq->tx_ring_phys_addr = mz->iova;
 790         txq->tx_ring = (struct iavf_tx_desc *)mz->addr;
 791
 792         txq->mz = mz;
 793         reset_tx_queue(txq);
 794         txq->q_set = true;
 795         dev->data->tx_queues[queue_idx] = txq;
 796         txq->qtx_tail = hw->hw_addr + IAVF_QTX_TAIL1(queue_idx);
 797         txq->ops = &def_txq_ops;
 798
 799         if (check_tx_vec_allow(txq) == false) {
 800                 struct iavf_adapter *ad =
 801                         IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 802                 ad->tx_vec_allowed = false;
 803         }
 804
 805         if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_QOS &&
 806             vf->tm_conf.committed) {
 807                 int tc;
 808                 for (tc = 0; tc < vf->qos_cap->num_elem; tc++) {
 809                         if (txq->queue_id >= vf->qtc_map[tc].start_queue_id &&
 810                             txq->queue_id < (vf->qtc_map[tc].start_queue_id +
 811                             vf->qtc_map[tc].queue_count))
 812                                 break;
 813                 }
 814                 if (tc >= vf->qos_cap->num_elem) {
 815                         PMD_INIT_LOG(ERR, "Queue TC mapping is not correct");
 816                         return -EINVAL;
 817                 }
 818                 txq->tc = tc;
 819         }
 820
 821         return 0;
 822 }
 823
 824 int
 825 iavf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 826 {
 827         struct iavf_adapter *adapter =
 828                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 829         struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 830         struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 831         struct iavf_rx_queue *rxq;
 832         int err = 0;
 833
 834         PMD_DRV_FUNC_TRACE();
 835
 836         if (rx_queue_id >= dev->data->nb_rx_queues)
 837                 return -EINVAL;
 838
 839         rxq = dev->data->rx_queues[rx_queue_id];
 840
 841         err = alloc_rxq_mbufs(rxq);
 842         if (err) {
 843                 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
 844                 return err;
 845         }
 846
 847         rte_wmb();
 848
 849         /* Init the RX tail register. */
 850         IAVF_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 851         IAVF_WRITE_FLUSH(hw);
 852
 853         /* Ready to switch the queue on */
 854         if (!vf->lv_enabled)
 855                 err = iavf_switch_queue(adapter, rx_queue_id, true, true);
 856         else
 857                 err = iavf_switch_queue_lv(adapter, rx_queue_id, true, true);
 858
 859         if (err) {
 860                 release_rxq_mbufs(rxq);
 861                 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
 862                             rx_queue_id);
 863         } else {
 864                 dev->data->rx_queue_state[rx_queue_id] =
 865                         RTE_ETH_QUEUE_STATE_STARTED;
 866         }
 867
 868         return err;
 869 }
 870
 871 int
 872 iavf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 873 {
 874         struct iavf_adapter *adapter =
 875                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 876         struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 877         struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 878         struct iavf_tx_queue *txq;
 879         int err = 0;
 880
 881         PMD_DRV_FUNC_TRACE();
 882
 883         if (tx_queue_id >= dev->data->nb_tx_queues)
 884                 return -EINVAL;
 885
 886         txq = dev->data->tx_queues[tx_queue_id];
 887
 888         /* Init the RX tail register. */
 889         IAVF_PCI_REG_WRITE(txq->qtx_tail, 0);
 890         IAVF_WRITE_FLUSH(hw);
 891
 892         /* Ready to switch the queue on */
 893         if (!vf->lv_enabled)
 894                 err = iavf_switch_queue(adapter, tx_queue_id, false, true);
 895         else
 896                 err = iavf_switch_queue_lv(adapter, tx_queue_id, false, true);
 897
 898         if (err)
 899                 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
 900                             tx_queue_id);
 901         else
 902                 dev->data->tx_queue_state[tx_queue_id] =
 903                         RTE_ETH_QUEUE_STATE_STARTED;
 904
 905         return err;
 906 }
 907
 908 int
 909 iavf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 910 {
 911         struct iavf_adapter *adapter =
 912                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 913         struct iavf_rx_queue *rxq;
 914         int err;
 915
 916         PMD_DRV_FUNC_TRACE();
 917
 918         if (rx_queue_id >= dev->data->nb_rx_queues)
 919                 return -EINVAL;
 920
 921         err = iavf_switch_queue(adapter, rx_queue_id, true, false);
 922         if (err) {
 923                 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
 924                             rx_queue_id);
 925                 return err;
 926         }
 927
 928         rxq = dev->data->rx_queues[rx_queue_id];
 929         rxq->ops->release_mbufs(rxq);
 930         reset_rx_queue(rxq);
 931         dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 932
 933         return 0;
 934 }
 935
 936 int
 937 iavf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 938 {
 939         struct iavf_adapter *adapter =
 940                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 941         struct iavf_tx_queue *txq;
 942         int err;
 943
 944         PMD_DRV_FUNC_TRACE();
 945
 946         if (tx_queue_id >= dev->data->nb_tx_queues)
 947                 return -EINVAL;
 948
 949         err = iavf_switch_queue(adapter, tx_queue_id, false, false);
 950         if (err) {
 951                 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u off",
 952                             tx_queue_id);
 953                 return err;
 954         }
 955
 956         txq = dev->data->tx_queues[tx_queue_id];
 957         txq->ops->release_mbufs(txq);
 958         reset_tx_queue(txq);
 959         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 960
 961         return 0;
 962 }
 963
 964 void
 965 iavf_dev_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
 966 {
 967         struct iavf_rx_queue *q = dev->data->rx_queues[qid];
 968
 969         if (!q)
 970                 return;
 971
 972         q->ops->release_mbufs(q);
 973         rte_free(q->sw_ring);
 974         rte_memzone_free(q->mz);
 975         rte_free(q);
 976 }
 977
 978 void
 979 iavf_dev_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
 980 {
 981         struct iavf_tx_queue *q = dev->data->tx_queues[qid];
 982
 983         if (!q)
 984                 return;
 985
 986         q->ops->release_mbufs(q);
 987         rte_free(q->sw_ring);
 988         rte_memzone_free(q->mz);
 989         rte_free(q);
 990 }
 991
 992 void
 993 iavf_stop_queues(struct rte_eth_dev *dev)
 994 {
 995         struct iavf_adapter *adapter =
 996                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 997         struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 998         struct iavf_rx_queue *rxq;
 999         struct iavf_tx_queue *txq;
1000         int ret, i;
1001
1002         /* Stop All queues */
1003         if (!vf->lv_enabled) {
1004                 ret = iavf_disable_queues(adapter);
1005                 if (ret)
1006                         PMD_DRV_LOG(WARNING, "Fail to stop queues");
1007         } else {
1008                 ret = iavf_disable_queues_lv(adapter);
1009                 if (ret)
1010                         PMD_DRV_LOG(WARNING, "Fail to stop queues for large VF");
1011         }
1012
1013         if (ret)
1014                 PMD_DRV_LOG(WARNING, "Fail to stop queues");
1015
1016         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1017                 txq = dev->data->tx_queues[i];
1018                 if (!txq)
1019                         continue;
1020                 txq->ops->release_mbufs(txq);
1021                 reset_tx_queue(txq);
1022                 dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED;
1023         }
1024         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1025                 rxq = dev->data->rx_queues[i];
1026                 if (!rxq)
1027                         continue;
1028                 rxq->ops->release_mbufs(rxq);
1029                 reset_rx_queue(rxq);
1030                 dev->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED;
1031         }
1032 }
1033
1034 #define IAVF_RX_FLEX_ERR0_BITS  \
1035         ((1 << IAVF_RX_FLEX_DESC_STATUS0_HBO_S) |       \
1036          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_IPE_S) |  \
1037          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_L4E_S) |  \
1038          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S) | \
1039          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S) |        \
1040          (1 << IAVF_RX_FLEX_DESC_STATUS0_RXE_S))
1041
1042 static inline void
1043 iavf_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union iavf_rx_desc *rxdp)
1044 {
1045         if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1046                 (1 << IAVF_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
1047                 mb->ol_flags |= RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED;
1048                 mb->vlan_tci =
1049                         rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
1050         } else {
1051                 mb->vlan_tci = 0;
1052         }
1053 }
1054
1055 static inline void
1056 iavf_flex_rxd_to_vlan_tci(struct rte_mbuf *mb,
1057                           volatile union iavf_rx_flex_desc *rxdp)
1058 {
1059         if (rte_le_to_cpu_64(rxdp->wb.status_error0) &
1060                 (1 << IAVF_RX_FLEX_DESC_STATUS0_L2TAG1P_S)) {
1061                 mb->ol_flags |= RTE_MBUF_F_RX_VLAN |
1062                                 RTE_MBUF_F_RX_VLAN_STRIPPED;
1063                 mb->vlan_tci =
1064                         rte_le_to_cpu_16(rxdp->wb.l2tag1);
1065         } else {
1066                 mb->vlan_tci = 0;
1067         }
1068
1069 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
1070         if (rte_le_to_cpu_16(rxdp->wb.status_error1) &
1071             (1 << IAVF_RX_FLEX_DESC_STATUS1_L2TAG2P_S)) {
1072                 mb->ol_flags |= RTE_MBUF_F_RX_QINQ_STRIPPED |
1073                                 RTE_MBUF_F_RX_QINQ |
1074                                 RTE_MBUF_F_RX_VLAN_STRIPPED |
1075                                 RTE_MBUF_F_RX_VLAN;
1076                 mb->vlan_tci_outer = mb->vlan_tci;
1077                 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.l2tag2_2nd);
1078                 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
1079                            rte_le_to_cpu_16(rxdp->wb.l2tag2_1st),
1080                            rte_le_to_cpu_16(rxdp->wb.l2tag2_2nd));
1081         } else {
1082                 mb->vlan_tci_outer = 0;
1083         }
1084 #endif
1085 }
1086
1087 /* Translate the rx descriptor status and error fields to pkt flags */
1088 static inline uint64_t
1089 iavf_rxd_to_pkt_flags(uint64_t qword)
1090 {
1091         uint64_t flags;
1092         uint64_t error_bits = (qword >> IAVF_RXD_QW1_ERROR_SHIFT);
1093
1094 #define IAVF_RX_ERR_BITS 0x3f
1095
1096         /* Check if RSS_HASH */
1097         flags = (((qword >> IAVF_RX_DESC_STATUS_FLTSTAT_SHIFT) &
1098                                         IAVF_RX_DESC_FLTSTAT_RSS_HASH) ==
1099                         IAVF_RX_DESC_FLTSTAT_RSS_HASH) ? RTE_MBUF_F_RX_RSS_HASH : 0;
1100
1101         /* Check if FDIR Match */
1102         flags |= (qword & (1 << IAVF_RX_DESC_STATUS_FLM_SHIFT) ?
1103                                 RTE_MBUF_F_RX_FDIR : 0);
1104
1105         if (likely((error_bits & IAVF_RX_ERR_BITS) == 0)) {
1106                 flags |= (RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_GOOD);
1107                 return flags;
1108         }
1109
1110         if (unlikely(error_bits & (1 << IAVF_RX_DESC_ERROR_IPE_SHIFT)))
1111                 flags |= RTE_MBUF_F_RX_IP_CKSUM_BAD;
1112         else
1113                 flags |= RTE_MBUF_F_RX_IP_CKSUM_GOOD;
1114
1115         if (unlikely(error_bits & (1 << IAVF_RX_DESC_ERROR_L4E_SHIFT)))
1116                 flags |= RTE_MBUF_F_RX_L4_CKSUM_BAD;
1117         else
1118                 flags |= RTE_MBUF_F_RX_L4_CKSUM_GOOD;
1119
1120         /* TODO: Oversize error bit is not processed here */
1121
1122         return flags;
1123 }
1124
1125 static inline uint64_t
1126 iavf_rxd_build_fdir(volatile union iavf_rx_desc *rxdp, struct rte_mbuf *mb)
1127 {
1128         uint64_t flags = 0;
1129 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
1130         uint16_t flexbh;
1131
1132         flexbh = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
1133                 IAVF_RX_DESC_EXT_STATUS_FLEXBH_SHIFT) &
1134                 IAVF_RX_DESC_EXT_STATUS_FLEXBH_MASK;
1135
1136         if (flexbh == IAVF_RX_DESC_EXT_STATUS_FLEXBH_FD_ID) {
1137                 mb->hash.fdir.hi =
1138                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.fd_id);
1139                 flags |= RTE_MBUF_F_RX_FDIR_ID;
1140         }
1141 #else
1142         mb->hash.fdir.hi =
1143                 rte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.fd_id);
1144         flags |= RTE_MBUF_F_RX_FDIR_ID;
1145 #endif
1146         return flags;
1147 }
1148
1149 #define IAVF_RX_FLEX_ERR0_BITS  \
1150         ((1 << IAVF_RX_FLEX_DESC_STATUS0_HBO_S) |       \
1151          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_IPE_S) |  \
1152          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_L4E_S) |  \
1153          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S) | \
1154          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S) |        \
1155          (1 << IAVF_RX_FLEX_DESC_STATUS0_RXE_S))
1156
1157 /* Rx L3/L4 checksum */
1158 static inline uint64_t
1159 iavf_flex_rxd_error_to_pkt_flags(uint16_t stat_err0)
1160 {
1161         uint64_t flags = 0;
1162
1163         /* check if HW has decoded the packet and checksum */
1164         if (unlikely(!(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_L3L4P_S))))
1165                 return 0;
1166
1167         if (likely(!(stat_err0 & IAVF_RX_FLEX_ERR0_BITS))) {
1168                 flags |= (RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_GOOD);
1169                 return flags;
1170         }
1171
1172         if (unlikely(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_IPE_S)))
1173                 flags |= RTE_MBUF_F_RX_IP_CKSUM_BAD;
1174         else
1175                 flags |= RTE_MBUF_F_RX_IP_CKSUM_GOOD;
1176
1177         if (unlikely(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_L4E_S)))
1178                 flags |= RTE_MBUF_F_RX_L4_CKSUM_BAD;
1179         else
1180                 flags |= RTE_MBUF_F_RX_L4_CKSUM_GOOD;
1181
1182         if (unlikely(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S)))
1183                 flags |= RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD;
1184
1185         return flags;
1186 }
1187
1188 /* If the number of free RX descriptors is greater than the RX free
1189  * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1190  * register. Update the RDT with the value of the last processed RX
1191  * descriptor minus 1, to guarantee that the RDT register is never
1192  * equal to the RDH register, which creates a "full" ring situation
1193  * from the hardware point of view.
1194  */
1195 static inline void
1196 iavf_update_rx_tail(struct iavf_rx_queue *rxq, uint16_t nb_hold, uint16_t rx_id)
1197 {
1198         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1199
1200         if (nb_hold > rxq->rx_free_thresh) {
1201                 PMD_RX_LOG(DEBUG,
1202                            "port_id=%u queue_id=%u rx_tail=%u nb_hold=%u",
1203                            rxq->port_id, rxq->queue_id, rx_id, nb_hold);
1204                 rx_id = (uint16_t)((rx_id == 0) ?
1205                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
1206                 IAVF_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
1207                 nb_hold = 0;
1208         }
1209         rxq->nb_rx_hold = nb_hold;
1210 }
1211
1212 /* implement recv_pkts */
1213 uint16_t
1214 iavf_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1215 {
1216         volatile union iavf_rx_desc *rx_ring;
1217         volatile union iavf_rx_desc *rxdp;
1218         struct iavf_rx_queue *rxq;
1219         union iavf_rx_desc rxd;
1220         struct rte_mbuf *rxe;
1221         struct rte_eth_dev *dev;
1222         struct rte_mbuf *rxm;
1223         struct rte_mbuf *nmb;
1224         uint16_t nb_rx;
1225         uint32_t rx_status;
1226         uint64_t qword1;
1227         uint16_t rx_packet_len;
1228         uint16_t rx_id, nb_hold;
1229         uint64_t dma_addr;
1230         uint64_t pkt_flags;
1231         const uint32_t *ptype_tbl;
1232
1233         nb_rx = 0;
1234         nb_hold = 0;
1235         rxq = rx_queue;
1236         rx_id = rxq->rx_tail;
1237         rx_ring = rxq->rx_ring;
1238         ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1239
1240         while (nb_rx < nb_pkts) {
1241                 rxdp = &rx_ring[rx_id];
1242                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1243                 rx_status = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
1244                             IAVF_RXD_QW1_STATUS_SHIFT;
1245
1246                 /* Check the DD bit first */
1247                 if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)))
1248                         break;
1249                 IAVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
1250
1251                 nmb = rte_mbuf_raw_alloc(rxq->mp);
1252                 if (unlikely(!nmb)) {
1253                         dev = &rte_eth_devices[rxq->port_id];
1254                         dev->data->rx_mbuf_alloc_failed++;
1255                         PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1256                                    "queue_id=%u", rxq->port_id, rxq->queue_id);
1257                         break;
1258                 }
1259
1260                 rxd = *rxdp;
1261                 nb_hold++;
1262                 rxe = rxq->sw_ring[rx_id];
1263                 rxq->sw_ring[rx_id] = nmb;
1264                 rx_id++;
1265                 if (unlikely(rx_id == rxq->nb_rx_desc))
1266                         rx_id = 0;
1267
1268                 /* Prefetch next mbuf */
1269                 rte_prefetch0(rxq->sw_ring[rx_id]);
1270
1271                 /* When next RX descriptor is on a cache line boundary,
1272                  * prefetch the next 4 RX descriptors and next 8 pointers
1273                  * to mbufs.
1274                  */
1275                 if ((rx_id & 0x3) == 0) {
1276                         rte_prefetch0(&rx_ring[rx_id]);
1277                         rte_prefetch0(rxq->sw_ring[rx_id]);
1278                 }
1279                 rxm = rxe;
1280                 dma_addr =
1281                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1282                 rxdp->read.hdr_addr = 0;
1283                 rxdp->read.pkt_addr = dma_addr;
1284
1285                 rx_packet_len = ((qword1 & IAVF_RXD_QW1_LENGTH_PBUF_MASK) >>
1286                                 IAVF_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
1287
1288                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1289                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
1290                 rxm->nb_segs = 1;
1291                 rxm->next = NULL;
1292                 rxm->pkt_len = rx_packet_len;
1293                 rxm->data_len = rx_packet_len;
1294                 rxm->port = rxq->port_id;
1295                 rxm->ol_flags = 0;
1296                 iavf_rxd_to_vlan_tci(rxm, &rxd);
1297                 pkt_flags = iavf_rxd_to_pkt_flags(qword1);
1298                 rxm->packet_type =
1299                         ptype_tbl[(uint8_t)((qword1 &
1300                         IAVF_RXD_QW1_PTYPE_MASK) >> IAVF_RXD_QW1_PTYPE_SHIFT)];
1301
1302                 if (pkt_flags & RTE_MBUF_F_RX_RSS_HASH)
1303                         rxm->hash.rss =
1304                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1305
1306                 if (pkt_flags & RTE_MBUF_F_RX_FDIR)
1307                         pkt_flags |= iavf_rxd_build_fdir(&rxd, rxm);
1308
1309                 rxm->ol_flags |= pkt_flags;
1310
1311                 rx_pkts[nb_rx++] = rxm;
1312         }
1313         rxq->rx_tail = rx_id;
1314
1315         iavf_update_rx_tail(rxq, nb_hold, rx_id);
1316
1317         return nb_rx;
1318 }
1319
1320 /* implement recv_pkts for flexible Rx descriptor */
1321 uint16_t
1322 iavf_recv_pkts_flex_rxd(void *rx_queue,
1323                         struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1324 {
1325         volatile union iavf_rx_desc *rx_ring;
1326         volatile union iavf_rx_flex_desc *rxdp;
1327         struct iavf_rx_queue *rxq;
1328         union iavf_rx_flex_desc rxd;
1329         struct rte_mbuf *rxe;
1330         struct rte_eth_dev *dev;
1331         struct rte_mbuf *rxm;
1332         struct rte_mbuf *nmb;
1333         uint16_t nb_rx;
1334         uint16_t rx_stat_err0;
1335         uint16_t rx_packet_len;
1336         uint16_t rx_id, nb_hold;
1337         uint64_t dma_addr;
1338         uint64_t pkt_flags;
1339         const uint32_t *ptype_tbl;
1340
1341         nb_rx = 0;
1342         nb_hold = 0;
1343         rxq = rx_queue;
1344         rx_id = rxq->rx_tail;
1345         rx_ring = rxq->rx_ring;
1346         ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1347
1348         while (nb_rx < nb_pkts) {
1349                 rxdp = (volatile union iavf_rx_flex_desc *)&rx_ring[rx_id];
1350                 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1351
1352                 /* Check the DD bit first */
1353                 if (!(rx_stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S)))
1354                         break;
1355                 IAVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
1356
1357                 nmb = rte_mbuf_raw_alloc(rxq->mp);
1358                 if (unlikely(!nmb)) {
1359                         dev = &rte_eth_devices[rxq->port_id];
1360                         dev->data->rx_mbuf_alloc_failed++;
1361                         PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1362                                    "queue_id=%u", rxq->port_id, rxq->queue_id);
1363                         break;
1364                 }
1365
1366                 rxd = *rxdp;
1367                 nb_hold++;
1368                 rxe = rxq->sw_ring[rx_id];
1369                 rxq->sw_ring[rx_id] = nmb;
1370                 rx_id++;
1371                 if (unlikely(rx_id == rxq->nb_rx_desc))
1372                         rx_id = 0;
1373
1374                 /* Prefetch next mbuf */
1375                 rte_prefetch0(rxq->sw_ring[rx_id]);
1376
1377                 /* When next RX descriptor is on a cache line boundary,
1378                  * prefetch the next 4 RX descriptors and next 8 pointers
1379                  * to mbufs.
1380                  */
1381                 if ((rx_id & 0x3) == 0) {
1382                         rte_prefetch0(&rx_ring[rx_id]);
1383                         rte_prefetch0(rxq->sw_ring[rx_id]);
1384                 }
1385                 rxm = rxe;
1386                 dma_addr =
1387                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1388                 rxdp->read.hdr_addr = 0;
1389                 rxdp->read.pkt_addr = dma_addr;
1390
1391                 rx_packet_len = (rte_le_to_cpu_16(rxd.wb.pkt_len) &
1392                                 IAVF_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
1393
1394                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1395                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
1396                 rxm->nb_segs = 1;
1397                 rxm->next = NULL;
1398                 rxm->pkt_len = rx_packet_len;
1399                 rxm->data_len = rx_packet_len;
1400                 rxm->port = rxq->port_id;
1401                 rxm->ol_flags = 0;
1402                 rxm->packet_type = ptype_tbl[IAVF_RX_FLEX_DESC_PTYPE_M &
1403                         rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
1404                 iavf_flex_rxd_to_vlan_tci(rxm, &rxd);
1405                 rxq->rxd_to_pkt_fields(rxq, rxm, &rxd);
1406                 pkt_flags = iavf_flex_rxd_error_to_pkt_flags(rx_stat_err0);
1407                 rxm->ol_flags |= pkt_flags;
1408
1409                 rx_pkts[nb_rx++] = rxm;
1410         }
1411         rxq->rx_tail = rx_id;
1412
1413         iavf_update_rx_tail(rxq, nb_hold, rx_id);
1414
1415         return nb_rx;
1416 }
1417
1418 /* implement recv_scattered_pkts for flexible Rx descriptor */
1419 uint16_t
1420 iavf_recv_scattered_pkts_flex_rxd(void *rx_queue, struct rte_mbuf **rx_pkts,
1421                                   uint16_t nb_pkts)
1422 {
1423         struct iavf_rx_queue *rxq = rx_queue;
1424         union iavf_rx_flex_desc rxd;
1425         struct rte_mbuf *rxe;
1426         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1427         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1428         struct rte_mbuf *nmb, *rxm;
1429         uint16_t rx_id = rxq->rx_tail;
1430         uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
1431         struct rte_eth_dev *dev;
1432         uint16_t rx_stat_err0;
1433         uint64_t dma_addr;
1434         uint64_t pkt_flags;
1435
1436         volatile union iavf_rx_desc *rx_ring = rxq->rx_ring;
1437         volatile union iavf_rx_flex_desc *rxdp;
1438         const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1439
1440         while (nb_rx < nb_pkts) {
1441                 rxdp = (volatile union iavf_rx_flex_desc *)&rx_ring[rx_id];
1442                 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1443
1444                 /* Check the DD bit */
1445                 if (!(rx_stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S)))
1446                         break;
1447                 IAVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
1448
1449                 nmb = rte_mbuf_raw_alloc(rxq->mp);
1450                 if (unlikely(!nmb)) {
1451                         PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1452                                    "queue_id=%u", rxq->port_id, rxq->queue_id);
1453                         dev = &rte_eth_devices[rxq->port_id];
1454                         dev->data->rx_mbuf_alloc_failed++;
1455                         break;
1456                 }
1457
1458                 rxd = *rxdp;
1459                 nb_hold++;
1460                 rxe = rxq->sw_ring[rx_id];
1461                 rxq->sw_ring[rx_id] = nmb;
1462                 rx_id++;
1463                 if (rx_id == rxq->nb_rx_desc)
1464                         rx_id = 0;
1465
1466                 /* Prefetch next mbuf */
1467                 rte_prefetch0(rxq->sw_ring[rx_id]);
1468
1469                 /* When next RX descriptor is on a cache line boundary,
1470                  * prefetch the next 4 RX descriptors and next 8 pointers
1471                  * to mbufs.
1472                  */
1473                 if ((rx_id & 0x3) == 0) {
1474                         rte_prefetch0(&rx_ring[rx_id]);
1475                         rte_prefetch0(rxq->sw_ring[rx_id]);
1476                 }
1477
1478                 rxm = rxe;
1479                 dma_addr =
1480                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1481
1482                 /* Set data buffer address and data length of the mbuf */
1483                 rxdp->read.hdr_addr = 0;
1484                 rxdp->read.pkt_addr = dma_addr;
1485                 rx_packet_len = rte_le_to_cpu_16(rxd.wb.pkt_len) &
1486                                 IAVF_RX_FLX_DESC_PKT_LEN_M;
1487                 rxm->data_len = rx_packet_len;
1488                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1489
1490                 /* If this is the first buffer of the received packet, set the
1491                  * pointer to the first mbuf of the packet and initialize its
1492                  * context. Otherwise, update the total length and the number
1493                  * of segments of the current scattered packet, and update the
1494                  * pointer to the last mbuf of the current packet.
1495                  */
1496                 if (!first_seg) {
1497                         first_seg = rxm;
1498                         first_seg->nb_segs = 1;
1499                         first_seg->pkt_len = rx_packet_len;
1500                 } else {
1501                         first_seg->pkt_len =
1502                                 (uint16_t)(first_seg->pkt_len +
1503                                                 rx_packet_len);
1504                         first_seg->nb_segs++;
1505                         last_seg->next = rxm;
1506                 }
1507
1508                 /* If this is not the last buffer of the received packet,
1509                  * update the pointer to the last mbuf of the current scattered
1510                  * packet and continue to parse the RX ring.
1511                  */
1512                 if (!(rx_stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_EOF_S))) {
1513                         last_seg = rxm;
1514                         continue;
1515                 }
1516
1517                 /* This is the last buffer of the received packet. If the CRC
1518                  * is not stripped by the hardware:
1519                  *  - Subtract the CRC length from the total packet length.
1520                  *  - If the last buffer only contains the whole CRC or a part
1521                  *  of it, free the mbuf associated to the last buffer. If part
1522                  *  of the CRC is also contained in the previous mbuf, subtract
1523                  *  the length of that CRC part from the data length of the
1524                  *  previous mbuf.
1525                  */
1526                 rxm->next = NULL;
1527                 if (unlikely(rxq->crc_len > 0)) {
1528                         first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
1529                         if (rx_packet_len <= RTE_ETHER_CRC_LEN) {
1530                                 rte_pktmbuf_free_seg(rxm);
1531                                 first_seg->nb_segs--;
1532                                 last_seg->data_len =
1533                                         (uint16_t)(last_seg->data_len -
1534                                         (RTE_ETHER_CRC_LEN - rx_packet_len));
1535                                 last_seg->next = NULL;
1536                         } else {
1537                                 rxm->data_len = (uint16_t)(rx_packet_len -
1538                                                         RTE_ETHER_CRC_LEN);
1539                         }
1540                 }
1541
1542                 first_seg->port = rxq->port_id;
1543                 first_seg->ol_flags = 0;
1544                 first_seg->packet_type = ptype_tbl[IAVF_RX_FLEX_DESC_PTYPE_M &
1545                         rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
1546                 iavf_flex_rxd_to_vlan_tci(first_seg, &rxd);
1547                 rxq->rxd_to_pkt_fields(rxq, first_seg, &rxd);
1548                 pkt_flags = iavf_flex_rxd_error_to_pkt_flags(rx_stat_err0);
1549
1550                 first_seg->ol_flags |= pkt_flags;
1551
1552                 /* Prefetch data of first segment, if configured to do so. */
1553                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1554                                           first_seg->data_off));
1555                 rx_pkts[nb_rx++] = first_seg;
1556                 first_seg = NULL;
1557         }
1558
1559         /* Record index of the next RX descriptor to probe. */
1560         rxq->rx_tail = rx_id;
1561         rxq->pkt_first_seg = first_seg;
1562         rxq->pkt_last_seg = last_seg;
1563
1564         iavf_update_rx_tail(rxq, nb_hold, rx_id);
1565
1566         return nb_rx;
1567 }
1568
1569 /* implement recv_scattered_pkts  */
1570 uint16_t
1571 iavf_recv_scattered_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1572                         uint16_t nb_pkts)
1573 {
1574         struct iavf_rx_queue *rxq = rx_queue;
1575         union iavf_rx_desc rxd;
1576         struct rte_mbuf *rxe;
1577         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1578         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1579         struct rte_mbuf *nmb, *rxm;
1580         uint16_t rx_id = rxq->rx_tail;
1581         uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
1582         struct rte_eth_dev *dev;
1583         uint32_t rx_status;
1584         uint64_t qword1;
1585         uint64_t dma_addr;
1586         uint64_t pkt_flags;
1587
1588         volatile union iavf_rx_desc *rx_ring = rxq->rx_ring;
1589         volatile union iavf_rx_desc *rxdp;
1590         const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1591
1592         while (nb_rx < nb_pkts) {
1593                 rxdp = &rx_ring[rx_id];
1594                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1595                 rx_status = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
1596                             IAVF_RXD_QW1_STATUS_SHIFT;
1597
1598                 /* Check the DD bit */
1599                 if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)))
1600                         break;
1601                 IAVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
1602
1603                 nmb = rte_mbuf_raw_alloc(rxq->mp);
1604                 if (unlikely(!nmb)) {
1605                         PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1606                                    "queue_id=%u", rxq->port_id, rxq->queue_id);
1607                         dev = &rte_eth_devices[rxq->port_id];
1608                         dev->data->rx_mbuf_alloc_failed++;
1609                         break;
1610                 }
1611
1612                 rxd = *rxdp;
1613                 nb_hold++;
1614                 rxe = rxq->sw_ring[rx_id];
1615                 rxq->sw_ring[rx_id] = nmb;
1616                 rx_id++;
1617                 if (rx_id == rxq->nb_rx_desc)
1618                         rx_id = 0;
1619
1620                 /* Prefetch next mbuf */
1621                 rte_prefetch0(rxq->sw_ring[rx_id]);
1622
1623                 /* When next RX descriptor is on a cache line boundary,
1624                  * prefetch the next 4 RX descriptors and next 8 pointers
1625                  * to mbufs.
1626                  */
1627                 if ((rx_id & 0x3) == 0) {
1628                         rte_prefetch0(&rx_ring[rx_id]);
1629                         rte_prefetch0(rxq->sw_ring[rx_id]);
1630                 }
1631
1632                 rxm = rxe;
1633                 dma_addr =
1634                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1635
1636                 /* Set data buffer address and data length of the mbuf */
1637                 rxdp->read.hdr_addr = 0;
1638                 rxdp->read.pkt_addr = dma_addr;
1639                 rx_packet_len = (qword1 & IAVF_RXD_QW1_LENGTH_PBUF_MASK) >>
1640                                  IAVF_RXD_QW1_LENGTH_PBUF_SHIFT;
1641                 rxm->data_len = rx_packet_len;
1642                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1643
1644                 /* If this is the first buffer of the received packet, set the
1645                  * pointer to the first mbuf of the packet and initialize its
1646                  * context. Otherwise, update the total length and the number
1647                  * of segments of the current scattered packet, and update the
1648                  * pointer to the last mbuf of the current packet.
1649                  */
1650                 if (!first_seg) {
1651                         first_seg = rxm;
1652                         first_seg->nb_segs = 1;
1653                         first_seg->pkt_len = rx_packet_len;
1654                 } else {
1655                         first_seg->pkt_len =
1656                                 (uint16_t)(first_seg->pkt_len +
1657                                                 rx_packet_len);
1658                         first_seg->nb_segs++;
1659                         last_seg->next = rxm;
1660                 }
1661
1662                 /* If this is not the last buffer of the received packet,
1663                  * update the pointer to the last mbuf of the current scattered
1664                  * packet and continue to parse the RX ring.
1665                  */
1666                 if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_EOF_SHIFT))) {
1667                         last_seg = rxm;
1668                         continue;
1669                 }
1670
1671                 /* This is the last buffer of the received packet. If the CRC
1672                  * is not stripped by the hardware:
1673                  *  - Subtract the CRC length from the total packet length.
1674                  *  - If the last buffer only contains the whole CRC or a part
1675                  *  of it, free the mbuf associated to the last buffer. If part
1676                  *  of the CRC is also contained in the previous mbuf, subtract
1677                  *  the length of that CRC part from the data length of the
1678                  *  previous mbuf.
1679                  */
1680                 rxm->next = NULL;
1681                 if (unlikely(rxq->crc_len > 0)) {
1682                         first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
1683                         if (rx_packet_len <= RTE_ETHER_CRC_LEN) {
1684                                 rte_pktmbuf_free_seg(rxm);
1685                                 first_seg->nb_segs--;
1686                                 last_seg->data_len =
1687                                         (uint16_t)(last_seg->data_len -
1688                                         (RTE_ETHER_CRC_LEN - rx_packet_len));
1689                                 last_seg->next = NULL;
1690                         } else
1691                                 rxm->data_len = (uint16_t)(rx_packet_len -
1692                                                         RTE_ETHER_CRC_LEN);
1693                 }
1694
1695                 first_seg->port = rxq->port_id;
1696                 first_seg->ol_flags = 0;
1697                 iavf_rxd_to_vlan_tci(first_seg, &rxd);
1698                 pkt_flags = iavf_rxd_to_pkt_flags(qword1);
1699                 first_seg->packet_type =
1700                         ptype_tbl[(uint8_t)((qword1 &
1701                         IAVF_RXD_QW1_PTYPE_MASK) >> IAVF_RXD_QW1_PTYPE_SHIFT)];
1702
1703                 if (pkt_flags & RTE_MBUF_F_RX_RSS_HASH)
1704                         first_seg->hash.rss =
1705                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1706
1707                 if (pkt_flags & RTE_MBUF_F_RX_FDIR)
1708                         pkt_flags |= iavf_rxd_build_fdir(&rxd, first_seg);
1709
1710                 first_seg->ol_flags |= pkt_flags;
1711
1712                 /* Prefetch data of first segment, if configured to do so. */
1713                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1714                                           first_seg->data_off));
1715                 rx_pkts[nb_rx++] = first_seg;
1716                 first_seg = NULL;
1717         }
1718
1719         /* Record index of the next RX descriptor to probe. */
1720         rxq->rx_tail = rx_id;
1721         rxq->pkt_first_seg = first_seg;
1722         rxq->pkt_last_seg = last_seg;
1723
1724         iavf_update_rx_tail(rxq, nb_hold, rx_id);
1725
1726         return nb_rx;
1727 }
1728
1729 #define IAVF_LOOK_AHEAD 8
1730 static inline int
1731 iavf_rx_scan_hw_ring_flex_rxd(struct iavf_rx_queue *rxq)
1732 {
1733         volatile union iavf_rx_flex_desc *rxdp;
1734         struct rte_mbuf **rxep;
1735         struct rte_mbuf *mb;
1736         uint16_t stat_err0;
1737         uint16_t pkt_len;
1738         int32_t s[IAVF_LOOK_AHEAD], nb_dd;
1739         int32_t i, j, nb_rx = 0;
1740         uint64_t pkt_flags;
1741         const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1742
1743         rxdp = (volatile union iavf_rx_flex_desc *)&rxq->rx_ring[rxq->rx_tail];
1744         rxep = &rxq->sw_ring[rxq->rx_tail];
1745
1746         stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1747
1748         /* Make sure there is at least 1 packet to receive */
1749         if (!(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S)))
1750                 return 0;
1751
1752         /* Scan LOOK_AHEAD descriptors at a time to determine which
1753          * descriptors reference packets that are ready to be received.
1754          */
1755         for (i = 0; i < IAVF_RX_MAX_BURST; i += IAVF_LOOK_AHEAD,
1756              rxdp += IAVF_LOOK_AHEAD, rxep += IAVF_LOOK_AHEAD) {
1757                 /* Read desc statuses backwards to avoid race condition */
1758                 for (j = IAVF_LOOK_AHEAD - 1; j >= 0; j--)
1759                         s[j] = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1760
1761                 rte_smp_rmb();
1762
1763                 /* Compute how many status bits were set */
1764                 for (j = 0, nb_dd = 0; j < IAVF_LOOK_AHEAD; j++)
1765                         nb_dd += s[j] & (1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S);
1766
1767                 nb_rx += nb_dd;
1768
1769                 /* Translate descriptor info to mbuf parameters */
1770                 for (j = 0; j < nb_dd; j++) {
1771                         IAVF_DUMP_RX_DESC(rxq, &rxdp[j],
1772                                           rxq->rx_tail +
1773                                           i * IAVF_LOOK_AHEAD + j);
1774
1775                         mb = rxep[j];
1776                         pkt_len = (rte_le_to_cpu_16(rxdp[j].wb.pkt_len) &
1777                                 IAVF_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
1778                         mb->data_len = pkt_len;
1779                         mb->pkt_len = pkt_len;
1780                         mb->ol_flags = 0;
1781
1782                         mb->packet_type = ptype_tbl[IAVF_RX_FLEX_DESC_PTYPE_M &
1783                                 rte_le_to_cpu_16(rxdp[j].wb.ptype_flex_flags0)];
1784                         iavf_flex_rxd_to_vlan_tci(mb, &rxdp[j]);
1785                         rxq->rxd_to_pkt_fields(rxq, mb, &rxdp[j]);
1786                         stat_err0 = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1787                         pkt_flags = iavf_flex_rxd_error_to_pkt_flags(stat_err0);
1788
1789                         mb->ol_flags |= pkt_flags;
1790                 }
1791
1792                 for (j = 0; j < IAVF_LOOK_AHEAD; j++)
1793                         rxq->rx_stage[i + j] = rxep[j];
1794
1795                 if (nb_dd != IAVF_LOOK_AHEAD)
1796                         break;
1797         }
1798
1799         /* Clear software ring entries */
1800         for (i = 0; i < nb_rx; i++)
1801                 rxq->sw_ring[rxq->rx_tail + i] = NULL;
1802
1803         return nb_rx;
1804 }
1805
1806 static inline int
1807 iavf_rx_scan_hw_ring(struct iavf_rx_queue *rxq)
1808 {
1809         volatile union iavf_rx_desc *rxdp;
1810         struct rte_mbuf **rxep;
1811         struct rte_mbuf *mb;
1812         uint16_t pkt_len;
1813         uint64_t qword1;
1814         uint32_t rx_status;
1815         int32_t s[IAVF_LOOK_AHEAD], nb_dd;
1816         int32_t i, j, nb_rx = 0;
1817         uint64_t pkt_flags;
1818         const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1819
1820         rxdp = &rxq->rx_ring[rxq->rx_tail];
1821         rxep = &rxq->sw_ring[rxq->rx_tail];
1822
1823         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1824         rx_status = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
1825                     IAVF_RXD_QW1_STATUS_SHIFT;
1826
1827         /* Make sure there is at least 1 packet to receive */
1828         if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)))
1829                 return 0;
1830
1831         /* Scan LOOK_AHEAD descriptors at a time to determine which
1832          * descriptors reference packets that are ready to be received.
1833          */
1834         for (i = 0; i < IAVF_RX_MAX_BURST; i += IAVF_LOOK_AHEAD,
1835              rxdp += IAVF_LOOK_AHEAD, rxep += IAVF_LOOK_AHEAD) {
1836                 /* Read desc statuses backwards to avoid race condition */
1837                 for (j = IAVF_LOOK_AHEAD - 1; j >= 0; j--) {
1838                         qword1 = rte_le_to_cpu_64(
1839                                 rxdp[j].wb.qword1.status_error_len);
1840                         s[j] = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
1841                                IAVF_RXD_QW1_STATUS_SHIFT;
1842                 }
1843
1844                 rte_smp_rmb();
1845
1846                 /* Compute how many status bits were set */
1847                 for (j = 0, nb_dd = 0; j < IAVF_LOOK_AHEAD; j++)
1848                         nb_dd += s[j] & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT);
1849
1850                 nb_rx += nb_dd;
1851
1852                 /* Translate descriptor info to mbuf parameters */
1853                 for (j = 0; j < nb_dd; j++) {
1854                         IAVF_DUMP_RX_DESC(rxq, &rxdp[j],
1855                                          rxq->rx_tail + i * IAVF_LOOK_AHEAD + j);
1856
1857                         mb = rxep[j];
1858                         qword1 = rte_le_to_cpu_64
1859                                         (rxdp[j].wb.qword1.status_error_len);
1860                         pkt_len = ((qword1 & IAVF_RXD_QW1_LENGTH_PBUF_MASK) >>
1861                                   IAVF_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
1862                         mb->data_len = pkt_len;
1863                         mb->pkt_len = pkt_len;
1864                         mb->ol_flags = 0;
1865                         iavf_rxd_to_vlan_tci(mb, &rxdp[j]);
1866                         pkt_flags = iavf_rxd_to_pkt_flags(qword1);
1867                         mb->packet_type =
1868                                 ptype_tbl[(uint8_t)((qword1 &
1869                                 IAVF_RXD_QW1_PTYPE_MASK) >>
1870                                 IAVF_RXD_QW1_PTYPE_SHIFT)];
1871
1872                         if (pkt_flags & RTE_MBUF_F_RX_RSS_HASH)
1873                                 mb->hash.rss = rte_le_to_cpu_32(
1874                                         rxdp[j].wb.qword0.hi_dword.rss);
1875
1876                         if (pkt_flags & RTE_MBUF_F_RX_FDIR)
1877                                 pkt_flags |= iavf_rxd_build_fdir(&rxdp[j], mb);
1878
1879                         mb->ol_flags |= pkt_flags;
1880                 }
1881
1882                 for (j = 0; j < IAVF_LOOK_AHEAD; j++)
1883                         rxq->rx_stage[i + j] = rxep[j];
1884
1885                 if (nb_dd != IAVF_LOOK_AHEAD)
1886                         break;
1887         }
1888
1889         /* Clear software ring entries */
1890         for (i = 0; i < nb_rx; i++)
1891                 rxq->sw_ring[rxq->rx_tail + i] = NULL;
1892
1893         return nb_rx;
1894 }
1895
1896 static inline uint16_t
1897 iavf_rx_fill_from_stage(struct iavf_rx_queue *rxq,
1898                        struct rte_mbuf **rx_pkts,
1899                        uint16_t nb_pkts)
1900 {
1901         uint16_t i;
1902         struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1903
1904         nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1905
1906         for (i = 0; i < nb_pkts; i++)
1907                 rx_pkts[i] = stage[i];
1908
1909         rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1910         rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1911
1912         return nb_pkts;
1913 }
1914
1915 static inline int
1916 iavf_rx_alloc_bufs(struct iavf_rx_queue *rxq)
1917 {
1918         volatile union iavf_rx_desc *rxdp;
1919         struct rte_mbuf **rxep;
1920         struct rte_mbuf *mb;
1921         uint16_t alloc_idx, i;
1922         uint64_t dma_addr;
1923         int diag;
1924
1925         /* Allocate buffers in bulk */
1926         alloc_idx = (uint16_t)(rxq->rx_free_trigger -
1927                                 (rxq->rx_free_thresh - 1));
1928         rxep = &rxq->sw_ring[alloc_idx];
1929         diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
1930                                     rxq->rx_free_thresh);
1931         if (unlikely(diag != 0)) {
1932                 PMD_RX_LOG(ERR, "Failed to get mbufs in bulk");
1933                 return -ENOMEM;
1934         }
1935
1936         rxdp = &rxq->rx_ring[alloc_idx];
1937         for (i = 0; i < rxq->rx_free_thresh; i++) {
1938                 if (likely(i < (rxq->rx_free_thresh - 1)))
1939                         /* Prefetch next mbuf */
1940                         rte_prefetch0(rxep[i + 1]);
1941
1942                 mb = rxep[i];
1943                 rte_mbuf_refcnt_set(mb, 1);
1944                 mb->next = NULL;
1945                 mb->data_off = RTE_PKTMBUF_HEADROOM;
1946                 mb->nb_segs = 1;
1947                 mb->port = rxq->port_id;
1948                 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mb));
1949                 rxdp[i].read.hdr_addr = 0;
1950                 rxdp[i].read.pkt_addr = dma_addr;
1951         }
1952
1953         /* Update rx tail register */
1954         rte_wmb();
1955         IAVF_PCI_REG_WC_WRITE_RELAXED(rxq->qrx_tail, rxq->rx_free_trigger);
1956
1957         rxq->rx_free_trigger =
1958                 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
1959         if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1960                 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
1961
1962         return 0;
1963 }
1964
1965 static inline uint16_t
1966 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1967 {
1968         struct iavf_rx_queue *rxq = (struct iavf_rx_queue *)rx_queue;
1969         uint16_t nb_rx = 0;
1970
1971         if (!nb_pkts)
1972                 return 0;
1973
1974         if (rxq->rx_nb_avail)
1975                 return iavf_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1976
1977         if (rxq->rxdid >= IAVF_RXDID_FLEX_NIC && rxq->rxdid <= IAVF_RXDID_LAST)
1978                 nb_rx = (uint16_t)iavf_rx_scan_hw_ring_flex_rxd(rxq);
1979         else
1980                 nb_rx = (uint16_t)iavf_rx_scan_hw_ring(rxq);
1981         rxq->rx_next_avail = 0;
1982         rxq->rx_nb_avail = nb_rx;
1983         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1984
1985         if (rxq->rx_tail > rxq->rx_free_trigger) {
1986                 if (iavf_rx_alloc_bufs(rxq) != 0) {
1987                         uint16_t i, j;
1988
1989                         /* TODO: count rx_mbuf_alloc_failed here */
1990
1991                         rxq->rx_nb_avail = 0;
1992                         rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1993                         for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
1994                                 rxq->sw_ring[j] = rxq->rx_stage[i];
1995
1996                         return 0;
1997                 }
1998         }
1999
2000         if (rxq->rx_tail >= rxq->nb_rx_desc)
2001                 rxq->rx_tail = 0;
2002
2003         PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u, nb_rx=%u",
2004                    rxq->port_id, rxq->queue_id,
2005                    rxq->rx_tail, nb_rx);
2006
2007         if (rxq->rx_nb_avail)
2008                 return iavf_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
2009
2010         return 0;
2011 }
2012
2013 static uint16_t
2014 iavf_recv_pkts_bulk_alloc(void *rx_queue,
2015                          struct rte_mbuf **rx_pkts,
2016                          uint16_t nb_pkts)
2017 {
2018         uint16_t nb_rx = 0, n, count;
2019
2020         if (unlikely(nb_pkts == 0))
2021                 return 0;
2022
2023         if (likely(nb_pkts <= IAVF_RX_MAX_BURST))
2024                 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
2025
2026         while (nb_pkts) {
2027                 n = RTE_MIN(nb_pkts, IAVF_RX_MAX_BURST);
2028                 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
2029                 nb_rx = (uint16_t)(nb_rx + count);
2030                 nb_pkts = (uint16_t)(nb_pkts - count);
2031                 if (count < n)
2032                         break;
2033         }
2034
2035         return nb_rx;
2036 }
2037
2038 static inline int
2039 iavf_xmit_cleanup(struct iavf_tx_queue *txq)
2040 {
2041         struct iavf_tx_entry *sw_ring = txq->sw_ring;
2042         uint16_t last_desc_cleaned = txq->last_desc_cleaned;
2043         uint16_t nb_tx_desc = txq->nb_tx_desc;
2044         uint16_t desc_to_clean_to;
2045         uint16_t nb_tx_to_clean;
2046
2047         volatile struct iavf_tx_desc *txd = txq->tx_ring;
2048
2049         desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->rs_thresh);
2050         if (desc_to_clean_to >= nb_tx_desc)
2051                 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
2052
2053         desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
2054         if ((txd[desc_to_clean_to].cmd_type_offset_bsz &
2055                         rte_cpu_to_le_64(IAVF_TXD_QW1_DTYPE_MASK)) !=
2056                         rte_cpu_to_le_64(IAVF_TX_DESC_DTYPE_DESC_DONE)) {
2057                 PMD_TX_LOG(DEBUG, "TX descriptor %4u is not done "
2058                            "(port=%d queue=%d)", desc_to_clean_to,
2059                            txq->port_id, txq->queue_id);
2060                 return -1;
2061         }
2062
2063         if (last_desc_cleaned > desc_to_clean_to)
2064                 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
2065                                                         desc_to_clean_to);
2066         else
2067                 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
2068                                         last_desc_cleaned);
2069
2070         txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
2071
2072         txq->last_desc_cleaned = desc_to_clean_to;
2073         txq->nb_free = (uint16_t)(txq->nb_free + nb_tx_to_clean);
2074
2075         return 0;
2076 }
2077
2078
2079
2080 static inline void
2081 iavf_fill_ctx_desc_cmd_field(volatile uint64_t *field, struct rte_mbuf *m)
2082 {
2083         uint64_t cmd = 0;
2084
2085         /* TSO enabled */
2086         if (m->ol_flags & (RTE_MBUF_F_TX_TCP_SEG | RTE_MBUF_F_TX_UDP_SEG))
2087                 cmd = IAVF_TX_CTX_DESC_TSO << IAVF_TXD_DATA_QW1_CMD_SHIFT;
2088
2089         /* Time Sync - Currently not supported */
2090
2091         /* Outer L2 TAG 2 Insertion - Currently not supported */
2092         /* Inner L2 TAG 2 Insertion - Currently not supported */
2093
2094         *field |= cmd;
2095 }
2096
2097 static inline void
2098 iavf_fill_ctx_desc_tunnelling_field(volatile uint64_t *qw0,
2099                 const struct rte_mbuf *m)
2100 {
2101         uint64_t eip_typ = IAVF_TX_CTX_DESC_EIPT_NONE;
2102         uint64_t eip_len = 0;
2103         uint64_t eip_noinc = 0;
2104         /* Default - IP_ID is increment in each segment of LSO */
2105
2106         switch (m->ol_flags & (RTE_MBUF_F_TX_OUTER_IPV4 |
2107                         RTE_MBUF_F_TX_OUTER_IPV6 |
2108                         RTE_MBUF_F_TX_OUTER_IP_CKSUM)) {
2109         case RTE_MBUF_F_TX_OUTER_IPV4:
2110                 eip_typ = IAVF_TX_CTX_DESC_EIPT_IPV4_NO_CHECKSUM_OFFLOAD;
2111                 eip_len = m->outer_l3_len >> 2;
2112         break;
2113         case RTE_MBUF_F_TX_OUTER_IPV4 | RTE_MBUF_F_TX_OUTER_IP_CKSUM:
2114                 eip_typ = IAVF_TX_CTX_DESC_EIPT_IPV4_CHECKSUM_OFFLOAD;
2115                 eip_len = m->outer_l3_len >> 2;
2116         break;
2117         case RTE_MBUF_F_TX_OUTER_IPV6:
2118                 eip_typ = IAVF_TX_CTX_DESC_EIPT_IPV6;
2119                 eip_len = m->outer_l3_len >> 2;
2120         break;
2121         }
2122
2123         *qw0 = eip_typ << IAVF_TXD_CTX_QW0_TUN_PARAMS_EIPT_SHIFT |
2124                 eip_len << IAVF_TXD_CTX_QW0_TUN_PARAMS_EIPLEN_SHIFT |
2125                 eip_noinc << IAVF_TXD_CTX_QW0_TUN_PARAMS_EIP_NOINC_SHIFT;
2126 }
2127
2128 static inline uint16_t
2129 iavf_fill_ctx_desc_segmentation_field(volatile uint64_t *field,
2130         struct rte_mbuf *m)
2131 {
2132         uint64_t segmentation_field = 0;
2133         uint64_t total_length = 0;
2134
2135         total_length = m->pkt_len - (m->l2_len + m->l3_len + m->l4_len);
2136
2137         if (m->ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK)
2138                 total_length -= m->outer_l3_len;
2139
2140 #ifdef RTE_LIBRTE_IAVF_DEBUG_TX
2141         if (!m->l4_len || !m->tso_segsz)
2142                 PMD_TX_LOG(DEBUG, "L4 length %d, LSO Segment size %d",
2143                          m->l4_len, m->tso_segsz);
2144         if (m->tso_segsz < 88)
2145                 PMD_TX_LOG(DEBUG, "LSO Segment size %d is less than minimum %d",
2146                         m->tso_segsz, 88);
2147 #endif
2148         segmentation_field =
2149                 (((uint64_t)total_length << IAVF_TXD_CTX_QW1_TSO_LEN_SHIFT) &
2150                                 IAVF_TXD_CTX_QW1_TSO_LEN_MASK) |
2151                 (((uint64_t)m->tso_segsz << IAVF_TXD_CTX_QW1_MSS_SHIFT) &
2152                                 IAVF_TXD_CTX_QW1_MSS_MASK);
2153
2154         *field |= segmentation_field;
2155
2156         return total_length;
2157 }
2158
2159
2160 struct iavf_tx_context_desc_qws {
2161         __le64 qw0;
2162         __le64 qw1;
2163 };
2164
2165 static inline void
2166 iavf_fill_context_desc(volatile struct iavf_tx_context_desc *desc,
2167         struct rte_mbuf *m, uint16_t *tlen)
2168 {
2169         volatile struct iavf_tx_context_desc_qws *desc_qws =
2170                         (volatile struct iavf_tx_context_desc_qws *)desc;
2171         /* fill descriptor type field */
2172         desc_qws->qw1 = IAVF_TX_DESC_DTYPE_CONTEXT;
2173
2174         /* fill command field */
2175         iavf_fill_ctx_desc_cmd_field(&desc_qws->qw1, m);
2176
2177         /* fill segmentation field */
2178         if (m->ol_flags & (RTE_MBUF_F_TX_TCP_SEG | RTE_MBUF_F_TX_UDP_SEG)) {
2179                 *tlen = iavf_fill_ctx_desc_segmentation_field(&desc_qws->qw1,
2180                                 m);
2181         }
2182
2183         /* fill tunnelling field */
2184         if (m->ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK)
2185                 iavf_fill_ctx_desc_tunnelling_field(&desc_qws->qw0, m);
2186         else
2187                 desc_qws->qw0 = 0;
2188
2189         desc_qws->qw0 = rte_cpu_to_le_64(desc_qws->qw0);
2190         desc_qws->qw1 = rte_cpu_to_le_64(desc_qws->qw1);
2191 }
2192
2193
2194 static inline void
2195 iavf_build_data_desc_cmd_offset_fields(volatile uint64_t *qw1,
2196                 struct rte_mbuf *m)
2197 {
2198         uint64_t command = 0;
2199         uint64_t offset = 0;
2200         uint64_t l2tag1 = 0;
2201
2202         *qw1 = IAVF_TX_DESC_DTYPE_DATA;
2203
2204         command = (uint64_t)IAVF_TX_DESC_CMD_ICRC;
2205
2206         /* Descriptor based VLAN insertion */
2207         if (m->ol_flags & RTE_MBUF_F_TX_VLAN) {
2208                 command |= (uint64_t)IAVF_TX_DESC_CMD_IL2TAG1;
2209                 l2tag1 |= m->vlan_tci;
2210         }
2211
2212         /* Set MACLEN */
2213         offset |= (m->l2_len >> 1) << IAVF_TX_DESC_LENGTH_MACLEN_SHIFT;
2214
2215         /* Enable L3 checksum offloading inner */
2216         if (m->ol_flags & (RTE_MBUF_F_TX_IP_CKSUM | RTE_MBUF_F_TX_IPV4)) {
2217                 command |= IAVF_TX_DESC_CMD_IIPT_IPV4_CSUM;
2218                 offset |= (m->l3_len >> 2) << IAVF_TX_DESC_LENGTH_IPLEN_SHIFT;
2219         } else if (m->ol_flags & RTE_MBUF_F_TX_IPV4) {
2220                 command |= IAVF_TX_DESC_CMD_IIPT_IPV4;
2221                 offset |= (m->l3_len >> 2) << IAVF_TX_DESC_LENGTH_IPLEN_SHIFT;
2222         } else if (m->ol_flags & RTE_MBUF_F_TX_IPV6) {
2223                 command |= IAVF_TX_DESC_CMD_IIPT_IPV6;
2224                 offset |= (m->l3_len >> 2) << IAVF_TX_DESC_LENGTH_IPLEN_SHIFT;
2225         }
2226
2227         if (m->ol_flags & RTE_MBUF_F_TX_TCP_SEG) {
2228                 command |= IAVF_TX_DESC_CMD_L4T_EOFT_TCP;
2229                 offset |= (m->l4_len >> 2) <<
2230                               IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2231         }
2232
2233         /* Enable L4 checksum offloads */
2234         switch (m->ol_flags & RTE_MBUF_F_TX_L4_MASK) {
2235         case RTE_MBUF_F_TX_TCP_CKSUM:
2236                 command |= IAVF_TX_DESC_CMD_L4T_EOFT_TCP;
2237                 offset |= (sizeof(struct rte_tcp_hdr) >> 2) <<
2238                                 IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2239                 break;
2240         case RTE_MBUF_F_TX_SCTP_CKSUM:
2241                 command |= IAVF_TX_DESC_CMD_L4T_EOFT_SCTP;
2242                 offset |= (sizeof(struct rte_sctp_hdr) >> 2) <<
2243                                 IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2244                 break;
2245         case RTE_MBUF_F_TX_UDP_CKSUM:
2246                 command |= IAVF_TX_DESC_CMD_L4T_EOFT_UDP;
2247                 offset |= (sizeof(struct rte_udp_hdr) >> 2) <<
2248                                 IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2249                 break;
2250         }
2251
2252         *qw1 = rte_cpu_to_le_64((((uint64_t)command <<
2253                 IAVF_TXD_DATA_QW1_CMD_SHIFT) & IAVF_TXD_DATA_QW1_CMD_MASK) |
2254                 (((uint64_t)offset << IAVF_TXD_DATA_QW1_OFFSET_SHIFT) &
2255                 IAVF_TXD_DATA_QW1_OFFSET_MASK) |
2256                 ((uint64_t)l2tag1 << IAVF_TXD_DATA_QW1_L2TAG1_SHIFT));
2257 }
2258
2259 static inline void
2260 iavf_fill_data_desc(volatile struct iavf_tx_desc *desc,
2261         struct rte_mbuf *m, uint64_t desc_template,
2262         uint16_t tlen, uint16_t ipseclen)
2263 {
2264         uint32_t hdrlen = m->l2_len;
2265         uint32_t bufsz = 0;
2266
2267         /* fill data descriptor qw1 from template */
2268         desc->cmd_type_offset_bsz = desc_template;
2269
2270         /* set data buffer address */
2271         desc->buffer_addr = rte_mbuf_data_iova(m);
2272
2273         /* calculate data buffer size less set header lengths */
2274         if ((m->ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK) &&
2275                         (m->ol_flags & (RTE_MBUF_F_TX_TCP_SEG |
2276                                         RTE_MBUF_F_TX_UDP_SEG))) {
2277                 hdrlen += m->outer_l3_len;
2278                 if (m->ol_flags & RTE_MBUF_F_TX_L4_MASK)
2279                         hdrlen += m->l3_len + m->l4_len;
2280                 else
2281                         hdrlen += m->l3_len;
2282                 if (m->ol_flags & RTE_MBUF_F_TX_SEC_OFFLOAD)
2283                         hdrlen += ipseclen;
2284                 bufsz = hdrlen + tlen;
2285         } else {
2286                 bufsz = m->data_len;
2287         }
2288
2289         /* set data buffer size */
2290         desc->cmd_type_offset_bsz |=
2291                 (((uint64_t)bufsz << IAVF_TXD_DATA_QW1_TX_BUF_SZ_SHIFT) &
2292                 IAVF_TXD_DATA_QW1_TX_BUF_SZ_MASK);
2293
2294         desc->buffer_addr = rte_cpu_to_le_64(desc->buffer_addr);
2295         desc->cmd_type_offset_bsz = rte_cpu_to_le_64(desc->cmd_type_offset_bsz);
2296 }
2297
2298
2299 /* TX function */
2300 uint16_t
2301 iavf_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2302 {
2303         struct iavf_tx_queue *txq = tx_queue;
2304         volatile struct iavf_tx_desc *txr = txq->tx_ring;
2305         struct iavf_tx_entry *txe_ring = txq->sw_ring;
2306         struct iavf_tx_entry *txe, *txn;
2307         struct rte_mbuf *mb, *mb_seg;
2308         uint16_t desc_idx, desc_idx_last;
2309         uint16_t idx;
2310
2311
2312         /* Check if the descriptor ring needs to be cleaned. */
2313         if (txq->nb_free < txq->free_thresh)
2314                 iavf_xmit_cleanup(txq);
2315
2316         desc_idx = txq->tx_tail;
2317         txe = &txe_ring[desc_idx];
2318
2319 #ifdef RTE_LIBRTE_IAVF_DEBUG_TX_DESC_RING
2320                 iavf_dump_tx_entry_ring(txq);
2321                 iavf_dump_tx_desc_ring(txq);
2322 #endif
2323
2324
2325         for (idx = 0; idx < nb_pkts; idx++) {
2326                 volatile struct iavf_tx_desc *ddesc;
2327                 uint16_t nb_desc_ctx;
2328                 uint16_t nb_desc_data, nb_desc_required;
2329                 uint16_t tlen = 0, ipseclen = 0;
2330                 uint64_t ddesc_template = 0;
2331                 uint64_t ddesc_cmd = 0;
2332
2333                 mb = tx_pkts[idx];
2334
2335                 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
2336
2337                 nb_desc_data = mb->nb_segs;
2338                 nb_desc_ctx = !!(mb->ol_flags &
2339                         (RTE_MBUF_F_TX_TCP_SEG | RTE_MBUF_F_TX_UDP_SEG |
2340                                         RTE_MBUF_F_TX_TUNNEL_MASK));
2341
2342                 /**
2343                  * The number of descriptors that must be allocated for
2344                  * a packet equals to the number of the segments of that
2345                  * packet plus the context and ipsec descriptors if needed.
2346                  */
2347                 nb_desc_required = nb_desc_data + nb_desc_ctx;
2348
2349                 desc_idx_last = (uint16_t)(desc_idx + nb_desc_required - 1);
2350
2351                 /* wrap descriptor ring */
2352                 if (desc_idx_last >= txq->nb_tx_desc)
2353                         desc_idx_last =
2354                                 (uint16_t)(desc_idx_last - txq->nb_tx_desc);
2355
2356                 PMD_TX_LOG(DEBUG,
2357                         "port_id=%u queue_id=%u tx_first=%u tx_last=%u",
2358                         txq->port_id, txq->queue_id, desc_idx, desc_idx_last);
2359
2360                 if (nb_desc_required > txq->nb_free) {
2361                         if (iavf_xmit_cleanup(txq)) {
2362                                 if (idx == 0)
2363                                         return 0;
2364                                 goto end_of_tx;
2365                         }
2366                         if (unlikely(nb_desc_required > txq->rs_thresh)) {
2367                                 while (nb_desc_required > txq->nb_free) {
2368                                         if (iavf_xmit_cleanup(txq)) {
2369                                                 if (idx == 0)
2370                                                         return 0;
2371                                                 goto end_of_tx;
2372                                         }
2373                                 }
2374                         }
2375                 }
2376
2377                 iavf_build_data_desc_cmd_offset_fields(&ddesc_template, mb);
2378
2379                         /* Setup TX context descriptor if required */
2380                 if (nb_desc_ctx) {
2381                         volatile struct iavf_tx_context_desc *ctx_desc =
2382                                 (volatile struct iavf_tx_context_desc *)
2383                                         &txr[desc_idx];
2384
2385                         /* clear QW0 or the previous writeback value
2386                          * may impact next write
2387                          */
2388                         *(volatile uint64_t *)ctx_desc = 0;
2389
2390                         txn = &txe_ring[txe->next_id];
2391                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
2392
2393                         if (txe->mbuf) {
2394                                 rte_pktmbuf_free_seg(txe->mbuf);
2395                                 txe->mbuf = NULL;
2396                         }
2397
2398                         iavf_fill_context_desc(ctx_desc, mb, &tlen);
2399                         IAVF_DUMP_TX_DESC(txq, ctx_desc, desc_idx);
2400
2401                         txe->last_id = desc_idx_last;
2402                         desc_idx = txe->next_id;
2403                         txe = txn;
2404                         }
2405
2406
2407
2408                 mb_seg = mb;
2409
2410                 do {
2411                         ddesc = (volatile struct iavf_tx_desc *)
2412                                         &txr[desc_idx];
2413
2414                         txn = &txe_ring[txe->next_id];
2415                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
2416
2417                         if (txe->mbuf)
2418                                 rte_pktmbuf_free_seg(txe->mbuf);
2419
2420                         txe->mbuf = mb_seg;
2421                         iavf_fill_data_desc(ddesc, mb_seg,
2422                                         ddesc_template, tlen, ipseclen);
2423
2424                         IAVF_DUMP_TX_DESC(txq, ddesc, desc_idx);
2425
2426                         txe->last_id = desc_idx_last;
2427                         desc_idx = txe->next_id;
2428                         txe = txn;
2429                         mb_seg = mb_seg->next;
2430                 } while (mb_seg);
2431
2432                 /* The last packet data descriptor needs End Of Packet (EOP) */
2433                 ddesc_cmd = IAVF_TX_DESC_CMD_EOP;
2434
2435                 txq->nb_used = (uint16_t)(txq->nb_used + nb_desc_required);
2436                 txq->nb_free = (uint16_t)(txq->nb_free - nb_desc_required);
2437
2438                 if (txq->nb_used >= txq->rs_thresh) {
2439                         PMD_TX_LOG(DEBUG, "Setting RS bit on TXD id="
2440                                    "%4u (port=%d queue=%d)",
2441                                    desc_idx_last, txq->port_id, txq->queue_id);
2442
2443                         ddesc_cmd |= IAVF_TX_DESC_CMD_RS;
2444
2445                         /* Update txq RS bit counters */
2446                         txq->nb_used = 0;
2447                 }
2448
2449                 ddesc->cmd_type_offset_bsz |= rte_cpu_to_le_64(ddesc_cmd <<
2450                                 IAVF_TXD_DATA_QW1_CMD_SHIFT);
2451
2452                 IAVF_DUMP_TX_DESC(txq, ddesc, desc_idx - 1);
2453         }
2454
2455 end_of_tx:
2456         rte_wmb();
2457
2458         PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
2459                    txq->port_id, txq->queue_id, desc_idx, idx);
2460
2461         IAVF_PCI_REG_WRITE_RELAXED(txq->qtx_tail, desc_idx);
2462         txq->tx_tail = desc_idx;
2463
2464         return idx;
2465 }
2466
2467 /* Check if the packet with vlan user priority is transmitted in the
2468  * correct queue.
2469  */
2470 static int
2471 iavf_check_vlan_up2tc(struct iavf_tx_queue *txq, struct rte_mbuf *m)
2472 {
2473         struct rte_eth_dev *dev = &rte_eth_devices[txq->port_id];
2474         struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2475         uint16_t up;
2476
2477         up = m->vlan_tci >> IAVF_VLAN_TAG_PCP_OFFSET;
2478
2479         if (!(vf->qos_cap->cap[txq->tc].tc_prio & BIT(up))) {
2480                 PMD_TX_LOG(ERR, "packet with vlan pcp %u cannot transmit in queue %u\n",
2481                         up, txq->queue_id);
2482                 return -1;
2483         } else {
2484                 return 0;
2485         }
2486 }
2487
2488 /* TX prep functions */
2489 uint16_t
2490 iavf_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
2491               uint16_t nb_pkts)
2492 {
2493         int i, ret;
2494         uint64_t ol_flags;
2495         struct rte_mbuf *m;
2496         struct iavf_tx_queue *txq = tx_queue;
2497         struct rte_eth_dev *dev = &rte_eth_devices[txq->port_id];
2498         struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2499
2500         for (i = 0; i < nb_pkts; i++) {
2501                 m = tx_pkts[i];
2502                 ol_flags = m->ol_flags;
2503
2504                 /* Check condition for nb_segs > IAVF_TX_MAX_MTU_SEG. */
2505                 if (!(ol_flags & RTE_MBUF_F_TX_TCP_SEG)) {
2506                         if (m->nb_segs > IAVF_TX_MAX_MTU_SEG) {
2507                                 rte_errno = EINVAL;
2508                                 return i;
2509                         }
2510                 } else if ((m->tso_segsz < IAVF_MIN_TSO_MSS) ||
2511                            (m->tso_segsz > IAVF_MAX_TSO_MSS)) {
2512                         /* MSS outside the range are considered malicious */
2513                         rte_errno = EINVAL;
2514                         return i;
2515                 }
2516
2517                 if (ol_flags & IAVF_TX_OFFLOAD_NOTSUP_MASK) {
2518                         rte_errno = ENOTSUP;
2519                         return i;
2520                 }
2521
2522 #ifdef RTE_ETHDEV_DEBUG_TX
2523                 ret = rte_validate_tx_offload(m);
2524                 if (ret != 0) {
2525                         rte_errno = -ret;
2526                         return i;
2527                 }
2528 #endif
2529                 ret = rte_net_intel_cksum_prepare(m);
2530                 if (ret != 0) {
2531                         rte_errno = -ret;
2532                         return i;
2533                 }
2534
2535                 if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_QOS &&
2536                     ol_flags & (RTE_MBUF_F_RX_VLAN_STRIPPED | RTE_MBUF_F_RX_VLAN)) {
2537                         ret = iavf_check_vlan_up2tc(txq, m);
2538                         if (ret != 0) {
2539                                 rte_errno = -ret;
2540                                 return i;
2541                         }
2542                 }
2543         }
2544
2545         return i;
2546 }
2547
2548 /* choose rx function*/
2549 void
2550 iavf_set_rx_function(struct rte_eth_dev *dev)
2551 {
2552         struct iavf_adapter *adapter =
2553                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2554         struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2555
2556 #ifdef RTE_ARCH_X86
2557         struct iavf_rx_queue *rxq;
2558         int i;
2559         int check_ret;
2560         bool use_avx2 = false;
2561         bool use_avx512 = false;
2562         bool use_flex = false;
2563
2564         check_ret = iavf_rx_vec_dev_check(dev);
2565         if (check_ret >= 0 &&
2566             rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
2567                 if ((rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
2568                      rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) &&
2569                     rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256)
2570                         use_avx2 = true;
2571
2572 #ifdef CC_AVX512_SUPPORT
2573                 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 &&
2574                     rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1 &&
2575                     rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512)
2576                         use_avx512 = true;
2577 #endif
2578
2579                 if (vf->vf_res->vf_cap_flags &
2580                         VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC)
2581                         use_flex = true;
2582
2583                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2584                         rxq = dev->data->rx_queues[i];
2585                         (void)iavf_rxq_vec_setup(rxq);
2586                 }
2587
2588                 if (dev->data->scattered_rx) {
2589                         if (!use_avx512) {
2590                                 PMD_DRV_LOG(DEBUG,
2591                                             "Using %sVector Scattered Rx (port %d).",
2592                                             use_avx2 ? "avx2 " : "",
2593                                             dev->data->port_id);
2594                         } else {
2595                                 if (check_ret == IAVF_VECTOR_PATH)
2596                                         PMD_DRV_LOG(DEBUG,
2597                                                     "Using AVX512 Vector Scattered Rx (port %d).",
2598                                                     dev->data->port_id);
2599                                 else
2600                                         PMD_DRV_LOG(DEBUG,
2601                                                     "Using AVX512 OFFLOAD Vector Scattered Rx (port %d).",
2602                                                     dev->data->port_id);
2603                         }
2604                         if (use_flex) {
2605                                 dev->rx_pkt_burst = use_avx2 ?
2606                                         iavf_recv_scattered_pkts_vec_avx2_flex_rxd :
2607                                         iavf_recv_scattered_pkts_vec_flex_rxd;
2608 #ifdef CC_AVX512_SUPPORT
2609                                 if (use_avx512) {
2610                                         if (check_ret == IAVF_VECTOR_PATH)
2611                                                 dev->rx_pkt_burst =
2612                                                         iavf_recv_scattered_pkts_vec_avx512_flex_rxd;
2613                                         else
2614                                                 dev->rx_pkt_burst =
2615                                                         iavf_recv_scattered_pkts_vec_avx512_flex_rxd_offload;
2616                                 }
2617 #endif
2618                         } else {
2619                                 dev->rx_pkt_burst = use_avx2 ?
2620                                         iavf_recv_scattered_pkts_vec_avx2 :
2621                                         iavf_recv_scattered_pkts_vec;
2622 #ifdef CC_AVX512_SUPPORT
2623                                 if (use_avx512) {
2624                                         if (check_ret == IAVF_VECTOR_PATH)
2625                                                 dev->rx_pkt_burst =
2626                                                         iavf_recv_scattered_pkts_vec_avx512;
2627                                         else
2628                                                 dev->rx_pkt_burst =
2629                                                         iavf_recv_scattered_pkts_vec_avx512_offload;
2630                                 }
2631 #endif
2632                         }
2633                 } else {
2634                         if (!use_avx512) {
2635                                 PMD_DRV_LOG(DEBUG, "Using %sVector Rx (port %d).",
2636                                             use_avx2 ? "avx2 " : "",
2637                                             dev->data->port_id);
2638                         } else {
2639                                 if (check_ret == IAVF_VECTOR_PATH)
2640                                         PMD_DRV_LOG(DEBUG,
2641                                                     "Using AVX512 Vector Rx (port %d).",
2642                                                     dev->data->port_id);
2643                                 else
2644                                         PMD_DRV_LOG(DEBUG,
2645                                                     "Using AVX512 OFFLOAD Vector Rx (port %d).",
2646                                                     dev->data->port_id);
2647                         }
2648                         if (use_flex) {
2649                                 dev->rx_pkt_burst = use_avx2 ?
2650                                         iavf_recv_pkts_vec_avx2_flex_rxd :
2651                                         iavf_recv_pkts_vec_flex_rxd;
2652 #ifdef CC_AVX512_SUPPORT
2653                                 if (use_avx512) {
2654                                         if (check_ret == IAVF_VECTOR_PATH)
2655                                                 dev->rx_pkt_burst =
2656                                                         iavf_recv_pkts_vec_avx512_flex_rxd;
2657                                         else
2658                                                 dev->rx_pkt_burst =
2659                                                         iavf_recv_pkts_vec_avx512_flex_rxd_offload;
2660                                 }
2661 #endif
2662                         } else {
2663                                 dev->rx_pkt_burst = use_avx2 ?
2664                                         iavf_recv_pkts_vec_avx2 :
2665                                         iavf_recv_pkts_vec;
2666 #ifdef CC_AVX512_SUPPORT
2667                                 if (use_avx512) {
2668                                         if (check_ret == IAVF_VECTOR_PATH)
2669                                                 dev->rx_pkt_burst =
2670                                                         iavf_recv_pkts_vec_avx512;
2671                                         else
2672                                                 dev->rx_pkt_burst =
2673                                                         iavf_recv_pkts_vec_avx512_offload;
2674                                 }
2675 #endif
2676                         }
2677                 }
2678
2679                 return;
2680         }
2681
2682 #endif
2683         if (dev->data->scattered_rx) {
2684                 PMD_DRV_LOG(DEBUG, "Using a Scattered Rx callback (port=%d).",
2685                             dev->data->port_id);
2686                 if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC)
2687                         dev->rx_pkt_burst = iavf_recv_scattered_pkts_flex_rxd;
2688                 else
2689                         dev->rx_pkt_burst = iavf_recv_scattered_pkts;
2690         } else if (adapter->rx_bulk_alloc_allowed) {
2691                 PMD_DRV_LOG(DEBUG, "Using bulk Rx callback (port=%d).",
2692                             dev->data->port_id);
2693                 dev->rx_pkt_burst = iavf_recv_pkts_bulk_alloc;
2694         } else {
2695                 PMD_DRV_LOG(DEBUG, "Using Basic Rx callback (port=%d).",
2696                             dev->data->port_id);
2697                 if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC)
2698                         dev->rx_pkt_burst = iavf_recv_pkts_flex_rxd;
2699                 else
2700                         dev->rx_pkt_burst = iavf_recv_pkts;
2701         }
2702 }
2703
2704 /* choose tx function*/
2705 void
2706 iavf_set_tx_function(struct rte_eth_dev *dev)
2707 {
2708 #ifdef RTE_ARCH_X86
2709         struct iavf_tx_queue *txq;
2710         int i;
2711         int check_ret;
2712         bool use_sse = false;
2713         bool use_avx2 = false;
2714         bool use_avx512 = false;
2715
2716         check_ret = iavf_tx_vec_dev_check(dev);
2717
2718         if (check_ret >= 0 &&
2719             rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
2720                 /* SSE and AVX2 not support offload path yet. */
2721                 if (check_ret == IAVF_VECTOR_PATH) {
2722                         use_sse = true;
2723                         if ((rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
2724                              rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) &&
2725                             rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256)
2726                                 use_avx2 = true;
2727                 }
2728 #ifdef CC_AVX512_SUPPORT
2729                 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 &&
2730                     rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1 &&
2731                     rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512)
2732                         use_avx512 = true;
2733 #endif
2734
2735                 if (!use_sse && !use_avx2 && !use_avx512)
2736                         goto normal;
2737
2738                 if (!use_avx512) {
2739                         PMD_DRV_LOG(DEBUG, "Using %sVector Tx (port %d).",
2740                                     use_avx2 ? "avx2 " : "",
2741                                     dev->data->port_id);
2742                         dev->tx_pkt_burst = use_avx2 ?
2743                                             iavf_xmit_pkts_vec_avx2 :
2744                                             iavf_xmit_pkts_vec;
2745                 }
2746                 dev->tx_pkt_prepare = NULL;
2747 #ifdef CC_AVX512_SUPPORT
2748                 if (use_avx512) {
2749                         if (check_ret == IAVF_VECTOR_PATH) {
2750                                 dev->tx_pkt_burst = iavf_xmit_pkts_vec_avx512;
2751                                 PMD_DRV_LOG(DEBUG, "Using AVX512 Vector Tx (port %d).",
2752                                             dev->data->port_id);
2753                         } else {
2754                                 dev->tx_pkt_burst = iavf_xmit_pkts_vec_avx512_offload;
2755                                 dev->tx_pkt_prepare = iavf_prep_pkts;
2756                                 PMD_DRV_LOG(DEBUG, "Using AVX512 OFFLOAD Vector Tx (port %d).",
2757                                             dev->data->port_id);
2758                         }
2759                 }
2760 #endif
2761
2762                 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2763                         txq = dev->data->tx_queues[i];
2764                         if (!txq)
2765                                 continue;
2766 #ifdef CC_AVX512_SUPPORT
2767                         if (use_avx512)
2768                                 iavf_txq_vec_setup_avx512(txq);
2769                         else
2770                                 iavf_txq_vec_setup(txq);
2771 #else
2772                         iavf_txq_vec_setup(txq);
2773 #endif
2774                 }
2775
2776                 return;
2777         }
2778
2779 normal:
2780 #endif
2781         PMD_DRV_LOG(DEBUG, "Using Basic Tx callback (port=%d).",
2782                     dev->data->port_id);
2783         dev->tx_pkt_burst = iavf_xmit_pkts;
2784         dev->tx_pkt_prepare = iavf_prep_pkts;
2785 }
2786
2787 static int
2788 iavf_tx_done_cleanup_full(struct iavf_tx_queue *txq,
2789                         uint32_t free_cnt)
2790 {
2791         struct iavf_tx_entry *swr_ring = txq->sw_ring;
2792         uint16_t i, tx_last, tx_id;
2793         uint16_t nb_tx_free_last;
2794         uint16_t nb_tx_to_clean;
2795         uint32_t pkt_cnt;
2796
2797         /* Start free mbuf from the next of tx_tail */
2798         tx_last = txq->tx_tail;
2799         tx_id  = swr_ring[tx_last].next_id;
2800
2801         if (txq->nb_free == 0 && iavf_xmit_cleanup(txq))
2802                 return 0;
2803
2804         nb_tx_to_clean = txq->nb_free;
2805         nb_tx_free_last = txq->nb_free;
2806         if (!free_cnt)
2807                 free_cnt = txq->nb_tx_desc;
2808
2809         /* Loop through swr_ring to count the amount of
2810          * freeable mubfs and packets.
2811          */
2812         for (pkt_cnt = 0; pkt_cnt < free_cnt; ) {
2813                 for (i = 0; i < nb_tx_to_clean &&
2814                         pkt_cnt < free_cnt &&
2815                         tx_id != tx_last; i++) {
2816                         if (swr_ring[tx_id].mbuf != NULL) {
2817                                 rte_pktmbuf_free_seg(swr_ring[tx_id].mbuf);
2818                                 swr_ring[tx_id].mbuf = NULL;
2819
2820                                 /*
2821                                  * last segment in the packet,
2822                                  * increment packet count
2823                                  */
2824                                 pkt_cnt += (swr_ring[tx_id].last_id == tx_id);
2825                         }
2826
2827                         tx_id = swr_ring[tx_id].next_id;
2828                 }
2829
2830                 if (txq->rs_thresh > txq->nb_tx_desc -
2831                         txq->nb_free || tx_id == tx_last)
2832                         break;
2833
2834                 if (pkt_cnt < free_cnt) {
2835                         if (iavf_xmit_cleanup(txq))
2836                                 break;
2837
2838                         nb_tx_to_clean = txq->nb_free - nb_tx_free_last;
2839                         nb_tx_free_last = txq->nb_free;
2840                 }
2841         }
2842
2843         return (int)pkt_cnt;
2844 }
2845
2846 int
2847 iavf_dev_tx_done_cleanup(void *txq, uint32_t free_cnt)
2848 {
2849         struct iavf_tx_queue *q = (struct iavf_tx_queue *)txq;
2850
2851         return iavf_tx_done_cleanup_full(q, free_cnt);
2852 }
2853
2854 void
2855 iavf_dev_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2856                      struct rte_eth_rxq_info *qinfo)
2857 {
2858         struct iavf_rx_queue *rxq;
2859
2860         rxq = dev->data->rx_queues[queue_id];
2861
2862         qinfo->mp = rxq->mp;
2863         qinfo->scattered_rx = dev->data->scattered_rx;
2864         qinfo->nb_desc = rxq->nb_rx_desc;
2865
2866         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2867         qinfo->conf.rx_drop_en = true;
2868         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2869 }
2870
2871 void
2872 iavf_dev_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2873                      struct rte_eth_txq_info *qinfo)
2874 {
2875         struct iavf_tx_queue *txq;
2876
2877         txq = dev->data->tx_queues[queue_id];
2878
2879         qinfo->nb_desc = txq->nb_tx_desc;
2880
2881         qinfo->conf.tx_free_thresh = txq->free_thresh;
2882         qinfo->conf.tx_rs_thresh = txq->rs_thresh;
2883         qinfo->conf.offloads = txq->offloads;
2884         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2885 }
2886
2887 /* Get the number of used descriptors of a rx queue */
2888 uint32_t
2889 iavf_dev_rxq_count(void *rx_queue)
2890 {
2891 #define IAVF_RXQ_SCAN_INTERVAL 4
2892         volatile union iavf_rx_desc *rxdp;
2893         struct iavf_rx_queue *rxq;
2894         uint16_t desc = 0;
2895
2896         rxq = rx_queue;
2897         rxdp = &rxq->rx_ring[rxq->rx_tail];
2898
2899         while ((desc < rxq->nb_rx_desc) &&
2900                ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
2901                  IAVF_RXD_QW1_STATUS_MASK) >> IAVF_RXD_QW1_STATUS_SHIFT) &
2902                (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)) {
2903                 /* Check the DD bit of a rx descriptor of each 4 in a group,
2904                  * to avoid checking too frequently and downgrading performance
2905                  * too much.
2906                  */
2907                 desc += IAVF_RXQ_SCAN_INTERVAL;
2908                 rxdp += IAVF_RXQ_SCAN_INTERVAL;
2909                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
2910                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
2911                                         desc - rxq->nb_rx_desc]);
2912         }
2913
2914         return desc;
2915 }
2916
2917 int
2918 iavf_dev_rx_desc_status(void *rx_queue, uint16_t offset)
2919 {
2920         struct iavf_rx_queue *rxq = rx_queue;
2921         volatile uint64_t *status;
2922         uint64_t mask;
2923         uint32_t desc;
2924
2925         if (unlikely(offset >= rxq->nb_rx_desc))
2926                 return -EINVAL;
2927
2928         if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
2929                 return RTE_ETH_RX_DESC_UNAVAIL;
2930
2931         desc = rxq->rx_tail + offset;
2932         if (desc >= rxq->nb_rx_desc)
2933                 desc -= rxq->nb_rx_desc;
2934
2935         status = &rxq->rx_ring[desc].wb.qword1.status_error_len;
2936         mask = rte_le_to_cpu_64((1ULL << IAVF_RX_DESC_STATUS_DD_SHIFT)
2937                 << IAVF_RXD_QW1_STATUS_SHIFT);
2938         if (*status & mask)
2939                 return RTE_ETH_RX_DESC_DONE;
2940
2941         return RTE_ETH_RX_DESC_AVAIL;
2942 }
2943
2944 int
2945 iavf_dev_tx_desc_status(void *tx_queue, uint16_t offset)
2946 {
2947         struct iavf_tx_queue *txq = tx_queue;
2948         volatile uint64_t *status;
2949         uint64_t mask, expect;
2950         uint32_t desc;
2951
2952         if (unlikely(offset >= txq->nb_tx_desc))
2953                 return -EINVAL;
2954
2955         desc = txq->tx_tail + offset;
2956         /* go to next desc that has the RS bit */
2957         desc = ((desc + txq->rs_thresh - 1) / txq->rs_thresh) *
2958                 txq->rs_thresh;
2959         if (desc >= txq->nb_tx_desc) {
2960                 desc -= txq->nb_tx_desc;
2961                 if (desc >= txq->nb_tx_desc)
2962                         desc -= txq->nb_tx_desc;
2963         }
2964
2965         status = &txq->tx_ring[desc].cmd_type_offset_bsz;
2966         mask = rte_le_to_cpu_64(IAVF_TXD_QW1_DTYPE_MASK);
2967         expect = rte_cpu_to_le_64(
2968                  IAVF_TX_DESC_DTYPE_DESC_DONE << IAVF_TXD_QW1_DTYPE_SHIFT);
2969         if ((*status & mask) == expect)
2970                 return RTE_ETH_TX_DESC_DONE;
2971
2972         return RTE_ETH_TX_DESC_FULL;
2973 }
2974
2975 static inline uint32_t
2976 iavf_get_default_ptype(uint16_t ptype)
2977 {
2978         static const uint32_t ptype_tbl[IAVF_MAX_PKT_TYPE]
2979                 __rte_cache_aligned = {
2980                 /* L2 types */
2981                 /* [0] reserved */
2982                 [1] = RTE_PTYPE_L2_ETHER,
2983                 [2] = RTE_PTYPE_L2_ETHER_TIMESYNC,
2984                 /* [3] - [5] reserved */
2985                 [6] = RTE_PTYPE_L2_ETHER_LLDP,
2986                 /* [7] - [10] reserved */
2987                 [11] = RTE_PTYPE_L2_ETHER_ARP,
2988                 /* [12] - [21] reserved */
2989
2990                 /* Non tunneled IPv4 */
2991                 [22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2992                        RTE_PTYPE_L4_FRAG,
2993                 [23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2994                        RTE_PTYPE_L4_NONFRAG,
2995                 [24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2996                        RTE_PTYPE_L4_UDP,
2997                 /* [25] reserved */
2998                 [26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2999                        RTE_PTYPE_L4_TCP,
3000                 [27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3001                        RTE_PTYPE_L4_SCTP,
3002                 [28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3003                        RTE_PTYPE_L4_ICMP,
3004
3005                 /* IPv4 --> IPv4 */
3006                 [29] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3007                        RTE_PTYPE_TUNNEL_IP |
3008                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3009                        RTE_PTYPE_INNER_L4_FRAG,
3010                 [30] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3011                        RTE_PTYPE_TUNNEL_IP |
3012                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3013                        RTE_PTYPE_INNER_L4_NONFRAG,
3014                 [31] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3015                        RTE_PTYPE_TUNNEL_IP |
3016                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3017                        RTE_PTYPE_INNER_L4_UDP,
3018                 /* [32] reserved */
3019                 [33] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3020                        RTE_PTYPE_TUNNEL_IP |
3021                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3022                        RTE_PTYPE_INNER_L4_TCP,
3023                 [34] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3024                        RTE_PTYPE_TUNNEL_IP |
3025                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3026                        RTE_PTYPE_INNER_L4_SCTP,
3027                 [35] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3028                        RTE_PTYPE_TUNNEL_IP |
3029                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3030                        RTE_PTYPE_INNER_L4_ICMP,
3031
3032                 /* IPv4 --> IPv6 */
3033                 [36] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3034                        RTE_PTYPE_TUNNEL_IP |
3035                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3036                        RTE_PTYPE_INNER_L4_FRAG,
3037                 [37] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3038                        RTE_PTYPE_TUNNEL_IP |
3039                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3040                        RTE_PTYPE_INNER_L4_NONFRAG,
3041                 [38] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3042                        RTE_PTYPE_TUNNEL_IP |
3043                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3044                        RTE_PTYPE_INNER_L4_UDP,
3045                 /* [39] reserved */
3046                 [40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3047                        RTE_PTYPE_TUNNEL_IP |
3048                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3049                        RTE_PTYPE_INNER_L4_TCP,
3050                 [41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3051                        RTE_PTYPE_TUNNEL_IP |
3052                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3053                        RTE_PTYPE_INNER_L4_SCTP,
3054                 [42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3055                        RTE_PTYPE_TUNNEL_IP |
3056                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3057                        RTE_PTYPE_INNER_L4_ICMP,
3058
3059                 /* IPv4 --> GRE/Teredo/VXLAN */
3060                 [43] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3061                        RTE_PTYPE_TUNNEL_GRENAT,
3062
3063                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv4 */
3064                 [44] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3065                        RTE_PTYPE_TUNNEL_GRENAT |
3066                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3067                        RTE_PTYPE_INNER_L4_FRAG,
3068                 [45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3069                        RTE_PTYPE_TUNNEL_GRENAT |
3070                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3071                        RTE_PTYPE_INNER_L4_NONFRAG,
3072                 [46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3073                        RTE_PTYPE_TUNNEL_GRENAT |
3074                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3075                        RTE_PTYPE_INNER_L4_UDP,
3076                 /* [47] reserved */
3077                 [48] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3078                        RTE_PTYPE_TUNNEL_GRENAT |
3079                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3080                        RTE_PTYPE_INNER_L4_TCP,
3081                 [49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3082                        RTE_PTYPE_TUNNEL_GRENAT |
3083                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3084                        RTE_PTYPE_INNER_L4_SCTP,
3085                 [50] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3086                        RTE_PTYPE_TUNNEL_GRENAT |
3087                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3088                        RTE_PTYPE_INNER_L4_ICMP,
3089
3090                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv6 */
3091                 [51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3092                        RTE_PTYPE_TUNNEL_GRENAT |
3093                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3094                        RTE_PTYPE_INNER_L4_FRAG,
3095                 [52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3096                        RTE_PTYPE_TUNNEL_GRENAT |
3097                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3098                        RTE_PTYPE_INNER_L4_NONFRAG,
3099                 [53] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3100                        RTE_PTYPE_TUNNEL_GRENAT |
3101                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3102                        RTE_PTYPE_INNER_L4_UDP,
3103                 /* [54] reserved */
3104                 [55] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3105                        RTE_PTYPE_TUNNEL_GRENAT |
3106                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3107                        RTE_PTYPE_INNER_L4_TCP,
3108                 [56] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3109                        RTE_PTYPE_TUNNEL_GRENAT |
3110                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3111                        RTE_PTYPE_INNER_L4_SCTP,
3112                 [57] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3113                        RTE_PTYPE_TUNNEL_GRENAT |
3114                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3115                        RTE_PTYPE_INNER_L4_ICMP,
3116
3117                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC */
3118                 [58] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3119                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
3120
3121                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
3122                 [59] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3123                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3124                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3125                        RTE_PTYPE_INNER_L4_FRAG,
3126                 [60] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3127                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3128                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3129                        RTE_PTYPE_INNER_L4_NONFRAG,
3130                 [61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3131                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3132                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3133                        RTE_PTYPE_INNER_L4_UDP,
3134                 /* [62] reserved */
3135                 [63] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3136                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3137                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3138                        RTE_PTYPE_INNER_L4_TCP,
3139                 [64] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3140                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3141                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3142                        RTE_PTYPE_INNER_L4_SCTP,
3143                 [65] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3144                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3145                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3146                        RTE_PTYPE_INNER_L4_ICMP,
3147
3148                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
3149                 [66] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3150                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3151                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3152                        RTE_PTYPE_INNER_L4_FRAG,
3153                 [67] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3154                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3155                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3156                        RTE_PTYPE_INNER_L4_NONFRAG,
3157                 [68] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3158                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3159                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3160                        RTE_PTYPE_INNER_L4_UDP,
3161                 /* [69] reserved */
3162                 [70] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3163                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3164                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3165                        RTE_PTYPE_INNER_L4_TCP,
3166                 [71] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3167                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3168                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3169                        RTE_PTYPE_INNER_L4_SCTP,
3170                 [72] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3171                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3172                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3173                        RTE_PTYPE_INNER_L4_ICMP,
3174                 /* [73] - [87] reserved */
3175
3176                 /* Non tunneled IPv6 */
3177                 [88] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3178                        RTE_PTYPE_L4_FRAG,
3179                 [89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3180                        RTE_PTYPE_L4_NONFRAG,
3181                 [90] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3182                        RTE_PTYPE_L4_UDP,
3183                 /* [91] reserved */
3184                 [92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3185                        RTE_PTYPE_L4_TCP,
3186                 [93] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3187                        RTE_PTYPE_L4_SCTP,
3188                 [94] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3189                        RTE_PTYPE_L4_ICMP,
3190
3191                 /* IPv6 --> IPv4 */
3192                 [95] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3193                        RTE_PTYPE_TUNNEL_IP |
3194                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3195                        RTE_PTYPE_INNER_L4_FRAG,
3196                 [96] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3197                        RTE_PTYPE_TUNNEL_IP |
3198                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3199                        RTE_PTYPE_INNER_L4_NONFRAG,
3200                 [97] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3201                        RTE_PTYPE_TUNNEL_IP |
3202                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3203                        RTE_PTYPE_INNER_L4_UDP,
3204                 /* [98] reserved */
3205                 [99] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3206                        RTE_PTYPE_TUNNEL_IP |
3207                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3208                        RTE_PTYPE_INNER_L4_TCP,
3209                 [100] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3210                         RTE_PTYPE_TUNNEL_IP |
3211                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3212                         RTE_PTYPE_INNER_L4_SCTP,
3213                 [101] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3214                         RTE_PTYPE_TUNNEL_IP |
3215                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3216                         RTE_PTYPE_INNER_L4_ICMP,
3217
3218                 /* IPv6 --> IPv6 */
3219                 [102] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3220                         RTE_PTYPE_TUNNEL_IP |
3221                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3222                         RTE_PTYPE_INNER_L4_FRAG,
3223                 [103] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3224                         RTE_PTYPE_TUNNEL_IP |
3225                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3226                         RTE_PTYPE_INNER_L4_NONFRAG,
3227                 [104] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3228                         RTE_PTYPE_TUNNEL_IP |
3229                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3230                         RTE_PTYPE_INNER_L4_UDP,
3231                 /* [105] reserved */
3232                 [106] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3233                         RTE_PTYPE_TUNNEL_IP |
3234                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3235                         RTE_PTYPE_INNER_L4_TCP,
3236                 [107] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3237                         RTE_PTYPE_TUNNEL_IP |
3238                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3239                         RTE_PTYPE_INNER_L4_SCTP,
3240                 [108] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3241                         RTE_PTYPE_TUNNEL_IP |
3242                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3243                         RTE_PTYPE_INNER_L4_ICMP,
3244
3245                 /* IPv6 --> GRE/Teredo/VXLAN */
3246                 [109] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3247                         RTE_PTYPE_TUNNEL_GRENAT,
3248
3249                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv4 */
3250                 [110] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3251                         RTE_PTYPE_TUNNEL_GRENAT |
3252                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3253                         RTE_PTYPE_INNER_L4_FRAG,
3254                 [111] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3255                         RTE_PTYPE_TUNNEL_GRENAT |
3256                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3257                         RTE_PTYPE_INNER_L4_NONFRAG,
3258                 [112] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3259                         RTE_PTYPE_TUNNEL_GRENAT |
3260                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3261                         RTE_PTYPE_INNER_L4_UDP,
3262                 /* [113] reserved */
3263                 [114] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3264                         RTE_PTYPE_TUNNEL_GRENAT |
3265                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3266                         RTE_PTYPE_INNER_L4_TCP,
3267                 [115] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3268                         RTE_PTYPE_TUNNEL_GRENAT |
3269                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3270                         RTE_PTYPE_INNER_L4_SCTP,
3271                 [116] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3272                         RTE_PTYPE_TUNNEL_GRENAT |
3273                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3274                         RTE_PTYPE_INNER_L4_ICMP,
3275
3276                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv6 */
3277                 [117] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3278                         RTE_PTYPE_TUNNEL_GRENAT |
3279                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3280                         RTE_PTYPE_INNER_L4_FRAG,
3281                 [118] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3282                         RTE_PTYPE_TUNNEL_GRENAT |
3283                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3284                         RTE_PTYPE_INNER_L4_NONFRAG,
3285                 [119] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3286                         RTE_PTYPE_TUNNEL_GRENAT |
3287                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3288                         RTE_PTYPE_INNER_L4_UDP,
3289                 /* [120] reserved */
3290                 [121] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3291                         RTE_PTYPE_TUNNEL_GRENAT |
3292                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3293                         RTE_PTYPE_INNER_L4_TCP,
3294                 [122] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3295                         RTE_PTYPE_TUNNEL_GRENAT |
3296                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3297                         RTE_PTYPE_INNER_L4_SCTP,
3298                 [123] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3299                         RTE_PTYPE_TUNNEL_GRENAT |
3300                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3301                         RTE_PTYPE_INNER_L4_ICMP,
3302
3303                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC */
3304                 [124] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3305                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
3306
3307                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
3308                 [125] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3309                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3310                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3311                         RTE_PTYPE_INNER_L4_FRAG,
3312                 [126] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3313                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3314                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3315                         RTE_PTYPE_INNER_L4_NONFRAG,
3316                 [127] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3317                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3318                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3319                         RTE_PTYPE_INNER_L4_UDP,
3320                 /* [128] reserved */
3321                 [129] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3322                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3323                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3324                         RTE_PTYPE_INNER_L4_TCP,
3325                 [130] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3326                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3327                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3328                         RTE_PTYPE_INNER_L4_SCTP,
3329                 [131] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3330                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3331                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3332                         RTE_PTYPE_INNER_L4_ICMP,
3333
3334                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
3335                 [132] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3336                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3337                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3338                         RTE_PTYPE_INNER_L4_FRAG,
3339                 [133] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3340                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3341                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3342                         RTE_PTYPE_INNER_L4_NONFRAG,
3343                 [134] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3344                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3345                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3346                         RTE_PTYPE_INNER_L4_UDP,
3347                 /* [135] reserved */
3348                 [136] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3349                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3350                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3351                         RTE_PTYPE_INNER_L4_TCP,
3352                 [137] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3353                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3354                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3355                         RTE_PTYPE_INNER_L4_SCTP,
3356                 [138] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3357                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3358                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3359                         RTE_PTYPE_INNER_L4_ICMP,
3360                 /* [139] - [299] reserved */
3361
3362                 /* PPPoE */
3363                 [300] = RTE_PTYPE_L2_ETHER_PPPOE,
3364                 [301] = RTE_PTYPE_L2_ETHER_PPPOE,
3365
3366                 /* PPPoE --> IPv4 */
3367                 [302] = RTE_PTYPE_L2_ETHER_PPPOE |
3368                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3369                         RTE_PTYPE_L4_FRAG,
3370                 [303] = RTE_PTYPE_L2_ETHER_PPPOE |
3371                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3372                         RTE_PTYPE_L4_NONFRAG,
3373                 [304] = RTE_PTYPE_L2_ETHER_PPPOE |
3374                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3375                         RTE_PTYPE_L4_UDP,
3376                 [305] = RTE_PTYPE_L2_ETHER_PPPOE |
3377                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3378                         RTE_PTYPE_L4_TCP,
3379                 [306] = RTE_PTYPE_L2_ETHER_PPPOE |
3380                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3381                         RTE_PTYPE_L4_SCTP,
3382                 [307] = RTE_PTYPE_L2_ETHER_PPPOE |
3383                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3384                         RTE_PTYPE_L4_ICMP,
3385
3386                 /* PPPoE --> IPv6 */
3387                 [308] = RTE_PTYPE_L2_ETHER_PPPOE |
3388                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3389                         RTE_PTYPE_L4_FRAG,
3390                 [309] = RTE_PTYPE_L2_ETHER_PPPOE |
3391                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3392                         RTE_PTYPE_L4_NONFRAG,
3393                 [310] = RTE_PTYPE_L2_ETHER_PPPOE |
3394                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3395                         RTE_PTYPE_L4_UDP,
3396                 [311] = RTE_PTYPE_L2_ETHER_PPPOE |
3397                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3398                         RTE_PTYPE_L4_TCP,
3399                 [312] = RTE_PTYPE_L2_ETHER_PPPOE |
3400                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3401                         RTE_PTYPE_L4_SCTP,
3402                 [313] = RTE_PTYPE_L2_ETHER_PPPOE |
3403                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3404                         RTE_PTYPE_L4_ICMP,
3405                 /* [314] - [324] reserved */
3406
3407                 /* IPv4/IPv6 --> GTPC/GTPU */
3408                 [325] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3409                         RTE_PTYPE_TUNNEL_GTPC,
3410                 [326] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3411                         RTE_PTYPE_TUNNEL_GTPC,
3412                 [327] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3413                         RTE_PTYPE_TUNNEL_GTPC,
3414                 [328] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3415                         RTE_PTYPE_TUNNEL_GTPC,
3416                 [329] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3417                         RTE_PTYPE_TUNNEL_GTPU,
3418                 [330] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3419                         RTE_PTYPE_TUNNEL_GTPU,
3420
3421                 /* IPv4 --> GTPU --> IPv4 */
3422                 [331] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3423                         RTE_PTYPE_TUNNEL_GTPU |
3424                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3425                         RTE_PTYPE_INNER_L4_FRAG,
3426                 [332] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3427                         RTE_PTYPE_TUNNEL_GTPU |
3428                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3429                         RTE_PTYPE_INNER_L4_NONFRAG,
3430                 [333] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3431                         RTE_PTYPE_TUNNEL_GTPU |
3432                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3433                         RTE_PTYPE_INNER_L4_UDP,
3434                 [334] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3435                         RTE_PTYPE_TUNNEL_GTPU |
3436                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3437                         RTE_PTYPE_INNER_L4_TCP,
3438                 [335] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3439                         RTE_PTYPE_TUNNEL_GTPU |
3440                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3441                         RTE_PTYPE_INNER_L4_ICMP,
3442
3443                 /* IPv6 --> GTPU --> IPv4 */
3444                 [336] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3445                         RTE_PTYPE_TUNNEL_GTPU |
3446                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3447                         RTE_PTYPE_INNER_L4_FRAG,
3448                 [337] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3449                         RTE_PTYPE_TUNNEL_GTPU |
3450                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3451                         RTE_PTYPE_INNER_L4_NONFRAG,
3452                 [338] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3453                         RTE_PTYPE_TUNNEL_GTPU |
3454                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3455                         RTE_PTYPE_INNER_L4_UDP,
3456                 [339] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3457                         RTE_PTYPE_TUNNEL_GTPU |
3458                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3459                         RTE_PTYPE_INNER_L4_TCP,
3460                 [340] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3461                         RTE_PTYPE_TUNNEL_GTPU |
3462                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3463                         RTE_PTYPE_INNER_L4_ICMP,
3464
3465                 /* IPv4 --> GTPU --> IPv6 */
3466                 [341] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3467                         RTE_PTYPE_TUNNEL_GTPU |
3468                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3469                         RTE_PTYPE_INNER_L4_FRAG,
3470                 [342] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3471                         RTE_PTYPE_TUNNEL_GTPU |
3472                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3473                         RTE_PTYPE_INNER_L4_NONFRAG,
3474                 [343] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3475                         RTE_PTYPE_TUNNEL_GTPU |
3476                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3477                         RTE_PTYPE_INNER_L4_UDP,
3478                 [344] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3479                         RTE_PTYPE_TUNNEL_GTPU |
3480                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3481                         RTE_PTYPE_INNER_L4_TCP,
3482                 [345] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3483                         RTE_PTYPE_TUNNEL_GTPU |
3484                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3485                         RTE_PTYPE_INNER_L4_ICMP,
3486
3487                 /* IPv6 --> GTPU --> IPv6 */
3488                 [346] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3489                         RTE_PTYPE_TUNNEL_GTPU |
3490                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3491                         RTE_PTYPE_INNER_L4_FRAG,
3492                 [347] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3493                         RTE_PTYPE_TUNNEL_GTPU |
3494                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3495                         RTE_PTYPE_INNER_L4_NONFRAG,
3496                 [348] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3497                         RTE_PTYPE_TUNNEL_GTPU |
3498                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3499                         RTE_PTYPE_INNER_L4_UDP,
3500                 [349] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3501                         RTE_PTYPE_TUNNEL_GTPU |
3502                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3503                         RTE_PTYPE_INNER_L4_TCP,
3504                 [350] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3505                         RTE_PTYPE_TUNNEL_GTPU |
3506                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3507                         RTE_PTYPE_INNER_L4_ICMP,
3508
3509                 /* IPv4 --> UDP ECPRI */
3510                 [372] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3511                         RTE_PTYPE_L4_UDP,
3512                 [373] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3513                         RTE_PTYPE_L4_UDP,
3514                 [374] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3515                         RTE_PTYPE_L4_UDP,
3516                 [375] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3517                         RTE_PTYPE_L4_UDP,
3518                 [376] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3519                         RTE_PTYPE_L4_UDP,
3520                 [377] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3521                         RTE_PTYPE_L4_UDP,
3522                 [378] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3523                         RTE_PTYPE_L4_UDP,
3524                 [379] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3525                         RTE_PTYPE_L4_UDP,
3526                 [380] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3527                         RTE_PTYPE_L4_UDP,
3528                 [381] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3529                         RTE_PTYPE_L4_UDP,
3530
3531                 /* IPV6 --> UDP ECPRI */
3532                 [382] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3533                         RTE_PTYPE_L4_UDP,
3534                 [383] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3535                         RTE_PTYPE_L4_UDP,
3536                 [384] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3537                         RTE_PTYPE_L4_UDP,
3538                 [385] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3539                         RTE_PTYPE_L4_UDP,
3540                 [386] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3541                         RTE_PTYPE_L4_UDP,
3542                 [387] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3543                         RTE_PTYPE_L4_UDP,
3544                 [388] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3545                         RTE_PTYPE_L4_UDP,
3546                 [389] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3547                         RTE_PTYPE_L4_UDP,
3548                 [390] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3549                         RTE_PTYPE_L4_UDP,
3550                 [391] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3551                         RTE_PTYPE_L4_UDP,
3552                 /* All others reserved */
3553         };
3554
3555         return ptype_tbl[ptype];
3556 }
3557
3558 void __rte_cold
3559 iavf_set_default_ptype_table(struct rte_eth_dev *dev)
3560 {
3561         struct iavf_adapter *ad =
3562                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3563         int i;
3564
3565         for (i = 0; i < IAVF_MAX_PKT_TYPE; i++)
3566                 ad->ptype_tbl[i] = iavf_get_default_ptype(i);
3567 }