drivers/net/iavf/iavf_rxtx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2017 Intel Corporation
   3  */
   4
   5 #include <stdio.h>
   6 #include <stdlib.h>
   7 #include <string.h>
   8 #include <errno.h>
   9 #include <stdint.h>
  10 #include <stdarg.h>
  11 #include <unistd.h>
  12 #include <inttypes.h>
  13 #include <sys/queue.h>
  14
  15 #include <rte_string_fns.h>
  16 #include <rte_memzone.h>
  17 #include <rte_mbuf.h>
  18 #include <rte_malloc.h>
  19 #include <rte_ether.h>
  20 #include <ethdev_driver.h>
  21 #include <rte_tcp.h>
  22 #include <rte_sctp.h>
  23 #include <rte_udp.h>
  24 #include <rte_ip.h>
  25 #include <rte_net.h>
  26 #include <rte_vect.h>
  27
  28 #include "iavf.h"
  29 #include "iavf_rxtx.h"
  30 #include "iavf_ipsec_crypto.h"
  31 #include "rte_pmd_iavf.h"
  32
  33 /* Offset of mbuf dynamic field for protocol extraction's metadata */
  34 int rte_pmd_ifd_dynfield_proto_xtr_metadata_offs = -1;
  35
  36 /* Mask of mbuf dynamic flags for protocol extraction's type */
  37 uint64_t rte_pmd_ifd_dynflag_proto_xtr_vlan_mask;
  38 uint64_t rte_pmd_ifd_dynflag_proto_xtr_ipv4_mask;
  39 uint64_t rte_pmd_ifd_dynflag_proto_xtr_ipv6_mask;
  40 uint64_t rte_pmd_ifd_dynflag_proto_xtr_ipv6_flow_mask;
  41 uint64_t rte_pmd_ifd_dynflag_proto_xtr_tcp_mask;
  42 uint64_t rte_pmd_ifd_dynflag_proto_xtr_ip_offset_mask;
  43 uint64_t rte_pmd_ifd_dynflag_proto_xtr_ipsec_crypto_said_mask;
  44
  45 uint8_t
  46 iavf_proto_xtr_type_to_rxdid(uint8_t flex_type)
  47 {
  48         static uint8_t rxdid_map[] = {
  49                 [IAVF_PROTO_XTR_NONE]      = IAVF_RXDID_COMMS_OVS_1,
  50                 [IAVF_PROTO_XTR_VLAN]      = IAVF_RXDID_COMMS_AUX_VLAN,
  51                 [IAVF_PROTO_XTR_IPV4]      = IAVF_RXDID_COMMS_AUX_IPV4,
  52                 [IAVF_PROTO_XTR_IPV6]      = IAVF_RXDID_COMMS_AUX_IPV6,
  53                 [IAVF_PROTO_XTR_IPV6_FLOW] = IAVF_RXDID_COMMS_AUX_IPV6_FLOW,
  54                 [IAVF_PROTO_XTR_TCP]       = IAVF_RXDID_COMMS_AUX_TCP,
  55                 [IAVF_PROTO_XTR_IP_OFFSET] = IAVF_RXDID_COMMS_AUX_IP_OFFSET,
  56                 [IAVF_PROTO_XTR_IPSEC_CRYPTO_SAID] =
  57                                 IAVF_RXDID_COMMS_IPSEC_CRYPTO,
  58         };
  59
  60         return flex_type < RTE_DIM(rxdid_map) ?
  61                                 rxdid_map[flex_type] : IAVF_RXDID_COMMS_OVS_1;
  62 }
  63
  64 static int
  65 iavf_monitor_callback(const uint64_t value,
  66                 const uint64_t arg[RTE_POWER_MONITOR_OPAQUE_SZ] __rte_unused)
  67 {
  68         const uint64_t m = rte_cpu_to_le_64(1 << IAVF_RX_DESC_STATUS_DD_SHIFT);
  69         /*
  70          * we expect the DD bit to be set to 1 if this descriptor was already
  71          * written to.
  72          */
  73         return (value & m) == m ? -1 : 0;
  74 }
  75
  76 int
  77 iavf_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc)
  78 {
  79         struct iavf_rx_queue *rxq = rx_queue;
  80         volatile union iavf_rx_desc *rxdp;
  81         uint16_t desc;
  82
  83         desc = rxq->rx_tail;
  84         rxdp = &rxq->rx_ring[desc];
  85         /* watch for changes in status bit */
  86         pmc->addr = &rxdp->wb.qword1.status_error_len;
  87
  88         /* comparison callback */
  89         pmc->fn = iavf_monitor_callback;
  90
  91         /* registers are 64-bit */
  92         pmc->size = sizeof(uint64_t);
  93
  94         return 0;
  95 }
  96
  97 static inline int
  98 check_rx_thresh(uint16_t nb_desc, uint16_t thresh)
  99 {
 100         /* The following constraints must be satisfied:
 101          *   thresh < rxq->nb_rx_desc
 102          */
 103         if (thresh >= nb_desc) {
 104                 PMD_INIT_LOG(ERR, "rx_free_thresh (%u) must be less than %u",
 105                              thresh, nb_desc);
 106                 return -EINVAL;
 107         }
 108         return 0;
 109 }
 110
 111 static inline int
 112 check_tx_thresh(uint16_t nb_desc, uint16_t tx_rs_thresh,
 113                 uint16_t tx_free_thresh)
 114 {
 115         /* TX descriptors will have their RS bit set after tx_rs_thresh
 116          * descriptors have been used. The TX descriptor ring will be cleaned
 117          * after tx_free_thresh descriptors are used or if the number of
 118          * descriptors required to transmit a packet is greater than the
 119          * number of free TX descriptors.
 120          *
 121          * The following constraints must be satisfied:
 122          *  - tx_rs_thresh must be less than the size of the ring minus 2.
 123          *  - tx_free_thresh must be less than the size of the ring minus 3.
 124          *  - tx_rs_thresh must be less than or equal to tx_free_thresh.
 125          *  - tx_rs_thresh must be a divisor of the ring size.
 126          *
 127          * One descriptor in the TX ring is used as a sentinel to avoid a H/W
 128          * race condition, hence the maximum threshold constraints. When set
 129          * to zero use default values.
 130          */
 131         if (tx_rs_thresh >= (nb_desc - 2)) {
 132                 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be less than the "
 133                              "number of TX descriptors (%u) minus 2",
 134                              tx_rs_thresh, nb_desc);
 135                 return -EINVAL;
 136         }
 137         if (tx_free_thresh >= (nb_desc - 3)) {
 138                 PMD_INIT_LOG(ERR, "tx_free_thresh (%u) must be less than the "
 139                              "number of TX descriptors (%u) minus 3.",
 140                              tx_free_thresh, nb_desc);
 141                 return -EINVAL;
 142         }
 143         if (tx_rs_thresh > tx_free_thresh) {
 144                 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be less than or "
 145                              "equal to tx_free_thresh (%u).",
 146                              tx_rs_thresh, tx_free_thresh);
 147                 return -EINVAL;
 148         }
 149         if ((nb_desc % tx_rs_thresh) != 0) {
 150                 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be a divisor of the "
 151                              "number of TX descriptors (%u).",
 152                              tx_rs_thresh, nb_desc);
 153                 return -EINVAL;
 154         }
 155
 156         return 0;
 157 }
 158
 159 static inline bool
 160 check_rx_vec_allow(struct iavf_rx_queue *rxq)
 161 {
 162         if (rxq->rx_free_thresh >= IAVF_VPMD_RX_MAX_BURST &&
 163             rxq->nb_rx_desc % rxq->rx_free_thresh == 0) {
 164                 PMD_INIT_LOG(DEBUG, "Vector Rx can be enabled on this rxq.");
 165                 return true;
 166         }
 167
 168         PMD_INIT_LOG(DEBUG, "Vector Rx cannot be enabled on this rxq.");
 169         return false;
 170 }
 171
 172 static inline bool
 173 check_tx_vec_allow(struct iavf_tx_queue *txq)
 174 {
 175         if (!(txq->offloads & IAVF_TX_NO_VECTOR_FLAGS) &&
 176             txq->rs_thresh >= IAVF_VPMD_TX_MAX_BURST &&
 177             txq->rs_thresh <= IAVF_VPMD_TX_MAX_FREE_BUF) {
 178                 PMD_INIT_LOG(DEBUG, "Vector tx can be enabled on this txq.");
 179                 return true;
 180         }
 181         PMD_INIT_LOG(DEBUG, "Vector Tx cannot be enabled on this txq.");
 182         return false;
 183 }
 184
 185 static inline bool
 186 check_rx_bulk_allow(struct iavf_rx_queue *rxq)
 187 {
 188         int ret = true;
 189
 190         if (!(rxq->rx_free_thresh >= IAVF_RX_MAX_BURST)) {
 191                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 192                              "rxq->rx_free_thresh=%d, "
 193                              "IAVF_RX_MAX_BURST=%d",
 194                              rxq->rx_free_thresh, IAVF_RX_MAX_BURST);
 195                 ret = false;
 196         } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
 197                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 198                              "rxq->nb_rx_desc=%d, "
 199                              "rxq->rx_free_thresh=%d",
 200                              rxq->nb_rx_desc, rxq->rx_free_thresh);
 201                 ret = false;
 202         }
 203         return ret;
 204 }
 205
 206 static inline void
 207 reset_rx_queue(struct iavf_rx_queue *rxq)
 208 {
 209         uint16_t len;
 210         uint32_t i;
 211
 212         if (!rxq)
 213                 return;
 214
 215         len = rxq->nb_rx_desc + IAVF_RX_MAX_BURST;
 216
 217         for (i = 0; i < len * sizeof(union iavf_rx_desc); i++)
 218                 ((volatile char *)rxq->rx_ring)[i] = 0;
 219
 220         memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
 221
 222         for (i = 0; i < IAVF_RX_MAX_BURST; i++)
 223                 rxq->sw_ring[rxq->nb_rx_desc + i] = &rxq->fake_mbuf;
 224
 225         /* for rx bulk */
 226         rxq->rx_nb_avail = 0;
 227         rxq->rx_next_avail = 0;
 228         rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
 229
 230         rxq->rx_tail = 0;
 231         rxq->nb_rx_hold = 0;
 232
 233         rte_pktmbuf_free(rxq->pkt_first_seg);
 234
 235         rxq->pkt_first_seg = NULL;
 236         rxq->pkt_last_seg = NULL;
 237         rxq->rxrearm_nb = 0;
 238         rxq->rxrearm_start = 0;
 239 }
 240
 241 static inline void
 242 reset_tx_queue(struct iavf_tx_queue *txq)
 243 {
 244         struct iavf_tx_entry *txe;
 245         uint32_t i, size;
 246         uint16_t prev;
 247
 248         if (!txq) {
 249                 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
 250                 return;
 251         }
 252
 253         txe = txq->sw_ring;
 254         size = sizeof(struct iavf_tx_desc) * txq->nb_tx_desc;
 255         for (i = 0; i < size; i++)
 256                 ((volatile char *)txq->tx_ring)[i] = 0;
 257
 258         prev = (uint16_t)(txq->nb_tx_desc - 1);
 259         for (i = 0; i < txq->nb_tx_desc; i++) {
 260                 txq->tx_ring[i].cmd_type_offset_bsz =
 261                         rte_cpu_to_le_64(IAVF_TX_DESC_DTYPE_DESC_DONE);
 262                 txe[i].mbuf =  NULL;
 263                 txe[i].last_id = i;
 264                 txe[prev].next_id = i;
 265                 prev = i;
 266         }
 267
 268         txq->tx_tail = 0;
 269         txq->nb_used = 0;
 270
 271         txq->last_desc_cleaned = txq->nb_tx_desc - 1;
 272         txq->nb_free = txq->nb_tx_desc - 1;
 273
 274         txq->next_dd = txq->rs_thresh - 1;
 275         txq->next_rs = txq->rs_thresh - 1;
 276 }
 277
 278 static int
 279 alloc_rxq_mbufs(struct iavf_rx_queue *rxq)
 280 {
 281         volatile union iavf_rx_desc *rxd;
 282         struct rte_mbuf *mbuf = NULL;
 283         uint64_t dma_addr;
 284         uint16_t i, j;
 285
 286         for (i = 0; i < rxq->nb_rx_desc; i++) {
 287                 mbuf = rte_mbuf_raw_alloc(rxq->mp);
 288                 if (unlikely(!mbuf)) {
 289                         for (j = 0; j < i; j++) {
 290                                 rte_pktmbuf_free_seg(rxq->sw_ring[j]);
 291                                 rxq->sw_ring[j] = NULL;
 292                         }
 293                         PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
 294                         return -ENOMEM;
 295                 }
 296
 297                 rte_mbuf_refcnt_set(mbuf, 1);
 298                 mbuf->next = NULL;
 299                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
 300                 mbuf->nb_segs = 1;
 301                 mbuf->port = rxq->port_id;
 302
 303                 dma_addr =
 304                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
 305
 306                 rxd = &rxq->rx_ring[i];
 307                 rxd->read.pkt_addr = dma_addr;
 308                 rxd->read.hdr_addr = 0;
 309 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
 310                 rxd->read.rsvd1 = 0;
 311                 rxd->read.rsvd2 = 0;
 312 #endif
 313
 314                 rxq->sw_ring[i] = mbuf;
 315         }
 316
 317         return 0;
 318 }
 319
 320 static inline void
 321 release_rxq_mbufs(struct iavf_rx_queue *rxq)
 322 {
 323         uint16_t i;
 324
 325         if (!rxq->sw_ring)
 326                 return;
 327
 328         for (i = 0; i < rxq->nb_rx_desc; i++) {
 329                 if (rxq->sw_ring[i]) {
 330                         rte_pktmbuf_free_seg(rxq->sw_ring[i]);
 331                         rxq->sw_ring[i] = NULL;
 332                 }
 333         }
 334
 335         /* for rx bulk */
 336         if (rxq->rx_nb_avail == 0)
 337                 return;
 338         for (i = 0; i < rxq->rx_nb_avail; i++) {
 339                 struct rte_mbuf *mbuf;
 340
 341                 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
 342                 rte_pktmbuf_free_seg(mbuf);
 343         }
 344         rxq->rx_nb_avail = 0;
 345 }
 346
 347 static inline void
 348 release_txq_mbufs(struct iavf_tx_queue *txq)
 349 {
 350         uint16_t i;
 351
 352         if (!txq || !txq->sw_ring) {
 353                 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
 354                 return;
 355         }
 356
 357         for (i = 0; i < txq->nb_tx_desc; i++) {
 358                 if (txq->sw_ring[i].mbuf) {
 359                         rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
 360                         txq->sw_ring[i].mbuf = NULL;
 361                 }
 362         }
 363 }
 364
 365 static const struct iavf_rxq_ops def_rxq_ops = {
 366         .release_mbufs = release_rxq_mbufs,
 367 };
 368
 369 static const struct iavf_txq_ops def_txq_ops = {
 370         .release_mbufs = release_txq_mbufs,
 371 };
 372
 373 static inline void
 374 iavf_rxd_to_pkt_fields_by_comms_ovs(__rte_unused struct iavf_rx_queue *rxq,
 375                                     struct rte_mbuf *mb,
 376                                     volatile union iavf_rx_flex_desc *rxdp)
 377 {
 378         volatile struct iavf_32b_rx_flex_desc_comms_ovs *desc =
 379                         (volatile struct iavf_32b_rx_flex_desc_comms_ovs *)rxdp;
 380 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
 381         uint16_t stat_err;
 382 #endif
 383
 384         if (desc->flow_id != 0xFFFFFFFF) {
 385                 mb->ol_flags |= RTE_MBUF_F_RX_FDIR | RTE_MBUF_F_RX_FDIR_ID;
 386                 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
 387         }
 388
 389 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
 390         stat_err = rte_le_to_cpu_16(desc->status_error0);
 391         if (likely(stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
 392                 mb->ol_flags |= RTE_MBUF_F_RX_RSS_HASH;
 393                 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
 394         }
 395 #endif
 396 }
 397
 398 static inline void
 399 iavf_rxd_to_pkt_fields_by_comms_aux_v1(struct iavf_rx_queue *rxq,
 400                                        struct rte_mbuf *mb,
 401                                        volatile union iavf_rx_flex_desc *rxdp)
 402 {
 403         volatile struct iavf_32b_rx_flex_desc_comms *desc =
 404                         (volatile struct iavf_32b_rx_flex_desc_comms *)rxdp;
 405         uint16_t stat_err;
 406
 407         stat_err = rte_le_to_cpu_16(desc->status_error0);
 408         if (likely(stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
 409                 mb->ol_flags |= RTE_MBUF_F_RX_RSS_HASH;
 410                 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
 411         }
 412
 413 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
 414         if (desc->flow_id != 0xFFFFFFFF) {
 415                 mb->ol_flags |= RTE_MBUF_F_RX_FDIR | RTE_MBUF_F_RX_FDIR_ID;
 416                 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
 417         }
 418
 419         if (rxq->xtr_ol_flag) {
 420                 uint32_t metadata = 0;
 421
 422                 stat_err = rte_le_to_cpu_16(desc->status_error1);
 423
 424                 if (stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS1_XTRMD4_VALID_S))
 425                         metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux0);
 426
 427                 if (stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS1_XTRMD5_VALID_S))
 428                         metadata |=
 429                                 rte_le_to_cpu_16(desc->flex_ts.flex.aux1) << 16;
 430
 431                 if (metadata) {
 432                         mb->ol_flags |= rxq->xtr_ol_flag;
 433
 434                         *RTE_PMD_IFD_DYNF_PROTO_XTR_METADATA(mb) = metadata;
 435                 }
 436         }
 437 #endif
 438 }
 439
 440 static inline void
 441 iavf_rxd_to_pkt_fields_by_comms_aux_v2(struct iavf_rx_queue *rxq,
 442                                        struct rte_mbuf *mb,
 443                                        volatile union iavf_rx_flex_desc *rxdp)
 444 {
 445         volatile struct iavf_32b_rx_flex_desc_comms *desc =
 446                         (volatile struct iavf_32b_rx_flex_desc_comms *)rxdp;
 447         uint16_t stat_err;
 448
 449         stat_err = rte_le_to_cpu_16(desc->status_error0);
 450         if (likely(stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
 451                 mb->ol_flags |= RTE_MBUF_F_RX_RSS_HASH;
 452                 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
 453         }
 454
 455 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
 456         if (desc->flow_id != 0xFFFFFFFF) {
 457                 mb->ol_flags |= RTE_MBUF_F_RX_FDIR | RTE_MBUF_F_RX_FDIR_ID;
 458                 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
 459         }
 460
 461         if (rxq->xtr_ol_flag) {
 462                 uint32_t metadata = 0;
 463
 464                 if (desc->flex_ts.flex.aux0 != 0xFFFF)
 465                         metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux0);
 466                 else if (desc->flex_ts.flex.aux1 != 0xFFFF)
 467                         metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux1);
 468
 469                 if (metadata) {
 470                         mb->ol_flags |= rxq->xtr_ol_flag;
 471
 472                         *RTE_PMD_IFD_DYNF_PROTO_XTR_METADATA(mb) = metadata;
 473                 }
 474         }
 475 #endif
 476 }
 477
 478 static void
 479 iavf_select_rxd_to_pkt_fields_handler(struct iavf_rx_queue *rxq, uint32_t rxdid)
 480 {
 481         switch (rxdid) {
 482         case IAVF_RXDID_COMMS_AUX_VLAN:
 483                 rxq->xtr_ol_flag = rte_pmd_ifd_dynflag_proto_xtr_vlan_mask;
 484                 rxq->rxd_to_pkt_fields =
 485                         iavf_rxd_to_pkt_fields_by_comms_aux_v1;
 486                 break;
 487         case IAVF_RXDID_COMMS_AUX_IPV4:
 488                 rxq->xtr_ol_flag = rte_pmd_ifd_dynflag_proto_xtr_ipv4_mask;
 489                 rxq->rxd_to_pkt_fields =
 490                         iavf_rxd_to_pkt_fields_by_comms_aux_v1;
 491                 break;
 492         case IAVF_RXDID_COMMS_AUX_IPV6:
 493                 rxq->xtr_ol_flag = rte_pmd_ifd_dynflag_proto_xtr_ipv6_mask;
 494                 rxq->rxd_to_pkt_fields =
 495                         iavf_rxd_to_pkt_fields_by_comms_aux_v1;
 496                 break;
 497         case IAVF_RXDID_COMMS_AUX_IPV6_FLOW:
 498                 rxq->xtr_ol_flag =
 499                         rte_pmd_ifd_dynflag_proto_xtr_ipv6_flow_mask;
 500                 rxq->rxd_to_pkt_fields =
 501                         iavf_rxd_to_pkt_fields_by_comms_aux_v1;
 502                 break;
 503         case IAVF_RXDID_COMMS_AUX_TCP:
 504                 rxq->xtr_ol_flag = rte_pmd_ifd_dynflag_proto_xtr_tcp_mask;
 505                 rxq->rxd_to_pkt_fields =
 506                         iavf_rxd_to_pkt_fields_by_comms_aux_v1;
 507                 break;
 508         case IAVF_RXDID_COMMS_AUX_IP_OFFSET:
 509                 rxq->xtr_ol_flag =
 510                         rte_pmd_ifd_dynflag_proto_xtr_ip_offset_mask;
 511                 rxq->rxd_to_pkt_fields =
 512                         iavf_rxd_to_pkt_fields_by_comms_aux_v2;
 513                 break;
 514         case IAVF_RXDID_COMMS_IPSEC_CRYPTO:
 515                 rxq->xtr_ol_flag =
 516                         rte_pmd_ifd_dynflag_proto_xtr_ipsec_crypto_said_mask;
 517                 rxq->rxd_to_pkt_fields =
 518                         iavf_rxd_to_pkt_fields_by_comms_aux_v2;
 519                 break;
 520         case IAVF_RXDID_COMMS_OVS_1:
 521                 rxq->rxd_to_pkt_fields = iavf_rxd_to_pkt_fields_by_comms_ovs;
 522                 break;
 523         default:
 524                 /* update this according to the RXDID for FLEX_DESC_NONE */
 525                 rxq->rxd_to_pkt_fields = iavf_rxd_to_pkt_fields_by_comms_ovs;
 526                 break;
 527         }
 528
 529         if (!rte_pmd_ifd_dynf_proto_xtr_metadata_avail())
 530                 rxq->xtr_ol_flag = 0;
 531 }
 532
 533 int
 534 iavf_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 535                        uint16_t nb_desc, unsigned int socket_id,
 536                        const struct rte_eth_rxconf *rx_conf,
 537                        struct rte_mempool *mp)
 538 {
 539         struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 540         struct iavf_adapter *ad =
 541                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 542         struct iavf_info *vf =
 543                 IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 544         struct iavf_vsi *vsi = &vf->vsi;
 545         struct iavf_rx_queue *rxq;
 546         const struct rte_memzone *mz;
 547         uint32_t ring_size;
 548         uint8_t proto_xtr;
 549         uint16_t len;
 550         uint16_t rx_free_thresh;
 551         uint64_t offloads;
 552
 553         PMD_INIT_FUNC_TRACE();
 554
 555         offloads = rx_conf->offloads | dev->data->dev_conf.rxmode.offloads;
 556
 557         if (nb_desc % IAVF_ALIGN_RING_DESC != 0 ||
 558             nb_desc > IAVF_MAX_RING_DESC ||
 559             nb_desc < IAVF_MIN_RING_DESC) {
 560                 PMD_INIT_LOG(ERR, "Number (%u) of receive descriptors is "
 561                              "invalid", nb_desc);
 562                 return -EINVAL;
 563         }
 564
 565         /* Check free threshold */
 566         rx_free_thresh = (rx_conf->rx_free_thresh == 0) ?
 567                          IAVF_DEFAULT_RX_FREE_THRESH :
 568                          rx_conf->rx_free_thresh;
 569         if (check_rx_thresh(nb_desc, rx_free_thresh) != 0)
 570                 return -EINVAL;
 571
 572         /* Free memory if needed */
 573         if (dev->data->rx_queues[queue_idx]) {
 574                 iavf_dev_rx_queue_release(dev, queue_idx);
 575                 dev->data->rx_queues[queue_idx] = NULL;
 576         }
 577
 578         /* Allocate the rx queue data structure */
 579         rxq = rte_zmalloc_socket("iavf rxq",
 580                                  sizeof(struct iavf_rx_queue),
 581                                  RTE_CACHE_LINE_SIZE,
 582                                  socket_id);
 583         if (!rxq) {
 584                 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
 585                              "rx queue data structure");
 586                 return -ENOMEM;
 587         }
 588
 589         if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC) {
 590                 proto_xtr = vf->proto_xtr ? vf->proto_xtr[queue_idx] :
 591                                 IAVF_PROTO_XTR_NONE;
 592                 rxq->rxdid = iavf_proto_xtr_type_to_rxdid(proto_xtr);
 593                 rxq->proto_xtr = proto_xtr;
 594         } else {
 595                 rxq->rxdid = IAVF_RXDID_LEGACY_1;
 596                 rxq->proto_xtr = IAVF_PROTO_XTR_NONE;
 597         }
 598
 599         if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_VLAN_V2) {
 600                 struct virtchnl_vlan_supported_caps *stripping_support =
 601                                 &vf->vlan_v2_caps.offloads.stripping_support;
 602                 uint32_t stripping_cap;
 603
 604                 if (stripping_support->outer)
 605                         stripping_cap = stripping_support->outer;
 606                 else
 607                         stripping_cap = stripping_support->inner;
 608
 609                 if (stripping_cap & VIRTCHNL_VLAN_TAG_LOCATION_L2TAG1)
 610                         rxq->rx_flags = IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG1;
 611                 else if (stripping_cap & VIRTCHNL_VLAN_TAG_LOCATION_L2TAG2_2)
 612                         rxq->rx_flags = IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG2_2;
 613         } else {
 614                 rxq->rx_flags = IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG1;
 615         }
 616
 617         iavf_select_rxd_to_pkt_fields_handler(rxq, rxq->rxdid);
 618
 619         rxq->mp = mp;
 620         rxq->nb_rx_desc = nb_desc;
 621         rxq->rx_free_thresh = rx_free_thresh;
 622         rxq->queue_id = queue_idx;
 623         rxq->port_id = dev->data->port_id;
 624         rxq->rx_deferred_start = rx_conf->rx_deferred_start;
 625         rxq->rx_hdr_len = 0;
 626         rxq->vsi = vsi;
 627         rxq->offloads = offloads;
 628
 629         if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_KEEP_CRC)
 630                 rxq->crc_len = RTE_ETHER_CRC_LEN;
 631         else
 632                 rxq->crc_len = 0;
 633
 634         len = rte_pktmbuf_data_room_size(rxq->mp) - RTE_PKTMBUF_HEADROOM;
 635         rxq->rx_buf_len = RTE_ALIGN_FLOOR(len, (1 << IAVF_RXQ_CTX_DBUFF_SHIFT));
 636
 637         /* Allocate the software ring. */
 638         len = nb_desc + IAVF_RX_MAX_BURST;
 639         rxq->sw_ring =
 640                 rte_zmalloc_socket("iavf rx sw ring",
 641                                    sizeof(struct rte_mbuf *) * len,
 642                                    RTE_CACHE_LINE_SIZE,
 643                                    socket_id);
 644         if (!rxq->sw_ring) {
 645                 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW ring");
 646                 rte_free(rxq);
 647                 return -ENOMEM;
 648         }
 649
 650         /* Allocate the maximum number of RX ring hardware descriptor with
 651          * a little more to support bulk allocate.
 652          */
 653         len = IAVF_MAX_RING_DESC + IAVF_RX_MAX_BURST;
 654         ring_size = RTE_ALIGN(len * sizeof(union iavf_rx_desc),
 655                               IAVF_DMA_MEM_ALIGN);
 656         mz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
 657                                       ring_size, IAVF_RING_BASE_ALIGN,
 658                                       socket_id);
 659         if (!mz) {
 660                 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for RX");
 661                 rte_free(rxq->sw_ring);
 662                 rte_free(rxq);
 663                 return -ENOMEM;
 664         }
 665         /* Zero all the descriptors in the ring. */
 666         memset(mz->addr, 0, ring_size);
 667         rxq->rx_ring_phys_addr = mz->iova;
 668         rxq->rx_ring = (union iavf_rx_desc *)mz->addr;
 669
 670         rxq->mz = mz;
 671         reset_rx_queue(rxq);
 672         rxq->q_set = true;
 673         dev->data->rx_queues[queue_idx] = rxq;
 674         rxq->qrx_tail = hw->hw_addr + IAVF_QRX_TAIL1(rxq->queue_id);
 675         rxq->ops = &def_rxq_ops;
 676
 677         if (check_rx_bulk_allow(rxq) == true) {
 678                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
 679                              "satisfied. Rx Burst Bulk Alloc function will be "
 680                              "used on port=%d, queue=%d.",
 681                              rxq->port_id, rxq->queue_id);
 682         } else {
 683                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
 684                              "not satisfied, Scattered Rx is requested "
 685                              "on port=%d, queue=%d.",
 686                              rxq->port_id, rxq->queue_id);
 687                 ad->rx_bulk_alloc_allowed = false;
 688         }
 689
 690         if (check_rx_vec_allow(rxq) == false)
 691                 ad->rx_vec_allowed = false;
 692
 693         return 0;
 694 }
 695
 696 int
 697 iavf_dev_tx_queue_setup(struct rte_eth_dev *dev,
 698                        uint16_t queue_idx,
 699                        uint16_t nb_desc,
 700                        unsigned int socket_id,
 701                        const struct rte_eth_txconf *tx_conf)
 702 {
 703         struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 704         struct iavf_adapter *adapter =
 705                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 706         struct iavf_info *vf =
 707                 IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 708         struct iavf_tx_queue *txq;
 709         const struct rte_memzone *mz;
 710         uint32_t ring_size;
 711         uint16_t tx_rs_thresh, tx_free_thresh;
 712         uint64_t offloads;
 713
 714         PMD_INIT_FUNC_TRACE();
 715
 716         offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
 717
 718         if (nb_desc % IAVF_ALIGN_RING_DESC != 0 ||
 719             nb_desc > IAVF_MAX_RING_DESC ||
 720             nb_desc < IAVF_MIN_RING_DESC) {
 721                 PMD_INIT_LOG(ERR, "Number (%u) of transmit descriptors is "
 722                             "invalid", nb_desc);
 723                 return -EINVAL;
 724         }
 725
 726         tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
 727                 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
 728         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
 729                 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
 730         if (check_tx_thresh(nb_desc, tx_rs_thresh, tx_free_thresh) != 0)
 731                 return -EINVAL;
 732
 733         /* Free memory if needed. */
 734         if (dev->data->tx_queues[queue_idx]) {
 735                 iavf_dev_tx_queue_release(dev, queue_idx);
 736                 dev->data->tx_queues[queue_idx] = NULL;
 737         }
 738
 739         /* Allocate the TX queue data structure. */
 740         txq = rte_zmalloc_socket("iavf txq",
 741                                  sizeof(struct iavf_tx_queue),
 742                                  RTE_CACHE_LINE_SIZE,
 743                                  socket_id);
 744         if (!txq) {
 745                 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
 746                              "tx queue structure");
 747                 return -ENOMEM;
 748         }
 749
 750         if (adapter->vf.vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_VLAN_V2) {
 751                 struct virtchnl_vlan_supported_caps *insertion_support =
 752                         &adapter->vf.vlan_v2_caps.offloads.insertion_support;
 753                 uint32_t insertion_cap;
 754
 755                 if (insertion_support->outer)
 756                         insertion_cap = insertion_support->outer;
 757                 else
 758                         insertion_cap = insertion_support->inner;
 759
 760                 if (insertion_cap & VIRTCHNL_VLAN_TAG_LOCATION_L2TAG1)
 761                         txq->vlan_flag = IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG1;
 762                 else if (insertion_cap & VIRTCHNL_VLAN_TAG_LOCATION_L2TAG2)
 763                         txq->vlan_flag = IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG2;
 764         } else {
 765                 txq->vlan_flag = IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG1;
 766         }
 767
 768         txq->nb_tx_desc = nb_desc;
 769         txq->rs_thresh = tx_rs_thresh;
 770         txq->free_thresh = tx_free_thresh;
 771         txq->queue_id = queue_idx;
 772         txq->port_id = dev->data->port_id;
 773         txq->offloads = offloads;
 774         txq->tx_deferred_start = tx_conf->tx_deferred_start;
 775
 776         if (iavf_ipsec_crypto_supported(adapter))
 777                 txq->ipsec_crypto_pkt_md_offset =
 778                         iavf_security_get_pkt_md_offset(adapter);
 779
 780         /* Allocate software ring */
 781         txq->sw_ring =
 782                 rte_zmalloc_socket("iavf tx sw ring",
 783                                    sizeof(struct iavf_tx_entry) * nb_desc,
 784                                    RTE_CACHE_LINE_SIZE,
 785                                    socket_id);
 786         if (!txq->sw_ring) {
 787                 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW TX ring");
 788                 rte_free(txq);
 789                 return -ENOMEM;
 790         }
 791
 792         /* Allocate TX hardware ring descriptors. */
 793         ring_size = sizeof(struct iavf_tx_desc) * IAVF_MAX_RING_DESC;
 794         ring_size = RTE_ALIGN(ring_size, IAVF_DMA_MEM_ALIGN);
 795         mz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
 796                                       ring_size, IAVF_RING_BASE_ALIGN,
 797                                       socket_id);
 798         if (!mz) {
 799                 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for TX");
 800                 rte_free(txq->sw_ring);
 801                 rte_free(txq);
 802                 return -ENOMEM;
 803         }
 804         txq->tx_ring_phys_addr = mz->iova;
 805         txq->tx_ring = (struct iavf_tx_desc *)mz->addr;
 806
 807         txq->mz = mz;
 808         reset_tx_queue(txq);
 809         txq->q_set = true;
 810         dev->data->tx_queues[queue_idx] = txq;
 811         txq->qtx_tail = hw->hw_addr + IAVF_QTX_TAIL1(queue_idx);
 812         txq->ops = &def_txq_ops;
 813
 814         if (check_tx_vec_allow(txq) == false) {
 815                 struct iavf_adapter *ad =
 816                         IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 817                 ad->tx_vec_allowed = false;
 818         }
 819
 820         if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_QOS &&
 821             vf->tm_conf.committed) {
 822                 int tc;
 823                 for (tc = 0; tc < vf->qos_cap->num_elem; tc++) {
 824                         if (txq->queue_id >= vf->qtc_map[tc].start_queue_id &&
 825                             txq->queue_id < (vf->qtc_map[tc].start_queue_id +
 826                             vf->qtc_map[tc].queue_count))
 827                                 break;
 828                 }
 829                 if (tc >= vf->qos_cap->num_elem) {
 830                         PMD_INIT_LOG(ERR, "Queue TC mapping is not correct");
 831                         return -EINVAL;
 832                 }
 833                 txq->tc = tc;
 834         }
 835
 836         return 0;
 837 }
 838
 839 int
 840 iavf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 841 {
 842         struct iavf_adapter *adapter =
 843                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 844         struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 845         struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 846         struct iavf_rx_queue *rxq;
 847         int err = 0;
 848
 849         PMD_DRV_FUNC_TRACE();
 850
 851         if (rx_queue_id >= dev->data->nb_rx_queues)
 852                 return -EINVAL;
 853
 854         rxq = dev->data->rx_queues[rx_queue_id];
 855
 856         err = alloc_rxq_mbufs(rxq);
 857         if (err) {
 858                 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
 859                 return err;
 860         }
 861
 862         rte_wmb();
 863
 864         /* Init the RX tail register. */
 865         IAVF_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 866         IAVF_WRITE_FLUSH(hw);
 867
 868         /* Ready to switch the queue on */
 869         if (!vf->lv_enabled)
 870                 err = iavf_switch_queue(adapter, rx_queue_id, true, true);
 871         else
 872                 err = iavf_switch_queue_lv(adapter, rx_queue_id, true, true);
 873
 874         if (err) {
 875                 release_rxq_mbufs(rxq);
 876                 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
 877                             rx_queue_id);
 878         } else {
 879                 dev->data->rx_queue_state[rx_queue_id] =
 880                         RTE_ETH_QUEUE_STATE_STARTED;
 881         }
 882
 883         return err;
 884 }
 885
 886 int
 887 iavf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 888 {
 889         struct iavf_adapter *adapter =
 890                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 891         struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 892         struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 893         struct iavf_tx_queue *txq;
 894         int err = 0;
 895
 896         PMD_DRV_FUNC_TRACE();
 897
 898         if (tx_queue_id >= dev->data->nb_tx_queues)
 899                 return -EINVAL;
 900
 901         txq = dev->data->tx_queues[tx_queue_id];
 902
 903         /* Init the RX tail register. */
 904         IAVF_PCI_REG_WRITE(txq->qtx_tail, 0);
 905         IAVF_WRITE_FLUSH(hw);
 906
 907         /* Ready to switch the queue on */
 908         if (!vf->lv_enabled)
 909                 err = iavf_switch_queue(adapter, tx_queue_id, false, true);
 910         else
 911                 err = iavf_switch_queue_lv(adapter, tx_queue_id, false, true);
 912
 913         if (err)
 914                 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
 915                             tx_queue_id);
 916         else
 917                 dev->data->tx_queue_state[tx_queue_id] =
 918                         RTE_ETH_QUEUE_STATE_STARTED;
 919
 920         return err;
 921 }
 922
 923 int
 924 iavf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 925 {
 926         struct iavf_adapter *adapter =
 927                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 928         struct iavf_rx_queue *rxq;
 929         int err;
 930
 931         PMD_DRV_FUNC_TRACE();
 932
 933         if (rx_queue_id >= dev->data->nb_rx_queues)
 934                 return -EINVAL;
 935
 936         err = iavf_switch_queue(adapter, rx_queue_id, true, false);
 937         if (err) {
 938                 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
 939                             rx_queue_id);
 940                 return err;
 941         }
 942
 943         rxq = dev->data->rx_queues[rx_queue_id];
 944         rxq->ops->release_mbufs(rxq);
 945         reset_rx_queue(rxq);
 946         dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 947
 948         return 0;
 949 }
 950
 951 int
 952 iavf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 953 {
 954         struct iavf_adapter *adapter =
 955                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 956         struct iavf_tx_queue *txq;
 957         int err;
 958
 959         PMD_DRV_FUNC_TRACE();
 960
 961         if (tx_queue_id >= dev->data->nb_tx_queues)
 962                 return -EINVAL;
 963
 964         err = iavf_switch_queue(adapter, tx_queue_id, false, false);
 965         if (err) {
 966                 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u off",
 967                             tx_queue_id);
 968                 return err;
 969         }
 970
 971         txq = dev->data->tx_queues[tx_queue_id];
 972         txq->ops->release_mbufs(txq);
 973         reset_tx_queue(txq);
 974         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 975
 976         return 0;
 977 }
 978
 979 void
 980 iavf_dev_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
 981 {
 982         struct iavf_rx_queue *q = dev->data->rx_queues[qid];
 983
 984         if (!q)
 985                 return;
 986
 987         q->ops->release_mbufs(q);
 988         rte_free(q->sw_ring);
 989         rte_memzone_free(q->mz);
 990         rte_free(q);
 991 }
 992
 993 void
 994 iavf_dev_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
 995 {
 996         struct iavf_tx_queue *q = dev->data->tx_queues[qid];
 997
 998         if (!q)
 999                 return;
1000
1001         q->ops->release_mbufs(q);
1002         rte_free(q->sw_ring);
1003         rte_memzone_free(q->mz);
1004         rte_free(q);
1005 }
1006
1007 void
1008 iavf_stop_queues(struct rte_eth_dev *dev)
1009 {
1010         struct iavf_adapter *adapter =
1011                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1012         struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1013         struct iavf_rx_queue *rxq;
1014         struct iavf_tx_queue *txq;
1015         int ret, i;
1016
1017         /* Stop All queues */
1018         if (!vf->lv_enabled) {
1019                 ret = iavf_disable_queues(adapter);
1020                 if (ret)
1021                         PMD_DRV_LOG(WARNING, "Fail to stop queues");
1022         } else {
1023                 ret = iavf_disable_queues_lv(adapter);
1024                 if (ret)
1025                         PMD_DRV_LOG(WARNING, "Fail to stop queues for large VF");
1026         }
1027
1028         if (ret)
1029                 PMD_DRV_LOG(WARNING, "Fail to stop queues");
1030
1031         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1032                 txq = dev->data->tx_queues[i];
1033                 if (!txq)
1034                         continue;
1035                 txq->ops->release_mbufs(txq);
1036                 reset_tx_queue(txq);
1037                 dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED;
1038         }
1039         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1040                 rxq = dev->data->rx_queues[i];
1041                 if (!rxq)
1042                         continue;
1043                 rxq->ops->release_mbufs(rxq);
1044                 reset_rx_queue(rxq);
1045                 dev->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED;
1046         }
1047 }
1048
1049 #define IAVF_RX_FLEX_ERR0_BITS  \
1050         ((1 << IAVF_RX_FLEX_DESC_STATUS0_HBO_S) |       \
1051          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_IPE_S) |  \
1052          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_L4E_S) |  \
1053          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S) | \
1054          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S) |        \
1055          (1 << IAVF_RX_FLEX_DESC_STATUS0_RXE_S))
1056
1057 static inline void
1058 iavf_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union iavf_rx_desc *rxdp)
1059 {
1060         if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1061                 (1 << IAVF_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
1062                 mb->ol_flags |= RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED;
1063                 mb->vlan_tci =
1064                         rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
1065         } else {
1066                 mb->vlan_tci = 0;
1067         }
1068 }
1069
1070 static inline void
1071 iavf_flex_rxd_to_vlan_tci(struct rte_mbuf *mb,
1072                           volatile union iavf_rx_flex_desc *rxdp)
1073 {
1074         if (rte_le_to_cpu_64(rxdp->wb.status_error0) &
1075                 (1 << IAVF_RX_FLEX_DESC_STATUS0_L2TAG1P_S)) {
1076                 mb->ol_flags |= RTE_MBUF_F_RX_VLAN |
1077                                 RTE_MBUF_F_RX_VLAN_STRIPPED;
1078                 mb->vlan_tci =
1079                         rte_le_to_cpu_16(rxdp->wb.l2tag1);
1080         } else {
1081                 mb->vlan_tci = 0;
1082         }
1083
1084 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
1085         if (rte_le_to_cpu_16(rxdp->wb.status_error1) &
1086             (1 << IAVF_RX_FLEX_DESC_STATUS1_L2TAG2P_S)) {
1087                 mb->ol_flags |= RTE_MBUF_F_RX_QINQ_STRIPPED |
1088                                 RTE_MBUF_F_RX_QINQ |
1089                                 RTE_MBUF_F_RX_VLAN_STRIPPED |
1090                                 RTE_MBUF_F_RX_VLAN;
1091                 mb->vlan_tci_outer = mb->vlan_tci;
1092                 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.l2tag2_2nd);
1093                 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
1094                            rte_le_to_cpu_16(rxdp->wb.l2tag2_1st),
1095                            rte_le_to_cpu_16(rxdp->wb.l2tag2_2nd));
1096         } else {
1097                 mb->vlan_tci_outer = 0;
1098         }
1099 #endif
1100 }
1101
1102 static inline void
1103 iavf_flex_rxd_to_ipsec_crypto_said_get(struct rte_mbuf *mb,
1104                           volatile union iavf_rx_flex_desc *rxdp)
1105 {
1106         volatile struct iavf_32b_rx_flex_desc_comms_ipsec *desc =
1107                 (volatile struct iavf_32b_rx_flex_desc_comms_ipsec *)rxdp;
1108
1109         mb->dynfield1[0] = desc->ipsec_said &
1110                          IAVF_RX_FLEX_DESC_IPSEC_CRYPTO_SAID_MASK;
1111         }
1112
1113 static inline void
1114 iavf_flex_rxd_to_ipsec_crypto_status(struct rte_mbuf *mb,
1115                           volatile union iavf_rx_flex_desc *rxdp,
1116                           struct iavf_ipsec_crypto_stats *stats)
1117 {
1118         uint16_t status1 = rte_le_to_cpu_64(rxdp->wb.status_error1);
1119
1120         if (status1 & BIT(IAVF_RX_FLEX_DESC_STATUS1_IPSEC_CRYPTO_PROCESSED)) {
1121                 uint16_t ipsec_status;
1122
1123                 mb->ol_flags |= RTE_MBUF_F_RX_SEC_OFFLOAD;
1124
1125                 ipsec_status = status1 &
1126                         IAVF_RX_FLEX_DESC_IPSEC_CRYPTO_STATUS_MASK;
1127
1128
1129                 if (unlikely(ipsec_status !=
1130                         IAVF_IPSEC_CRYPTO_STATUS_SUCCESS)) {
1131                         mb->ol_flags |= RTE_MBUF_F_RX_SEC_OFFLOAD_FAILED;
1132
1133                         switch (ipsec_status) {
1134                         case IAVF_IPSEC_CRYPTO_STATUS_SAD_MISS:
1135                                 stats->ierrors.sad_miss++;
1136                                 break;
1137                         case IAVF_IPSEC_CRYPTO_STATUS_NOT_PROCESSED:
1138                                 stats->ierrors.not_processed++;
1139                                 break;
1140                         case IAVF_IPSEC_CRYPTO_STATUS_ICV_CHECK_FAIL:
1141                                 stats->ierrors.icv_check++;
1142                                 break;
1143                         case IAVF_IPSEC_CRYPTO_STATUS_LENGTH_ERR:
1144                                 stats->ierrors.ipsec_length++;
1145                                 break;
1146                         case IAVF_IPSEC_CRYPTO_STATUS_MISC_ERR:
1147                                 stats->ierrors.misc++;
1148                                 break;
1149 }
1150
1151                         stats->ierrors.count++;
1152                         return;
1153                 }
1154
1155                 stats->icount++;
1156                 stats->ibytes += rxdp->wb.pkt_len & 0x3FFF;
1157
1158                 if (rxdp->wb.rxdid == IAVF_RXDID_COMMS_IPSEC_CRYPTO &&
1159                         ipsec_status !=
1160                                 IAVF_IPSEC_CRYPTO_STATUS_SAD_MISS)
1161                         iavf_flex_rxd_to_ipsec_crypto_said_get(mb, rxdp);
1162         }
1163 }
1164
1165
1166 /* Translate the rx descriptor status and error fields to pkt flags */
1167 static inline uint64_t
1168 iavf_rxd_to_pkt_flags(uint64_t qword)
1169 {
1170         uint64_t flags;
1171         uint64_t error_bits = (qword >> IAVF_RXD_QW1_ERROR_SHIFT);
1172
1173 #define IAVF_RX_ERR_BITS 0x3f
1174
1175         /* Check if RSS_HASH */
1176         flags = (((qword >> IAVF_RX_DESC_STATUS_FLTSTAT_SHIFT) &
1177                                         IAVF_RX_DESC_FLTSTAT_RSS_HASH) ==
1178                         IAVF_RX_DESC_FLTSTAT_RSS_HASH) ? RTE_MBUF_F_RX_RSS_HASH : 0;
1179
1180         /* Check if FDIR Match */
1181         flags |= (qword & (1 << IAVF_RX_DESC_STATUS_FLM_SHIFT) ?
1182                                 RTE_MBUF_F_RX_FDIR : 0);
1183
1184         if (likely((error_bits & IAVF_RX_ERR_BITS) == 0)) {
1185                 flags |= (RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_GOOD);
1186                 return flags;
1187         }
1188
1189         if (unlikely(error_bits & (1 << IAVF_RX_DESC_ERROR_IPE_SHIFT)))
1190                 flags |= RTE_MBUF_F_RX_IP_CKSUM_BAD;
1191         else
1192                 flags |= RTE_MBUF_F_RX_IP_CKSUM_GOOD;
1193
1194         if (unlikely(error_bits & (1 << IAVF_RX_DESC_ERROR_L4E_SHIFT)))
1195                 flags |= RTE_MBUF_F_RX_L4_CKSUM_BAD;
1196         else
1197                 flags |= RTE_MBUF_F_RX_L4_CKSUM_GOOD;
1198
1199         /* TODO: Oversize error bit is not processed here */
1200
1201         return flags;
1202 }
1203
1204 static inline uint64_t
1205 iavf_rxd_build_fdir(volatile union iavf_rx_desc *rxdp, struct rte_mbuf *mb)
1206 {
1207         uint64_t flags = 0;
1208 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
1209         uint16_t flexbh;
1210
1211         flexbh = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
1212                 IAVF_RX_DESC_EXT_STATUS_FLEXBH_SHIFT) &
1213                 IAVF_RX_DESC_EXT_STATUS_FLEXBH_MASK;
1214
1215         if (flexbh == IAVF_RX_DESC_EXT_STATUS_FLEXBH_FD_ID) {
1216                 mb->hash.fdir.hi =
1217                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.fd_id);
1218                 flags |= RTE_MBUF_F_RX_FDIR_ID;
1219         }
1220 #else
1221         mb->hash.fdir.hi =
1222                 rte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.fd_id);
1223         flags |= RTE_MBUF_F_RX_FDIR_ID;
1224 #endif
1225         return flags;
1226 }
1227
1228 #define IAVF_RX_FLEX_ERR0_BITS  \
1229         ((1 << IAVF_RX_FLEX_DESC_STATUS0_HBO_S) |       \
1230          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_IPE_S) |  \
1231          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_L4E_S) |  \
1232          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S) | \
1233          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S) |        \
1234          (1 << IAVF_RX_FLEX_DESC_STATUS0_RXE_S))
1235
1236 /* Rx L3/L4 checksum */
1237 static inline uint64_t
1238 iavf_flex_rxd_error_to_pkt_flags(uint16_t stat_err0)
1239 {
1240         uint64_t flags = 0;
1241
1242         /* check if HW has decoded the packet and checksum */
1243         if (unlikely(!(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_L3L4P_S))))
1244                 return 0;
1245
1246         if (likely(!(stat_err0 & IAVF_RX_FLEX_ERR0_BITS))) {
1247                 flags |= (RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_GOOD);
1248                 return flags;
1249         }
1250
1251         if (unlikely(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_IPE_S)))
1252                 flags |= RTE_MBUF_F_RX_IP_CKSUM_BAD;
1253         else
1254                 flags |= RTE_MBUF_F_RX_IP_CKSUM_GOOD;
1255
1256         if (unlikely(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_L4E_S)))
1257                 flags |= RTE_MBUF_F_RX_L4_CKSUM_BAD;
1258         else
1259                 flags |= RTE_MBUF_F_RX_L4_CKSUM_GOOD;
1260
1261         if (unlikely(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S)))
1262                 flags |= RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD;
1263
1264         return flags;
1265 }
1266
1267 /* If the number of free RX descriptors is greater than the RX free
1268  * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1269  * register. Update the RDT with the value of the last processed RX
1270  * descriptor minus 1, to guarantee that the RDT register is never
1271  * equal to the RDH register, which creates a "full" ring situation
1272  * from the hardware point of view.
1273  */
1274 static inline void
1275 iavf_update_rx_tail(struct iavf_rx_queue *rxq, uint16_t nb_hold, uint16_t rx_id)
1276 {
1277         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1278
1279         if (nb_hold > rxq->rx_free_thresh) {
1280                 PMD_RX_LOG(DEBUG,
1281                            "port_id=%u queue_id=%u rx_tail=%u nb_hold=%u",
1282                            rxq->port_id, rxq->queue_id, rx_id, nb_hold);
1283                 rx_id = (uint16_t)((rx_id == 0) ?
1284                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
1285                 IAVF_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
1286                 nb_hold = 0;
1287         }
1288         rxq->nb_rx_hold = nb_hold;
1289 }
1290
1291 /* implement recv_pkts */
1292 uint16_t
1293 iavf_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1294 {
1295         volatile union iavf_rx_desc *rx_ring;
1296         volatile union iavf_rx_desc *rxdp;
1297         struct iavf_rx_queue *rxq;
1298         union iavf_rx_desc rxd;
1299         struct rte_mbuf *rxe;
1300         struct rte_eth_dev *dev;
1301         struct rte_mbuf *rxm;
1302         struct rte_mbuf *nmb;
1303         uint16_t nb_rx;
1304         uint32_t rx_status;
1305         uint64_t qword1;
1306         uint16_t rx_packet_len;
1307         uint16_t rx_id, nb_hold;
1308         uint64_t dma_addr;
1309         uint64_t pkt_flags;
1310         const uint32_t *ptype_tbl;
1311
1312         nb_rx = 0;
1313         nb_hold = 0;
1314         rxq = rx_queue;
1315         rx_id = rxq->rx_tail;
1316         rx_ring = rxq->rx_ring;
1317         ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1318
1319         while (nb_rx < nb_pkts) {
1320                 rxdp = &rx_ring[rx_id];
1321                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1322                 rx_status = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
1323                             IAVF_RXD_QW1_STATUS_SHIFT;
1324
1325                 /* Check the DD bit first */
1326                 if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)))
1327                         break;
1328                 IAVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
1329
1330                 nmb = rte_mbuf_raw_alloc(rxq->mp);
1331                 if (unlikely(!nmb)) {
1332                         dev = &rte_eth_devices[rxq->port_id];
1333                         dev->data->rx_mbuf_alloc_failed++;
1334                         PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1335                                    "queue_id=%u", rxq->port_id, rxq->queue_id);
1336                         break;
1337                 }
1338
1339                 rxd = *rxdp;
1340                 nb_hold++;
1341                 rxe = rxq->sw_ring[rx_id];
1342                 rxq->sw_ring[rx_id] = nmb;
1343                 rx_id++;
1344                 if (unlikely(rx_id == rxq->nb_rx_desc))
1345                         rx_id = 0;
1346
1347                 /* Prefetch next mbuf */
1348                 rte_prefetch0(rxq->sw_ring[rx_id]);
1349
1350                 /* When next RX descriptor is on a cache line boundary,
1351                  * prefetch the next 4 RX descriptors and next 8 pointers
1352                  * to mbufs.
1353                  */
1354                 if ((rx_id & 0x3) == 0) {
1355                         rte_prefetch0(&rx_ring[rx_id]);
1356                         rte_prefetch0(rxq->sw_ring[rx_id]);
1357                 }
1358                 rxm = rxe;
1359                 dma_addr =
1360                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1361                 rxdp->read.hdr_addr = 0;
1362                 rxdp->read.pkt_addr = dma_addr;
1363
1364                 rx_packet_len = ((qword1 & IAVF_RXD_QW1_LENGTH_PBUF_MASK) >>
1365                                 IAVF_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
1366
1367                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1368                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
1369                 rxm->nb_segs = 1;
1370                 rxm->next = NULL;
1371                 rxm->pkt_len = rx_packet_len;
1372                 rxm->data_len = rx_packet_len;
1373                 rxm->port = rxq->port_id;
1374                 rxm->ol_flags = 0;
1375                 iavf_rxd_to_vlan_tci(rxm, &rxd);
1376                 pkt_flags = iavf_rxd_to_pkt_flags(qword1);
1377                 rxm->packet_type =
1378                         ptype_tbl[(uint8_t)((qword1 &
1379                         IAVF_RXD_QW1_PTYPE_MASK) >> IAVF_RXD_QW1_PTYPE_SHIFT)];
1380
1381                 if (pkt_flags & RTE_MBUF_F_RX_RSS_HASH)
1382                         rxm->hash.rss =
1383                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1384
1385                 if (pkt_flags & RTE_MBUF_F_RX_FDIR)
1386                         pkt_flags |= iavf_rxd_build_fdir(&rxd, rxm);
1387
1388                 rxm->ol_flags |= pkt_flags;
1389
1390                 rx_pkts[nb_rx++] = rxm;
1391         }
1392         rxq->rx_tail = rx_id;
1393
1394         iavf_update_rx_tail(rxq, nb_hold, rx_id);
1395
1396         return nb_rx;
1397 }
1398
1399 /* implement recv_pkts for flexible Rx descriptor */
1400 uint16_t
1401 iavf_recv_pkts_flex_rxd(void *rx_queue,
1402                         struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1403 {
1404         volatile union iavf_rx_desc *rx_ring;
1405         volatile union iavf_rx_flex_desc *rxdp;
1406         struct iavf_rx_queue *rxq;
1407         union iavf_rx_flex_desc rxd;
1408         struct rte_mbuf *rxe;
1409         struct rte_eth_dev *dev;
1410         struct rte_mbuf *rxm;
1411         struct rte_mbuf *nmb;
1412         uint16_t nb_rx;
1413         uint16_t rx_stat_err0;
1414         uint16_t rx_packet_len;
1415         uint16_t rx_id, nb_hold;
1416         uint64_t dma_addr;
1417         uint64_t pkt_flags;
1418         const uint32_t *ptype_tbl;
1419
1420         nb_rx = 0;
1421         nb_hold = 0;
1422         rxq = rx_queue;
1423         rx_id = rxq->rx_tail;
1424         rx_ring = rxq->rx_ring;
1425         ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1426
1427         while (nb_rx < nb_pkts) {
1428                 rxdp = (volatile union iavf_rx_flex_desc *)&rx_ring[rx_id];
1429                 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1430
1431                 /* Check the DD bit first */
1432                 if (!(rx_stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S)))
1433                         break;
1434                 IAVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
1435
1436                 nmb = rte_mbuf_raw_alloc(rxq->mp);
1437                 if (unlikely(!nmb)) {
1438                         dev = &rte_eth_devices[rxq->port_id];
1439                         dev->data->rx_mbuf_alloc_failed++;
1440                         PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1441                                    "queue_id=%u", rxq->port_id, rxq->queue_id);
1442                         break;
1443                 }
1444
1445                 rxd = *rxdp;
1446                 nb_hold++;
1447                 rxe = rxq->sw_ring[rx_id];
1448                 rxq->sw_ring[rx_id] = nmb;
1449                 rx_id++;
1450                 if (unlikely(rx_id == rxq->nb_rx_desc))
1451                         rx_id = 0;
1452
1453                 /* Prefetch next mbuf */
1454                 rte_prefetch0(rxq->sw_ring[rx_id]);
1455
1456                 /* When next RX descriptor is on a cache line boundary,
1457                  * prefetch the next 4 RX descriptors and next 8 pointers
1458                  * to mbufs.
1459                  */
1460                 if ((rx_id & 0x3) == 0) {
1461                         rte_prefetch0(&rx_ring[rx_id]);
1462                         rte_prefetch0(rxq->sw_ring[rx_id]);
1463                 }
1464                 rxm = rxe;
1465                 dma_addr =
1466                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1467                 rxdp->read.hdr_addr = 0;
1468                 rxdp->read.pkt_addr = dma_addr;
1469
1470                 rx_packet_len = (rte_le_to_cpu_16(rxd.wb.pkt_len) &
1471                                 IAVF_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
1472
1473                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1474                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
1475                 rxm->nb_segs = 1;
1476                 rxm->next = NULL;
1477                 rxm->pkt_len = rx_packet_len;
1478                 rxm->data_len = rx_packet_len;
1479                 rxm->port = rxq->port_id;
1480                 rxm->ol_flags = 0;
1481                 rxm->packet_type = ptype_tbl[IAVF_RX_FLEX_DESC_PTYPE_M &
1482                         rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
1483                 iavf_flex_rxd_to_vlan_tci(rxm, &rxd);
1484                 iavf_flex_rxd_to_ipsec_crypto_status(rxm, &rxd,
1485                                 &rxq->stats.ipsec_crypto);
1486                 rxq->rxd_to_pkt_fields(rxq, rxm, &rxd);
1487                 pkt_flags = iavf_flex_rxd_error_to_pkt_flags(rx_stat_err0);
1488                 rxm->ol_flags |= pkt_flags;
1489
1490                 rx_pkts[nb_rx++] = rxm;
1491         }
1492         rxq->rx_tail = rx_id;
1493
1494         iavf_update_rx_tail(rxq, nb_hold, rx_id);
1495
1496         return nb_rx;
1497 }
1498
1499 /* implement recv_scattered_pkts for flexible Rx descriptor */
1500 uint16_t
1501 iavf_recv_scattered_pkts_flex_rxd(void *rx_queue, struct rte_mbuf **rx_pkts,
1502                                   uint16_t nb_pkts)
1503 {
1504         struct iavf_rx_queue *rxq = rx_queue;
1505         union iavf_rx_flex_desc rxd;
1506         struct rte_mbuf *rxe;
1507         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1508         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1509         struct rte_mbuf *nmb, *rxm;
1510         uint16_t rx_id = rxq->rx_tail;
1511         uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
1512         struct rte_eth_dev *dev;
1513         uint16_t rx_stat_err0;
1514         uint64_t dma_addr;
1515         uint64_t pkt_flags;
1516
1517         volatile union iavf_rx_desc *rx_ring = rxq->rx_ring;
1518         volatile union iavf_rx_flex_desc *rxdp;
1519         const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1520
1521         while (nb_rx < nb_pkts) {
1522                 rxdp = (volatile union iavf_rx_flex_desc *)&rx_ring[rx_id];
1523                 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1524
1525                 /* Check the DD bit */
1526                 if (!(rx_stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S)))
1527                         break;
1528                 IAVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
1529
1530                 nmb = rte_mbuf_raw_alloc(rxq->mp);
1531                 if (unlikely(!nmb)) {
1532                         PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1533                                    "queue_id=%u", rxq->port_id, rxq->queue_id);
1534                         dev = &rte_eth_devices[rxq->port_id];
1535                         dev->data->rx_mbuf_alloc_failed++;
1536                         break;
1537                 }
1538
1539                 rxd = *rxdp;
1540                 nb_hold++;
1541                 rxe = rxq->sw_ring[rx_id];
1542                 rxq->sw_ring[rx_id] = nmb;
1543                 rx_id++;
1544                 if (rx_id == rxq->nb_rx_desc)
1545                         rx_id = 0;
1546
1547                 /* Prefetch next mbuf */
1548                 rte_prefetch0(rxq->sw_ring[rx_id]);
1549
1550                 /* When next RX descriptor is on a cache line boundary,
1551                  * prefetch the next 4 RX descriptors and next 8 pointers
1552                  * to mbufs.
1553                  */
1554                 if ((rx_id & 0x3) == 0) {
1555                         rte_prefetch0(&rx_ring[rx_id]);
1556                         rte_prefetch0(rxq->sw_ring[rx_id]);
1557                 }
1558
1559                 rxm = rxe;
1560                 dma_addr =
1561                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1562
1563                 /* Set data buffer address and data length of the mbuf */
1564                 rxdp->read.hdr_addr = 0;
1565                 rxdp->read.pkt_addr = dma_addr;
1566                 rx_packet_len = rte_le_to_cpu_16(rxd.wb.pkt_len) &
1567                                 IAVF_RX_FLX_DESC_PKT_LEN_M;
1568                 rxm->data_len = rx_packet_len;
1569                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1570
1571                 /* If this is the first buffer of the received packet, set the
1572                  * pointer to the first mbuf of the packet and initialize its
1573                  * context. Otherwise, update the total length and the number
1574                  * of segments of the current scattered packet, and update the
1575                  * pointer to the last mbuf of the current packet.
1576                  */
1577                 if (!first_seg) {
1578                         first_seg = rxm;
1579                         first_seg->nb_segs = 1;
1580                         first_seg->pkt_len = rx_packet_len;
1581                 } else {
1582                         first_seg->pkt_len =
1583                                 (uint16_t)(first_seg->pkt_len +
1584                                                 rx_packet_len);
1585                         first_seg->nb_segs++;
1586                         last_seg->next = rxm;
1587                 }
1588
1589                 /* If this is not the last buffer of the received packet,
1590                  * update the pointer to the last mbuf of the current scattered
1591                  * packet and continue to parse the RX ring.
1592                  */
1593                 if (!(rx_stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_EOF_S))) {
1594                         last_seg = rxm;
1595                         continue;
1596                 }
1597
1598                 /* This is the last buffer of the received packet. If the CRC
1599                  * is not stripped by the hardware:
1600                  *  - Subtract the CRC length from the total packet length.
1601                  *  - If the last buffer only contains the whole CRC or a part
1602                  *  of it, free the mbuf associated to the last buffer. If part
1603                  *  of the CRC is also contained in the previous mbuf, subtract
1604                  *  the length of that CRC part from the data length of the
1605                  *  previous mbuf.
1606                  */
1607                 rxm->next = NULL;
1608                 if (unlikely(rxq->crc_len > 0)) {
1609                         first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
1610                         if (rx_packet_len <= RTE_ETHER_CRC_LEN) {
1611                                 rte_pktmbuf_free_seg(rxm);
1612                                 first_seg->nb_segs--;
1613                                 last_seg->data_len =
1614                                         (uint16_t)(last_seg->data_len -
1615                                         (RTE_ETHER_CRC_LEN - rx_packet_len));
1616                                 last_seg->next = NULL;
1617                         } else {
1618                                 rxm->data_len = (uint16_t)(rx_packet_len -
1619                                                         RTE_ETHER_CRC_LEN);
1620                         }
1621                 }
1622
1623                 first_seg->port = rxq->port_id;
1624                 first_seg->ol_flags = 0;
1625                 first_seg->packet_type = ptype_tbl[IAVF_RX_FLEX_DESC_PTYPE_M &
1626                         rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
1627                 iavf_flex_rxd_to_vlan_tci(first_seg, &rxd);
1628                 iavf_flex_rxd_to_ipsec_crypto_status(first_seg, &rxd,
1629                                 &rxq->stats.ipsec_crypto);
1630                 rxq->rxd_to_pkt_fields(rxq, first_seg, &rxd);
1631                 pkt_flags = iavf_flex_rxd_error_to_pkt_flags(rx_stat_err0);
1632
1633                 first_seg->ol_flags |= pkt_flags;
1634
1635                 /* Prefetch data of first segment, if configured to do so. */
1636                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1637                                           first_seg->data_off));
1638                 rx_pkts[nb_rx++] = first_seg;
1639                 first_seg = NULL;
1640         }
1641
1642         /* Record index of the next RX descriptor to probe. */
1643         rxq->rx_tail = rx_id;
1644         rxq->pkt_first_seg = first_seg;
1645         rxq->pkt_last_seg = last_seg;
1646
1647         iavf_update_rx_tail(rxq, nb_hold, rx_id);
1648
1649         return nb_rx;
1650 }
1651
1652 /* implement recv_scattered_pkts  */
1653 uint16_t
1654 iavf_recv_scattered_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1655                         uint16_t nb_pkts)
1656 {
1657         struct iavf_rx_queue *rxq = rx_queue;
1658         union iavf_rx_desc rxd;
1659         struct rte_mbuf *rxe;
1660         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1661         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1662         struct rte_mbuf *nmb, *rxm;
1663         uint16_t rx_id = rxq->rx_tail;
1664         uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
1665         struct rte_eth_dev *dev;
1666         uint32_t rx_status;
1667         uint64_t qword1;
1668         uint64_t dma_addr;
1669         uint64_t pkt_flags;
1670
1671         volatile union iavf_rx_desc *rx_ring = rxq->rx_ring;
1672         volatile union iavf_rx_desc *rxdp;
1673         const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1674
1675         while (nb_rx < nb_pkts) {
1676                 rxdp = &rx_ring[rx_id];
1677                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1678                 rx_status = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
1679                             IAVF_RXD_QW1_STATUS_SHIFT;
1680
1681                 /* Check the DD bit */
1682                 if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)))
1683                         break;
1684                 IAVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
1685
1686                 nmb = rte_mbuf_raw_alloc(rxq->mp);
1687                 if (unlikely(!nmb)) {
1688                         PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1689                                    "queue_id=%u", rxq->port_id, rxq->queue_id);
1690                         dev = &rte_eth_devices[rxq->port_id];
1691                         dev->data->rx_mbuf_alloc_failed++;
1692                         break;
1693                 }
1694
1695                 rxd = *rxdp;
1696                 nb_hold++;
1697                 rxe = rxq->sw_ring[rx_id];
1698                 rxq->sw_ring[rx_id] = nmb;
1699                 rx_id++;
1700                 if (rx_id == rxq->nb_rx_desc)
1701                         rx_id = 0;
1702
1703                 /* Prefetch next mbuf */
1704                 rte_prefetch0(rxq->sw_ring[rx_id]);
1705
1706                 /* When next RX descriptor is on a cache line boundary,
1707                  * prefetch the next 4 RX descriptors and next 8 pointers
1708                  * to mbufs.
1709                  */
1710                 if ((rx_id & 0x3) == 0) {
1711                         rte_prefetch0(&rx_ring[rx_id]);
1712                         rte_prefetch0(rxq->sw_ring[rx_id]);
1713                 }
1714
1715                 rxm = rxe;
1716                 dma_addr =
1717                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1718
1719                 /* Set data buffer address and data length of the mbuf */
1720                 rxdp->read.hdr_addr = 0;
1721                 rxdp->read.pkt_addr = dma_addr;
1722                 rx_packet_len = (qword1 & IAVF_RXD_QW1_LENGTH_PBUF_MASK) >>
1723                                  IAVF_RXD_QW1_LENGTH_PBUF_SHIFT;
1724                 rxm->data_len = rx_packet_len;
1725                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1726
1727                 /* If this is the first buffer of the received packet, set the
1728                  * pointer to the first mbuf of the packet and initialize its
1729                  * context. Otherwise, update the total length and the number
1730                  * of segments of the current scattered packet, and update the
1731                  * pointer to the last mbuf of the current packet.
1732                  */
1733                 if (!first_seg) {
1734                         first_seg = rxm;
1735                         first_seg->nb_segs = 1;
1736                         first_seg->pkt_len = rx_packet_len;
1737                 } else {
1738                         first_seg->pkt_len =
1739                                 (uint16_t)(first_seg->pkt_len +
1740                                                 rx_packet_len);
1741                         first_seg->nb_segs++;
1742                         last_seg->next = rxm;
1743                 }
1744
1745                 /* If this is not the last buffer of the received packet,
1746                  * update the pointer to the last mbuf of the current scattered
1747                  * packet and continue to parse the RX ring.
1748                  */
1749                 if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_EOF_SHIFT))) {
1750                         last_seg = rxm;
1751                         continue;
1752                 }
1753
1754                 /* This is the last buffer of the received packet. If the CRC
1755                  * is not stripped by the hardware:
1756                  *  - Subtract the CRC length from the total packet length.
1757                  *  - If the last buffer only contains the whole CRC or a part
1758                  *  of it, free the mbuf associated to the last buffer. If part
1759                  *  of the CRC is also contained in the previous mbuf, subtract
1760                  *  the length of that CRC part from the data length of the
1761                  *  previous mbuf.
1762                  */
1763                 rxm->next = NULL;
1764                 if (unlikely(rxq->crc_len > 0)) {
1765                         first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
1766                         if (rx_packet_len <= RTE_ETHER_CRC_LEN) {
1767                                 rte_pktmbuf_free_seg(rxm);
1768                                 first_seg->nb_segs--;
1769                                 last_seg->data_len =
1770                                         (uint16_t)(last_seg->data_len -
1771                                         (RTE_ETHER_CRC_LEN - rx_packet_len));
1772                                 last_seg->next = NULL;
1773                         } else
1774                                 rxm->data_len = (uint16_t)(rx_packet_len -
1775                                                         RTE_ETHER_CRC_LEN);
1776                 }
1777
1778                 first_seg->port = rxq->port_id;
1779                 first_seg->ol_flags = 0;
1780                 iavf_rxd_to_vlan_tci(first_seg, &rxd);
1781                 pkt_flags = iavf_rxd_to_pkt_flags(qword1);
1782                 first_seg->packet_type =
1783                         ptype_tbl[(uint8_t)((qword1 &
1784                         IAVF_RXD_QW1_PTYPE_MASK) >> IAVF_RXD_QW1_PTYPE_SHIFT)];
1785
1786                 if (pkt_flags & RTE_MBUF_F_RX_RSS_HASH)
1787                         first_seg->hash.rss =
1788                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1789
1790                 if (pkt_flags & RTE_MBUF_F_RX_FDIR)
1791                         pkt_flags |= iavf_rxd_build_fdir(&rxd, first_seg);
1792
1793                 first_seg->ol_flags |= pkt_flags;
1794
1795                 /* Prefetch data of first segment, if configured to do so. */
1796                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1797                                           first_seg->data_off));
1798                 rx_pkts[nb_rx++] = first_seg;
1799                 first_seg = NULL;
1800         }
1801
1802         /* Record index of the next RX descriptor to probe. */
1803         rxq->rx_tail = rx_id;
1804         rxq->pkt_first_seg = first_seg;
1805         rxq->pkt_last_seg = last_seg;
1806
1807         iavf_update_rx_tail(rxq, nb_hold, rx_id);
1808
1809         return nb_rx;
1810 }
1811
1812 #define IAVF_LOOK_AHEAD 8
1813 static inline int
1814 iavf_rx_scan_hw_ring_flex_rxd(struct iavf_rx_queue *rxq)
1815 {
1816         volatile union iavf_rx_flex_desc *rxdp;
1817         struct rte_mbuf **rxep;
1818         struct rte_mbuf *mb;
1819         uint16_t stat_err0;
1820         uint16_t pkt_len;
1821         int32_t s[IAVF_LOOK_AHEAD], nb_dd;
1822         int32_t i, j, nb_rx = 0;
1823         uint64_t pkt_flags;
1824         const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1825
1826         rxdp = (volatile union iavf_rx_flex_desc *)&rxq->rx_ring[rxq->rx_tail];
1827         rxep = &rxq->sw_ring[rxq->rx_tail];
1828
1829         stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1830
1831         /* Make sure there is at least 1 packet to receive */
1832         if (!(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S)))
1833                 return 0;
1834
1835         /* Scan LOOK_AHEAD descriptors at a time to determine which
1836          * descriptors reference packets that are ready to be received.
1837          */
1838         for (i = 0; i < IAVF_RX_MAX_BURST; i += IAVF_LOOK_AHEAD,
1839              rxdp += IAVF_LOOK_AHEAD, rxep += IAVF_LOOK_AHEAD) {
1840                 /* Read desc statuses backwards to avoid race condition */
1841                 for (j = IAVF_LOOK_AHEAD - 1; j >= 0; j--)
1842                         s[j] = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1843
1844                 rte_smp_rmb();
1845
1846                 /* Compute how many status bits were set */
1847                 for (j = 0, nb_dd = 0; j < IAVF_LOOK_AHEAD; j++)
1848                         nb_dd += s[j] & (1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S);
1849
1850                 nb_rx += nb_dd;
1851
1852                 /* Translate descriptor info to mbuf parameters */
1853                 for (j = 0; j < nb_dd; j++) {
1854                         IAVF_DUMP_RX_DESC(rxq, &rxdp[j],
1855                                           rxq->rx_tail +
1856                                           i * IAVF_LOOK_AHEAD + j);
1857
1858                         mb = rxep[j];
1859                         pkt_len = (rte_le_to_cpu_16(rxdp[j].wb.pkt_len) &
1860                                 IAVF_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
1861                         mb->data_len = pkt_len;
1862                         mb->pkt_len = pkt_len;
1863                         mb->ol_flags = 0;
1864
1865                         mb->packet_type = ptype_tbl[IAVF_RX_FLEX_DESC_PTYPE_M &
1866                                 rte_le_to_cpu_16(rxdp[j].wb.ptype_flex_flags0)];
1867                         iavf_flex_rxd_to_vlan_tci(mb, &rxdp[j]);
1868                         iavf_flex_rxd_to_ipsec_crypto_status(mb, &rxdp[j],
1869                                 &rxq->stats.ipsec_crypto);
1870                         rxq->rxd_to_pkt_fields(rxq, mb, &rxdp[j]);
1871                         stat_err0 = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1872                         pkt_flags = iavf_flex_rxd_error_to_pkt_flags(stat_err0);
1873
1874                         mb->ol_flags |= pkt_flags;
1875                 }
1876
1877                 for (j = 0; j < IAVF_LOOK_AHEAD; j++)
1878                         rxq->rx_stage[i + j] = rxep[j];
1879
1880                 if (nb_dd != IAVF_LOOK_AHEAD)
1881                         break;
1882         }
1883
1884         /* Clear software ring entries */
1885         for (i = 0; i < nb_rx; i++)
1886                 rxq->sw_ring[rxq->rx_tail + i] = NULL;
1887
1888         return nb_rx;
1889 }
1890
1891 static inline int
1892 iavf_rx_scan_hw_ring(struct iavf_rx_queue *rxq)
1893 {
1894         volatile union iavf_rx_desc *rxdp;
1895         struct rte_mbuf **rxep;
1896         struct rte_mbuf *mb;
1897         uint16_t pkt_len;
1898         uint64_t qword1;
1899         uint32_t rx_status;
1900         int32_t s[IAVF_LOOK_AHEAD], var, nb_dd;
1901         int32_t i, j, nb_rx = 0;
1902         uint64_t pkt_flags;
1903         const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1904
1905         rxdp = &rxq->rx_ring[rxq->rx_tail];
1906         rxep = &rxq->sw_ring[rxq->rx_tail];
1907
1908         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1909         rx_status = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
1910                     IAVF_RXD_QW1_STATUS_SHIFT;
1911
1912         /* Make sure there is at least 1 packet to receive */
1913         if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)))
1914                 return 0;
1915
1916         /* Scan LOOK_AHEAD descriptors at a time to determine which
1917          * descriptors reference packets that are ready to be received.
1918          */
1919         for (i = 0; i < IAVF_RX_MAX_BURST; i += IAVF_LOOK_AHEAD,
1920              rxdp += IAVF_LOOK_AHEAD, rxep += IAVF_LOOK_AHEAD) {
1921                 /* Read desc statuses backwards to avoid race condition */
1922                 for (j = IAVF_LOOK_AHEAD - 1; j >= 0; j--) {
1923                         qword1 = rte_le_to_cpu_64(
1924                                 rxdp[j].wb.qword1.status_error_len);
1925                         s[j] = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
1926                                IAVF_RXD_QW1_STATUS_SHIFT;
1927                 }
1928
1929                 rte_smp_rmb();
1930
1931                 /* Compute how many contiguous DD bits were set */
1932                 for (j = 0, nb_dd = 0; j < IAVF_LOOK_AHEAD; j++) {
1933                         var = s[j] & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT);
1934 #ifdef RTE_ARCH_ARM
1935                         /* For Arm platforms, count only contiguous descriptors
1936                          * whose DD bit is set to 1. On Arm platforms, reads of
1937                          * descriptors can be reordered. Since the CPU may
1938                          * be reading the descriptors as the NIC updates them
1939                          * in memory, it is possbile that the DD bit for a
1940                          * descriptor earlier in the queue is read as not set
1941                          * while the DD bit for a descriptor later in the queue
1942                          * is read as set.
1943                          */
1944                         if (var)
1945                                 nb_dd += 1;
1946                         else
1947                                 break;
1948 #else
1949                         nb_dd += var;
1950 #endif
1951                 }
1952
1953                 nb_rx += nb_dd;
1954
1955                 /* Translate descriptor info to mbuf parameters */
1956                 for (j = 0; j < nb_dd; j++) {
1957                         IAVF_DUMP_RX_DESC(rxq, &rxdp[j],
1958                                          rxq->rx_tail + i * IAVF_LOOK_AHEAD + j);
1959
1960                         mb = rxep[j];
1961                         qword1 = rte_le_to_cpu_64
1962                                         (rxdp[j].wb.qword1.status_error_len);
1963                         pkt_len = ((qword1 & IAVF_RXD_QW1_LENGTH_PBUF_MASK) >>
1964                                   IAVF_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
1965                         mb->data_len = pkt_len;
1966                         mb->pkt_len = pkt_len;
1967                         mb->ol_flags = 0;
1968                         iavf_rxd_to_vlan_tci(mb, &rxdp[j]);
1969                         pkt_flags = iavf_rxd_to_pkt_flags(qword1);
1970                         mb->packet_type =
1971                                 ptype_tbl[(uint8_t)((qword1 &
1972                                 IAVF_RXD_QW1_PTYPE_MASK) >>
1973                                 IAVF_RXD_QW1_PTYPE_SHIFT)];
1974
1975                         if (pkt_flags & RTE_MBUF_F_RX_RSS_HASH)
1976                                 mb->hash.rss = rte_le_to_cpu_32(
1977                                         rxdp[j].wb.qword0.hi_dword.rss);
1978
1979                         if (pkt_flags & RTE_MBUF_F_RX_FDIR)
1980                                 pkt_flags |= iavf_rxd_build_fdir(&rxdp[j], mb);
1981
1982                         mb->ol_flags |= pkt_flags;
1983                 }
1984
1985                 for (j = 0; j < IAVF_LOOK_AHEAD; j++)
1986                         rxq->rx_stage[i + j] = rxep[j];
1987
1988                 if (nb_dd != IAVF_LOOK_AHEAD)
1989                         break;
1990         }
1991
1992         /* Clear software ring entries */
1993         for (i = 0; i < nb_rx; i++)
1994                 rxq->sw_ring[rxq->rx_tail + i] = NULL;
1995
1996         return nb_rx;
1997 }
1998
1999 static inline uint16_t
2000 iavf_rx_fill_from_stage(struct iavf_rx_queue *rxq,
2001                        struct rte_mbuf **rx_pkts,
2002                        uint16_t nb_pkts)
2003 {
2004         uint16_t i;
2005         struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
2006
2007         nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
2008
2009         for (i = 0; i < nb_pkts; i++)
2010                 rx_pkts[i] = stage[i];
2011
2012         rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
2013         rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
2014
2015         return nb_pkts;
2016 }
2017
2018 static inline int
2019 iavf_rx_alloc_bufs(struct iavf_rx_queue *rxq)
2020 {
2021         volatile union iavf_rx_desc *rxdp;
2022         struct rte_mbuf **rxep;
2023         struct rte_mbuf *mb;
2024         uint16_t alloc_idx, i;
2025         uint64_t dma_addr;
2026         int diag;
2027
2028         /* Allocate buffers in bulk */
2029         alloc_idx = (uint16_t)(rxq->rx_free_trigger -
2030                                 (rxq->rx_free_thresh - 1));
2031         rxep = &rxq->sw_ring[alloc_idx];
2032         diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
2033                                     rxq->rx_free_thresh);
2034         if (unlikely(diag != 0)) {
2035                 PMD_RX_LOG(ERR, "Failed to get mbufs in bulk");
2036                 return -ENOMEM;
2037         }
2038
2039         rxdp = &rxq->rx_ring[alloc_idx];
2040         for (i = 0; i < rxq->rx_free_thresh; i++) {
2041                 if (likely(i < (rxq->rx_free_thresh - 1)))
2042                         /* Prefetch next mbuf */
2043                         rte_prefetch0(rxep[i + 1]);
2044
2045                 mb = rxep[i];
2046                 rte_mbuf_refcnt_set(mb, 1);
2047                 mb->next = NULL;
2048                 mb->data_off = RTE_PKTMBUF_HEADROOM;
2049                 mb->nb_segs = 1;
2050                 mb->port = rxq->port_id;
2051                 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mb));
2052                 rxdp[i].read.hdr_addr = 0;
2053                 rxdp[i].read.pkt_addr = dma_addr;
2054         }
2055
2056         /* Update rx tail register */
2057         rte_wmb();
2058         IAVF_PCI_REG_WC_WRITE_RELAXED(rxq->qrx_tail, rxq->rx_free_trigger);
2059
2060         rxq->rx_free_trigger =
2061                 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
2062         if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
2063                 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2064
2065         return 0;
2066 }
2067
2068 static inline uint16_t
2069 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
2070 {
2071         struct iavf_rx_queue *rxq = (struct iavf_rx_queue *)rx_queue;
2072         uint16_t nb_rx = 0;
2073
2074         if (!nb_pkts)
2075                 return 0;
2076
2077         if (rxq->rx_nb_avail)
2078                 return iavf_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
2079
2080         if (rxq->rxdid >= IAVF_RXDID_FLEX_NIC && rxq->rxdid <= IAVF_RXDID_LAST)
2081                 nb_rx = (uint16_t)iavf_rx_scan_hw_ring_flex_rxd(rxq);
2082         else
2083                 nb_rx = (uint16_t)iavf_rx_scan_hw_ring(rxq);
2084         rxq->rx_next_avail = 0;
2085         rxq->rx_nb_avail = nb_rx;
2086         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
2087
2088         if (rxq->rx_tail > rxq->rx_free_trigger) {
2089                 if (iavf_rx_alloc_bufs(rxq) != 0) {
2090                         uint16_t i, j;
2091
2092                         /* TODO: count rx_mbuf_alloc_failed here */
2093
2094                         rxq->rx_nb_avail = 0;
2095                         rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
2096                         for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
2097                                 rxq->sw_ring[j] = rxq->rx_stage[i];
2098
2099                         return 0;
2100                 }
2101         }
2102
2103         if (rxq->rx_tail >= rxq->nb_rx_desc)
2104                 rxq->rx_tail = 0;
2105
2106         PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u, nb_rx=%u",
2107                    rxq->port_id, rxq->queue_id,
2108                    rxq->rx_tail, nb_rx);
2109
2110         if (rxq->rx_nb_avail)
2111                 return iavf_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
2112
2113         return 0;
2114 }
2115
2116 static uint16_t
2117 iavf_recv_pkts_bulk_alloc(void *rx_queue,
2118                          struct rte_mbuf **rx_pkts,
2119                          uint16_t nb_pkts)
2120 {
2121         uint16_t nb_rx = 0, n, count;
2122
2123         if (unlikely(nb_pkts == 0))
2124                 return 0;
2125
2126         if (likely(nb_pkts <= IAVF_RX_MAX_BURST))
2127                 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
2128
2129         while (nb_pkts) {
2130                 n = RTE_MIN(nb_pkts, IAVF_RX_MAX_BURST);
2131                 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
2132                 nb_rx = (uint16_t)(nb_rx + count);
2133                 nb_pkts = (uint16_t)(nb_pkts - count);
2134                 if (count < n)
2135                         break;
2136         }
2137
2138         return nb_rx;
2139 }
2140
2141 static inline int
2142 iavf_xmit_cleanup(struct iavf_tx_queue *txq)
2143 {
2144         struct iavf_tx_entry *sw_ring = txq->sw_ring;
2145         uint16_t last_desc_cleaned = txq->last_desc_cleaned;
2146         uint16_t nb_tx_desc = txq->nb_tx_desc;
2147         uint16_t desc_to_clean_to;
2148         uint16_t nb_tx_to_clean;
2149
2150         volatile struct iavf_tx_desc *txd = txq->tx_ring;
2151
2152         desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->rs_thresh);
2153         if (desc_to_clean_to >= nb_tx_desc)
2154                 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
2155
2156         desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
2157         if ((txd[desc_to_clean_to].cmd_type_offset_bsz &
2158                         rte_cpu_to_le_64(IAVF_TXD_QW1_DTYPE_MASK)) !=
2159                         rte_cpu_to_le_64(IAVF_TX_DESC_DTYPE_DESC_DONE)) {
2160                 PMD_TX_LOG(DEBUG, "TX descriptor %4u is not done "
2161                            "(port=%d queue=%d)", desc_to_clean_to,
2162                            txq->port_id, txq->queue_id);
2163                 return -1;
2164         }
2165
2166         if (last_desc_cleaned > desc_to_clean_to)
2167                 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
2168                                                         desc_to_clean_to);
2169         else
2170                 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
2171                                         last_desc_cleaned);
2172
2173         txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
2174
2175         txq->last_desc_cleaned = desc_to_clean_to;
2176         txq->nb_free = (uint16_t)(txq->nb_free + nb_tx_to_clean);
2177
2178         return 0;
2179 }
2180
2181 /* Check if the context descriptor is needed for TX offloading */
2182 static inline uint16_t
2183 iavf_calc_context_desc(uint64_t flags, uint8_t vlan_flag)
2184 {
2185         if (flags & (RTE_MBUF_F_TX_TCP_SEG | RTE_MBUF_F_TX_UDP_SEG |
2186                         RTE_MBUF_F_TX_TUNNEL_MASK))
2187                 return 1;
2188         if (flags & RTE_MBUF_F_TX_VLAN &&
2189             vlan_flag & IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG2)
2190                 return 1;
2191         return 0;
2192 }
2193
2194 static inline void
2195 iavf_fill_ctx_desc_cmd_field(volatile uint64_t *field, struct rte_mbuf *m,
2196                 uint8_t vlan_flag)
2197 {
2198         uint64_t cmd = 0;
2199
2200         /* TSO enabled */
2201         if (m->ol_flags & (RTE_MBUF_F_TX_TCP_SEG | RTE_MBUF_F_TX_UDP_SEG))
2202                 cmd = IAVF_TX_CTX_DESC_TSO << IAVF_TXD_CTX_QW1_CMD_SHIFT;
2203
2204         if (m->ol_flags & RTE_MBUF_F_TX_VLAN &&
2205                         vlan_flag & IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG2) {
2206                 cmd |= IAVF_TX_CTX_DESC_IL2TAG2
2207                         << IAVF_TXD_CTX_QW1_CMD_SHIFT;
2208         }
2209
2210         *field |= cmd;
2211 }
2212
2213 static inline void
2214 iavf_fill_ctx_desc_ipsec_field(volatile uint64_t *field,
2215         struct iavf_ipsec_crypto_pkt_metadata *ipsec_md)
2216 {
2217         uint64_t ipsec_field =
2218                 (uint64_t)ipsec_md->ctx_desc_ipsec_params <<
2219                         IAVF_TXD_CTX_QW1_IPSEC_PARAMS_CIPHERBLK_SHIFT;
2220
2221         *field |= ipsec_field;
2222 }
2223
2224
2225 static inline void
2226 iavf_fill_ctx_desc_tunnelling_field(volatile uint64_t *qw0,
2227                 const struct rte_mbuf *m)
2228 {
2229         uint64_t eip_typ = IAVF_TX_CTX_DESC_EIPT_NONE;
2230         uint64_t eip_len = 0;
2231         uint64_t eip_noinc = 0;
2232         /* Default - IP_ID is increment in each segment of LSO */
2233
2234         switch (m->ol_flags & (RTE_MBUF_F_TX_OUTER_IPV4 |
2235                         RTE_MBUF_F_TX_OUTER_IPV6 |
2236                         RTE_MBUF_F_TX_OUTER_IP_CKSUM)) {
2237         case RTE_MBUF_F_TX_OUTER_IPV4:
2238                 eip_typ = IAVF_TX_CTX_DESC_EIPT_IPV4_NO_CHECKSUM_OFFLOAD;
2239                 eip_len = m->outer_l3_len >> 2;
2240         break;
2241         case RTE_MBUF_F_TX_OUTER_IPV4 | RTE_MBUF_F_TX_OUTER_IP_CKSUM:
2242                 eip_typ = IAVF_TX_CTX_DESC_EIPT_IPV4_CHECKSUM_OFFLOAD;
2243                 eip_len = m->outer_l3_len >> 2;
2244         break;
2245         case RTE_MBUF_F_TX_OUTER_IPV6:
2246                 eip_typ = IAVF_TX_CTX_DESC_EIPT_IPV6;
2247                 eip_len = m->outer_l3_len >> 2;
2248         break;
2249         }
2250
2251         *qw0 = eip_typ << IAVF_TXD_CTX_QW0_TUN_PARAMS_EIPT_SHIFT |
2252                 eip_len << IAVF_TXD_CTX_QW0_TUN_PARAMS_EIPLEN_SHIFT |
2253                 eip_noinc << IAVF_TXD_CTX_QW0_TUN_PARAMS_EIP_NOINC_SHIFT;
2254 }
2255
2256 static inline uint16_t
2257 iavf_fill_ctx_desc_segmentation_field(volatile uint64_t *field,
2258         struct rte_mbuf *m, struct iavf_ipsec_crypto_pkt_metadata *ipsec_md)
2259 {
2260         uint64_t segmentation_field = 0;
2261         uint64_t total_length = 0;
2262
2263         if (m->ol_flags & RTE_MBUF_F_TX_SEC_OFFLOAD) {
2264                 total_length = ipsec_md->l4_payload_len;
2265         } else {
2266                 total_length = m->pkt_len - (m->l2_len + m->l3_len + m->l4_len);
2267
2268                 if (m->ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK)
2269                         total_length -= m->outer_l3_len;
2270         }
2271
2272 #ifdef RTE_LIBRTE_IAVF_DEBUG_TX
2273         if (!m->l4_len || !m->tso_segsz)
2274                 PMD_TX_LOG(DEBUG, "L4 length %d, LSO Segment size %d",
2275                          m->l4_len, m->tso_segsz);
2276         if (m->tso_segsz < 88)
2277                 PMD_TX_LOG(DEBUG, "LSO Segment size %d is less than minimum %d",
2278                         m->tso_segsz, 88);
2279 #endif
2280         segmentation_field =
2281                 (((uint64_t)total_length << IAVF_TXD_CTX_QW1_TSO_LEN_SHIFT) &
2282                                 IAVF_TXD_CTX_QW1_TSO_LEN_MASK) |
2283                 (((uint64_t)m->tso_segsz << IAVF_TXD_CTX_QW1_MSS_SHIFT) &
2284                                 IAVF_TXD_CTX_QW1_MSS_MASK);
2285
2286         *field |= segmentation_field;
2287
2288         return total_length;
2289 }
2290
2291
2292 struct iavf_tx_context_desc_qws {
2293         __le64 qw0;
2294         __le64 qw1;
2295 };
2296
2297 static inline void
2298 iavf_fill_context_desc(volatile struct iavf_tx_context_desc *desc,
2299         struct rte_mbuf *m, struct iavf_ipsec_crypto_pkt_metadata *ipsec_md,
2300         uint16_t *tlen, uint8_t vlan_flag)
2301 {
2302         volatile struct iavf_tx_context_desc_qws *desc_qws =
2303                         (volatile struct iavf_tx_context_desc_qws *)desc;
2304         /* fill descriptor type field */
2305         desc_qws->qw1 = IAVF_TX_DESC_DTYPE_CONTEXT;
2306
2307         /* fill command field */
2308         iavf_fill_ctx_desc_cmd_field(&desc_qws->qw1, m, vlan_flag);
2309
2310         /* fill segmentation field */
2311         if (m->ol_flags & (RTE_MBUF_F_TX_TCP_SEG | RTE_MBUF_F_TX_UDP_SEG)) {
2312                 /* fill IPsec field */
2313                 if (m->ol_flags & RTE_MBUF_F_TX_SEC_OFFLOAD)
2314                         iavf_fill_ctx_desc_ipsec_field(&desc_qws->qw1,
2315                                 ipsec_md);
2316
2317                 *tlen = iavf_fill_ctx_desc_segmentation_field(&desc_qws->qw1,
2318                                 m, ipsec_md);
2319         }
2320
2321         /* fill tunnelling field */
2322         if (m->ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK)
2323                 iavf_fill_ctx_desc_tunnelling_field(&desc_qws->qw0, m);
2324         else
2325                 desc_qws->qw0 = 0;
2326
2327         desc_qws->qw0 = rte_cpu_to_le_64(desc_qws->qw0);
2328         desc_qws->qw1 = rte_cpu_to_le_64(desc_qws->qw1);
2329
2330         if (vlan_flag & IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG2)
2331                 desc->l2tag2 = m->vlan_tci;
2332 }
2333
2334
2335 static inline void
2336 iavf_fill_ipsec_desc(volatile struct iavf_tx_ipsec_desc *desc,
2337         const struct iavf_ipsec_crypto_pkt_metadata *md, uint16_t *ipsec_len)
2338 {
2339         desc->qw0 = rte_cpu_to_le_64(((uint64_t)md->l4_payload_len <<
2340                 IAVF_IPSEC_TX_DESC_QW0_L4PAYLEN_SHIFT) |
2341                 ((uint64_t)md->esn << IAVF_IPSEC_TX_DESC_QW0_IPSECESN_SHIFT) |
2342                 ((uint64_t)md->esp_trailer_len <<
2343                                 IAVF_IPSEC_TX_DESC_QW0_TRAILERLEN_SHIFT));
2344
2345         desc->qw1 = rte_cpu_to_le_64(((uint64_t)md->sa_idx <<
2346                 IAVF_IPSEC_TX_DESC_QW1_IPSECSA_SHIFT) |
2347                 ((uint64_t)md->next_proto <<
2348                                 IAVF_IPSEC_TX_DESC_QW1_IPSECNH_SHIFT) |
2349                 ((uint64_t)(md->len_iv & 0x3) <<
2350                                 IAVF_IPSEC_TX_DESC_QW1_IVLEN_SHIFT) |
2351                 ((uint64_t)(md->ol_flags & IAVF_IPSEC_CRYPTO_OL_FLAGS_NATT ?
2352                                 1ULL : 0ULL) <<
2353                                 IAVF_IPSEC_TX_DESC_QW1_UDP_SHIFT) |
2354                 (uint64_t)IAVF_TX_DESC_DTYPE_IPSEC);
2355
2356         /**
2357          * TODO: Pre-calculate this in the Session initialization
2358          *
2359          * Calculate IPsec length required in data descriptor func when TSO
2360          * offload is enabled
2361          */
2362         *ipsec_len = sizeof(struct rte_esp_hdr) + (md->len_iv >> 2) +
2363                         (md->ol_flags & IAVF_IPSEC_CRYPTO_OL_FLAGS_NATT ?
2364                         sizeof(struct rte_udp_hdr) : 0);
2365 }
2366
2367 static inline void
2368 iavf_build_data_desc_cmd_offset_fields(volatile uint64_t *qw1,
2369                 struct rte_mbuf *m, uint8_t vlan_flag)
2370 {
2371         uint64_t command = 0;
2372         uint64_t offset = 0;
2373         uint64_t l2tag1 = 0;
2374
2375         *qw1 = IAVF_TX_DESC_DTYPE_DATA;
2376
2377         command = (uint64_t)IAVF_TX_DESC_CMD_ICRC;
2378
2379         /* Descriptor based VLAN insertion */
2380         if ((vlan_flag & IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG1) &&
2381                         m->ol_flags & RTE_MBUF_F_TX_VLAN) {
2382                 command |= (uint64_t)IAVF_TX_DESC_CMD_IL2TAG1;
2383                 l2tag1 |= m->vlan_tci;
2384         }
2385
2386         /* Set MACLEN */
2387         offset |= (m->l2_len >> 1) << IAVF_TX_DESC_LENGTH_MACLEN_SHIFT;
2388
2389         /* Enable L3 checksum offloading inner */
2390         if (m->ol_flags & (RTE_MBUF_F_TX_IP_CKSUM | RTE_MBUF_F_TX_IPV4)) {
2391                 command |= IAVF_TX_DESC_CMD_IIPT_IPV4_CSUM;
2392                 offset |= (m->l3_len >> 2) << IAVF_TX_DESC_LENGTH_IPLEN_SHIFT;
2393         } else if (m->ol_flags & RTE_MBUF_F_TX_IPV4) {
2394                 command |= IAVF_TX_DESC_CMD_IIPT_IPV4;
2395                 offset |= (m->l3_len >> 2) << IAVF_TX_DESC_LENGTH_IPLEN_SHIFT;
2396         } else if (m->ol_flags & RTE_MBUF_F_TX_IPV6) {
2397                 command |= IAVF_TX_DESC_CMD_IIPT_IPV6;
2398                 offset |= (m->l3_len >> 2) << IAVF_TX_DESC_LENGTH_IPLEN_SHIFT;
2399         }
2400
2401         if (m->ol_flags & RTE_MBUF_F_TX_TCP_SEG) {
2402                 command |= IAVF_TX_DESC_CMD_L4T_EOFT_TCP;
2403                 offset |= (m->l4_len >> 2) <<
2404                               IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2405         }
2406
2407         /* Enable L4 checksum offloads */
2408         switch (m->ol_flags & RTE_MBUF_F_TX_L4_MASK) {
2409         case RTE_MBUF_F_TX_TCP_CKSUM:
2410                 command |= IAVF_TX_DESC_CMD_L4T_EOFT_TCP;
2411                 offset |= (sizeof(struct rte_tcp_hdr) >> 2) <<
2412                                 IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2413                 break;
2414         case RTE_MBUF_F_TX_SCTP_CKSUM:
2415                 command |= IAVF_TX_DESC_CMD_L4T_EOFT_SCTP;
2416                 offset |= (sizeof(struct rte_sctp_hdr) >> 2) <<
2417                                 IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2418                 break;
2419         case RTE_MBUF_F_TX_UDP_CKSUM:
2420                 command |= IAVF_TX_DESC_CMD_L4T_EOFT_UDP;
2421                 offset |= (sizeof(struct rte_udp_hdr) >> 2) <<
2422                                 IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2423                 break;
2424         }
2425
2426         *qw1 = rte_cpu_to_le_64((((uint64_t)command <<
2427                 IAVF_TXD_DATA_QW1_CMD_SHIFT) & IAVF_TXD_DATA_QW1_CMD_MASK) |
2428                 (((uint64_t)offset << IAVF_TXD_DATA_QW1_OFFSET_SHIFT) &
2429                 IAVF_TXD_DATA_QW1_OFFSET_MASK) |
2430                 ((uint64_t)l2tag1 << IAVF_TXD_DATA_QW1_L2TAG1_SHIFT));
2431 }
2432
2433 static inline void
2434 iavf_fill_data_desc(volatile struct iavf_tx_desc *desc,
2435         struct rte_mbuf *m, uint64_t desc_template,
2436         uint16_t tlen, uint16_t ipseclen)
2437 {
2438         uint32_t hdrlen = m->l2_len;
2439         uint32_t bufsz = 0;
2440
2441         /* fill data descriptor qw1 from template */
2442         desc->cmd_type_offset_bsz = desc_template;
2443
2444         /* set data buffer address */
2445         desc->buffer_addr = rte_mbuf_data_iova(m);
2446
2447         /* calculate data buffer size less set header lengths */
2448         if (m->ol_flags & (RTE_MBUF_F_TX_TCP_SEG | RTE_MBUF_F_TX_UDP_SEG)) {
2449                 if (m->ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK)
2450                         hdrlen += m->outer_l3_len;
2451                 if (m->ol_flags & RTE_MBUF_F_TX_L4_MASK)
2452                         hdrlen += m->l3_len + m->l4_len;
2453                 else
2454                         hdrlen += m->l3_len;
2455                 if (m->ol_flags & RTE_MBUF_F_TX_SEC_OFFLOAD)
2456                         hdrlen += ipseclen;
2457                 bufsz = hdrlen + tlen;
2458         } else {
2459                 bufsz = m->data_len;
2460         }
2461
2462         /* set data buffer size */
2463         desc->cmd_type_offset_bsz |=
2464                 (((uint64_t)bufsz << IAVF_TXD_DATA_QW1_TX_BUF_SZ_SHIFT) &
2465                 IAVF_TXD_DATA_QW1_TX_BUF_SZ_MASK);
2466
2467         desc->buffer_addr = rte_cpu_to_le_64(desc->buffer_addr);
2468         desc->cmd_type_offset_bsz = rte_cpu_to_le_64(desc->cmd_type_offset_bsz);
2469 }
2470
2471
2472 static struct iavf_ipsec_crypto_pkt_metadata *
2473 iavf_ipsec_crypto_get_pkt_metadata(const struct iavf_tx_queue *txq,
2474                 struct rte_mbuf *m)
2475 {
2476         if (m->ol_flags & RTE_MBUF_F_TX_SEC_OFFLOAD)
2477                 return RTE_MBUF_DYNFIELD(m, txq->ipsec_crypto_pkt_md_offset,
2478                                 struct iavf_ipsec_crypto_pkt_metadata *);
2479
2480         return NULL;
2481 }
2482
2483 /* TX function */
2484 uint16_t
2485 iavf_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2486 {
2487         struct iavf_tx_queue *txq = tx_queue;
2488         volatile struct iavf_tx_desc *txr = txq->tx_ring;
2489         struct iavf_tx_entry *txe_ring = txq->sw_ring;
2490         struct iavf_tx_entry *txe, *txn;
2491         struct rte_mbuf *mb, *mb_seg;
2492         uint16_t desc_idx, desc_idx_last;
2493         uint16_t idx;
2494
2495
2496         /* Check if the descriptor ring needs to be cleaned. */
2497         if (txq->nb_free < txq->free_thresh)
2498                 iavf_xmit_cleanup(txq);
2499
2500         desc_idx = txq->tx_tail;
2501         txe = &txe_ring[desc_idx];
2502
2503 #ifdef RTE_LIBRTE_IAVF_DEBUG_TX_DESC_RING
2504                 iavf_dump_tx_entry_ring(txq);
2505                 iavf_dump_tx_desc_ring(txq);
2506 #endif
2507
2508
2509         for (idx = 0; idx < nb_pkts; idx++) {
2510                 volatile struct iavf_tx_desc *ddesc;
2511                 struct iavf_ipsec_crypto_pkt_metadata *ipsec_md;
2512
2513                 uint16_t nb_desc_ctx, nb_desc_ipsec;
2514                 uint16_t nb_desc_data, nb_desc_required;
2515                 uint16_t tlen = 0, ipseclen = 0;
2516                 uint64_t ddesc_template = 0;
2517                 uint64_t ddesc_cmd = 0;
2518
2519                 mb = tx_pkts[idx];
2520
2521                 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
2522
2523                 /**
2524                  * Get metadata for ipsec crypto from mbuf dynamic fields if
2525                  * security offload is specified.
2526                  */
2527                 ipsec_md = iavf_ipsec_crypto_get_pkt_metadata(txq, mb);
2528
2529                 nb_desc_data = mb->nb_segs;
2530                 nb_desc_ctx =
2531                         iavf_calc_context_desc(mb->ol_flags, txq->vlan_flag);
2532                 nb_desc_ipsec = !!(mb->ol_flags & RTE_MBUF_F_TX_SEC_OFFLOAD);
2533
2534                 /**
2535                  * The number of descriptors that must be allocated for
2536                  * a packet equals to the number of the segments of that
2537                  * packet plus the context and ipsec descriptors if needed.
2538                  */
2539                 nb_desc_required = nb_desc_data + nb_desc_ctx + nb_desc_ipsec;
2540
2541                 desc_idx_last = (uint16_t)(desc_idx + nb_desc_required - 1);
2542
2543                 /* wrap descriptor ring */
2544                 if (desc_idx_last >= txq->nb_tx_desc)
2545                         desc_idx_last =
2546                                 (uint16_t)(desc_idx_last - txq->nb_tx_desc);
2547
2548                 PMD_TX_LOG(DEBUG,
2549                         "port_id=%u queue_id=%u tx_first=%u tx_last=%u",
2550                         txq->port_id, txq->queue_id, desc_idx, desc_idx_last);
2551
2552                 if (nb_desc_required > txq->nb_free) {
2553                         if (iavf_xmit_cleanup(txq)) {
2554                                 if (idx == 0)
2555                                         return 0;
2556                                 goto end_of_tx;
2557                         }
2558                         if (unlikely(nb_desc_required > txq->rs_thresh)) {
2559                                 while (nb_desc_required > txq->nb_free) {
2560                                         if (iavf_xmit_cleanup(txq)) {
2561                                                 if (idx == 0)
2562                                                         return 0;
2563                                                 goto end_of_tx;
2564                                         }
2565                                 }
2566                         }
2567                 }
2568
2569                 iavf_build_data_desc_cmd_offset_fields(&ddesc_template, mb,
2570                         txq->vlan_flag);
2571
2572                         /* Setup TX context descriptor if required */
2573                 if (nb_desc_ctx) {
2574                         volatile struct iavf_tx_context_desc *ctx_desc =
2575                                 (volatile struct iavf_tx_context_desc *)
2576                                         &txr[desc_idx];
2577
2578                         /* clear QW0 or the previous writeback value
2579                          * may impact next write
2580                          */
2581                         *(volatile uint64_t *)ctx_desc = 0;
2582
2583                         txn = &txe_ring[txe->next_id];
2584                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
2585
2586                         if (txe->mbuf) {
2587                                 rte_pktmbuf_free_seg(txe->mbuf);
2588                                 txe->mbuf = NULL;
2589                         }
2590
2591                         iavf_fill_context_desc(ctx_desc, mb, ipsec_md, &tlen,
2592                                 txq->vlan_flag);
2593                         IAVF_DUMP_TX_DESC(txq, ctx_desc, desc_idx);
2594
2595                         txe->last_id = desc_idx_last;
2596                         desc_idx = txe->next_id;
2597                         txe = txn;
2598                         }
2599
2600                 if (nb_desc_ipsec) {
2601                         volatile struct iavf_tx_ipsec_desc *ipsec_desc =
2602                                 (volatile struct iavf_tx_ipsec_desc *)
2603                                         &txr[desc_idx];
2604
2605                         txn = &txe_ring[txe->next_id];
2606                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
2607
2608                         if (txe->mbuf) {
2609                                 rte_pktmbuf_free_seg(txe->mbuf);
2610                                 txe->mbuf = NULL;
2611                 }
2612
2613                         iavf_fill_ipsec_desc(ipsec_desc, ipsec_md, &ipseclen);
2614
2615                         IAVF_DUMP_TX_DESC(txq, ipsec_desc, desc_idx);
2616
2617                         txe->last_id = desc_idx_last;
2618                         desc_idx = txe->next_id;
2619                         txe = txn;
2620                 }
2621
2622                 mb_seg = mb;
2623
2624                 do {
2625                         ddesc = (volatile struct iavf_tx_desc *)
2626                                         &txr[desc_idx];
2627
2628                         txn = &txe_ring[txe->next_id];
2629                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
2630
2631                         if (txe->mbuf)
2632                                 rte_pktmbuf_free_seg(txe->mbuf);
2633
2634                         txe->mbuf = mb_seg;
2635                         iavf_fill_data_desc(ddesc, mb_seg,
2636                                         ddesc_template, tlen, ipseclen);
2637
2638                         IAVF_DUMP_TX_DESC(txq, ddesc, desc_idx);
2639
2640                         txe->last_id = desc_idx_last;
2641                         desc_idx = txe->next_id;
2642                         txe = txn;
2643                         mb_seg = mb_seg->next;
2644                 } while (mb_seg);
2645
2646                 /* The last packet data descriptor needs End Of Packet (EOP) */
2647                 ddesc_cmd = IAVF_TX_DESC_CMD_EOP;
2648
2649                 txq->nb_used = (uint16_t)(txq->nb_used + nb_desc_required);
2650                 txq->nb_free = (uint16_t)(txq->nb_free - nb_desc_required);
2651
2652                 if (txq->nb_used >= txq->rs_thresh) {
2653                         PMD_TX_LOG(DEBUG, "Setting RS bit on TXD id="
2654                                    "%4u (port=%d queue=%d)",
2655                                    desc_idx_last, txq->port_id, txq->queue_id);
2656
2657                         ddesc_cmd |= IAVF_TX_DESC_CMD_RS;
2658
2659                         /* Update txq RS bit counters */
2660                         txq->nb_used = 0;
2661                 }
2662
2663                 ddesc->cmd_type_offset_bsz |= rte_cpu_to_le_64(ddesc_cmd <<
2664                                 IAVF_TXD_DATA_QW1_CMD_SHIFT);
2665
2666                 IAVF_DUMP_TX_DESC(txq, ddesc, desc_idx - 1);
2667         }
2668
2669 end_of_tx:
2670         rte_wmb();
2671
2672         PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
2673                    txq->port_id, txq->queue_id, desc_idx, idx);
2674
2675         IAVF_PCI_REG_WRITE_RELAXED(txq->qtx_tail, desc_idx);
2676         txq->tx_tail = desc_idx;
2677
2678         return idx;
2679 }
2680
2681 /* Check if the packet with vlan user priority is transmitted in the
2682  * correct queue.
2683  */
2684 static int
2685 iavf_check_vlan_up2tc(struct iavf_tx_queue *txq, struct rte_mbuf *m)
2686 {
2687         struct rte_eth_dev *dev = &rte_eth_devices[txq->port_id];
2688         struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2689         uint16_t up;
2690
2691         up = m->vlan_tci >> IAVF_VLAN_TAG_PCP_OFFSET;
2692
2693         if (!(vf->qos_cap->cap[txq->tc].tc_prio & BIT(up))) {
2694                 PMD_TX_LOG(ERR, "packet with vlan pcp %u cannot transmit in queue %u\n",
2695                         up, txq->queue_id);
2696                 return -1;
2697         } else {
2698                 return 0;
2699         }
2700 }
2701
2702 /* TX prep functions */
2703 uint16_t
2704 iavf_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
2705               uint16_t nb_pkts)
2706 {
2707         int i, ret;
2708         uint64_t ol_flags;
2709         struct rte_mbuf *m;
2710         struct iavf_tx_queue *txq = tx_queue;
2711         struct rte_eth_dev *dev = &rte_eth_devices[txq->port_id];
2712         struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2713
2714         for (i = 0; i < nb_pkts; i++) {
2715                 m = tx_pkts[i];
2716                 ol_flags = m->ol_flags;
2717
2718                 /* Check condition for nb_segs > IAVF_TX_MAX_MTU_SEG. */
2719                 if (!(ol_flags & RTE_MBUF_F_TX_TCP_SEG)) {
2720                         if (m->nb_segs > IAVF_TX_MAX_MTU_SEG) {
2721                                 rte_errno = EINVAL;
2722                                 return i;
2723                         }
2724                 } else if ((m->tso_segsz < IAVF_MIN_TSO_MSS) ||
2725                            (m->tso_segsz > IAVF_MAX_TSO_MSS)) {
2726                         /* MSS outside the range are considered malicious */
2727                         rte_errno = EINVAL;
2728                         return i;
2729                 }
2730
2731                 if (ol_flags & IAVF_TX_OFFLOAD_NOTSUP_MASK) {
2732                         rte_errno = ENOTSUP;
2733                         return i;
2734                 }
2735
2736 #ifdef RTE_ETHDEV_DEBUG_TX
2737                 ret = rte_validate_tx_offload(m);
2738                 if (ret != 0) {
2739                         rte_errno = -ret;
2740                         return i;
2741                 }
2742 #endif
2743                 ret = rte_net_intel_cksum_prepare(m);
2744                 if (ret != 0) {
2745                         rte_errno = -ret;
2746                         return i;
2747                 }
2748
2749                 if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_QOS &&
2750                     ol_flags & (RTE_MBUF_F_RX_VLAN_STRIPPED | RTE_MBUF_F_RX_VLAN)) {
2751                         ret = iavf_check_vlan_up2tc(txq, m);
2752                         if (ret != 0) {
2753                                 rte_errno = -ret;
2754                                 return i;
2755                         }
2756                 }
2757         }
2758
2759         return i;
2760 }
2761
2762 /* choose rx function*/
2763 void
2764 iavf_set_rx_function(struct rte_eth_dev *dev)
2765 {
2766         struct iavf_adapter *adapter =
2767                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2768         struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2769
2770 #ifdef RTE_ARCH_X86
2771         struct iavf_rx_queue *rxq;
2772         int i;
2773         int check_ret;
2774         bool use_avx2 = false;
2775         bool use_avx512 = false;
2776         bool use_flex = false;
2777
2778         check_ret = iavf_rx_vec_dev_check(dev);
2779         if (check_ret >= 0 &&
2780             rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
2781                 if ((rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
2782                      rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) &&
2783                     rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256)
2784                         use_avx2 = true;
2785
2786 #ifdef CC_AVX512_SUPPORT
2787                 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 &&
2788                     rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1 &&
2789                     rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512)
2790                         use_avx512 = true;
2791 #endif
2792
2793                 if (vf->vf_res->vf_cap_flags &
2794                         VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC)
2795                         use_flex = true;
2796
2797                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2798                         rxq = dev->data->rx_queues[i];
2799                         (void)iavf_rxq_vec_setup(rxq);
2800                 }
2801
2802                 if (dev->data->scattered_rx) {
2803                         if (!use_avx512) {
2804                                 PMD_DRV_LOG(DEBUG,
2805                                             "Using %sVector Scattered Rx (port %d).",
2806                                             use_avx2 ? "avx2 " : "",
2807                                             dev->data->port_id);
2808                         } else {
2809                                 if (check_ret == IAVF_VECTOR_PATH)
2810                                         PMD_DRV_LOG(DEBUG,
2811                                                     "Using AVX512 Vector Scattered Rx (port %d).",
2812                                                     dev->data->port_id);
2813                                 else
2814                                         PMD_DRV_LOG(DEBUG,
2815                                                     "Using AVX512 OFFLOAD Vector Scattered Rx (port %d).",
2816                                                     dev->data->port_id);
2817                         }
2818                         if (use_flex) {
2819                                 dev->rx_pkt_burst = use_avx2 ?
2820                                         iavf_recv_scattered_pkts_vec_avx2_flex_rxd :
2821                                         iavf_recv_scattered_pkts_vec_flex_rxd;
2822 #ifdef CC_AVX512_SUPPORT
2823                                 if (use_avx512) {
2824                                         if (check_ret == IAVF_VECTOR_PATH)
2825                                                 dev->rx_pkt_burst =
2826                                                         iavf_recv_scattered_pkts_vec_avx512_flex_rxd;
2827                                         else
2828                                                 dev->rx_pkt_burst =
2829                                                         iavf_recv_scattered_pkts_vec_avx512_flex_rxd_offload;
2830                                 }
2831 #endif
2832                         } else {
2833                                 dev->rx_pkt_burst = use_avx2 ?
2834                                         iavf_recv_scattered_pkts_vec_avx2 :
2835                                         iavf_recv_scattered_pkts_vec;
2836 #ifdef CC_AVX512_SUPPORT
2837                                 if (use_avx512) {
2838                                         if (check_ret == IAVF_VECTOR_PATH)
2839                                                 dev->rx_pkt_burst =
2840                                                         iavf_recv_scattered_pkts_vec_avx512;
2841                                         else
2842                                                 dev->rx_pkt_burst =
2843                                                         iavf_recv_scattered_pkts_vec_avx512_offload;
2844                                 }
2845 #endif
2846                         }
2847                 } else {
2848                         if (!use_avx512) {
2849                                 PMD_DRV_LOG(DEBUG, "Using %sVector Rx (port %d).",
2850                                             use_avx2 ? "avx2 " : "",
2851                                             dev->data->port_id);
2852                         } else {
2853                                 if (check_ret == IAVF_VECTOR_PATH)
2854                                         PMD_DRV_LOG(DEBUG,
2855                                                     "Using AVX512 Vector Rx (port %d).",
2856                                                     dev->data->port_id);
2857                                 else
2858                                         PMD_DRV_LOG(DEBUG,
2859                                                     "Using AVX512 OFFLOAD Vector Rx (port %d).",
2860                                                     dev->data->port_id);
2861                         }
2862                         if (use_flex) {
2863                                 dev->rx_pkt_burst = use_avx2 ?
2864                                         iavf_recv_pkts_vec_avx2_flex_rxd :
2865                                         iavf_recv_pkts_vec_flex_rxd;
2866 #ifdef CC_AVX512_SUPPORT
2867                                 if (use_avx512) {
2868                                         if (check_ret == IAVF_VECTOR_PATH)
2869                                                 dev->rx_pkt_burst =
2870                                                         iavf_recv_pkts_vec_avx512_flex_rxd;
2871                                         else
2872                                                 dev->rx_pkt_burst =
2873                                                         iavf_recv_pkts_vec_avx512_flex_rxd_offload;
2874                                 }
2875 #endif
2876                         } else {
2877                                 dev->rx_pkt_burst = use_avx2 ?
2878                                         iavf_recv_pkts_vec_avx2 :
2879                                         iavf_recv_pkts_vec;
2880 #ifdef CC_AVX512_SUPPORT
2881                                 if (use_avx512) {
2882                                         if (check_ret == IAVF_VECTOR_PATH)
2883                                                 dev->rx_pkt_burst =
2884                                                         iavf_recv_pkts_vec_avx512;
2885                                         else
2886                                                 dev->rx_pkt_burst =
2887                                                         iavf_recv_pkts_vec_avx512_offload;
2888                                 }
2889 #endif
2890                         }
2891                 }
2892
2893                 return;
2894         }
2895
2896 #endif
2897         if (dev->data->scattered_rx) {
2898                 PMD_DRV_LOG(DEBUG, "Using a Scattered Rx callback (port=%d).",
2899                             dev->data->port_id);
2900                 if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC)
2901                         dev->rx_pkt_burst = iavf_recv_scattered_pkts_flex_rxd;
2902                 else
2903                         dev->rx_pkt_burst = iavf_recv_scattered_pkts;
2904         } else if (adapter->rx_bulk_alloc_allowed) {
2905                 PMD_DRV_LOG(DEBUG, "Using bulk Rx callback (port=%d).",
2906                             dev->data->port_id);
2907                 dev->rx_pkt_burst = iavf_recv_pkts_bulk_alloc;
2908         } else {
2909                 PMD_DRV_LOG(DEBUG, "Using Basic Rx callback (port=%d).",
2910                             dev->data->port_id);
2911                 if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC)
2912                         dev->rx_pkt_burst = iavf_recv_pkts_flex_rxd;
2913                 else
2914                         dev->rx_pkt_burst = iavf_recv_pkts;
2915         }
2916 }
2917
2918 /* choose tx function*/
2919 void
2920 iavf_set_tx_function(struct rte_eth_dev *dev)
2921 {
2922 #ifdef RTE_ARCH_X86
2923         struct iavf_tx_queue *txq;
2924         int i;
2925         int check_ret;
2926         bool use_sse = false;
2927         bool use_avx2 = false;
2928         bool use_avx512 = false;
2929
2930         check_ret = iavf_tx_vec_dev_check(dev);
2931
2932         if (check_ret >= 0 &&
2933             rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
2934                 /* SSE and AVX2 not support offload path yet. */
2935                 if (check_ret == IAVF_VECTOR_PATH) {
2936                         use_sse = true;
2937                         if ((rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
2938                              rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) &&
2939                             rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256)
2940                                 use_avx2 = true;
2941                 }
2942 #ifdef CC_AVX512_SUPPORT
2943                 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 &&
2944                     rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1 &&
2945                     rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512)
2946                         use_avx512 = true;
2947 #endif
2948
2949                 if (!use_sse && !use_avx2 && !use_avx512)
2950                         goto normal;
2951
2952                 if (!use_avx512) {
2953                         PMD_DRV_LOG(DEBUG, "Using %sVector Tx (port %d).",
2954                                     use_avx2 ? "avx2 " : "",
2955                                     dev->data->port_id);
2956                         dev->tx_pkt_burst = use_avx2 ?
2957                                             iavf_xmit_pkts_vec_avx2 :
2958                                             iavf_xmit_pkts_vec;
2959                 }
2960                 dev->tx_pkt_prepare = NULL;
2961 #ifdef CC_AVX512_SUPPORT
2962                 if (use_avx512) {
2963                         if (check_ret == IAVF_VECTOR_PATH) {
2964                                 dev->tx_pkt_burst = iavf_xmit_pkts_vec_avx512;
2965                                 PMD_DRV_LOG(DEBUG, "Using AVX512 Vector Tx (port %d).",
2966                                             dev->data->port_id);
2967                         } else {
2968                                 dev->tx_pkt_burst = iavf_xmit_pkts_vec_avx512_offload;
2969                                 dev->tx_pkt_prepare = iavf_prep_pkts;
2970                                 PMD_DRV_LOG(DEBUG, "Using AVX512 OFFLOAD Vector Tx (port %d).",
2971                                             dev->data->port_id);
2972                         }
2973                 }
2974 #endif
2975
2976                 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2977                         txq = dev->data->tx_queues[i];
2978                         if (!txq)
2979                                 continue;
2980 #ifdef CC_AVX512_SUPPORT
2981                         if (use_avx512)
2982                                 iavf_txq_vec_setup_avx512(txq);
2983                         else
2984                                 iavf_txq_vec_setup(txq);
2985 #else
2986                         iavf_txq_vec_setup(txq);
2987 #endif
2988                 }
2989
2990                 return;
2991         }
2992
2993 normal:
2994 #endif
2995         PMD_DRV_LOG(DEBUG, "Using Basic Tx callback (port=%d).",
2996                     dev->data->port_id);
2997         dev->tx_pkt_burst = iavf_xmit_pkts;
2998         dev->tx_pkt_prepare = iavf_prep_pkts;
2999 }
3000
3001 static int
3002 iavf_tx_done_cleanup_full(struct iavf_tx_queue *txq,
3003                         uint32_t free_cnt)
3004 {
3005         struct iavf_tx_entry *swr_ring = txq->sw_ring;
3006         uint16_t i, tx_last, tx_id;
3007         uint16_t nb_tx_free_last;
3008         uint16_t nb_tx_to_clean;
3009         uint32_t pkt_cnt;
3010
3011         /* Start free mbuf from the next of tx_tail */
3012         tx_last = txq->tx_tail;
3013         tx_id  = swr_ring[tx_last].next_id;
3014
3015         if (txq->nb_free == 0 && iavf_xmit_cleanup(txq))
3016                 return 0;
3017
3018         nb_tx_to_clean = txq->nb_free;
3019         nb_tx_free_last = txq->nb_free;
3020         if (!free_cnt)
3021                 free_cnt = txq->nb_tx_desc;
3022
3023         /* Loop through swr_ring to count the amount of
3024          * freeable mubfs and packets.
3025          */
3026         for (pkt_cnt = 0; pkt_cnt < free_cnt; ) {
3027                 for (i = 0; i < nb_tx_to_clean &&
3028                         pkt_cnt < free_cnt &&
3029                         tx_id != tx_last; i++) {
3030                         if (swr_ring[tx_id].mbuf != NULL) {
3031                                 rte_pktmbuf_free_seg(swr_ring[tx_id].mbuf);
3032                                 swr_ring[tx_id].mbuf = NULL;
3033
3034                                 /*
3035                                  * last segment in the packet,
3036                                  * increment packet count
3037                                  */
3038                                 pkt_cnt += (swr_ring[tx_id].last_id == tx_id);
3039                         }
3040
3041                         tx_id = swr_ring[tx_id].next_id;
3042                 }
3043
3044                 if (txq->rs_thresh > txq->nb_tx_desc -
3045                         txq->nb_free || tx_id == tx_last)
3046                         break;
3047
3048                 if (pkt_cnt < free_cnt) {
3049                         if (iavf_xmit_cleanup(txq))
3050                                 break;
3051
3052                         nb_tx_to_clean = txq->nb_free - nb_tx_free_last;
3053                         nb_tx_free_last = txq->nb_free;
3054                 }
3055         }
3056
3057         return (int)pkt_cnt;
3058 }
3059
3060 int
3061 iavf_dev_tx_done_cleanup(void *txq, uint32_t free_cnt)
3062 {
3063         struct iavf_tx_queue *q = (struct iavf_tx_queue *)txq;
3064
3065         return iavf_tx_done_cleanup_full(q, free_cnt);
3066 }
3067
3068 void
3069 iavf_dev_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
3070                      struct rte_eth_rxq_info *qinfo)
3071 {
3072         struct iavf_rx_queue *rxq;
3073
3074         rxq = dev->data->rx_queues[queue_id];
3075
3076         qinfo->mp = rxq->mp;
3077         qinfo->scattered_rx = dev->data->scattered_rx;
3078         qinfo->nb_desc = rxq->nb_rx_desc;
3079
3080         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
3081         qinfo->conf.rx_drop_en = true;
3082         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
3083 }
3084
3085 void
3086 iavf_dev_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
3087                      struct rte_eth_txq_info *qinfo)
3088 {
3089         struct iavf_tx_queue *txq;
3090
3091         txq = dev->data->tx_queues[queue_id];
3092
3093         qinfo->nb_desc = txq->nb_tx_desc;
3094
3095         qinfo->conf.tx_free_thresh = txq->free_thresh;
3096         qinfo->conf.tx_rs_thresh = txq->rs_thresh;
3097         qinfo->conf.offloads = txq->offloads;
3098         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
3099 }
3100
3101 /* Get the number of used descriptors of a rx queue */
3102 uint32_t
3103 iavf_dev_rxq_count(void *rx_queue)
3104 {
3105 #define IAVF_RXQ_SCAN_INTERVAL 4
3106         volatile union iavf_rx_desc *rxdp;
3107         struct iavf_rx_queue *rxq;
3108         uint16_t desc = 0;
3109
3110         rxq = rx_queue;
3111         rxdp = &rxq->rx_ring[rxq->rx_tail];
3112
3113         while ((desc < rxq->nb_rx_desc) &&
3114                ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
3115                  IAVF_RXD_QW1_STATUS_MASK) >> IAVF_RXD_QW1_STATUS_SHIFT) &
3116                (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)) {
3117                 /* Check the DD bit of a rx descriptor of each 4 in a group,
3118                  * to avoid checking too frequently and downgrading performance
3119                  * too much.
3120                  */
3121                 desc += IAVF_RXQ_SCAN_INTERVAL;
3122                 rxdp += IAVF_RXQ_SCAN_INTERVAL;
3123                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
3124                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
3125                                         desc - rxq->nb_rx_desc]);
3126         }
3127
3128         return desc;
3129 }
3130
3131 int
3132 iavf_dev_rx_desc_status(void *rx_queue, uint16_t offset)
3133 {
3134         struct iavf_rx_queue *rxq = rx_queue;
3135         volatile uint64_t *status;
3136         uint64_t mask;
3137         uint32_t desc;
3138
3139         if (unlikely(offset >= rxq->nb_rx_desc))
3140                 return -EINVAL;
3141
3142         if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
3143                 return RTE_ETH_RX_DESC_UNAVAIL;
3144
3145         desc = rxq->rx_tail + offset;
3146         if (desc >= rxq->nb_rx_desc)
3147                 desc -= rxq->nb_rx_desc;
3148
3149         status = &rxq->rx_ring[desc].wb.qword1.status_error_len;
3150         mask = rte_le_to_cpu_64((1ULL << IAVF_RX_DESC_STATUS_DD_SHIFT)
3151                 << IAVF_RXD_QW1_STATUS_SHIFT);
3152         if (*status & mask)
3153                 return RTE_ETH_RX_DESC_DONE;
3154
3155         return RTE_ETH_RX_DESC_AVAIL;
3156 }
3157
3158 int
3159 iavf_dev_tx_desc_status(void *tx_queue, uint16_t offset)
3160 {
3161         struct iavf_tx_queue *txq = tx_queue;
3162         volatile uint64_t *status;
3163         uint64_t mask, expect;
3164         uint32_t desc;
3165
3166         if (unlikely(offset >= txq->nb_tx_desc))
3167                 return -EINVAL;
3168
3169         desc = txq->tx_tail + offset;
3170         /* go to next desc that has the RS bit */
3171         desc = ((desc + txq->rs_thresh - 1) / txq->rs_thresh) *
3172                 txq->rs_thresh;
3173         if (desc >= txq->nb_tx_desc) {
3174                 desc -= txq->nb_tx_desc;
3175                 if (desc >= txq->nb_tx_desc)
3176                         desc -= txq->nb_tx_desc;
3177         }
3178
3179         status = &txq->tx_ring[desc].cmd_type_offset_bsz;
3180         mask = rte_le_to_cpu_64(IAVF_TXD_QW1_DTYPE_MASK);
3181         expect = rte_cpu_to_le_64(
3182                  IAVF_TX_DESC_DTYPE_DESC_DONE << IAVF_TXD_QW1_DTYPE_SHIFT);
3183         if ((*status & mask) == expect)
3184                 return RTE_ETH_TX_DESC_DONE;
3185
3186         return RTE_ETH_TX_DESC_FULL;
3187 }
3188
3189 static inline uint32_t
3190 iavf_get_default_ptype(uint16_t ptype)
3191 {
3192         static const uint32_t ptype_tbl[IAVF_MAX_PKT_TYPE]
3193                 __rte_cache_aligned = {
3194                 /* L2 types */
3195                 /* [0] reserved */
3196                 [1] = RTE_PTYPE_L2_ETHER,
3197                 [2] = RTE_PTYPE_L2_ETHER_TIMESYNC,
3198                 /* [3] - [5] reserved */
3199                 [6] = RTE_PTYPE_L2_ETHER_LLDP,
3200                 /* [7] - [10] reserved */
3201                 [11] = RTE_PTYPE_L2_ETHER_ARP,
3202                 /* [12] - [21] reserved */
3203
3204                 /* Non tunneled IPv4 */
3205                 [22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3206                        RTE_PTYPE_L4_FRAG,
3207                 [23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3208                        RTE_PTYPE_L4_NONFRAG,
3209                 [24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3210                        RTE_PTYPE_L4_UDP,
3211                 /* [25] reserved */
3212                 [26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3213                        RTE_PTYPE_L4_TCP,
3214                 [27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3215                        RTE_PTYPE_L4_SCTP,
3216                 [28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3217                        RTE_PTYPE_L4_ICMP,
3218
3219                 /* IPv4 --> IPv4 */
3220                 [29] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3221                        RTE_PTYPE_TUNNEL_IP |
3222                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3223                        RTE_PTYPE_INNER_L4_FRAG,
3224                 [30] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3225                        RTE_PTYPE_TUNNEL_IP |
3226                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3227                        RTE_PTYPE_INNER_L4_NONFRAG,
3228                 [31] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3229                        RTE_PTYPE_TUNNEL_IP |
3230                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3231                        RTE_PTYPE_INNER_L4_UDP,
3232                 /* [32] reserved */
3233                 [33] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3234                        RTE_PTYPE_TUNNEL_IP |
3235                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3236                        RTE_PTYPE_INNER_L4_TCP,
3237                 [34] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3238                        RTE_PTYPE_TUNNEL_IP |
3239                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3240                        RTE_PTYPE_INNER_L4_SCTP,
3241                 [35] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3242                        RTE_PTYPE_TUNNEL_IP |
3243                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3244                        RTE_PTYPE_INNER_L4_ICMP,
3245
3246                 /* IPv4 --> IPv6 */
3247                 [36] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3248                        RTE_PTYPE_TUNNEL_IP |
3249                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3250                        RTE_PTYPE_INNER_L4_FRAG,
3251                 [37] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3252                        RTE_PTYPE_TUNNEL_IP |
3253                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3254                        RTE_PTYPE_INNER_L4_NONFRAG,
3255                 [38] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3256                        RTE_PTYPE_TUNNEL_IP |
3257                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3258                        RTE_PTYPE_INNER_L4_UDP,
3259                 /* [39] reserved */
3260                 [40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3261                        RTE_PTYPE_TUNNEL_IP |
3262                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3263                        RTE_PTYPE_INNER_L4_TCP,
3264                 [41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3265                        RTE_PTYPE_TUNNEL_IP |
3266                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3267                        RTE_PTYPE_INNER_L4_SCTP,
3268                 [42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3269                        RTE_PTYPE_TUNNEL_IP |
3270                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3271                        RTE_PTYPE_INNER_L4_ICMP,
3272
3273                 /* IPv4 --> GRE/Teredo/VXLAN */
3274                 [43] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3275                        RTE_PTYPE_TUNNEL_GRENAT,
3276
3277                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv4 */
3278                 [44] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3279                        RTE_PTYPE_TUNNEL_GRENAT |
3280                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3281                        RTE_PTYPE_INNER_L4_FRAG,
3282                 [45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3283                        RTE_PTYPE_TUNNEL_GRENAT |
3284                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3285                        RTE_PTYPE_INNER_L4_NONFRAG,
3286                 [46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3287                        RTE_PTYPE_TUNNEL_GRENAT |
3288                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3289                        RTE_PTYPE_INNER_L4_UDP,
3290                 /* [47] reserved */
3291                 [48] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3292                        RTE_PTYPE_TUNNEL_GRENAT |
3293                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3294                        RTE_PTYPE_INNER_L4_TCP,
3295                 [49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3296                        RTE_PTYPE_TUNNEL_GRENAT |
3297                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3298                        RTE_PTYPE_INNER_L4_SCTP,
3299                 [50] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3300                        RTE_PTYPE_TUNNEL_GRENAT |
3301                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3302                        RTE_PTYPE_INNER_L4_ICMP,
3303
3304                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv6 */
3305                 [51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3306                        RTE_PTYPE_TUNNEL_GRENAT |
3307                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3308                        RTE_PTYPE_INNER_L4_FRAG,
3309                 [52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3310                        RTE_PTYPE_TUNNEL_GRENAT |
3311                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3312                        RTE_PTYPE_INNER_L4_NONFRAG,
3313                 [53] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3314                        RTE_PTYPE_TUNNEL_GRENAT |
3315                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3316                        RTE_PTYPE_INNER_L4_UDP,
3317                 /* [54] reserved */
3318                 [55] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3319                        RTE_PTYPE_TUNNEL_GRENAT |
3320                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3321                        RTE_PTYPE_INNER_L4_TCP,
3322                 [56] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3323                        RTE_PTYPE_TUNNEL_GRENAT |
3324                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3325                        RTE_PTYPE_INNER_L4_SCTP,
3326                 [57] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3327                        RTE_PTYPE_TUNNEL_GRENAT |
3328                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3329                        RTE_PTYPE_INNER_L4_ICMP,
3330
3331                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC */
3332                 [58] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3333                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
3334
3335                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
3336                 [59] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3337                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3338                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3339                        RTE_PTYPE_INNER_L4_FRAG,
3340                 [60] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3341                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3342                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3343                        RTE_PTYPE_INNER_L4_NONFRAG,
3344                 [61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3345                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3346                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3347                        RTE_PTYPE_INNER_L4_UDP,
3348                 /* [62] reserved */
3349                 [63] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3350                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3351                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3352                        RTE_PTYPE_INNER_L4_TCP,
3353                 [64] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3354                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3355                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3356                        RTE_PTYPE_INNER_L4_SCTP,
3357                 [65] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3358                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3359                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3360                        RTE_PTYPE_INNER_L4_ICMP,
3361
3362                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
3363                 [66] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3364                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3365                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3366                        RTE_PTYPE_INNER_L4_FRAG,
3367                 [67] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3368                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3369                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3370                        RTE_PTYPE_INNER_L4_NONFRAG,
3371                 [68] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3372                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3373                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3374                        RTE_PTYPE_INNER_L4_UDP,
3375                 /* [69] reserved */
3376                 [70] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3377                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3378                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3379                        RTE_PTYPE_INNER_L4_TCP,
3380                 [71] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3381                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3382                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3383                        RTE_PTYPE_INNER_L4_SCTP,
3384                 [72] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3385                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3386                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3387                        RTE_PTYPE_INNER_L4_ICMP,
3388                 /* [73] - [87] reserved */
3389
3390                 /* Non tunneled IPv6 */
3391                 [88] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3392                        RTE_PTYPE_L4_FRAG,
3393                 [89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3394                        RTE_PTYPE_L4_NONFRAG,
3395                 [90] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3396                        RTE_PTYPE_L4_UDP,
3397                 /* [91] reserved */
3398                 [92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3399                        RTE_PTYPE_L4_TCP,
3400                 [93] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3401                        RTE_PTYPE_L4_SCTP,
3402                 [94] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3403                        RTE_PTYPE_L4_ICMP,
3404
3405                 /* IPv6 --> IPv4 */
3406                 [95] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3407                        RTE_PTYPE_TUNNEL_IP |
3408                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3409                        RTE_PTYPE_INNER_L4_FRAG,
3410                 [96] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3411                        RTE_PTYPE_TUNNEL_IP |
3412                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3413                        RTE_PTYPE_INNER_L4_NONFRAG,
3414                 [97] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3415                        RTE_PTYPE_TUNNEL_IP |
3416                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3417                        RTE_PTYPE_INNER_L4_UDP,
3418                 /* [98] reserved */
3419                 [99] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3420                        RTE_PTYPE_TUNNEL_IP |
3421                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3422                        RTE_PTYPE_INNER_L4_TCP,
3423                 [100] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3424                         RTE_PTYPE_TUNNEL_IP |
3425                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3426                         RTE_PTYPE_INNER_L4_SCTP,
3427                 [101] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3428                         RTE_PTYPE_TUNNEL_IP |
3429                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3430                         RTE_PTYPE_INNER_L4_ICMP,
3431
3432                 /* IPv6 --> IPv6 */
3433                 [102] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3434                         RTE_PTYPE_TUNNEL_IP |
3435                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3436                         RTE_PTYPE_INNER_L4_FRAG,
3437                 [103] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3438                         RTE_PTYPE_TUNNEL_IP |
3439                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3440                         RTE_PTYPE_INNER_L4_NONFRAG,
3441                 [104] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3442                         RTE_PTYPE_TUNNEL_IP |
3443                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3444                         RTE_PTYPE_INNER_L4_UDP,
3445                 /* [105] reserved */
3446                 [106] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3447                         RTE_PTYPE_TUNNEL_IP |
3448                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3449                         RTE_PTYPE_INNER_L4_TCP,
3450                 [107] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3451                         RTE_PTYPE_TUNNEL_IP |
3452                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3453                         RTE_PTYPE_INNER_L4_SCTP,
3454                 [108] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3455                         RTE_PTYPE_TUNNEL_IP |
3456                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3457                         RTE_PTYPE_INNER_L4_ICMP,
3458
3459                 /* IPv6 --> GRE/Teredo/VXLAN */
3460                 [109] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3461                         RTE_PTYPE_TUNNEL_GRENAT,
3462
3463                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv4 */
3464                 [110] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3465                         RTE_PTYPE_TUNNEL_GRENAT |
3466                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3467                         RTE_PTYPE_INNER_L4_FRAG,
3468                 [111] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3469                         RTE_PTYPE_TUNNEL_GRENAT |
3470                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3471                         RTE_PTYPE_INNER_L4_NONFRAG,
3472                 [112] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3473                         RTE_PTYPE_TUNNEL_GRENAT |
3474                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3475                         RTE_PTYPE_INNER_L4_UDP,
3476                 /* [113] reserved */
3477                 [114] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3478                         RTE_PTYPE_TUNNEL_GRENAT |
3479                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3480                         RTE_PTYPE_INNER_L4_TCP,
3481                 [115] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3482                         RTE_PTYPE_TUNNEL_GRENAT |
3483                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3484                         RTE_PTYPE_INNER_L4_SCTP,
3485                 [116] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3486                         RTE_PTYPE_TUNNEL_GRENAT |
3487                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3488                         RTE_PTYPE_INNER_L4_ICMP,
3489
3490                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv6 */
3491                 [117] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3492                         RTE_PTYPE_TUNNEL_GRENAT |
3493                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3494                         RTE_PTYPE_INNER_L4_FRAG,
3495                 [118] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3496                         RTE_PTYPE_TUNNEL_GRENAT |
3497                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3498                         RTE_PTYPE_INNER_L4_NONFRAG,
3499                 [119] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3500                         RTE_PTYPE_TUNNEL_GRENAT |
3501                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3502                         RTE_PTYPE_INNER_L4_UDP,
3503                 /* [120] reserved */
3504                 [121] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3505                         RTE_PTYPE_TUNNEL_GRENAT |
3506                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3507                         RTE_PTYPE_INNER_L4_TCP,
3508                 [122] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3509                         RTE_PTYPE_TUNNEL_GRENAT |
3510                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3511                         RTE_PTYPE_INNER_L4_SCTP,
3512                 [123] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3513                         RTE_PTYPE_TUNNEL_GRENAT |
3514                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3515                         RTE_PTYPE_INNER_L4_ICMP,
3516
3517                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC */
3518                 [124] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3519                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
3520
3521                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
3522                 [125] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3523                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3524                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3525                         RTE_PTYPE_INNER_L4_FRAG,
3526                 [126] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3527                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3528                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3529                         RTE_PTYPE_INNER_L4_NONFRAG,
3530                 [127] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3531                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3532                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3533                         RTE_PTYPE_INNER_L4_UDP,
3534                 /* [128] reserved */
3535                 [129] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3536                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3537                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3538                         RTE_PTYPE_INNER_L4_TCP,
3539                 [130] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3540                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3541                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3542                         RTE_PTYPE_INNER_L4_SCTP,
3543                 [131] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3544                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3545                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3546                         RTE_PTYPE_INNER_L4_ICMP,
3547
3548                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
3549                 [132] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3550                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3551                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3552                         RTE_PTYPE_INNER_L4_FRAG,
3553                 [133] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3554                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3555                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3556                         RTE_PTYPE_INNER_L4_NONFRAG,
3557                 [134] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3558                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3559                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3560                         RTE_PTYPE_INNER_L4_UDP,
3561                 /* [135] reserved */
3562                 [136] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3563                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3564                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3565                         RTE_PTYPE_INNER_L4_TCP,
3566                 [137] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3567                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3568                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3569                         RTE_PTYPE_INNER_L4_SCTP,
3570                 [138] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3571                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3572                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3573                         RTE_PTYPE_INNER_L4_ICMP,
3574                 /* [139] - [299] reserved */
3575
3576                 /* PPPoE */
3577                 [300] = RTE_PTYPE_L2_ETHER_PPPOE,
3578                 [301] = RTE_PTYPE_L2_ETHER_PPPOE,
3579
3580                 /* PPPoE --> IPv4 */
3581                 [302] = RTE_PTYPE_L2_ETHER_PPPOE |
3582                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3583                         RTE_PTYPE_L4_FRAG,
3584                 [303] = RTE_PTYPE_L2_ETHER_PPPOE |
3585                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3586                         RTE_PTYPE_L4_NONFRAG,
3587                 [304] = RTE_PTYPE_L2_ETHER_PPPOE |
3588                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3589                         RTE_PTYPE_L4_UDP,
3590                 [305] = RTE_PTYPE_L2_ETHER_PPPOE |
3591                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3592                         RTE_PTYPE_L4_TCP,
3593                 [306] = RTE_PTYPE_L2_ETHER_PPPOE |
3594                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3595                         RTE_PTYPE_L4_SCTP,
3596                 [307] = RTE_PTYPE_L2_ETHER_PPPOE |
3597                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3598                         RTE_PTYPE_L4_ICMP,
3599
3600                 /* PPPoE --> IPv6 */
3601                 [308] = RTE_PTYPE_L2_ETHER_PPPOE |
3602                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3603                         RTE_PTYPE_L4_FRAG,
3604                 [309] = RTE_PTYPE_L2_ETHER_PPPOE |
3605                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3606                         RTE_PTYPE_L4_NONFRAG,
3607                 [310] = RTE_PTYPE_L2_ETHER_PPPOE |
3608                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3609                         RTE_PTYPE_L4_UDP,
3610                 [311] = RTE_PTYPE_L2_ETHER_PPPOE |
3611                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3612                         RTE_PTYPE_L4_TCP,
3613                 [312] = RTE_PTYPE_L2_ETHER_PPPOE |
3614                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3615                         RTE_PTYPE_L4_SCTP,
3616                 [313] = RTE_PTYPE_L2_ETHER_PPPOE |
3617                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3618                         RTE_PTYPE_L4_ICMP,
3619                 /* [314] - [324] reserved */
3620
3621                 /* IPv4/IPv6 --> GTPC/GTPU */
3622                 [325] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3623                         RTE_PTYPE_TUNNEL_GTPC,
3624                 [326] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3625                         RTE_PTYPE_TUNNEL_GTPC,
3626                 [327] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3627                         RTE_PTYPE_TUNNEL_GTPC,
3628                 [328] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3629                         RTE_PTYPE_TUNNEL_GTPC,
3630                 [329] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3631                         RTE_PTYPE_TUNNEL_GTPU,
3632                 [330] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3633                         RTE_PTYPE_TUNNEL_GTPU,
3634
3635                 /* IPv4 --> GTPU --> IPv4 */
3636                 [331] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3637                         RTE_PTYPE_TUNNEL_GTPU |
3638                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3639                         RTE_PTYPE_INNER_L4_FRAG,
3640                 [332] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3641                         RTE_PTYPE_TUNNEL_GTPU |
3642                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3643                         RTE_PTYPE_INNER_L4_NONFRAG,
3644                 [333] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3645                         RTE_PTYPE_TUNNEL_GTPU |
3646                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3647                         RTE_PTYPE_INNER_L4_UDP,
3648                 [334] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3649                         RTE_PTYPE_TUNNEL_GTPU |
3650                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3651                         RTE_PTYPE_INNER_L4_TCP,
3652                 [335] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3653                         RTE_PTYPE_TUNNEL_GTPU |
3654                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3655                         RTE_PTYPE_INNER_L4_ICMP,
3656
3657                 /* IPv6 --> GTPU --> IPv4 */
3658                 [336] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3659                         RTE_PTYPE_TUNNEL_GTPU |
3660                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3661                         RTE_PTYPE_INNER_L4_FRAG,
3662                 [337] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3663                         RTE_PTYPE_TUNNEL_GTPU |
3664                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3665                         RTE_PTYPE_INNER_L4_NONFRAG,
3666                 [338] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3667                         RTE_PTYPE_TUNNEL_GTPU |
3668                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3669                         RTE_PTYPE_INNER_L4_UDP,
3670                 [339] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3671                         RTE_PTYPE_TUNNEL_GTPU |
3672                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3673                         RTE_PTYPE_INNER_L4_TCP,
3674                 [340] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3675                         RTE_PTYPE_TUNNEL_GTPU |
3676                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3677                         RTE_PTYPE_INNER_L4_ICMP,
3678
3679                 /* IPv4 --> GTPU --> IPv6 */
3680                 [341] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3681                         RTE_PTYPE_TUNNEL_GTPU |
3682                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3683                         RTE_PTYPE_INNER_L4_FRAG,
3684                 [342] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3685                         RTE_PTYPE_TUNNEL_GTPU |
3686                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3687                         RTE_PTYPE_INNER_L4_NONFRAG,
3688                 [343] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3689                         RTE_PTYPE_TUNNEL_GTPU |
3690                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3691                         RTE_PTYPE_INNER_L4_UDP,
3692                 [344] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3693                         RTE_PTYPE_TUNNEL_GTPU |
3694                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3695                         RTE_PTYPE_INNER_L4_TCP,
3696                 [345] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3697                         RTE_PTYPE_TUNNEL_GTPU |
3698                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3699                         RTE_PTYPE_INNER_L4_ICMP,
3700
3701                 /* IPv6 --> GTPU --> IPv6 */
3702                 [346] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3703                         RTE_PTYPE_TUNNEL_GTPU |
3704                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3705                         RTE_PTYPE_INNER_L4_FRAG,
3706                 [347] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3707                         RTE_PTYPE_TUNNEL_GTPU |
3708                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3709                         RTE_PTYPE_INNER_L4_NONFRAG,
3710                 [348] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3711                         RTE_PTYPE_TUNNEL_GTPU |
3712                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3713                         RTE_PTYPE_INNER_L4_UDP,
3714                 [349] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3715                         RTE_PTYPE_TUNNEL_GTPU |
3716                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3717                         RTE_PTYPE_INNER_L4_TCP,
3718                 [350] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3719                         RTE_PTYPE_TUNNEL_GTPU |
3720                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3721                         RTE_PTYPE_INNER_L4_ICMP,
3722
3723                 /* IPv4 --> UDP ECPRI */
3724                 [372] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3725                         RTE_PTYPE_L4_UDP,
3726                 [373] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3727                         RTE_PTYPE_L4_UDP,
3728                 [374] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3729                         RTE_PTYPE_L4_UDP,
3730                 [375] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3731                         RTE_PTYPE_L4_UDP,
3732                 [376] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3733                         RTE_PTYPE_L4_UDP,
3734                 [377] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3735                         RTE_PTYPE_L4_UDP,
3736                 [378] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3737                         RTE_PTYPE_L4_UDP,
3738                 [379] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3739                         RTE_PTYPE_L4_UDP,
3740                 [380] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3741                         RTE_PTYPE_L4_UDP,
3742                 [381] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3743                         RTE_PTYPE_L4_UDP,
3744
3745                 /* IPV6 --> UDP ECPRI */
3746                 [382] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3747                         RTE_PTYPE_L4_UDP,
3748                 [383] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3749                         RTE_PTYPE_L4_UDP,
3750                 [384] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3751                         RTE_PTYPE_L4_UDP,
3752                 [385] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3753                         RTE_PTYPE_L4_UDP,
3754                 [386] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3755                         RTE_PTYPE_L4_UDP,
3756                 [387] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3757                         RTE_PTYPE_L4_UDP,
3758                 [388] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3759                         RTE_PTYPE_L4_UDP,
3760                 [389] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3761                         RTE_PTYPE_L4_UDP,
3762                 [390] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3763                         RTE_PTYPE_L4_UDP,
3764                 [391] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3765                         RTE_PTYPE_L4_UDP,
3766                 /* All others reserved */
3767         };
3768
3769         return ptype_tbl[ptype];
3770 }
3771
3772 void __rte_cold
3773 iavf_set_default_ptype_table(struct rte_eth_dev *dev)
3774 {
3775         struct iavf_adapter *ad =
3776                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3777         int i;
3778
3779         for (i = 0; i < IAVF_MAX_PKT_TYPE; i++)
3780                 ad->ptype_tbl[i] = iavf_get_default_ptype(i);
3781 }