drivers/net/iavf/iavf_rxtx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2017 Intel Corporation
   3  */
   4
   5 #include <stdio.h>
   6 #include <stdlib.h>
   7 #include <string.h>
   8 #include <errno.h>
   9 #include <stdint.h>
  10 #include <stdarg.h>
  11 #include <unistd.h>
  12 #include <inttypes.h>
  13 #include <sys/queue.h>
  14
  15 #include <rte_string_fns.h>
  16 #include <rte_memzone.h>
  17 #include <rte_mbuf.h>
  18 #include <rte_malloc.h>
  19 #include <rte_ether.h>
  20 #include <ethdev_driver.h>
  21 #include <rte_tcp.h>
  22 #include <rte_sctp.h>
  23 #include <rte_udp.h>
  24 #include <rte_ip.h>
  25 #include <rte_net.h>
  26 #include <rte_vect.h>
  27
  28 #include "iavf.h"
  29 #include "iavf_rxtx.h"
  30 #include "iavf_ipsec_crypto.h"
  31 #include "rte_pmd_iavf.h"
  32
  33 /* Offset of mbuf dynamic field for protocol extraction's metadata */
  34 int rte_pmd_ifd_dynfield_proto_xtr_metadata_offs = -1;
  35
  36 /* Mask of mbuf dynamic flags for protocol extraction's type */
  37 uint64_t rte_pmd_ifd_dynflag_proto_xtr_vlan_mask;
  38 uint64_t rte_pmd_ifd_dynflag_proto_xtr_ipv4_mask;
  39 uint64_t rte_pmd_ifd_dynflag_proto_xtr_ipv6_mask;
  40 uint64_t rte_pmd_ifd_dynflag_proto_xtr_ipv6_flow_mask;
  41 uint64_t rte_pmd_ifd_dynflag_proto_xtr_tcp_mask;
  42 uint64_t rte_pmd_ifd_dynflag_proto_xtr_ip_offset_mask;
  43 uint64_t rte_pmd_ifd_dynflag_proto_xtr_ipsec_crypto_said_mask;
  44
  45 uint8_t
  46 iavf_proto_xtr_type_to_rxdid(uint8_t flex_type)
  47 {
  48         static uint8_t rxdid_map[] = {
  49                 [IAVF_PROTO_XTR_NONE]      = IAVF_RXDID_COMMS_OVS_1,
  50                 [IAVF_PROTO_XTR_VLAN]      = IAVF_RXDID_COMMS_AUX_VLAN,
  51                 [IAVF_PROTO_XTR_IPV4]      = IAVF_RXDID_COMMS_AUX_IPV4,
  52                 [IAVF_PROTO_XTR_IPV6]      = IAVF_RXDID_COMMS_AUX_IPV6,
  53                 [IAVF_PROTO_XTR_IPV6_FLOW] = IAVF_RXDID_COMMS_AUX_IPV6_FLOW,
  54                 [IAVF_PROTO_XTR_TCP]       = IAVF_RXDID_COMMS_AUX_TCP,
  55                 [IAVF_PROTO_XTR_IP_OFFSET] = IAVF_RXDID_COMMS_AUX_IP_OFFSET,
  56                 [IAVF_PROTO_XTR_IPSEC_CRYPTO_SAID] =
  57                                 IAVF_RXDID_COMMS_IPSEC_CRYPTO,
  58         };
  59
  60         return flex_type < RTE_DIM(rxdid_map) ?
  61                                 rxdid_map[flex_type] : IAVF_RXDID_COMMS_OVS_1;
  62 }
  63
  64 static int
  65 iavf_monitor_callback(const uint64_t value,
  66                 const uint64_t arg[RTE_POWER_MONITOR_OPAQUE_SZ] __rte_unused)
  67 {
  68         const uint64_t m = rte_cpu_to_le_64(1 << IAVF_RX_DESC_STATUS_DD_SHIFT);
  69         /*
  70          * we expect the DD bit to be set to 1 if this descriptor was already
  71          * written to.
  72          */
  73         return (value & m) == m ? -1 : 0;
  74 }
  75
  76 int
  77 iavf_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc)
  78 {
  79         struct iavf_rx_queue *rxq = rx_queue;
  80         volatile union iavf_rx_desc *rxdp;
  81         uint16_t desc;
  82
  83         desc = rxq->rx_tail;
  84         rxdp = &rxq->rx_ring[desc];
  85         /* watch for changes in status bit */
  86         pmc->addr = &rxdp->wb.qword1.status_error_len;
  87
  88         /* comparison callback */
  89         pmc->fn = iavf_monitor_callback;
  90
  91         /* registers are 64-bit */
  92         pmc->size = sizeof(uint64_t);
  93
  94         return 0;
  95 }
  96
  97 static inline int
  98 check_rx_thresh(uint16_t nb_desc, uint16_t thresh)
  99 {
 100         /* The following constraints must be satisfied:
 101          *   thresh < rxq->nb_rx_desc
 102          */
 103         if (thresh >= nb_desc) {
 104                 PMD_INIT_LOG(ERR, "rx_free_thresh (%u) must be less than %u",
 105                              thresh, nb_desc);
 106                 return -EINVAL;
 107         }
 108         return 0;
 109 }
 110
 111 static inline int
 112 check_tx_thresh(uint16_t nb_desc, uint16_t tx_rs_thresh,
 113                 uint16_t tx_free_thresh)
 114 {
 115         /* TX descriptors will have their RS bit set after tx_rs_thresh
 116          * descriptors have been used. The TX descriptor ring will be cleaned
 117          * after tx_free_thresh descriptors are used or if the number of
 118          * descriptors required to transmit a packet is greater than the
 119          * number of free TX descriptors.
 120          *
 121          * The following constraints must be satisfied:
 122          *  - tx_rs_thresh must be less than the size of the ring minus 2.
 123          *  - tx_free_thresh must be less than the size of the ring minus 3.
 124          *  - tx_rs_thresh must be less than or equal to tx_free_thresh.
 125          *  - tx_rs_thresh must be a divisor of the ring size.
 126          *
 127          * One descriptor in the TX ring is used as a sentinel to avoid a H/W
 128          * race condition, hence the maximum threshold constraints. When set
 129          * to zero use default values.
 130          */
 131         if (tx_rs_thresh >= (nb_desc - 2)) {
 132                 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be less than the "
 133                              "number of TX descriptors (%u) minus 2",
 134                              tx_rs_thresh, nb_desc);
 135                 return -EINVAL;
 136         }
 137         if (tx_free_thresh >= (nb_desc - 3)) {
 138                 PMD_INIT_LOG(ERR, "tx_free_thresh (%u) must be less than the "
 139                              "number of TX descriptors (%u) minus 3.",
 140                              tx_free_thresh, nb_desc);
 141                 return -EINVAL;
 142         }
 143         if (tx_rs_thresh > tx_free_thresh) {
 144                 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be less than or "
 145                              "equal to tx_free_thresh (%u).",
 146                              tx_rs_thresh, tx_free_thresh);
 147                 return -EINVAL;
 148         }
 149         if ((nb_desc % tx_rs_thresh) != 0) {
 150                 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be a divisor of the "
 151                              "number of TX descriptors (%u).",
 152                              tx_rs_thresh, nb_desc);
 153                 return -EINVAL;
 154         }
 155
 156         return 0;
 157 }
 158
 159 static inline bool
 160 check_rx_vec_allow(struct iavf_rx_queue *rxq)
 161 {
 162         if (rxq->rx_free_thresh >= IAVF_VPMD_RX_MAX_BURST &&
 163             rxq->nb_rx_desc % rxq->rx_free_thresh == 0) {
 164                 PMD_INIT_LOG(DEBUG, "Vector Rx can be enabled on this rxq.");
 165                 return true;
 166         }
 167
 168         PMD_INIT_LOG(DEBUG, "Vector Rx cannot be enabled on this rxq.");
 169         return false;
 170 }
 171
 172 static inline bool
 173 check_tx_vec_allow(struct iavf_tx_queue *txq)
 174 {
 175         if (!(txq->offloads & IAVF_TX_NO_VECTOR_FLAGS) &&
 176             txq->rs_thresh >= IAVF_VPMD_TX_MAX_BURST &&
 177             txq->rs_thresh <= IAVF_VPMD_TX_MAX_FREE_BUF) {
 178                 PMD_INIT_LOG(DEBUG, "Vector tx can be enabled on this txq.");
 179                 return true;
 180         }
 181         PMD_INIT_LOG(DEBUG, "Vector Tx cannot be enabled on this txq.");
 182         return false;
 183 }
 184
 185 static inline bool
 186 check_rx_bulk_allow(struct iavf_rx_queue *rxq)
 187 {
 188         int ret = true;
 189
 190         if (!(rxq->rx_free_thresh >= IAVF_RX_MAX_BURST)) {
 191                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 192                              "rxq->rx_free_thresh=%d, "
 193                              "IAVF_RX_MAX_BURST=%d",
 194                              rxq->rx_free_thresh, IAVF_RX_MAX_BURST);
 195                 ret = false;
 196         } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
 197                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 198                              "rxq->nb_rx_desc=%d, "
 199                              "rxq->rx_free_thresh=%d",
 200                              rxq->nb_rx_desc, rxq->rx_free_thresh);
 201                 ret = false;
 202         }
 203         return ret;
 204 }
 205
 206 static inline void
 207 reset_rx_queue(struct iavf_rx_queue *rxq)
 208 {
 209         uint16_t len;
 210         uint32_t i;
 211
 212         if (!rxq)
 213                 return;
 214
 215         len = rxq->nb_rx_desc + IAVF_RX_MAX_BURST;
 216
 217         for (i = 0; i < len * sizeof(union iavf_rx_desc); i++)
 218                 ((volatile char *)rxq->rx_ring)[i] = 0;
 219
 220         memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
 221
 222         for (i = 0; i < IAVF_RX_MAX_BURST; i++)
 223                 rxq->sw_ring[rxq->nb_rx_desc + i] = &rxq->fake_mbuf;
 224
 225         /* for rx bulk */
 226         rxq->rx_nb_avail = 0;
 227         rxq->rx_next_avail = 0;
 228         rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
 229
 230         rxq->rx_tail = 0;
 231         rxq->nb_rx_hold = 0;
 232
 233         rte_pktmbuf_free(rxq->pkt_first_seg);
 234
 235         rxq->pkt_first_seg = NULL;
 236         rxq->pkt_last_seg = NULL;
 237         rxq->rxrearm_nb = 0;
 238         rxq->rxrearm_start = 0;
 239 }
 240
 241 static inline void
 242 reset_tx_queue(struct iavf_tx_queue *txq)
 243 {
 244         struct iavf_tx_entry *txe;
 245         uint32_t i, size;
 246         uint16_t prev;
 247
 248         if (!txq) {
 249                 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
 250                 return;
 251         }
 252
 253         txe = txq->sw_ring;
 254         size = sizeof(struct iavf_tx_desc) * txq->nb_tx_desc;
 255         for (i = 0; i < size; i++)
 256                 ((volatile char *)txq->tx_ring)[i] = 0;
 257
 258         prev = (uint16_t)(txq->nb_tx_desc - 1);
 259         for (i = 0; i < txq->nb_tx_desc; i++) {
 260                 txq->tx_ring[i].cmd_type_offset_bsz =
 261                         rte_cpu_to_le_64(IAVF_TX_DESC_DTYPE_DESC_DONE);
 262                 txe[i].mbuf =  NULL;
 263                 txe[i].last_id = i;
 264                 txe[prev].next_id = i;
 265                 prev = i;
 266         }
 267
 268         txq->tx_tail = 0;
 269         txq->nb_used = 0;
 270
 271         txq->last_desc_cleaned = txq->nb_tx_desc - 1;
 272         txq->nb_free = txq->nb_tx_desc - 1;
 273
 274         txq->next_dd = txq->rs_thresh - 1;
 275         txq->next_rs = txq->rs_thresh - 1;
 276 }
 277
 278 static int
 279 alloc_rxq_mbufs(struct iavf_rx_queue *rxq)
 280 {
 281         volatile union iavf_rx_desc *rxd;
 282         struct rte_mbuf *mbuf = NULL;
 283         uint64_t dma_addr;
 284         uint16_t i, j;
 285
 286         for (i = 0; i < rxq->nb_rx_desc; i++) {
 287                 mbuf = rte_mbuf_raw_alloc(rxq->mp);
 288                 if (unlikely(!mbuf)) {
 289                         for (j = 0; j < i; j++) {
 290                                 rte_pktmbuf_free_seg(rxq->sw_ring[j]);
 291                                 rxq->sw_ring[j] = NULL;
 292                         }
 293                         PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
 294                         return -ENOMEM;
 295                 }
 296
 297                 rte_mbuf_refcnt_set(mbuf, 1);
 298                 mbuf->next = NULL;
 299                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
 300                 mbuf->nb_segs = 1;
 301                 mbuf->port = rxq->port_id;
 302
 303                 dma_addr =
 304                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
 305
 306                 rxd = &rxq->rx_ring[i];
 307                 rxd->read.pkt_addr = dma_addr;
 308                 rxd->read.hdr_addr = 0;
 309 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
 310                 rxd->read.rsvd1 = 0;
 311                 rxd->read.rsvd2 = 0;
 312 #endif
 313
 314                 rxq->sw_ring[i] = mbuf;
 315         }
 316
 317         return 0;
 318 }
 319
 320 static inline void
 321 release_rxq_mbufs(struct iavf_rx_queue *rxq)
 322 {
 323         uint16_t i;
 324
 325         if (!rxq->sw_ring)
 326                 return;
 327
 328         for (i = 0; i < rxq->nb_rx_desc; i++) {
 329                 if (rxq->sw_ring[i]) {
 330                         rte_pktmbuf_free_seg(rxq->sw_ring[i]);
 331                         rxq->sw_ring[i] = NULL;
 332                 }
 333         }
 334
 335         /* for rx bulk */
 336         if (rxq->rx_nb_avail == 0)
 337                 return;
 338         for (i = 0; i < rxq->rx_nb_avail; i++) {
 339                 struct rte_mbuf *mbuf;
 340
 341                 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
 342                 rte_pktmbuf_free_seg(mbuf);
 343         }
 344         rxq->rx_nb_avail = 0;
 345 }
 346
 347 static inline void
 348 release_txq_mbufs(struct iavf_tx_queue *txq)
 349 {
 350         uint16_t i;
 351
 352         if (!txq || !txq->sw_ring) {
 353                 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
 354                 return;
 355         }
 356
 357         for (i = 0; i < txq->nb_tx_desc; i++) {
 358                 if (txq->sw_ring[i].mbuf) {
 359                         rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
 360                         txq->sw_ring[i].mbuf = NULL;
 361                 }
 362         }
 363 }
 364
 365 static const struct iavf_rxq_ops def_rxq_ops = {
 366         .release_mbufs = release_rxq_mbufs,
 367 };
 368
 369 static const struct iavf_txq_ops def_txq_ops = {
 370         .release_mbufs = release_txq_mbufs,
 371 };
 372
 373 static inline void
 374 iavf_rxd_to_pkt_fields_by_comms_ovs(__rte_unused struct iavf_rx_queue *rxq,
 375                                     struct rte_mbuf *mb,
 376                                     volatile union iavf_rx_flex_desc *rxdp)
 377 {
 378         volatile struct iavf_32b_rx_flex_desc_comms_ovs *desc =
 379                         (volatile struct iavf_32b_rx_flex_desc_comms_ovs *)rxdp;
 380 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
 381         uint16_t stat_err;
 382 #endif
 383
 384         if (desc->flow_id != 0xFFFFFFFF) {
 385                 mb->ol_flags |= RTE_MBUF_F_RX_FDIR | RTE_MBUF_F_RX_FDIR_ID;
 386                 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
 387         }
 388
 389 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
 390         stat_err = rte_le_to_cpu_16(desc->status_error0);
 391         if (likely(stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
 392                 mb->ol_flags |= RTE_MBUF_F_RX_RSS_HASH;
 393                 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
 394         }
 395 #endif
 396 }
 397
 398 static inline void
 399 iavf_rxd_to_pkt_fields_by_comms_aux_v1(struct iavf_rx_queue *rxq,
 400                                        struct rte_mbuf *mb,
 401                                        volatile union iavf_rx_flex_desc *rxdp)
 402 {
 403         volatile struct iavf_32b_rx_flex_desc_comms *desc =
 404                         (volatile struct iavf_32b_rx_flex_desc_comms *)rxdp;
 405         uint16_t stat_err;
 406
 407         stat_err = rte_le_to_cpu_16(desc->status_error0);
 408         if (likely(stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
 409                 mb->ol_flags |= RTE_MBUF_F_RX_RSS_HASH;
 410                 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
 411         }
 412
 413 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
 414         if (desc->flow_id != 0xFFFFFFFF) {
 415                 mb->ol_flags |= RTE_MBUF_F_RX_FDIR | RTE_MBUF_F_RX_FDIR_ID;
 416                 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
 417         }
 418
 419         if (rxq->xtr_ol_flag) {
 420                 uint32_t metadata = 0;
 421
 422                 stat_err = rte_le_to_cpu_16(desc->status_error1);
 423
 424                 if (stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS1_XTRMD4_VALID_S))
 425                         metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux0);
 426
 427                 if (stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS1_XTRMD5_VALID_S))
 428                         metadata |=
 429                                 rte_le_to_cpu_16(desc->flex_ts.flex.aux1) << 16;
 430
 431                 if (metadata) {
 432                         mb->ol_flags |= rxq->xtr_ol_flag;
 433
 434                         *RTE_PMD_IFD_DYNF_PROTO_XTR_METADATA(mb) = metadata;
 435                 }
 436         }
 437 #endif
 438 }
 439
 440 static inline void
 441 iavf_rxd_to_pkt_fields_by_comms_aux_v2(struct iavf_rx_queue *rxq,
 442                                        struct rte_mbuf *mb,
 443                                        volatile union iavf_rx_flex_desc *rxdp)
 444 {
 445         volatile struct iavf_32b_rx_flex_desc_comms *desc =
 446                         (volatile struct iavf_32b_rx_flex_desc_comms *)rxdp;
 447         uint16_t stat_err;
 448
 449         stat_err = rte_le_to_cpu_16(desc->status_error0);
 450         if (likely(stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
 451                 mb->ol_flags |= RTE_MBUF_F_RX_RSS_HASH;
 452                 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
 453         }
 454
 455 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
 456         if (desc->flow_id != 0xFFFFFFFF) {
 457                 mb->ol_flags |= RTE_MBUF_F_RX_FDIR | RTE_MBUF_F_RX_FDIR_ID;
 458                 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
 459         }
 460
 461         if (rxq->xtr_ol_flag) {
 462                 uint32_t metadata = 0;
 463
 464                 if (desc->flex_ts.flex.aux0 != 0xFFFF)
 465                         metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux0);
 466                 else if (desc->flex_ts.flex.aux1 != 0xFFFF)
 467                         metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux1);
 468
 469                 if (metadata) {
 470                         mb->ol_flags |= rxq->xtr_ol_flag;
 471
 472                         *RTE_PMD_IFD_DYNF_PROTO_XTR_METADATA(mb) = metadata;
 473                 }
 474         }
 475 #endif
 476 }
 477
 478 static void
 479 iavf_select_rxd_to_pkt_fields_handler(struct iavf_rx_queue *rxq, uint32_t rxdid)
 480 {
 481         switch (rxdid) {
 482         case IAVF_RXDID_COMMS_AUX_VLAN:
 483                 rxq->xtr_ol_flag = rte_pmd_ifd_dynflag_proto_xtr_vlan_mask;
 484                 rxq->rxd_to_pkt_fields =
 485                         iavf_rxd_to_pkt_fields_by_comms_aux_v1;
 486                 break;
 487         case IAVF_RXDID_COMMS_AUX_IPV4:
 488                 rxq->xtr_ol_flag = rte_pmd_ifd_dynflag_proto_xtr_ipv4_mask;
 489                 rxq->rxd_to_pkt_fields =
 490                         iavf_rxd_to_pkt_fields_by_comms_aux_v1;
 491                 break;
 492         case IAVF_RXDID_COMMS_AUX_IPV6:
 493                 rxq->xtr_ol_flag = rte_pmd_ifd_dynflag_proto_xtr_ipv6_mask;
 494                 rxq->rxd_to_pkt_fields =
 495                         iavf_rxd_to_pkt_fields_by_comms_aux_v1;
 496                 break;
 497         case IAVF_RXDID_COMMS_AUX_IPV6_FLOW:
 498                 rxq->xtr_ol_flag =
 499                         rte_pmd_ifd_dynflag_proto_xtr_ipv6_flow_mask;
 500                 rxq->rxd_to_pkt_fields =
 501                         iavf_rxd_to_pkt_fields_by_comms_aux_v1;
 502                 break;
 503         case IAVF_RXDID_COMMS_AUX_TCP:
 504                 rxq->xtr_ol_flag = rte_pmd_ifd_dynflag_proto_xtr_tcp_mask;
 505                 rxq->rxd_to_pkt_fields =
 506                         iavf_rxd_to_pkt_fields_by_comms_aux_v1;
 507                 break;
 508         case IAVF_RXDID_COMMS_AUX_IP_OFFSET:
 509                 rxq->xtr_ol_flag =
 510                         rte_pmd_ifd_dynflag_proto_xtr_ip_offset_mask;
 511                 rxq->rxd_to_pkt_fields =
 512                         iavf_rxd_to_pkt_fields_by_comms_aux_v2;
 513                 break;
 514         case IAVF_RXDID_COMMS_IPSEC_CRYPTO:
 515                 rxq->xtr_ol_flag =
 516                         rte_pmd_ifd_dynflag_proto_xtr_ipsec_crypto_said_mask;
 517                 rxq->rxd_to_pkt_fields =
 518                         iavf_rxd_to_pkt_fields_by_comms_aux_v2;
 519                 break;
 520         case IAVF_RXDID_COMMS_OVS_1:
 521                 rxq->rxd_to_pkt_fields = iavf_rxd_to_pkt_fields_by_comms_ovs;
 522                 break;
 523         default:
 524                 /* update this according to the RXDID for FLEX_DESC_NONE */
 525                 rxq->rxd_to_pkt_fields = iavf_rxd_to_pkt_fields_by_comms_ovs;
 526                 break;
 527         }
 528
 529         if (!rte_pmd_ifd_dynf_proto_xtr_metadata_avail())
 530                 rxq->xtr_ol_flag = 0;
 531 }
 532
 533 int
 534 iavf_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 535                        uint16_t nb_desc, unsigned int socket_id,
 536                        const struct rte_eth_rxconf *rx_conf,
 537                        struct rte_mempool *mp)
 538 {
 539         struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 540         struct iavf_adapter *ad =
 541                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 542         struct iavf_info *vf =
 543                 IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 544         struct iavf_vsi *vsi = &vf->vsi;
 545         struct iavf_rx_queue *rxq;
 546         const struct rte_memzone *mz;
 547         uint32_t ring_size;
 548         uint8_t proto_xtr;
 549         uint16_t len;
 550         uint16_t rx_free_thresh;
 551         uint64_t offloads;
 552
 553         PMD_INIT_FUNC_TRACE();
 554
 555         offloads = rx_conf->offloads | dev->data->dev_conf.rxmode.offloads;
 556
 557         if (nb_desc % IAVF_ALIGN_RING_DESC != 0 ||
 558             nb_desc > IAVF_MAX_RING_DESC ||
 559             nb_desc < IAVF_MIN_RING_DESC) {
 560                 PMD_INIT_LOG(ERR, "Number (%u) of receive descriptors is "
 561                              "invalid", nb_desc);
 562                 return -EINVAL;
 563         }
 564
 565         /* Check free threshold */
 566         rx_free_thresh = (rx_conf->rx_free_thresh == 0) ?
 567                          IAVF_DEFAULT_RX_FREE_THRESH :
 568                          rx_conf->rx_free_thresh;
 569         if (check_rx_thresh(nb_desc, rx_free_thresh) != 0)
 570                 return -EINVAL;
 571
 572         /* Free memory if needed */
 573         if (dev->data->rx_queues[queue_idx]) {
 574                 iavf_dev_rx_queue_release(dev, queue_idx);
 575                 dev->data->rx_queues[queue_idx] = NULL;
 576         }
 577
 578         /* Allocate the rx queue data structure */
 579         rxq = rte_zmalloc_socket("iavf rxq",
 580                                  sizeof(struct iavf_rx_queue),
 581                                  RTE_CACHE_LINE_SIZE,
 582                                  socket_id);
 583         if (!rxq) {
 584                 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
 585                              "rx queue data structure");
 586                 return -ENOMEM;
 587         }
 588
 589         if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC) {
 590                 proto_xtr = vf->proto_xtr ? vf->proto_xtr[queue_idx] :
 591                                 IAVF_PROTO_XTR_NONE;
 592                 rxq->rxdid = iavf_proto_xtr_type_to_rxdid(proto_xtr);
 593                 rxq->proto_xtr = proto_xtr;
 594         } else {
 595                 rxq->rxdid = IAVF_RXDID_LEGACY_1;
 596                 rxq->proto_xtr = IAVF_PROTO_XTR_NONE;
 597         }
 598
 599         if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_VLAN_V2) {
 600                 struct virtchnl_vlan_supported_caps *stripping_support =
 601                                 &vf->vlan_v2_caps.offloads.stripping_support;
 602                 uint32_t stripping_cap;
 603
 604                 if (stripping_support->outer)
 605                         stripping_cap = stripping_support->outer;
 606                 else
 607                         stripping_cap = stripping_support->inner;
 608
 609                 if (stripping_cap & VIRTCHNL_VLAN_TAG_LOCATION_L2TAG1)
 610                         rxq->rx_flags = IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG1;
 611                 else if (stripping_cap & VIRTCHNL_VLAN_TAG_LOCATION_L2TAG2_2)
 612                         rxq->rx_flags = IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG2_2;
 613         } else {
 614                 rxq->rx_flags = IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG1;
 615         }
 616
 617         iavf_select_rxd_to_pkt_fields_handler(rxq, rxq->rxdid);
 618
 619         rxq->mp = mp;
 620         rxq->nb_rx_desc = nb_desc;
 621         rxq->rx_free_thresh = rx_free_thresh;
 622         rxq->queue_id = queue_idx;
 623         rxq->port_id = dev->data->port_id;
 624         rxq->rx_deferred_start = rx_conf->rx_deferred_start;
 625         rxq->rx_hdr_len = 0;
 626         rxq->vsi = vsi;
 627         rxq->offloads = offloads;
 628
 629         if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_KEEP_CRC)
 630                 rxq->crc_len = RTE_ETHER_CRC_LEN;
 631         else
 632                 rxq->crc_len = 0;
 633
 634         len = rte_pktmbuf_data_room_size(rxq->mp) - RTE_PKTMBUF_HEADROOM;
 635         rxq->rx_buf_len = RTE_ALIGN_FLOOR(len, (1 << IAVF_RXQ_CTX_DBUFF_SHIFT));
 636
 637         /* Allocate the software ring. */
 638         len = nb_desc + IAVF_RX_MAX_BURST;
 639         rxq->sw_ring =
 640                 rte_zmalloc_socket("iavf rx sw ring",
 641                                    sizeof(struct rte_mbuf *) * len,
 642                                    RTE_CACHE_LINE_SIZE,
 643                                    socket_id);
 644         if (!rxq->sw_ring) {
 645                 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW ring");
 646                 rte_free(rxq);
 647                 return -ENOMEM;
 648         }
 649
 650         /* Allocate the maximum number of RX ring hardware descriptor with
 651          * a little more to support bulk allocate.
 652          */
 653         len = IAVF_MAX_RING_DESC + IAVF_RX_MAX_BURST;
 654         ring_size = RTE_ALIGN(len * sizeof(union iavf_rx_desc),
 655                               IAVF_DMA_MEM_ALIGN);
 656         mz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
 657                                       ring_size, IAVF_RING_BASE_ALIGN,
 658                                       socket_id);
 659         if (!mz) {
 660                 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for RX");
 661                 rte_free(rxq->sw_ring);
 662                 rte_free(rxq);
 663                 return -ENOMEM;
 664         }
 665         /* Zero all the descriptors in the ring. */
 666         memset(mz->addr, 0, ring_size);
 667         rxq->rx_ring_phys_addr = mz->iova;
 668         rxq->rx_ring = (union iavf_rx_desc *)mz->addr;
 669
 670         rxq->mz = mz;
 671         reset_rx_queue(rxq);
 672         rxq->q_set = true;
 673         dev->data->rx_queues[queue_idx] = rxq;
 674         rxq->qrx_tail = hw->hw_addr + IAVF_QRX_TAIL1(rxq->queue_id);
 675         rxq->ops = &def_rxq_ops;
 676
 677         if (check_rx_bulk_allow(rxq) == true) {
 678                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
 679                              "satisfied. Rx Burst Bulk Alloc function will be "
 680                              "used on port=%d, queue=%d.",
 681                              rxq->port_id, rxq->queue_id);
 682         } else {
 683                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
 684                              "not satisfied, Scattered Rx is requested "
 685                              "on port=%d, queue=%d.",
 686                              rxq->port_id, rxq->queue_id);
 687                 ad->rx_bulk_alloc_allowed = false;
 688         }
 689
 690         if (check_rx_vec_allow(rxq) == false)
 691                 ad->rx_vec_allowed = false;
 692
 693         return 0;
 694 }
 695
 696 int
 697 iavf_dev_tx_queue_setup(struct rte_eth_dev *dev,
 698                        uint16_t queue_idx,
 699                        uint16_t nb_desc,
 700                        unsigned int socket_id,
 701                        const struct rte_eth_txconf *tx_conf)
 702 {
 703         struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 704         struct iavf_adapter *adapter =
 705                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 706         struct iavf_info *vf =
 707                 IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 708         struct iavf_tx_queue *txq;
 709         const struct rte_memzone *mz;
 710         uint32_t ring_size;
 711         uint16_t tx_rs_thresh, tx_free_thresh;
 712         uint64_t offloads;
 713
 714         PMD_INIT_FUNC_TRACE();
 715
 716         offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
 717
 718         if (nb_desc % IAVF_ALIGN_RING_DESC != 0 ||
 719             nb_desc > IAVF_MAX_RING_DESC ||
 720             nb_desc < IAVF_MIN_RING_DESC) {
 721                 PMD_INIT_LOG(ERR, "Number (%u) of transmit descriptors is "
 722                             "invalid", nb_desc);
 723                 return -EINVAL;
 724         }
 725
 726         tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
 727                 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
 728         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
 729                 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
 730         if (check_tx_thresh(nb_desc, tx_rs_thresh, tx_free_thresh) != 0)
 731                 return -EINVAL;
 732
 733         /* Free memory if needed. */
 734         if (dev->data->tx_queues[queue_idx]) {
 735                 iavf_dev_tx_queue_release(dev, queue_idx);
 736                 dev->data->tx_queues[queue_idx] = NULL;
 737         }
 738
 739         /* Allocate the TX queue data structure. */
 740         txq = rte_zmalloc_socket("iavf txq",
 741                                  sizeof(struct iavf_tx_queue),
 742                                  RTE_CACHE_LINE_SIZE,
 743                                  socket_id);
 744         if (!txq) {
 745                 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
 746                              "tx queue structure");
 747                 return -ENOMEM;
 748         }
 749
 750         if (adapter->vf.vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_VLAN_V2) {
 751                 struct virtchnl_vlan_supported_caps *insertion_support =
 752                         &adapter->vf.vlan_v2_caps.offloads.insertion_support;
 753                 uint32_t insertion_cap;
 754
 755                 if (insertion_support->outer)
 756                         insertion_cap = insertion_support->outer;
 757                 else
 758                         insertion_cap = insertion_support->inner;
 759
 760                 if (insertion_cap & VIRTCHNL_VLAN_TAG_LOCATION_L2TAG1)
 761                         txq->vlan_flag = IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG1;
 762                 else if (insertion_cap & VIRTCHNL_VLAN_TAG_LOCATION_L2TAG2)
 763                         txq->vlan_flag = IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG2;
 764         } else {
 765                 txq->vlan_flag = IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG1;
 766         }
 767
 768         txq->nb_tx_desc = nb_desc;
 769         txq->rs_thresh = tx_rs_thresh;
 770         txq->free_thresh = tx_free_thresh;
 771         txq->queue_id = queue_idx;
 772         txq->port_id = dev->data->port_id;
 773         txq->offloads = offloads;
 774         txq->tx_deferred_start = tx_conf->tx_deferred_start;
 775
 776         if (iavf_ipsec_crypto_supported(adapter))
 777                 txq->ipsec_crypto_pkt_md_offset =
 778                         iavf_security_get_pkt_md_offset(adapter);
 779
 780         /* Allocate software ring */
 781         txq->sw_ring =
 782                 rte_zmalloc_socket("iavf tx sw ring",
 783                                    sizeof(struct iavf_tx_entry) * nb_desc,
 784                                    RTE_CACHE_LINE_SIZE,
 785                                    socket_id);
 786         if (!txq->sw_ring) {
 787                 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW TX ring");
 788                 rte_free(txq);
 789                 return -ENOMEM;
 790         }
 791
 792         /* Allocate TX hardware ring descriptors. */
 793         ring_size = sizeof(struct iavf_tx_desc) * IAVF_MAX_RING_DESC;
 794         ring_size = RTE_ALIGN(ring_size, IAVF_DMA_MEM_ALIGN);
 795         mz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
 796                                       ring_size, IAVF_RING_BASE_ALIGN,
 797                                       socket_id);
 798         if (!mz) {
 799                 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for TX");
 800                 rte_free(txq->sw_ring);
 801                 rte_free(txq);
 802                 return -ENOMEM;
 803         }
 804         txq->tx_ring_phys_addr = mz->iova;
 805         txq->tx_ring = (struct iavf_tx_desc *)mz->addr;
 806
 807         txq->mz = mz;
 808         reset_tx_queue(txq);
 809         txq->q_set = true;
 810         dev->data->tx_queues[queue_idx] = txq;
 811         txq->qtx_tail = hw->hw_addr + IAVF_QTX_TAIL1(queue_idx);
 812         txq->ops = &def_txq_ops;
 813
 814         if (check_tx_vec_allow(txq) == false) {
 815                 struct iavf_adapter *ad =
 816                         IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 817                 ad->tx_vec_allowed = false;
 818         }
 819
 820         if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_QOS &&
 821             vf->tm_conf.committed) {
 822                 int tc;
 823                 for (tc = 0; tc < vf->qos_cap->num_elem; tc++) {
 824                         if (txq->queue_id >= vf->qtc_map[tc].start_queue_id &&
 825                             txq->queue_id < (vf->qtc_map[tc].start_queue_id +
 826                             vf->qtc_map[tc].queue_count))
 827                                 break;
 828                 }
 829                 if (tc >= vf->qos_cap->num_elem) {
 830                         PMD_INIT_LOG(ERR, "Queue TC mapping is not correct");
 831                         return -EINVAL;
 832                 }
 833                 txq->tc = tc;
 834         }
 835
 836         return 0;
 837 }
 838
 839 int
 840 iavf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 841 {
 842         struct iavf_adapter *adapter =
 843                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 844         struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 845         struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 846         struct iavf_rx_queue *rxq;
 847         int err = 0;
 848
 849         PMD_DRV_FUNC_TRACE();
 850
 851         if (rx_queue_id >= dev->data->nb_rx_queues)
 852                 return -EINVAL;
 853
 854         rxq = dev->data->rx_queues[rx_queue_id];
 855
 856         err = alloc_rxq_mbufs(rxq);
 857         if (err) {
 858                 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
 859                 return err;
 860         }
 861
 862         rte_wmb();
 863
 864         /* Init the RX tail register. */
 865         IAVF_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 866         IAVF_WRITE_FLUSH(hw);
 867
 868         /* Ready to switch the queue on */
 869         if (!vf->lv_enabled)
 870                 err = iavf_switch_queue(adapter, rx_queue_id, true, true);
 871         else
 872                 err = iavf_switch_queue_lv(adapter, rx_queue_id, true, true);
 873
 874         if (err) {
 875                 release_rxq_mbufs(rxq);
 876                 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
 877                             rx_queue_id);
 878         } else {
 879                 dev->data->rx_queue_state[rx_queue_id] =
 880                         RTE_ETH_QUEUE_STATE_STARTED;
 881         }
 882
 883         return err;
 884 }
 885
 886 int
 887 iavf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 888 {
 889         struct iavf_adapter *adapter =
 890                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 891         struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 892         struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 893         struct iavf_tx_queue *txq;
 894         int err = 0;
 895
 896         PMD_DRV_FUNC_TRACE();
 897
 898         if (tx_queue_id >= dev->data->nb_tx_queues)
 899                 return -EINVAL;
 900
 901         txq = dev->data->tx_queues[tx_queue_id];
 902
 903         /* Init the RX tail register. */
 904         IAVF_PCI_REG_WRITE(txq->qtx_tail, 0);
 905         IAVF_WRITE_FLUSH(hw);
 906
 907         /* Ready to switch the queue on */
 908         if (!vf->lv_enabled)
 909                 err = iavf_switch_queue(adapter, tx_queue_id, false, true);
 910         else
 911                 err = iavf_switch_queue_lv(adapter, tx_queue_id, false, true);
 912
 913         if (err)
 914                 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
 915                             tx_queue_id);
 916         else
 917                 dev->data->tx_queue_state[tx_queue_id] =
 918                         RTE_ETH_QUEUE_STATE_STARTED;
 919
 920         return err;
 921 }
 922
 923 int
 924 iavf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 925 {
 926         struct iavf_adapter *adapter =
 927                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 928         struct iavf_rx_queue *rxq;
 929         int err;
 930
 931         PMD_DRV_FUNC_TRACE();
 932
 933         if (rx_queue_id >= dev->data->nb_rx_queues)
 934                 return -EINVAL;
 935
 936         err = iavf_switch_queue(adapter, rx_queue_id, true, false);
 937         if (err) {
 938                 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
 939                             rx_queue_id);
 940                 return err;
 941         }
 942
 943         rxq = dev->data->rx_queues[rx_queue_id];
 944         rxq->ops->release_mbufs(rxq);
 945         reset_rx_queue(rxq);
 946         dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 947
 948         return 0;
 949 }
 950
 951 int
 952 iavf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 953 {
 954         struct iavf_adapter *adapter =
 955                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 956         struct iavf_tx_queue *txq;
 957         int err;
 958
 959         PMD_DRV_FUNC_TRACE();
 960
 961         if (tx_queue_id >= dev->data->nb_tx_queues)
 962                 return -EINVAL;
 963
 964         err = iavf_switch_queue(adapter, tx_queue_id, false, false);
 965         if (err) {
 966                 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u off",
 967                             tx_queue_id);
 968                 return err;
 969         }
 970
 971         txq = dev->data->tx_queues[tx_queue_id];
 972         txq->ops->release_mbufs(txq);
 973         reset_tx_queue(txq);
 974         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 975
 976         return 0;
 977 }
 978
 979 void
 980 iavf_dev_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
 981 {
 982         struct iavf_rx_queue *q = dev->data->rx_queues[qid];
 983
 984         if (!q)
 985                 return;
 986
 987         q->ops->release_mbufs(q);
 988         rte_free(q->sw_ring);
 989         rte_memzone_free(q->mz);
 990         rte_free(q);
 991 }
 992
 993 void
 994 iavf_dev_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
 995 {
 996         struct iavf_tx_queue *q = dev->data->tx_queues[qid];
 997
 998         if (!q)
 999                 return;
1000
1001         q->ops->release_mbufs(q);
1002         rte_free(q->sw_ring);
1003         rte_memzone_free(q->mz);
1004         rte_free(q);
1005 }
1006
1007 void
1008 iavf_stop_queues(struct rte_eth_dev *dev)
1009 {
1010         struct iavf_adapter *adapter =
1011                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1012         struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1013         struct iavf_rx_queue *rxq;
1014         struct iavf_tx_queue *txq;
1015         int ret, i;
1016
1017         /* Stop All queues */
1018         if (!vf->lv_enabled) {
1019                 ret = iavf_disable_queues(adapter);
1020                 if (ret)
1021                         PMD_DRV_LOG(WARNING, "Fail to stop queues");
1022         } else {
1023                 ret = iavf_disable_queues_lv(adapter);
1024                 if (ret)
1025                         PMD_DRV_LOG(WARNING, "Fail to stop queues for large VF");
1026         }
1027
1028         if (ret)
1029                 PMD_DRV_LOG(WARNING, "Fail to stop queues");
1030
1031         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1032                 txq = dev->data->tx_queues[i];
1033                 if (!txq)
1034                         continue;
1035                 txq->ops->release_mbufs(txq);
1036                 reset_tx_queue(txq);
1037                 dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED;
1038         }
1039         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1040                 rxq = dev->data->rx_queues[i];
1041                 if (!rxq)
1042                         continue;
1043                 rxq->ops->release_mbufs(rxq);
1044                 reset_rx_queue(rxq);
1045                 dev->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED;
1046         }
1047 }
1048
1049 #define IAVF_RX_FLEX_ERR0_BITS  \
1050         ((1 << IAVF_RX_FLEX_DESC_STATUS0_HBO_S) |       \
1051          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_IPE_S) |  \
1052          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_L4E_S) |  \
1053          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S) | \
1054          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S) |        \
1055          (1 << IAVF_RX_FLEX_DESC_STATUS0_RXE_S))
1056
1057 static inline void
1058 iavf_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union iavf_rx_desc *rxdp)
1059 {
1060         if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1061                 (1 << IAVF_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
1062                 mb->ol_flags |= RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED;
1063                 mb->vlan_tci =
1064                         rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
1065         } else {
1066                 mb->vlan_tci = 0;
1067         }
1068 }
1069
1070 static inline void
1071 iavf_flex_rxd_to_vlan_tci(struct rte_mbuf *mb,
1072                           volatile union iavf_rx_flex_desc *rxdp)
1073 {
1074         if (rte_le_to_cpu_64(rxdp->wb.status_error0) &
1075                 (1 << IAVF_RX_FLEX_DESC_STATUS0_L2TAG1P_S)) {
1076                 mb->ol_flags |= RTE_MBUF_F_RX_VLAN |
1077                                 RTE_MBUF_F_RX_VLAN_STRIPPED;
1078                 mb->vlan_tci =
1079                         rte_le_to_cpu_16(rxdp->wb.l2tag1);
1080         } else {
1081                 mb->vlan_tci = 0;
1082         }
1083
1084 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
1085         if (rte_le_to_cpu_16(rxdp->wb.status_error1) &
1086             (1 << IAVF_RX_FLEX_DESC_STATUS1_L2TAG2P_S)) {
1087                 mb->ol_flags |= RTE_MBUF_F_RX_QINQ_STRIPPED |
1088                                 RTE_MBUF_F_RX_QINQ |
1089                                 RTE_MBUF_F_RX_VLAN_STRIPPED |
1090                                 RTE_MBUF_F_RX_VLAN;
1091                 mb->vlan_tci_outer = mb->vlan_tci;
1092                 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.l2tag2_2nd);
1093                 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
1094                            rte_le_to_cpu_16(rxdp->wb.l2tag2_1st),
1095                            rte_le_to_cpu_16(rxdp->wb.l2tag2_2nd));
1096         } else {
1097                 mb->vlan_tci_outer = 0;
1098         }
1099 #endif
1100 }
1101
1102 static inline void
1103 iavf_flex_rxd_to_ipsec_crypto_said_get(struct rte_mbuf *mb,
1104                           volatile union iavf_rx_flex_desc *rxdp)
1105 {
1106         volatile struct iavf_32b_rx_flex_desc_comms_ipsec *desc =
1107                 (volatile struct iavf_32b_rx_flex_desc_comms_ipsec *)rxdp;
1108
1109         mb->dynfield1[0] = desc->ipsec_said &
1110                          IAVF_RX_FLEX_DESC_IPSEC_CRYPTO_SAID_MASK;
1111         }
1112
1113 static inline void
1114 iavf_flex_rxd_to_ipsec_crypto_status(struct rte_mbuf *mb,
1115                           volatile union iavf_rx_flex_desc *rxdp,
1116                           struct iavf_ipsec_crypto_stats *stats)
1117 {
1118         uint16_t status1 = rte_le_to_cpu_64(rxdp->wb.status_error1);
1119
1120         if (status1 & BIT(IAVF_RX_FLEX_DESC_STATUS1_IPSEC_CRYPTO_PROCESSED)) {
1121                 uint16_t ipsec_status;
1122
1123                 mb->ol_flags |= RTE_MBUF_F_RX_SEC_OFFLOAD;
1124
1125                 ipsec_status = status1 &
1126                         IAVF_RX_FLEX_DESC_IPSEC_CRYPTO_STATUS_MASK;
1127
1128
1129                 if (unlikely(ipsec_status !=
1130                         IAVF_IPSEC_CRYPTO_STATUS_SUCCESS)) {
1131                         mb->ol_flags |= RTE_MBUF_F_RX_SEC_OFFLOAD_FAILED;
1132
1133                         switch (ipsec_status) {
1134                         case IAVF_IPSEC_CRYPTO_STATUS_SAD_MISS:
1135                                 stats->ierrors.sad_miss++;
1136                                 break;
1137                         case IAVF_IPSEC_CRYPTO_STATUS_NOT_PROCESSED:
1138                                 stats->ierrors.not_processed++;
1139                                 break;
1140                         case IAVF_IPSEC_CRYPTO_STATUS_ICV_CHECK_FAIL:
1141                                 stats->ierrors.icv_check++;
1142                                 break;
1143                         case IAVF_IPSEC_CRYPTO_STATUS_LENGTH_ERR:
1144                                 stats->ierrors.ipsec_length++;
1145                                 break;
1146                         case IAVF_IPSEC_CRYPTO_STATUS_MISC_ERR:
1147                                 stats->ierrors.misc++;
1148                                 break;
1149 }
1150
1151                         stats->ierrors.count++;
1152                         return;
1153                 }
1154
1155                 stats->icount++;
1156                 stats->ibytes += rxdp->wb.pkt_len & 0x3FFF;
1157
1158                 if (rxdp->wb.rxdid == IAVF_RXDID_COMMS_IPSEC_CRYPTO &&
1159                         ipsec_status !=
1160                                 IAVF_IPSEC_CRYPTO_STATUS_SAD_MISS)
1161                         iavf_flex_rxd_to_ipsec_crypto_said_get(mb, rxdp);
1162         }
1163 }
1164
1165
1166 /* Translate the rx descriptor status and error fields to pkt flags */
1167 static inline uint64_t
1168 iavf_rxd_to_pkt_flags(uint64_t qword)
1169 {
1170         uint64_t flags;
1171         uint64_t error_bits = (qword >> IAVF_RXD_QW1_ERROR_SHIFT);
1172
1173 #define IAVF_RX_ERR_BITS 0x3f
1174
1175         /* Check if RSS_HASH */
1176         flags = (((qword >> IAVF_RX_DESC_STATUS_FLTSTAT_SHIFT) &
1177                                         IAVF_RX_DESC_FLTSTAT_RSS_HASH) ==
1178                         IAVF_RX_DESC_FLTSTAT_RSS_HASH) ? RTE_MBUF_F_RX_RSS_HASH : 0;
1179
1180         /* Check if FDIR Match */
1181         flags |= (qword & (1 << IAVF_RX_DESC_STATUS_FLM_SHIFT) ?
1182                                 RTE_MBUF_F_RX_FDIR : 0);
1183
1184         if (likely((error_bits & IAVF_RX_ERR_BITS) == 0)) {
1185                 flags |= (RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_GOOD);
1186                 return flags;
1187         }
1188
1189         if (unlikely(error_bits & (1 << IAVF_RX_DESC_ERROR_IPE_SHIFT)))
1190                 flags |= RTE_MBUF_F_RX_IP_CKSUM_BAD;
1191         else
1192                 flags |= RTE_MBUF_F_RX_IP_CKSUM_GOOD;
1193
1194         if (unlikely(error_bits & (1 << IAVF_RX_DESC_ERROR_L4E_SHIFT)))
1195                 flags |= RTE_MBUF_F_RX_L4_CKSUM_BAD;
1196         else
1197                 flags |= RTE_MBUF_F_RX_L4_CKSUM_GOOD;
1198
1199         /* TODO: Oversize error bit is not processed here */
1200
1201         return flags;
1202 }
1203
1204 static inline uint64_t
1205 iavf_rxd_build_fdir(volatile union iavf_rx_desc *rxdp, struct rte_mbuf *mb)
1206 {
1207         uint64_t flags = 0;
1208 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
1209         uint16_t flexbh;
1210
1211         flexbh = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
1212                 IAVF_RX_DESC_EXT_STATUS_FLEXBH_SHIFT) &
1213                 IAVF_RX_DESC_EXT_STATUS_FLEXBH_MASK;
1214
1215         if (flexbh == IAVF_RX_DESC_EXT_STATUS_FLEXBH_FD_ID) {
1216                 mb->hash.fdir.hi =
1217                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.fd_id);
1218                 flags |= RTE_MBUF_F_RX_FDIR_ID;
1219         }
1220 #else
1221         mb->hash.fdir.hi =
1222                 rte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.fd_id);
1223         flags |= RTE_MBUF_F_RX_FDIR_ID;
1224 #endif
1225         return flags;
1226 }
1227
1228 #define IAVF_RX_FLEX_ERR0_BITS  \
1229         ((1 << IAVF_RX_FLEX_DESC_STATUS0_HBO_S) |       \
1230          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_IPE_S) |  \
1231          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_L4E_S) |  \
1232          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S) | \
1233          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S) |        \
1234          (1 << IAVF_RX_FLEX_DESC_STATUS0_RXE_S))
1235
1236 /* Rx L3/L4 checksum */
1237 static inline uint64_t
1238 iavf_flex_rxd_error_to_pkt_flags(uint16_t stat_err0)
1239 {
1240         uint64_t flags = 0;
1241
1242         /* check if HW has decoded the packet and checksum */
1243         if (unlikely(!(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_L3L4P_S))))
1244                 return 0;
1245
1246         if (likely(!(stat_err0 & IAVF_RX_FLEX_ERR0_BITS))) {
1247                 flags |= (RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_GOOD);
1248                 return flags;
1249         }
1250
1251         if (unlikely(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_IPE_S)))
1252                 flags |= RTE_MBUF_F_RX_IP_CKSUM_BAD;
1253         else
1254                 flags |= RTE_MBUF_F_RX_IP_CKSUM_GOOD;
1255
1256         if (unlikely(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_L4E_S)))
1257                 flags |= RTE_MBUF_F_RX_L4_CKSUM_BAD;
1258         else
1259                 flags |= RTE_MBUF_F_RX_L4_CKSUM_GOOD;
1260
1261         if (unlikely(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S)))
1262                 flags |= RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD;
1263
1264         return flags;
1265 }
1266
1267 /* If the number of free RX descriptors is greater than the RX free
1268  * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1269  * register. Update the RDT with the value of the last processed RX
1270  * descriptor minus 1, to guarantee that the RDT register is never
1271  * equal to the RDH register, which creates a "full" ring situation
1272  * from the hardware point of view.
1273  */
1274 static inline void
1275 iavf_update_rx_tail(struct iavf_rx_queue *rxq, uint16_t nb_hold, uint16_t rx_id)
1276 {
1277         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1278
1279         if (nb_hold > rxq->rx_free_thresh) {
1280                 PMD_RX_LOG(DEBUG,
1281                            "port_id=%u queue_id=%u rx_tail=%u nb_hold=%u",
1282                            rxq->port_id, rxq->queue_id, rx_id, nb_hold);
1283                 rx_id = (uint16_t)((rx_id == 0) ?
1284                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
1285                 IAVF_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
1286                 nb_hold = 0;
1287         }
1288         rxq->nb_rx_hold = nb_hold;
1289 }
1290
1291 /* implement recv_pkts */
1292 uint16_t
1293 iavf_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1294 {
1295         volatile union iavf_rx_desc *rx_ring;
1296         volatile union iavf_rx_desc *rxdp;
1297         struct iavf_rx_queue *rxq;
1298         union iavf_rx_desc rxd;
1299         struct rte_mbuf *rxe;
1300         struct rte_eth_dev *dev;
1301         struct rte_mbuf *rxm;
1302         struct rte_mbuf *nmb;
1303         uint16_t nb_rx;
1304         uint32_t rx_status;
1305         uint64_t qword1;
1306         uint16_t rx_packet_len;
1307         uint16_t rx_id, nb_hold;
1308         uint64_t dma_addr;
1309         uint64_t pkt_flags;
1310         const uint32_t *ptype_tbl;
1311
1312         nb_rx = 0;
1313         nb_hold = 0;
1314         rxq = rx_queue;
1315         rx_id = rxq->rx_tail;
1316         rx_ring = rxq->rx_ring;
1317         ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1318
1319         while (nb_rx < nb_pkts) {
1320                 rxdp = &rx_ring[rx_id];
1321                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1322                 rx_status = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
1323                             IAVF_RXD_QW1_STATUS_SHIFT;
1324
1325                 /* Check the DD bit first */
1326                 if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)))
1327                         break;
1328                 IAVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
1329
1330                 nmb = rte_mbuf_raw_alloc(rxq->mp);
1331                 if (unlikely(!nmb)) {
1332                         dev = &rte_eth_devices[rxq->port_id];
1333                         dev->data->rx_mbuf_alloc_failed++;
1334                         PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1335                                    "queue_id=%u", rxq->port_id, rxq->queue_id);
1336                         break;
1337                 }
1338
1339                 rxd = *rxdp;
1340                 nb_hold++;
1341                 rxe = rxq->sw_ring[rx_id];
1342                 rxq->sw_ring[rx_id] = nmb;
1343                 rx_id++;
1344                 if (unlikely(rx_id == rxq->nb_rx_desc))
1345                         rx_id = 0;
1346
1347                 /* Prefetch next mbuf */
1348                 rte_prefetch0(rxq->sw_ring[rx_id]);
1349
1350                 /* When next RX descriptor is on a cache line boundary,
1351                  * prefetch the next 4 RX descriptors and next 8 pointers
1352                  * to mbufs.
1353                  */
1354                 if ((rx_id & 0x3) == 0) {
1355                         rte_prefetch0(&rx_ring[rx_id]);
1356                         rte_prefetch0(rxq->sw_ring[rx_id]);
1357                 }
1358                 rxm = rxe;
1359                 dma_addr =
1360                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1361                 rxdp->read.hdr_addr = 0;
1362                 rxdp->read.pkt_addr = dma_addr;
1363
1364                 rx_packet_len = ((qword1 & IAVF_RXD_QW1_LENGTH_PBUF_MASK) >>
1365                                 IAVF_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
1366
1367                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1368                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
1369                 rxm->nb_segs = 1;
1370                 rxm->next = NULL;
1371                 rxm->pkt_len = rx_packet_len;
1372                 rxm->data_len = rx_packet_len;
1373                 rxm->port = rxq->port_id;
1374                 rxm->ol_flags = 0;
1375                 iavf_rxd_to_vlan_tci(rxm, &rxd);
1376                 pkt_flags = iavf_rxd_to_pkt_flags(qword1);
1377                 rxm->packet_type =
1378                         ptype_tbl[(uint8_t)((qword1 &
1379                         IAVF_RXD_QW1_PTYPE_MASK) >> IAVF_RXD_QW1_PTYPE_SHIFT)];
1380
1381                 if (pkt_flags & RTE_MBUF_F_RX_RSS_HASH)
1382                         rxm->hash.rss =
1383                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1384
1385                 if (pkt_flags & RTE_MBUF_F_RX_FDIR)
1386                         pkt_flags |= iavf_rxd_build_fdir(&rxd, rxm);
1387
1388                 rxm->ol_flags |= pkt_flags;
1389
1390                 rx_pkts[nb_rx++] = rxm;
1391         }
1392         rxq->rx_tail = rx_id;
1393
1394         iavf_update_rx_tail(rxq, nb_hold, rx_id);
1395
1396         return nb_rx;
1397 }
1398
1399 /* implement recv_pkts for flexible Rx descriptor */
1400 uint16_t
1401 iavf_recv_pkts_flex_rxd(void *rx_queue,
1402                         struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1403 {
1404         volatile union iavf_rx_desc *rx_ring;
1405         volatile union iavf_rx_flex_desc *rxdp;
1406         struct iavf_rx_queue *rxq;
1407         union iavf_rx_flex_desc rxd;
1408         struct rte_mbuf *rxe;
1409         struct rte_eth_dev *dev;
1410         struct rte_mbuf *rxm;
1411         struct rte_mbuf *nmb;
1412         uint16_t nb_rx;
1413         uint16_t rx_stat_err0;
1414         uint16_t rx_packet_len;
1415         uint16_t rx_id, nb_hold;
1416         uint64_t dma_addr;
1417         uint64_t pkt_flags;
1418         const uint32_t *ptype_tbl;
1419
1420         nb_rx = 0;
1421         nb_hold = 0;
1422         rxq = rx_queue;
1423         rx_id = rxq->rx_tail;
1424         rx_ring = rxq->rx_ring;
1425         ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1426
1427         while (nb_rx < nb_pkts) {
1428                 rxdp = (volatile union iavf_rx_flex_desc *)&rx_ring[rx_id];
1429                 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1430
1431                 /* Check the DD bit first */
1432                 if (!(rx_stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S)))
1433                         break;
1434                 IAVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
1435
1436                 nmb = rte_mbuf_raw_alloc(rxq->mp);
1437                 if (unlikely(!nmb)) {
1438                         dev = &rte_eth_devices[rxq->port_id];
1439                         dev->data->rx_mbuf_alloc_failed++;
1440                         PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1441                                    "queue_id=%u", rxq->port_id, rxq->queue_id);
1442                         break;
1443                 }
1444
1445                 rxd = *rxdp;
1446                 nb_hold++;
1447                 rxe = rxq->sw_ring[rx_id];
1448                 rxq->sw_ring[rx_id] = nmb;
1449                 rx_id++;
1450                 if (unlikely(rx_id == rxq->nb_rx_desc))
1451                         rx_id = 0;
1452
1453                 /* Prefetch next mbuf */
1454                 rte_prefetch0(rxq->sw_ring[rx_id]);
1455
1456                 /* When next RX descriptor is on a cache line boundary,
1457                  * prefetch the next 4 RX descriptors and next 8 pointers
1458                  * to mbufs.
1459                  */
1460                 if ((rx_id & 0x3) == 0) {
1461                         rte_prefetch0(&rx_ring[rx_id]);
1462                         rte_prefetch0(rxq->sw_ring[rx_id]);
1463                 }
1464                 rxm = rxe;
1465                 dma_addr =
1466                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1467                 rxdp->read.hdr_addr = 0;
1468                 rxdp->read.pkt_addr = dma_addr;
1469
1470                 rx_packet_len = (rte_le_to_cpu_16(rxd.wb.pkt_len) &
1471                                 IAVF_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
1472
1473                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1474                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
1475                 rxm->nb_segs = 1;
1476                 rxm->next = NULL;
1477                 rxm->pkt_len = rx_packet_len;
1478                 rxm->data_len = rx_packet_len;
1479                 rxm->port = rxq->port_id;
1480                 rxm->ol_flags = 0;
1481                 rxm->packet_type = ptype_tbl[IAVF_RX_FLEX_DESC_PTYPE_M &
1482                         rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
1483                 iavf_flex_rxd_to_vlan_tci(rxm, &rxd);
1484                 iavf_flex_rxd_to_ipsec_crypto_status(rxm, &rxd,
1485                                 &rxq->stats.ipsec_crypto);
1486                 rxq->rxd_to_pkt_fields(rxq, rxm, &rxd);
1487                 pkt_flags = iavf_flex_rxd_error_to_pkt_flags(rx_stat_err0);
1488                 rxm->ol_flags |= pkt_flags;
1489
1490                 rx_pkts[nb_rx++] = rxm;
1491         }
1492         rxq->rx_tail = rx_id;
1493
1494         iavf_update_rx_tail(rxq, nb_hold, rx_id);
1495
1496         return nb_rx;
1497 }
1498
1499 /* implement recv_scattered_pkts for flexible Rx descriptor */
1500 uint16_t
1501 iavf_recv_scattered_pkts_flex_rxd(void *rx_queue, struct rte_mbuf **rx_pkts,
1502                                   uint16_t nb_pkts)
1503 {
1504         struct iavf_rx_queue *rxq = rx_queue;
1505         union iavf_rx_flex_desc rxd;
1506         struct rte_mbuf *rxe;
1507         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1508         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1509         struct rte_mbuf *nmb, *rxm;
1510         uint16_t rx_id = rxq->rx_tail;
1511         uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
1512         struct rte_eth_dev *dev;
1513         uint16_t rx_stat_err0;
1514         uint64_t dma_addr;
1515         uint64_t pkt_flags;
1516
1517         volatile union iavf_rx_desc *rx_ring = rxq->rx_ring;
1518         volatile union iavf_rx_flex_desc *rxdp;
1519         const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1520
1521         while (nb_rx < nb_pkts) {
1522                 rxdp = (volatile union iavf_rx_flex_desc *)&rx_ring[rx_id];
1523                 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1524
1525                 /* Check the DD bit */
1526                 if (!(rx_stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S)))
1527                         break;
1528                 IAVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
1529
1530                 nmb = rte_mbuf_raw_alloc(rxq->mp);
1531                 if (unlikely(!nmb)) {
1532                         PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1533                                    "queue_id=%u", rxq->port_id, rxq->queue_id);
1534                         dev = &rte_eth_devices[rxq->port_id];
1535                         dev->data->rx_mbuf_alloc_failed++;
1536                         break;
1537                 }
1538
1539                 rxd = *rxdp;
1540                 nb_hold++;
1541                 rxe = rxq->sw_ring[rx_id];
1542                 rxq->sw_ring[rx_id] = nmb;
1543                 rx_id++;
1544                 if (rx_id == rxq->nb_rx_desc)
1545                         rx_id = 0;
1546
1547                 /* Prefetch next mbuf */
1548                 rte_prefetch0(rxq->sw_ring[rx_id]);
1549
1550                 /* When next RX descriptor is on a cache line boundary,
1551                  * prefetch the next 4 RX descriptors and next 8 pointers
1552                  * to mbufs.
1553                  */
1554                 if ((rx_id & 0x3) == 0) {
1555                         rte_prefetch0(&rx_ring[rx_id]);
1556                         rte_prefetch0(rxq->sw_ring[rx_id]);
1557                 }
1558
1559                 rxm = rxe;
1560                 dma_addr =
1561                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1562
1563                 /* Set data buffer address and data length of the mbuf */
1564                 rxdp->read.hdr_addr = 0;
1565                 rxdp->read.pkt_addr = dma_addr;
1566                 rx_packet_len = rte_le_to_cpu_16(rxd.wb.pkt_len) &
1567                                 IAVF_RX_FLX_DESC_PKT_LEN_M;
1568                 rxm->data_len = rx_packet_len;
1569                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1570
1571                 /* If this is the first buffer of the received packet, set the
1572                  * pointer to the first mbuf of the packet and initialize its
1573                  * context. Otherwise, update the total length and the number
1574                  * of segments of the current scattered packet, and update the
1575                  * pointer to the last mbuf of the current packet.
1576                  */
1577                 if (!first_seg) {
1578                         first_seg = rxm;
1579                         first_seg->nb_segs = 1;
1580                         first_seg->pkt_len = rx_packet_len;
1581                 } else {
1582                         first_seg->pkt_len =
1583                                 (uint16_t)(first_seg->pkt_len +
1584                                                 rx_packet_len);
1585                         first_seg->nb_segs++;
1586                         last_seg->next = rxm;
1587                 }
1588
1589                 /* If this is not the last buffer of the received packet,
1590                  * update the pointer to the last mbuf of the current scattered
1591                  * packet and continue to parse the RX ring.
1592                  */
1593                 if (!(rx_stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_EOF_S))) {
1594                         last_seg = rxm;
1595                         continue;
1596                 }
1597
1598                 /* This is the last buffer of the received packet. If the CRC
1599                  * is not stripped by the hardware:
1600                  *  - Subtract the CRC length from the total packet length.
1601                  *  - If the last buffer only contains the whole CRC or a part
1602                  *  of it, free the mbuf associated to the last buffer. If part
1603                  *  of the CRC is also contained in the previous mbuf, subtract
1604                  *  the length of that CRC part from the data length of the
1605                  *  previous mbuf.
1606                  */
1607                 rxm->next = NULL;
1608                 if (unlikely(rxq->crc_len > 0)) {
1609                         first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
1610                         if (rx_packet_len <= RTE_ETHER_CRC_LEN) {
1611                                 rte_pktmbuf_free_seg(rxm);
1612                                 first_seg->nb_segs--;
1613                                 last_seg->data_len =
1614                                         (uint16_t)(last_seg->data_len -
1615                                         (RTE_ETHER_CRC_LEN - rx_packet_len));
1616                                 last_seg->next = NULL;
1617                         } else {
1618                                 rxm->data_len = (uint16_t)(rx_packet_len -
1619                                                         RTE_ETHER_CRC_LEN);
1620                         }
1621                 }
1622
1623                 first_seg->port = rxq->port_id;
1624                 first_seg->ol_flags = 0;
1625                 first_seg->packet_type = ptype_tbl[IAVF_RX_FLEX_DESC_PTYPE_M &
1626                         rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
1627                 iavf_flex_rxd_to_vlan_tci(first_seg, &rxd);
1628                 iavf_flex_rxd_to_ipsec_crypto_status(first_seg, &rxd,
1629                                 &rxq->stats.ipsec_crypto);
1630                 rxq->rxd_to_pkt_fields(rxq, first_seg, &rxd);
1631                 pkt_flags = iavf_flex_rxd_error_to_pkt_flags(rx_stat_err0);
1632
1633                 first_seg->ol_flags |= pkt_flags;
1634
1635                 /* Prefetch data of first segment, if configured to do so. */
1636                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1637                                           first_seg->data_off));
1638                 rx_pkts[nb_rx++] = first_seg;
1639                 first_seg = NULL;
1640         }
1641
1642         /* Record index of the next RX descriptor to probe. */
1643         rxq->rx_tail = rx_id;
1644         rxq->pkt_first_seg = first_seg;
1645         rxq->pkt_last_seg = last_seg;
1646
1647         iavf_update_rx_tail(rxq, nb_hold, rx_id);
1648
1649         return nb_rx;
1650 }
1651
1652 /* implement recv_scattered_pkts  */
1653 uint16_t
1654 iavf_recv_scattered_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1655                         uint16_t nb_pkts)
1656 {
1657         struct iavf_rx_queue *rxq = rx_queue;
1658         union iavf_rx_desc rxd;
1659         struct rte_mbuf *rxe;
1660         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1661         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1662         struct rte_mbuf *nmb, *rxm;
1663         uint16_t rx_id = rxq->rx_tail;
1664         uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
1665         struct rte_eth_dev *dev;
1666         uint32_t rx_status;
1667         uint64_t qword1;
1668         uint64_t dma_addr;
1669         uint64_t pkt_flags;
1670
1671         volatile union iavf_rx_desc *rx_ring = rxq->rx_ring;
1672         volatile union iavf_rx_desc *rxdp;
1673         const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1674
1675         while (nb_rx < nb_pkts) {
1676                 rxdp = &rx_ring[rx_id];
1677                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1678                 rx_status = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
1679                             IAVF_RXD_QW1_STATUS_SHIFT;
1680
1681                 /* Check the DD bit */
1682                 if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)))
1683                         break;
1684                 IAVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
1685
1686                 nmb = rte_mbuf_raw_alloc(rxq->mp);
1687                 if (unlikely(!nmb)) {
1688                         PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1689                                    "queue_id=%u", rxq->port_id, rxq->queue_id);
1690                         dev = &rte_eth_devices[rxq->port_id];
1691                         dev->data->rx_mbuf_alloc_failed++;
1692                         break;
1693                 }
1694
1695                 rxd = *rxdp;
1696                 nb_hold++;
1697                 rxe = rxq->sw_ring[rx_id];
1698                 rxq->sw_ring[rx_id] = nmb;
1699                 rx_id++;
1700                 if (rx_id == rxq->nb_rx_desc)
1701                         rx_id = 0;
1702
1703                 /* Prefetch next mbuf */
1704                 rte_prefetch0(rxq->sw_ring[rx_id]);
1705
1706                 /* When next RX descriptor is on a cache line boundary,
1707                  * prefetch the next 4 RX descriptors and next 8 pointers
1708                  * to mbufs.
1709                  */
1710                 if ((rx_id & 0x3) == 0) {
1711                         rte_prefetch0(&rx_ring[rx_id]);
1712                         rte_prefetch0(rxq->sw_ring[rx_id]);
1713                 }
1714
1715                 rxm = rxe;
1716                 dma_addr =
1717                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1718
1719                 /* Set data buffer address and data length of the mbuf */
1720                 rxdp->read.hdr_addr = 0;
1721                 rxdp->read.pkt_addr = dma_addr;
1722                 rx_packet_len = (qword1 & IAVF_RXD_QW1_LENGTH_PBUF_MASK) >>
1723                                  IAVF_RXD_QW1_LENGTH_PBUF_SHIFT;
1724                 rxm->data_len = rx_packet_len;
1725                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1726
1727                 /* If this is the first buffer of the received packet, set the
1728                  * pointer to the first mbuf of the packet and initialize its
1729                  * context. Otherwise, update the total length and the number
1730                  * of segments of the current scattered packet, and update the
1731                  * pointer to the last mbuf of the current packet.
1732                  */
1733                 if (!first_seg) {
1734                         first_seg = rxm;
1735                         first_seg->nb_segs = 1;
1736                         first_seg->pkt_len = rx_packet_len;
1737                 } else {
1738                         first_seg->pkt_len =
1739                                 (uint16_t)(first_seg->pkt_len +
1740                                                 rx_packet_len);
1741                         first_seg->nb_segs++;
1742                         last_seg->next = rxm;
1743                 }
1744
1745                 /* If this is not the last buffer of the received packet,
1746                  * update the pointer to the last mbuf of the current scattered
1747                  * packet and continue to parse the RX ring.
1748                  */
1749                 if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_EOF_SHIFT))) {
1750                         last_seg = rxm;
1751                         continue;
1752                 }
1753
1754                 /* This is the last buffer of the received packet. If the CRC
1755                  * is not stripped by the hardware:
1756                  *  - Subtract the CRC length from the total packet length.
1757                  *  - If the last buffer only contains the whole CRC or a part
1758                  *  of it, free the mbuf associated to the last buffer. If part
1759                  *  of the CRC is also contained in the previous mbuf, subtract
1760                  *  the length of that CRC part from the data length of the
1761                  *  previous mbuf.
1762                  */
1763                 rxm->next = NULL;
1764                 if (unlikely(rxq->crc_len > 0)) {
1765                         first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
1766                         if (rx_packet_len <= RTE_ETHER_CRC_LEN) {
1767                                 rte_pktmbuf_free_seg(rxm);
1768                                 first_seg->nb_segs--;
1769                                 last_seg->data_len =
1770                                         (uint16_t)(last_seg->data_len -
1771                                         (RTE_ETHER_CRC_LEN - rx_packet_len));
1772                                 last_seg->next = NULL;
1773                         } else
1774                                 rxm->data_len = (uint16_t)(rx_packet_len -
1775                                                         RTE_ETHER_CRC_LEN);
1776                 }
1777
1778                 first_seg->port = rxq->port_id;
1779                 first_seg->ol_flags = 0;
1780                 iavf_rxd_to_vlan_tci(first_seg, &rxd);
1781                 pkt_flags = iavf_rxd_to_pkt_flags(qword1);
1782                 first_seg->packet_type =
1783                         ptype_tbl[(uint8_t)((qword1 &
1784                         IAVF_RXD_QW1_PTYPE_MASK) >> IAVF_RXD_QW1_PTYPE_SHIFT)];
1785
1786                 if (pkt_flags & RTE_MBUF_F_RX_RSS_HASH)
1787                         first_seg->hash.rss =
1788                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1789
1790                 if (pkt_flags & RTE_MBUF_F_RX_FDIR)
1791                         pkt_flags |= iavf_rxd_build_fdir(&rxd, first_seg);
1792
1793                 first_seg->ol_flags |= pkt_flags;
1794
1795                 /* Prefetch data of first segment, if configured to do so. */
1796                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1797                                           first_seg->data_off));
1798                 rx_pkts[nb_rx++] = first_seg;
1799                 first_seg = NULL;
1800         }
1801
1802         /* Record index of the next RX descriptor to probe. */
1803         rxq->rx_tail = rx_id;
1804         rxq->pkt_first_seg = first_seg;
1805         rxq->pkt_last_seg = last_seg;
1806
1807         iavf_update_rx_tail(rxq, nb_hold, rx_id);
1808
1809         return nb_rx;
1810 }
1811
1812 #define IAVF_LOOK_AHEAD 8
1813 static inline int
1814 iavf_rx_scan_hw_ring_flex_rxd(struct iavf_rx_queue *rxq)
1815 {
1816         volatile union iavf_rx_flex_desc *rxdp;
1817         struct rte_mbuf **rxep;
1818         struct rte_mbuf *mb;
1819         uint16_t stat_err0;
1820         uint16_t pkt_len;
1821         int32_t s[IAVF_LOOK_AHEAD], var, nb_dd;
1822         int32_t i, j, nb_rx = 0;
1823         uint64_t pkt_flags;
1824         const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1825
1826         rxdp = (volatile union iavf_rx_flex_desc *)&rxq->rx_ring[rxq->rx_tail];
1827         rxep = &rxq->sw_ring[rxq->rx_tail];
1828
1829         stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1830
1831         /* Make sure there is at least 1 packet to receive */
1832         if (!(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S)))
1833                 return 0;
1834
1835         /* Scan LOOK_AHEAD descriptors at a time to determine which
1836          * descriptors reference packets that are ready to be received.
1837          */
1838         for (i = 0; i < IAVF_RX_MAX_BURST; i += IAVF_LOOK_AHEAD,
1839              rxdp += IAVF_LOOK_AHEAD, rxep += IAVF_LOOK_AHEAD) {
1840                 /* Read desc statuses backwards to avoid race condition */
1841                 for (j = IAVF_LOOK_AHEAD - 1; j >= 0; j--)
1842                         s[j] = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1843
1844                 rte_smp_rmb();
1845
1846                 /* Compute how many contiguous DD bits were set */
1847                 for (j = 0, nb_dd = 0; j < IAVF_LOOK_AHEAD; j++) {
1848                         var = s[j] & (1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S);
1849 #ifdef RTE_ARCH_ARM
1850                         /* For Arm platforms, count only contiguous descriptors
1851                          * whose DD bit is set to 1. On Arm platforms, reads of
1852                          * descriptors can be reordered. Since the CPU may
1853                          * be reading the descriptors as the NIC updates them
1854                          * in memory, it is possbile that the DD bit for a
1855                          * descriptor earlier in the queue is read as not set
1856                          * while the DD bit for a descriptor later in the queue
1857                          * is read as set.
1858                          */
1859                         if (var)
1860                                 nb_dd += 1;
1861                         else
1862                                 break;
1863 #else
1864                         nb_dd += var;
1865 #endif
1866                 }
1867
1868                 nb_rx += nb_dd;
1869
1870                 /* Translate descriptor info to mbuf parameters */
1871                 for (j = 0; j < nb_dd; j++) {
1872                         IAVF_DUMP_RX_DESC(rxq, &rxdp[j],
1873                                           rxq->rx_tail +
1874                                           i * IAVF_LOOK_AHEAD + j);
1875
1876                         mb = rxep[j];
1877                         pkt_len = (rte_le_to_cpu_16(rxdp[j].wb.pkt_len) &
1878                                 IAVF_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
1879                         mb->data_len = pkt_len;
1880                         mb->pkt_len = pkt_len;
1881                         mb->ol_flags = 0;
1882
1883                         mb->packet_type = ptype_tbl[IAVF_RX_FLEX_DESC_PTYPE_M &
1884                                 rte_le_to_cpu_16(rxdp[j].wb.ptype_flex_flags0)];
1885                         iavf_flex_rxd_to_vlan_tci(mb, &rxdp[j]);
1886                         iavf_flex_rxd_to_ipsec_crypto_status(mb, &rxdp[j],
1887                                 &rxq->stats.ipsec_crypto);
1888                         rxq->rxd_to_pkt_fields(rxq, mb, &rxdp[j]);
1889                         stat_err0 = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1890                         pkt_flags = iavf_flex_rxd_error_to_pkt_flags(stat_err0);
1891
1892                         mb->ol_flags |= pkt_flags;
1893                 }
1894
1895                 for (j = 0; j < IAVF_LOOK_AHEAD; j++)
1896                         rxq->rx_stage[i + j] = rxep[j];
1897
1898                 if (nb_dd != IAVF_LOOK_AHEAD)
1899                         break;
1900         }
1901
1902         /* Clear software ring entries */
1903         for (i = 0; i < nb_rx; i++)
1904                 rxq->sw_ring[rxq->rx_tail + i] = NULL;
1905
1906         return nb_rx;
1907 }
1908
1909 static inline int
1910 iavf_rx_scan_hw_ring(struct iavf_rx_queue *rxq)
1911 {
1912         volatile union iavf_rx_desc *rxdp;
1913         struct rte_mbuf **rxep;
1914         struct rte_mbuf *mb;
1915         uint16_t pkt_len;
1916         uint64_t qword1;
1917         uint32_t rx_status;
1918         int32_t s[IAVF_LOOK_AHEAD], var, nb_dd;
1919         int32_t i, j, nb_rx = 0;
1920         uint64_t pkt_flags;
1921         const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1922
1923         rxdp = &rxq->rx_ring[rxq->rx_tail];
1924         rxep = &rxq->sw_ring[rxq->rx_tail];
1925
1926         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1927         rx_status = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
1928                     IAVF_RXD_QW1_STATUS_SHIFT;
1929
1930         /* Make sure there is at least 1 packet to receive */
1931         if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)))
1932                 return 0;
1933
1934         /* Scan LOOK_AHEAD descriptors at a time to determine which
1935          * descriptors reference packets that are ready to be received.
1936          */
1937         for (i = 0; i < IAVF_RX_MAX_BURST; i += IAVF_LOOK_AHEAD,
1938              rxdp += IAVF_LOOK_AHEAD, rxep += IAVF_LOOK_AHEAD) {
1939                 /* Read desc statuses backwards to avoid race condition */
1940                 for (j = IAVF_LOOK_AHEAD - 1; j >= 0; j--) {
1941                         qword1 = rte_le_to_cpu_64(
1942                                 rxdp[j].wb.qword1.status_error_len);
1943                         s[j] = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
1944                                IAVF_RXD_QW1_STATUS_SHIFT;
1945                 }
1946
1947                 rte_smp_rmb();
1948
1949                 /* Compute how many contiguous DD bits were set */
1950                 for (j = 0, nb_dd = 0; j < IAVF_LOOK_AHEAD; j++) {
1951                         var = s[j] & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT);
1952 #ifdef RTE_ARCH_ARM
1953                         /* For Arm platforms, count only contiguous descriptors
1954                          * whose DD bit is set to 1. On Arm platforms, reads of
1955                          * descriptors can be reordered. Since the CPU may
1956                          * be reading the descriptors as the NIC updates them
1957                          * in memory, it is possbile that the DD bit for a
1958                          * descriptor earlier in the queue is read as not set
1959                          * while the DD bit for a descriptor later in the queue
1960                          * is read as set.
1961                          */
1962                         if (var)
1963                                 nb_dd += 1;
1964                         else
1965                                 break;
1966 #else
1967                         nb_dd += var;
1968 #endif
1969                 }
1970
1971                 nb_rx += nb_dd;
1972
1973                 /* Translate descriptor info to mbuf parameters */
1974                 for (j = 0; j < nb_dd; j++) {
1975                         IAVF_DUMP_RX_DESC(rxq, &rxdp[j],
1976                                          rxq->rx_tail + i * IAVF_LOOK_AHEAD + j);
1977
1978                         mb = rxep[j];
1979                         qword1 = rte_le_to_cpu_64
1980                                         (rxdp[j].wb.qword1.status_error_len);
1981                         pkt_len = ((qword1 & IAVF_RXD_QW1_LENGTH_PBUF_MASK) >>
1982                                   IAVF_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
1983                         mb->data_len = pkt_len;
1984                         mb->pkt_len = pkt_len;
1985                         mb->ol_flags = 0;
1986                         iavf_rxd_to_vlan_tci(mb, &rxdp[j]);
1987                         pkt_flags = iavf_rxd_to_pkt_flags(qword1);
1988                         mb->packet_type =
1989                                 ptype_tbl[(uint8_t)((qword1 &
1990                                 IAVF_RXD_QW1_PTYPE_MASK) >>
1991                                 IAVF_RXD_QW1_PTYPE_SHIFT)];
1992
1993                         if (pkt_flags & RTE_MBUF_F_RX_RSS_HASH)
1994                                 mb->hash.rss = rte_le_to_cpu_32(
1995                                         rxdp[j].wb.qword0.hi_dword.rss);
1996
1997                         if (pkt_flags & RTE_MBUF_F_RX_FDIR)
1998                                 pkt_flags |= iavf_rxd_build_fdir(&rxdp[j], mb);
1999
2000                         mb->ol_flags |= pkt_flags;
2001                 }
2002
2003                 for (j = 0; j < IAVF_LOOK_AHEAD; j++)
2004                         rxq->rx_stage[i + j] = rxep[j];
2005
2006                 if (nb_dd != IAVF_LOOK_AHEAD)
2007                         break;
2008         }
2009
2010         /* Clear software ring entries */
2011         for (i = 0; i < nb_rx; i++)
2012                 rxq->sw_ring[rxq->rx_tail + i] = NULL;
2013
2014         return nb_rx;
2015 }
2016
2017 static inline uint16_t
2018 iavf_rx_fill_from_stage(struct iavf_rx_queue *rxq,
2019                        struct rte_mbuf **rx_pkts,
2020                        uint16_t nb_pkts)
2021 {
2022         uint16_t i;
2023         struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
2024
2025         nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
2026
2027         for (i = 0; i < nb_pkts; i++)
2028                 rx_pkts[i] = stage[i];
2029
2030         rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
2031         rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
2032
2033         return nb_pkts;
2034 }
2035
2036 static inline int
2037 iavf_rx_alloc_bufs(struct iavf_rx_queue *rxq)
2038 {
2039         volatile union iavf_rx_desc *rxdp;
2040         struct rte_mbuf **rxep;
2041         struct rte_mbuf *mb;
2042         uint16_t alloc_idx, i;
2043         uint64_t dma_addr;
2044         int diag;
2045
2046         /* Allocate buffers in bulk */
2047         alloc_idx = (uint16_t)(rxq->rx_free_trigger -
2048                                 (rxq->rx_free_thresh - 1));
2049         rxep = &rxq->sw_ring[alloc_idx];
2050         diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
2051                                     rxq->rx_free_thresh);
2052         if (unlikely(diag != 0)) {
2053                 PMD_RX_LOG(ERR, "Failed to get mbufs in bulk");
2054                 return -ENOMEM;
2055         }
2056
2057         rxdp = &rxq->rx_ring[alloc_idx];
2058         for (i = 0; i < rxq->rx_free_thresh; i++) {
2059                 if (likely(i < (rxq->rx_free_thresh - 1)))
2060                         /* Prefetch next mbuf */
2061                         rte_prefetch0(rxep[i + 1]);
2062
2063                 mb = rxep[i];
2064                 rte_mbuf_refcnt_set(mb, 1);
2065                 mb->next = NULL;
2066                 mb->data_off = RTE_PKTMBUF_HEADROOM;
2067                 mb->nb_segs = 1;
2068                 mb->port = rxq->port_id;
2069                 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mb));
2070                 rxdp[i].read.hdr_addr = 0;
2071                 rxdp[i].read.pkt_addr = dma_addr;
2072         }
2073
2074         /* Update rx tail register */
2075         rte_wmb();
2076         IAVF_PCI_REG_WC_WRITE_RELAXED(rxq->qrx_tail, rxq->rx_free_trigger);
2077
2078         rxq->rx_free_trigger =
2079                 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
2080         if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
2081                 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2082
2083         return 0;
2084 }
2085
2086 static inline uint16_t
2087 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
2088 {
2089         struct iavf_rx_queue *rxq = (struct iavf_rx_queue *)rx_queue;
2090         uint16_t nb_rx = 0;
2091
2092         if (!nb_pkts)
2093                 return 0;
2094
2095         if (rxq->rx_nb_avail)
2096                 return iavf_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
2097
2098         if (rxq->rxdid >= IAVF_RXDID_FLEX_NIC && rxq->rxdid <= IAVF_RXDID_LAST)
2099                 nb_rx = (uint16_t)iavf_rx_scan_hw_ring_flex_rxd(rxq);
2100         else
2101                 nb_rx = (uint16_t)iavf_rx_scan_hw_ring(rxq);
2102         rxq->rx_next_avail = 0;
2103         rxq->rx_nb_avail = nb_rx;
2104         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
2105
2106         if (rxq->rx_tail > rxq->rx_free_trigger) {
2107                 if (iavf_rx_alloc_bufs(rxq) != 0) {
2108                         uint16_t i, j;
2109
2110                         /* TODO: count rx_mbuf_alloc_failed here */
2111
2112                         rxq->rx_nb_avail = 0;
2113                         rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
2114                         for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
2115                                 rxq->sw_ring[j] = rxq->rx_stage[i];
2116
2117                         return 0;
2118                 }
2119         }
2120
2121         if (rxq->rx_tail >= rxq->nb_rx_desc)
2122                 rxq->rx_tail = 0;
2123
2124         PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u, nb_rx=%u",
2125                    rxq->port_id, rxq->queue_id,
2126                    rxq->rx_tail, nb_rx);
2127
2128         if (rxq->rx_nb_avail)
2129                 return iavf_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
2130
2131         return 0;
2132 }
2133
2134 static uint16_t
2135 iavf_recv_pkts_bulk_alloc(void *rx_queue,
2136                          struct rte_mbuf **rx_pkts,
2137                          uint16_t nb_pkts)
2138 {
2139         uint16_t nb_rx = 0, n, count;
2140
2141         if (unlikely(nb_pkts == 0))
2142                 return 0;
2143
2144         if (likely(nb_pkts <= IAVF_RX_MAX_BURST))
2145                 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
2146
2147         while (nb_pkts) {
2148                 n = RTE_MIN(nb_pkts, IAVF_RX_MAX_BURST);
2149                 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
2150                 nb_rx = (uint16_t)(nb_rx + count);
2151                 nb_pkts = (uint16_t)(nb_pkts - count);
2152                 if (count < n)
2153                         break;
2154         }
2155
2156         return nb_rx;
2157 }
2158
2159 static inline int
2160 iavf_xmit_cleanup(struct iavf_tx_queue *txq)
2161 {
2162         struct iavf_tx_entry *sw_ring = txq->sw_ring;
2163         uint16_t last_desc_cleaned = txq->last_desc_cleaned;
2164         uint16_t nb_tx_desc = txq->nb_tx_desc;
2165         uint16_t desc_to_clean_to;
2166         uint16_t nb_tx_to_clean;
2167
2168         volatile struct iavf_tx_desc *txd = txq->tx_ring;
2169
2170         desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->rs_thresh);
2171         if (desc_to_clean_to >= nb_tx_desc)
2172                 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
2173
2174         desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
2175         if ((txd[desc_to_clean_to].cmd_type_offset_bsz &
2176                         rte_cpu_to_le_64(IAVF_TXD_QW1_DTYPE_MASK)) !=
2177                         rte_cpu_to_le_64(IAVF_TX_DESC_DTYPE_DESC_DONE)) {
2178                 PMD_TX_LOG(DEBUG, "TX descriptor %4u is not done "
2179                            "(port=%d queue=%d)", desc_to_clean_to,
2180                            txq->port_id, txq->queue_id);
2181                 return -1;
2182         }
2183
2184         if (last_desc_cleaned > desc_to_clean_to)
2185                 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
2186                                                         desc_to_clean_to);
2187         else
2188                 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
2189                                         last_desc_cleaned);
2190
2191         txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
2192
2193         txq->last_desc_cleaned = desc_to_clean_to;
2194         txq->nb_free = (uint16_t)(txq->nb_free + nb_tx_to_clean);
2195
2196         return 0;
2197 }
2198
2199 /* Check if the context descriptor is needed for TX offloading */
2200 static inline uint16_t
2201 iavf_calc_context_desc(uint64_t flags, uint8_t vlan_flag)
2202 {
2203         if (flags & (RTE_MBUF_F_TX_TCP_SEG | RTE_MBUF_F_TX_UDP_SEG |
2204                         RTE_MBUF_F_TX_TUNNEL_MASK))
2205                 return 1;
2206         if (flags & RTE_MBUF_F_TX_VLAN &&
2207             vlan_flag & IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG2)
2208                 return 1;
2209         return 0;
2210 }
2211
2212 static inline void
2213 iavf_fill_ctx_desc_cmd_field(volatile uint64_t *field, struct rte_mbuf *m,
2214                 uint8_t vlan_flag)
2215 {
2216         uint64_t cmd = 0;
2217
2218         /* TSO enabled */
2219         if (m->ol_flags & (RTE_MBUF_F_TX_TCP_SEG | RTE_MBUF_F_TX_UDP_SEG))
2220                 cmd = IAVF_TX_CTX_DESC_TSO << IAVF_TXD_CTX_QW1_CMD_SHIFT;
2221
2222         if (m->ol_flags & RTE_MBUF_F_TX_VLAN &&
2223                         vlan_flag & IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG2) {
2224                 cmd |= IAVF_TX_CTX_DESC_IL2TAG2
2225                         << IAVF_TXD_CTX_QW1_CMD_SHIFT;
2226         }
2227
2228         *field |= cmd;
2229 }
2230
2231 static inline void
2232 iavf_fill_ctx_desc_ipsec_field(volatile uint64_t *field,
2233         struct iavf_ipsec_crypto_pkt_metadata *ipsec_md)
2234 {
2235         uint64_t ipsec_field =
2236                 (uint64_t)ipsec_md->ctx_desc_ipsec_params <<
2237                         IAVF_TXD_CTX_QW1_IPSEC_PARAMS_CIPHERBLK_SHIFT;
2238
2239         *field |= ipsec_field;
2240 }
2241
2242
2243 static inline void
2244 iavf_fill_ctx_desc_tunnelling_field(volatile uint64_t *qw0,
2245                 const struct rte_mbuf *m)
2246 {
2247         uint64_t eip_typ = IAVF_TX_CTX_DESC_EIPT_NONE;
2248         uint64_t eip_len = 0;
2249         uint64_t eip_noinc = 0;
2250         /* Default - IP_ID is increment in each segment of LSO */
2251
2252         switch (m->ol_flags & (RTE_MBUF_F_TX_OUTER_IPV4 |
2253                         RTE_MBUF_F_TX_OUTER_IPV6 |
2254                         RTE_MBUF_F_TX_OUTER_IP_CKSUM)) {
2255         case RTE_MBUF_F_TX_OUTER_IPV4:
2256                 eip_typ = IAVF_TX_CTX_DESC_EIPT_IPV4_NO_CHECKSUM_OFFLOAD;
2257                 eip_len = m->outer_l3_len >> 2;
2258         break;
2259         case RTE_MBUF_F_TX_OUTER_IPV4 | RTE_MBUF_F_TX_OUTER_IP_CKSUM:
2260                 eip_typ = IAVF_TX_CTX_DESC_EIPT_IPV4_CHECKSUM_OFFLOAD;
2261                 eip_len = m->outer_l3_len >> 2;
2262         break;
2263         case RTE_MBUF_F_TX_OUTER_IPV6:
2264                 eip_typ = IAVF_TX_CTX_DESC_EIPT_IPV6;
2265                 eip_len = m->outer_l3_len >> 2;
2266         break;
2267         }
2268
2269         *qw0 = eip_typ << IAVF_TXD_CTX_QW0_TUN_PARAMS_EIPT_SHIFT |
2270                 eip_len << IAVF_TXD_CTX_QW0_TUN_PARAMS_EIPLEN_SHIFT |
2271                 eip_noinc << IAVF_TXD_CTX_QW0_TUN_PARAMS_EIP_NOINC_SHIFT;
2272 }
2273
2274 static inline uint16_t
2275 iavf_fill_ctx_desc_segmentation_field(volatile uint64_t *field,
2276         struct rte_mbuf *m, struct iavf_ipsec_crypto_pkt_metadata *ipsec_md)
2277 {
2278         uint64_t segmentation_field = 0;
2279         uint64_t total_length = 0;
2280
2281         if (m->ol_flags & RTE_MBUF_F_TX_SEC_OFFLOAD) {
2282                 total_length = ipsec_md->l4_payload_len;
2283         } else {
2284                 total_length = m->pkt_len - (m->l2_len + m->l3_len + m->l4_len);
2285
2286                 if (m->ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK)
2287                         total_length -= m->outer_l3_len;
2288         }
2289
2290 #ifdef RTE_LIBRTE_IAVF_DEBUG_TX
2291         if (!m->l4_len || !m->tso_segsz)
2292                 PMD_TX_LOG(DEBUG, "L4 length %d, LSO Segment size %d",
2293                          m->l4_len, m->tso_segsz);
2294         if (m->tso_segsz < 88)
2295                 PMD_TX_LOG(DEBUG, "LSO Segment size %d is less than minimum %d",
2296                         m->tso_segsz, 88);
2297 #endif
2298         segmentation_field =
2299                 (((uint64_t)total_length << IAVF_TXD_CTX_QW1_TSO_LEN_SHIFT) &
2300                                 IAVF_TXD_CTX_QW1_TSO_LEN_MASK) |
2301                 (((uint64_t)m->tso_segsz << IAVF_TXD_CTX_QW1_MSS_SHIFT) &
2302                                 IAVF_TXD_CTX_QW1_MSS_MASK);
2303
2304         *field |= segmentation_field;
2305
2306         return total_length;
2307 }
2308
2309
2310 struct iavf_tx_context_desc_qws {
2311         __le64 qw0;
2312         __le64 qw1;
2313 };
2314
2315 static inline void
2316 iavf_fill_context_desc(volatile struct iavf_tx_context_desc *desc,
2317         struct rte_mbuf *m, struct iavf_ipsec_crypto_pkt_metadata *ipsec_md,
2318         uint16_t *tlen, uint8_t vlan_flag)
2319 {
2320         volatile struct iavf_tx_context_desc_qws *desc_qws =
2321                         (volatile struct iavf_tx_context_desc_qws *)desc;
2322         /* fill descriptor type field */
2323         desc_qws->qw1 = IAVF_TX_DESC_DTYPE_CONTEXT;
2324
2325         /* fill command field */
2326         iavf_fill_ctx_desc_cmd_field(&desc_qws->qw1, m, vlan_flag);
2327
2328         /* fill segmentation field */
2329         if (m->ol_flags & (RTE_MBUF_F_TX_TCP_SEG | RTE_MBUF_F_TX_UDP_SEG)) {
2330                 /* fill IPsec field */
2331                 if (m->ol_flags & RTE_MBUF_F_TX_SEC_OFFLOAD)
2332                         iavf_fill_ctx_desc_ipsec_field(&desc_qws->qw1,
2333                                 ipsec_md);
2334
2335                 *tlen = iavf_fill_ctx_desc_segmentation_field(&desc_qws->qw1,
2336                                 m, ipsec_md);
2337         }
2338
2339         /* fill tunnelling field */
2340         if (m->ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK)
2341                 iavf_fill_ctx_desc_tunnelling_field(&desc_qws->qw0, m);
2342         else
2343                 desc_qws->qw0 = 0;
2344
2345         desc_qws->qw0 = rte_cpu_to_le_64(desc_qws->qw0);
2346         desc_qws->qw1 = rte_cpu_to_le_64(desc_qws->qw1);
2347
2348         if (vlan_flag & IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG2)
2349                 desc->l2tag2 = m->vlan_tci;
2350 }
2351
2352
2353 static inline void
2354 iavf_fill_ipsec_desc(volatile struct iavf_tx_ipsec_desc *desc,
2355         const struct iavf_ipsec_crypto_pkt_metadata *md, uint16_t *ipsec_len)
2356 {
2357         desc->qw0 = rte_cpu_to_le_64(((uint64_t)md->l4_payload_len <<
2358                 IAVF_IPSEC_TX_DESC_QW0_L4PAYLEN_SHIFT) |
2359                 ((uint64_t)md->esn << IAVF_IPSEC_TX_DESC_QW0_IPSECESN_SHIFT) |
2360                 ((uint64_t)md->esp_trailer_len <<
2361                                 IAVF_IPSEC_TX_DESC_QW0_TRAILERLEN_SHIFT));
2362
2363         desc->qw1 = rte_cpu_to_le_64(((uint64_t)md->sa_idx <<
2364                 IAVF_IPSEC_TX_DESC_QW1_IPSECSA_SHIFT) |
2365                 ((uint64_t)md->next_proto <<
2366                                 IAVF_IPSEC_TX_DESC_QW1_IPSECNH_SHIFT) |
2367                 ((uint64_t)(md->len_iv & 0x3) <<
2368                                 IAVF_IPSEC_TX_DESC_QW1_IVLEN_SHIFT) |
2369                 ((uint64_t)(md->ol_flags & IAVF_IPSEC_CRYPTO_OL_FLAGS_NATT ?
2370                                 1ULL : 0ULL) <<
2371                                 IAVF_IPSEC_TX_DESC_QW1_UDP_SHIFT) |
2372                 (uint64_t)IAVF_TX_DESC_DTYPE_IPSEC);
2373
2374         /**
2375          * TODO: Pre-calculate this in the Session initialization
2376          *
2377          * Calculate IPsec length required in data descriptor func when TSO
2378          * offload is enabled
2379          */
2380         *ipsec_len = sizeof(struct rte_esp_hdr) + (md->len_iv >> 2) +
2381                         (md->ol_flags & IAVF_IPSEC_CRYPTO_OL_FLAGS_NATT ?
2382                         sizeof(struct rte_udp_hdr) : 0);
2383 }
2384
2385 static inline void
2386 iavf_build_data_desc_cmd_offset_fields(volatile uint64_t *qw1,
2387                 struct rte_mbuf *m, uint8_t vlan_flag)
2388 {
2389         uint64_t command = 0;
2390         uint64_t offset = 0;
2391         uint64_t l2tag1 = 0;
2392
2393         *qw1 = IAVF_TX_DESC_DTYPE_DATA;
2394
2395         command = (uint64_t)IAVF_TX_DESC_CMD_ICRC;
2396
2397         /* Descriptor based VLAN insertion */
2398         if ((vlan_flag & IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG1) &&
2399                         m->ol_flags & RTE_MBUF_F_TX_VLAN) {
2400                 command |= (uint64_t)IAVF_TX_DESC_CMD_IL2TAG1;
2401                 l2tag1 |= m->vlan_tci;
2402         }
2403
2404         /* Set MACLEN */
2405         offset |= (m->l2_len >> 1) << IAVF_TX_DESC_LENGTH_MACLEN_SHIFT;
2406
2407         /* Enable L3 checksum offloading inner */
2408         if (m->ol_flags & (RTE_MBUF_F_TX_IP_CKSUM | RTE_MBUF_F_TX_IPV4)) {
2409                 command |= IAVF_TX_DESC_CMD_IIPT_IPV4_CSUM;
2410                 offset |= (m->l3_len >> 2) << IAVF_TX_DESC_LENGTH_IPLEN_SHIFT;
2411         } else if (m->ol_flags & RTE_MBUF_F_TX_IPV4) {
2412                 command |= IAVF_TX_DESC_CMD_IIPT_IPV4;
2413                 offset |= (m->l3_len >> 2) << IAVF_TX_DESC_LENGTH_IPLEN_SHIFT;
2414         } else if (m->ol_flags & RTE_MBUF_F_TX_IPV6) {
2415                 command |= IAVF_TX_DESC_CMD_IIPT_IPV6;
2416                 offset |= (m->l3_len >> 2) << IAVF_TX_DESC_LENGTH_IPLEN_SHIFT;
2417         }
2418
2419         if (m->ol_flags & RTE_MBUF_F_TX_TCP_SEG) {
2420                 command |= IAVF_TX_DESC_CMD_L4T_EOFT_TCP;
2421                 offset |= (m->l4_len >> 2) <<
2422                               IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2423         }
2424
2425         /* Enable L4 checksum offloads */
2426         switch (m->ol_flags & RTE_MBUF_F_TX_L4_MASK) {
2427         case RTE_MBUF_F_TX_TCP_CKSUM:
2428                 command |= IAVF_TX_DESC_CMD_L4T_EOFT_TCP;
2429                 offset |= (sizeof(struct rte_tcp_hdr) >> 2) <<
2430                                 IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2431                 break;
2432         case RTE_MBUF_F_TX_SCTP_CKSUM:
2433                 command |= IAVF_TX_DESC_CMD_L4T_EOFT_SCTP;
2434                 offset |= (sizeof(struct rte_sctp_hdr) >> 2) <<
2435                                 IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2436                 break;
2437         case RTE_MBUF_F_TX_UDP_CKSUM:
2438                 command |= IAVF_TX_DESC_CMD_L4T_EOFT_UDP;
2439                 offset |= (sizeof(struct rte_udp_hdr) >> 2) <<
2440                                 IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2441                 break;
2442         }
2443
2444         *qw1 = rte_cpu_to_le_64((((uint64_t)command <<
2445                 IAVF_TXD_DATA_QW1_CMD_SHIFT) & IAVF_TXD_DATA_QW1_CMD_MASK) |
2446                 (((uint64_t)offset << IAVF_TXD_DATA_QW1_OFFSET_SHIFT) &
2447                 IAVF_TXD_DATA_QW1_OFFSET_MASK) |
2448                 ((uint64_t)l2tag1 << IAVF_TXD_DATA_QW1_L2TAG1_SHIFT));
2449 }
2450
2451 static inline void
2452 iavf_fill_data_desc(volatile struct iavf_tx_desc *desc,
2453         struct rte_mbuf *m, uint64_t desc_template,
2454         uint16_t tlen, uint16_t ipseclen)
2455 {
2456         uint32_t hdrlen = m->l2_len;
2457         uint32_t bufsz = 0;
2458
2459         /* fill data descriptor qw1 from template */
2460         desc->cmd_type_offset_bsz = desc_template;
2461
2462         /* set data buffer address */
2463         desc->buffer_addr = rte_mbuf_data_iova(m);
2464
2465         /* calculate data buffer size less set header lengths */
2466         if ((m->ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK) &&
2467                         (m->ol_flags & (RTE_MBUF_F_TX_TCP_SEG |
2468                                         RTE_MBUF_F_TX_UDP_SEG))) {
2469                 hdrlen += m->outer_l3_len;
2470                 if (m->ol_flags & RTE_MBUF_F_TX_L4_MASK)
2471                         hdrlen += m->l3_len + m->l4_len;
2472                 else
2473                         hdrlen += m->l3_len;
2474                 if (m->ol_flags & RTE_MBUF_F_TX_SEC_OFFLOAD)
2475                         hdrlen += ipseclen;
2476                 bufsz = hdrlen + tlen;
2477         } else if ((m->ol_flags & RTE_MBUF_F_TX_SEC_OFFLOAD) &&
2478                         (m->ol_flags & (RTE_MBUF_F_TX_TCP_SEG |
2479                                         RTE_MBUF_F_TX_UDP_SEG))) {
2480                 hdrlen += m->outer_l3_len + m->l3_len + ipseclen;
2481                 if (m->ol_flags & RTE_MBUF_F_TX_L4_MASK)
2482                         hdrlen += m->l4_len;
2483                 bufsz = hdrlen + tlen;
2484
2485         } else {
2486                 bufsz = m->data_len;
2487         }
2488
2489         /* set data buffer size */
2490         desc->cmd_type_offset_bsz |=
2491                 (((uint64_t)bufsz << IAVF_TXD_DATA_QW1_TX_BUF_SZ_SHIFT) &
2492                 IAVF_TXD_DATA_QW1_TX_BUF_SZ_MASK);
2493
2494         desc->buffer_addr = rte_cpu_to_le_64(desc->buffer_addr);
2495         desc->cmd_type_offset_bsz = rte_cpu_to_le_64(desc->cmd_type_offset_bsz);
2496 }
2497
2498
2499 static struct iavf_ipsec_crypto_pkt_metadata *
2500 iavf_ipsec_crypto_get_pkt_metadata(const struct iavf_tx_queue *txq,
2501                 struct rte_mbuf *m)
2502 {
2503         if (m->ol_flags & RTE_MBUF_F_TX_SEC_OFFLOAD)
2504                 return RTE_MBUF_DYNFIELD(m, txq->ipsec_crypto_pkt_md_offset,
2505                                 struct iavf_ipsec_crypto_pkt_metadata *);
2506
2507         return NULL;
2508 }
2509
2510 /* TX function */
2511 uint16_t
2512 iavf_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2513 {
2514         struct iavf_tx_queue *txq = tx_queue;
2515         volatile struct iavf_tx_desc *txr = txq->tx_ring;
2516         struct iavf_tx_entry *txe_ring = txq->sw_ring;
2517         struct iavf_tx_entry *txe, *txn;
2518         struct rte_mbuf *mb, *mb_seg;
2519         uint16_t desc_idx, desc_idx_last;
2520         uint16_t idx;
2521
2522
2523         /* Check if the descriptor ring needs to be cleaned. */
2524         if (txq->nb_free < txq->free_thresh)
2525                 iavf_xmit_cleanup(txq);
2526
2527         desc_idx = txq->tx_tail;
2528         txe = &txe_ring[desc_idx];
2529
2530 #ifdef RTE_LIBRTE_IAVF_DEBUG_TX_DESC_RING
2531                 iavf_dump_tx_entry_ring(txq);
2532                 iavf_dump_tx_desc_ring(txq);
2533 #endif
2534
2535
2536         for (idx = 0; idx < nb_pkts; idx++) {
2537                 volatile struct iavf_tx_desc *ddesc;
2538                 struct iavf_ipsec_crypto_pkt_metadata *ipsec_md;
2539
2540                 uint16_t nb_desc_ctx, nb_desc_ipsec;
2541                 uint16_t nb_desc_data, nb_desc_required;
2542                 uint16_t tlen = 0, ipseclen = 0;
2543                 uint64_t ddesc_template = 0;
2544                 uint64_t ddesc_cmd = 0;
2545
2546                 mb = tx_pkts[idx];
2547
2548                 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
2549
2550                 /**
2551                  * Get metadata for ipsec crypto from mbuf dynamic fields if
2552                  * security offload is specified.
2553                  */
2554                 ipsec_md = iavf_ipsec_crypto_get_pkt_metadata(txq, mb);
2555
2556                 nb_desc_data = mb->nb_segs;
2557                 nb_desc_ctx =
2558                         iavf_calc_context_desc(mb->ol_flags, txq->vlan_flag);
2559                 nb_desc_ipsec = !!(mb->ol_flags & RTE_MBUF_F_TX_SEC_OFFLOAD);
2560
2561                 /**
2562                  * The number of descriptors that must be allocated for
2563                  * a packet equals to the number of the segments of that
2564                  * packet plus the context and ipsec descriptors if needed.
2565                  */
2566                 nb_desc_required = nb_desc_data + nb_desc_ctx + nb_desc_ipsec;
2567
2568                 desc_idx_last = (uint16_t)(desc_idx + nb_desc_required - 1);
2569
2570                 /* wrap descriptor ring */
2571                 if (desc_idx_last >= txq->nb_tx_desc)
2572                         desc_idx_last =
2573                                 (uint16_t)(desc_idx_last - txq->nb_tx_desc);
2574
2575                 PMD_TX_LOG(DEBUG,
2576                         "port_id=%u queue_id=%u tx_first=%u tx_last=%u",
2577                         txq->port_id, txq->queue_id, desc_idx, desc_idx_last);
2578
2579                 if (nb_desc_required > txq->nb_free) {
2580                         if (iavf_xmit_cleanup(txq)) {
2581                                 if (idx == 0)
2582                                         return 0;
2583                                 goto end_of_tx;
2584                         }
2585                         if (unlikely(nb_desc_required > txq->rs_thresh)) {
2586                                 while (nb_desc_required > txq->nb_free) {
2587                                         if (iavf_xmit_cleanup(txq)) {
2588                                                 if (idx == 0)
2589                                                         return 0;
2590                                                 goto end_of_tx;
2591                                         }
2592                                 }
2593                         }
2594                 }
2595
2596                 iavf_build_data_desc_cmd_offset_fields(&ddesc_template, mb,
2597                         txq->vlan_flag);
2598
2599                         /* Setup TX context descriptor if required */
2600                 if (nb_desc_ctx) {
2601                         volatile struct iavf_tx_context_desc *ctx_desc =
2602                                 (volatile struct iavf_tx_context_desc *)
2603                                         &txr[desc_idx];
2604
2605                         /* clear QW0 or the previous writeback value
2606                          * may impact next write
2607                          */
2608                         *(volatile uint64_t *)ctx_desc = 0;
2609
2610                         txn = &txe_ring[txe->next_id];
2611                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
2612
2613                         if (txe->mbuf) {
2614                                 rte_pktmbuf_free_seg(txe->mbuf);
2615                                 txe->mbuf = NULL;
2616                         }
2617
2618                         iavf_fill_context_desc(ctx_desc, mb, ipsec_md, &tlen,
2619                                 txq->vlan_flag);
2620                         IAVF_DUMP_TX_DESC(txq, ctx_desc, desc_idx);
2621
2622                         txe->last_id = desc_idx_last;
2623                         desc_idx = txe->next_id;
2624                         txe = txn;
2625                         }
2626
2627                 if (nb_desc_ipsec) {
2628                         volatile struct iavf_tx_ipsec_desc *ipsec_desc =
2629                                 (volatile struct iavf_tx_ipsec_desc *)
2630                                         &txr[desc_idx];
2631
2632                         txn = &txe_ring[txe->next_id];
2633                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
2634
2635                         if (txe->mbuf) {
2636                                 rte_pktmbuf_free_seg(txe->mbuf);
2637                                 txe->mbuf = NULL;
2638                 }
2639
2640                         iavf_fill_ipsec_desc(ipsec_desc, ipsec_md, &ipseclen);
2641
2642                         IAVF_DUMP_TX_DESC(txq, ipsec_desc, desc_idx);
2643
2644                         txe->last_id = desc_idx_last;
2645                         desc_idx = txe->next_id;
2646                         txe = txn;
2647                 }
2648
2649                 mb_seg = mb;
2650
2651                 do {
2652                         ddesc = (volatile struct iavf_tx_desc *)
2653                                         &txr[desc_idx];
2654
2655                         txn = &txe_ring[txe->next_id];
2656                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
2657
2658                         if (txe->mbuf)
2659                                 rte_pktmbuf_free_seg(txe->mbuf);
2660
2661                         txe->mbuf = mb_seg;
2662                         iavf_fill_data_desc(ddesc, mb_seg,
2663                                         ddesc_template, tlen, ipseclen);
2664
2665                         IAVF_DUMP_TX_DESC(txq, ddesc, desc_idx);
2666
2667                         txe->last_id = desc_idx_last;
2668                         desc_idx = txe->next_id;
2669                         txe = txn;
2670                         mb_seg = mb_seg->next;
2671                 } while (mb_seg);
2672
2673                 /* The last packet data descriptor needs End Of Packet (EOP) */
2674                 ddesc_cmd = IAVF_TX_DESC_CMD_EOP;
2675
2676                 txq->nb_used = (uint16_t)(txq->nb_used + nb_desc_required);
2677                 txq->nb_free = (uint16_t)(txq->nb_free - nb_desc_required);
2678
2679                 if (txq->nb_used >= txq->rs_thresh) {
2680                         PMD_TX_LOG(DEBUG, "Setting RS bit on TXD id="
2681                                    "%4u (port=%d queue=%d)",
2682                                    desc_idx_last, txq->port_id, txq->queue_id);
2683
2684                         ddesc_cmd |= IAVF_TX_DESC_CMD_RS;
2685
2686                         /* Update txq RS bit counters */
2687                         txq->nb_used = 0;
2688                 }
2689
2690                 ddesc->cmd_type_offset_bsz |= rte_cpu_to_le_64(ddesc_cmd <<
2691                                 IAVF_TXD_DATA_QW1_CMD_SHIFT);
2692
2693                 IAVF_DUMP_TX_DESC(txq, ddesc, desc_idx - 1);
2694         }
2695
2696 end_of_tx:
2697         rte_wmb();
2698
2699         PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
2700                    txq->port_id, txq->queue_id, desc_idx, idx);
2701
2702         IAVF_PCI_REG_WRITE_RELAXED(txq->qtx_tail, desc_idx);
2703         txq->tx_tail = desc_idx;
2704
2705         return idx;
2706 }
2707
2708 /* Check if the packet with vlan user priority is transmitted in the
2709  * correct queue.
2710  */
2711 static int
2712 iavf_check_vlan_up2tc(struct iavf_tx_queue *txq, struct rte_mbuf *m)
2713 {
2714         struct rte_eth_dev *dev = &rte_eth_devices[txq->port_id];
2715         struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2716         uint16_t up;
2717
2718         up = m->vlan_tci >> IAVF_VLAN_TAG_PCP_OFFSET;
2719
2720         if (!(vf->qos_cap->cap[txq->tc].tc_prio & BIT(up))) {
2721                 PMD_TX_LOG(ERR, "packet with vlan pcp %u cannot transmit in queue %u\n",
2722                         up, txq->queue_id);
2723                 return -1;
2724         } else {
2725                 return 0;
2726         }
2727 }
2728
2729 /* TX prep functions */
2730 uint16_t
2731 iavf_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
2732               uint16_t nb_pkts)
2733 {
2734         int i, ret;
2735         uint64_t ol_flags;
2736         struct rte_mbuf *m;
2737         struct iavf_tx_queue *txq = tx_queue;
2738         struct rte_eth_dev *dev = &rte_eth_devices[txq->port_id];
2739         struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2740
2741         for (i = 0; i < nb_pkts; i++) {
2742                 m = tx_pkts[i];
2743                 ol_flags = m->ol_flags;
2744
2745                 /* Check condition for nb_segs > IAVF_TX_MAX_MTU_SEG. */
2746                 if (!(ol_flags & RTE_MBUF_F_TX_TCP_SEG)) {
2747                         if (m->nb_segs > IAVF_TX_MAX_MTU_SEG) {
2748                                 rte_errno = EINVAL;
2749                                 return i;
2750                         }
2751                 } else if ((m->tso_segsz < IAVF_MIN_TSO_MSS) ||
2752                            (m->tso_segsz > IAVF_MAX_TSO_MSS)) {
2753                         /* MSS outside the range are considered malicious */
2754                         rte_errno = EINVAL;
2755                         return i;
2756                 }
2757
2758                 if (ol_flags & IAVF_TX_OFFLOAD_NOTSUP_MASK) {
2759                         rte_errno = ENOTSUP;
2760                         return i;
2761                 }
2762
2763 #ifdef RTE_ETHDEV_DEBUG_TX
2764                 ret = rte_validate_tx_offload(m);
2765                 if (ret != 0) {
2766                         rte_errno = -ret;
2767                         return i;
2768                 }
2769 #endif
2770                 ret = rte_net_intel_cksum_prepare(m);
2771                 if (ret != 0) {
2772                         rte_errno = -ret;
2773                         return i;
2774                 }
2775
2776                 if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_QOS &&
2777                     ol_flags & (RTE_MBUF_F_RX_VLAN_STRIPPED | RTE_MBUF_F_RX_VLAN)) {
2778                         ret = iavf_check_vlan_up2tc(txq, m);
2779                         if (ret != 0) {
2780                                 rte_errno = -ret;
2781                                 return i;
2782                         }
2783                 }
2784         }
2785
2786         return i;
2787 }
2788
2789 /* choose rx function*/
2790 void
2791 iavf_set_rx_function(struct rte_eth_dev *dev)
2792 {
2793         struct iavf_adapter *adapter =
2794                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2795         struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2796
2797 #ifdef RTE_ARCH_X86
2798         struct iavf_rx_queue *rxq;
2799         int i;
2800         int check_ret;
2801         bool use_avx2 = false;
2802         bool use_avx512 = false;
2803         bool use_flex = false;
2804
2805         check_ret = iavf_rx_vec_dev_check(dev);
2806         if (check_ret >= 0 &&
2807             rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
2808                 if ((rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
2809                      rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) &&
2810                     rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256)
2811                         use_avx2 = true;
2812
2813 #ifdef CC_AVX512_SUPPORT
2814                 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 &&
2815                     rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1 &&
2816                     rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512)
2817                         use_avx512 = true;
2818 #endif
2819
2820                 if (vf->vf_res->vf_cap_flags &
2821                         VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC)
2822                         use_flex = true;
2823
2824                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2825                         rxq = dev->data->rx_queues[i];
2826                         (void)iavf_rxq_vec_setup(rxq);
2827                 }
2828
2829                 if (dev->data->scattered_rx) {
2830                         if (!use_avx512) {
2831                                 PMD_DRV_LOG(DEBUG,
2832                                             "Using %sVector Scattered Rx (port %d).",
2833                                             use_avx2 ? "avx2 " : "",
2834                                             dev->data->port_id);
2835                         } else {
2836                                 if (check_ret == IAVF_VECTOR_PATH)
2837                                         PMD_DRV_LOG(DEBUG,
2838                                                     "Using AVX512 Vector Scattered Rx (port %d).",
2839                                                     dev->data->port_id);
2840                                 else
2841                                         PMD_DRV_LOG(DEBUG,
2842                                                     "Using AVX512 OFFLOAD Vector Scattered Rx (port %d).",
2843                                                     dev->data->port_id);
2844                         }
2845                         if (use_flex) {
2846                                 dev->rx_pkt_burst = use_avx2 ?
2847                                         iavf_recv_scattered_pkts_vec_avx2_flex_rxd :
2848                                         iavf_recv_scattered_pkts_vec_flex_rxd;
2849 #ifdef CC_AVX512_SUPPORT
2850                                 if (use_avx512) {
2851                                         if (check_ret == IAVF_VECTOR_PATH)
2852                                                 dev->rx_pkt_burst =
2853                                                         iavf_recv_scattered_pkts_vec_avx512_flex_rxd;
2854                                         else
2855                                                 dev->rx_pkt_burst =
2856                                                         iavf_recv_scattered_pkts_vec_avx512_flex_rxd_offload;
2857                                 }
2858 #endif
2859                         } else {
2860                                 dev->rx_pkt_burst = use_avx2 ?
2861                                         iavf_recv_scattered_pkts_vec_avx2 :
2862                                         iavf_recv_scattered_pkts_vec;
2863 #ifdef CC_AVX512_SUPPORT
2864                                 if (use_avx512) {
2865                                         if (check_ret == IAVF_VECTOR_PATH)
2866                                                 dev->rx_pkt_burst =
2867                                                         iavf_recv_scattered_pkts_vec_avx512;
2868                                         else
2869                                                 dev->rx_pkt_burst =
2870                                                         iavf_recv_scattered_pkts_vec_avx512_offload;
2871                                 }
2872 #endif
2873                         }
2874                 } else {
2875                         if (!use_avx512) {
2876                                 PMD_DRV_LOG(DEBUG, "Using %sVector Rx (port %d).",
2877                                             use_avx2 ? "avx2 " : "",
2878                                             dev->data->port_id);
2879                         } else {
2880                                 if (check_ret == IAVF_VECTOR_PATH)
2881                                         PMD_DRV_LOG(DEBUG,
2882                                                     "Using AVX512 Vector Rx (port %d).",
2883                                                     dev->data->port_id);
2884                                 else
2885                                         PMD_DRV_LOG(DEBUG,
2886                                                     "Using AVX512 OFFLOAD Vector Rx (port %d).",
2887                                                     dev->data->port_id);
2888                         }
2889                         if (use_flex) {
2890                                 dev->rx_pkt_burst = use_avx2 ?
2891                                         iavf_recv_pkts_vec_avx2_flex_rxd :
2892                                         iavf_recv_pkts_vec_flex_rxd;
2893 #ifdef CC_AVX512_SUPPORT
2894                                 if (use_avx512) {
2895                                         if (check_ret == IAVF_VECTOR_PATH)
2896                                                 dev->rx_pkt_burst =
2897                                                         iavf_recv_pkts_vec_avx512_flex_rxd;
2898                                         else
2899                                                 dev->rx_pkt_burst =
2900                                                         iavf_recv_pkts_vec_avx512_flex_rxd_offload;
2901                                 }
2902 #endif
2903                         } else {
2904                                 dev->rx_pkt_burst = use_avx2 ?
2905                                         iavf_recv_pkts_vec_avx2 :
2906                                         iavf_recv_pkts_vec;
2907 #ifdef CC_AVX512_SUPPORT
2908                                 if (use_avx512) {
2909                                         if (check_ret == IAVF_VECTOR_PATH)
2910                                                 dev->rx_pkt_burst =
2911                                                         iavf_recv_pkts_vec_avx512;
2912                                         else
2913                                                 dev->rx_pkt_burst =
2914                                                         iavf_recv_pkts_vec_avx512_offload;
2915                                 }
2916 #endif
2917                         }
2918                 }
2919
2920                 return;
2921         }
2922
2923 #endif
2924         if (dev->data->scattered_rx) {
2925                 PMD_DRV_LOG(DEBUG, "Using a Scattered Rx callback (port=%d).",
2926                             dev->data->port_id);
2927                 if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC)
2928                         dev->rx_pkt_burst = iavf_recv_scattered_pkts_flex_rxd;
2929                 else
2930                         dev->rx_pkt_burst = iavf_recv_scattered_pkts;
2931         } else if (adapter->rx_bulk_alloc_allowed) {
2932                 PMD_DRV_LOG(DEBUG, "Using bulk Rx callback (port=%d).",
2933                             dev->data->port_id);
2934                 dev->rx_pkt_burst = iavf_recv_pkts_bulk_alloc;
2935         } else {
2936                 PMD_DRV_LOG(DEBUG, "Using Basic Rx callback (port=%d).",
2937                             dev->data->port_id);
2938                 if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC)
2939                         dev->rx_pkt_burst = iavf_recv_pkts_flex_rxd;
2940                 else
2941                         dev->rx_pkt_burst = iavf_recv_pkts;
2942         }
2943 }
2944
2945 /* choose tx function*/
2946 void
2947 iavf_set_tx_function(struct rte_eth_dev *dev)
2948 {
2949 #ifdef RTE_ARCH_X86
2950         struct iavf_tx_queue *txq;
2951         int i;
2952         int check_ret;
2953         bool use_sse = false;
2954         bool use_avx2 = false;
2955         bool use_avx512 = false;
2956
2957         check_ret = iavf_tx_vec_dev_check(dev);
2958
2959         if (check_ret >= 0 &&
2960             rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
2961                 /* SSE and AVX2 not support offload path yet. */
2962                 if (check_ret == IAVF_VECTOR_PATH) {
2963                         use_sse = true;
2964                         if ((rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
2965                              rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) &&
2966                             rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256)
2967                                 use_avx2 = true;
2968                 }
2969 #ifdef CC_AVX512_SUPPORT
2970                 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 &&
2971                     rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1 &&
2972                     rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512)
2973                         use_avx512 = true;
2974 #endif
2975
2976                 if (!use_sse && !use_avx2 && !use_avx512)
2977                         goto normal;
2978
2979                 if (!use_avx512) {
2980                         PMD_DRV_LOG(DEBUG, "Using %sVector Tx (port %d).",
2981                                     use_avx2 ? "avx2 " : "",
2982                                     dev->data->port_id);
2983                         dev->tx_pkt_burst = use_avx2 ?
2984                                             iavf_xmit_pkts_vec_avx2 :
2985                                             iavf_xmit_pkts_vec;
2986                 }
2987                 dev->tx_pkt_prepare = NULL;
2988 #ifdef CC_AVX512_SUPPORT
2989                 if (use_avx512) {
2990                         if (check_ret == IAVF_VECTOR_PATH) {
2991                                 dev->tx_pkt_burst = iavf_xmit_pkts_vec_avx512;
2992                                 PMD_DRV_LOG(DEBUG, "Using AVX512 Vector Tx (port %d).",
2993                                             dev->data->port_id);
2994                         } else {
2995                                 dev->tx_pkt_burst = iavf_xmit_pkts_vec_avx512_offload;
2996                                 dev->tx_pkt_prepare = iavf_prep_pkts;
2997                                 PMD_DRV_LOG(DEBUG, "Using AVX512 OFFLOAD Vector Tx (port %d).",
2998                                             dev->data->port_id);
2999                         }
3000                 }
3001 #endif
3002
3003                 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3004                         txq = dev->data->tx_queues[i];
3005                         if (!txq)
3006                                 continue;
3007 #ifdef CC_AVX512_SUPPORT
3008                         if (use_avx512)
3009                                 iavf_txq_vec_setup_avx512(txq);
3010                         else
3011                                 iavf_txq_vec_setup(txq);
3012 #else
3013                         iavf_txq_vec_setup(txq);
3014 #endif
3015                 }
3016
3017                 return;
3018         }
3019
3020 normal:
3021 #endif
3022         PMD_DRV_LOG(DEBUG, "Using Basic Tx callback (port=%d).",
3023                     dev->data->port_id);
3024         dev->tx_pkt_burst = iavf_xmit_pkts;
3025         dev->tx_pkt_prepare = iavf_prep_pkts;
3026 }
3027
3028 static int
3029 iavf_tx_done_cleanup_full(struct iavf_tx_queue *txq,
3030                         uint32_t free_cnt)
3031 {
3032         struct iavf_tx_entry *swr_ring = txq->sw_ring;
3033         uint16_t i, tx_last, tx_id;
3034         uint16_t nb_tx_free_last;
3035         uint16_t nb_tx_to_clean;
3036         uint32_t pkt_cnt;
3037
3038         /* Start free mbuf from the next of tx_tail */
3039         tx_last = txq->tx_tail;
3040         tx_id  = swr_ring[tx_last].next_id;
3041
3042         if (txq->nb_free == 0 && iavf_xmit_cleanup(txq))
3043                 return 0;
3044
3045         nb_tx_to_clean = txq->nb_free;
3046         nb_tx_free_last = txq->nb_free;
3047         if (!free_cnt)
3048                 free_cnt = txq->nb_tx_desc;
3049
3050         /* Loop through swr_ring to count the amount of
3051          * freeable mubfs and packets.
3052          */
3053         for (pkt_cnt = 0; pkt_cnt < free_cnt; ) {
3054                 for (i = 0; i < nb_tx_to_clean &&
3055                         pkt_cnt < free_cnt &&
3056                         tx_id != tx_last; i++) {
3057                         if (swr_ring[tx_id].mbuf != NULL) {
3058                                 rte_pktmbuf_free_seg(swr_ring[tx_id].mbuf);
3059                                 swr_ring[tx_id].mbuf = NULL;
3060
3061                                 /*
3062                                  * last segment in the packet,
3063                                  * increment packet count
3064                                  */
3065                                 pkt_cnt += (swr_ring[tx_id].last_id == tx_id);
3066                         }
3067
3068                         tx_id = swr_ring[tx_id].next_id;
3069                 }
3070
3071                 if (txq->rs_thresh > txq->nb_tx_desc -
3072                         txq->nb_free || tx_id == tx_last)
3073                         break;
3074
3075                 if (pkt_cnt < free_cnt) {
3076                         if (iavf_xmit_cleanup(txq))
3077                                 break;
3078
3079                         nb_tx_to_clean = txq->nb_free - nb_tx_free_last;
3080                         nb_tx_free_last = txq->nb_free;
3081                 }
3082         }
3083
3084         return (int)pkt_cnt;
3085 }
3086
3087 int
3088 iavf_dev_tx_done_cleanup(void *txq, uint32_t free_cnt)
3089 {
3090         struct iavf_tx_queue *q = (struct iavf_tx_queue *)txq;
3091
3092         return iavf_tx_done_cleanup_full(q, free_cnt);
3093 }
3094
3095 void
3096 iavf_dev_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
3097                      struct rte_eth_rxq_info *qinfo)
3098 {
3099         struct iavf_rx_queue *rxq;
3100
3101         rxq = dev->data->rx_queues[queue_id];
3102
3103         qinfo->mp = rxq->mp;
3104         qinfo->scattered_rx = dev->data->scattered_rx;
3105         qinfo->nb_desc = rxq->nb_rx_desc;
3106
3107         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
3108         qinfo->conf.rx_drop_en = true;
3109         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
3110 }
3111
3112 void
3113 iavf_dev_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
3114                      struct rte_eth_txq_info *qinfo)
3115 {
3116         struct iavf_tx_queue *txq;
3117
3118         txq = dev->data->tx_queues[queue_id];
3119
3120         qinfo->nb_desc = txq->nb_tx_desc;
3121
3122         qinfo->conf.tx_free_thresh = txq->free_thresh;
3123         qinfo->conf.tx_rs_thresh = txq->rs_thresh;
3124         qinfo->conf.offloads = txq->offloads;
3125         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
3126 }
3127
3128 /* Get the number of used descriptors of a rx queue */
3129 uint32_t
3130 iavf_dev_rxq_count(void *rx_queue)
3131 {
3132 #define IAVF_RXQ_SCAN_INTERVAL 4
3133         volatile union iavf_rx_desc *rxdp;
3134         struct iavf_rx_queue *rxq;
3135         uint16_t desc = 0;
3136
3137         rxq = rx_queue;
3138         rxdp = &rxq->rx_ring[rxq->rx_tail];
3139
3140         while ((desc < rxq->nb_rx_desc) &&
3141                ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
3142                  IAVF_RXD_QW1_STATUS_MASK) >> IAVF_RXD_QW1_STATUS_SHIFT) &
3143                (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)) {
3144                 /* Check the DD bit of a rx descriptor of each 4 in a group,
3145                  * to avoid checking too frequently and downgrading performance
3146                  * too much.
3147                  */
3148                 desc += IAVF_RXQ_SCAN_INTERVAL;
3149                 rxdp += IAVF_RXQ_SCAN_INTERVAL;
3150                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
3151                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
3152                                         desc - rxq->nb_rx_desc]);
3153         }
3154
3155         return desc;
3156 }
3157
3158 int
3159 iavf_dev_rx_desc_status(void *rx_queue, uint16_t offset)
3160 {
3161         struct iavf_rx_queue *rxq = rx_queue;
3162         volatile uint64_t *status;
3163         uint64_t mask;
3164         uint32_t desc;
3165
3166         if (unlikely(offset >= rxq->nb_rx_desc))
3167                 return -EINVAL;
3168
3169         if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
3170                 return RTE_ETH_RX_DESC_UNAVAIL;
3171
3172         desc = rxq->rx_tail + offset;
3173         if (desc >= rxq->nb_rx_desc)
3174                 desc -= rxq->nb_rx_desc;
3175
3176         status = &rxq->rx_ring[desc].wb.qword1.status_error_len;
3177         mask = rte_le_to_cpu_64((1ULL << IAVF_RX_DESC_STATUS_DD_SHIFT)
3178                 << IAVF_RXD_QW1_STATUS_SHIFT);
3179         if (*status & mask)
3180                 return RTE_ETH_RX_DESC_DONE;
3181
3182         return RTE_ETH_RX_DESC_AVAIL;
3183 }
3184
3185 int
3186 iavf_dev_tx_desc_status(void *tx_queue, uint16_t offset)
3187 {
3188         struct iavf_tx_queue *txq = tx_queue;
3189         volatile uint64_t *status;
3190         uint64_t mask, expect;
3191         uint32_t desc;
3192
3193         if (unlikely(offset >= txq->nb_tx_desc))
3194                 return -EINVAL;
3195
3196         desc = txq->tx_tail + offset;
3197         /* go to next desc that has the RS bit */
3198         desc = ((desc + txq->rs_thresh - 1) / txq->rs_thresh) *
3199                 txq->rs_thresh;
3200         if (desc >= txq->nb_tx_desc) {
3201                 desc -= txq->nb_tx_desc;
3202                 if (desc >= txq->nb_tx_desc)
3203                         desc -= txq->nb_tx_desc;
3204         }
3205
3206         status = &txq->tx_ring[desc].cmd_type_offset_bsz;
3207         mask = rte_le_to_cpu_64(IAVF_TXD_QW1_DTYPE_MASK);
3208         expect = rte_cpu_to_le_64(
3209                  IAVF_TX_DESC_DTYPE_DESC_DONE << IAVF_TXD_QW1_DTYPE_SHIFT);
3210         if ((*status & mask) == expect)
3211                 return RTE_ETH_TX_DESC_DONE;
3212
3213         return RTE_ETH_TX_DESC_FULL;
3214 }
3215
3216 static inline uint32_t
3217 iavf_get_default_ptype(uint16_t ptype)
3218 {
3219         static const uint32_t ptype_tbl[IAVF_MAX_PKT_TYPE]
3220                 __rte_cache_aligned = {
3221                 /* L2 types */
3222                 /* [0] reserved */
3223                 [1] = RTE_PTYPE_L2_ETHER,
3224                 [2] = RTE_PTYPE_L2_ETHER_TIMESYNC,
3225                 /* [3] - [5] reserved */
3226                 [6] = RTE_PTYPE_L2_ETHER_LLDP,
3227                 /* [7] - [10] reserved */
3228                 [11] = RTE_PTYPE_L2_ETHER_ARP,
3229                 /* [12] - [21] reserved */
3230
3231                 /* Non tunneled IPv4 */
3232                 [22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3233                        RTE_PTYPE_L4_FRAG,
3234                 [23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3235                        RTE_PTYPE_L4_NONFRAG,
3236                 [24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3237                        RTE_PTYPE_L4_UDP,
3238                 /* [25] reserved */
3239                 [26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3240                        RTE_PTYPE_L4_TCP,
3241                 [27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3242                        RTE_PTYPE_L4_SCTP,
3243                 [28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3244                        RTE_PTYPE_L4_ICMP,
3245
3246                 /* IPv4 --> IPv4 */
3247                 [29] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3248                        RTE_PTYPE_TUNNEL_IP |
3249                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3250                        RTE_PTYPE_INNER_L4_FRAG,
3251                 [30] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3252                        RTE_PTYPE_TUNNEL_IP |
3253                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3254                        RTE_PTYPE_INNER_L4_NONFRAG,
3255                 [31] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3256                        RTE_PTYPE_TUNNEL_IP |
3257                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3258                        RTE_PTYPE_INNER_L4_UDP,
3259                 /* [32] reserved */
3260                 [33] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3261                        RTE_PTYPE_TUNNEL_IP |
3262                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3263                        RTE_PTYPE_INNER_L4_TCP,
3264                 [34] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3265                        RTE_PTYPE_TUNNEL_IP |
3266                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3267                        RTE_PTYPE_INNER_L4_SCTP,
3268                 [35] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3269                        RTE_PTYPE_TUNNEL_IP |
3270                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3271                        RTE_PTYPE_INNER_L4_ICMP,
3272
3273                 /* IPv4 --> IPv6 */
3274                 [36] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3275                        RTE_PTYPE_TUNNEL_IP |
3276                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3277                        RTE_PTYPE_INNER_L4_FRAG,
3278                 [37] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3279                        RTE_PTYPE_TUNNEL_IP |
3280                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3281                        RTE_PTYPE_INNER_L4_NONFRAG,
3282                 [38] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3283                        RTE_PTYPE_TUNNEL_IP |
3284                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3285                        RTE_PTYPE_INNER_L4_UDP,
3286                 /* [39] reserved */
3287                 [40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3288                        RTE_PTYPE_TUNNEL_IP |
3289                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3290                        RTE_PTYPE_INNER_L4_TCP,
3291                 [41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3292                        RTE_PTYPE_TUNNEL_IP |
3293                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3294                        RTE_PTYPE_INNER_L4_SCTP,
3295                 [42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3296                        RTE_PTYPE_TUNNEL_IP |
3297                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3298                        RTE_PTYPE_INNER_L4_ICMP,
3299
3300                 /* IPv4 --> GRE/Teredo/VXLAN */
3301                 [43] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3302                        RTE_PTYPE_TUNNEL_GRENAT,
3303
3304                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv4 */
3305                 [44] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3306                        RTE_PTYPE_TUNNEL_GRENAT |
3307                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3308                        RTE_PTYPE_INNER_L4_FRAG,
3309                 [45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3310                        RTE_PTYPE_TUNNEL_GRENAT |
3311                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3312                        RTE_PTYPE_INNER_L4_NONFRAG,
3313                 [46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3314                        RTE_PTYPE_TUNNEL_GRENAT |
3315                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3316                        RTE_PTYPE_INNER_L4_UDP,
3317                 /* [47] reserved */
3318                 [48] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3319                        RTE_PTYPE_TUNNEL_GRENAT |
3320                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3321                        RTE_PTYPE_INNER_L4_TCP,
3322                 [49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3323                        RTE_PTYPE_TUNNEL_GRENAT |
3324                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3325                        RTE_PTYPE_INNER_L4_SCTP,
3326                 [50] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3327                        RTE_PTYPE_TUNNEL_GRENAT |
3328                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3329                        RTE_PTYPE_INNER_L4_ICMP,
3330
3331                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv6 */
3332                 [51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3333                        RTE_PTYPE_TUNNEL_GRENAT |
3334                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3335                        RTE_PTYPE_INNER_L4_FRAG,
3336                 [52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3337                        RTE_PTYPE_TUNNEL_GRENAT |
3338                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3339                        RTE_PTYPE_INNER_L4_NONFRAG,
3340                 [53] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3341                        RTE_PTYPE_TUNNEL_GRENAT |
3342                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3343                        RTE_PTYPE_INNER_L4_UDP,
3344                 /* [54] reserved */
3345                 [55] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3346                        RTE_PTYPE_TUNNEL_GRENAT |
3347                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3348                        RTE_PTYPE_INNER_L4_TCP,
3349                 [56] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3350                        RTE_PTYPE_TUNNEL_GRENAT |
3351                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3352                        RTE_PTYPE_INNER_L4_SCTP,
3353                 [57] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3354                        RTE_PTYPE_TUNNEL_GRENAT |
3355                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3356                        RTE_PTYPE_INNER_L4_ICMP,
3357
3358                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC */
3359                 [58] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3360                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
3361
3362                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
3363                 [59] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3364                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3365                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3366                        RTE_PTYPE_INNER_L4_FRAG,
3367                 [60] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3368                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3369                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3370                        RTE_PTYPE_INNER_L4_NONFRAG,
3371                 [61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3372                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3373                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3374                        RTE_PTYPE_INNER_L4_UDP,
3375                 /* [62] reserved */
3376                 [63] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3377                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3378                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3379                        RTE_PTYPE_INNER_L4_TCP,
3380                 [64] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3381                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3382                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3383                        RTE_PTYPE_INNER_L4_SCTP,
3384                 [65] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3385                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3386                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3387                        RTE_PTYPE_INNER_L4_ICMP,
3388
3389                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
3390                 [66] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3391                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3392                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3393                        RTE_PTYPE_INNER_L4_FRAG,
3394                 [67] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3395                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3396                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3397                        RTE_PTYPE_INNER_L4_NONFRAG,
3398                 [68] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3399                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3400                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3401                        RTE_PTYPE_INNER_L4_UDP,
3402                 /* [69] reserved */
3403                 [70] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3404                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3405                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3406                        RTE_PTYPE_INNER_L4_TCP,
3407                 [71] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3408                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3409                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3410                        RTE_PTYPE_INNER_L4_SCTP,
3411                 [72] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3412                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3413                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3414                        RTE_PTYPE_INNER_L4_ICMP,
3415                 /* [73] - [87] reserved */
3416
3417                 /* Non tunneled IPv6 */
3418                 [88] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3419                        RTE_PTYPE_L4_FRAG,
3420                 [89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3421                        RTE_PTYPE_L4_NONFRAG,
3422                 [90] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3423                        RTE_PTYPE_L4_UDP,
3424                 /* [91] reserved */
3425                 [92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3426                        RTE_PTYPE_L4_TCP,
3427                 [93] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3428                        RTE_PTYPE_L4_SCTP,
3429                 [94] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3430                        RTE_PTYPE_L4_ICMP,
3431
3432                 /* IPv6 --> IPv4 */
3433                 [95] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3434                        RTE_PTYPE_TUNNEL_IP |
3435                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3436                        RTE_PTYPE_INNER_L4_FRAG,
3437                 [96] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3438                        RTE_PTYPE_TUNNEL_IP |
3439                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3440                        RTE_PTYPE_INNER_L4_NONFRAG,
3441                 [97] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3442                        RTE_PTYPE_TUNNEL_IP |
3443                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3444                        RTE_PTYPE_INNER_L4_UDP,
3445                 /* [98] reserved */
3446                 [99] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3447                        RTE_PTYPE_TUNNEL_IP |
3448                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3449                        RTE_PTYPE_INNER_L4_TCP,
3450                 [100] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3451                         RTE_PTYPE_TUNNEL_IP |
3452                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3453                         RTE_PTYPE_INNER_L4_SCTP,
3454                 [101] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3455                         RTE_PTYPE_TUNNEL_IP |
3456                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3457                         RTE_PTYPE_INNER_L4_ICMP,
3458
3459                 /* IPv6 --> IPv6 */
3460                 [102] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3461                         RTE_PTYPE_TUNNEL_IP |
3462                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3463                         RTE_PTYPE_INNER_L4_FRAG,
3464                 [103] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3465                         RTE_PTYPE_TUNNEL_IP |
3466                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3467                         RTE_PTYPE_INNER_L4_NONFRAG,
3468                 [104] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3469                         RTE_PTYPE_TUNNEL_IP |
3470                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3471                         RTE_PTYPE_INNER_L4_UDP,
3472                 /* [105] reserved */
3473                 [106] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3474                         RTE_PTYPE_TUNNEL_IP |
3475                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3476                         RTE_PTYPE_INNER_L4_TCP,
3477                 [107] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3478                         RTE_PTYPE_TUNNEL_IP |
3479                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3480                         RTE_PTYPE_INNER_L4_SCTP,
3481                 [108] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3482                         RTE_PTYPE_TUNNEL_IP |
3483                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3484                         RTE_PTYPE_INNER_L4_ICMP,
3485
3486                 /* IPv6 --> GRE/Teredo/VXLAN */
3487                 [109] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3488                         RTE_PTYPE_TUNNEL_GRENAT,
3489
3490                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv4 */
3491                 [110] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3492                         RTE_PTYPE_TUNNEL_GRENAT |
3493                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3494                         RTE_PTYPE_INNER_L4_FRAG,
3495                 [111] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3496                         RTE_PTYPE_TUNNEL_GRENAT |
3497                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3498                         RTE_PTYPE_INNER_L4_NONFRAG,
3499                 [112] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3500                         RTE_PTYPE_TUNNEL_GRENAT |
3501                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3502                         RTE_PTYPE_INNER_L4_UDP,
3503                 /* [113] reserved */
3504                 [114] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3505                         RTE_PTYPE_TUNNEL_GRENAT |
3506                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3507                         RTE_PTYPE_INNER_L4_TCP,
3508                 [115] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3509                         RTE_PTYPE_TUNNEL_GRENAT |
3510                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3511                         RTE_PTYPE_INNER_L4_SCTP,
3512                 [116] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3513                         RTE_PTYPE_TUNNEL_GRENAT |
3514                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3515                         RTE_PTYPE_INNER_L4_ICMP,
3516
3517                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv6 */
3518                 [117] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3519                         RTE_PTYPE_TUNNEL_GRENAT |
3520                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3521                         RTE_PTYPE_INNER_L4_FRAG,
3522                 [118] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3523                         RTE_PTYPE_TUNNEL_GRENAT |
3524                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3525                         RTE_PTYPE_INNER_L4_NONFRAG,
3526                 [119] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3527                         RTE_PTYPE_TUNNEL_GRENAT |
3528                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3529                         RTE_PTYPE_INNER_L4_UDP,
3530                 /* [120] reserved */
3531                 [121] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3532                         RTE_PTYPE_TUNNEL_GRENAT |
3533                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3534                         RTE_PTYPE_INNER_L4_TCP,
3535                 [122] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3536                         RTE_PTYPE_TUNNEL_GRENAT |
3537                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3538                         RTE_PTYPE_INNER_L4_SCTP,
3539                 [123] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3540                         RTE_PTYPE_TUNNEL_GRENAT |
3541                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3542                         RTE_PTYPE_INNER_L4_ICMP,
3543
3544                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC */
3545                 [124] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3546                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
3547
3548                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
3549                 [125] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3550                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3551                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3552                         RTE_PTYPE_INNER_L4_FRAG,
3553                 [126] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3554                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3555                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3556                         RTE_PTYPE_INNER_L4_NONFRAG,
3557                 [127] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3558                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3559                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3560                         RTE_PTYPE_INNER_L4_UDP,
3561                 /* [128] reserved */
3562                 [129] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3563                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3564                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3565                         RTE_PTYPE_INNER_L4_TCP,
3566                 [130] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3567                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3568                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3569                         RTE_PTYPE_INNER_L4_SCTP,
3570                 [131] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3571                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3572                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3573                         RTE_PTYPE_INNER_L4_ICMP,
3574
3575                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
3576                 [132] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3577                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3578                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3579                         RTE_PTYPE_INNER_L4_FRAG,
3580                 [133] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3581                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3582                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3583                         RTE_PTYPE_INNER_L4_NONFRAG,
3584                 [134] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3585                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3586                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3587                         RTE_PTYPE_INNER_L4_UDP,
3588                 /* [135] reserved */
3589                 [136] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3590                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3591                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3592                         RTE_PTYPE_INNER_L4_TCP,
3593                 [137] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3594                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3595                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3596                         RTE_PTYPE_INNER_L4_SCTP,
3597                 [138] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3598                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3599                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3600                         RTE_PTYPE_INNER_L4_ICMP,
3601                 /* [139] - [299] reserved */
3602
3603                 /* PPPoE */
3604                 [300] = RTE_PTYPE_L2_ETHER_PPPOE,
3605                 [301] = RTE_PTYPE_L2_ETHER_PPPOE,
3606
3607                 /* PPPoE --> IPv4 */
3608                 [302] = RTE_PTYPE_L2_ETHER_PPPOE |
3609                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3610                         RTE_PTYPE_L4_FRAG,
3611                 [303] = RTE_PTYPE_L2_ETHER_PPPOE |
3612                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3613                         RTE_PTYPE_L4_NONFRAG,
3614                 [304] = RTE_PTYPE_L2_ETHER_PPPOE |
3615                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3616                         RTE_PTYPE_L4_UDP,
3617                 [305] = RTE_PTYPE_L2_ETHER_PPPOE |
3618                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3619                         RTE_PTYPE_L4_TCP,
3620                 [306] = RTE_PTYPE_L2_ETHER_PPPOE |
3621                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3622                         RTE_PTYPE_L4_SCTP,
3623                 [307] = RTE_PTYPE_L2_ETHER_PPPOE |
3624                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3625                         RTE_PTYPE_L4_ICMP,
3626
3627                 /* PPPoE --> IPv6 */
3628                 [308] = RTE_PTYPE_L2_ETHER_PPPOE |
3629                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3630                         RTE_PTYPE_L4_FRAG,
3631                 [309] = RTE_PTYPE_L2_ETHER_PPPOE |
3632                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3633                         RTE_PTYPE_L4_NONFRAG,
3634                 [310] = RTE_PTYPE_L2_ETHER_PPPOE |
3635                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3636                         RTE_PTYPE_L4_UDP,
3637                 [311] = RTE_PTYPE_L2_ETHER_PPPOE |
3638                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3639                         RTE_PTYPE_L4_TCP,
3640                 [312] = RTE_PTYPE_L2_ETHER_PPPOE |
3641                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3642                         RTE_PTYPE_L4_SCTP,
3643                 [313] = RTE_PTYPE_L2_ETHER_PPPOE |
3644                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3645                         RTE_PTYPE_L4_ICMP,
3646                 /* [314] - [324] reserved */
3647
3648                 /* IPv4/IPv6 --> GTPC/GTPU */
3649                 [325] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3650                         RTE_PTYPE_TUNNEL_GTPC,
3651                 [326] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3652                         RTE_PTYPE_TUNNEL_GTPC,
3653                 [327] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3654                         RTE_PTYPE_TUNNEL_GTPC,
3655                 [328] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3656                         RTE_PTYPE_TUNNEL_GTPC,
3657                 [329] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3658                         RTE_PTYPE_TUNNEL_GTPU,
3659                 [330] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3660                         RTE_PTYPE_TUNNEL_GTPU,
3661
3662                 /* IPv4 --> GTPU --> IPv4 */
3663                 [331] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3664                         RTE_PTYPE_TUNNEL_GTPU |
3665                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3666                         RTE_PTYPE_INNER_L4_FRAG,
3667                 [332] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3668                         RTE_PTYPE_TUNNEL_GTPU |
3669                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3670                         RTE_PTYPE_INNER_L4_NONFRAG,
3671                 [333] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3672                         RTE_PTYPE_TUNNEL_GTPU |
3673                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3674                         RTE_PTYPE_INNER_L4_UDP,
3675                 [334] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3676                         RTE_PTYPE_TUNNEL_GTPU |
3677                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3678                         RTE_PTYPE_INNER_L4_TCP,
3679                 [335] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3680                         RTE_PTYPE_TUNNEL_GTPU |
3681                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3682                         RTE_PTYPE_INNER_L4_ICMP,
3683
3684                 /* IPv6 --> GTPU --> IPv4 */
3685                 [336] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3686                         RTE_PTYPE_TUNNEL_GTPU |
3687                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3688                         RTE_PTYPE_INNER_L4_FRAG,
3689                 [337] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3690                         RTE_PTYPE_TUNNEL_GTPU |
3691                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3692                         RTE_PTYPE_INNER_L4_NONFRAG,
3693                 [338] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3694                         RTE_PTYPE_TUNNEL_GTPU |
3695                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3696                         RTE_PTYPE_INNER_L4_UDP,
3697                 [339] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3698                         RTE_PTYPE_TUNNEL_GTPU |
3699                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3700                         RTE_PTYPE_INNER_L4_TCP,
3701                 [340] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3702                         RTE_PTYPE_TUNNEL_GTPU |
3703                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3704                         RTE_PTYPE_INNER_L4_ICMP,
3705
3706                 /* IPv4 --> GTPU --> IPv6 */
3707                 [341] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3708                         RTE_PTYPE_TUNNEL_GTPU |
3709                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3710                         RTE_PTYPE_INNER_L4_FRAG,
3711                 [342] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3712                         RTE_PTYPE_TUNNEL_GTPU |
3713                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3714                         RTE_PTYPE_INNER_L4_NONFRAG,
3715                 [343] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3716                         RTE_PTYPE_TUNNEL_GTPU |
3717                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3718                         RTE_PTYPE_INNER_L4_UDP,
3719                 [344] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3720                         RTE_PTYPE_TUNNEL_GTPU |
3721                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3722                         RTE_PTYPE_INNER_L4_TCP,
3723                 [345] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3724                         RTE_PTYPE_TUNNEL_GTPU |
3725                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3726                         RTE_PTYPE_INNER_L4_ICMP,
3727
3728                 /* IPv6 --> GTPU --> IPv6 */
3729                 [346] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3730                         RTE_PTYPE_TUNNEL_GTPU |
3731                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3732                         RTE_PTYPE_INNER_L4_FRAG,
3733                 [347] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3734                         RTE_PTYPE_TUNNEL_GTPU |
3735                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3736                         RTE_PTYPE_INNER_L4_NONFRAG,
3737                 [348] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3738                         RTE_PTYPE_TUNNEL_GTPU |
3739                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3740                         RTE_PTYPE_INNER_L4_UDP,
3741                 [349] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3742                         RTE_PTYPE_TUNNEL_GTPU |
3743                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3744                         RTE_PTYPE_INNER_L4_TCP,
3745                 [350] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3746                         RTE_PTYPE_TUNNEL_GTPU |
3747                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3748                         RTE_PTYPE_INNER_L4_ICMP,
3749
3750                 /* IPv4 --> UDP ECPRI */
3751                 [372] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3752                         RTE_PTYPE_L4_UDP,
3753                 [373] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3754                         RTE_PTYPE_L4_UDP,
3755                 [374] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3756                         RTE_PTYPE_L4_UDP,
3757                 [375] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3758                         RTE_PTYPE_L4_UDP,
3759                 [376] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3760                         RTE_PTYPE_L4_UDP,
3761                 [377] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3762                         RTE_PTYPE_L4_UDP,
3763                 [378] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3764                         RTE_PTYPE_L4_UDP,
3765                 [379] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3766                         RTE_PTYPE_L4_UDP,
3767                 [380] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3768                         RTE_PTYPE_L4_UDP,
3769                 [381] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3770                         RTE_PTYPE_L4_UDP,
3771
3772                 /* IPV6 --> UDP ECPRI */
3773                 [382] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3774                         RTE_PTYPE_L4_UDP,
3775                 [383] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3776                         RTE_PTYPE_L4_UDP,
3777                 [384] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3778                         RTE_PTYPE_L4_UDP,
3779                 [385] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3780                         RTE_PTYPE_L4_UDP,
3781                 [386] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3782                         RTE_PTYPE_L4_UDP,
3783                 [387] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3784                         RTE_PTYPE_L4_UDP,
3785                 [388] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3786                         RTE_PTYPE_L4_UDP,
3787                 [389] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3788                         RTE_PTYPE_L4_UDP,
3789                 [390] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3790                         RTE_PTYPE_L4_UDP,
3791                 [391] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3792                         RTE_PTYPE_L4_UDP,
3793                 /* All others reserved */
3794         };
3795
3796         return ptype_tbl[ptype];
3797 }
3798
3799 void __rte_cold
3800 iavf_set_default_ptype_table(struct rte_eth_dev *dev)
3801 {
3802         struct iavf_adapter *ad =
3803                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3804         int i;
3805
3806         for (i = 0; i < IAVF_MAX_PKT_TYPE; i++)
3807                 ad->ptype_tbl[i] = iavf_get_default_ptype(i);
3808 }