drivers/net/iavf/iavf_rxtx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2017 Intel Corporation
   3  */
   4
   5 #include <stdio.h>
   6 #include <stdlib.h>
   7 #include <string.h>
   8 #include <errno.h>
   9 #include <stdint.h>
  10 #include <stdarg.h>
  11 #include <unistd.h>
  12 #include <inttypes.h>
  13 #include <sys/queue.h>
  14
  15 #include <rte_string_fns.h>
  16 #include <rte_memzone.h>
  17 #include <rte_mbuf.h>
  18 #include <rte_malloc.h>
  19 #include <rte_ether.h>
  20 #include <ethdev_driver.h>
  21 #include <rte_tcp.h>
  22 #include <rte_sctp.h>
  23 #include <rte_udp.h>
  24 #include <rte_ip.h>
  25 #include <rte_net.h>
  26 #include <rte_vect.h>
  27
  28 #include "iavf.h"
  29 #include "iavf_rxtx.h"
  30 #include "iavf_ipsec_crypto.h"
  31 #include "rte_pmd_iavf.h"
  32
  33 /* Offset of mbuf dynamic field for protocol extraction's metadata */
  34 int rte_pmd_ifd_dynfield_proto_xtr_metadata_offs = -1;
  35
  36 /* Mask of mbuf dynamic flags for protocol extraction's type */
  37 uint64_t rte_pmd_ifd_dynflag_proto_xtr_vlan_mask;
  38 uint64_t rte_pmd_ifd_dynflag_proto_xtr_ipv4_mask;
  39 uint64_t rte_pmd_ifd_dynflag_proto_xtr_ipv6_mask;
  40 uint64_t rte_pmd_ifd_dynflag_proto_xtr_ipv6_flow_mask;
  41 uint64_t rte_pmd_ifd_dynflag_proto_xtr_tcp_mask;
  42 uint64_t rte_pmd_ifd_dynflag_proto_xtr_ip_offset_mask;
  43 uint64_t rte_pmd_ifd_dynflag_proto_xtr_ipsec_crypto_said_mask;
  44
  45 uint8_t
  46 iavf_proto_xtr_type_to_rxdid(uint8_t flex_type)
  47 {
  48         static uint8_t rxdid_map[] = {
  49                 [IAVF_PROTO_XTR_NONE]      = IAVF_RXDID_COMMS_OVS_1,
  50                 [IAVF_PROTO_XTR_VLAN]      = IAVF_RXDID_COMMS_AUX_VLAN,
  51                 [IAVF_PROTO_XTR_IPV4]      = IAVF_RXDID_COMMS_AUX_IPV4,
  52                 [IAVF_PROTO_XTR_IPV6]      = IAVF_RXDID_COMMS_AUX_IPV6,
  53                 [IAVF_PROTO_XTR_IPV6_FLOW] = IAVF_RXDID_COMMS_AUX_IPV6_FLOW,
  54                 [IAVF_PROTO_XTR_TCP]       = IAVF_RXDID_COMMS_AUX_TCP,
  55                 [IAVF_PROTO_XTR_IP_OFFSET] = IAVF_RXDID_COMMS_AUX_IP_OFFSET,
  56                 [IAVF_PROTO_XTR_IPSEC_CRYPTO_SAID] =
  57                                 IAVF_RXDID_COMMS_IPSEC_CRYPTO,
  58         };
  59
  60         return flex_type < RTE_DIM(rxdid_map) ?
  61                                 rxdid_map[flex_type] : IAVF_RXDID_COMMS_OVS_1;
  62 }
  63
  64 static int
  65 iavf_monitor_callback(const uint64_t value,
  66                 const uint64_t arg[RTE_POWER_MONITOR_OPAQUE_SZ] __rte_unused)
  67 {
  68         const uint64_t m = rte_cpu_to_le_64(1 << IAVF_RX_DESC_STATUS_DD_SHIFT);
  69         /*
  70          * we expect the DD bit to be set to 1 if this descriptor was already
  71          * written to.
  72          */
  73         return (value & m) == m ? -1 : 0;
  74 }
  75
  76 int
  77 iavf_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc)
  78 {
  79         struct iavf_rx_queue *rxq = rx_queue;
  80         volatile union iavf_rx_desc *rxdp;
  81         uint16_t desc;
  82
  83         desc = rxq->rx_tail;
  84         rxdp = &rxq->rx_ring[desc];
  85         /* watch for changes in status bit */
  86         pmc->addr = &rxdp->wb.qword1.status_error_len;
  87
  88         /* comparison callback */
  89         pmc->fn = iavf_monitor_callback;
  90
  91         /* registers are 64-bit */
  92         pmc->size = sizeof(uint64_t);
  93
  94         return 0;
  95 }
  96
  97 static inline int
  98 check_rx_thresh(uint16_t nb_desc, uint16_t thresh)
  99 {
 100         /* The following constraints must be satisfied:
 101          *   thresh < rxq->nb_rx_desc
 102          */
 103         if (thresh >= nb_desc) {
 104                 PMD_INIT_LOG(ERR, "rx_free_thresh (%u) must be less than %u",
 105                              thresh, nb_desc);
 106                 return -EINVAL;
 107         }
 108         return 0;
 109 }
 110
 111 static inline int
 112 check_tx_thresh(uint16_t nb_desc, uint16_t tx_rs_thresh,
 113                 uint16_t tx_free_thresh)
 114 {
 115         /* TX descriptors will have their RS bit set after tx_rs_thresh
 116          * descriptors have been used. The TX descriptor ring will be cleaned
 117          * after tx_free_thresh descriptors are used or if the number of
 118          * descriptors required to transmit a packet is greater than the
 119          * number of free TX descriptors.
 120          *
 121          * The following constraints must be satisfied:
 122          *  - tx_rs_thresh must be less than the size of the ring minus 2.
 123          *  - tx_free_thresh must be less than the size of the ring minus 3.
 124          *  - tx_rs_thresh must be less than or equal to tx_free_thresh.
 125          *  - tx_rs_thresh must be a divisor of the ring size.
 126          *
 127          * One descriptor in the TX ring is used as a sentinel to avoid a H/W
 128          * race condition, hence the maximum threshold constraints. When set
 129          * to zero use default values.
 130          */
 131         if (tx_rs_thresh >= (nb_desc - 2)) {
 132                 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be less than the "
 133                              "number of TX descriptors (%u) minus 2",
 134                              tx_rs_thresh, nb_desc);
 135                 return -EINVAL;
 136         }
 137         if (tx_free_thresh >= (nb_desc - 3)) {
 138                 PMD_INIT_LOG(ERR, "tx_free_thresh (%u) must be less than the "
 139                              "number of TX descriptors (%u) minus 3.",
 140                              tx_free_thresh, nb_desc);
 141                 return -EINVAL;
 142         }
 143         if (tx_rs_thresh > tx_free_thresh) {
 144                 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be less than or "
 145                              "equal to tx_free_thresh (%u).",
 146                              tx_rs_thresh, tx_free_thresh);
 147                 return -EINVAL;
 148         }
 149         if ((nb_desc % tx_rs_thresh) != 0) {
 150                 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be a divisor of the "
 151                              "number of TX descriptors (%u).",
 152                              tx_rs_thresh, nb_desc);
 153                 return -EINVAL;
 154         }
 155
 156         return 0;
 157 }
 158
 159 static inline bool
 160 check_rx_vec_allow(struct iavf_rx_queue *rxq)
 161 {
 162         if (rxq->rx_free_thresh >= IAVF_VPMD_RX_MAX_BURST &&
 163             rxq->nb_rx_desc % rxq->rx_free_thresh == 0) {
 164                 PMD_INIT_LOG(DEBUG, "Vector Rx can be enabled on this rxq.");
 165                 return true;
 166         }
 167
 168         PMD_INIT_LOG(DEBUG, "Vector Rx cannot be enabled on this rxq.");
 169         return false;
 170 }
 171
 172 static inline bool
 173 check_tx_vec_allow(struct iavf_tx_queue *txq)
 174 {
 175         if (!(txq->offloads & IAVF_TX_NO_VECTOR_FLAGS) &&
 176             txq->rs_thresh >= IAVF_VPMD_TX_MAX_BURST &&
 177             txq->rs_thresh <= IAVF_VPMD_TX_MAX_FREE_BUF) {
 178                 PMD_INIT_LOG(DEBUG, "Vector tx can be enabled on this txq.");
 179                 return true;
 180         }
 181         PMD_INIT_LOG(DEBUG, "Vector Tx cannot be enabled on this txq.");
 182         return false;
 183 }
 184
 185 static inline bool
 186 check_rx_bulk_allow(struct iavf_rx_queue *rxq)
 187 {
 188         int ret = true;
 189
 190         if (!(rxq->rx_free_thresh >= IAVF_RX_MAX_BURST)) {
 191                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 192                              "rxq->rx_free_thresh=%d, "
 193                              "IAVF_RX_MAX_BURST=%d",
 194                              rxq->rx_free_thresh, IAVF_RX_MAX_BURST);
 195                 ret = false;
 196         } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
 197                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 198                              "rxq->nb_rx_desc=%d, "
 199                              "rxq->rx_free_thresh=%d",
 200                              rxq->nb_rx_desc, rxq->rx_free_thresh);
 201                 ret = false;
 202         }
 203         return ret;
 204 }
 205
 206 static inline void
 207 reset_rx_queue(struct iavf_rx_queue *rxq)
 208 {
 209         uint16_t len;
 210         uint32_t i;
 211
 212         if (!rxq)
 213                 return;
 214
 215         len = rxq->nb_rx_desc + IAVF_RX_MAX_BURST;
 216
 217         for (i = 0; i < len * sizeof(union iavf_rx_desc); i++)
 218                 ((volatile char *)rxq->rx_ring)[i] = 0;
 219
 220         memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
 221
 222         for (i = 0; i < IAVF_RX_MAX_BURST; i++)
 223                 rxq->sw_ring[rxq->nb_rx_desc + i] = &rxq->fake_mbuf;
 224
 225         /* for rx bulk */
 226         rxq->rx_nb_avail = 0;
 227         rxq->rx_next_avail = 0;
 228         rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
 229
 230         rxq->rx_tail = 0;
 231         rxq->nb_rx_hold = 0;
 232
 233         rte_pktmbuf_free(rxq->pkt_first_seg);
 234
 235         rxq->pkt_first_seg = NULL;
 236         rxq->pkt_last_seg = NULL;
 237         rxq->rxrearm_nb = 0;
 238         rxq->rxrearm_start = 0;
 239 }
 240
 241 static inline void
 242 reset_tx_queue(struct iavf_tx_queue *txq)
 243 {
 244         struct iavf_tx_entry *txe;
 245         uint32_t i, size;
 246         uint16_t prev;
 247
 248         if (!txq) {
 249                 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
 250                 return;
 251         }
 252
 253         txe = txq->sw_ring;
 254         size = sizeof(struct iavf_tx_desc) * txq->nb_tx_desc;
 255         for (i = 0; i < size; i++)
 256                 ((volatile char *)txq->tx_ring)[i] = 0;
 257
 258         prev = (uint16_t)(txq->nb_tx_desc - 1);
 259         for (i = 0; i < txq->nb_tx_desc; i++) {
 260                 txq->tx_ring[i].cmd_type_offset_bsz =
 261                         rte_cpu_to_le_64(IAVF_TX_DESC_DTYPE_DESC_DONE);
 262                 txe[i].mbuf =  NULL;
 263                 txe[i].last_id = i;
 264                 txe[prev].next_id = i;
 265                 prev = i;
 266         }
 267
 268         txq->tx_tail = 0;
 269         txq->nb_used = 0;
 270
 271         txq->last_desc_cleaned = txq->nb_tx_desc - 1;
 272         txq->nb_free = txq->nb_tx_desc - 1;
 273
 274         txq->next_dd = txq->rs_thresh - 1;
 275         txq->next_rs = txq->rs_thresh - 1;
 276 }
 277
 278 static int
 279 alloc_rxq_mbufs(struct iavf_rx_queue *rxq)
 280 {
 281         volatile union iavf_rx_desc *rxd;
 282         struct rte_mbuf *mbuf = NULL;
 283         uint64_t dma_addr;
 284         uint16_t i, j;
 285
 286         for (i = 0; i < rxq->nb_rx_desc; i++) {
 287                 mbuf = rte_mbuf_raw_alloc(rxq->mp);
 288                 if (unlikely(!mbuf)) {
 289                         for (j = 0; j < i; j++) {
 290                                 rte_pktmbuf_free_seg(rxq->sw_ring[j]);
 291                                 rxq->sw_ring[j] = NULL;
 292                         }
 293                         PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
 294                         return -ENOMEM;
 295                 }
 296
 297                 rte_mbuf_refcnt_set(mbuf, 1);
 298                 mbuf->next = NULL;
 299                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
 300                 mbuf->nb_segs = 1;
 301                 mbuf->port = rxq->port_id;
 302
 303                 dma_addr =
 304                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
 305
 306                 rxd = &rxq->rx_ring[i];
 307                 rxd->read.pkt_addr = dma_addr;
 308                 rxd->read.hdr_addr = 0;
 309 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
 310                 rxd->read.rsvd1 = 0;
 311                 rxd->read.rsvd2 = 0;
 312 #endif
 313
 314                 rxq->sw_ring[i] = mbuf;
 315         }
 316
 317         return 0;
 318 }
 319
 320 static inline void
 321 release_rxq_mbufs(struct iavf_rx_queue *rxq)
 322 {
 323         uint16_t i;
 324
 325         if (!rxq->sw_ring)
 326                 return;
 327
 328         for (i = 0; i < rxq->nb_rx_desc; i++) {
 329                 if (rxq->sw_ring[i]) {
 330                         rte_pktmbuf_free_seg(rxq->sw_ring[i]);
 331                         rxq->sw_ring[i] = NULL;
 332                 }
 333         }
 334
 335         /* for rx bulk */
 336         if (rxq->rx_nb_avail == 0)
 337                 return;
 338         for (i = 0; i < rxq->rx_nb_avail; i++) {
 339                 struct rte_mbuf *mbuf;
 340
 341                 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
 342                 rte_pktmbuf_free_seg(mbuf);
 343         }
 344         rxq->rx_nb_avail = 0;
 345 }
 346
 347 static inline void
 348 release_txq_mbufs(struct iavf_tx_queue *txq)
 349 {
 350         uint16_t i;
 351
 352         if (!txq || !txq->sw_ring) {
 353                 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
 354                 return;
 355         }
 356
 357         for (i = 0; i < txq->nb_tx_desc; i++) {
 358                 if (txq->sw_ring[i].mbuf) {
 359                         rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
 360                         txq->sw_ring[i].mbuf = NULL;
 361                 }
 362         }
 363 }
 364
 365 static const struct iavf_rxq_ops def_rxq_ops = {
 366         .release_mbufs = release_rxq_mbufs,
 367 };
 368
 369 static const struct iavf_txq_ops def_txq_ops = {
 370         .release_mbufs = release_txq_mbufs,
 371 };
 372
 373 static inline void
 374 iavf_rxd_to_pkt_fields_by_comms_ovs(__rte_unused struct iavf_rx_queue *rxq,
 375                                     struct rte_mbuf *mb,
 376                                     volatile union iavf_rx_flex_desc *rxdp)
 377 {
 378         volatile struct iavf_32b_rx_flex_desc_comms_ovs *desc =
 379                         (volatile struct iavf_32b_rx_flex_desc_comms_ovs *)rxdp;
 380 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
 381         uint16_t stat_err;
 382 #endif
 383
 384         if (desc->flow_id != 0xFFFFFFFF) {
 385                 mb->ol_flags |= RTE_MBUF_F_RX_FDIR | RTE_MBUF_F_RX_FDIR_ID;
 386                 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
 387         }
 388
 389 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
 390         stat_err = rte_le_to_cpu_16(desc->status_error0);
 391         if (likely(stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
 392                 mb->ol_flags |= RTE_MBUF_F_RX_RSS_HASH;
 393                 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
 394         }
 395 #endif
 396 }
 397
 398 static inline void
 399 iavf_rxd_to_pkt_fields_by_comms_aux_v1(struct iavf_rx_queue *rxq,
 400                                        struct rte_mbuf *mb,
 401                                        volatile union iavf_rx_flex_desc *rxdp)
 402 {
 403         volatile struct iavf_32b_rx_flex_desc_comms *desc =
 404                         (volatile struct iavf_32b_rx_flex_desc_comms *)rxdp;
 405         uint16_t stat_err;
 406
 407         stat_err = rte_le_to_cpu_16(desc->status_error0);
 408         if (likely(stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
 409                 mb->ol_flags |= RTE_MBUF_F_RX_RSS_HASH;
 410                 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
 411         }
 412
 413 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
 414         if (desc->flow_id != 0xFFFFFFFF) {
 415                 mb->ol_flags |= RTE_MBUF_F_RX_FDIR | RTE_MBUF_F_RX_FDIR_ID;
 416                 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
 417         }
 418
 419         if (rxq->xtr_ol_flag) {
 420                 uint32_t metadata = 0;
 421
 422                 stat_err = rte_le_to_cpu_16(desc->status_error1);
 423
 424                 if (stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS1_XTRMD4_VALID_S))
 425                         metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux0);
 426
 427                 if (stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS1_XTRMD5_VALID_S))
 428                         metadata |=
 429                                 rte_le_to_cpu_16(desc->flex_ts.flex.aux1) << 16;
 430
 431                 if (metadata) {
 432                         mb->ol_flags |= rxq->xtr_ol_flag;
 433
 434                         *RTE_PMD_IFD_DYNF_PROTO_XTR_METADATA(mb) = metadata;
 435                 }
 436         }
 437 #endif
 438 }
 439
 440 static inline void
 441 iavf_rxd_to_pkt_fields_by_comms_aux_v2(struct iavf_rx_queue *rxq,
 442                                        struct rte_mbuf *mb,
 443                                        volatile union iavf_rx_flex_desc *rxdp)
 444 {
 445         volatile struct iavf_32b_rx_flex_desc_comms *desc =
 446                         (volatile struct iavf_32b_rx_flex_desc_comms *)rxdp;
 447         uint16_t stat_err;
 448
 449         stat_err = rte_le_to_cpu_16(desc->status_error0);
 450         if (likely(stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
 451                 mb->ol_flags |= RTE_MBUF_F_RX_RSS_HASH;
 452                 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
 453         }
 454
 455 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
 456         if (desc->flow_id != 0xFFFFFFFF) {
 457                 mb->ol_flags |= RTE_MBUF_F_RX_FDIR | RTE_MBUF_F_RX_FDIR_ID;
 458                 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
 459         }
 460
 461         if (rxq->xtr_ol_flag) {
 462                 uint32_t metadata = 0;
 463
 464                 if (desc->flex_ts.flex.aux0 != 0xFFFF)
 465                         metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux0);
 466                 else if (desc->flex_ts.flex.aux1 != 0xFFFF)
 467                         metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux1);
 468
 469                 if (metadata) {
 470                         mb->ol_flags |= rxq->xtr_ol_flag;
 471
 472                         *RTE_PMD_IFD_DYNF_PROTO_XTR_METADATA(mb) = metadata;
 473                 }
 474         }
 475 #endif
 476 }
 477
 478 static const
 479 iavf_rxd_to_pkt_fields_t rxd_to_pkt_fields_ops[IAVF_RXDID_LAST + 1] = {
 480         [IAVF_RXDID_COMMS_AUX_VLAN] = iavf_rxd_to_pkt_fields_by_comms_aux_v1,
 481         [IAVF_RXDID_COMMS_AUX_IPV4] = iavf_rxd_to_pkt_fields_by_comms_aux_v1,
 482         [IAVF_RXDID_COMMS_AUX_IPV6] = iavf_rxd_to_pkt_fields_by_comms_aux_v1,
 483         [IAVF_RXDID_COMMS_AUX_IPV6_FLOW] =
 484                 iavf_rxd_to_pkt_fields_by_comms_aux_v1,
 485         [IAVF_RXDID_COMMS_AUX_TCP] = iavf_rxd_to_pkt_fields_by_comms_aux_v1,
 486         [IAVF_RXDID_COMMS_AUX_IP_OFFSET] =
 487                 iavf_rxd_to_pkt_fields_by_comms_aux_v2,
 488         [IAVF_RXDID_COMMS_IPSEC_CRYPTO] =
 489                 iavf_rxd_to_pkt_fields_by_comms_aux_v2,
 490         [IAVF_RXDID_COMMS_OVS_1] = iavf_rxd_to_pkt_fields_by_comms_ovs,
 491 };
 492
 493 static void
 494 iavf_select_rxd_to_pkt_fields_handler(struct iavf_rx_queue *rxq, uint32_t rxdid)
 495 {
 496         rxq->rxdid = rxdid;
 497
 498         switch (rxdid) {
 499         case IAVF_RXDID_COMMS_AUX_VLAN:
 500                 rxq->xtr_ol_flag = rte_pmd_ifd_dynflag_proto_xtr_vlan_mask;
 501                 break;
 502         case IAVF_RXDID_COMMS_AUX_IPV4:
 503                 rxq->xtr_ol_flag = rte_pmd_ifd_dynflag_proto_xtr_ipv4_mask;
 504                 break;
 505         case IAVF_RXDID_COMMS_AUX_IPV6:
 506                 rxq->xtr_ol_flag = rte_pmd_ifd_dynflag_proto_xtr_ipv6_mask;
 507                 break;
 508         case IAVF_RXDID_COMMS_AUX_IPV6_FLOW:
 509                 rxq->xtr_ol_flag =
 510                         rte_pmd_ifd_dynflag_proto_xtr_ipv6_flow_mask;
 511                 break;
 512         case IAVF_RXDID_COMMS_AUX_TCP:
 513                 rxq->xtr_ol_flag = rte_pmd_ifd_dynflag_proto_xtr_tcp_mask;
 514                 break;
 515         case IAVF_RXDID_COMMS_AUX_IP_OFFSET:
 516                 rxq->xtr_ol_flag =
 517                         rte_pmd_ifd_dynflag_proto_xtr_ip_offset_mask;
 518                 break;
 519         case IAVF_RXDID_COMMS_IPSEC_CRYPTO:
 520                 rxq->xtr_ol_flag =
 521                         rte_pmd_ifd_dynflag_proto_xtr_ipsec_crypto_said_mask;
 522                 break;
 523         case IAVF_RXDID_COMMS_OVS_1:
 524                 break;
 525         default:
 526                 /* update this according to the RXDID for FLEX_DESC_NONE */
 527                 rxq->rxdid = IAVF_RXDID_COMMS_OVS_1;
 528                 break;
 529         }
 530
 531         if (!rte_pmd_ifd_dynf_proto_xtr_metadata_avail())
 532                 rxq->xtr_ol_flag = 0;
 533 }
 534
 535 int
 536 iavf_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 537                        uint16_t nb_desc, unsigned int socket_id,
 538                        const struct rte_eth_rxconf *rx_conf,
 539                        struct rte_mempool *mp)
 540 {
 541         struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 542         struct iavf_adapter *ad =
 543                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 544         struct iavf_info *vf =
 545                 IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 546         struct iavf_vsi *vsi = &vf->vsi;
 547         struct iavf_rx_queue *rxq;
 548         const struct rte_memzone *mz;
 549         uint32_t ring_size;
 550         uint8_t proto_xtr;
 551         uint16_t len;
 552         uint16_t rx_free_thresh;
 553         uint64_t offloads;
 554
 555         PMD_INIT_FUNC_TRACE();
 556
 557         offloads = rx_conf->offloads | dev->data->dev_conf.rxmode.offloads;
 558
 559         if (nb_desc % IAVF_ALIGN_RING_DESC != 0 ||
 560             nb_desc > IAVF_MAX_RING_DESC ||
 561             nb_desc < IAVF_MIN_RING_DESC) {
 562                 PMD_INIT_LOG(ERR, "Number (%u) of receive descriptors is "
 563                              "invalid", nb_desc);
 564                 return -EINVAL;
 565         }
 566
 567         /* Check free threshold */
 568         rx_free_thresh = (rx_conf->rx_free_thresh == 0) ?
 569                          IAVF_DEFAULT_RX_FREE_THRESH :
 570                          rx_conf->rx_free_thresh;
 571         if (check_rx_thresh(nb_desc, rx_free_thresh) != 0)
 572                 return -EINVAL;
 573
 574         /* Free memory if needed */
 575         if (dev->data->rx_queues[queue_idx]) {
 576                 iavf_dev_rx_queue_release(dev, queue_idx);
 577                 dev->data->rx_queues[queue_idx] = NULL;
 578         }
 579
 580         /* Allocate the rx queue data structure */
 581         rxq = rte_zmalloc_socket("iavf rxq",
 582                                  sizeof(struct iavf_rx_queue),
 583                                  RTE_CACHE_LINE_SIZE,
 584                                  socket_id);
 585         if (!rxq) {
 586                 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
 587                              "rx queue data structure");
 588                 return -ENOMEM;
 589         }
 590
 591         if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC) {
 592                 proto_xtr = vf->proto_xtr ? vf->proto_xtr[queue_idx] :
 593                                 IAVF_PROTO_XTR_NONE;
 594                 rxq->rxdid = iavf_proto_xtr_type_to_rxdid(proto_xtr);
 595                 rxq->proto_xtr = proto_xtr;
 596         } else {
 597                 rxq->rxdid = IAVF_RXDID_LEGACY_1;
 598                 rxq->proto_xtr = IAVF_PROTO_XTR_NONE;
 599         }
 600
 601         if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_VLAN_V2) {
 602                 struct virtchnl_vlan_supported_caps *stripping_support =
 603                                 &vf->vlan_v2_caps.offloads.stripping_support;
 604                 uint32_t stripping_cap;
 605
 606                 if (stripping_support->outer)
 607                         stripping_cap = stripping_support->outer;
 608                 else
 609                         stripping_cap = stripping_support->inner;
 610
 611                 if (stripping_cap & VIRTCHNL_VLAN_TAG_LOCATION_L2TAG1)
 612                         rxq->rx_flags = IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG1;
 613                 else if (stripping_cap & VIRTCHNL_VLAN_TAG_LOCATION_L2TAG2_2)
 614                         rxq->rx_flags = IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG2_2;
 615         } else {
 616                 rxq->rx_flags = IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG1;
 617         }
 618
 619         iavf_select_rxd_to_pkt_fields_handler(rxq, rxq->rxdid);
 620
 621         rxq->mp = mp;
 622         rxq->nb_rx_desc = nb_desc;
 623         rxq->rx_free_thresh = rx_free_thresh;
 624         rxq->queue_id = queue_idx;
 625         rxq->port_id = dev->data->port_id;
 626         rxq->rx_deferred_start = rx_conf->rx_deferred_start;
 627         rxq->rx_hdr_len = 0;
 628         rxq->vsi = vsi;
 629         rxq->offloads = offloads;
 630
 631         if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_KEEP_CRC)
 632                 rxq->crc_len = RTE_ETHER_CRC_LEN;
 633         else
 634                 rxq->crc_len = 0;
 635
 636         len = rte_pktmbuf_data_room_size(rxq->mp) - RTE_PKTMBUF_HEADROOM;
 637         rxq->rx_buf_len = RTE_ALIGN_FLOOR(len, (1 << IAVF_RXQ_CTX_DBUFF_SHIFT));
 638
 639         /* Allocate the software ring. */
 640         len = nb_desc + IAVF_RX_MAX_BURST;
 641         rxq->sw_ring =
 642                 rte_zmalloc_socket("iavf rx sw ring",
 643                                    sizeof(struct rte_mbuf *) * len,
 644                                    RTE_CACHE_LINE_SIZE,
 645                                    socket_id);
 646         if (!rxq->sw_ring) {
 647                 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW ring");
 648                 rte_free(rxq);
 649                 return -ENOMEM;
 650         }
 651
 652         /* Allocate the maximum number of RX ring hardware descriptor with
 653          * a little more to support bulk allocate.
 654          */
 655         len = IAVF_MAX_RING_DESC + IAVF_RX_MAX_BURST;
 656         ring_size = RTE_ALIGN(len * sizeof(union iavf_rx_desc),
 657                               IAVF_DMA_MEM_ALIGN);
 658         mz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
 659                                       ring_size, IAVF_RING_BASE_ALIGN,
 660                                       socket_id);
 661         if (!mz) {
 662                 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for RX");
 663                 rte_free(rxq->sw_ring);
 664                 rte_free(rxq);
 665                 return -ENOMEM;
 666         }
 667         /* Zero all the descriptors in the ring. */
 668         memset(mz->addr, 0, ring_size);
 669         rxq->rx_ring_phys_addr = mz->iova;
 670         rxq->rx_ring = (union iavf_rx_desc *)mz->addr;
 671
 672         rxq->mz = mz;
 673         reset_rx_queue(rxq);
 674         rxq->q_set = true;
 675         dev->data->rx_queues[queue_idx] = rxq;
 676         rxq->qrx_tail = hw->hw_addr + IAVF_QRX_TAIL1(rxq->queue_id);
 677         rxq->ops = &def_rxq_ops;
 678
 679         if (check_rx_bulk_allow(rxq) == true) {
 680                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
 681                              "satisfied. Rx Burst Bulk Alloc function will be "
 682                              "used on port=%d, queue=%d.",
 683                              rxq->port_id, rxq->queue_id);
 684         } else {
 685                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
 686                              "not satisfied, Scattered Rx is requested "
 687                              "on port=%d, queue=%d.",
 688                              rxq->port_id, rxq->queue_id);
 689                 ad->rx_bulk_alloc_allowed = false;
 690         }
 691
 692         if (check_rx_vec_allow(rxq) == false)
 693                 ad->rx_vec_allowed = false;
 694
 695         return 0;
 696 }
 697
 698 int
 699 iavf_dev_tx_queue_setup(struct rte_eth_dev *dev,
 700                        uint16_t queue_idx,
 701                        uint16_t nb_desc,
 702                        unsigned int socket_id,
 703                        const struct rte_eth_txconf *tx_conf)
 704 {
 705         struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 706         struct iavf_adapter *adapter =
 707                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 708         struct iavf_info *vf =
 709                 IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 710         struct iavf_tx_queue *txq;
 711         const struct rte_memzone *mz;
 712         uint32_t ring_size;
 713         uint16_t tx_rs_thresh, tx_free_thresh;
 714         uint64_t offloads;
 715
 716         PMD_INIT_FUNC_TRACE();
 717
 718         offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
 719
 720         if (nb_desc % IAVF_ALIGN_RING_DESC != 0 ||
 721             nb_desc > IAVF_MAX_RING_DESC ||
 722             nb_desc < IAVF_MIN_RING_DESC) {
 723                 PMD_INIT_LOG(ERR, "Number (%u) of transmit descriptors is "
 724                             "invalid", nb_desc);
 725                 return -EINVAL;
 726         }
 727
 728         tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
 729                 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
 730         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
 731                 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
 732         if (check_tx_thresh(nb_desc, tx_rs_thresh, tx_free_thresh) != 0)
 733                 return -EINVAL;
 734
 735         /* Free memory if needed. */
 736         if (dev->data->tx_queues[queue_idx]) {
 737                 iavf_dev_tx_queue_release(dev, queue_idx);
 738                 dev->data->tx_queues[queue_idx] = NULL;
 739         }
 740
 741         /* Allocate the TX queue data structure. */
 742         txq = rte_zmalloc_socket("iavf txq",
 743                                  sizeof(struct iavf_tx_queue),
 744                                  RTE_CACHE_LINE_SIZE,
 745                                  socket_id);
 746         if (!txq) {
 747                 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
 748                              "tx queue structure");
 749                 return -ENOMEM;
 750         }
 751
 752         if (adapter->vf.vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_VLAN_V2) {
 753                 struct virtchnl_vlan_supported_caps *insertion_support =
 754                         &adapter->vf.vlan_v2_caps.offloads.insertion_support;
 755                 uint32_t insertion_cap;
 756
 757                 if (insertion_support->outer)
 758                         insertion_cap = insertion_support->outer;
 759                 else
 760                         insertion_cap = insertion_support->inner;
 761
 762                 if (insertion_cap & VIRTCHNL_VLAN_TAG_LOCATION_L2TAG1)
 763                         txq->vlan_flag = IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG1;
 764                 else if (insertion_cap & VIRTCHNL_VLAN_TAG_LOCATION_L2TAG2)
 765                         txq->vlan_flag = IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG2;
 766         } else {
 767                 txq->vlan_flag = IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG1;
 768         }
 769
 770         txq->nb_tx_desc = nb_desc;
 771         txq->rs_thresh = tx_rs_thresh;
 772         txq->free_thresh = tx_free_thresh;
 773         txq->queue_id = queue_idx;
 774         txq->port_id = dev->data->port_id;
 775         txq->offloads = offloads;
 776         txq->tx_deferred_start = tx_conf->tx_deferred_start;
 777
 778         if (iavf_ipsec_crypto_supported(adapter))
 779                 txq->ipsec_crypto_pkt_md_offset =
 780                         iavf_security_get_pkt_md_offset(adapter);
 781
 782         /* Allocate software ring */
 783         txq->sw_ring =
 784                 rte_zmalloc_socket("iavf tx sw ring",
 785                                    sizeof(struct iavf_tx_entry) * nb_desc,
 786                                    RTE_CACHE_LINE_SIZE,
 787                                    socket_id);
 788         if (!txq->sw_ring) {
 789                 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW TX ring");
 790                 rte_free(txq);
 791                 return -ENOMEM;
 792         }
 793
 794         /* Allocate TX hardware ring descriptors. */
 795         ring_size = sizeof(struct iavf_tx_desc) * IAVF_MAX_RING_DESC;
 796         ring_size = RTE_ALIGN(ring_size, IAVF_DMA_MEM_ALIGN);
 797         mz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
 798                                       ring_size, IAVF_RING_BASE_ALIGN,
 799                                       socket_id);
 800         if (!mz) {
 801                 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for TX");
 802                 rte_free(txq->sw_ring);
 803                 rte_free(txq);
 804                 return -ENOMEM;
 805         }
 806         txq->tx_ring_phys_addr = mz->iova;
 807         txq->tx_ring = (struct iavf_tx_desc *)mz->addr;
 808
 809         txq->mz = mz;
 810         reset_tx_queue(txq);
 811         txq->q_set = true;
 812         dev->data->tx_queues[queue_idx] = txq;
 813         txq->qtx_tail = hw->hw_addr + IAVF_QTX_TAIL1(queue_idx);
 814         txq->ops = &def_txq_ops;
 815
 816         if (check_tx_vec_allow(txq) == false) {
 817                 struct iavf_adapter *ad =
 818                         IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 819                 ad->tx_vec_allowed = false;
 820         }
 821
 822         if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_QOS &&
 823             vf->tm_conf.committed) {
 824                 int tc;
 825                 for (tc = 0; tc < vf->qos_cap->num_elem; tc++) {
 826                         if (txq->queue_id >= vf->qtc_map[tc].start_queue_id &&
 827                             txq->queue_id < (vf->qtc_map[tc].start_queue_id +
 828                             vf->qtc_map[tc].queue_count))
 829                                 break;
 830                 }
 831                 if (tc >= vf->qos_cap->num_elem) {
 832                         PMD_INIT_LOG(ERR, "Queue TC mapping is not correct");
 833                         return -EINVAL;
 834                 }
 835                 txq->tc = tc;
 836         }
 837
 838         return 0;
 839 }
 840
 841 int
 842 iavf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 843 {
 844         struct iavf_adapter *adapter =
 845                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 846         struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 847         struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 848         struct iavf_rx_queue *rxq;
 849         int err = 0;
 850
 851         PMD_DRV_FUNC_TRACE();
 852
 853         if (rx_queue_id >= dev->data->nb_rx_queues)
 854                 return -EINVAL;
 855
 856         rxq = dev->data->rx_queues[rx_queue_id];
 857
 858         err = alloc_rxq_mbufs(rxq);
 859         if (err) {
 860                 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
 861                 return err;
 862         }
 863
 864         rte_wmb();
 865
 866         /* Init the RX tail register. */
 867         IAVF_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 868         IAVF_WRITE_FLUSH(hw);
 869
 870         /* Ready to switch the queue on */
 871         if (!vf->lv_enabled)
 872                 err = iavf_switch_queue(adapter, rx_queue_id, true, true);
 873         else
 874                 err = iavf_switch_queue_lv(adapter, rx_queue_id, true, true);
 875
 876         if (err) {
 877                 release_rxq_mbufs(rxq);
 878                 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
 879                             rx_queue_id);
 880         } else {
 881                 dev->data->rx_queue_state[rx_queue_id] =
 882                         RTE_ETH_QUEUE_STATE_STARTED;
 883         }
 884
 885         return err;
 886 }
 887
 888 int
 889 iavf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 890 {
 891         struct iavf_adapter *adapter =
 892                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 893         struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 894         struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 895         struct iavf_tx_queue *txq;
 896         int err = 0;
 897
 898         PMD_DRV_FUNC_TRACE();
 899
 900         if (tx_queue_id >= dev->data->nb_tx_queues)
 901                 return -EINVAL;
 902
 903         txq = dev->data->tx_queues[tx_queue_id];
 904
 905         /* Init the RX tail register. */
 906         IAVF_PCI_REG_WRITE(txq->qtx_tail, 0);
 907         IAVF_WRITE_FLUSH(hw);
 908
 909         /* Ready to switch the queue on */
 910         if (!vf->lv_enabled)
 911                 err = iavf_switch_queue(adapter, tx_queue_id, false, true);
 912         else
 913                 err = iavf_switch_queue_lv(adapter, tx_queue_id, false, true);
 914
 915         if (err)
 916                 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
 917                             tx_queue_id);
 918         else
 919                 dev->data->tx_queue_state[tx_queue_id] =
 920                         RTE_ETH_QUEUE_STATE_STARTED;
 921
 922         return err;
 923 }
 924
 925 int
 926 iavf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 927 {
 928         struct iavf_adapter *adapter =
 929                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 930         struct iavf_rx_queue *rxq;
 931         int err;
 932
 933         PMD_DRV_FUNC_TRACE();
 934
 935         if (rx_queue_id >= dev->data->nb_rx_queues)
 936                 return -EINVAL;
 937
 938         err = iavf_switch_queue(adapter, rx_queue_id, true, false);
 939         if (err) {
 940                 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
 941                             rx_queue_id);
 942                 return err;
 943         }
 944
 945         rxq = dev->data->rx_queues[rx_queue_id];
 946         rxq->ops->release_mbufs(rxq);
 947         reset_rx_queue(rxq);
 948         dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 949
 950         return 0;
 951 }
 952
 953 int
 954 iavf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 955 {
 956         struct iavf_adapter *adapter =
 957                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 958         struct iavf_tx_queue *txq;
 959         int err;
 960
 961         PMD_DRV_FUNC_TRACE();
 962
 963         if (tx_queue_id >= dev->data->nb_tx_queues)
 964                 return -EINVAL;
 965
 966         err = iavf_switch_queue(adapter, tx_queue_id, false, false);
 967         if (err) {
 968                 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u off",
 969                             tx_queue_id);
 970                 return err;
 971         }
 972
 973         txq = dev->data->tx_queues[tx_queue_id];
 974         txq->ops->release_mbufs(txq);
 975         reset_tx_queue(txq);
 976         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 977
 978         return 0;
 979 }
 980
 981 void
 982 iavf_dev_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
 983 {
 984         struct iavf_rx_queue *q = dev->data->rx_queues[qid];
 985
 986         if (!q)
 987                 return;
 988
 989         q->ops->release_mbufs(q);
 990         rte_free(q->sw_ring);
 991         rte_memzone_free(q->mz);
 992         rte_free(q);
 993 }
 994
 995 void
 996 iavf_dev_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
 997 {
 998         struct iavf_tx_queue *q = dev->data->tx_queues[qid];
 999
1000         if (!q)
1001                 return;
1002
1003         q->ops->release_mbufs(q);
1004         rte_free(q->sw_ring);
1005         rte_memzone_free(q->mz);
1006         rte_free(q);
1007 }
1008
1009 void
1010 iavf_stop_queues(struct rte_eth_dev *dev)
1011 {
1012         struct iavf_adapter *adapter =
1013                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1014         struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1015         struct iavf_rx_queue *rxq;
1016         struct iavf_tx_queue *txq;
1017         int ret, i;
1018
1019         /* Stop All queues */
1020         if (!vf->lv_enabled) {
1021                 ret = iavf_disable_queues(adapter);
1022                 if (ret)
1023                         PMD_DRV_LOG(WARNING, "Fail to stop queues");
1024         } else {
1025                 ret = iavf_disable_queues_lv(adapter);
1026                 if (ret)
1027                         PMD_DRV_LOG(WARNING, "Fail to stop queues for large VF");
1028         }
1029
1030         if (ret)
1031                 PMD_DRV_LOG(WARNING, "Fail to stop queues");
1032
1033         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1034                 txq = dev->data->tx_queues[i];
1035                 if (!txq)
1036                         continue;
1037                 txq->ops->release_mbufs(txq);
1038                 reset_tx_queue(txq);
1039                 dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED;
1040         }
1041         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1042                 rxq = dev->data->rx_queues[i];
1043                 if (!rxq)
1044                         continue;
1045                 rxq->ops->release_mbufs(rxq);
1046                 reset_rx_queue(rxq);
1047                 dev->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED;
1048         }
1049 }
1050
1051 #define IAVF_RX_FLEX_ERR0_BITS  \
1052         ((1 << IAVF_RX_FLEX_DESC_STATUS0_HBO_S) |       \
1053          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_IPE_S) |  \
1054          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_L4E_S) |  \
1055          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S) | \
1056          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S) |        \
1057          (1 << IAVF_RX_FLEX_DESC_STATUS0_RXE_S))
1058
1059 static inline void
1060 iavf_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union iavf_rx_desc *rxdp)
1061 {
1062         if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1063                 (1 << IAVF_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
1064                 mb->ol_flags |= RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED;
1065                 mb->vlan_tci =
1066                         rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
1067         } else {
1068                 mb->vlan_tci = 0;
1069         }
1070 }
1071
1072 static inline void
1073 iavf_flex_rxd_to_vlan_tci(struct rte_mbuf *mb,
1074                           volatile union iavf_rx_flex_desc *rxdp)
1075 {
1076         if (rte_le_to_cpu_64(rxdp->wb.status_error0) &
1077                 (1 << IAVF_RX_FLEX_DESC_STATUS0_L2TAG1P_S)) {
1078                 mb->ol_flags |= RTE_MBUF_F_RX_VLAN |
1079                                 RTE_MBUF_F_RX_VLAN_STRIPPED;
1080                 mb->vlan_tci =
1081                         rte_le_to_cpu_16(rxdp->wb.l2tag1);
1082         } else {
1083                 mb->vlan_tci = 0;
1084         }
1085
1086 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
1087         if (rte_le_to_cpu_16(rxdp->wb.status_error1) &
1088             (1 << IAVF_RX_FLEX_DESC_STATUS1_L2TAG2P_S)) {
1089                 mb->ol_flags |= RTE_MBUF_F_RX_QINQ_STRIPPED |
1090                                 RTE_MBUF_F_RX_QINQ |
1091                                 RTE_MBUF_F_RX_VLAN_STRIPPED |
1092                                 RTE_MBUF_F_RX_VLAN;
1093                 mb->vlan_tci_outer = mb->vlan_tci;
1094                 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.l2tag2_2nd);
1095                 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
1096                            rte_le_to_cpu_16(rxdp->wb.l2tag2_1st),
1097                            rte_le_to_cpu_16(rxdp->wb.l2tag2_2nd));
1098         } else {
1099                 mb->vlan_tci_outer = 0;
1100         }
1101 #endif
1102 }
1103
1104 static inline void
1105 iavf_flex_rxd_to_ipsec_crypto_said_get(struct rte_mbuf *mb,
1106                           volatile union iavf_rx_flex_desc *rxdp)
1107 {
1108         volatile struct iavf_32b_rx_flex_desc_comms_ipsec *desc =
1109                 (volatile struct iavf_32b_rx_flex_desc_comms_ipsec *)rxdp;
1110
1111         mb->dynfield1[0] = desc->ipsec_said &
1112                          IAVF_RX_FLEX_DESC_IPSEC_CRYPTO_SAID_MASK;
1113         }
1114
1115 static inline void
1116 iavf_flex_rxd_to_ipsec_crypto_status(struct rte_mbuf *mb,
1117                           volatile union iavf_rx_flex_desc *rxdp,
1118                           struct iavf_ipsec_crypto_stats *stats)
1119 {
1120         uint16_t status1 = rte_le_to_cpu_64(rxdp->wb.status_error1);
1121
1122         if (status1 & BIT(IAVF_RX_FLEX_DESC_STATUS1_IPSEC_CRYPTO_PROCESSED)) {
1123                 uint16_t ipsec_status;
1124
1125                 mb->ol_flags |= RTE_MBUF_F_RX_SEC_OFFLOAD;
1126
1127                 ipsec_status = status1 &
1128                         IAVF_RX_FLEX_DESC_IPSEC_CRYPTO_STATUS_MASK;
1129
1130
1131                 if (unlikely(ipsec_status !=
1132                         IAVF_IPSEC_CRYPTO_STATUS_SUCCESS)) {
1133                         mb->ol_flags |= RTE_MBUF_F_RX_SEC_OFFLOAD_FAILED;
1134
1135                         switch (ipsec_status) {
1136                         case IAVF_IPSEC_CRYPTO_STATUS_SAD_MISS:
1137                                 stats->ierrors.sad_miss++;
1138                                 break;
1139                         case IAVF_IPSEC_CRYPTO_STATUS_NOT_PROCESSED:
1140                                 stats->ierrors.not_processed++;
1141                                 break;
1142                         case IAVF_IPSEC_CRYPTO_STATUS_ICV_CHECK_FAIL:
1143                                 stats->ierrors.icv_check++;
1144                                 break;
1145                         case IAVF_IPSEC_CRYPTO_STATUS_LENGTH_ERR:
1146                                 stats->ierrors.ipsec_length++;
1147                                 break;
1148                         case IAVF_IPSEC_CRYPTO_STATUS_MISC_ERR:
1149                                 stats->ierrors.misc++;
1150                                 break;
1151 }
1152
1153                         stats->ierrors.count++;
1154                         return;
1155                 }
1156
1157                 stats->icount++;
1158                 stats->ibytes += rxdp->wb.pkt_len & 0x3FFF;
1159
1160                 if (rxdp->wb.rxdid == IAVF_RXDID_COMMS_IPSEC_CRYPTO &&
1161                         ipsec_status !=
1162                                 IAVF_IPSEC_CRYPTO_STATUS_SAD_MISS)
1163                         iavf_flex_rxd_to_ipsec_crypto_said_get(mb, rxdp);
1164         }
1165 }
1166
1167
1168 /* Translate the rx descriptor status and error fields to pkt flags */
1169 static inline uint64_t
1170 iavf_rxd_to_pkt_flags(uint64_t qword)
1171 {
1172         uint64_t flags;
1173         uint64_t error_bits = (qword >> IAVF_RXD_QW1_ERROR_SHIFT);
1174
1175 #define IAVF_RX_ERR_BITS 0x3f
1176
1177         /* Check if RSS_HASH */
1178         flags = (((qword >> IAVF_RX_DESC_STATUS_FLTSTAT_SHIFT) &
1179                                         IAVF_RX_DESC_FLTSTAT_RSS_HASH) ==
1180                         IAVF_RX_DESC_FLTSTAT_RSS_HASH) ? RTE_MBUF_F_RX_RSS_HASH : 0;
1181
1182         /* Check if FDIR Match */
1183         flags |= (qword & (1 << IAVF_RX_DESC_STATUS_FLM_SHIFT) ?
1184                                 RTE_MBUF_F_RX_FDIR : 0);
1185
1186         if (likely((error_bits & IAVF_RX_ERR_BITS) == 0)) {
1187                 flags |= (RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_GOOD);
1188                 return flags;
1189         }
1190
1191         if (unlikely(error_bits & (1 << IAVF_RX_DESC_ERROR_IPE_SHIFT)))
1192                 flags |= RTE_MBUF_F_RX_IP_CKSUM_BAD;
1193         else
1194                 flags |= RTE_MBUF_F_RX_IP_CKSUM_GOOD;
1195
1196         if (unlikely(error_bits & (1 << IAVF_RX_DESC_ERROR_L4E_SHIFT)))
1197                 flags |= RTE_MBUF_F_RX_L4_CKSUM_BAD;
1198         else
1199                 flags |= RTE_MBUF_F_RX_L4_CKSUM_GOOD;
1200
1201         /* TODO: Oversize error bit is not processed here */
1202
1203         return flags;
1204 }
1205
1206 static inline uint64_t
1207 iavf_rxd_build_fdir(volatile union iavf_rx_desc *rxdp, struct rte_mbuf *mb)
1208 {
1209         uint64_t flags = 0;
1210 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
1211         uint16_t flexbh;
1212
1213         flexbh = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
1214                 IAVF_RX_DESC_EXT_STATUS_FLEXBH_SHIFT) &
1215                 IAVF_RX_DESC_EXT_STATUS_FLEXBH_MASK;
1216
1217         if (flexbh == IAVF_RX_DESC_EXT_STATUS_FLEXBH_FD_ID) {
1218                 mb->hash.fdir.hi =
1219                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.fd_id);
1220                 flags |= RTE_MBUF_F_RX_FDIR_ID;
1221         }
1222 #else
1223         mb->hash.fdir.hi =
1224                 rte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.fd_id);
1225         flags |= RTE_MBUF_F_RX_FDIR_ID;
1226 #endif
1227         return flags;
1228 }
1229
1230 #define IAVF_RX_FLEX_ERR0_BITS  \
1231         ((1 << IAVF_RX_FLEX_DESC_STATUS0_HBO_S) |       \
1232          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_IPE_S) |  \
1233          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_L4E_S) |  \
1234          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S) | \
1235          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S) |        \
1236          (1 << IAVF_RX_FLEX_DESC_STATUS0_RXE_S))
1237
1238 /* Rx L3/L4 checksum */
1239 static inline uint64_t
1240 iavf_flex_rxd_error_to_pkt_flags(uint16_t stat_err0)
1241 {
1242         uint64_t flags = 0;
1243
1244         /* check if HW has decoded the packet and checksum */
1245         if (unlikely(!(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_L3L4P_S))))
1246                 return 0;
1247
1248         if (likely(!(stat_err0 & IAVF_RX_FLEX_ERR0_BITS))) {
1249                 flags |= (RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_GOOD);
1250                 return flags;
1251         }
1252
1253         if (unlikely(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_IPE_S)))
1254                 flags |= RTE_MBUF_F_RX_IP_CKSUM_BAD;
1255         else
1256                 flags |= RTE_MBUF_F_RX_IP_CKSUM_GOOD;
1257
1258         if (unlikely(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_L4E_S)))
1259                 flags |= RTE_MBUF_F_RX_L4_CKSUM_BAD;
1260         else
1261                 flags |= RTE_MBUF_F_RX_L4_CKSUM_GOOD;
1262
1263         if (unlikely(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S)))
1264                 flags |= RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD;
1265
1266         return flags;
1267 }
1268
1269 /* If the number of free RX descriptors is greater than the RX free
1270  * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1271  * register. Update the RDT with the value of the last processed RX
1272  * descriptor minus 1, to guarantee that the RDT register is never
1273  * equal to the RDH register, which creates a "full" ring situation
1274  * from the hardware point of view.
1275  */
1276 static inline void
1277 iavf_update_rx_tail(struct iavf_rx_queue *rxq, uint16_t nb_hold, uint16_t rx_id)
1278 {
1279         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1280
1281         if (nb_hold > rxq->rx_free_thresh) {
1282                 PMD_RX_LOG(DEBUG,
1283                            "port_id=%u queue_id=%u rx_tail=%u nb_hold=%u",
1284                            rxq->port_id, rxq->queue_id, rx_id, nb_hold);
1285                 rx_id = (uint16_t)((rx_id == 0) ?
1286                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
1287                 IAVF_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
1288                 nb_hold = 0;
1289         }
1290         rxq->nb_rx_hold = nb_hold;
1291 }
1292
1293 /* implement recv_pkts */
1294 uint16_t
1295 iavf_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1296 {
1297         volatile union iavf_rx_desc *rx_ring;
1298         volatile union iavf_rx_desc *rxdp;
1299         struct iavf_rx_queue *rxq;
1300         union iavf_rx_desc rxd;
1301         struct rte_mbuf *rxe;
1302         struct rte_eth_dev *dev;
1303         struct rte_mbuf *rxm;
1304         struct rte_mbuf *nmb;
1305         uint16_t nb_rx;
1306         uint32_t rx_status;
1307         uint64_t qword1;
1308         uint16_t rx_packet_len;
1309         uint16_t rx_id, nb_hold;
1310         uint64_t dma_addr;
1311         uint64_t pkt_flags;
1312         const uint32_t *ptype_tbl;
1313
1314         nb_rx = 0;
1315         nb_hold = 0;
1316         rxq = rx_queue;
1317         rx_id = rxq->rx_tail;
1318         rx_ring = rxq->rx_ring;
1319         ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1320
1321         while (nb_rx < nb_pkts) {
1322                 rxdp = &rx_ring[rx_id];
1323                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1324                 rx_status = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
1325                             IAVF_RXD_QW1_STATUS_SHIFT;
1326
1327                 /* Check the DD bit first */
1328                 if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)))
1329                         break;
1330                 IAVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
1331
1332                 nmb = rte_mbuf_raw_alloc(rxq->mp);
1333                 if (unlikely(!nmb)) {
1334                         dev = &rte_eth_devices[rxq->port_id];
1335                         dev->data->rx_mbuf_alloc_failed++;
1336                         PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1337                                    "queue_id=%u", rxq->port_id, rxq->queue_id);
1338                         break;
1339                 }
1340
1341                 rxd = *rxdp;
1342                 nb_hold++;
1343                 rxe = rxq->sw_ring[rx_id];
1344                 rxq->sw_ring[rx_id] = nmb;
1345                 rx_id++;
1346                 if (unlikely(rx_id == rxq->nb_rx_desc))
1347                         rx_id = 0;
1348
1349                 /* Prefetch next mbuf */
1350                 rte_prefetch0(rxq->sw_ring[rx_id]);
1351
1352                 /* When next RX descriptor is on a cache line boundary,
1353                  * prefetch the next 4 RX descriptors and next 8 pointers
1354                  * to mbufs.
1355                  */
1356                 if ((rx_id & 0x3) == 0) {
1357                         rte_prefetch0(&rx_ring[rx_id]);
1358                         rte_prefetch0(rxq->sw_ring[rx_id]);
1359                 }
1360                 rxm = rxe;
1361                 dma_addr =
1362                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1363                 rxdp->read.hdr_addr = 0;
1364                 rxdp->read.pkt_addr = dma_addr;
1365
1366                 rx_packet_len = ((qword1 & IAVF_RXD_QW1_LENGTH_PBUF_MASK) >>
1367                                 IAVF_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
1368
1369                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1370                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
1371                 rxm->nb_segs = 1;
1372                 rxm->next = NULL;
1373                 rxm->pkt_len = rx_packet_len;
1374                 rxm->data_len = rx_packet_len;
1375                 rxm->port = rxq->port_id;
1376                 rxm->ol_flags = 0;
1377                 iavf_rxd_to_vlan_tci(rxm, &rxd);
1378                 pkt_flags = iavf_rxd_to_pkt_flags(qword1);
1379                 rxm->packet_type =
1380                         ptype_tbl[(uint8_t)((qword1 &
1381                         IAVF_RXD_QW1_PTYPE_MASK) >> IAVF_RXD_QW1_PTYPE_SHIFT)];
1382
1383                 if (pkt_flags & RTE_MBUF_F_RX_RSS_HASH)
1384                         rxm->hash.rss =
1385                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1386
1387                 if (pkt_flags & RTE_MBUF_F_RX_FDIR)
1388                         pkt_flags |= iavf_rxd_build_fdir(&rxd, rxm);
1389
1390                 rxm->ol_flags |= pkt_flags;
1391
1392                 rx_pkts[nb_rx++] = rxm;
1393         }
1394         rxq->rx_tail = rx_id;
1395
1396         iavf_update_rx_tail(rxq, nb_hold, rx_id);
1397
1398         return nb_rx;
1399 }
1400
1401 /* implement recv_pkts for flexible Rx descriptor */
1402 uint16_t
1403 iavf_recv_pkts_flex_rxd(void *rx_queue,
1404                         struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1405 {
1406         volatile union iavf_rx_desc *rx_ring;
1407         volatile union iavf_rx_flex_desc *rxdp;
1408         struct iavf_rx_queue *rxq;
1409         union iavf_rx_flex_desc rxd;
1410         struct rte_mbuf *rxe;
1411         struct rte_eth_dev *dev;
1412         struct rte_mbuf *rxm;
1413         struct rte_mbuf *nmb;
1414         uint16_t nb_rx;
1415         uint16_t rx_stat_err0;
1416         uint16_t rx_packet_len;
1417         uint16_t rx_id, nb_hold;
1418         uint64_t dma_addr;
1419         uint64_t pkt_flags;
1420         const uint32_t *ptype_tbl;
1421
1422         nb_rx = 0;
1423         nb_hold = 0;
1424         rxq = rx_queue;
1425         rx_id = rxq->rx_tail;
1426         rx_ring = rxq->rx_ring;
1427         ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1428
1429         while (nb_rx < nb_pkts) {
1430                 rxdp = (volatile union iavf_rx_flex_desc *)&rx_ring[rx_id];
1431                 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1432
1433                 /* Check the DD bit first */
1434                 if (!(rx_stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S)))
1435                         break;
1436                 IAVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
1437
1438                 nmb = rte_mbuf_raw_alloc(rxq->mp);
1439                 if (unlikely(!nmb)) {
1440                         dev = &rte_eth_devices[rxq->port_id];
1441                         dev->data->rx_mbuf_alloc_failed++;
1442                         PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1443                                    "queue_id=%u", rxq->port_id, rxq->queue_id);
1444                         break;
1445                 }
1446
1447                 rxd = *rxdp;
1448                 nb_hold++;
1449                 rxe = rxq->sw_ring[rx_id];
1450                 rxq->sw_ring[rx_id] = nmb;
1451                 rx_id++;
1452                 if (unlikely(rx_id == rxq->nb_rx_desc))
1453                         rx_id = 0;
1454
1455                 /* Prefetch next mbuf */
1456                 rte_prefetch0(rxq->sw_ring[rx_id]);
1457
1458                 /* When next RX descriptor is on a cache line boundary,
1459                  * prefetch the next 4 RX descriptors and next 8 pointers
1460                  * to mbufs.
1461                  */
1462                 if ((rx_id & 0x3) == 0) {
1463                         rte_prefetch0(&rx_ring[rx_id]);
1464                         rte_prefetch0(rxq->sw_ring[rx_id]);
1465                 }
1466                 rxm = rxe;
1467                 dma_addr =
1468                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1469                 rxdp->read.hdr_addr = 0;
1470                 rxdp->read.pkt_addr = dma_addr;
1471
1472                 rx_packet_len = (rte_le_to_cpu_16(rxd.wb.pkt_len) &
1473                                 IAVF_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
1474
1475                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1476                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
1477                 rxm->nb_segs = 1;
1478                 rxm->next = NULL;
1479                 rxm->pkt_len = rx_packet_len;
1480                 rxm->data_len = rx_packet_len;
1481                 rxm->port = rxq->port_id;
1482                 rxm->ol_flags = 0;
1483                 rxm->packet_type = ptype_tbl[IAVF_RX_FLEX_DESC_PTYPE_M &
1484                         rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
1485                 iavf_flex_rxd_to_vlan_tci(rxm, &rxd);
1486                 iavf_flex_rxd_to_ipsec_crypto_status(rxm, &rxd,
1487                                 &rxq->stats.ipsec_crypto);
1488                 rxd_to_pkt_fields_ops[rxq->rxdid](rxq, rxm, &rxd);
1489                 pkt_flags = iavf_flex_rxd_error_to_pkt_flags(rx_stat_err0);
1490                 rxm->ol_flags |= pkt_flags;
1491
1492                 rx_pkts[nb_rx++] = rxm;
1493         }
1494         rxq->rx_tail = rx_id;
1495
1496         iavf_update_rx_tail(rxq, nb_hold, rx_id);
1497
1498         return nb_rx;
1499 }
1500
1501 /* implement recv_scattered_pkts for flexible Rx descriptor */
1502 uint16_t
1503 iavf_recv_scattered_pkts_flex_rxd(void *rx_queue, struct rte_mbuf **rx_pkts,
1504                                   uint16_t nb_pkts)
1505 {
1506         struct iavf_rx_queue *rxq = rx_queue;
1507         union iavf_rx_flex_desc rxd;
1508         struct rte_mbuf *rxe;
1509         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1510         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1511         struct rte_mbuf *nmb, *rxm;
1512         uint16_t rx_id = rxq->rx_tail;
1513         uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
1514         struct rte_eth_dev *dev;
1515         uint16_t rx_stat_err0;
1516         uint64_t dma_addr;
1517         uint64_t pkt_flags;
1518
1519         volatile union iavf_rx_desc *rx_ring = rxq->rx_ring;
1520         volatile union iavf_rx_flex_desc *rxdp;
1521         const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1522
1523         while (nb_rx < nb_pkts) {
1524                 rxdp = (volatile union iavf_rx_flex_desc *)&rx_ring[rx_id];
1525                 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1526
1527                 /* Check the DD bit */
1528                 if (!(rx_stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S)))
1529                         break;
1530                 IAVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
1531
1532                 nmb = rte_mbuf_raw_alloc(rxq->mp);
1533                 if (unlikely(!nmb)) {
1534                         PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1535                                    "queue_id=%u", rxq->port_id, rxq->queue_id);
1536                         dev = &rte_eth_devices[rxq->port_id];
1537                         dev->data->rx_mbuf_alloc_failed++;
1538                         break;
1539                 }
1540
1541                 rxd = *rxdp;
1542                 nb_hold++;
1543                 rxe = rxq->sw_ring[rx_id];
1544                 rxq->sw_ring[rx_id] = nmb;
1545                 rx_id++;
1546                 if (rx_id == rxq->nb_rx_desc)
1547                         rx_id = 0;
1548
1549                 /* Prefetch next mbuf */
1550                 rte_prefetch0(rxq->sw_ring[rx_id]);
1551
1552                 /* When next RX descriptor is on a cache line boundary,
1553                  * prefetch the next 4 RX descriptors and next 8 pointers
1554                  * to mbufs.
1555                  */
1556                 if ((rx_id & 0x3) == 0) {
1557                         rte_prefetch0(&rx_ring[rx_id]);
1558                         rte_prefetch0(rxq->sw_ring[rx_id]);
1559                 }
1560
1561                 rxm = rxe;
1562                 dma_addr =
1563                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1564
1565                 /* Set data buffer address and data length of the mbuf */
1566                 rxdp->read.hdr_addr = 0;
1567                 rxdp->read.pkt_addr = dma_addr;
1568                 rx_packet_len = rte_le_to_cpu_16(rxd.wb.pkt_len) &
1569                                 IAVF_RX_FLX_DESC_PKT_LEN_M;
1570                 rxm->data_len = rx_packet_len;
1571                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1572
1573                 /* If this is the first buffer of the received packet, set the
1574                  * pointer to the first mbuf of the packet and initialize its
1575                  * context. Otherwise, update the total length and the number
1576                  * of segments of the current scattered packet, and update the
1577                  * pointer to the last mbuf of the current packet.
1578                  */
1579                 if (!first_seg) {
1580                         first_seg = rxm;
1581                         first_seg->nb_segs = 1;
1582                         first_seg->pkt_len = rx_packet_len;
1583                 } else {
1584                         first_seg->pkt_len =
1585                                 (uint16_t)(first_seg->pkt_len +
1586                                                 rx_packet_len);
1587                         first_seg->nb_segs++;
1588                         last_seg->next = rxm;
1589                 }
1590
1591                 /* If this is not the last buffer of the received packet,
1592                  * update the pointer to the last mbuf of the current scattered
1593                  * packet and continue to parse the RX ring.
1594                  */
1595                 if (!(rx_stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_EOF_S))) {
1596                         last_seg = rxm;
1597                         continue;
1598                 }
1599
1600                 /* This is the last buffer of the received packet. If the CRC
1601                  * is not stripped by the hardware:
1602                  *  - Subtract the CRC length from the total packet length.
1603                  *  - If the last buffer only contains the whole CRC or a part
1604                  *  of it, free the mbuf associated to the last buffer. If part
1605                  *  of the CRC is also contained in the previous mbuf, subtract
1606                  *  the length of that CRC part from the data length of the
1607                  *  previous mbuf.
1608                  */
1609                 rxm->next = NULL;
1610                 if (unlikely(rxq->crc_len > 0)) {
1611                         first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
1612                         if (rx_packet_len <= RTE_ETHER_CRC_LEN) {
1613                                 rte_pktmbuf_free_seg(rxm);
1614                                 first_seg->nb_segs--;
1615                                 last_seg->data_len =
1616                                         (uint16_t)(last_seg->data_len -
1617                                         (RTE_ETHER_CRC_LEN - rx_packet_len));
1618                                 last_seg->next = NULL;
1619                         } else {
1620                                 rxm->data_len = (uint16_t)(rx_packet_len -
1621                                                         RTE_ETHER_CRC_LEN);
1622                         }
1623                 }
1624
1625                 first_seg->port = rxq->port_id;
1626                 first_seg->ol_flags = 0;
1627                 first_seg->packet_type = ptype_tbl[IAVF_RX_FLEX_DESC_PTYPE_M &
1628                         rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
1629                 iavf_flex_rxd_to_vlan_tci(first_seg, &rxd);
1630                 iavf_flex_rxd_to_ipsec_crypto_status(first_seg, &rxd,
1631                                 &rxq->stats.ipsec_crypto);
1632                 rxd_to_pkt_fields_ops[rxq->rxdid](rxq, first_seg, &rxd);
1633                 pkt_flags = iavf_flex_rxd_error_to_pkt_flags(rx_stat_err0);
1634
1635                 first_seg->ol_flags |= pkt_flags;
1636
1637                 /* Prefetch data of first segment, if configured to do so. */
1638                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1639                                           first_seg->data_off));
1640                 rx_pkts[nb_rx++] = first_seg;
1641                 first_seg = NULL;
1642         }
1643
1644         /* Record index of the next RX descriptor to probe. */
1645         rxq->rx_tail = rx_id;
1646         rxq->pkt_first_seg = first_seg;
1647         rxq->pkt_last_seg = last_seg;
1648
1649         iavf_update_rx_tail(rxq, nb_hold, rx_id);
1650
1651         return nb_rx;
1652 }
1653
1654 /* implement recv_scattered_pkts  */
1655 uint16_t
1656 iavf_recv_scattered_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1657                         uint16_t nb_pkts)
1658 {
1659         struct iavf_rx_queue *rxq = rx_queue;
1660         union iavf_rx_desc rxd;
1661         struct rte_mbuf *rxe;
1662         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1663         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1664         struct rte_mbuf *nmb, *rxm;
1665         uint16_t rx_id = rxq->rx_tail;
1666         uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
1667         struct rte_eth_dev *dev;
1668         uint32_t rx_status;
1669         uint64_t qword1;
1670         uint64_t dma_addr;
1671         uint64_t pkt_flags;
1672
1673         volatile union iavf_rx_desc *rx_ring = rxq->rx_ring;
1674         volatile union iavf_rx_desc *rxdp;
1675         const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1676
1677         while (nb_rx < nb_pkts) {
1678                 rxdp = &rx_ring[rx_id];
1679                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1680                 rx_status = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
1681                             IAVF_RXD_QW1_STATUS_SHIFT;
1682
1683                 /* Check the DD bit */
1684                 if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)))
1685                         break;
1686                 IAVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
1687
1688                 nmb = rte_mbuf_raw_alloc(rxq->mp);
1689                 if (unlikely(!nmb)) {
1690                         PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1691                                    "queue_id=%u", rxq->port_id, rxq->queue_id);
1692                         dev = &rte_eth_devices[rxq->port_id];
1693                         dev->data->rx_mbuf_alloc_failed++;
1694                         break;
1695                 }
1696
1697                 rxd = *rxdp;
1698                 nb_hold++;
1699                 rxe = rxq->sw_ring[rx_id];
1700                 rxq->sw_ring[rx_id] = nmb;
1701                 rx_id++;
1702                 if (rx_id == rxq->nb_rx_desc)
1703                         rx_id = 0;
1704
1705                 /* Prefetch next mbuf */
1706                 rte_prefetch0(rxq->sw_ring[rx_id]);
1707
1708                 /* When next RX descriptor is on a cache line boundary,
1709                  * prefetch the next 4 RX descriptors and next 8 pointers
1710                  * to mbufs.
1711                  */
1712                 if ((rx_id & 0x3) == 0) {
1713                         rte_prefetch0(&rx_ring[rx_id]);
1714                         rte_prefetch0(rxq->sw_ring[rx_id]);
1715                 }
1716
1717                 rxm = rxe;
1718                 dma_addr =
1719                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1720
1721                 /* Set data buffer address and data length of the mbuf */
1722                 rxdp->read.hdr_addr = 0;
1723                 rxdp->read.pkt_addr = dma_addr;
1724                 rx_packet_len = (qword1 & IAVF_RXD_QW1_LENGTH_PBUF_MASK) >>
1725                                  IAVF_RXD_QW1_LENGTH_PBUF_SHIFT;
1726                 rxm->data_len = rx_packet_len;
1727                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1728
1729                 /* If this is the first buffer of the received packet, set the
1730                  * pointer to the first mbuf of the packet and initialize its
1731                  * context. Otherwise, update the total length and the number
1732                  * of segments of the current scattered packet, and update the
1733                  * pointer to the last mbuf of the current packet.
1734                  */
1735                 if (!first_seg) {
1736                         first_seg = rxm;
1737                         first_seg->nb_segs = 1;
1738                         first_seg->pkt_len = rx_packet_len;
1739                 } else {
1740                         first_seg->pkt_len =
1741                                 (uint16_t)(first_seg->pkt_len +
1742                                                 rx_packet_len);
1743                         first_seg->nb_segs++;
1744                         last_seg->next = rxm;
1745                 }
1746
1747                 /* If this is not the last buffer of the received packet,
1748                  * update the pointer to the last mbuf of the current scattered
1749                  * packet and continue to parse the RX ring.
1750                  */
1751                 if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_EOF_SHIFT))) {
1752                         last_seg = rxm;
1753                         continue;
1754                 }
1755
1756                 /* This is the last buffer of the received packet. If the CRC
1757                  * is not stripped by the hardware:
1758                  *  - Subtract the CRC length from the total packet length.
1759                  *  - If the last buffer only contains the whole CRC or a part
1760                  *  of it, free the mbuf associated to the last buffer. If part
1761                  *  of the CRC is also contained in the previous mbuf, subtract
1762                  *  the length of that CRC part from the data length of the
1763                  *  previous mbuf.
1764                  */
1765                 rxm->next = NULL;
1766                 if (unlikely(rxq->crc_len > 0)) {
1767                         first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
1768                         if (rx_packet_len <= RTE_ETHER_CRC_LEN) {
1769                                 rte_pktmbuf_free_seg(rxm);
1770                                 first_seg->nb_segs--;
1771                                 last_seg->data_len =
1772                                         (uint16_t)(last_seg->data_len -
1773                                         (RTE_ETHER_CRC_LEN - rx_packet_len));
1774                                 last_seg->next = NULL;
1775                         } else
1776                                 rxm->data_len = (uint16_t)(rx_packet_len -
1777                                                         RTE_ETHER_CRC_LEN);
1778                 }
1779
1780                 first_seg->port = rxq->port_id;
1781                 first_seg->ol_flags = 0;
1782                 iavf_rxd_to_vlan_tci(first_seg, &rxd);
1783                 pkt_flags = iavf_rxd_to_pkt_flags(qword1);
1784                 first_seg->packet_type =
1785                         ptype_tbl[(uint8_t)((qword1 &
1786                         IAVF_RXD_QW1_PTYPE_MASK) >> IAVF_RXD_QW1_PTYPE_SHIFT)];
1787
1788                 if (pkt_flags & RTE_MBUF_F_RX_RSS_HASH)
1789                         first_seg->hash.rss =
1790                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1791
1792                 if (pkt_flags & RTE_MBUF_F_RX_FDIR)
1793                         pkt_flags |= iavf_rxd_build_fdir(&rxd, first_seg);
1794
1795                 first_seg->ol_flags |= pkt_flags;
1796
1797                 /* Prefetch data of first segment, if configured to do so. */
1798                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1799                                           first_seg->data_off));
1800                 rx_pkts[nb_rx++] = first_seg;
1801                 first_seg = NULL;
1802         }
1803
1804         /* Record index of the next RX descriptor to probe. */
1805         rxq->rx_tail = rx_id;
1806         rxq->pkt_first_seg = first_seg;
1807         rxq->pkt_last_seg = last_seg;
1808
1809         iavf_update_rx_tail(rxq, nb_hold, rx_id);
1810
1811         return nb_rx;
1812 }
1813
1814 #define IAVF_LOOK_AHEAD 8
1815 static inline int
1816 iavf_rx_scan_hw_ring_flex_rxd(struct iavf_rx_queue *rxq)
1817 {
1818         volatile union iavf_rx_flex_desc *rxdp;
1819         struct rte_mbuf **rxep;
1820         struct rte_mbuf *mb;
1821         uint16_t stat_err0;
1822         uint16_t pkt_len;
1823         int32_t s[IAVF_LOOK_AHEAD], var, nb_dd;
1824         int32_t i, j, nb_rx = 0;
1825         uint64_t pkt_flags;
1826         const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1827
1828         rxdp = (volatile union iavf_rx_flex_desc *)&rxq->rx_ring[rxq->rx_tail];
1829         rxep = &rxq->sw_ring[rxq->rx_tail];
1830
1831         stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1832
1833         /* Make sure there is at least 1 packet to receive */
1834         if (!(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S)))
1835                 return 0;
1836
1837         /* Scan LOOK_AHEAD descriptors at a time to determine which
1838          * descriptors reference packets that are ready to be received.
1839          */
1840         for (i = 0; i < IAVF_RX_MAX_BURST; i += IAVF_LOOK_AHEAD,
1841              rxdp += IAVF_LOOK_AHEAD, rxep += IAVF_LOOK_AHEAD) {
1842                 /* Read desc statuses backwards to avoid race condition */
1843                 for (j = IAVF_LOOK_AHEAD - 1; j >= 0; j--)
1844                         s[j] = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1845
1846                 /* This barrier is to order loads of different words in the descriptor */
1847                 rte_atomic_thread_fence(__ATOMIC_ACQUIRE);
1848
1849                 /* Compute how many contiguous DD bits were set */
1850                 for (j = 0, nb_dd = 0; j < IAVF_LOOK_AHEAD; j++) {
1851                         var = s[j] & (1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S);
1852 #ifdef RTE_ARCH_ARM
1853                         /* For Arm platforms, count only contiguous descriptors
1854                          * whose DD bit is set to 1. On Arm platforms, reads of
1855                          * descriptors can be reordered. Since the CPU may
1856                          * be reading the descriptors as the NIC updates them
1857                          * in memory, it is possbile that the DD bit for a
1858                          * descriptor earlier in the queue is read as not set
1859                          * while the DD bit for a descriptor later in the queue
1860                          * is read as set.
1861                          */
1862                         if (var)
1863                                 nb_dd += 1;
1864                         else
1865                                 break;
1866 #else
1867                         nb_dd += var;
1868 #endif
1869                 }
1870
1871                 nb_rx += nb_dd;
1872
1873                 /* Translate descriptor info to mbuf parameters */
1874                 for (j = 0; j < nb_dd; j++) {
1875                         IAVF_DUMP_RX_DESC(rxq, &rxdp[j],
1876                                           rxq->rx_tail +
1877                                           i * IAVF_LOOK_AHEAD + j);
1878
1879                         mb = rxep[j];
1880                         pkt_len = (rte_le_to_cpu_16(rxdp[j].wb.pkt_len) &
1881                                 IAVF_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
1882                         mb->data_len = pkt_len;
1883                         mb->pkt_len = pkt_len;
1884                         mb->ol_flags = 0;
1885
1886                         mb->packet_type = ptype_tbl[IAVF_RX_FLEX_DESC_PTYPE_M &
1887                                 rte_le_to_cpu_16(rxdp[j].wb.ptype_flex_flags0)];
1888                         iavf_flex_rxd_to_vlan_tci(mb, &rxdp[j]);
1889                         iavf_flex_rxd_to_ipsec_crypto_status(mb, &rxdp[j],
1890                                 &rxq->stats.ipsec_crypto);
1891                         rxd_to_pkt_fields_ops[rxq->rxdid](rxq, mb, &rxdp[j]);
1892                         stat_err0 = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1893                         pkt_flags = iavf_flex_rxd_error_to_pkt_flags(stat_err0);
1894
1895                         mb->ol_flags |= pkt_flags;
1896                 }
1897
1898                 for (j = 0; j < IAVF_LOOK_AHEAD; j++)
1899                         rxq->rx_stage[i + j] = rxep[j];
1900
1901                 if (nb_dd != IAVF_LOOK_AHEAD)
1902                         break;
1903         }
1904
1905         /* Clear software ring entries */
1906         for (i = 0; i < nb_rx; i++)
1907                 rxq->sw_ring[rxq->rx_tail + i] = NULL;
1908
1909         return nb_rx;
1910 }
1911
1912 static inline int
1913 iavf_rx_scan_hw_ring(struct iavf_rx_queue *rxq)
1914 {
1915         volatile union iavf_rx_desc *rxdp;
1916         struct rte_mbuf **rxep;
1917         struct rte_mbuf *mb;
1918         uint16_t pkt_len;
1919         uint64_t qword1;
1920         uint32_t rx_status;
1921         int32_t s[IAVF_LOOK_AHEAD], var, nb_dd;
1922         int32_t i, j, nb_rx = 0;
1923         uint64_t pkt_flags;
1924         const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1925
1926         rxdp = &rxq->rx_ring[rxq->rx_tail];
1927         rxep = &rxq->sw_ring[rxq->rx_tail];
1928
1929         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1930         rx_status = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
1931                     IAVF_RXD_QW1_STATUS_SHIFT;
1932
1933         /* Make sure there is at least 1 packet to receive */
1934         if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)))
1935                 return 0;
1936
1937         /* Scan LOOK_AHEAD descriptors at a time to determine which
1938          * descriptors reference packets that are ready to be received.
1939          */
1940         for (i = 0; i < IAVF_RX_MAX_BURST; i += IAVF_LOOK_AHEAD,
1941              rxdp += IAVF_LOOK_AHEAD, rxep += IAVF_LOOK_AHEAD) {
1942                 /* Read desc statuses backwards to avoid race condition */
1943                 for (j = IAVF_LOOK_AHEAD - 1; j >= 0; j--) {
1944                         qword1 = rte_le_to_cpu_64(
1945                                 rxdp[j].wb.qword1.status_error_len);
1946                         s[j] = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
1947                                IAVF_RXD_QW1_STATUS_SHIFT;
1948                 }
1949
1950                 /* This barrier is to order loads of different words in the descriptor */
1951                 rte_atomic_thread_fence(__ATOMIC_ACQUIRE);
1952
1953                 /* Compute how many contiguous DD bits were set */
1954                 for (j = 0, nb_dd = 0; j < IAVF_LOOK_AHEAD; j++) {
1955                         var = s[j] & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT);
1956 #ifdef RTE_ARCH_ARM
1957                         /* For Arm platforms, count only contiguous descriptors
1958                          * whose DD bit is set to 1. On Arm platforms, reads of
1959                          * descriptors can be reordered. Since the CPU may
1960                          * be reading the descriptors as the NIC updates them
1961                          * in memory, it is possbile that the DD bit for a
1962                          * descriptor earlier in the queue is read as not set
1963                          * while the DD bit for a descriptor later in the queue
1964                          * is read as set.
1965                          */
1966                         if (var)
1967                                 nb_dd += 1;
1968                         else
1969                                 break;
1970 #else
1971                         nb_dd += var;
1972 #endif
1973                 }
1974
1975                 nb_rx += nb_dd;
1976
1977                 /* Translate descriptor info to mbuf parameters */
1978                 for (j = 0; j < nb_dd; j++) {
1979                         IAVF_DUMP_RX_DESC(rxq, &rxdp[j],
1980                                          rxq->rx_tail + i * IAVF_LOOK_AHEAD + j);
1981
1982                         mb = rxep[j];
1983                         qword1 = rte_le_to_cpu_64
1984                                         (rxdp[j].wb.qword1.status_error_len);
1985                         pkt_len = ((qword1 & IAVF_RXD_QW1_LENGTH_PBUF_MASK) >>
1986                                   IAVF_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
1987                         mb->data_len = pkt_len;
1988                         mb->pkt_len = pkt_len;
1989                         mb->ol_flags = 0;
1990                         iavf_rxd_to_vlan_tci(mb, &rxdp[j]);
1991                         pkt_flags = iavf_rxd_to_pkt_flags(qword1);
1992                         mb->packet_type =
1993                                 ptype_tbl[(uint8_t)((qword1 &
1994                                 IAVF_RXD_QW1_PTYPE_MASK) >>
1995                                 IAVF_RXD_QW1_PTYPE_SHIFT)];
1996
1997                         if (pkt_flags & RTE_MBUF_F_RX_RSS_HASH)
1998                                 mb->hash.rss = rte_le_to_cpu_32(
1999                                         rxdp[j].wb.qword0.hi_dword.rss);
2000
2001                         if (pkt_flags & RTE_MBUF_F_RX_FDIR)
2002                                 pkt_flags |= iavf_rxd_build_fdir(&rxdp[j], mb);
2003
2004                         mb->ol_flags |= pkt_flags;
2005                 }
2006
2007                 for (j = 0; j < IAVF_LOOK_AHEAD; j++)
2008                         rxq->rx_stage[i + j] = rxep[j];
2009
2010                 if (nb_dd != IAVF_LOOK_AHEAD)
2011                         break;
2012         }
2013
2014         /* Clear software ring entries */
2015         for (i = 0; i < nb_rx; i++)
2016                 rxq->sw_ring[rxq->rx_tail + i] = NULL;
2017
2018         return nb_rx;
2019 }
2020
2021 static inline uint16_t
2022 iavf_rx_fill_from_stage(struct iavf_rx_queue *rxq,
2023                        struct rte_mbuf **rx_pkts,
2024                        uint16_t nb_pkts)
2025 {
2026         uint16_t i;
2027         struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
2028
2029         nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
2030
2031         for (i = 0; i < nb_pkts; i++)
2032                 rx_pkts[i] = stage[i];
2033
2034         rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
2035         rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
2036
2037         return nb_pkts;
2038 }
2039
2040 static inline int
2041 iavf_rx_alloc_bufs(struct iavf_rx_queue *rxq)
2042 {
2043         volatile union iavf_rx_desc *rxdp;
2044         struct rte_mbuf **rxep;
2045         struct rte_mbuf *mb;
2046         uint16_t alloc_idx, i;
2047         uint64_t dma_addr;
2048         int diag;
2049
2050         /* Allocate buffers in bulk */
2051         alloc_idx = (uint16_t)(rxq->rx_free_trigger -
2052                                 (rxq->rx_free_thresh - 1));
2053         rxep = &rxq->sw_ring[alloc_idx];
2054         diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
2055                                     rxq->rx_free_thresh);
2056         if (unlikely(diag != 0)) {
2057                 PMD_RX_LOG(ERR, "Failed to get mbufs in bulk");
2058                 return -ENOMEM;
2059         }
2060
2061         rxdp = &rxq->rx_ring[alloc_idx];
2062         for (i = 0; i < rxq->rx_free_thresh; i++) {
2063                 if (likely(i < (rxq->rx_free_thresh - 1)))
2064                         /* Prefetch next mbuf */
2065                         rte_prefetch0(rxep[i + 1]);
2066
2067                 mb = rxep[i];
2068                 rte_mbuf_refcnt_set(mb, 1);
2069                 mb->next = NULL;
2070                 mb->data_off = RTE_PKTMBUF_HEADROOM;
2071                 mb->nb_segs = 1;
2072                 mb->port = rxq->port_id;
2073                 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mb));
2074                 rxdp[i].read.hdr_addr = 0;
2075                 rxdp[i].read.pkt_addr = dma_addr;
2076         }
2077
2078         /* Update rx tail register */
2079         rte_wmb();
2080         IAVF_PCI_REG_WC_WRITE_RELAXED(rxq->qrx_tail, rxq->rx_free_trigger);
2081
2082         rxq->rx_free_trigger =
2083                 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
2084         if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
2085                 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2086
2087         return 0;
2088 }
2089
2090 static inline uint16_t
2091 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
2092 {
2093         struct iavf_rx_queue *rxq = (struct iavf_rx_queue *)rx_queue;
2094         uint16_t nb_rx = 0;
2095
2096         if (!nb_pkts)
2097                 return 0;
2098
2099         if (rxq->rx_nb_avail)
2100                 return iavf_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
2101
2102         if (rxq->rxdid >= IAVF_RXDID_FLEX_NIC && rxq->rxdid <= IAVF_RXDID_LAST)
2103                 nb_rx = (uint16_t)iavf_rx_scan_hw_ring_flex_rxd(rxq);
2104         else
2105                 nb_rx = (uint16_t)iavf_rx_scan_hw_ring(rxq);
2106         rxq->rx_next_avail = 0;
2107         rxq->rx_nb_avail = nb_rx;
2108         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
2109
2110         if (rxq->rx_tail > rxq->rx_free_trigger) {
2111                 if (iavf_rx_alloc_bufs(rxq) != 0) {
2112                         uint16_t i, j;
2113
2114                         /* TODO: count rx_mbuf_alloc_failed here */
2115
2116                         rxq->rx_nb_avail = 0;
2117                         rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
2118                         for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
2119                                 rxq->sw_ring[j] = rxq->rx_stage[i];
2120
2121                         return 0;
2122                 }
2123         }
2124
2125         if (rxq->rx_tail >= rxq->nb_rx_desc)
2126                 rxq->rx_tail = 0;
2127
2128         PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u, nb_rx=%u",
2129                    rxq->port_id, rxq->queue_id,
2130                    rxq->rx_tail, nb_rx);
2131
2132         if (rxq->rx_nb_avail)
2133                 return iavf_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
2134
2135         return 0;
2136 }
2137
2138 static uint16_t
2139 iavf_recv_pkts_bulk_alloc(void *rx_queue,
2140                          struct rte_mbuf **rx_pkts,
2141                          uint16_t nb_pkts)
2142 {
2143         uint16_t nb_rx = 0, n, count;
2144
2145         if (unlikely(nb_pkts == 0))
2146                 return 0;
2147
2148         if (likely(nb_pkts <= IAVF_RX_MAX_BURST))
2149                 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
2150
2151         while (nb_pkts) {
2152                 n = RTE_MIN(nb_pkts, IAVF_RX_MAX_BURST);
2153                 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
2154                 nb_rx = (uint16_t)(nb_rx + count);
2155                 nb_pkts = (uint16_t)(nb_pkts - count);
2156                 if (count < n)
2157                         break;
2158         }
2159
2160         return nb_rx;
2161 }
2162
2163 static inline int
2164 iavf_xmit_cleanup(struct iavf_tx_queue *txq)
2165 {
2166         struct iavf_tx_entry *sw_ring = txq->sw_ring;
2167         uint16_t last_desc_cleaned = txq->last_desc_cleaned;
2168         uint16_t nb_tx_desc = txq->nb_tx_desc;
2169         uint16_t desc_to_clean_to;
2170         uint16_t nb_tx_to_clean;
2171
2172         volatile struct iavf_tx_desc *txd = txq->tx_ring;
2173
2174         desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->rs_thresh);
2175         if (desc_to_clean_to >= nb_tx_desc)
2176                 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
2177
2178         desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
2179         if ((txd[desc_to_clean_to].cmd_type_offset_bsz &
2180                         rte_cpu_to_le_64(IAVF_TXD_QW1_DTYPE_MASK)) !=
2181                         rte_cpu_to_le_64(IAVF_TX_DESC_DTYPE_DESC_DONE)) {
2182                 PMD_TX_LOG(DEBUG, "TX descriptor %4u is not done "
2183                            "(port=%d queue=%d)", desc_to_clean_to,
2184                            txq->port_id, txq->queue_id);
2185                 return -1;
2186         }
2187
2188         if (last_desc_cleaned > desc_to_clean_to)
2189                 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
2190                                                         desc_to_clean_to);
2191         else
2192                 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
2193                                         last_desc_cleaned);
2194
2195         txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
2196
2197         txq->last_desc_cleaned = desc_to_clean_to;
2198         txq->nb_free = (uint16_t)(txq->nb_free + nb_tx_to_clean);
2199
2200         return 0;
2201 }
2202
2203 /* Check if the context descriptor is needed for TX offloading */
2204 static inline uint16_t
2205 iavf_calc_context_desc(uint64_t flags, uint8_t vlan_flag)
2206 {
2207         if (flags & (RTE_MBUF_F_TX_TCP_SEG | RTE_MBUF_F_TX_UDP_SEG |
2208                         RTE_MBUF_F_TX_TUNNEL_MASK))
2209                 return 1;
2210         if (flags & RTE_MBUF_F_TX_VLAN &&
2211             vlan_flag & IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG2)
2212                 return 1;
2213         return 0;
2214 }
2215
2216 static inline void
2217 iavf_fill_ctx_desc_cmd_field(volatile uint64_t *field, struct rte_mbuf *m,
2218                 uint8_t vlan_flag)
2219 {
2220         uint64_t cmd = 0;
2221
2222         /* TSO enabled */
2223         if (m->ol_flags & (RTE_MBUF_F_TX_TCP_SEG | RTE_MBUF_F_TX_UDP_SEG))
2224                 cmd = IAVF_TX_CTX_DESC_TSO << IAVF_TXD_CTX_QW1_CMD_SHIFT;
2225
2226         if (m->ol_flags & RTE_MBUF_F_TX_VLAN &&
2227                         vlan_flag & IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG2) {
2228                 cmd |= IAVF_TX_CTX_DESC_IL2TAG2
2229                         << IAVF_TXD_CTX_QW1_CMD_SHIFT;
2230         }
2231
2232         *field |= cmd;
2233 }
2234
2235 static inline void
2236 iavf_fill_ctx_desc_ipsec_field(volatile uint64_t *field,
2237         struct iavf_ipsec_crypto_pkt_metadata *ipsec_md)
2238 {
2239         uint64_t ipsec_field =
2240                 (uint64_t)ipsec_md->ctx_desc_ipsec_params <<
2241                         IAVF_TXD_CTX_QW1_IPSEC_PARAMS_CIPHERBLK_SHIFT;
2242
2243         *field |= ipsec_field;
2244 }
2245
2246
2247 static inline void
2248 iavf_fill_ctx_desc_tunnelling_field(volatile uint64_t *qw0,
2249                 const struct rte_mbuf *m)
2250 {
2251         uint64_t eip_typ = IAVF_TX_CTX_DESC_EIPT_NONE;
2252         uint64_t eip_len = 0;
2253         uint64_t eip_noinc = 0;
2254         /* Default - IP_ID is increment in each segment of LSO */
2255
2256         switch (m->ol_flags & (RTE_MBUF_F_TX_OUTER_IPV4 |
2257                         RTE_MBUF_F_TX_OUTER_IPV6 |
2258                         RTE_MBUF_F_TX_OUTER_IP_CKSUM)) {
2259         case RTE_MBUF_F_TX_OUTER_IPV4:
2260                 eip_typ = IAVF_TX_CTX_DESC_EIPT_IPV4_NO_CHECKSUM_OFFLOAD;
2261                 eip_len = m->outer_l3_len >> 2;
2262         break;
2263         case RTE_MBUF_F_TX_OUTER_IPV4 | RTE_MBUF_F_TX_OUTER_IP_CKSUM:
2264                 eip_typ = IAVF_TX_CTX_DESC_EIPT_IPV4_CHECKSUM_OFFLOAD;
2265                 eip_len = m->outer_l3_len >> 2;
2266         break;
2267         case RTE_MBUF_F_TX_OUTER_IPV6:
2268                 eip_typ = IAVF_TX_CTX_DESC_EIPT_IPV6;
2269                 eip_len = m->outer_l3_len >> 2;
2270         break;
2271         }
2272
2273         *qw0 = eip_typ << IAVF_TXD_CTX_QW0_TUN_PARAMS_EIPT_SHIFT |
2274                 eip_len << IAVF_TXD_CTX_QW0_TUN_PARAMS_EIPLEN_SHIFT |
2275                 eip_noinc << IAVF_TXD_CTX_QW0_TUN_PARAMS_EIP_NOINC_SHIFT;
2276 }
2277
2278 static inline uint16_t
2279 iavf_fill_ctx_desc_segmentation_field(volatile uint64_t *field,
2280         struct rte_mbuf *m, struct iavf_ipsec_crypto_pkt_metadata *ipsec_md)
2281 {
2282         uint64_t segmentation_field = 0;
2283         uint64_t total_length = 0;
2284
2285         if (m->ol_flags & RTE_MBUF_F_TX_SEC_OFFLOAD) {
2286                 total_length = ipsec_md->l4_payload_len;
2287         } else {
2288                 total_length = m->pkt_len - (m->l2_len + m->l3_len + m->l4_len);
2289
2290                 if (m->ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK)
2291                         total_length -= m->outer_l3_len;
2292         }
2293
2294 #ifdef RTE_LIBRTE_IAVF_DEBUG_TX
2295         if (!m->l4_len || !m->tso_segsz)
2296                 PMD_TX_LOG(DEBUG, "L4 length %d, LSO Segment size %d",
2297                          m->l4_len, m->tso_segsz);
2298         if (m->tso_segsz < 88)
2299                 PMD_TX_LOG(DEBUG, "LSO Segment size %d is less than minimum %d",
2300                         m->tso_segsz, 88);
2301 #endif
2302         segmentation_field =
2303                 (((uint64_t)total_length << IAVF_TXD_CTX_QW1_TSO_LEN_SHIFT) &
2304                                 IAVF_TXD_CTX_QW1_TSO_LEN_MASK) |
2305                 (((uint64_t)m->tso_segsz << IAVF_TXD_CTX_QW1_MSS_SHIFT) &
2306                                 IAVF_TXD_CTX_QW1_MSS_MASK);
2307
2308         *field |= segmentation_field;
2309
2310         return total_length;
2311 }
2312
2313
2314 struct iavf_tx_context_desc_qws {
2315         __le64 qw0;
2316         __le64 qw1;
2317 };
2318
2319 static inline void
2320 iavf_fill_context_desc(volatile struct iavf_tx_context_desc *desc,
2321         struct rte_mbuf *m, struct iavf_ipsec_crypto_pkt_metadata *ipsec_md,
2322         uint16_t *tlen, uint8_t vlan_flag)
2323 {
2324         volatile struct iavf_tx_context_desc_qws *desc_qws =
2325                         (volatile struct iavf_tx_context_desc_qws *)desc;
2326         /* fill descriptor type field */
2327         desc_qws->qw1 = IAVF_TX_DESC_DTYPE_CONTEXT;
2328
2329         /* fill command field */
2330         iavf_fill_ctx_desc_cmd_field(&desc_qws->qw1, m, vlan_flag);
2331
2332         /* fill segmentation field */
2333         if (m->ol_flags & (RTE_MBUF_F_TX_TCP_SEG | RTE_MBUF_F_TX_UDP_SEG)) {
2334                 /* fill IPsec field */
2335                 if (m->ol_flags & RTE_MBUF_F_TX_SEC_OFFLOAD)
2336                         iavf_fill_ctx_desc_ipsec_field(&desc_qws->qw1,
2337                                 ipsec_md);
2338
2339                 *tlen = iavf_fill_ctx_desc_segmentation_field(&desc_qws->qw1,
2340                                 m, ipsec_md);
2341         }
2342
2343         /* fill tunnelling field */
2344         if (m->ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK)
2345                 iavf_fill_ctx_desc_tunnelling_field(&desc_qws->qw0, m);
2346         else
2347                 desc_qws->qw0 = 0;
2348
2349         desc_qws->qw0 = rte_cpu_to_le_64(desc_qws->qw0);
2350         desc_qws->qw1 = rte_cpu_to_le_64(desc_qws->qw1);
2351
2352         if (vlan_flag & IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG2)
2353                 desc->l2tag2 = m->vlan_tci;
2354 }
2355
2356
2357 static inline void
2358 iavf_fill_ipsec_desc(volatile struct iavf_tx_ipsec_desc *desc,
2359         const struct iavf_ipsec_crypto_pkt_metadata *md, uint16_t *ipsec_len)
2360 {
2361         desc->qw0 = rte_cpu_to_le_64(((uint64_t)md->l4_payload_len <<
2362                 IAVF_IPSEC_TX_DESC_QW0_L4PAYLEN_SHIFT) |
2363                 ((uint64_t)md->esn << IAVF_IPSEC_TX_DESC_QW0_IPSECESN_SHIFT) |
2364                 ((uint64_t)md->esp_trailer_len <<
2365                                 IAVF_IPSEC_TX_DESC_QW0_TRAILERLEN_SHIFT));
2366
2367         desc->qw1 = rte_cpu_to_le_64(((uint64_t)md->sa_idx <<
2368                 IAVF_IPSEC_TX_DESC_QW1_IPSECSA_SHIFT) |
2369                 ((uint64_t)md->next_proto <<
2370                                 IAVF_IPSEC_TX_DESC_QW1_IPSECNH_SHIFT) |
2371                 ((uint64_t)(md->len_iv & 0x3) <<
2372                                 IAVF_IPSEC_TX_DESC_QW1_IVLEN_SHIFT) |
2373                 ((uint64_t)(md->ol_flags & IAVF_IPSEC_CRYPTO_OL_FLAGS_NATT ?
2374                                 1ULL : 0ULL) <<
2375                                 IAVF_IPSEC_TX_DESC_QW1_UDP_SHIFT) |
2376                 (uint64_t)IAVF_TX_DESC_DTYPE_IPSEC);
2377
2378         /**
2379          * TODO: Pre-calculate this in the Session initialization
2380          *
2381          * Calculate IPsec length required in data descriptor func when TSO
2382          * offload is enabled
2383          */
2384         *ipsec_len = sizeof(struct rte_esp_hdr) + (md->len_iv >> 2) +
2385                         (md->ol_flags & IAVF_IPSEC_CRYPTO_OL_FLAGS_NATT ?
2386                         sizeof(struct rte_udp_hdr) : 0);
2387 }
2388
2389 static inline void
2390 iavf_build_data_desc_cmd_offset_fields(volatile uint64_t *qw1,
2391                 struct rte_mbuf *m, uint8_t vlan_flag)
2392 {
2393         uint64_t command = 0;
2394         uint64_t offset = 0;
2395         uint64_t l2tag1 = 0;
2396
2397         *qw1 = IAVF_TX_DESC_DTYPE_DATA;
2398
2399         command = (uint64_t)IAVF_TX_DESC_CMD_ICRC;
2400
2401         /* Descriptor based VLAN insertion */
2402         if ((vlan_flag & IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG1) &&
2403                         m->ol_flags & RTE_MBUF_F_TX_VLAN) {
2404                 command |= (uint64_t)IAVF_TX_DESC_CMD_IL2TAG1;
2405                 l2tag1 |= m->vlan_tci;
2406         }
2407
2408         /* Set MACLEN */
2409         offset |= (m->l2_len >> 1) << IAVF_TX_DESC_LENGTH_MACLEN_SHIFT;
2410
2411         /* Enable L3 checksum offloading inner */
2412         if (m->ol_flags & (RTE_MBUF_F_TX_IP_CKSUM | RTE_MBUF_F_TX_IPV4)) {
2413                 command |= IAVF_TX_DESC_CMD_IIPT_IPV4_CSUM;
2414                 offset |= (m->l3_len >> 2) << IAVF_TX_DESC_LENGTH_IPLEN_SHIFT;
2415         } else if (m->ol_flags & RTE_MBUF_F_TX_IPV4) {
2416                 command |= IAVF_TX_DESC_CMD_IIPT_IPV4;
2417                 offset |= (m->l3_len >> 2) << IAVF_TX_DESC_LENGTH_IPLEN_SHIFT;
2418         } else if (m->ol_flags & RTE_MBUF_F_TX_IPV6) {
2419                 command |= IAVF_TX_DESC_CMD_IIPT_IPV6;
2420                 offset |= (m->l3_len >> 2) << IAVF_TX_DESC_LENGTH_IPLEN_SHIFT;
2421         }
2422
2423         if (m->ol_flags & RTE_MBUF_F_TX_TCP_SEG) {
2424                 command |= IAVF_TX_DESC_CMD_L4T_EOFT_TCP;
2425                 offset |= (m->l4_len >> 2) <<
2426                               IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2427         }
2428
2429         /* Enable L4 checksum offloads */
2430         switch (m->ol_flags & RTE_MBUF_F_TX_L4_MASK) {
2431         case RTE_MBUF_F_TX_TCP_CKSUM:
2432                 command |= IAVF_TX_DESC_CMD_L4T_EOFT_TCP;
2433                 offset |= (sizeof(struct rte_tcp_hdr) >> 2) <<
2434                                 IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2435                 break;
2436         case RTE_MBUF_F_TX_SCTP_CKSUM:
2437                 command |= IAVF_TX_DESC_CMD_L4T_EOFT_SCTP;
2438                 offset |= (sizeof(struct rte_sctp_hdr) >> 2) <<
2439                                 IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2440                 break;
2441         case RTE_MBUF_F_TX_UDP_CKSUM:
2442                 command |= IAVF_TX_DESC_CMD_L4T_EOFT_UDP;
2443                 offset |= (sizeof(struct rte_udp_hdr) >> 2) <<
2444                                 IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2445                 break;
2446         }
2447
2448         *qw1 = rte_cpu_to_le_64((((uint64_t)command <<
2449                 IAVF_TXD_DATA_QW1_CMD_SHIFT) & IAVF_TXD_DATA_QW1_CMD_MASK) |
2450                 (((uint64_t)offset << IAVF_TXD_DATA_QW1_OFFSET_SHIFT) &
2451                 IAVF_TXD_DATA_QW1_OFFSET_MASK) |
2452                 ((uint64_t)l2tag1 << IAVF_TXD_DATA_QW1_L2TAG1_SHIFT));
2453 }
2454
2455 static inline void
2456 iavf_fill_data_desc(volatile struct iavf_tx_desc *desc,
2457         struct rte_mbuf *m, uint64_t desc_template,
2458         uint16_t tlen, uint16_t ipseclen)
2459 {
2460         uint32_t hdrlen = m->l2_len;
2461         uint32_t bufsz = 0;
2462
2463         /* fill data descriptor qw1 from template */
2464         desc->cmd_type_offset_bsz = desc_template;
2465
2466         /* set data buffer address */
2467         desc->buffer_addr = rte_mbuf_data_iova(m);
2468
2469         /* calculate data buffer size less set header lengths */
2470         if ((m->ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK) &&
2471                         (m->ol_flags & (RTE_MBUF_F_TX_TCP_SEG |
2472                                         RTE_MBUF_F_TX_UDP_SEG))) {
2473                 hdrlen += m->outer_l3_len;
2474                 if (m->ol_flags & RTE_MBUF_F_TX_L4_MASK)
2475                         hdrlen += m->l3_len + m->l4_len;
2476                 else
2477                         hdrlen += m->l3_len;
2478                 if (m->ol_flags & RTE_MBUF_F_TX_SEC_OFFLOAD)
2479                         hdrlen += ipseclen;
2480                 bufsz = hdrlen + tlen;
2481         } else if ((m->ol_flags & RTE_MBUF_F_TX_SEC_OFFLOAD) &&
2482                         (m->ol_flags & (RTE_MBUF_F_TX_TCP_SEG |
2483                                         RTE_MBUF_F_TX_UDP_SEG))) {
2484                 hdrlen += m->outer_l3_len + m->l3_len + ipseclen;
2485                 if (m->ol_flags & RTE_MBUF_F_TX_L4_MASK)
2486                         hdrlen += m->l4_len;
2487                 bufsz = hdrlen + tlen;
2488
2489         } else {
2490                 bufsz = m->data_len;
2491         }
2492
2493         /* set data buffer size */
2494         desc->cmd_type_offset_bsz |=
2495                 (((uint64_t)bufsz << IAVF_TXD_DATA_QW1_TX_BUF_SZ_SHIFT) &
2496                 IAVF_TXD_DATA_QW1_TX_BUF_SZ_MASK);
2497
2498         desc->buffer_addr = rte_cpu_to_le_64(desc->buffer_addr);
2499         desc->cmd_type_offset_bsz = rte_cpu_to_le_64(desc->cmd_type_offset_bsz);
2500 }
2501
2502
2503 static struct iavf_ipsec_crypto_pkt_metadata *
2504 iavf_ipsec_crypto_get_pkt_metadata(const struct iavf_tx_queue *txq,
2505                 struct rte_mbuf *m)
2506 {
2507         if (m->ol_flags & RTE_MBUF_F_TX_SEC_OFFLOAD)
2508                 return RTE_MBUF_DYNFIELD(m, txq->ipsec_crypto_pkt_md_offset,
2509                                 struct iavf_ipsec_crypto_pkt_metadata *);
2510
2511         return NULL;
2512 }
2513
2514 /* TX function */
2515 uint16_t
2516 iavf_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2517 {
2518         struct iavf_tx_queue *txq = tx_queue;
2519         volatile struct iavf_tx_desc *txr = txq->tx_ring;
2520         struct iavf_tx_entry *txe_ring = txq->sw_ring;
2521         struct iavf_tx_entry *txe, *txn;
2522         struct rte_mbuf *mb, *mb_seg;
2523         uint16_t desc_idx, desc_idx_last;
2524         uint16_t idx;
2525
2526
2527         /* Check if the descriptor ring needs to be cleaned. */
2528         if (txq->nb_free < txq->free_thresh)
2529                 iavf_xmit_cleanup(txq);
2530
2531         desc_idx = txq->tx_tail;
2532         txe = &txe_ring[desc_idx];
2533
2534 #ifdef RTE_LIBRTE_IAVF_DEBUG_TX_DESC_RING
2535                 iavf_dump_tx_entry_ring(txq);
2536                 iavf_dump_tx_desc_ring(txq);
2537 #endif
2538
2539
2540         for (idx = 0; idx < nb_pkts; idx++) {
2541                 volatile struct iavf_tx_desc *ddesc;
2542                 struct iavf_ipsec_crypto_pkt_metadata *ipsec_md;
2543
2544                 uint16_t nb_desc_ctx, nb_desc_ipsec;
2545                 uint16_t nb_desc_data, nb_desc_required;
2546                 uint16_t tlen = 0, ipseclen = 0;
2547                 uint64_t ddesc_template = 0;
2548                 uint64_t ddesc_cmd = 0;
2549
2550                 mb = tx_pkts[idx];
2551
2552                 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
2553
2554                 /**
2555                  * Get metadata for ipsec crypto from mbuf dynamic fields if
2556                  * security offload is specified.
2557                  */
2558                 ipsec_md = iavf_ipsec_crypto_get_pkt_metadata(txq, mb);
2559
2560                 nb_desc_data = mb->nb_segs;
2561                 nb_desc_ctx =
2562                         iavf_calc_context_desc(mb->ol_flags, txq->vlan_flag);
2563                 nb_desc_ipsec = !!(mb->ol_flags & RTE_MBUF_F_TX_SEC_OFFLOAD);
2564
2565                 /**
2566                  * The number of descriptors that must be allocated for
2567                  * a packet equals to the number of the segments of that
2568                  * packet plus the context and ipsec descriptors if needed.
2569                  */
2570                 nb_desc_required = nb_desc_data + nb_desc_ctx + nb_desc_ipsec;
2571
2572                 desc_idx_last = (uint16_t)(desc_idx + nb_desc_required - 1);
2573
2574                 /* wrap descriptor ring */
2575                 if (desc_idx_last >= txq->nb_tx_desc)
2576                         desc_idx_last =
2577                                 (uint16_t)(desc_idx_last - txq->nb_tx_desc);
2578
2579                 PMD_TX_LOG(DEBUG,
2580                         "port_id=%u queue_id=%u tx_first=%u tx_last=%u",
2581                         txq->port_id, txq->queue_id, desc_idx, desc_idx_last);
2582
2583                 if (nb_desc_required > txq->nb_free) {
2584                         if (iavf_xmit_cleanup(txq)) {
2585                                 if (idx == 0)
2586                                         return 0;
2587                                 goto end_of_tx;
2588                         }
2589                         if (unlikely(nb_desc_required > txq->rs_thresh)) {
2590                                 while (nb_desc_required > txq->nb_free) {
2591                                         if (iavf_xmit_cleanup(txq)) {
2592                                                 if (idx == 0)
2593                                                         return 0;
2594                                                 goto end_of_tx;
2595                                         }
2596                                 }
2597                         }
2598                 }
2599
2600                 iavf_build_data_desc_cmd_offset_fields(&ddesc_template, mb,
2601                         txq->vlan_flag);
2602
2603                         /* Setup TX context descriptor if required */
2604                 if (nb_desc_ctx) {
2605                         volatile struct iavf_tx_context_desc *ctx_desc =
2606                                 (volatile struct iavf_tx_context_desc *)
2607                                         &txr[desc_idx];
2608
2609                         /* clear QW0 or the previous writeback value
2610                          * may impact next write
2611                          */
2612                         *(volatile uint64_t *)ctx_desc = 0;
2613
2614                         txn = &txe_ring[txe->next_id];
2615                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
2616
2617                         if (txe->mbuf) {
2618                                 rte_pktmbuf_free_seg(txe->mbuf);
2619                                 txe->mbuf = NULL;
2620                         }
2621
2622                         iavf_fill_context_desc(ctx_desc, mb, ipsec_md, &tlen,
2623                                 txq->vlan_flag);
2624                         IAVF_DUMP_TX_DESC(txq, ctx_desc, desc_idx);
2625
2626                         txe->last_id = desc_idx_last;
2627                         desc_idx = txe->next_id;
2628                         txe = txn;
2629                         }
2630
2631                 if (nb_desc_ipsec) {
2632                         volatile struct iavf_tx_ipsec_desc *ipsec_desc =
2633                                 (volatile struct iavf_tx_ipsec_desc *)
2634                                         &txr[desc_idx];
2635
2636                         txn = &txe_ring[txe->next_id];
2637                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
2638
2639                         if (txe->mbuf) {
2640                                 rte_pktmbuf_free_seg(txe->mbuf);
2641                                 txe->mbuf = NULL;
2642                 }
2643
2644                         iavf_fill_ipsec_desc(ipsec_desc, ipsec_md, &ipseclen);
2645
2646                         IAVF_DUMP_TX_DESC(txq, ipsec_desc, desc_idx);
2647
2648                         txe->last_id = desc_idx_last;
2649                         desc_idx = txe->next_id;
2650                         txe = txn;
2651                 }
2652
2653                 mb_seg = mb;
2654
2655                 do {
2656                         ddesc = (volatile struct iavf_tx_desc *)
2657                                         &txr[desc_idx];
2658
2659                         txn = &txe_ring[txe->next_id];
2660                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
2661
2662                         if (txe->mbuf)
2663                                 rte_pktmbuf_free_seg(txe->mbuf);
2664
2665                         txe->mbuf = mb_seg;
2666                         iavf_fill_data_desc(ddesc, mb_seg,
2667                                         ddesc_template, tlen, ipseclen);
2668
2669                         IAVF_DUMP_TX_DESC(txq, ddesc, desc_idx);
2670
2671                         txe->last_id = desc_idx_last;
2672                         desc_idx = txe->next_id;
2673                         txe = txn;
2674                         mb_seg = mb_seg->next;
2675                 } while (mb_seg);
2676
2677                 /* The last packet data descriptor needs End Of Packet (EOP) */
2678                 ddesc_cmd = IAVF_TX_DESC_CMD_EOP;
2679
2680                 txq->nb_used = (uint16_t)(txq->nb_used + nb_desc_required);
2681                 txq->nb_free = (uint16_t)(txq->nb_free - nb_desc_required);
2682
2683                 if (txq->nb_used >= txq->rs_thresh) {
2684                         PMD_TX_LOG(DEBUG, "Setting RS bit on TXD id="
2685                                    "%4u (port=%d queue=%d)",
2686                                    desc_idx_last, txq->port_id, txq->queue_id);
2687
2688                         ddesc_cmd |= IAVF_TX_DESC_CMD_RS;
2689
2690                         /* Update txq RS bit counters */
2691                         txq->nb_used = 0;
2692                 }
2693
2694                 ddesc->cmd_type_offset_bsz |= rte_cpu_to_le_64(ddesc_cmd <<
2695                                 IAVF_TXD_DATA_QW1_CMD_SHIFT);
2696
2697                 IAVF_DUMP_TX_DESC(txq, ddesc, desc_idx - 1);
2698         }
2699
2700 end_of_tx:
2701         rte_wmb();
2702
2703         PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
2704                    txq->port_id, txq->queue_id, desc_idx, idx);
2705
2706         IAVF_PCI_REG_WRITE_RELAXED(txq->qtx_tail, desc_idx);
2707         txq->tx_tail = desc_idx;
2708
2709         return idx;
2710 }
2711
2712 /* Check if the packet with vlan user priority is transmitted in the
2713  * correct queue.
2714  */
2715 static int
2716 iavf_check_vlan_up2tc(struct iavf_tx_queue *txq, struct rte_mbuf *m)
2717 {
2718         struct rte_eth_dev *dev = &rte_eth_devices[txq->port_id];
2719         struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2720         uint16_t up;
2721
2722         up = m->vlan_tci >> IAVF_VLAN_TAG_PCP_OFFSET;
2723
2724         if (!(vf->qos_cap->cap[txq->tc].tc_prio & BIT(up))) {
2725                 PMD_TX_LOG(ERR, "packet with vlan pcp %u cannot transmit in queue %u\n",
2726                         up, txq->queue_id);
2727                 return -1;
2728         } else {
2729                 return 0;
2730         }
2731 }
2732
2733 /* TX prep functions */
2734 uint16_t
2735 iavf_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
2736               uint16_t nb_pkts)
2737 {
2738         int i, ret;
2739         uint64_t ol_flags;
2740         struct rte_mbuf *m;
2741         struct iavf_tx_queue *txq = tx_queue;
2742         struct rte_eth_dev *dev = &rte_eth_devices[txq->port_id];
2743         struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2744
2745         for (i = 0; i < nb_pkts; i++) {
2746                 m = tx_pkts[i];
2747                 ol_flags = m->ol_flags;
2748
2749                 /* Check condition for nb_segs > IAVF_TX_MAX_MTU_SEG. */
2750                 if (!(ol_flags & RTE_MBUF_F_TX_TCP_SEG)) {
2751                         if (m->nb_segs > IAVF_TX_MAX_MTU_SEG) {
2752                                 rte_errno = EINVAL;
2753                                 return i;
2754                         }
2755                 } else if ((m->tso_segsz < IAVF_MIN_TSO_MSS) ||
2756                            (m->tso_segsz > IAVF_MAX_TSO_MSS)) {
2757                         /* MSS outside the range are considered malicious */
2758                         rte_errno = EINVAL;
2759                         return i;
2760                 }
2761
2762                 if (ol_flags & IAVF_TX_OFFLOAD_NOTSUP_MASK) {
2763                         rte_errno = ENOTSUP;
2764                         return i;
2765                 }
2766
2767 #ifdef RTE_ETHDEV_DEBUG_TX
2768                 ret = rte_validate_tx_offload(m);
2769                 if (ret != 0) {
2770                         rte_errno = -ret;
2771                         return i;
2772                 }
2773 #endif
2774                 ret = rte_net_intel_cksum_prepare(m);
2775                 if (ret != 0) {
2776                         rte_errno = -ret;
2777                         return i;
2778                 }
2779
2780                 if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_QOS &&
2781                     ol_flags & (RTE_MBUF_F_RX_VLAN_STRIPPED | RTE_MBUF_F_RX_VLAN)) {
2782                         ret = iavf_check_vlan_up2tc(txq, m);
2783                         if (ret != 0) {
2784                                 rte_errno = -ret;
2785                                 return i;
2786                         }
2787                 }
2788         }
2789
2790         return i;
2791 }
2792
2793 /* choose rx function*/
2794 void
2795 iavf_set_rx_function(struct rte_eth_dev *dev)
2796 {
2797         struct iavf_adapter *adapter =
2798                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2799         struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2800
2801 #ifdef RTE_ARCH_X86
2802         struct iavf_rx_queue *rxq;
2803         int i;
2804         int check_ret;
2805         bool use_avx2 = false;
2806         bool use_avx512 = false;
2807         bool use_flex = false;
2808
2809         check_ret = iavf_rx_vec_dev_check(dev);
2810         if (check_ret >= 0 &&
2811             rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
2812                 if ((rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
2813                      rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) &&
2814                     rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256)
2815                         use_avx2 = true;
2816
2817 #ifdef CC_AVX512_SUPPORT
2818                 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 &&
2819                     rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1 &&
2820                     rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512)
2821                         use_avx512 = true;
2822 #endif
2823
2824                 if (vf->vf_res->vf_cap_flags &
2825                         VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC)
2826                         use_flex = true;
2827
2828                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2829                         rxq = dev->data->rx_queues[i];
2830                         (void)iavf_rxq_vec_setup(rxq);
2831                 }
2832
2833                 if (dev->data->scattered_rx) {
2834                         if (!use_avx512) {
2835                                 PMD_DRV_LOG(DEBUG,
2836                                             "Using %sVector Scattered Rx (port %d).",
2837                                             use_avx2 ? "avx2 " : "",
2838                                             dev->data->port_id);
2839                         } else {
2840                                 if (check_ret == IAVF_VECTOR_PATH)
2841                                         PMD_DRV_LOG(DEBUG,
2842                                                     "Using AVX512 Vector Scattered Rx (port %d).",
2843                                                     dev->data->port_id);
2844                                 else
2845                                         PMD_DRV_LOG(DEBUG,
2846                                                     "Using AVX512 OFFLOAD Vector Scattered Rx (port %d).",
2847                                                     dev->data->port_id);
2848                         }
2849                         if (use_flex) {
2850                                 dev->rx_pkt_burst = use_avx2 ?
2851                                         iavf_recv_scattered_pkts_vec_avx2_flex_rxd :
2852                                         iavf_recv_scattered_pkts_vec_flex_rxd;
2853 #ifdef CC_AVX512_SUPPORT
2854                                 if (use_avx512) {
2855                                         if (check_ret == IAVF_VECTOR_PATH)
2856                                                 dev->rx_pkt_burst =
2857                                                         iavf_recv_scattered_pkts_vec_avx512_flex_rxd;
2858                                         else
2859                                                 dev->rx_pkt_burst =
2860                                                         iavf_recv_scattered_pkts_vec_avx512_flex_rxd_offload;
2861                                 }
2862 #endif
2863                         } else {
2864                                 dev->rx_pkt_burst = use_avx2 ?
2865                                         iavf_recv_scattered_pkts_vec_avx2 :
2866                                         iavf_recv_scattered_pkts_vec;
2867 #ifdef CC_AVX512_SUPPORT
2868                                 if (use_avx512) {
2869                                         if (check_ret == IAVF_VECTOR_PATH)
2870                                                 dev->rx_pkt_burst =
2871                                                         iavf_recv_scattered_pkts_vec_avx512;
2872                                         else
2873                                                 dev->rx_pkt_burst =
2874                                                         iavf_recv_scattered_pkts_vec_avx512_offload;
2875                                 }
2876 #endif
2877                         }
2878                 } else {
2879                         if (!use_avx512) {
2880                                 PMD_DRV_LOG(DEBUG, "Using %sVector Rx (port %d).",
2881                                             use_avx2 ? "avx2 " : "",
2882                                             dev->data->port_id);
2883                         } else {
2884                                 if (check_ret == IAVF_VECTOR_PATH)
2885                                         PMD_DRV_LOG(DEBUG,
2886                                                     "Using AVX512 Vector Rx (port %d).",
2887                                                     dev->data->port_id);
2888                                 else
2889                                         PMD_DRV_LOG(DEBUG,
2890                                                     "Using AVX512 OFFLOAD Vector Rx (port %d).",
2891                                                     dev->data->port_id);
2892                         }
2893                         if (use_flex) {
2894                                 dev->rx_pkt_burst = use_avx2 ?
2895                                         iavf_recv_pkts_vec_avx2_flex_rxd :
2896                                         iavf_recv_pkts_vec_flex_rxd;
2897 #ifdef CC_AVX512_SUPPORT
2898                                 if (use_avx512) {
2899                                         if (check_ret == IAVF_VECTOR_PATH)
2900                                                 dev->rx_pkt_burst =
2901                                                         iavf_recv_pkts_vec_avx512_flex_rxd;
2902                                         else
2903                                                 dev->rx_pkt_burst =
2904                                                         iavf_recv_pkts_vec_avx512_flex_rxd_offload;
2905                                 }
2906 #endif
2907                         } else {
2908                                 dev->rx_pkt_burst = use_avx2 ?
2909                                         iavf_recv_pkts_vec_avx2 :
2910                                         iavf_recv_pkts_vec;
2911 #ifdef CC_AVX512_SUPPORT
2912                                 if (use_avx512) {
2913                                         if (check_ret == IAVF_VECTOR_PATH)
2914                                                 dev->rx_pkt_burst =
2915                                                         iavf_recv_pkts_vec_avx512;
2916                                         else
2917                                                 dev->rx_pkt_burst =
2918                                                         iavf_recv_pkts_vec_avx512_offload;
2919                                 }
2920 #endif
2921                         }
2922                 }
2923
2924                 return;
2925         }
2926
2927 #endif
2928         if (dev->data->scattered_rx) {
2929                 PMD_DRV_LOG(DEBUG, "Using a Scattered Rx callback (port=%d).",
2930                             dev->data->port_id);
2931                 if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC)
2932                         dev->rx_pkt_burst = iavf_recv_scattered_pkts_flex_rxd;
2933                 else
2934                         dev->rx_pkt_burst = iavf_recv_scattered_pkts;
2935         } else if (adapter->rx_bulk_alloc_allowed) {
2936                 PMD_DRV_LOG(DEBUG, "Using bulk Rx callback (port=%d).",
2937                             dev->data->port_id);
2938                 dev->rx_pkt_burst = iavf_recv_pkts_bulk_alloc;
2939         } else {
2940                 PMD_DRV_LOG(DEBUG, "Using Basic Rx callback (port=%d).",
2941                             dev->data->port_id);
2942                 if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC)
2943                         dev->rx_pkt_burst = iavf_recv_pkts_flex_rxd;
2944                 else
2945                         dev->rx_pkt_burst = iavf_recv_pkts;
2946         }
2947 }
2948
2949 /* choose tx function*/
2950 void
2951 iavf_set_tx_function(struct rte_eth_dev *dev)
2952 {
2953 #ifdef RTE_ARCH_X86
2954         struct iavf_tx_queue *txq;
2955         int i;
2956         int check_ret;
2957         bool use_sse = false;
2958         bool use_avx2 = false;
2959         bool use_avx512 = false;
2960
2961         check_ret = iavf_tx_vec_dev_check(dev);
2962
2963         if (check_ret >= 0 &&
2964             rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
2965                 /* SSE and AVX2 not support offload path yet. */
2966                 if (check_ret == IAVF_VECTOR_PATH) {
2967                         use_sse = true;
2968                         if ((rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
2969                              rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) &&
2970                             rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256)
2971                                 use_avx2 = true;
2972                 }
2973 #ifdef CC_AVX512_SUPPORT
2974                 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 &&
2975                     rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1 &&
2976                     rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512)
2977                         use_avx512 = true;
2978 #endif
2979
2980                 if (!use_sse && !use_avx2 && !use_avx512)
2981                         goto normal;
2982
2983                 if (!use_avx512) {
2984                         PMD_DRV_LOG(DEBUG, "Using %sVector Tx (port %d).",
2985                                     use_avx2 ? "avx2 " : "",
2986                                     dev->data->port_id);
2987                         dev->tx_pkt_burst = use_avx2 ?
2988                                             iavf_xmit_pkts_vec_avx2 :
2989                                             iavf_xmit_pkts_vec;
2990                 }
2991                 dev->tx_pkt_prepare = NULL;
2992 #ifdef CC_AVX512_SUPPORT
2993                 if (use_avx512) {
2994                         if (check_ret == IAVF_VECTOR_PATH) {
2995                                 dev->tx_pkt_burst = iavf_xmit_pkts_vec_avx512;
2996                                 PMD_DRV_LOG(DEBUG, "Using AVX512 Vector Tx (port %d).",
2997                                             dev->data->port_id);
2998                         } else {
2999                                 dev->tx_pkt_burst = iavf_xmit_pkts_vec_avx512_offload;
3000                                 dev->tx_pkt_prepare = iavf_prep_pkts;
3001                                 PMD_DRV_LOG(DEBUG, "Using AVX512 OFFLOAD Vector Tx (port %d).",
3002                                             dev->data->port_id);
3003                         }
3004                 }
3005 #endif
3006
3007                 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3008                         txq = dev->data->tx_queues[i];
3009                         if (!txq)
3010                                 continue;
3011 #ifdef CC_AVX512_SUPPORT
3012                         if (use_avx512)
3013                                 iavf_txq_vec_setup_avx512(txq);
3014                         else
3015                                 iavf_txq_vec_setup(txq);
3016 #else
3017                         iavf_txq_vec_setup(txq);
3018 #endif
3019                 }
3020
3021                 return;
3022         }
3023
3024 normal:
3025 #endif
3026         PMD_DRV_LOG(DEBUG, "Using Basic Tx callback (port=%d).",
3027                     dev->data->port_id);
3028         dev->tx_pkt_burst = iavf_xmit_pkts;
3029         dev->tx_pkt_prepare = iavf_prep_pkts;
3030 }
3031
3032 static int
3033 iavf_tx_done_cleanup_full(struct iavf_tx_queue *txq,
3034                         uint32_t free_cnt)
3035 {
3036         struct iavf_tx_entry *swr_ring = txq->sw_ring;
3037         uint16_t i, tx_last, tx_id;
3038         uint16_t nb_tx_free_last;
3039         uint16_t nb_tx_to_clean;
3040         uint32_t pkt_cnt;
3041
3042         /* Start free mbuf from the next of tx_tail */
3043         tx_last = txq->tx_tail;
3044         tx_id  = swr_ring[tx_last].next_id;
3045
3046         if (txq->nb_free == 0 && iavf_xmit_cleanup(txq))
3047                 return 0;
3048
3049         nb_tx_to_clean = txq->nb_free;
3050         nb_tx_free_last = txq->nb_free;
3051         if (!free_cnt)
3052                 free_cnt = txq->nb_tx_desc;
3053
3054         /* Loop through swr_ring to count the amount of
3055          * freeable mubfs and packets.
3056          */
3057         for (pkt_cnt = 0; pkt_cnt < free_cnt; ) {
3058                 for (i = 0; i < nb_tx_to_clean &&
3059                         pkt_cnt < free_cnt &&
3060                         tx_id != tx_last; i++) {
3061                         if (swr_ring[tx_id].mbuf != NULL) {
3062                                 rte_pktmbuf_free_seg(swr_ring[tx_id].mbuf);
3063                                 swr_ring[tx_id].mbuf = NULL;
3064
3065                                 /*
3066                                  * last segment in the packet,
3067                                  * increment packet count
3068                                  */
3069                                 pkt_cnt += (swr_ring[tx_id].last_id == tx_id);
3070                         }
3071
3072                         tx_id = swr_ring[tx_id].next_id;
3073                 }
3074
3075                 if (txq->rs_thresh > txq->nb_tx_desc -
3076                         txq->nb_free || tx_id == tx_last)
3077                         break;
3078
3079                 if (pkt_cnt < free_cnt) {
3080                         if (iavf_xmit_cleanup(txq))
3081                                 break;
3082
3083                         nb_tx_to_clean = txq->nb_free - nb_tx_free_last;
3084                         nb_tx_free_last = txq->nb_free;
3085                 }
3086         }
3087
3088         return (int)pkt_cnt;
3089 }
3090
3091 int
3092 iavf_dev_tx_done_cleanup(void *txq, uint32_t free_cnt)
3093 {
3094         struct iavf_tx_queue *q = (struct iavf_tx_queue *)txq;
3095
3096         return iavf_tx_done_cleanup_full(q, free_cnt);
3097 }
3098
3099 void
3100 iavf_dev_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
3101                      struct rte_eth_rxq_info *qinfo)
3102 {
3103         struct iavf_rx_queue *rxq;
3104
3105         rxq = dev->data->rx_queues[queue_id];
3106
3107         qinfo->mp = rxq->mp;
3108         qinfo->scattered_rx = dev->data->scattered_rx;
3109         qinfo->nb_desc = rxq->nb_rx_desc;
3110
3111         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
3112         qinfo->conf.rx_drop_en = true;
3113         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
3114 }
3115
3116 void
3117 iavf_dev_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
3118                      struct rte_eth_txq_info *qinfo)
3119 {
3120         struct iavf_tx_queue *txq;
3121
3122         txq = dev->data->tx_queues[queue_id];
3123
3124         qinfo->nb_desc = txq->nb_tx_desc;
3125
3126         qinfo->conf.tx_free_thresh = txq->free_thresh;
3127         qinfo->conf.tx_rs_thresh = txq->rs_thresh;
3128         qinfo->conf.offloads = txq->offloads;
3129         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
3130 }
3131
3132 /* Get the number of used descriptors of a rx queue */
3133 uint32_t
3134 iavf_dev_rxq_count(void *rx_queue)
3135 {
3136 #define IAVF_RXQ_SCAN_INTERVAL 4
3137         volatile union iavf_rx_desc *rxdp;
3138         struct iavf_rx_queue *rxq;
3139         uint16_t desc = 0;
3140
3141         rxq = rx_queue;
3142         rxdp = &rxq->rx_ring[rxq->rx_tail];
3143
3144         while ((desc < rxq->nb_rx_desc) &&
3145                ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
3146                  IAVF_RXD_QW1_STATUS_MASK) >> IAVF_RXD_QW1_STATUS_SHIFT) &
3147                (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)) {
3148                 /* Check the DD bit of a rx descriptor of each 4 in a group,
3149                  * to avoid checking too frequently and downgrading performance
3150                  * too much.
3151                  */
3152                 desc += IAVF_RXQ_SCAN_INTERVAL;
3153                 rxdp += IAVF_RXQ_SCAN_INTERVAL;
3154                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
3155                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
3156                                         desc - rxq->nb_rx_desc]);
3157         }
3158
3159         return desc;
3160 }
3161
3162 int
3163 iavf_dev_rx_desc_status(void *rx_queue, uint16_t offset)
3164 {
3165         struct iavf_rx_queue *rxq = rx_queue;
3166         volatile uint64_t *status;
3167         uint64_t mask;
3168         uint32_t desc;
3169
3170         if (unlikely(offset >= rxq->nb_rx_desc))
3171                 return -EINVAL;
3172
3173         if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
3174                 return RTE_ETH_RX_DESC_UNAVAIL;
3175
3176         desc = rxq->rx_tail + offset;
3177         if (desc >= rxq->nb_rx_desc)
3178                 desc -= rxq->nb_rx_desc;
3179
3180         status = &rxq->rx_ring[desc].wb.qword1.status_error_len;
3181         mask = rte_le_to_cpu_64((1ULL << IAVF_RX_DESC_STATUS_DD_SHIFT)
3182                 << IAVF_RXD_QW1_STATUS_SHIFT);
3183         if (*status & mask)
3184                 return RTE_ETH_RX_DESC_DONE;
3185
3186         return RTE_ETH_RX_DESC_AVAIL;
3187 }
3188
3189 int
3190 iavf_dev_tx_desc_status(void *tx_queue, uint16_t offset)
3191 {
3192         struct iavf_tx_queue *txq = tx_queue;
3193         volatile uint64_t *status;
3194         uint64_t mask, expect;
3195         uint32_t desc;
3196
3197         if (unlikely(offset >= txq->nb_tx_desc))
3198                 return -EINVAL;
3199
3200         desc = txq->tx_tail + offset;
3201         /* go to next desc that has the RS bit */
3202         desc = ((desc + txq->rs_thresh - 1) / txq->rs_thresh) *
3203                 txq->rs_thresh;
3204         if (desc >= txq->nb_tx_desc) {
3205                 desc -= txq->nb_tx_desc;
3206                 if (desc >= txq->nb_tx_desc)
3207                         desc -= txq->nb_tx_desc;
3208         }
3209
3210         status = &txq->tx_ring[desc].cmd_type_offset_bsz;
3211         mask = rte_le_to_cpu_64(IAVF_TXD_QW1_DTYPE_MASK);
3212         expect = rte_cpu_to_le_64(
3213                  IAVF_TX_DESC_DTYPE_DESC_DONE << IAVF_TXD_QW1_DTYPE_SHIFT);
3214         if ((*status & mask) == expect)
3215                 return RTE_ETH_TX_DESC_DONE;
3216
3217         return RTE_ETH_TX_DESC_FULL;
3218 }
3219
3220 static inline uint32_t
3221 iavf_get_default_ptype(uint16_t ptype)
3222 {
3223         static const uint32_t ptype_tbl[IAVF_MAX_PKT_TYPE]
3224                 __rte_cache_aligned = {
3225                 /* L2 types */
3226                 /* [0] reserved */
3227                 [1] = RTE_PTYPE_L2_ETHER,
3228                 [2] = RTE_PTYPE_L2_ETHER_TIMESYNC,
3229                 /* [3] - [5] reserved */
3230                 [6] = RTE_PTYPE_L2_ETHER_LLDP,
3231                 /* [7] - [10] reserved */
3232                 [11] = RTE_PTYPE_L2_ETHER_ARP,
3233                 /* [12] - [21] reserved */
3234
3235                 /* Non tunneled IPv4 */
3236                 [22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3237                        RTE_PTYPE_L4_FRAG,
3238                 [23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3239                        RTE_PTYPE_L4_NONFRAG,
3240                 [24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3241                        RTE_PTYPE_L4_UDP,
3242                 /* [25] reserved */
3243                 [26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3244                        RTE_PTYPE_L4_TCP,
3245                 [27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3246                        RTE_PTYPE_L4_SCTP,
3247                 [28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3248                        RTE_PTYPE_L4_ICMP,
3249
3250                 /* IPv4 --> IPv4 */
3251                 [29] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3252                        RTE_PTYPE_TUNNEL_IP |
3253                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3254                        RTE_PTYPE_INNER_L4_FRAG,
3255                 [30] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3256                        RTE_PTYPE_TUNNEL_IP |
3257                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3258                        RTE_PTYPE_INNER_L4_NONFRAG,
3259                 [31] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3260                        RTE_PTYPE_TUNNEL_IP |
3261                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3262                        RTE_PTYPE_INNER_L4_UDP,
3263                 /* [32] reserved */
3264                 [33] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3265                        RTE_PTYPE_TUNNEL_IP |
3266                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3267                        RTE_PTYPE_INNER_L4_TCP,
3268                 [34] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3269                        RTE_PTYPE_TUNNEL_IP |
3270                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3271                        RTE_PTYPE_INNER_L4_SCTP,
3272                 [35] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3273                        RTE_PTYPE_TUNNEL_IP |
3274                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3275                        RTE_PTYPE_INNER_L4_ICMP,
3276
3277                 /* IPv4 --> IPv6 */
3278                 [36] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3279                        RTE_PTYPE_TUNNEL_IP |
3280                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3281                        RTE_PTYPE_INNER_L4_FRAG,
3282                 [37] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3283                        RTE_PTYPE_TUNNEL_IP |
3284                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3285                        RTE_PTYPE_INNER_L4_NONFRAG,
3286                 [38] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3287                        RTE_PTYPE_TUNNEL_IP |
3288                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3289                        RTE_PTYPE_INNER_L4_UDP,
3290                 /* [39] reserved */
3291                 [40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3292                        RTE_PTYPE_TUNNEL_IP |
3293                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3294                        RTE_PTYPE_INNER_L4_TCP,
3295                 [41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3296                        RTE_PTYPE_TUNNEL_IP |
3297                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3298                        RTE_PTYPE_INNER_L4_SCTP,
3299                 [42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3300                        RTE_PTYPE_TUNNEL_IP |
3301                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3302                        RTE_PTYPE_INNER_L4_ICMP,
3303
3304                 /* IPv4 --> GRE/Teredo/VXLAN */
3305                 [43] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3306                        RTE_PTYPE_TUNNEL_GRENAT,
3307
3308                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv4 */
3309                 [44] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3310                        RTE_PTYPE_TUNNEL_GRENAT |
3311                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3312                        RTE_PTYPE_INNER_L4_FRAG,
3313                 [45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3314                        RTE_PTYPE_TUNNEL_GRENAT |
3315                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3316                        RTE_PTYPE_INNER_L4_NONFRAG,
3317                 [46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3318                        RTE_PTYPE_TUNNEL_GRENAT |
3319                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3320                        RTE_PTYPE_INNER_L4_UDP,
3321                 /* [47] reserved */
3322                 [48] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3323                        RTE_PTYPE_TUNNEL_GRENAT |
3324                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3325                        RTE_PTYPE_INNER_L4_TCP,
3326                 [49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3327                        RTE_PTYPE_TUNNEL_GRENAT |
3328                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3329                        RTE_PTYPE_INNER_L4_SCTP,
3330                 [50] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3331                        RTE_PTYPE_TUNNEL_GRENAT |
3332                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3333                        RTE_PTYPE_INNER_L4_ICMP,
3334
3335                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv6 */
3336                 [51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3337                        RTE_PTYPE_TUNNEL_GRENAT |
3338                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3339                        RTE_PTYPE_INNER_L4_FRAG,
3340                 [52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3341                        RTE_PTYPE_TUNNEL_GRENAT |
3342                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3343                        RTE_PTYPE_INNER_L4_NONFRAG,
3344                 [53] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3345                        RTE_PTYPE_TUNNEL_GRENAT |
3346                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3347                        RTE_PTYPE_INNER_L4_UDP,
3348                 /* [54] reserved */
3349                 [55] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3350                        RTE_PTYPE_TUNNEL_GRENAT |
3351                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3352                        RTE_PTYPE_INNER_L4_TCP,
3353                 [56] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3354                        RTE_PTYPE_TUNNEL_GRENAT |
3355                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3356                        RTE_PTYPE_INNER_L4_SCTP,
3357                 [57] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3358                        RTE_PTYPE_TUNNEL_GRENAT |
3359                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3360                        RTE_PTYPE_INNER_L4_ICMP,
3361
3362                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC */
3363                 [58] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3364                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
3365
3366                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
3367                 [59] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3368                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3369                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3370                        RTE_PTYPE_INNER_L4_FRAG,
3371                 [60] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3372                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3373                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3374                        RTE_PTYPE_INNER_L4_NONFRAG,
3375                 [61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3376                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3377                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3378                        RTE_PTYPE_INNER_L4_UDP,
3379                 /* [62] reserved */
3380                 [63] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3381                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3382                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3383                        RTE_PTYPE_INNER_L4_TCP,
3384                 [64] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3385                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3386                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3387                        RTE_PTYPE_INNER_L4_SCTP,
3388                 [65] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3389                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3390                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3391                        RTE_PTYPE_INNER_L4_ICMP,
3392
3393                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
3394                 [66] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3395                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3396                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3397                        RTE_PTYPE_INNER_L4_FRAG,
3398                 [67] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3399                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3400                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3401                        RTE_PTYPE_INNER_L4_NONFRAG,
3402                 [68] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3403                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3404                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3405                        RTE_PTYPE_INNER_L4_UDP,
3406                 /* [69] reserved */
3407                 [70] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3408                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3409                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3410                        RTE_PTYPE_INNER_L4_TCP,
3411                 [71] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3412                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3413                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3414                        RTE_PTYPE_INNER_L4_SCTP,
3415                 [72] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3416                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3417                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3418                        RTE_PTYPE_INNER_L4_ICMP,
3419                 /* [73] - [87] reserved */
3420
3421                 /* Non tunneled IPv6 */
3422                 [88] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3423                        RTE_PTYPE_L4_FRAG,
3424                 [89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3425                        RTE_PTYPE_L4_NONFRAG,
3426                 [90] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3427                        RTE_PTYPE_L4_UDP,
3428                 /* [91] reserved */
3429                 [92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3430                        RTE_PTYPE_L4_TCP,
3431                 [93] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3432                        RTE_PTYPE_L4_SCTP,
3433                 [94] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3434                        RTE_PTYPE_L4_ICMP,
3435
3436                 /* IPv6 --> IPv4 */
3437                 [95] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3438                        RTE_PTYPE_TUNNEL_IP |
3439                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3440                        RTE_PTYPE_INNER_L4_FRAG,
3441                 [96] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3442                        RTE_PTYPE_TUNNEL_IP |
3443                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3444                        RTE_PTYPE_INNER_L4_NONFRAG,
3445                 [97] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3446                        RTE_PTYPE_TUNNEL_IP |
3447                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3448                        RTE_PTYPE_INNER_L4_UDP,
3449                 /* [98] reserved */
3450                 [99] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3451                        RTE_PTYPE_TUNNEL_IP |
3452                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3453                        RTE_PTYPE_INNER_L4_TCP,
3454                 [100] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3455                         RTE_PTYPE_TUNNEL_IP |
3456                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3457                         RTE_PTYPE_INNER_L4_SCTP,
3458                 [101] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3459                         RTE_PTYPE_TUNNEL_IP |
3460                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3461                         RTE_PTYPE_INNER_L4_ICMP,
3462
3463                 /* IPv6 --> IPv6 */
3464                 [102] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3465                         RTE_PTYPE_TUNNEL_IP |
3466                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3467                         RTE_PTYPE_INNER_L4_FRAG,
3468                 [103] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3469                         RTE_PTYPE_TUNNEL_IP |
3470                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3471                         RTE_PTYPE_INNER_L4_NONFRAG,
3472                 [104] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3473                         RTE_PTYPE_TUNNEL_IP |
3474                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3475                         RTE_PTYPE_INNER_L4_UDP,
3476                 /* [105] reserved */
3477                 [106] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3478                         RTE_PTYPE_TUNNEL_IP |
3479                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3480                         RTE_PTYPE_INNER_L4_TCP,
3481                 [107] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3482                         RTE_PTYPE_TUNNEL_IP |
3483                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3484                         RTE_PTYPE_INNER_L4_SCTP,
3485                 [108] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3486                         RTE_PTYPE_TUNNEL_IP |
3487                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3488                         RTE_PTYPE_INNER_L4_ICMP,
3489
3490                 /* IPv6 --> GRE/Teredo/VXLAN */
3491                 [109] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3492                         RTE_PTYPE_TUNNEL_GRENAT,
3493
3494                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv4 */
3495                 [110] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3496                         RTE_PTYPE_TUNNEL_GRENAT |
3497                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3498                         RTE_PTYPE_INNER_L4_FRAG,
3499                 [111] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3500                         RTE_PTYPE_TUNNEL_GRENAT |
3501                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3502                         RTE_PTYPE_INNER_L4_NONFRAG,
3503                 [112] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3504                         RTE_PTYPE_TUNNEL_GRENAT |
3505                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3506                         RTE_PTYPE_INNER_L4_UDP,
3507                 /* [113] reserved */
3508                 [114] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3509                         RTE_PTYPE_TUNNEL_GRENAT |
3510                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3511                         RTE_PTYPE_INNER_L4_TCP,
3512                 [115] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3513                         RTE_PTYPE_TUNNEL_GRENAT |
3514                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3515                         RTE_PTYPE_INNER_L4_SCTP,
3516                 [116] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3517                         RTE_PTYPE_TUNNEL_GRENAT |
3518                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3519                         RTE_PTYPE_INNER_L4_ICMP,
3520
3521                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv6 */
3522                 [117] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3523                         RTE_PTYPE_TUNNEL_GRENAT |
3524                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3525                         RTE_PTYPE_INNER_L4_FRAG,
3526                 [118] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3527                         RTE_PTYPE_TUNNEL_GRENAT |
3528                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3529                         RTE_PTYPE_INNER_L4_NONFRAG,
3530                 [119] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3531                         RTE_PTYPE_TUNNEL_GRENAT |
3532                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3533                         RTE_PTYPE_INNER_L4_UDP,
3534                 /* [120] reserved */
3535                 [121] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3536                         RTE_PTYPE_TUNNEL_GRENAT |
3537                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3538                         RTE_PTYPE_INNER_L4_TCP,
3539                 [122] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3540                         RTE_PTYPE_TUNNEL_GRENAT |
3541                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3542                         RTE_PTYPE_INNER_L4_SCTP,
3543                 [123] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3544                         RTE_PTYPE_TUNNEL_GRENAT |
3545                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3546                         RTE_PTYPE_INNER_L4_ICMP,
3547
3548                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC */
3549                 [124] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3550                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
3551
3552                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
3553                 [125] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3554                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3555                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3556                         RTE_PTYPE_INNER_L4_FRAG,
3557                 [126] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3558                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3559                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3560                         RTE_PTYPE_INNER_L4_NONFRAG,
3561                 [127] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3562                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3563                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3564                         RTE_PTYPE_INNER_L4_UDP,
3565                 /* [128] reserved */
3566                 [129] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3567                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3568                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3569                         RTE_PTYPE_INNER_L4_TCP,
3570                 [130] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3571                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3572                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3573                         RTE_PTYPE_INNER_L4_SCTP,
3574                 [131] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3575                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3576                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3577                         RTE_PTYPE_INNER_L4_ICMP,
3578
3579                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
3580                 [132] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3581                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3582                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3583                         RTE_PTYPE_INNER_L4_FRAG,
3584                 [133] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3585                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3586                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3587                         RTE_PTYPE_INNER_L4_NONFRAG,
3588                 [134] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3589                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3590                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3591                         RTE_PTYPE_INNER_L4_UDP,
3592                 /* [135] reserved */
3593                 [136] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3594                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3595                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3596                         RTE_PTYPE_INNER_L4_TCP,
3597                 [137] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3598                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3599                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3600                         RTE_PTYPE_INNER_L4_SCTP,
3601                 [138] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3602                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3603                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3604                         RTE_PTYPE_INNER_L4_ICMP,
3605                 /* [139] - [299] reserved */
3606
3607                 /* PPPoE */
3608                 [300] = RTE_PTYPE_L2_ETHER_PPPOE,
3609                 [301] = RTE_PTYPE_L2_ETHER_PPPOE,
3610
3611                 /* PPPoE --> IPv4 */
3612                 [302] = RTE_PTYPE_L2_ETHER_PPPOE |
3613                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3614                         RTE_PTYPE_L4_FRAG,
3615                 [303] = RTE_PTYPE_L2_ETHER_PPPOE |
3616                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3617                         RTE_PTYPE_L4_NONFRAG,
3618                 [304] = RTE_PTYPE_L2_ETHER_PPPOE |
3619                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3620                         RTE_PTYPE_L4_UDP,
3621                 [305] = RTE_PTYPE_L2_ETHER_PPPOE |
3622                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3623                         RTE_PTYPE_L4_TCP,
3624                 [306] = RTE_PTYPE_L2_ETHER_PPPOE |
3625                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3626                         RTE_PTYPE_L4_SCTP,
3627                 [307] = RTE_PTYPE_L2_ETHER_PPPOE |
3628                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3629                         RTE_PTYPE_L4_ICMP,
3630
3631                 /* PPPoE --> IPv6 */
3632                 [308] = RTE_PTYPE_L2_ETHER_PPPOE |
3633                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3634                         RTE_PTYPE_L4_FRAG,
3635                 [309] = RTE_PTYPE_L2_ETHER_PPPOE |
3636                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3637                         RTE_PTYPE_L4_NONFRAG,
3638                 [310] = RTE_PTYPE_L2_ETHER_PPPOE |
3639                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3640                         RTE_PTYPE_L4_UDP,
3641                 [311] = RTE_PTYPE_L2_ETHER_PPPOE |
3642                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3643                         RTE_PTYPE_L4_TCP,
3644                 [312] = RTE_PTYPE_L2_ETHER_PPPOE |
3645                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3646                         RTE_PTYPE_L4_SCTP,
3647                 [313] = RTE_PTYPE_L2_ETHER_PPPOE |
3648                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3649                         RTE_PTYPE_L4_ICMP,
3650                 /* [314] - [324] reserved */
3651
3652                 /* IPv4/IPv6 --> GTPC/GTPU */
3653                 [325] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3654                         RTE_PTYPE_TUNNEL_GTPC,
3655                 [326] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3656                         RTE_PTYPE_TUNNEL_GTPC,
3657                 [327] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3658                         RTE_PTYPE_TUNNEL_GTPC,
3659                 [328] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3660                         RTE_PTYPE_TUNNEL_GTPC,
3661                 [329] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3662                         RTE_PTYPE_TUNNEL_GTPU,
3663                 [330] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3664                         RTE_PTYPE_TUNNEL_GTPU,
3665
3666                 /* IPv4 --> GTPU --> IPv4 */
3667                 [331] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3668                         RTE_PTYPE_TUNNEL_GTPU |
3669                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3670                         RTE_PTYPE_INNER_L4_FRAG,
3671                 [332] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3672                         RTE_PTYPE_TUNNEL_GTPU |
3673                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3674                         RTE_PTYPE_INNER_L4_NONFRAG,
3675                 [333] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3676                         RTE_PTYPE_TUNNEL_GTPU |
3677                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3678                         RTE_PTYPE_INNER_L4_UDP,
3679                 [334] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3680                         RTE_PTYPE_TUNNEL_GTPU |
3681                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3682                         RTE_PTYPE_INNER_L4_TCP,
3683                 [335] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3684                         RTE_PTYPE_TUNNEL_GTPU |
3685                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3686                         RTE_PTYPE_INNER_L4_ICMP,
3687
3688                 /* IPv6 --> GTPU --> IPv4 */
3689                 [336] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3690                         RTE_PTYPE_TUNNEL_GTPU |
3691                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3692                         RTE_PTYPE_INNER_L4_FRAG,
3693                 [337] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3694                         RTE_PTYPE_TUNNEL_GTPU |
3695                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3696                         RTE_PTYPE_INNER_L4_NONFRAG,
3697                 [338] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3698                         RTE_PTYPE_TUNNEL_GTPU |
3699                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3700                         RTE_PTYPE_INNER_L4_UDP,
3701                 [339] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3702                         RTE_PTYPE_TUNNEL_GTPU |
3703                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3704                         RTE_PTYPE_INNER_L4_TCP,
3705                 [340] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3706                         RTE_PTYPE_TUNNEL_GTPU |
3707                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3708                         RTE_PTYPE_INNER_L4_ICMP,
3709
3710                 /* IPv4 --> GTPU --> IPv6 */
3711                 [341] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3712                         RTE_PTYPE_TUNNEL_GTPU |
3713                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3714                         RTE_PTYPE_INNER_L4_FRAG,
3715                 [342] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3716                         RTE_PTYPE_TUNNEL_GTPU |
3717                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3718                         RTE_PTYPE_INNER_L4_NONFRAG,
3719                 [343] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3720                         RTE_PTYPE_TUNNEL_GTPU |
3721                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3722                         RTE_PTYPE_INNER_L4_UDP,
3723                 [344] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3724                         RTE_PTYPE_TUNNEL_GTPU |
3725                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3726                         RTE_PTYPE_INNER_L4_TCP,
3727                 [345] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3728                         RTE_PTYPE_TUNNEL_GTPU |
3729                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3730                         RTE_PTYPE_INNER_L4_ICMP,
3731
3732                 /* IPv6 --> GTPU --> IPv6 */
3733                 [346] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3734                         RTE_PTYPE_TUNNEL_GTPU |
3735                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3736                         RTE_PTYPE_INNER_L4_FRAG,
3737                 [347] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3738                         RTE_PTYPE_TUNNEL_GTPU |
3739                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3740                         RTE_PTYPE_INNER_L4_NONFRAG,
3741                 [348] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3742                         RTE_PTYPE_TUNNEL_GTPU |
3743                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3744                         RTE_PTYPE_INNER_L4_UDP,
3745                 [349] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3746                         RTE_PTYPE_TUNNEL_GTPU |
3747                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3748                         RTE_PTYPE_INNER_L4_TCP,
3749                 [350] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3750                         RTE_PTYPE_TUNNEL_GTPU |
3751                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3752                         RTE_PTYPE_INNER_L4_ICMP,
3753
3754                 /* IPv4 --> UDP ECPRI */
3755                 [372] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3756                         RTE_PTYPE_L4_UDP,
3757                 [373] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3758                         RTE_PTYPE_L4_UDP,
3759                 [374] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3760                         RTE_PTYPE_L4_UDP,
3761                 [375] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3762                         RTE_PTYPE_L4_UDP,
3763                 [376] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3764                         RTE_PTYPE_L4_UDP,
3765                 [377] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3766                         RTE_PTYPE_L4_UDP,
3767                 [378] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3768                         RTE_PTYPE_L4_UDP,
3769                 [379] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3770                         RTE_PTYPE_L4_UDP,
3771                 [380] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3772                         RTE_PTYPE_L4_UDP,
3773                 [381] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3774                         RTE_PTYPE_L4_UDP,
3775
3776                 /* IPV6 --> UDP ECPRI */
3777                 [382] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3778                         RTE_PTYPE_L4_UDP,
3779                 [383] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3780                         RTE_PTYPE_L4_UDP,
3781                 [384] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3782                         RTE_PTYPE_L4_UDP,
3783                 [385] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3784                         RTE_PTYPE_L4_UDP,
3785                 [386] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3786                         RTE_PTYPE_L4_UDP,
3787                 [387] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3788                         RTE_PTYPE_L4_UDP,
3789                 [388] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3790                         RTE_PTYPE_L4_UDP,
3791                 [389] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3792                         RTE_PTYPE_L4_UDP,
3793                 [390] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3794                         RTE_PTYPE_L4_UDP,
3795                 [391] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3796                         RTE_PTYPE_L4_UDP,
3797                 /* All others reserved */
3798         };
3799
3800         return ptype_tbl[ptype];
3801 }
3802
3803 void __rte_cold
3804 iavf_set_default_ptype_table(struct rte_eth_dev *dev)
3805 {
3806         struct iavf_adapter *ad =
3807                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3808         int i;
3809
3810         for (i = 0; i < IAVF_MAX_PKT_TYPE; i++)
3811                 ad->ptype_tbl[i] = iavf_get_default_ptype(i);
3812 }