1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2017 Intel Corporation
8 /* In QLEN must be whole number of 32 descriptors. */
9 #define IAVF_ALIGN_RING_DESC 32
10 #define IAVF_MIN_RING_DESC 64
11 #define IAVF_MAX_RING_DESC 4096
12 #define IAVF_DMA_MEM_ALIGN 4096
13 /* Base address of the HW descriptor ring should be 128B aligned. */
14 #define IAVF_RING_BASE_ALIGN 128
16 /* used for Rx Bulk Allocate */
17 #define IAVF_RX_MAX_BURST 32
19 /* used for Vector PMD */
20 #define IAVF_VPMD_RX_MAX_BURST 32
21 #define IAVF_VPMD_TX_MAX_BURST 32
22 #define IAVF_RXQ_REARM_THRESH 32
23 #define IAVF_VPMD_DESCS_PER_LOOP 4
24 #define IAVF_VPMD_TX_MAX_FREE_BUF 64
26 #define IAVF_TX_NO_VECTOR_FLAGS ( \
27 RTE_ETH_TX_OFFLOAD_MULTI_SEGS | \
28 RTE_ETH_TX_OFFLOAD_TCP_TSO | \
29 RTE_ETH_TX_OFFLOAD_SECURITY)
31 #define IAVF_TX_VECTOR_OFFLOAD ( \
32 RTE_ETH_TX_OFFLOAD_VLAN_INSERT | \
33 RTE_ETH_TX_OFFLOAD_QINQ_INSERT | \
34 RTE_ETH_TX_OFFLOAD_IPV4_CKSUM | \
35 RTE_ETH_TX_OFFLOAD_SCTP_CKSUM | \
36 RTE_ETH_TX_OFFLOAD_UDP_CKSUM | \
37 RTE_ETH_TX_OFFLOAD_TCP_CKSUM)
39 #define IAVF_RX_VECTOR_OFFLOAD ( \
40 RTE_ETH_RX_OFFLOAD_CHECKSUM | \
41 RTE_ETH_RX_OFFLOAD_SCTP_CKSUM | \
42 RTE_ETH_RX_OFFLOAD_VLAN | \
43 RTE_ETH_RX_OFFLOAD_RSS_HASH)
45 #define IAVF_VECTOR_PATH 0
46 #define IAVF_VECTOR_OFFLOAD_PATH 1
48 #define DEFAULT_TX_RS_THRESH 32
49 #define DEFAULT_TX_FREE_THRESH 32
51 #define IAVF_MIN_TSO_MSS 256
52 #define IAVF_MAX_TSO_MSS 9668
53 #define IAVF_TSO_MAX_SEG UINT8_MAX
54 #define IAVF_TX_MAX_MTU_SEG 8
56 #define IAVF_TX_CKSUM_OFFLOAD_MASK ( \
57 RTE_MBUF_F_TX_IP_CKSUM | \
58 RTE_MBUF_F_TX_L4_MASK | \
59 RTE_MBUF_F_TX_TCP_SEG)
61 #define IAVF_TX_OFFLOAD_MASK ( \
62 RTE_MBUF_F_TX_OUTER_IPV6 | \
63 RTE_MBUF_F_TX_OUTER_IPV4 | \
64 RTE_MBUF_F_TX_IPV6 | \
65 RTE_MBUF_F_TX_IPV4 | \
66 RTE_MBUF_F_TX_VLAN | \
67 RTE_MBUF_F_TX_IP_CKSUM | \
68 RTE_MBUF_F_TX_L4_MASK | \
69 RTE_MBUF_F_TX_TCP_SEG | \
70 RTE_ETH_TX_OFFLOAD_SECURITY)
72 #define IAVF_TX_OFFLOAD_NOTSUP_MASK \
73 (RTE_MBUF_F_TX_OFFLOAD_MASK ^ IAVF_TX_OFFLOAD_MASK)
75 extern uint64_t iavf_timestamp_dynflag;
76 extern int iavf_timestamp_dynfield_offset;
80 * These descriptors are used instead of the legacy version descriptors
82 union iavf_16b_rx_flex_desc {
84 __le64 pkt_addr; /* Packet buffer address */
85 __le64 hdr_addr; /* Header buffer address */
86 /* bit 0 of hdr_addr is DD bit */
90 u8 rxdid; /* descriptor builder profile ID */
91 u8 mir_id_umb_cast; /* mirror=[5:0], umb=[7:6] */
92 __le16 ptype_flex_flags0; /* ptype=[9:0], ff0=[15:10] */
93 __le16 pkt_len; /* [15:14] are reserved */
94 __le16 hdr_len_sph_flex_flags1; /* header=[10:0] */
103 } wb; /* writeback */
106 union iavf_32b_rx_flex_desc {
108 __le64 pkt_addr; /* Packet buffer address */
109 __le64 hdr_addr; /* Header buffer address */
110 /* bit 0 of hdr_addr is DD bit */
116 u8 rxdid; /* descriptor builder profile ID */
117 u8 mir_id_umb_cast; /* mirror=[5:0], umb=[7:6] */
118 __le16 ptype_flex_flags0; /* ptype=[9:0], ff0=[15:10] */
119 __le16 pkt_len; /* [15:14] are reserved */
120 __le16 hdr_len_sph_flex_flags1; /* header=[10:0] */
122 /* ff1/ext=[15:12] */
125 __le16 status_error0;
131 __le16 status_error1;
147 } wb; /* writeback */
150 /* HW desc structure, both 16-byte and 32-byte types are supported */
151 #ifdef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
152 #define iavf_rx_desc iavf_16byte_rx_desc
153 #define iavf_rx_flex_desc iavf_16b_rx_flex_desc
155 #define iavf_rx_desc iavf_32byte_rx_desc
156 #define iavf_rx_flex_desc iavf_32b_rx_flex_desc
159 typedef void (*iavf_rxd_to_pkt_fields_t)(struct iavf_rx_queue *rxq,
161 volatile union iavf_rx_flex_desc *rxdp);
163 struct iavf_rxq_ops {
164 void (*release_mbufs)(struct iavf_rx_queue *rxq);
167 struct iavf_txq_ops {
168 void (*release_mbufs)(struct iavf_tx_queue *txq);
172 struct iavf_rx_queue_stats {
174 struct iavf_ipsec_crypto_stats ipsec_crypto;
177 /* Structure associated with each Rx queue. */
178 struct iavf_rx_queue {
179 struct rte_mempool *mp; /* mbuf pool to populate Rx ring */
180 const struct rte_memzone *mz; /* memzone for Rx ring */
181 volatile union iavf_rx_desc *rx_ring; /* Rx ring virtual address */
182 uint64_t rx_ring_phys_addr; /* Rx ring DMA address */
183 struct rte_mbuf **sw_ring; /* address of SW ring */
184 uint16_t nb_rx_desc; /* ring length */
185 uint16_t rx_tail; /* current value of tail */
186 volatile uint8_t *qrx_tail; /* register address of tail */
187 uint16_t rx_free_thresh; /* max free RX desc to hold */
188 uint16_t nb_rx_hold; /* number of held free RX desc */
189 struct rte_mbuf *pkt_first_seg; /* first segment of current packet */
190 struct rte_mbuf *pkt_last_seg; /* last segment of current packet */
191 struct rte_mbuf fake_mbuf; /* dummy mbuf */
193 uint8_t rel_mbufs_type;
196 uint16_t rxrearm_nb; /* number of remaining to be re-armed */
197 uint16_t rxrearm_start; /* the idx we start the re-arming from */
198 uint64_t mbuf_initializer; /* value to init mbufs */
201 uint16_t rx_nb_avail; /* number of staged packets ready */
202 uint16_t rx_next_avail; /* index of next staged packets */
203 uint16_t rx_free_trigger; /* triggers rx buffer allocation */
204 struct rte_mbuf *rx_stage[IAVF_RX_MAX_BURST * 2]; /* store mbuf */
206 uint16_t port_id; /* device port ID */
207 uint8_t crc_len; /* 0 if CRC stripped, 4 otherwise */
208 uint8_t fdir_enabled; /* 0 if FDIR disabled, 1 when enabled */
209 uint16_t queue_id; /* Rx queue index */
210 uint16_t rx_buf_len; /* The packet buffer size */
211 uint16_t rx_hdr_len; /* The header buffer size */
212 uint16_t max_pkt_len; /* Maximum packet length */
213 struct iavf_vsi *vsi; /**< the VSI this queue belongs to */
215 bool q_set; /* if rx queue has been configured */
216 bool rx_deferred_start; /* don't start this queue in dev start */
217 const struct iavf_rxq_ops *ops;
219 #define IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG1 BIT(0)
220 #define IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG2_2 BIT(1)
221 uint8_t proto_xtr; /* protocol extraction type */
222 uint64_t xtr_ol_flag;
223 /* flexible descriptor metadata extraction offload flag */
224 struct iavf_rx_queue_stats stats;
227 uint64_t hw_time_update;
230 struct iavf_tx_entry {
231 struct rte_mbuf *mbuf;
236 struct iavf_tx_vec_entry {
237 struct rte_mbuf *mbuf;
240 /* Structure associated with each TX queue. */
241 struct iavf_tx_queue {
242 const struct rte_memzone *mz; /* memzone for Tx ring */
243 volatile struct iavf_tx_desc *tx_ring; /* Tx ring virtual address */
244 uint64_t tx_ring_phys_addr; /* Tx ring DMA address */
245 struct iavf_tx_entry *sw_ring; /* address array of SW ring */
246 uint16_t nb_tx_desc; /* ring length */
247 uint16_t tx_tail; /* current value of tail */
248 volatile uint8_t *qtx_tail; /* register address of tail */
249 /* number of used desc since RS bit set */
252 uint16_t last_desc_cleaned; /* last desc have been cleaned*/
253 uint16_t free_thresh;
255 uint8_t rel_mbufs_type;
260 uint16_t next_dd; /* next to set RS, for VPMD */
261 uint16_t next_rs; /* next to check DD, for VPMD */
262 uint16_t ipsec_crypto_pkt_md_offset;
264 bool q_set; /* if rx queue has been configured */
265 bool tx_deferred_start; /* don't start this queue in dev start */
266 const struct iavf_txq_ops *ops;
267 #define IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG1 BIT(0)
268 #define IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG2 BIT(1)
273 /* Offload features */
274 union iavf_tx_offload {
277 uint64_t l2_len:7; /* L2 (MAC) Header Length. */
278 uint64_t l3_len:9; /* L3 (IP) Header Length. */
279 uint64_t l4_len:8; /* L4 Header Length. */
280 uint64_t tso_segsz:16; /* TCP TSO segment size */
281 /* uint64_t unused : 24; */
285 /* Rx Flex Descriptor
286 * RxDID Profile ID 16-21
287 * Flex-field 0: RSS hash lower 16-bits
288 * Flex-field 1: RSS hash upper 16-bits
289 * Flex-field 2: Flow ID lower 16-bits
290 * Flex-field 3: Flow ID upper 16-bits
294 struct iavf_32b_rx_flex_desc_comms {
298 __le16 ptype_flexi_flags0;
300 __le16 hdr_len_sph_flex_flags1;
303 __le16 status_error0;
308 __le16 status_error1;
325 /* Rx Flex Descriptor
326 * RxDID Profile ID 22-23 (swap Hash and FlowID)
327 * Flex-field 0: Flow ID lower 16-bits
328 * Flex-field 1: Flow ID upper 16-bits
329 * Flex-field 2: RSS hash lower 16-bits
330 * Flex-field 3: RSS hash upper 16-bits
334 struct iavf_32b_rx_flex_desc_comms_ovs {
338 __le16 ptype_flexi_flags0;
340 __le16 hdr_len_sph_flex_flags1;
343 __le16 status_error0;
348 __le16 status_error1;
365 /* Rx Flex Descriptor
366 * RxDID Profile ID 24 Inline IPsec
367 * Flex-field 0: RSS hash lower 16-bits
368 * Flex-field 1: RSS hash upper 16-bits
369 * Flex-field 2: Flow ID lower 16-bits
370 * Flex-field 3: Flow ID upper 16-bits
371 * Flex-field 4: Inline IPsec SAID lower 16-bits
372 * Flex-field 5: Inline IPsec SAID upper 16-bits
374 struct iavf_32b_rx_flex_desc_comms_ipsec {
378 __le16 ptype_flexi_flags0;
380 __le16 hdr_len_sph_flex_flags1;
383 __le16 status_error0;
388 __le16 status_error1;
399 enum iavf_rxtx_rel_mbufs_type {
400 IAVF_REL_MBUFS_DEFAULT = 0,
401 IAVF_REL_MBUFS_SSE_VEC = 1,
402 IAVF_REL_MBUFS_AVX512_VEC = 2,
405 /* Receive Flex Descriptor profile IDs: There are a total
406 * of 64 profiles where profile IDs 0/1 are for legacy; and
407 * profiles 2-63 are flex profiles that can be programmed
408 * with a specific metadata (profile 7 reserved for HW)
411 IAVF_RXDID_LEGACY_0 = 0,
412 IAVF_RXDID_LEGACY_1 = 1,
413 IAVF_RXDID_FLEX_NIC = 2,
414 IAVF_RXDID_FLEX_NIC_2 = 6,
416 IAVF_RXDID_COMMS_GENERIC = 16,
417 IAVF_RXDID_COMMS_AUX_VLAN = 17,
418 IAVF_RXDID_COMMS_AUX_IPV4 = 18,
419 IAVF_RXDID_COMMS_AUX_IPV6 = 19,
420 IAVF_RXDID_COMMS_AUX_IPV6_FLOW = 20,
421 IAVF_RXDID_COMMS_AUX_TCP = 21,
422 IAVF_RXDID_COMMS_OVS_1 = 22,
423 IAVF_RXDID_COMMS_OVS_2 = 23,
424 IAVF_RXDID_COMMS_IPSEC_CRYPTO = 24,
425 IAVF_RXDID_COMMS_AUX_IP_OFFSET = 25,
426 IAVF_RXDID_LAST = 63,
429 enum iavf_rx_flex_desc_status_error_0_bits {
430 /* Note: These are predefined bit offsets */
431 IAVF_RX_FLEX_DESC_STATUS0_DD_S = 0,
432 IAVF_RX_FLEX_DESC_STATUS0_EOF_S,
433 IAVF_RX_FLEX_DESC_STATUS0_HBO_S,
434 IAVF_RX_FLEX_DESC_STATUS0_L3L4P_S,
435 IAVF_RX_FLEX_DESC_STATUS0_XSUM_IPE_S,
436 IAVF_RX_FLEX_DESC_STATUS0_XSUM_L4E_S,
437 IAVF_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S,
438 IAVF_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S,
439 IAVF_RX_FLEX_DESC_STATUS0_LPBK_S,
440 IAVF_RX_FLEX_DESC_STATUS0_IPV6EXADD_S,
441 IAVF_RX_FLEX_DESC_STATUS0_RXE_S,
442 IAVF_RX_FLEX_DESC_STATUS0_CRCP_S,
443 IAVF_RX_FLEX_DESC_STATUS0_RSS_VALID_S,
444 IAVF_RX_FLEX_DESC_STATUS0_L2TAG1P_S,
445 IAVF_RX_FLEX_DESC_STATUS0_XTRMD0_VALID_S,
446 IAVF_RX_FLEX_DESC_STATUS0_XTRMD1_VALID_S,
447 IAVF_RX_FLEX_DESC_STATUS0_LAST /* this entry must be last!!! */
450 enum iavf_rx_flex_desc_status_error_1_bits {
451 /* Note: These are predefined bit offsets */
452 /* Bits 3:0 are reserved for inline ipsec status */
453 IAVF_RX_FLEX_DESC_STATUS1_IPSEC_CRYPTO_STATUS_0 = 0,
454 IAVF_RX_FLEX_DESC_STATUS1_IPSEC_CRYPTO_STATUS_1,
455 IAVF_RX_FLEX_DESC_STATUS1_IPSEC_CRYPTO_STATUS_2,
456 IAVF_RX_FLEX_DESC_STATUS1_IPSEC_CRYPTO_STATUS_3,
457 IAVF_RX_FLEX_DESC_STATUS1_NAT_S,
458 IAVF_RX_FLEX_DESC_STATUS1_IPSEC_CRYPTO_PROCESSED,
459 /* [10:6] reserved */
460 IAVF_RX_FLEX_DESC_STATUS1_L2TAG2P_S = 11,
461 IAVF_RX_FLEX_DESC_STATUS1_XTRMD2_VALID_S = 12,
462 IAVF_RX_FLEX_DESC_STATUS1_XTRMD3_VALID_S = 13,
463 IAVF_RX_FLEX_DESC_STATUS1_XTRMD4_VALID_S = 14,
464 IAVF_RX_FLEX_DESC_STATUS1_XTRMD5_VALID_S = 15,
465 IAVF_RX_FLEX_DESC_STATUS1_LAST /* this entry must be last!!! */
468 #define IAVF_RX_FLEX_DESC_IPSEC_CRYPTO_STATUS_MASK ( \
469 BIT(IAVF_RX_FLEX_DESC_STATUS1_IPSEC_CRYPTO_STATUS_0) | \
470 BIT(IAVF_RX_FLEX_DESC_STATUS1_IPSEC_CRYPTO_STATUS_1) | \
471 BIT(IAVF_RX_FLEX_DESC_STATUS1_IPSEC_CRYPTO_STATUS_2) | \
472 BIT(IAVF_RX_FLEX_DESC_STATUS1_IPSEC_CRYPTO_STATUS_3))
474 enum iavf_rx_flex_desc_ipsec_crypto_status {
475 IAVF_IPSEC_CRYPTO_STATUS_SUCCESS = 0,
476 IAVF_IPSEC_CRYPTO_STATUS_SAD_MISS,
477 IAVF_IPSEC_CRYPTO_STATUS_NOT_PROCESSED,
478 IAVF_IPSEC_CRYPTO_STATUS_ICV_CHECK_FAIL,
479 IAVF_IPSEC_CRYPTO_STATUS_LENGTH_ERR,
481 IAVF_IPSEC_CRYPTO_STATUS_MISC_ERR = 0xF
486 #define IAVF_TXD_DATA_QW1_DTYPE_SHIFT (0)
487 #define IAVF_TXD_DATA_QW1_DTYPE_MASK (0xFUL << IAVF_TXD_QW1_DTYPE_SHIFT)
489 #define IAVF_TXD_DATA_QW1_CMD_SHIFT (4)
490 #define IAVF_TXD_DATA_QW1_CMD_MASK (0x3FFUL << IAVF_TXD_DATA_QW1_CMD_SHIFT)
492 #define IAVF_TXD_DATA_QW1_OFFSET_SHIFT (16)
493 #define IAVF_TXD_DATA_QW1_OFFSET_MASK (0x3FFFFULL << \
494 IAVF_TXD_DATA_QW1_OFFSET_SHIFT)
496 #define IAVF_TXD_DATA_QW1_OFFSET_MACLEN_SHIFT (IAVF_TXD_DATA_QW1_OFFSET_SHIFT)
497 #define IAVF_TXD_DATA_QW1_OFFSET_MACLEN_MASK \
498 (0x7FUL << IAVF_TXD_DATA_QW1_OFFSET_MACLEN_SHIFT)
500 #define IAVF_TXD_DATA_QW1_OFFSET_IPLEN_SHIFT \
501 (IAVF_TXD_DATA_QW1_OFFSET_SHIFT + IAVF_TX_DESC_LENGTH_IPLEN_SHIFT)
502 #define IAVF_TXD_DATA_QW1_OFFSET_IPLEN_MASK \
503 (0x7FUL << IAVF_TXD_DATA_QW1_OFFSET_IPLEN_SHIFT)
505 #define IAVF_TXD_DATA_QW1_OFFSET_L4LEN_SHIFT \
506 (IAVF_TXD_DATA_QW1_OFFSET_SHIFT + IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
507 #define IAVF_TXD_DATA_QW1_OFFSET_L4LEN_MASK \
508 (0xFUL << IAVF_TXD_DATA_QW1_OFFSET_L4LEN_SHIFT)
510 #define IAVF_TXD_DATA_QW1_MACLEN_MASK \
511 (0x7FUL << IAVF_TX_DESC_LENGTH_MACLEN_SHIFT)
512 #define IAVF_TXD_DATA_QW1_IPLEN_MASK \
513 (0x7FUL << IAVF_TX_DESC_LENGTH_IPLEN_SHIFT)
514 #define IAVF_TXD_DATA_QW1_L4LEN_MASK \
515 (0xFUL << IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
516 #define IAVF_TXD_DATA_QW1_FCLEN_MASK \
517 (0xFUL << IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
519 #define IAVF_TXD_DATA_QW1_TX_BUF_SZ_SHIFT (34)
520 #define IAVF_TXD_DATA_QW1_TX_BUF_SZ_MASK \
521 (0x3FFFULL << IAVF_TXD_DATA_QW1_TX_BUF_SZ_SHIFT)
523 #define IAVF_TXD_DATA_QW1_L2TAG1_SHIFT (48)
524 #define IAVF_TXD_DATA_QW1_L2TAG1_MASK \
525 (0xFFFFULL << IAVF_TXD_DATA_QW1_L2TAG1_SHIFT)
527 #define IAVF_TXD_CTX_QW1_IPSEC_PARAMS_CIPHERBLK_SHIFT (11)
528 #define IAVF_TXD_CTX_QW1_IPSEC_PARAMS_CIPHERBLK_MASK \
529 (0x7UL << IAVF_TXD_CTX_QW1_IPSEC_PARAMS_CIPHERBLK_SHIFT)
531 #define IAVF_TXD_CTX_QW1_IPSEC_PARAMS_ICVLEN_SHIFT (14)
532 #define IAVF_TXD_CTX_QW1_IPSEC_PARAMS_ICVLEN_MASK \
533 (0xFUL << IAVF_TXD_CTX_QW1_IPSEC_PARAMS_ICVLEN_SHIFT)
535 #define IAVF_TXD_CTX_QW1_SEG_PARAMS_TLEN_SHIFT (30)
536 #define IAVF_TXD_CTX_QW1_SEG_PARAMS_TLEN_MASK \
537 (0x3FFFFUL << IAVF_TXD_CTX_QW1_SEG_PARAMS_TLEN_SHIFT)
539 #define IAVF_TXD_CTX_QW1_TSYNC_PARAMS_TLEN_SHIFT (30)
540 #define IAVF_TXD_CTX_QW1_TSYNC_PARAMS_TLEN_MASK \
541 (0x3FUL << IAVF_TXD_CTX_QW1_SEG_PARAMS_TLEN_SHIFT)
543 #define IAVF_TXD_CTX_QW1_SEG_PARAMS_MSS_SHIFT (50)
544 #define IAVF_TXD_CTX_QW1_SEG_PARAMS_MSS_MASK \
545 (0x3FFFUL << IAVF_TXD_CTX_QW1_SEG_PARAMS_MSS_SHIFT)
547 #define IAVF_TXD_CTX_QW0_TUN_PARAMS_EIPT_SHIFT (0)
548 #define IAVF_TXD_CTX_QW0_TUN_PARAMS_EIPT_MASK (0x3UL)
550 enum iavf_tx_ctx_desc_tunnel_external_ip_type {
551 IAVF_TX_CTX_DESC_EIPT_NONE,
552 IAVF_TX_CTX_DESC_EIPT_IPV6,
553 IAVF_TX_CTX_DESC_EIPT_IPV4_NO_CHECKSUM_OFFLOAD,
554 IAVF_TX_CTX_DESC_EIPT_IPV4_CHECKSUM_OFFLOAD
557 #define IAVF_TXD_CTX_QW0_TUN_PARAMS_EIPLEN_SHIFT (2)
558 #define IAVF_TXD_CTX_QW0_TUN_PARAMS_EIPLEN_MASK (0x7FUL)
560 #define IAVF_TXD_CTX_QW0_TUN_PARAMS_L4TUNT_SHIFT (9)
561 #define IAVF_TXD_CTX_QW0_TUN_PARAMS_L4TUNT_MASK (0x3UL)
563 enum iavf_tx_ctx_desc_tunnel_l4_tunnel_type {
564 IAVF_TX_CTX_DESC_L4_TUN_TYP_NO_UDP_GRE,
565 IAVF_TX_CTX_DESC_L4_TUN_TYP_UDP,
566 IAVF_TX_CTX_DESC_L4_TUN_TYP_GRE
569 #define IAVF_TXD_CTX_QW0_TUN_PARAMS_EIP_NOINC_SHIFT (11)
570 #define IAVF_TXD_CTX_QW0_TUN_PARAMS_EIP_NOINC_MASK (0x1UL)
572 #define IAVF_TXD_CTX_QW0_TUN_PARAMS_L4TUNLEN_SHIFT (12)
573 #define IAVF_TXD_CTX_QW0_TUN_PARAMS_L4TUNLEN_MASK (0x7FUL)
575 #define IAVF_TXD_CTX_QW0_TUN_PARAMS_DECTTL_SHIFT (19)
576 #define IAVF_TXD_CTX_QW0_TUN_PARAMS_DECTTL_MASK (0xFUL)
578 #define IAVF_TXD_CTX_QW0_TUN_PARAMS_L4T_CS_SHIFT (23)
579 #define IAVF_TXD_CTX_QW0_TUN_PARAMS_L4T_CS_MASK (0x1UL)
581 #define IAVF_TXD_CTX_QW0_L2TAG2_PARAM (32)
582 #define IAVF_TXD_CTX_QW0_L2TAG2_MASK (0xFFFFUL)
585 #define IAVF_RX_FLEX_DESC_IPSEC_CRYPTO_SAID_MASK (0xFFFFF)
587 /* for iavf_32b_rx_flex_desc.ptype_flex_flags0 member */
588 #define IAVF_RX_FLEX_DESC_PTYPE_M (0x3FF) /* 10-bits */
591 /* for iavf_32b_rx_flex_desc.ptype_flex_flags0 member */
592 #define IAVF_RX_FLEX_DESC_PTYPE_M (0x3FF) /* 10-bits */
594 /* for iavf_32b_rx_flex_desc.pkt_len member */
595 #define IAVF_RX_FLX_DESC_PKT_LEN_M (0x3FFF) /* 14-bits */
597 int iavf_dev_rx_queue_setup(struct rte_eth_dev *dev,
600 unsigned int socket_id,
601 const struct rte_eth_rxconf *rx_conf,
602 struct rte_mempool *mp);
604 int iavf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
605 int iavf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
606 void iavf_dev_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid);
608 int iavf_dev_tx_queue_setup(struct rte_eth_dev *dev,
611 unsigned int socket_id,
612 const struct rte_eth_txconf *tx_conf);
613 int iavf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
614 int iavf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);
615 int iavf_dev_tx_done_cleanup(void *txq, uint32_t free_cnt);
616 void iavf_dev_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid);
617 void iavf_stop_queues(struct rte_eth_dev *dev);
618 uint16_t iavf_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
620 uint16_t iavf_recv_pkts_flex_rxd(void *rx_queue,
621 struct rte_mbuf **rx_pkts,
623 uint16_t iavf_recv_scattered_pkts(void *rx_queue,
624 struct rte_mbuf **rx_pkts,
626 uint16_t iavf_recv_scattered_pkts_flex_rxd(void *rx_queue,
627 struct rte_mbuf **rx_pkts,
629 uint16_t iavf_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
631 uint16_t iavf_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
633 void iavf_set_rx_function(struct rte_eth_dev *dev);
634 void iavf_set_tx_function(struct rte_eth_dev *dev);
635 void iavf_dev_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
636 struct rte_eth_rxq_info *qinfo);
637 void iavf_dev_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
638 struct rte_eth_txq_info *qinfo);
639 uint32_t iavf_dev_rxq_count(void *rx_queue);
640 int iavf_dev_rx_desc_status(void *rx_queue, uint16_t offset);
641 int iavf_dev_tx_desc_status(void *tx_queue, uint16_t offset);
643 uint16_t iavf_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
645 uint16_t iavf_recv_pkts_vec_flex_rxd(void *rx_queue, struct rte_mbuf **rx_pkts,
647 uint16_t iavf_recv_scattered_pkts_vec(void *rx_queue,
648 struct rte_mbuf **rx_pkts,
650 uint16_t iavf_recv_scattered_pkts_vec_flex_rxd(void *rx_queue,
651 struct rte_mbuf **rx_pkts,
653 uint16_t iavf_xmit_fixed_burst_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
655 uint16_t iavf_recv_pkts_vec_avx2(void *rx_queue, struct rte_mbuf **rx_pkts,
657 uint16_t iavf_recv_pkts_vec_avx2_flex_rxd(void *rx_queue,
658 struct rte_mbuf **rx_pkts,
660 uint16_t iavf_recv_scattered_pkts_vec_avx2(void *rx_queue,
661 struct rte_mbuf **rx_pkts,
663 uint16_t iavf_recv_scattered_pkts_vec_avx2_flex_rxd(void *rx_queue,
664 struct rte_mbuf **rx_pkts,
666 uint16_t iavf_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
668 uint16_t iavf_xmit_pkts_vec_avx2(void *tx_queue, struct rte_mbuf **tx_pkts,
670 int iavf_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc);
671 int iavf_rx_vec_dev_check(struct rte_eth_dev *dev);
672 int iavf_tx_vec_dev_check(struct rte_eth_dev *dev);
673 int iavf_rxq_vec_setup(struct iavf_rx_queue *rxq);
674 int iavf_txq_vec_setup(struct iavf_tx_queue *txq);
675 uint16_t iavf_recv_pkts_vec_avx512(void *rx_queue, struct rte_mbuf **rx_pkts,
677 uint16_t iavf_recv_pkts_vec_avx512_offload(void *rx_queue,
678 struct rte_mbuf **rx_pkts,
680 uint16_t iavf_recv_pkts_vec_avx512_flex_rxd(void *rx_queue,
681 struct rte_mbuf **rx_pkts,
683 uint16_t iavf_recv_pkts_vec_avx512_flex_rxd_offload(void *rx_queue,
684 struct rte_mbuf **rx_pkts,
686 uint16_t iavf_recv_scattered_pkts_vec_avx512(void *rx_queue,
687 struct rte_mbuf **rx_pkts,
689 uint16_t iavf_recv_scattered_pkts_vec_avx512_offload(void *rx_queue,
690 struct rte_mbuf **rx_pkts,
692 uint16_t iavf_recv_scattered_pkts_vec_avx512_flex_rxd(void *rx_queue,
693 struct rte_mbuf **rx_pkts,
695 uint16_t iavf_recv_scattered_pkts_vec_avx512_flex_rxd_offload(void *rx_queue,
696 struct rte_mbuf **rx_pkts,
698 uint16_t iavf_xmit_pkts_vec_avx512(void *tx_queue, struct rte_mbuf **tx_pkts,
700 uint16_t iavf_xmit_pkts_vec_avx512_offload(void *tx_queue,
701 struct rte_mbuf **tx_pkts,
703 int iavf_txq_vec_setup_avx512(struct iavf_tx_queue *txq);
705 uint8_t iavf_proto_xtr_type_to_rxdid(uint8_t xtr_type);
707 void iavf_set_default_ptype_table(struct rte_eth_dev *dev);
708 void iavf_tx_queue_release_mbufs_avx512(struct iavf_tx_queue *txq);
709 void iavf_rx_queue_release_mbufs_sse(struct iavf_rx_queue *rxq);
710 void iavf_tx_queue_release_mbufs_sse(struct iavf_tx_queue *txq);
713 void iavf_dump_rx_descriptor(struct iavf_rx_queue *rxq,
714 const volatile void *desc,
717 #ifdef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
718 const volatile union iavf_16byte_rx_desc *rx_desc = desc;
720 printf("Queue %d Rx_desc %d: QW0: 0x%016"PRIx64" QW1: 0x%016"PRIx64"\n",
721 rxq->queue_id, rx_id, rx_desc->read.pkt_addr,
722 rx_desc->read.hdr_addr);
724 const volatile union iavf_32byte_rx_desc *rx_desc = desc;
726 printf("Queue %d Rx_desc %d: QW0: 0x%016"PRIx64" QW1: 0x%016"PRIx64
727 " QW2: 0x%016"PRIx64" QW3: 0x%016"PRIx64"\n", rxq->queue_id,
728 rx_id, rx_desc->read.pkt_addr, rx_desc->read.hdr_addr,
729 rx_desc->read.rsvd1, rx_desc->read.rsvd2);
733 /* All the descriptors are 16 bytes, so just use one of them
734 * to print the qwords
737 void iavf_dump_tx_descriptor(const struct iavf_tx_queue *txq,
738 const volatile void *desc, uint16_t tx_id)
741 const volatile struct iavf_tx_desc *tx_desc = desc;
742 enum iavf_tx_desc_dtype_value type;
745 type = (enum iavf_tx_desc_dtype_value)
746 rte_le_to_cpu_64(tx_desc->cmd_type_offset_bsz &
747 rte_cpu_to_le_64(IAVF_TXD_DATA_QW1_DTYPE_MASK));
749 case IAVF_TX_DESC_DTYPE_DATA:
750 name = "Tx_data_desc";
752 case IAVF_TX_DESC_DTYPE_CONTEXT:
753 name = "Tx_context_desc";
755 case IAVF_TX_DESC_DTYPE_IPSEC:
756 name = "Tx_IPsec_desc";
759 name = "unknown_desc";
763 printf("Queue %d %s %d: QW0: 0x%016"PRIx64" QW1: 0x%016"PRIx64"\n",
764 txq->queue_id, name, tx_id, tx_desc->buffer_addr,
765 tx_desc->cmd_type_offset_bsz);
768 #define FDIR_PROC_ENABLE_PER_QUEUE(ad, on) do { \
770 for (i = 0; i < (ad)->dev_data->nb_rx_queues; i++) { \
771 struct iavf_rx_queue *rxq = (ad)->dev_data->rx_queues[i]; \
774 rxq->fdir_enabled = on; \
776 PMD_DRV_LOG(DEBUG, "FDIR processing on RX set to %d", on); \
779 /* Enable/disable flow director Rx processing in data path. */
781 void iavf_fdir_rx_proc_enable(struct iavf_adapter *ad, bool on)
784 /* enable flow director processing */
785 FDIR_PROC_ENABLE_PER_QUEUE(ad, on);
788 if (ad->fdir_ref_cnt >= 1) {
791 if (ad->fdir_ref_cnt == 0)
792 FDIR_PROC_ENABLE_PER_QUEUE(ad, on);
798 uint64_t iavf_tstamp_convert_32b_64b(uint64_t time, uint32_t in_timestamp)
800 const uint64_t mask = 0xFFFFFFFF;
804 delta = (in_timestamp - (uint32_t)(time & mask));
805 if (delta > (mask / 2)) {
806 delta = ((uint32_t)(time & mask) - in_timestamp);
815 #ifdef RTE_LIBRTE_IAVF_DEBUG_DUMP_DESC
816 #define IAVF_DUMP_RX_DESC(rxq, desc, rx_id) \
817 iavf_dump_rx_descriptor(rxq, desc, rx_id)
818 #define IAVF_DUMP_TX_DESC(txq, desc, tx_id) \
819 iavf_dump_tx_descriptor(txq, desc, tx_id)
821 #define IAVF_DUMP_RX_DESC(rxq, desc, rx_id) do { } while (0)
822 #define IAVF_DUMP_TX_DESC(txq, desc, tx_id) do { } while (0)
825 #endif /* _IAVF_RXTX_H_ */