drivers/net/iavf/iavf_rxtx.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2017 Intel Corporation
   3  */
   4
   5 #ifndef _IAVF_RXTX_H_
   6 #define _IAVF_RXTX_H_
   7
   8 /* In QLEN must be whole number of 32 descriptors. */
   9 #define IAVF_ALIGN_RING_DESC      32
  10 #define IAVF_MIN_RING_DESC        64
  11 #define IAVF_MAX_RING_DESC        4096
  12 #define IAVF_DMA_MEM_ALIGN        4096
  13 /* Base address of the HW descriptor ring should be 128B aligned. */
  14 #define IAVF_RING_BASE_ALIGN      128
  15
  16 /* used for Rx Bulk Allocate */
  17 #define IAVF_RX_MAX_BURST         32
  18
  19 /* used for Vector PMD */
  20 #define IAVF_VPMD_RX_MAX_BURST    32
  21 #define IAVF_VPMD_TX_MAX_BURST    32
  22 #define IAVF_RXQ_REARM_THRESH     32
  23 #define IAVF_VPMD_DESCS_PER_LOOP  4
  24 #define IAVF_VPMD_TX_MAX_FREE_BUF 64
  25
  26 #define IAVF_TX_NO_VECTOR_FLAGS (                                \
  27                 DEV_TX_OFFLOAD_MULTI_SEGS |              \
  28                 DEV_TX_OFFLOAD_TCP_TSO)
  29
  30 #define IAVF_TX_VECTOR_OFFLOAD (                                 \
  31                 DEV_TX_OFFLOAD_VLAN_INSERT |             \
  32                 DEV_TX_OFFLOAD_QINQ_INSERT |             \
  33                 DEV_TX_OFFLOAD_IPV4_CKSUM |              \
  34                 DEV_TX_OFFLOAD_SCTP_CKSUM |              \
  35                 DEV_TX_OFFLOAD_UDP_CKSUM |               \
  36                 DEV_TX_OFFLOAD_TCP_CKSUM)
  37
  38 #define IAVF_RX_VECTOR_OFFLOAD (                                 \
  39                 DEV_RX_OFFLOAD_CHECKSUM |                \
  40                 DEV_RX_OFFLOAD_SCTP_CKSUM |              \
  41                 DEV_RX_OFFLOAD_VLAN |            \
  42                 DEV_RX_OFFLOAD_RSS_HASH)
  43
  44 #define IAVF_VECTOR_PATH 0
  45 #define IAVF_VECTOR_OFFLOAD_PATH 1
  46
  47 #define DEFAULT_TX_RS_THRESH     32
  48 #define DEFAULT_TX_FREE_THRESH   32
  49
  50 #define IAVF_MIN_TSO_MSS          88
  51 #define IAVF_MAX_TSO_MSS          9668
  52 #define IAVF_TSO_MAX_SEG          UINT8_MAX
  53 #define IAVF_TX_MAX_MTU_SEG       8
  54
  55 #define IAVF_TX_CKSUM_OFFLOAD_MASK (             \
  56                 PKT_TX_IP_CKSUM |                \
  57                 PKT_TX_L4_MASK |                 \
  58                 PKT_TX_TCP_SEG)
  59
  60 #define IAVF_TX_OFFLOAD_MASK (  \
  61                 PKT_TX_OUTER_IPV6 |              \
  62                 PKT_TX_OUTER_IPV4 |              \
  63                 PKT_TX_IPV6 |                    \
  64                 PKT_TX_IPV4 |                    \
  65                 PKT_TX_VLAN_PKT |                \
  66                 PKT_TX_IP_CKSUM |                \
  67                 PKT_TX_L4_MASK |                 \
  68                 PKT_TX_TCP_SEG)
  69
  70 #define IAVF_TX_OFFLOAD_NOTSUP_MASK \
  71                 (PKT_TX_OFFLOAD_MASK ^ IAVF_TX_OFFLOAD_MASK)
  72
  73 /**
  74  * Rx Flex Descriptors
  75  * These descriptors are used instead of the legacy version descriptors
  76  */
  77 union iavf_16b_rx_flex_desc {
  78         struct {
  79                 __le64 pkt_addr; /* Packet buffer address */
  80                 __le64 hdr_addr; /* Header buffer address */
  81                                  /* bit 0 of hdr_addr is DD bit */
  82         } read;
  83         struct {
  84                 /* Qword 0 */
  85                 u8 rxdid; /* descriptor builder profile ID */
  86                 u8 mir_id_umb_cast; /* mirror=[5:0], umb=[7:6] */
  87                 __le16 ptype_flex_flags0; /* ptype=[9:0], ff0=[15:10] */
  88                 __le16 pkt_len; /* [15:14] are reserved */
  89                 __le16 hdr_len_sph_flex_flags1; /* header=[10:0] */
  90                                                 /* sph=[11:11] */
  91                                                 /* ff1/ext=[15:12] */
  92
  93                 /* Qword 1 */
  94                 __le16 status_error0;
  95                 __le16 l2tag1;
  96                 __le16 flex_meta0;
  97                 __le16 flex_meta1;
  98         } wb; /* writeback */
  99 };
 100
 101 union iavf_32b_rx_flex_desc {
 102         struct {
 103                 __le64 pkt_addr; /* Packet buffer address */
 104                 __le64 hdr_addr; /* Header buffer address */
 105                                  /* bit 0 of hdr_addr is DD bit */
 106                 __le64 rsvd1;
 107                 __le64 rsvd2;
 108         } read;
 109         struct {
 110                 /* Qword 0 */
 111                 u8 rxdid; /* descriptor builder profile ID */
 112                 u8 mir_id_umb_cast; /* mirror=[5:0], umb=[7:6] */
 113                 __le16 ptype_flex_flags0; /* ptype=[9:0], ff0=[15:10] */
 114                 __le16 pkt_len; /* [15:14] are reserved */
 115                 __le16 hdr_len_sph_flex_flags1; /* header=[10:0] */
 116                                                 /* sph=[11:11] */
 117                                                 /* ff1/ext=[15:12] */
 118
 119                 /* Qword 1 */
 120                 __le16 status_error0;
 121                 __le16 l2tag1;
 122                 __le16 flex_meta0;
 123                 __le16 flex_meta1;
 124
 125                 /* Qword 2 */
 126                 __le16 status_error1;
 127                 u8 flex_flags2;
 128                 u8 time_stamp_low;
 129                 __le16 l2tag2_1st;
 130                 __le16 l2tag2_2nd;
 131
 132                 /* Qword 3 */
 133                 __le16 flex_meta2;
 134                 __le16 flex_meta3;
 135                 union {
 136                         struct {
 137                                 __le16 flex_meta4;
 138                                 __le16 flex_meta5;
 139                         } flex;
 140                         __le32 ts_high;
 141                 } flex_ts;
 142         } wb; /* writeback */
 143 };
 144
 145 /* HW desc structure, both 16-byte and 32-byte types are supported */
 146 #ifdef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
 147 #define iavf_rx_desc iavf_16byte_rx_desc
 148 #define iavf_rx_flex_desc iavf_16b_rx_flex_desc
 149 #else
 150 #define iavf_rx_desc iavf_32byte_rx_desc
 151 #define iavf_rx_flex_desc iavf_32b_rx_flex_desc
 152 #endif
 153
 154 typedef void (*iavf_rxd_to_pkt_fields_t)(struct iavf_rx_queue *rxq,
 155                                 struct rte_mbuf *mb,
 156                                 volatile union iavf_rx_flex_desc *rxdp);
 157
 158 struct iavf_rxq_ops {
 159         void (*release_mbufs)(struct iavf_rx_queue *rxq);
 160 };
 161
 162 struct iavf_txq_ops {
 163         void (*release_mbufs)(struct iavf_tx_queue *txq);
 164 };
 165
 166 /* Structure associated with each Rx queue. */
 167 struct iavf_rx_queue {
 168         struct rte_mempool *mp;       /* mbuf pool to populate Rx ring */
 169         const struct rte_memzone *mz; /* memzone for Rx ring */
 170         volatile union iavf_rx_desc *rx_ring; /* Rx ring virtual address */
 171         uint64_t rx_ring_phys_addr;   /* Rx ring DMA address */
 172         struct rte_mbuf **sw_ring;     /* address of SW ring */
 173         uint16_t nb_rx_desc;          /* ring length */
 174         uint16_t rx_tail;             /* current value of tail */
 175         volatile uint8_t *qrx_tail;   /* register address of tail */
 176         uint16_t rx_free_thresh;      /* max free RX desc to hold */
 177         uint16_t nb_rx_hold;          /* number of held free RX desc */
 178         struct rte_mbuf *pkt_first_seg; /* first segment of current packet */
 179         struct rte_mbuf *pkt_last_seg;  /* last segment of current packet */
 180         struct rte_mbuf fake_mbuf;      /* dummy mbuf */
 181         uint8_t rxdid;
 182
 183         /* used for VPMD */
 184         uint16_t rxrearm_nb;       /* number of remaining to be re-armed */
 185         uint16_t rxrearm_start;    /* the idx we start the re-arming from */
 186         uint64_t mbuf_initializer; /* value to init mbufs */
 187
 188         /* for rx bulk */
 189         uint16_t rx_nb_avail;      /* number of staged packets ready */
 190         uint16_t rx_next_avail;    /* index of next staged packets */
 191         uint16_t rx_free_trigger;  /* triggers rx buffer allocation */
 192         struct rte_mbuf *rx_stage[IAVF_RX_MAX_BURST * 2]; /* store mbuf */
 193
 194         uint16_t port_id;        /* device port ID */
 195         uint8_t crc_len;        /* 0 if CRC stripped, 4 otherwise */
 196         uint8_t fdir_enabled;   /* 0 if FDIR disabled, 1 when enabled */
 197         uint16_t queue_id;      /* Rx queue index */
 198         uint16_t rx_buf_len;    /* The packet buffer size */
 199         uint16_t rx_hdr_len;    /* The header buffer size */
 200         uint16_t max_pkt_len;   /* Maximum packet length */
 201         struct iavf_vsi *vsi; /**< the VSI this queue belongs to */
 202
 203         bool q_set;             /* if rx queue has been configured */
 204         bool rx_deferred_start; /* don't start this queue in dev start */
 205         const struct iavf_rxq_ops *ops;
 206         uint8_t rx_flags;
 207 #define IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG1     BIT(0)
 208 #define IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG2_2   BIT(1)
 209         uint8_t proto_xtr; /* protocol extraction type */
 210         uint64_t xtr_ol_flag;
 211                 /* flexible descriptor metadata extraction offload flag */
 212         iavf_rxd_to_pkt_fields_t rxd_to_pkt_fields;
 213                                 /* handle flexible descriptor by RXDID */
 214         uint64_t offloads;
 215 };
 216
 217 struct iavf_tx_entry {
 218         struct rte_mbuf *mbuf;
 219         uint16_t next_id;
 220         uint16_t last_id;
 221 };
 222
 223 struct iavf_tx_vec_entry {
 224         struct rte_mbuf *mbuf;
 225 };
 226
 227 /* Structure associated with each TX queue. */
 228 struct iavf_tx_queue {
 229         const struct rte_memzone *mz;  /* memzone for Tx ring */
 230         volatile struct iavf_tx_desc *tx_ring; /* Tx ring virtual address */
 231         uint64_t tx_ring_phys_addr;    /* Tx ring DMA address */
 232         struct iavf_tx_entry *sw_ring;  /* address array of SW ring */
 233         uint16_t nb_tx_desc;           /* ring length */
 234         uint16_t tx_tail;              /* current value of tail */
 235         volatile uint8_t *qtx_tail;    /* register address of tail */
 236         /* number of used desc since RS bit set */
 237         uint16_t nb_used;
 238         uint16_t nb_free;
 239         uint16_t last_desc_cleaned;    /* last desc have been cleaned*/
 240         uint16_t free_thresh;
 241         uint16_t rs_thresh;
 242
 243         uint16_t port_id;
 244         uint16_t queue_id;
 245         uint64_t offloads;
 246         uint16_t next_dd;              /* next to set RS, for VPMD */
 247         uint16_t next_rs;              /* next to check DD,  for VPMD */
 248
 249         bool q_set;                    /* if rx queue has been configured */
 250         bool tx_deferred_start;        /* don't start this queue in dev start */
 251         const struct iavf_txq_ops *ops;
 252 #define IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG1       BIT(0)
 253 #define IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG2       BIT(1)
 254         uint8_t vlan_flag;
 255 };
 256
 257 /* Offload features */
 258 union iavf_tx_offload {
 259         uint64_t data;
 260         struct {
 261                 uint64_t l2_len:7; /* L2 (MAC) Header Length. */
 262                 uint64_t l3_len:9; /* L3 (IP) Header Length. */
 263                 uint64_t l4_len:8; /* L4 Header Length. */
 264                 uint64_t tso_segsz:16; /* TCP TSO segment size */
 265                 /* uint64_t unused : 24; */
 266         };
 267 };
 268
 269 /* Rx Flex Descriptor
 270  * RxDID Profile ID 16-21
 271  * Flex-field 0: RSS hash lower 16-bits
 272  * Flex-field 1: RSS hash upper 16-bits
 273  * Flex-field 2: Flow ID lower 16-bits
 274  * Flex-field 3: Flow ID upper 16-bits
 275  * Flex-field 4: AUX0
 276  * Flex-field 5: AUX1
 277  */
 278 struct iavf_32b_rx_flex_desc_comms {
 279         /* Qword 0 */
 280         u8 rxdid;
 281         u8 mir_id_umb_cast;
 282         __le16 ptype_flexi_flags0;
 283         __le16 pkt_len;
 284         __le16 hdr_len_sph_flex_flags1;
 285
 286         /* Qword 1 */
 287         __le16 status_error0;
 288         __le16 l2tag1;
 289         __le32 rss_hash;
 290
 291         /* Qword 2 */
 292         __le16 status_error1;
 293         u8 flexi_flags2;
 294         u8 ts_low;
 295         __le16 l2tag2_1st;
 296         __le16 l2tag2_2nd;
 297
 298         /* Qword 3 */
 299         __le32 flow_id;
 300         union {
 301                 struct {
 302                         __le16 aux0;
 303                         __le16 aux1;
 304                 } flex;
 305                 __le32 ts_high;
 306         } flex_ts;
 307 };
 308
 309 /* Rx Flex Descriptor
 310  * RxDID Profile ID 22-23 (swap Hash and FlowID)
 311  * Flex-field 0: Flow ID lower 16-bits
 312  * Flex-field 1: Flow ID upper 16-bits
 313  * Flex-field 2: RSS hash lower 16-bits
 314  * Flex-field 3: RSS hash upper 16-bits
 315  * Flex-field 4: AUX0
 316  * Flex-field 5: AUX1
 317  */
 318 struct iavf_32b_rx_flex_desc_comms_ovs {
 319         /* Qword 0 */
 320         u8 rxdid;
 321         u8 mir_id_umb_cast;
 322         __le16 ptype_flexi_flags0;
 323         __le16 pkt_len;
 324         __le16 hdr_len_sph_flex_flags1;
 325
 326         /* Qword 1 */
 327         __le16 status_error0;
 328         __le16 l2tag1;
 329         __le32 flow_id;
 330
 331         /* Qword 2 */
 332         __le16 status_error1;
 333         u8 flexi_flags2;
 334         u8 ts_low;
 335         __le16 l2tag2_1st;
 336         __le16 l2tag2_2nd;
 337
 338         /* Qword 3 */
 339         __le32 rss_hash;
 340         union {
 341                 struct {
 342                         __le16 aux0;
 343                         __le16 aux1;
 344                 } flex;
 345                 __le32 ts_high;
 346         } flex_ts;
 347 };
 348
 349 /* Receive Flex Descriptor profile IDs: There are a total
 350  * of 64 profiles where profile IDs 0/1 are for legacy; and
 351  * profiles 2-63 are flex profiles that can be programmed
 352  * with a specific metadata (profile 7 reserved for HW)
 353  */
 354 enum iavf_rxdid {
 355         IAVF_RXDID_LEGACY_0             = 0,
 356         IAVF_RXDID_LEGACY_1             = 1,
 357         IAVF_RXDID_FLEX_NIC             = 2,
 358         IAVF_RXDID_FLEX_NIC_2           = 6,
 359         IAVF_RXDID_HW                   = 7,
 360         IAVF_RXDID_COMMS_GENERIC        = 16,
 361         IAVF_RXDID_COMMS_AUX_VLAN       = 17,
 362         IAVF_RXDID_COMMS_AUX_IPV4       = 18,
 363         IAVF_RXDID_COMMS_AUX_IPV6       = 19,
 364         IAVF_RXDID_COMMS_AUX_IPV6_FLOW  = 20,
 365         IAVF_RXDID_COMMS_AUX_TCP        = 21,
 366         IAVF_RXDID_COMMS_OVS_1          = 22,
 367         IAVF_RXDID_COMMS_OVS_2          = 23,
 368         IAVF_RXDID_COMMS_AUX_IP_OFFSET  = 25,
 369         IAVF_RXDID_LAST                 = 63,
 370 };
 371
 372 enum iavf_rx_flex_desc_status_error_0_bits {
 373         /* Note: These are predefined bit offsets */
 374         IAVF_RX_FLEX_DESC_STATUS0_DD_S = 0,
 375         IAVF_RX_FLEX_DESC_STATUS0_EOF_S,
 376         IAVF_RX_FLEX_DESC_STATUS0_HBO_S,
 377         IAVF_RX_FLEX_DESC_STATUS0_L3L4P_S,
 378         IAVF_RX_FLEX_DESC_STATUS0_XSUM_IPE_S,
 379         IAVF_RX_FLEX_DESC_STATUS0_XSUM_L4E_S,
 380         IAVF_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S,
 381         IAVF_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S,
 382         IAVF_RX_FLEX_DESC_STATUS0_LPBK_S,
 383         IAVF_RX_FLEX_DESC_STATUS0_IPV6EXADD_S,
 384         IAVF_RX_FLEX_DESC_STATUS0_RXE_S,
 385         IAVF_RX_FLEX_DESC_STATUS0_CRCP_S,
 386         IAVF_RX_FLEX_DESC_STATUS0_RSS_VALID_S,
 387         IAVF_RX_FLEX_DESC_STATUS0_L2TAG1P_S,
 388         IAVF_RX_FLEX_DESC_STATUS0_XTRMD0_VALID_S,
 389         IAVF_RX_FLEX_DESC_STATUS0_XTRMD1_VALID_S,
 390         IAVF_RX_FLEX_DESC_STATUS0_LAST /* this entry must be last!!! */
 391 };
 392
 393 enum iavf_rx_flex_desc_status_error_1_bits {
 394         /* Note: These are predefined bit offsets */
 395         IAVF_RX_FLEX_DESC_STATUS1_CPM_S = 0, /* 4 bits */
 396         IAVF_RX_FLEX_DESC_STATUS1_NAT_S = 4,
 397         IAVF_RX_FLEX_DESC_STATUS1_CRYPTO_S = 5,
 398         /* [10:6] reserved */
 399         IAVF_RX_FLEX_DESC_STATUS1_L2TAG2P_S = 11,
 400         IAVF_RX_FLEX_DESC_STATUS1_XTRMD2_VALID_S = 12,
 401         IAVF_RX_FLEX_DESC_STATUS1_XTRMD3_VALID_S = 13,
 402         IAVF_RX_FLEX_DESC_STATUS1_XTRMD4_VALID_S = 14,
 403         IAVF_RX_FLEX_DESC_STATUS1_XTRMD5_VALID_S = 15,
 404         IAVF_RX_FLEX_DESC_STATUS1_LAST /* this entry must be last!!! */
 405 };
 406
 407 /* for iavf_32b_rx_flex_desc.ptype_flex_flags0 member */
 408 #define IAVF_RX_FLEX_DESC_PTYPE_M       (0x3FF) /* 10-bits */
 409
 410 /* for iavf_32b_rx_flex_desc.pkt_len member */
 411 #define IAVF_RX_FLX_DESC_PKT_LEN_M      (0x3FFF) /* 14-bits */
 412
 413 int iavf_dev_rx_queue_setup(struct rte_eth_dev *dev,
 414                            uint16_t queue_idx,
 415                            uint16_t nb_desc,
 416                            unsigned int socket_id,
 417                            const struct rte_eth_rxconf *rx_conf,
 418                            struct rte_mempool *mp);
 419
 420 int iavf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
 421 int iavf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
 422 void iavf_dev_rx_queue_release(void *rxq);
 423
 424 int iavf_dev_tx_queue_setup(struct rte_eth_dev *dev,
 425                            uint16_t queue_idx,
 426                            uint16_t nb_desc,
 427                            unsigned int socket_id,
 428                            const struct rte_eth_txconf *tx_conf);
 429 int iavf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
 430 int iavf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);
 431 int iavf_dev_tx_done_cleanup(void *txq, uint32_t free_cnt);
 432 void iavf_dev_tx_queue_release(void *txq);
 433 void iavf_stop_queues(struct rte_eth_dev *dev);
 434 uint16_t iavf_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
 435                        uint16_t nb_pkts);
 436 uint16_t iavf_recv_pkts_flex_rxd(void *rx_queue,
 437                                  struct rte_mbuf **rx_pkts,
 438                                  uint16_t nb_pkts);
 439 uint16_t iavf_recv_scattered_pkts(void *rx_queue,
 440                                  struct rte_mbuf **rx_pkts,
 441                                  uint16_t nb_pkts);
 442 uint16_t iavf_recv_scattered_pkts_flex_rxd(void *rx_queue,
 443                                            struct rte_mbuf **rx_pkts,
 444                                            uint16_t nb_pkts);
 445 uint16_t iavf_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 446                        uint16_t nb_pkts);
 447 uint16_t iavf_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 448                        uint16_t nb_pkts);
 449 void iavf_set_rx_function(struct rte_eth_dev *dev);
 450 void iavf_set_tx_function(struct rte_eth_dev *dev);
 451 void iavf_dev_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
 452                           struct rte_eth_rxq_info *qinfo);
 453 void iavf_dev_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
 454                           struct rte_eth_txq_info *qinfo);
 455 uint32_t iavf_dev_rxq_count(struct rte_eth_dev *dev, uint16_t queue_id);
 456 int iavf_dev_rx_desc_status(void *rx_queue, uint16_t offset);
 457 int iavf_dev_tx_desc_status(void *tx_queue, uint16_t offset);
 458
 459 uint16_t iavf_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
 460                            uint16_t nb_pkts);
 461 uint16_t iavf_recv_pkts_vec_flex_rxd(void *rx_queue, struct rte_mbuf **rx_pkts,
 462                                      uint16_t nb_pkts);
 463 uint16_t iavf_recv_scattered_pkts_vec(void *rx_queue,
 464                                      struct rte_mbuf **rx_pkts,
 465                                      uint16_t nb_pkts);
 466 uint16_t iavf_recv_scattered_pkts_vec_flex_rxd(void *rx_queue,
 467                                                struct rte_mbuf **rx_pkts,
 468                                                uint16_t nb_pkts);
 469 uint16_t iavf_xmit_fixed_burst_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
 470                                   uint16_t nb_pkts);
 471 uint16_t iavf_recv_pkts_vec_avx2(void *rx_queue, struct rte_mbuf **rx_pkts,
 472                                  uint16_t nb_pkts);
 473 uint16_t iavf_recv_pkts_vec_avx2_flex_rxd(void *rx_queue,
 474                                           struct rte_mbuf **rx_pkts,
 475                                           uint16_t nb_pkts);
 476 uint16_t iavf_recv_scattered_pkts_vec_avx2(void *rx_queue,
 477                                            struct rte_mbuf **rx_pkts,
 478                                            uint16_t nb_pkts);
 479 uint16_t iavf_recv_scattered_pkts_vec_avx2_flex_rxd(void *rx_queue,
 480                                                     struct rte_mbuf **rx_pkts,
 481                                                     uint16_t nb_pkts);
 482 uint16_t iavf_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
 483                             uint16_t nb_pkts);
 484 uint16_t iavf_xmit_pkts_vec_avx2(void *tx_queue, struct rte_mbuf **tx_pkts,
 485                                  uint16_t nb_pkts);
 486 int iavf_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc);
 487 int iavf_rx_vec_dev_check(struct rte_eth_dev *dev);
 488 int iavf_tx_vec_dev_check(struct rte_eth_dev *dev);
 489 int iavf_rxq_vec_setup(struct iavf_rx_queue *rxq);
 490 int iavf_txq_vec_setup(struct iavf_tx_queue *txq);
 491 uint16_t iavf_recv_pkts_vec_avx512(void *rx_queue, struct rte_mbuf **rx_pkts,
 492                                    uint16_t nb_pkts);
 493 uint16_t iavf_recv_pkts_vec_avx512_offload(void *rx_queue,
 494                                            struct rte_mbuf **rx_pkts,
 495                                            uint16_t nb_pkts);
 496 uint16_t iavf_recv_pkts_vec_avx512_flex_rxd(void *rx_queue,
 497                                             struct rte_mbuf **rx_pkts,
 498                                             uint16_t nb_pkts);
 499 uint16_t iavf_recv_pkts_vec_avx512_flex_rxd_offload(void *rx_queue,
 500                                                     struct rte_mbuf **rx_pkts,
 501                                                     uint16_t nb_pkts);
 502 uint16_t iavf_recv_scattered_pkts_vec_avx512(void *rx_queue,
 503                                              struct rte_mbuf **rx_pkts,
 504                                              uint16_t nb_pkts);
 505 uint16_t iavf_recv_scattered_pkts_vec_avx512_offload(void *rx_queue,
 506                                                      struct rte_mbuf **rx_pkts,
 507                                                      uint16_t nb_pkts);
 508 uint16_t iavf_recv_scattered_pkts_vec_avx512_flex_rxd(void *rx_queue,
 509                                                       struct rte_mbuf **rx_pkts,
 510                                                       uint16_t nb_pkts);
 511 uint16_t iavf_recv_scattered_pkts_vec_avx512_flex_rxd_offload(void *rx_queue,
 512                                                               struct rte_mbuf **rx_pkts,
 513                                                               uint16_t nb_pkts);
 514 uint16_t iavf_xmit_pkts_vec_avx512(void *tx_queue, struct rte_mbuf **tx_pkts,
 515                                    uint16_t nb_pkts);
 516 uint16_t iavf_xmit_pkts_vec_avx512_offload(void *tx_queue,
 517                                            struct rte_mbuf **tx_pkts,
 518                                            uint16_t nb_pkts);
 519 int iavf_txq_vec_setup_avx512(struct iavf_tx_queue *txq);
 520
 521 uint8_t iavf_proto_xtr_type_to_rxdid(uint8_t xtr_type);
 522
 523 const uint32_t *iavf_get_default_ptype_table(void);
 524
 525 static inline
 526 void iavf_dump_rx_descriptor(struct iavf_rx_queue *rxq,
 527                             const volatile void *desc,
 528                             uint16_t rx_id)
 529 {
 530 #ifdef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
 531         const volatile union iavf_16byte_rx_desc *rx_desc = desc;
 532
 533         printf("Queue %d Rx_desc %d: QW0: 0x%016"PRIx64" QW1: 0x%016"PRIx64"\n",
 534                rxq->queue_id, rx_id, rx_desc->read.pkt_addr,
 535                rx_desc->read.hdr_addr);
 536 #else
 537         const volatile union iavf_32byte_rx_desc *rx_desc = desc;
 538
 539         printf("Queue %d Rx_desc %d: QW0: 0x%016"PRIx64" QW1: 0x%016"PRIx64
 540                " QW2: 0x%016"PRIx64" QW3: 0x%016"PRIx64"\n", rxq->queue_id,
 541                rx_id, rx_desc->read.pkt_addr, rx_desc->read.hdr_addr,
 542                rx_desc->read.rsvd1, rx_desc->read.rsvd2);
 543 #endif
 544 }
 545
 546 /* All the descriptors are 16 bytes, so just use one of them
 547  * to print the qwords
 548  */
 549 static inline
 550 void iavf_dump_tx_descriptor(const struct iavf_tx_queue *txq,
 551                             const volatile void *desc, uint16_t tx_id)
 552 {
 553         const char *name;
 554         const volatile struct iavf_tx_desc *tx_desc = desc;
 555         enum iavf_tx_desc_dtype_value type;
 556
 557         type = (enum iavf_tx_desc_dtype_value)rte_le_to_cpu_64(
 558                 tx_desc->cmd_type_offset_bsz &
 559                 rte_cpu_to_le_64(IAVF_TXD_QW1_DTYPE_MASK));
 560         switch (type) {
 561         case IAVF_TX_DESC_DTYPE_DATA:
 562                 name = "Tx_data_desc";
 563                 break;
 564         case IAVF_TX_DESC_DTYPE_CONTEXT:
 565                 name = "Tx_context_desc";
 566                 break;
 567         default:
 568                 name = "unknown_desc";
 569                 break;
 570         }
 571
 572         printf("Queue %d %s %d: QW0: 0x%016"PRIx64" QW1: 0x%016"PRIx64"\n",
 573                txq->queue_id, name, tx_id, tx_desc->buffer_addr,
 574                tx_desc->cmd_type_offset_bsz);
 575 }
 576
 577 #define FDIR_PROC_ENABLE_PER_QUEUE(ad, on) do { \
 578         int i; \
 579         for (i = 0; i < (ad)->eth_dev->data->nb_rx_queues; i++) { \
 580                 struct iavf_rx_queue *rxq = (ad)->eth_dev->data->rx_queues[i]; \
 581                 if (!rxq) \
 582                         continue; \
 583                 rxq->fdir_enabled = on; \
 584         } \
 585         PMD_DRV_LOG(DEBUG, "FDIR processing on RX set to %d", on); \
 586 } while (0)
 587
 588 /* Enable/disable flow director Rx processing in data path. */
 589 static inline
 590 void iavf_fdir_rx_proc_enable(struct iavf_adapter *ad, bool on)
 591 {
 592         if (on) {
 593                 /* enable flow director processing */
 594                 FDIR_PROC_ENABLE_PER_QUEUE(ad, on);
 595                 ad->fdir_ref_cnt++;
 596         } else {
 597                 if (ad->fdir_ref_cnt >= 1) {
 598                         ad->fdir_ref_cnt--;
 599
 600                         if (ad->fdir_ref_cnt == 0)
 601                                 FDIR_PROC_ENABLE_PER_QUEUE(ad, on);
 602                 }
 603         }
 604 }
 605
 606 #ifdef RTE_LIBRTE_IAVF_DEBUG_DUMP_DESC
 607 #define IAVF_DUMP_RX_DESC(rxq, desc, rx_id) \
 608         iavf_dump_rx_descriptor(rxq, desc, rx_id)
 609 #define IAVF_DUMP_TX_DESC(txq, desc, tx_id) \
 610         iavf_dump_tx_descriptor(txq, desc, tx_id)
 611 #else
 612 #define IAVF_DUMP_RX_DESC(rxq, desc, rx_id) do { } while (0)
 613 #define IAVF_DUMP_TX_DESC(txq, desc, tx_id) do { } while (0)
 614 #endif
 615
 616 #endif /* _IAVF_RXTX_H_ */