net/virtio-user: fix setting filters
[dpdk.git] / drivers / net / iavf / iavf_rxtx.h
1 /* SPDX-License-Identifier: BSD-3-Clause
2  * Copyright(c) 2017 Intel Corporation
3  */
4
5 #ifndef _IAVF_RXTX_H_
6 #define _IAVF_RXTX_H_
7
8 /* In QLEN must be whole number of 32 descriptors. */
9 #define IAVF_ALIGN_RING_DESC      32
10 #define IAVF_MIN_RING_DESC        64
11 #define IAVF_MAX_RING_DESC        4096
12 #define IAVF_DMA_MEM_ALIGN        4096
13 /* Base address of the HW descriptor ring should be 128B aligned. */
14 #define IAVF_RING_BASE_ALIGN      128
15
16 /* used for Rx Bulk Allocate */
17 #define IAVF_RX_MAX_BURST         32
18
19 /* used for Vector PMD */
20 #define IAVF_VPMD_RX_MAX_BURST    32
21 #define IAVF_VPMD_TX_MAX_BURST    32
22 #define IAVF_RXQ_REARM_THRESH     32
23 #define IAVF_VPMD_DESCS_PER_LOOP  4
24 #define IAVF_VPMD_TX_MAX_FREE_BUF 64
25
26 #define IAVF_NO_VECTOR_FLAGS (                           \
27                 DEV_TX_OFFLOAD_MULTI_SEGS |              \
28                 DEV_TX_OFFLOAD_VLAN_INSERT |             \
29                 DEV_TX_OFFLOAD_SCTP_CKSUM |              \
30                 DEV_TX_OFFLOAD_UDP_CKSUM |               \
31                 DEV_TX_OFFLOAD_TCP_CKSUM)
32
33 #define DEFAULT_TX_RS_THRESH     32
34 #define DEFAULT_TX_FREE_THRESH   32
35
36 #define IAVF_MIN_TSO_MSS          256
37 #define IAVF_MAX_TSO_MSS          9668
38 #define IAVF_TSO_MAX_SEG          UINT8_MAX
39 #define IAVF_TX_MAX_MTU_SEG       8
40
41 #define IAVF_TX_CKSUM_OFFLOAD_MASK (             \
42                 PKT_TX_IP_CKSUM |                \
43                 PKT_TX_L4_MASK |                 \
44                 PKT_TX_TCP_SEG)
45
46 #define IAVF_TX_OFFLOAD_MASK (  \
47                 PKT_TX_OUTER_IPV6 |              \
48                 PKT_TX_OUTER_IPV4 |              \
49                 PKT_TX_IPV6 |                    \
50                 PKT_TX_IPV4 |                    \
51                 PKT_TX_VLAN_PKT |                \
52                 PKT_TX_IP_CKSUM |                \
53                 PKT_TX_L4_MASK |                 \
54                 PKT_TX_TCP_SEG)
55
56 #define IAVF_TX_OFFLOAD_NOTSUP_MASK \
57                 (PKT_TX_OFFLOAD_MASK ^ IAVF_TX_OFFLOAD_MASK)
58
59 /* HW desc structure, both 16-byte and 32-byte types are supported */
60 #ifdef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
61 #define iavf_rx_desc iavf_16byte_rx_desc
62 #else
63 #define iavf_rx_desc iavf_32byte_rx_desc
64 #endif
65
66 struct iavf_rxq_ops {
67         void (*release_mbufs)(struct iavf_rx_queue *rxq);
68 };
69
70 struct iavf_txq_ops {
71         void (*release_mbufs)(struct iavf_tx_queue *txq);
72 };
73
74 /* Structure associated with each Rx queue. */
75 struct iavf_rx_queue {
76         struct rte_mempool *mp;       /* mbuf pool to populate Rx ring */
77         const struct rte_memzone *mz; /* memzone for Rx ring */
78         volatile union iavf_rx_desc *rx_ring; /* Rx ring virtual address */
79         uint64_t rx_ring_phys_addr;   /* Rx ring DMA address */
80         struct rte_mbuf **sw_ring;     /* address of SW ring */
81         uint16_t nb_rx_desc;          /* ring length */
82         uint16_t rx_tail;             /* current value of tail */
83         volatile uint8_t *qrx_tail;   /* register address of tail */
84         uint16_t rx_free_thresh;      /* max free RX desc to hold */
85         uint16_t nb_rx_hold;          /* number of held free RX desc */
86         struct rte_mbuf *pkt_first_seg; /* first segment of current packet */
87         struct rte_mbuf *pkt_last_seg;  /* last segment of current packet */
88         struct rte_mbuf fake_mbuf;      /* dummy mbuf */
89
90         /* used for VPMD */
91         uint16_t rxrearm_nb;       /* number of remaining to be re-armed */
92         uint16_t rxrearm_start;    /* the idx we start the re-arming from */
93         uint64_t mbuf_initializer; /* value to init mbufs */
94
95         /* for rx bulk */
96         uint16_t rx_nb_avail;      /* number of staged packets ready */
97         uint16_t rx_next_avail;    /* index of next staged packets */
98         uint16_t rx_free_trigger;  /* triggers rx buffer allocation */
99         struct rte_mbuf *rx_stage[IAVF_RX_MAX_BURST * 2]; /* store mbuf */
100
101         uint16_t port_id;        /* device port ID */
102         uint8_t crc_len;        /* 0 if CRC stripped, 4 otherwise */
103         uint16_t queue_id;      /* Rx queue index */
104         uint16_t rx_buf_len;    /* The packet buffer size */
105         uint16_t rx_hdr_len;    /* The header buffer size */
106         uint16_t max_pkt_len;   /* Maximum packet length */
107
108         bool q_set;             /* if rx queue has been configured */
109         bool rx_deferred_start; /* don't start this queue in dev start */
110         const struct iavf_rxq_ops *ops;
111 };
112
113 struct iavf_tx_entry {
114         struct rte_mbuf *mbuf;
115         uint16_t next_id;
116         uint16_t last_id;
117 };
118
119 /* Structure associated with each TX queue. */
120 struct iavf_tx_queue {
121         const struct rte_memzone *mz;  /* memzone for Tx ring */
122         volatile struct iavf_tx_desc *tx_ring; /* Tx ring virtual address */
123         uint64_t tx_ring_phys_addr;    /* Tx ring DMA address */
124         struct iavf_tx_entry *sw_ring;  /* address array of SW ring */
125         uint16_t nb_tx_desc;           /* ring length */
126         uint16_t tx_tail;              /* current value of tail */
127         volatile uint8_t *qtx_tail;    /* register address of tail */
128         /* number of used desc since RS bit set */
129         uint16_t nb_used;
130         uint16_t nb_free;
131         uint16_t last_desc_cleaned;    /* last desc have been cleaned*/
132         uint16_t free_thresh;
133         uint16_t rs_thresh;
134
135         uint16_t port_id;
136         uint16_t queue_id;
137         uint64_t offloads;
138         uint16_t next_dd;              /* next to set RS, for VPMD */
139         uint16_t next_rs;              /* next to check DD,  for VPMD */
140
141         bool q_set;                    /* if rx queue has been configured */
142         bool tx_deferred_start;        /* don't start this queue in dev start */
143         const struct iavf_txq_ops *ops;
144 };
145
146 /* Offload features */
147 union iavf_tx_offload {
148         uint64_t data;
149         struct {
150                 uint64_t l2_len:7; /* L2 (MAC) Header Length. */
151                 uint64_t l3_len:9; /* L3 (IP) Header Length. */
152                 uint64_t l4_len:8; /* L4 Header Length. */
153                 uint64_t tso_segsz:16; /* TCP TSO segment size */
154                 /* uint64_t unused : 24; */
155         };
156 };
157
158 int iavf_dev_rx_queue_setup(struct rte_eth_dev *dev,
159                            uint16_t queue_idx,
160                            uint16_t nb_desc,
161                            unsigned int socket_id,
162                            const struct rte_eth_rxconf *rx_conf,
163                            struct rte_mempool *mp);
164
165 int iavf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
166 int iavf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
167 void iavf_dev_rx_queue_release(void *rxq);
168
169 int iavf_dev_tx_queue_setup(struct rte_eth_dev *dev,
170                            uint16_t queue_idx,
171                            uint16_t nb_desc,
172                            unsigned int socket_id,
173                            const struct rte_eth_txconf *tx_conf);
174 int iavf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
175 int iavf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);
176 void iavf_dev_tx_queue_release(void *txq);
177 void iavf_stop_queues(struct rte_eth_dev *dev);
178 uint16_t iavf_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
179                        uint16_t nb_pkts);
180 uint16_t iavf_recv_scattered_pkts(void *rx_queue,
181                                  struct rte_mbuf **rx_pkts,
182                                  uint16_t nb_pkts);
183 uint16_t iavf_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
184                        uint16_t nb_pkts);
185 uint16_t iavf_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
186                        uint16_t nb_pkts);
187 void iavf_set_rx_function(struct rte_eth_dev *dev);
188 void iavf_set_tx_function(struct rte_eth_dev *dev);
189 void iavf_dev_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
190                           struct rte_eth_rxq_info *qinfo);
191 void iavf_dev_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
192                           struct rte_eth_txq_info *qinfo);
193 uint32_t iavf_dev_rxq_count(struct rte_eth_dev *dev, uint16_t queue_id);
194 int iavf_dev_rx_desc_status(void *rx_queue, uint16_t offset);
195 int iavf_dev_tx_desc_status(void *tx_queue, uint16_t offset);
196
197 uint16_t iavf_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
198                            uint16_t nb_pkts);
199 uint16_t iavf_recv_scattered_pkts_vec(void *rx_queue,
200                                      struct rte_mbuf **rx_pkts,
201                                      uint16_t nb_pkts);
202 uint16_t iavf_xmit_fixed_burst_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
203                                   uint16_t nb_pkts);
204 uint16_t iavf_recv_pkts_vec_avx2(void *rx_queue, struct rte_mbuf **rx_pkts,
205                                  uint16_t nb_pkts);
206 uint16_t iavf_recv_scattered_pkts_vec_avx2(void *rx_queue,
207                                            struct rte_mbuf **rx_pkts,
208                                            uint16_t nb_pkts);
209 uint16_t iavf_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
210                             uint16_t nb_pkts);
211 uint16_t iavf_xmit_pkts_vec_avx2(void *tx_queue, struct rte_mbuf **tx_pkts,
212                                  uint16_t nb_pkts);
213 int iavf_rx_vec_dev_check(struct rte_eth_dev *dev);
214 int iavf_tx_vec_dev_check(struct rte_eth_dev *dev);
215 int iavf_rxq_vec_setup(struct iavf_rx_queue *rxq);
216 int iavf_txq_vec_setup(struct iavf_tx_queue *txq);
217
218 static inline
219 void iavf_dump_rx_descriptor(struct iavf_rx_queue *rxq,
220                             const volatile void *desc,
221                             uint16_t rx_id)
222 {
223 #ifdef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
224         const volatile union iavf_16byte_rx_desc *rx_desc = desc;
225
226         printf("Queue %d Rx_desc %d: QW0: 0x%016"PRIx64" QW1: 0x%016"PRIx64"\n",
227                rxq->queue_id, rx_id, rx_desc->read.pkt_addr,
228                rx_desc->read.hdr_addr);
229 #else
230         const volatile union iavf_32byte_rx_desc *rx_desc = desc;
231
232         printf("Queue %d Rx_desc %d: QW0: 0x%016"PRIx64" QW1: 0x%016"PRIx64
233                " QW2: 0x%016"PRIx64" QW3: 0x%016"PRIx64"\n", rxq->queue_id,
234                rx_id, rx_desc->read.pkt_addr, rx_desc->read.hdr_addr,
235                rx_desc->read.rsvd1, rx_desc->read.rsvd2);
236 #endif
237 }
238
239 /* All the descriptors are 16 bytes, so just use one of them
240  * to print the qwords
241  */
242 static inline
243 void iavf_dump_tx_descriptor(const struct iavf_tx_queue *txq,
244                             const volatile void *desc, uint16_t tx_id)
245 {
246         const char *name;
247         const volatile struct iavf_tx_desc *tx_desc = desc;
248         enum iavf_tx_desc_dtype_value type;
249
250         type = (enum iavf_tx_desc_dtype_value)rte_le_to_cpu_64(
251                 tx_desc->cmd_type_offset_bsz &
252                 rte_cpu_to_le_64(IAVF_TXD_QW1_DTYPE_MASK));
253         switch (type) {
254         case IAVF_TX_DESC_DTYPE_DATA:
255                 name = "Tx_data_desc";
256                 break;
257         case IAVF_TX_DESC_DTYPE_CONTEXT:
258                 name = "Tx_context_desc";
259                 break;
260         default:
261                 name = "unknown_desc";
262                 break;
263         }
264
265         printf("Queue %d %s %d: QW0: 0x%016"PRIx64" QW1: 0x%016"PRIx64"\n",
266                txq->queue_id, name, tx_id, tx_desc->buffer_addr,
267                tx_desc->cmd_type_offset_bsz);
268 }
269
270 #ifdef RTE_LIBRTE_IAVF_DEBUG_DUMP_DESC
271 #define IAVF_DUMP_RX_DESC(rxq, desc, rx_id) \
272         iavf_dump_rx_descriptor(rxq, desc, rx_id)
273 #define IAVF_DUMP_TX_DESC(txq, desc, tx_id) \
274         iavf_dump_tx_descriptor(txq, desc, tx_id)
275 #else
276 #define IAVF_DUMP_RX_DESC(rxq, desc, rx_id) do { } while (0)
277 #define IAVF_DUMP_TX_DESC(txq, desc, tx_id) do { } while (0)
278 #endif
279
280 #endif /* _IAVF_RXTX_H_ */