drivers/net/iavf/iavf_rxtx.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2017 Intel Corporation
   3  */
   4
   5 #ifndef _IAVF_RXTX_H_
   6 #define _IAVF_RXTX_H_
   7
   8 /* In QLEN must be whole number of 32 descriptors. */
   9 #define IAVF_ALIGN_RING_DESC      32
  10 #define IAVF_MIN_RING_DESC        64
  11 #define IAVF_MAX_RING_DESC        4096
  12 #define IAVF_DMA_MEM_ALIGN        4096
  13 /* Base address of the HW descriptor ring should be 128B aligned. */
  14 #define IAVF_RING_BASE_ALIGN      128
  15
  16 /* used for Rx Bulk Allocate */
  17 #define IAVF_RX_MAX_BURST         32
  18
  19 /* used for Vector PMD */
  20 #define IAVF_VPMD_RX_MAX_BURST    32
  21 #define IAVF_VPMD_TX_MAX_BURST    32
  22 #define IAVF_RXQ_REARM_THRESH     32
  23 #define IAVF_VPMD_DESCS_PER_LOOP  4
  24 #define IAVF_VPMD_TX_MAX_FREE_BUF 64
  25
  26 #define IAVF_NO_VECTOR_FLAGS (                           \
  27                 DEV_TX_OFFLOAD_MULTI_SEGS |              \
  28                 DEV_TX_OFFLOAD_VLAN_INSERT |             \
  29                 DEV_TX_OFFLOAD_SCTP_CKSUM |              \
  30                 DEV_TX_OFFLOAD_UDP_CKSUM |               \
  31                 DEV_TX_OFFLOAD_TCP_TSO |                 \
  32                 DEV_TX_OFFLOAD_TCP_CKSUM)
  33
  34 #define DEFAULT_TX_RS_THRESH     32
  35 #define DEFAULT_TX_FREE_THRESH   32
  36
  37 #define IAVF_MIN_TSO_MSS          256
  38 #define IAVF_MAX_TSO_MSS          9668
  39 #define IAVF_TSO_MAX_SEG          UINT8_MAX
  40 #define IAVF_TX_MAX_MTU_SEG       8
  41
  42 #define IAVF_TX_CKSUM_OFFLOAD_MASK (             \
  43                 PKT_TX_IP_CKSUM |                \
  44                 PKT_TX_L4_MASK |                 \
  45                 PKT_TX_TCP_SEG)
  46
  47 #define IAVF_TX_OFFLOAD_MASK (  \
  48                 PKT_TX_OUTER_IPV6 |              \
  49                 PKT_TX_OUTER_IPV4 |              \
  50                 PKT_TX_IPV6 |                    \
  51                 PKT_TX_IPV4 |                    \
  52                 PKT_TX_VLAN_PKT |                \
  53                 PKT_TX_IP_CKSUM |                \
  54                 PKT_TX_L4_MASK |                 \
  55                 PKT_TX_TCP_SEG)
  56
  57 #define IAVF_TX_OFFLOAD_NOTSUP_MASK \
  58                 (PKT_TX_OFFLOAD_MASK ^ IAVF_TX_OFFLOAD_MASK)
  59
  60 /* HW desc structure, both 16-byte and 32-byte types are supported */
  61 #ifdef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
  62 #define iavf_rx_desc iavf_16byte_rx_desc
  63 #define iavf_rx_flex_desc iavf_16b_rx_flex_desc
  64 #else
  65 #define iavf_rx_desc iavf_32byte_rx_desc
  66 #define iavf_rx_flex_desc iavf_32b_rx_flex_desc
  67 #endif
  68
  69 struct iavf_rxq_ops {
  70         void (*release_mbufs)(struct iavf_rx_queue *rxq);
  71 };
  72
  73 struct iavf_txq_ops {
  74         void (*release_mbufs)(struct iavf_tx_queue *txq);
  75 };
  76
  77 /* Structure associated with each Rx queue. */
  78 struct iavf_rx_queue {
  79         struct rte_mempool *mp;       /* mbuf pool to populate Rx ring */
  80         const struct rte_memzone *mz; /* memzone for Rx ring */
  81         volatile union iavf_rx_desc *rx_ring; /* Rx ring virtual address */
  82         uint64_t rx_ring_phys_addr;   /* Rx ring DMA address */
  83         struct rte_mbuf **sw_ring;     /* address of SW ring */
  84         uint16_t nb_rx_desc;          /* ring length */
  85         uint16_t rx_tail;             /* current value of tail */
  86         volatile uint8_t *qrx_tail;   /* register address of tail */
  87         uint16_t rx_free_thresh;      /* max free RX desc to hold */
  88         uint16_t nb_rx_hold;          /* number of held free RX desc */
  89         struct rte_mbuf *pkt_first_seg; /* first segment of current packet */
  90         struct rte_mbuf *pkt_last_seg;  /* last segment of current packet */
  91         struct rte_mbuf fake_mbuf;      /* dummy mbuf */
  92         uint8_t rxdid;
  93
  94         /* used for VPMD */
  95         uint16_t rxrearm_nb;       /* number of remaining to be re-armed */
  96         uint16_t rxrearm_start;    /* the idx we start the re-arming from */
  97         uint64_t mbuf_initializer; /* value to init mbufs */
  98
  99         /* for rx bulk */
 100         uint16_t rx_nb_avail;      /* number of staged packets ready */
 101         uint16_t rx_next_avail;    /* index of next staged packets */
 102         uint16_t rx_free_trigger;  /* triggers rx buffer allocation */
 103         struct rte_mbuf *rx_stage[IAVF_RX_MAX_BURST * 2]; /* store mbuf */
 104
 105         uint16_t port_id;        /* device port ID */
 106         uint8_t crc_len;        /* 0 if CRC stripped, 4 otherwise */
 107         uint8_t fdir_enabled;   /* 0 if FDIR disabled, 1 when enabled */
 108         uint16_t queue_id;      /* Rx queue index */
 109         uint16_t rx_buf_len;    /* The packet buffer size */
 110         uint16_t rx_hdr_len;    /* The header buffer size */
 111         uint16_t max_pkt_len;   /* Maximum packet length */
 112         struct iavf_vsi *vsi; /**< the VSI this queue belongs to */
 113
 114         bool q_set;             /* if rx queue has been configured */
 115         bool rx_deferred_start; /* don't start this queue in dev start */
 116         const struct iavf_rxq_ops *ops;
 117 };
 118
 119 struct iavf_tx_entry {
 120         struct rte_mbuf *mbuf;
 121         uint16_t next_id;
 122         uint16_t last_id;
 123 };
 124
 125 /* Structure associated with each TX queue. */
 126 struct iavf_tx_queue {
 127         const struct rte_memzone *mz;  /* memzone for Tx ring */
 128         volatile struct iavf_tx_desc *tx_ring; /* Tx ring virtual address */
 129         uint64_t tx_ring_phys_addr;    /* Tx ring DMA address */
 130         struct iavf_tx_entry *sw_ring;  /* address array of SW ring */
 131         uint16_t nb_tx_desc;           /* ring length */
 132         uint16_t tx_tail;              /* current value of tail */
 133         volatile uint8_t *qtx_tail;    /* register address of tail */
 134         /* number of used desc since RS bit set */
 135         uint16_t nb_used;
 136         uint16_t nb_free;
 137         uint16_t last_desc_cleaned;    /* last desc have been cleaned*/
 138         uint16_t free_thresh;
 139         uint16_t rs_thresh;
 140
 141         uint16_t port_id;
 142         uint16_t queue_id;
 143         uint64_t offloads;
 144         uint16_t next_dd;              /* next to set RS, for VPMD */
 145         uint16_t next_rs;              /* next to check DD,  for VPMD */
 146
 147         bool q_set;                    /* if rx queue has been configured */
 148         bool tx_deferred_start;        /* don't start this queue in dev start */
 149         const struct iavf_txq_ops *ops;
 150 };
 151
 152 /* Offload features */
 153 union iavf_tx_offload {
 154         uint64_t data;
 155         struct {
 156                 uint64_t l2_len:7; /* L2 (MAC) Header Length. */
 157                 uint64_t l3_len:9; /* L3 (IP) Header Length. */
 158                 uint64_t l4_len:8; /* L4 Header Length. */
 159                 uint64_t tso_segsz:16; /* TCP TSO segment size */
 160                 /* uint64_t unused : 24; */
 161         };
 162 };
 163
 164 /* Rx Flex Descriptors
 165  * These descriptors are used instead of the legacy version descriptors
 166  */
 167 union iavf_16b_rx_flex_desc {
 168         struct {
 169                 __le64 pkt_addr; /* Packet buffer address */
 170                 __le64 hdr_addr; /* Header buffer address */
 171                                  /* bit 0 of hdr_addr is DD bit */
 172         } read;
 173         struct {
 174                 /* Qword 0 */
 175                 u8 rxdid; /* descriptor builder profile ID */
 176                 u8 mir_id_umb_cast; /* mirror=[5:0], umb=[7:6] */
 177                 __le16 ptype_flex_flags0; /* ptype=[9:0], ff0=[15:10] */
 178                 __le16 pkt_len; /* [15:14] are reserved */
 179                 __le16 hdr_len_sph_flex_flags1; /* header=[10:0] */
 180                                                 /* sph=[11:11] */
 181                                                 /* ff1/ext=[15:12] */
 182
 183                 /* Qword 1 */
 184                 __le16 status_error0;
 185                 __le16 l2tag1;
 186                 __le16 flex_meta0;
 187                 __le16 flex_meta1;
 188         } wb; /* writeback */
 189 };
 190
 191 union iavf_32b_rx_flex_desc {
 192         struct {
 193                 __le64 pkt_addr; /* Packet buffer address */
 194                 __le64 hdr_addr; /* Header buffer address */
 195                                  /* bit 0 of hdr_addr is DD bit */
 196                 __le64 rsvd1;
 197                 __le64 rsvd2;
 198         } read;
 199         struct {
 200                 /* Qword 0 */
 201                 u8 rxdid; /* descriptor builder profile ID */
 202                 u8 mir_id_umb_cast; /* mirror=[5:0], umb=[7:6] */
 203                 __le16 ptype_flex_flags0; /* ptype=[9:0], ff0=[15:10] */
 204                 __le16 pkt_len; /* [15:14] are reserved */
 205                 __le16 hdr_len_sph_flex_flags1; /* header=[10:0] */
 206                                                 /* sph=[11:11] */
 207                                                 /* ff1/ext=[15:12] */
 208
 209                 /* Qword 1 */
 210                 __le16 status_error0;
 211                 __le16 l2tag1;
 212                 __le16 flex_meta0;
 213                 __le16 flex_meta1;
 214
 215                 /* Qword 2 */
 216                 __le16 status_error1;
 217                 u8 flex_flags2;
 218                 u8 time_stamp_low;
 219                 __le16 l2tag2_1st;
 220                 __le16 l2tag2_2nd;
 221
 222                 /* Qword 3 */
 223                 __le16 flex_meta2;
 224                 __le16 flex_meta3;
 225                 union {
 226                         struct {
 227                                 __le16 flex_meta4;
 228                                 __le16 flex_meta5;
 229                         } flex;
 230                         __le32 ts_high;
 231                 } flex_ts;
 232         } wb; /* writeback */
 233 };
 234
 235 /* Rx Flex Descriptor
 236  * RxDID Profile ID 16-21
 237  * Flex-field 0: RSS hash lower 16-bits
 238  * Flex-field 1: RSS hash upper 16-bits
 239  * Flex-field 2: Flow ID lower 16-bits
 240  * Flex-field 3: Flow ID upper 16-bits
 241  * Flex-field 4: AUX0
 242  * Flex-field 5: AUX1
 243  */
 244 struct iavf_32b_rx_flex_desc_comms {
 245         /* Qword 0 */
 246         u8 rxdid;
 247         u8 mir_id_umb_cast;
 248         __le16 ptype_flexi_flags0;
 249         __le16 pkt_len;
 250         __le16 hdr_len_sph_flex_flags1;
 251
 252         /* Qword 1 */
 253         __le16 status_error0;
 254         __le16 l2tag1;
 255         __le32 rss_hash;
 256
 257         /* Qword 2 */
 258         __le16 status_error1;
 259         u8 flexi_flags2;
 260         u8 ts_low;
 261         __le16 l2tag2_1st;
 262         __le16 l2tag2_2nd;
 263
 264         /* Qword 3 */
 265         __le32 flow_id;
 266         union {
 267                 struct {
 268                         __le16 aux0;
 269                         __le16 aux1;
 270                 } flex;
 271                 __le32 ts_high;
 272         } flex_ts;
 273 };
 274
 275 /* Rx Flex Descriptor
 276  * RxDID Profile ID 22-23 (swap Hash and FlowID)
 277  * Flex-field 0: Flow ID lower 16-bits
 278  * Flex-field 1: Flow ID upper 16-bits
 279  * Flex-field 2: RSS hash lower 16-bits
 280  * Flex-field 3: RSS hash upper 16-bits
 281  * Flex-field 4: AUX0
 282  * Flex-field 5: AUX1
 283  */
 284 struct iavf_32b_rx_flex_desc_comms_ovs {
 285         /* Qword 0 */
 286         u8 rxdid;
 287         u8 mir_id_umb_cast;
 288         __le16 ptype_flexi_flags0;
 289         __le16 pkt_len;
 290         __le16 hdr_len_sph_flex_flags1;
 291
 292         /* Qword 1 */
 293         __le16 status_error0;
 294         __le16 l2tag1;
 295         __le32 flow_id;
 296
 297         /* Qword 2 */
 298         __le16 status_error1;
 299         u8 flexi_flags2;
 300         u8 ts_low;
 301         __le16 l2tag2_1st;
 302         __le16 l2tag2_2nd;
 303
 304         /* Qword 3 */
 305         __le32 rss_hash;
 306         union {
 307                 struct {
 308                         __le16 aux0;
 309                         __le16 aux1;
 310                 } flex;
 311                 __le32 ts_high;
 312         } flex_ts;
 313 };
 314
 315 /* Receive Flex Descriptor profile IDs: There are a total
 316  * of 64 profiles where profile IDs 0/1 are for legacy; and
 317  * profiles 2-63 are flex profiles that can be programmed
 318  * with a specific metadata (profile 7 reserved for HW)
 319  */
 320 enum iavf_rxdid {
 321         IAVF_RXDID_LEGACY_0             = 0,
 322         IAVF_RXDID_LEGACY_1             = 1,
 323         IAVF_RXDID_FLEX_NIC             = 2,
 324         IAVF_RXDID_FLEX_NIC_2           = 6,
 325         IAVF_RXDID_HW                   = 7,
 326         IAVF_RXDID_COMMS_GENERIC        = 16,
 327         IAVF_RXDID_COMMS_AUX_VLAN       = 17,
 328         IAVF_RXDID_COMMS_AUX_IPV4       = 18,
 329         IAVF_RXDID_COMMS_AUX_IPV6       = 19,
 330         IAVF_RXDID_COMMS_AUX_IPV6_FLOW  = 20,
 331         IAVF_RXDID_COMMS_AUX_TCP        = 21,
 332         IAVF_RXDID_COMMS_OVS_1          = 22,
 333         IAVF_RXDID_COMMS_OVS_2          = 23,
 334         IAVF_RXDID_LAST                 = 63,
 335 };
 336
 337 enum iavf_rx_flex_desc_status_error_0_bits {
 338         /* Note: These are predefined bit offsets */
 339         IAVF_RX_FLEX_DESC_STATUS0_DD_S = 0,
 340         IAVF_RX_FLEX_DESC_STATUS0_EOF_S,
 341         IAVF_RX_FLEX_DESC_STATUS0_HBO_S,
 342         IAVF_RX_FLEX_DESC_STATUS0_L3L4P_S,
 343         IAVF_RX_FLEX_DESC_STATUS0_XSUM_IPE_S,
 344         IAVF_RX_FLEX_DESC_STATUS0_XSUM_L4E_S,
 345         IAVF_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S,
 346         IAVF_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S,
 347         IAVF_RX_FLEX_DESC_STATUS0_LPBK_S,
 348         IAVF_RX_FLEX_DESC_STATUS0_IPV6EXADD_S,
 349         IAVF_RX_FLEX_DESC_STATUS0_RXE_S,
 350         IAVF_RX_FLEX_DESC_STATUS0_CRCP_S,
 351         IAVF_RX_FLEX_DESC_STATUS0_RSS_VALID_S,
 352         IAVF_RX_FLEX_DESC_STATUS0_L2TAG1P_S,
 353         IAVF_RX_FLEX_DESC_STATUS0_XTRMD0_VALID_S,
 354         IAVF_RX_FLEX_DESC_STATUS0_XTRMD1_VALID_S,
 355         IAVF_RX_FLEX_DESC_STATUS0_LAST /* this entry must be last!!! */
 356 };
 357
 358 /* for iavf_32b_rx_flex_desc.ptype_flex_flags0 member */
 359 #define IAVF_RX_FLEX_DESC_PTYPE_M       (0x3FF) /* 10-bits */
 360
 361 /* for iavf_32b_rx_flex_desc.pkt_len member */
 362 #define IAVF_RX_FLX_DESC_PKT_LEN_M      (0x3FFF) /* 14-bits */
 363
 364 int iavf_dev_rx_queue_setup(struct rte_eth_dev *dev,
 365                            uint16_t queue_idx,
 366                            uint16_t nb_desc,
 367                            unsigned int socket_id,
 368                            const struct rte_eth_rxconf *rx_conf,
 369                            struct rte_mempool *mp);
 370
 371 int iavf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
 372 int iavf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
 373 void iavf_dev_rx_queue_release(void *rxq);
 374
 375 int iavf_dev_tx_queue_setup(struct rte_eth_dev *dev,
 376                            uint16_t queue_idx,
 377                            uint16_t nb_desc,
 378                            unsigned int socket_id,
 379                            const struct rte_eth_txconf *tx_conf);
 380 int iavf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
 381 int iavf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);
 382 void iavf_dev_tx_queue_release(void *txq);
 383 void iavf_stop_queues(struct rte_eth_dev *dev);
 384 uint16_t iavf_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
 385                        uint16_t nb_pkts);
 386 uint16_t iavf_recv_pkts_flex_rxd(void *rx_queue,
 387                                  struct rte_mbuf **rx_pkts,
 388                                  uint16_t nb_pkts);
 389 uint16_t iavf_recv_scattered_pkts(void *rx_queue,
 390                                  struct rte_mbuf **rx_pkts,
 391                                  uint16_t nb_pkts);
 392 uint16_t iavf_recv_scattered_pkts_flex_rxd(void *rx_queue,
 393                                            struct rte_mbuf **rx_pkts,
 394                                            uint16_t nb_pkts);
 395 uint16_t iavf_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 396                        uint16_t nb_pkts);
 397 uint16_t iavf_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 398                        uint16_t nb_pkts);
 399 void iavf_set_rx_function(struct rte_eth_dev *dev);
 400 void iavf_set_tx_function(struct rte_eth_dev *dev);
 401 void iavf_dev_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
 402                           struct rte_eth_rxq_info *qinfo);
 403 void iavf_dev_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
 404                           struct rte_eth_txq_info *qinfo);
 405 uint32_t iavf_dev_rxq_count(struct rte_eth_dev *dev, uint16_t queue_id);
 406 int iavf_dev_rx_desc_status(void *rx_queue, uint16_t offset);
 407 int iavf_dev_tx_desc_status(void *tx_queue, uint16_t offset);
 408
 409 uint16_t iavf_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
 410                            uint16_t nb_pkts);
 411 uint16_t iavf_recv_pkts_vec_flex_rxd(void *rx_queue, struct rte_mbuf **rx_pkts,
 412                                      uint16_t nb_pkts);
 413 uint16_t iavf_recv_scattered_pkts_vec(void *rx_queue,
 414                                      struct rte_mbuf **rx_pkts,
 415                                      uint16_t nb_pkts);
 416 uint16_t iavf_recv_scattered_pkts_vec_flex_rxd(void *rx_queue,
 417                                                struct rte_mbuf **rx_pkts,
 418                                                uint16_t nb_pkts);
 419 uint16_t iavf_xmit_fixed_burst_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
 420                                   uint16_t nb_pkts);
 421 uint16_t iavf_recv_pkts_vec_avx2(void *rx_queue, struct rte_mbuf **rx_pkts,
 422                                  uint16_t nb_pkts);
 423 uint16_t iavf_recv_pkts_vec_avx2_flex_rxd(void *rx_queue,
 424                                           struct rte_mbuf **rx_pkts,
 425                                           uint16_t nb_pkts);
 426 uint16_t iavf_recv_scattered_pkts_vec_avx2(void *rx_queue,
 427                                            struct rte_mbuf **rx_pkts,
 428                                            uint16_t nb_pkts);
 429 uint16_t iavf_recv_scattered_pkts_vec_avx2_flex_rxd(void *rx_queue,
 430                                                     struct rte_mbuf **rx_pkts,
 431                                                     uint16_t nb_pkts);
 432 uint16_t iavf_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
 433                             uint16_t nb_pkts);
 434 uint16_t iavf_xmit_pkts_vec_avx2(void *tx_queue, struct rte_mbuf **tx_pkts,
 435                                  uint16_t nb_pkts);
 436 int iavf_rx_vec_dev_check(struct rte_eth_dev *dev);
 437 int iavf_tx_vec_dev_check(struct rte_eth_dev *dev);
 438 int iavf_rxq_vec_setup(struct iavf_rx_queue *rxq);
 439 int iavf_txq_vec_setup(struct iavf_tx_queue *txq);
 440
 441 const uint32_t *iavf_get_default_ptype_table(void);
 442
 443 static inline
 444 void iavf_dump_rx_descriptor(struct iavf_rx_queue *rxq,
 445                             const volatile void *desc,
 446                             uint16_t rx_id)
 447 {
 448 #ifdef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
 449         const volatile union iavf_16byte_rx_desc *rx_desc = desc;
 450
 451         printf("Queue %d Rx_desc %d: QW0: 0x%016"PRIx64" QW1: 0x%016"PRIx64"\n",
 452                rxq->queue_id, rx_id, rx_desc->read.pkt_addr,
 453                rx_desc->read.hdr_addr);
 454 #else
 455         const volatile union iavf_32byte_rx_desc *rx_desc = desc;
 456
 457         printf("Queue %d Rx_desc %d: QW0: 0x%016"PRIx64" QW1: 0x%016"PRIx64
 458                " QW2: 0x%016"PRIx64" QW3: 0x%016"PRIx64"\n", rxq->queue_id,
 459                rx_id, rx_desc->read.pkt_addr, rx_desc->read.hdr_addr,
 460                rx_desc->read.rsvd1, rx_desc->read.rsvd2);
 461 #endif
 462 }
 463
 464 /* All the descriptors are 16 bytes, so just use one of them
 465  * to print the qwords
 466  */
 467 static inline
 468 void iavf_dump_tx_descriptor(const struct iavf_tx_queue *txq,
 469                             const volatile void *desc, uint16_t tx_id)
 470 {
 471         const char *name;
 472         const volatile struct iavf_tx_desc *tx_desc = desc;
 473         enum iavf_tx_desc_dtype_value type;
 474
 475         type = (enum iavf_tx_desc_dtype_value)rte_le_to_cpu_64(
 476                 tx_desc->cmd_type_offset_bsz &
 477                 rte_cpu_to_le_64(IAVF_TXD_QW1_DTYPE_MASK));
 478         switch (type) {
 479         case IAVF_TX_DESC_DTYPE_DATA:
 480                 name = "Tx_data_desc";
 481                 break;
 482         case IAVF_TX_DESC_DTYPE_CONTEXT:
 483                 name = "Tx_context_desc";
 484                 break;
 485         default:
 486                 name = "unknown_desc";
 487                 break;
 488         }
 489
 490         printf("Queue %d %s %d: QW0: 0x%016"PRIx64" QW1: 0x%016"PRIx64"\n",
 491                txq->queue_id, name, tx_id, tx_desc->buffer_addr,
 492                tx_desc->cmd_type_offset_bsz);
 493 }
 494
 495 #define FDIR_PROC_ENABLE_PER_QUEUE(ad, on) do { \
 496         int i; \
 497         for (i = 0; i < (ad)->eth_dev->data->nb_rx_queues; i++) { \
 498                 struct iavf_rx_queue *rxq = (ad)->eth_dev->data->rx_queues[i]; \
 499                 if (!rxq) \
 500                         continue; \
 501                 rxq->fdir_enabled = on; \
 502         } \
 503         PMD_DRV_LOG(DEBUG, "FDIR processing on RX set to %d", on); \
 504 } while (0)
 505
 506 /* Enable/disable flow director Rx processing in data path. */
 507 static inline
 508 void iavf_fdir_rx_proc_enable(struct iavf_adapter *ad, bool on)
 509 {
 510         if (on) {
 511                 /* enable flow director processing */
 512                 FDIR_PROC_ENABLE_PER_QUEUE(ad, on);
 513                 ad->fdir_ref_cnt++;
 514         } else {
 515                 if (ad->fdir_ref_cnt >= 1) {
 516                         ad->fdir_ref_cnt--;
 517
 518                         if (ad->fdir_ref_cnt == 0)
 519                                 FDIR_PROC_ENABLE_PER_QUEUE(ad, on);
 520                 }
 521         }
 522 }
 523
 524 #ifdef RTE_LIBRTE_IAVF_DEBUG_DUMP_DESC
 525 #define IAVF_DUMP_RX_DESC(rxq, desc, rx_id) \
 526         iavf_dump_rx_descriptor(rxq, desc, rx_id)
 527 #define IAVF_DUMP_TX_DESC(txq, desc, tx_id) \
 528         iavf_dump_tx_descriptor(txq, desc, tx_id)
 529 #else
 530 #define IAVF_DUMP_RX_DESC(rxq, desc, rx_id) do { } while (0)
 531 #define IAVF_DUMP_TX_DESC(txq, desc, tx_id) do { } while (0)
 532 #endif
 533
 534 #endif /* _IAVF_RXTX_H_ */