drivers/net/iavf/iavf_rxtx.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2017 Intel Corporation
   3  */
   4
   5 #ifndef _IAVF_RXTX_H_
   6 #define _IAVF_RXTX_H_
   7
   8 /* In QLEN must be whole number of 32 descriptors. */
   9 #define IAVF_ALIGN_RING_DESC      32
  10 #define IAVF_MIN_RING_DESC        64
  11 #define IAVF_MAX_RING_DESC        4096
  12 #define IAVF_DMA_MEM_ALIGN        4096
  13 /* Base address of the HW descriptor ring should be 128B aligned. */
  14 #define IAVF_RING_BASE_ALIGN      128
  15
  16 /* used for Rx Bulk Allocate */
  17 #define IAVF_RX_MAX_BURST         32
  18
  19 /* used for Vector PMD */
  20 #define IAVF_VPMD_RX_MAX_BURST    32
  21 #define IAVF_VPMD_TX_MAX_BURST    32
  22 #define IAVF_RXQ_REARM_THRESH     32
  23 #define IAVF_VPMD_DESCS_PER_LOOP  4
  24 #define IAVF_VPMD_TX_MAX_FREE_BUF 64
  25
  26 #define IAVF_NO_VECTOR_FLAGS (                           \
  27                 DEV_TX_OFFLOAD_MULTI_SEGS |              \
  28                 DEV_TX_OFFLOAD_VLAN_INSERT |             \
  29                 DEV_TX_OFFLOAD_SCTP_CKSUM |              \
  30                 DEV_TX_OFFLOAD_UDP_CKSUM |               \
  31                 DEV_TX_OFFLOAD_TCP_TSO |                 \
  32                 DEV_TX_OFFLOAD_TCP_CKSUM)
  33
  34 #define DEFAULT_TX_RS_THRESH     32
  35 #define DEFAULT_TX_FREE_THRESH   32
  36
  37 #define IAVF_MIN_TSO_MSS          256
  38 #define IAVF_MAX_TSO_MSS          9668
  39 #define IAVF_TSO_MAX_SEG          UINT8_MAX
  40 #define IAVF_TX_MAX_MTU_SEG       8
  41
  42 #define IAVF_TX_CKSUM_OFFLOAD_MASK (             \
  43                 PKT_TX_IP_CKSUM |                \
  44                 PKT_TX_L4_MASK |                 \
  45                 PKT_TX_TCP_SEG)
  46
  47 #define IAVF_TX_OFFLOAD_MASK (  \
  48                 PKT_TX_OUTER_IPV6 |              \
  49                 PKT_TX_OUTER_IPV4 |              \
  50                 PKT_TX_IPV6 |                    \
  51                 PKT_TX_IPV4 |                    \
  52                 PKT_TX_VLAN_PKT |                \
  53                 PKT_TX_IP_CKSUM |                \
  54                 PKT_TX_L4_MASK |                 \
  55                 PKT_TX_TCP_SEG)
  56
  57 #define IAVF_TX_OFFLOAD_NOTSUP_MASK \
  58                 (PKT_TX_OFFLOAD_MASK ^ IAVF_TX_OFFLOAD_MASK)
  59
  60 /* HW desc structure, both 16-byte and 32-byte types are supported */
  61 #ifdef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
  62 #define iavf_rx_desc iavf_16byte_rx_desc
  63 #else
  64 #define iavf_rx_desc iavf_32byte_rx_desc
  65 #endif
  66
  67 struct iavf_rxq_ops {
  68         void (*release_mbufs)(struct iavf_rx_queue *rxq);
  69 };
  70
  71 struct iavf_txq_ops {
  72         void (*release_mbufs)(struct iavf_tx_queue *txq);
  73 };
  74
  75 /* Structure associated with each Rx queue. */
  76 struct iavf_rx_queue {
  77         struct rte_mempool *mp;       /* mbuf pool to populate Rx ring */
  78         const struct rte_memzone *mz; /* memzone for Rx ring */
  79         volatile union iavf_rx_desc *rx_ring; /* Rx ring virtual address */
  80         uint64_t rx_ring_phys_addr;   /* Rx ring DMA address */
  81         struct rte_mbuf **sw_ring;     /* address of SW ring */
  82         uint16_t nb_rx_desc;          /* ring length */
  83         uint16_t rx_tail;             /* current value of tail */
  84         volatile uint8_t *qrx_tail;   /* register address of tail */
  85         uint16_t rx_free_thresh;      /* max free RX desc to hold */
  86         uint16_t nb_rx_hold;          /* number of held free RX desc */
  87         struct rte_mbuf *pkt_first_seg; /* first segment of current packet */
  88         struct rte_mbuf *pkt_last_seg;  /* last segment of current packet */
  89         struct rte_mbuf fake_mbuf;      /* dummy mbuf */
  90
  91         /* used for VPMD */
  92         uint16_t rxrearm_nb;       /* number of remaining to be re-armed */
  93         uint16_t rxrearm_start;    /* the idx we start the re-arming from */
  94         uint64_t mbuf_initializer; /* value to init mbufs */
  95
  96         /* for rx bulk */
  97         uint16_t rx_nb_avail;      /* number of staged packets ready */
  98         uint16_t rx_next_avail;    /* index of next staged packets */
  99         uint16_t rx_free_trigger;  /* triggers rx buffer allocation */
 100         struct rte_mbuf *rx_stage[IAVF_RX_MAX_BURST * 2]; /* store mbuf */
 101
 102         uint16_t port_id;        /* device port ID */
 103         uint8_t crc_len;        /* 0 if CRC stripped, 4 otherwise */
 104         uint16_t queue_id;      /* Rx queue index */
 105         uint16_t rx_buf_len;    /* The packet buffer size */
 106         uint16_t rx_hdr_len;    /* The header buffer size */
 107         uint16_t max_pkt_len;   /* Maximum packet length */
 108
 109         bool q_set;             /* if rx queue has been configured */
 110         bool rx_deferred_start; /* don't start this queue in dev start */
 111         const struct iavf_rxq_ops *ops;
 112 };
 113
 114 struct iavf_tx_entry {
 115         struct rte_mbuf *mbuf;
 116         uint16_t next_id;
 117         uint16_t last_id;
 118 };
 119
 120 /* Structure associated with each TX queue. */
 121 struct iavf_tx_queue {
 122         const struct rte_memzone *mz;  /* memzone for Tx ring */
 123         volatile struct iavf_tx_desc *tx_ring; /* Tx ring virtual address */
 124         uint64_t tx_ring_phys_addr;    /* Tx ring DMA address */
 125         struct iavf_tx_entry *sw_ring;  /* address array of SW ring */
 126         uint16_t nb_tx_desc;           /* ring length */
 127         uint16_t tx_tail;              /* current value of tail */
 128         volatile uint8_t *qtx_tail;    /* register address of tail */
 129         /* number of used desc since RS bit set */
 130         uint16_t nb_used;
 131         uint16_t nb_free;
 132         uint16_t last_desc_cleaned;    /* last desc have been cleaned*/
 133         uint16_t free_thresh;
 134         uint16_t rs_thresh;
 135
 136         uint16_t port_id;
 137         uint16_t queue_id;
 138         uint64_t offloads;
 139         uint16_t next_dd;              /* next to set RS, for VPMD */
 140         uint16_t next_rs;              /* next to check DD,  for VPMD */
 141
 142         bool q_set;                    /* if rx queue has been configured */
 143         bool tx_deferred_start;        /* don't start this queue in dev start */
 144         const struct iavf_txq_ops *ops;
 145 };
 146
 147 /* Offload features */
 148 union iavf_tx_offload {
 149         uint64_t data;
 150         struct {
 151                 uint64_t l2_len:7; /* L2 (MAC) Header Length. */
 152                 uint64_t l3_len:9; /* L3 (IP) Header Length. */
 153                 uint64_t l4_len:8; /* L4 Header Length. */
 154                 uint64_t tso_segsz:16; /* TCP TSO segment size */
 155                 /* uint64_t unused : 24; */
 156         };
 157 };
 158
 159 int iavf_dev_rx_queue_setup(struct rte_eth_dev *dev,
 160                            uint16_t queue_idx,
 161                            uint16_t nb_desc,
 162                            unsigned int socket_id,
 163                            const struct rte_eth_rxconf *rx_conf,
 164                            struct rte_mempool *mp);
 165
 166 int iavf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
 167 int iavf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
 168 void iavf_dev_rx_queue_release(void *rxq);
 169
 170 int iavf_dev_tx_queue_setup(struct rte_eth_dev *dev,
 171                            uint16_t queue_idx,
 172                            uint16_t nb_desc,
 173                            unsigned int socket_id,
 174                            const struct rte_eth_txconf *tx_conf);
 175 int iavf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
 176 int iavf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);
 177 void iavf_dev_tx_queue_release(void *txq);
 178 void iavf_stop_queues(struct rte_eth_dev *dev);
 179 uint16_t iavf_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
 180                        uint16_t nb_pkts);
 181 uint16_t iavf_recv_scattered_pkts(void *rx_queue,
 182                                  struct rte_mbuf **rx_pkts,
 183                                  uint16_t nb_pkts);
 184 uint16_t iavf_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 185                        uint16_t nb_pkts);
 186 uint16_t iavf_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 187                        uint16_t nb_pkts);
 188 void iavf_set_rx_function(struct rte_eth_dev *dev);
 189 void iavf_set_tx_function(struct rte_eth_dev *dev);
 190 void iavf_dev_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
 191                           struct rte_eth_rxq_info *qinfo);
 192 void iavf_dev_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
 193                           struct rte_eth_txq_info *qinfo);
 194 uint32_t iavf_dev_rxq_count(struct rte_eth_dev *dev, uint16_t queue_id);
 195 int iavf_dev_rx_desc_status(void *rx_queue, uint16_t offset);
 196 int iavf_dev_tx_desc_status(void *tx_queue, uint16_t offset);
 197
 198 uint16_t iavf_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
 199                            uint16_t nb_pkts);
 200 uint16_t iavf_recv_scattered_pkts_vec(void *rx_queue,
 201                                      struct rte_mbuf **rx_pkts,
 202                                      uint16_t nb_pkts);
 203 uint16_t iavf_xmit_fixed_burst_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
 204                                   uint16_t nb_pkts);
 205 uint16_t iavf_recv_pkts_vec_avx2(void *rx_queue, struct rte_mbuf **rx_pkts,
 206                                  uint16_t nb_pkts);
 207 uint16_t iavf_recv_scattered_pkts_vec_avx2(void *rx_queue,
 208                                            struct rte_mbuf **rx_pkts,
 209                                            uint16_t nb_pkts);
 210 uint16_t iavf_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
 211                             uint16_t nb_pkts);
 212 uint16_t iavf_xmit_pkts_vec_avx2(void *tx_queue, struct rte_mbuf **tx_pkts,
 213                                  uint16_t nb_pkts);
 214 int iavf_rx_vec_dev_check(struct rte_eth_dev *dev);
 215 int iavf_tx_vec_dev_check(struct rte_eth_dev *dev);
 216 int iavf_rxq_vec_setup(struct iavf_rx_queue *rxq);
 217 int iavf_txq_vec_setup(struct iavf_tx_queue *txq);
 218
 219 static inline
 220 void iavf_dump_rx_descriptor(struct iavf_rx_queue *rxq,
 221                             const volatile void *desc,
 222                             uint16_t rx_id)
 223 {
 224 #ifdef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
 225         const volatile union iavf_16byte_rx_desc *rx_desc = desc;
 226
 227         printf("Queue %d Rx_desc %d: QW0: 0x%016"PRIx64" QW1: 0x%016"PRIx64"\n",
 228                rxq->queue_id, rx_id, rx_desc->read.pkt_addr,
 229                rx_desc->read.hdr_addr);
 230 #else
 231         const volatile union iavf_32byte_rx_desc *rx_desc = desc;
 232
 233         printf("Queue %d Rx_desc %d: QW0: 0x%016"PRIx64" QW1: 0x%016"PRIx64
 234                " QW2: 0x%016"PRIx64" QW3: 0x%016"PRIx64"\n", rxq->queue_id,
 235                rx_id, rx_desc->read.pkt_addr, rx_desc->read.hdr_addr,
 236                rx_desc->read.rsvd1, rx_desc->read.rsvd2);
 237 #endif
 238 }
 239
 240 /* All the descriptors are 16 bytes, so just use one of them
 241  * to print the qwords
 242  */
 243 static inline
 244 void iavf_dump_tx_descriptor(const struct iavf_tx_queue *txq,
 245                             const volatile void *desc, uint16_t tx_id)
 246 {
 247         const char *name;
 248         const volatile struct iavf_tx_desc *tx_desc = desc;
 249         enum iavf_tx_desc_dtype_value type;
 250
 251         type = (enum iavf_tx_desc_dtype_value)rte_le_to_cpu_64(
 252                 tx_desc->cmd_type_offset_bsz &
 253                 rte_cpu_to_le_64(IAVF_TXD_QW1_DTYPE_MASK));
 254         switch (type) {
 255         case IAVF_TX_DESC_DTYPE_DATA:
 256                 name = "Tx_data_desc";
 257                 break;
 258         case IAVF_TX_DESC_DTYPE_CONTEXT:
 259                 name = "Tx_context_desc";
 260                 break;
 261         default:
 262                 name = "unknown_desc";
 263                 break;
 264         }
 265
 266         printf("Queue %d %s %d: QW0: 0x%016"PRIx64" QW1: 0x%016"PRIx64"\n",
 267                txq->queue_id, name, tx_id, tx_desc->buffer_addr,
 268                tx_desc->cmd_type_offset_bsz);
 269 }
 270
 271 #ifdef RTE_LIBRTE_IAVF_DEBUG_DUMP_DESC
 272 #define IAVF_DUMP_RX_DESC(rxq, desc, rx_id) \
 273         iavf_dump_rx_descriptor(rxq, desc, rx_id)
 274 #define IAVF_DUMP_TX_DESC(txq, desc, tx_id) \
 275         iavf_dump_tx_descriptor(txq, desc, tx_id)
 276 #else
 277 #define IAVF_DUMP_RX_DESC(rxq, desc, rx_id) do { } while (0)
 278 #define IAVF_DUMP_TX_DESC(txq, desc, tx_id) do { } while (0)
 279 #endif
 280
 281 #endif /* _IAVF_RXTX_H_ */