drivers/net/iavf/iavf_rxtx.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2017 Intel Corporation
   3  */
   4
   5 #ifndef _IAVF_RXTX_H_
   6 #define _IAVF_RXTX_H_
   7
   8 /* In QLEN must be whole number of 32 descriptors. */
   9 #define IAVF_ALIGN_RING_DESC      32
  10 #define IAVF_MIN_RING_DESC        64
  11 #define IAVF_MAX_RING_DESC        4096
  12 #define IAVF_DMA_MEM_ALIGN        4096
  13 /* Base address of the HW descriptor ring should be 128B aligned. */
  14 #define IAVF_RING_BASE_ALIGN      128
  15
  16 /* used for Rx Bulk Allocate */
  17 #define IAVF_RX_MAX_BURST         32
  18
  19 /* used for Vector PMD */
  20 #define IAVF_VPMD_RX_MAX_BURST    32
  21 #define IAVF_VPMD_TX_MAX_BURST    32
  22 #define IAVF_RXQ_REARM_THRESH     32
  23 #define IAVF_VPMD_DESCS_PER_LOOP  4
  24 #define IAVF_VPMD_TX_MAX_FREE_BUF 64
  25
  26 #define IAVF_TX_NO_VECTOR_FLAGS (                                \
  27                 RTE_ETH_TX_OFFLOAD_MULTI_SEGS |          \
  28                 RTE_ETH_TX_OFFLOAD_TCP_TSO)
  29
  30 #define IAVF_TX_VECTOR_OFFLOAD (                                 \
  31                 RTE_ETH_TX_OFFLOAD_VLAN_INSERT |                 \
  32                 RTE_ETH_TX_OFFLOAD_QINQ_INSERT |                 \
  33                 RTE_ETH_TX_OFFLOAD_IPV4_CKSUM |          \
  34                 RTE_ETH_TX_OFFLOAD_SCTP_CKSUM |          \
  35                 RTE_ETH_TX_OFFLOAD_UDP_CKSUM |           \
  36                 RTE_ETH_TX_OFFLOAD_TCP_CKSUM)
  37
  38 #define IAVF_RX_VECTOR_OFFLOAD (                                 \
  39                 RTE_ETH_RX_OFFLOAD_CHECKSUM |            \
  40                 RTE_ETH_RX_OFFLOAD_SCTP_CKSUM |          \
  41                 RTE_ETH_RX_OFFLOAD_VLAN |                \
  42                 RTE_ETH_RX_OFFLOAD_RSS_HASH)
  43
  44 #define IAVF_VECTOR_PATH 0
  45 #define IAVF_VECTOR_OFFLOAD_PATH 1
  46
  47 #define DEFAULT_TX_RS_THRESH     32
  48 #define DEFAULT_TX_FREE_THRESH   32
  49
  50 #define IAVF_MIN_TSO_MSS          88
  51 #define IAVF_MAX_TSO_MSS          9668
  52 #define IAVF_TSO_MAX_SEG          UINT8_MAX
  53 #define IAVF_TX_MAX_MTU_SEG       8
  54
  55 #define IAVF_TX_CKSUM_OFFLOAD_MASK (RTE_MBUF_F_TX_IP_CKSUM |             \
  56                 RTE_MBUF_F_TX_L4_MASK |          \
  57                 RTE_MBUF_F_TX_TCP_SEG)
  58
  59 #define IAVF_TX_OFFLOAD_MASK (RTE_MBUF_F_TX_OUTER_IPV6 |                 \
  60                 RTE_MBUF_F_TX_OUTER_IPV4 |               \
  61                 RTE_MBUF_F_TX_IPV6 |                     \
  62                 RTE_MBUF_F_TX_IPV4 |                     \
  63                 RTE_MBUF_F_TX_VLAN |             \
  64                 RTE_MBUF_F_TX_IP_CKSUM |                 \
  65                 RTE_MBUF_F_TX_L4_MASK |          \
  66                 RTE_MBUF_F_TX_TCP_SEG)
  67
  68 #define IAVF_TX_OFFLOAD_NOTSUP_MASK \
  69                 (RTE_MBUF_F_TX_OFFLOAD_MASK ^ IAVF_TX_OFFLOAD_MASK)
  70
  71 /**
  72  * Rx Flex Descriptors
  73  * These descriptors are used instead of the legacy version descriptors
  74  */
  75 union iavf_16b_rx_flex_desc {
  76         struct {
  77                 __le64 pkt_addr; /* Packet buffer address */
  78                 __le64 hdr_addr; /* Header buffer address */
  79                                  /* bit 0 of hdr_addr is DD bit */
  80         } read;
  81         struct {
  82                 /* Qword 0 */
  83                 u8 rxdid; /* descriptor builder profile ID */
  84                 u8 mir_id_umb_cast; /* mirror=[5:0], umb=[7:6] */
  85                 __le16 ptype_flex_flags0; /* ptype=[9:0], ff0=[15:10] */
  86                 __le16 pkt_len; /* [15:14] are reserved */
  87                 __le16 hdr_len_sph_flex_flags1; /* header=[10:0] */
  88                                                 /* sph=[11:11] */
  89                                                 /* ff1/ext=[15:12] */
  90
  91                 /* Qword 1 */
  92                 __le16 status_error0;
  93                 __le16 l2tag1;
  94                 __le16 flex_meta0;
  95                 __le16 flex_meta1;
  96         } wb; /* writeback */
  97 };
  98
  99 union iavf_32b_rx_flex_desc {
 100         struct {
 101                 __le64 pkt_addr; /* Packet buffer address */
 102                 __le64 hdr_addr; /* Header buffer address */
 103                                  /* bit 0 of hdr_addr is DD bit */
 104                 __le64 rsvd1;
 105                 __le64 rsvd2;
 106         } read;
 107         struct {
 108                 /* Qword 0 */
 109                 u8 rxdid; /* descriptor builder profile ID */
 110                 u8 mir_id_umb_cast; /* mirror=[5:0], umb=[7:6] */
 111                 __le16 ptype_flex_flags0; /* ptype=[9:0], ff0=[15:10] */
 112                 __le16 pkt_len; /* [15:14] are reserved */
 113                 __le16 hdr_len_sph_flex_flags1; /* header=[10:0] */
 114                                                 /* sph=[11:11] */
 115                                                 /* ff1/ext=[15:12] */
 116
 117                 /* Qword 1 */
 118                 __le16 status_error0;
 119                 __le16 l2tag1;
 120                 __le16 flex_meta0;
 121                 __le16 flex_meta1;
 122
 123                 /* Qword 2 */
 124                 __le16 status_error1;
 125                 u8 flex_flags2;
 126                 u8 time_stamp_low;
 127                 __le16 l2tag2_1st;
 128                 __le16 l2tag2_2nd;
 129
 130                 /* Qword 3 */
 131                 __le16 flex_meta2;
 132                 __le16 flex_meta3;
 133                 union {
 134                         struct {
 135                                 __le16 flex_meta4;
 136                                 __le16 flex_meta5;
 137                         } flex;
 138                         __le32 ts_high;
 139                 } flex_ts;
 140         } wb; /* writeback */
 141 };
 142
 143 /* HW desc structure, both 16-byte and 32-byte types are supported */
 144 #ifdef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
 145 #define iavf_rx_desc iavf_16byte_rx_desc
 146 #define iavf_rx_flex_desc iavf_16b_rx_flex_desc
 147 #else
 148 #define iavf_rx_desc iavf_32byte_rx_desc
 149 #define iavf_rx_flex_desc iavf_32b_rx_flex_desc
 150 #endif
 151
 152 typedef void (*iavf_rxd_to_pkt_fields_t)(struct iavf_rx_queue *rxq,
 153                                 struct rte_mbuf *mb,
 154                                 volatile union iavf_rx_flex_desc *rxdp);
 155
 156 struct iavf_rxq_ops {
 157         void (*release_mbufs)(struct iavf_rx_queue *rxq);
 158 };
 159
 160 struct iavf_txq_ops {
 161         void (*release_mbufs)(struct iavf_tx_queue *txq);
 162 };
 163
 164 /* Structure associated with each Rx queue. */
 165 struct iavf_rx_queue {
 166         struct rte_mempool *mp;       /* mbuf pool to populate Rx ring */
 167         const struct rte_memzone *mz; /* memzone for Rx ring */
 168         volatile union iavf_rx_desc *rx_ring; /* Rx ring virtual address */
 169         uint64_t rx_ring_phys_addr;   /* Rx ring DMA address */
 170         struct rte_mbuf **sw_ring;     /* address of SW ring */
 171         uint16_t nb_rx_desc;          /* ring length */
 172         uint16_t rx_tail;             /* current value of tail */
 173         volatile uint8_t *qrx_tail;   /* register address of tail */
 174         uint16_t rx_free_thresh;      /* max free RX desc to hold */
 175         uint16_t nb_rx_hold;          /* number of held free RX desc */
 176         struct rte_mbuf *pkt_first_seg; /* first segment of current packet */
 177         struct rte_mbuf *pkt_last_seg;  /* last segment of current packet */
 178         struct rte_mbuf fake_mbuf;      /* dummy mbuf */
 179         uint8_t rxdid;
 180
 181         /* used for VPMD */
 182         uint16_t rxrearm_nb;       /* number of remaining to be re-armed */
 183         uint16_t rxrearm_start;    /* the idx we start the re-arming from */
 184         uint64_t mbuf_initializer; /* value to init mbufs */
 185
 186         /* for rx bulk */
 187         uint16_t rx_nb_avail;      /* number of staged packets ready */
 188         uint16_t rx_next_avail;    /* index of next staged packets */
 189         uint16_t rx_free_trigger;  /* triggers rx buffer allocation */
 190         struct rte_mbuf *rx_stage[IAVF_RX_MAX_BURST * 2]; /* store mbuf */
 191
 192         uint16_t port_id;        /* device port ID */
 193         uint8_t crc_len;        /* 0 if CRC stripped, 4 otherwise */
 194         uint8_t fdir_enabled;   /* 0 if FDIR disabled, 1 when enabled */
 195         uint16_t queue_id;      /* Rx queue index */
 196         uint16_t rx_buf_len;    /* The packet buffer size */
 197         uint16_t rx_hdr_len;    /* The header buffer size */
 198         uint16_t max_pkt_len;   /* Maximum packet length */
 199         struct iavf_vsi *vsi; /**< the VSI this queue belongs to */
 200
 201         bool q_set;             /* if rx queue has been configured */
 202         bool rx_deferred_start; /* don't start this queue in dev start */
 203         const struct iavf_rxq_ops *ops;
 204         uint8_t rx_flags;
 205 #define IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG1     BIT(0)
 206 #define IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG2_2   BIT(1)
 207         uint8_t proto_xtr; /* protocol extraction type */
 208         uint64_t xtr_ol_flag;
 209                 /* flexible descriptor metadata extraction offload flag */
 210         iavf_rxd_to_pkt_fields_t rxd_to_pkt_fields;
 211                                 /* handle flexible descriptor by RXDID */
 212         uint64_t offloads;
 213 };
 214
 215 struct iavf_tx_entry {
 216         struct rte_mbuf *mbuf;
 217         uint16_t next_id;
 218         uint16_t last_id;
 219 };
 220
 221 struct iavf_tx_vec_entry {
 222         struct rte_mbuf *mbuf;
 223 };
 224
 225 /* Structure associated with each TX queue. */
 226 struct iavf_tx_queue {
 227         const struct rte_memzone *mz;  /* memzone for Tx ring */
 228         volatile struct iavf_tx_desc *tx_ring; /* Tx ring virtual address */
 229         uint64_t tx_ring_phys_addr;    /* Tx ring DMA address */
 230         struct iavf_tx_entry *sw_ring;  /* address array of SW ring */
 231         uint16_t nb_tx_desc;           /* ring length */
 232         uint16_t tx_tail;              /* current value of tail */
 233         volatile uint8_t *qtx_tail;    /* register address of tail */
 234         /* number of used desc since RS bit set */
 235         uint16_t nb_used;
 236         uint16_t nb_free;
 237         uint16_t last_desc_cleaned;    /* last desc have been cleaned*/
 238         uint16_t free_thresh;
 239         uint16_t rs_thresh;
 240
 241         uint16_t port_id;
 242         uint16_t queue_id;
 243         uint64_t offloads;
 244         uint16_t next_dd;              /* next to set RS, for VPMD */
 245         uint16_t next_rs;              /* next to check DD,  for VPMD */
 246
 247         bool q_set;                    /* if rx queue has been configured */
 248         bool tx_deferred_start;        /* don't start this queue in dev start */
 249         const struct iavf_txq_ops *ops;
 250 #define IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG1       BIT(0)
 251 #define IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG2       BIT(1)
 252         uint8_t vlan_flag;
 253         uint8_t tc;
 254 };
 255
 256 /* Offload features */
 257 union iavf_tx_offload {
 258         uint64_t data;
 259         struct {
 260                 uint64_t l2_len:7; /* L2 (MAC) Header Length. */
 261                 uint64_t l3_len:9; /* L3 (IP) Header Length. */
 262                 uint64_t l4_len:8; /* L4 Header Length. */
 263                 uint64_t tso_segsz:16; /* TCP TSO segment size */
 264                 /* uint64_t unused : 24; */
 265         };
 266 };
 267
 268 /* Rx Flex Descriptor
 269  * RxDID Profile ID 16-21
 270  * Flex-field 0: RSS hash lower 16-bits
 271  * Flex-field 1: RSS hash upper 16-bits
 272  * Flex-field 2: Flow ID lower 16-bits
 273  * Flex-field 3: Flow ID upper 16-bits
 274  * Flex-field 4: AUX0
 275  * Flex-field 5: AUX1
 276  */
 277 struct iavf_32b_rx_flex_desc_comms {
 278         /* Qword 0 */
 279         u8 rxdid;
 280         u8 mir_id_umb_cast;
 281         __le16 ptype_flexi_flags0;
 282         __le16 pkt_len;
 283         __le16 hdr_len_sph_flex_flags1;
 284
 285         /* Qword 1 */
 286         __le16 status_error0;
 287         __le16 l2tag1;
 288         __le32 rss_hash;
 289
 290         /* Qword 2 */
 291         __le16 status_error1;
 292         u8 flexi_flags2;
 293         u8 ts_low;
 294         __le16 l2tag2_1st;
 295         __le16 l2tag2_2nd;
 296
 297         /* Qword 3 */
 298         __le32 flow_id;
 299         union {
 300                 struct {
 301                         __le16 aux0;
 302                         __le16 aux1;
 303                 } flex;
 304                 __le32 ts_high;
 305         } flex_ts;
 306 };
 307
 308 /* Rx Flex Descriptor
 309  * RxDID Profile ID 22-23 (swap Hash and FlowID)
 310  * Flex-field 0: Flow ID lower 16-bits
 311  * Flex-field 1: Flow ID upper 16-bits
 312  * Flex-field 2: RSS hash lower 16-bits
 313  * Flex-field 3: RSS hash upper 16-bits
 314  * Flex-field 4: AUX0
 315  * Flex-field 5: AUX1
 316  */
 317 struct iavf_32b_rx_flex_desc_comms_ovs {
 318         /* Qword 0 */
 319         u8 rxdid;
 320         u8 mir_id_umb_cast;
 321         __le16 ptype_flexi_flags0;
 322         __le16 pkt_len;
 323         __le16 hdr_len_sph_flex_flags1;
 324
 325         /* Qword 1 */
 326         __le16 status_error0;
 327         __le16 l2tag1;
 328         __le32 flow_id;
 329
 330         /* Qword 2 */
 331         __le16 status_error1;
 332         u8 flexi_flags2;
 333         u8 ts_low;
 334         __le16 l2tag2_1st;
 335         __le16 l2tag2_2nd;
 336
 337         /* Qword 3 */
 338         __le32 rss_hash;
 339         union {
 340                 struct {
 341                         __le16 aux0;
 342                         __le16 aux1;
 343                 } flex;
 344                 __le32 ts_high;
 345         } flex_ts;
 346 };
 347
 348 /* Receive Flex Descriptor profile IDs: There are a total
 349  * of 64 profiles where profile IDs 0/1 are for legacy; and
 350  * profiles 2-63 are flex profiles that can be programmed
 351  * with a specific metadata (profile 7 reserved for HW)
 352  */
 353 enum iavf_rxdid {
 354         IAVF_RXDID_LEGACY_0             = 0,
 355         IAVF_RXDID_LEGACY_1             = 1,
 356         IAVF_RXDID_FLEX_NIC             = 2,
 357         IAVF_RXDID_FLEX_NIC_2           = 6,
 358         IAVF_RXDID_HW                   = 7,
 359         IAVF_RXDID_COMMS_GENERIC        = 16,
 360         IAVF_RXDID_COMMS_AUX_VLAN       = 17,
 361         IAVF_RXDID_COMMS_AUX_IPV4       = 18,
 362         IAVF_RXDID_COMMS_AUX_IPV6       = 19,
 363         IAVF_RXDID_COMMS_AUX_IPV6_FLOW  = 20,
 364         IAVF_RXDID_COMMS_AUX_TCP        = 21,
 365         IAVF_RXDID_COMMS_OVS_1          = 22,
 366         IAVF_RXDID_COMMS_OVS_2          = 23,
 367         IAVF_RXDID_COMMS_AUX_IP_OFFSET  = 25,
 368         IAVF_RXDID_LAST                 = 63,
 369 };
 370
 371 enum iavf_rx_flex_desc_status_error_0_bits {
 372         /* Note: These are predefined bit offsets */
 373         IAVF_RX_FLEX_DESC_STATUS0_DD_S = 0,
 374         IAVF_RX_FLEX_DESC_STATUS0_EOF_S,
 375         IAVF_RX_FLEX_DESC_STATUS0_HBO_S,
 376         IAVF_RX_FLEX_DESC_STATUS0_L3L4P_S,
 377         IAVF_RX_FLEX_DESC_STATUS0_XSUM_IPE_S,
 378         IAVF_RX_FLEX_DESC_STATUS0_XSUM_L4E_S,
 379         IAVF_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S,
 380         IAVF_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S,
 381         IAVF_RX_FLEX_DESC_STATUS0_LPBK_S,
 382         IAVF_RX_FLEX_DESC_STATUS0_IPV6EXADD_S,
 383         IAVF_RX_FLEX_DESC_STATUS0_RXE_S,
 384         IAVF_RX_FLEX_DESC_STATUS0_CRCP_S,
 385         IAVF_RX_FLEX_DESC_STATUS0_RSS_VALID_S,
 386         IAVF_RX_FLEX_DESC_STATUS0_L2TAG1P_S,
 387         IAVF_RX_FLEX_DESC_STATUS0_XTRMD0_VALID_S,
 388         IAVF_RX_FLEX_DESC_STATUS0_XTRMD1_VALID_S,
 389         IAVF_RX_FLEX_DESC_STATUS0_LAST /* this entry must be last!!! */
 390 };
 391
 392 enum iavf_rx_flex_desc_status_error_1_bits {
 393         /* Note: These are predefined bit offsets */
 394         IAVF_RX_FLEX_DESC_STATUS1_CPM_S = 0, /* 4 bits */
 395         IAVF_RX_FLEX_DESC_STATUS1_NAT_S = 4,
 396         IAVF_RX_FLEX_DESC_STATUS1_CRYPTO_S = 5,
 397         /* [10:6] reserved */
 398         IAVF_RX_FLEX_DESC_STATUS1_L2TAG2P_S = 11,
 399         IAVF_RX_FLEX_DESC_STATUS1_XTRMD2_VALID_S = 12,
 400         IAVF_RX_FLEX_DESC_STATUS1_XTRMD3_VALID_S = 13,
 401         IAVF_RX_FLEX_DESC_STATUS1_XTRMD4_VALID_S = 14,
 402         IAVF_RX_FLEX_DESC_STATUS1_XTRMD5_VALID_S = 15,
 403         IAVF_RX_FLEX_DESC_STATUS1_LAST /* this entry must be last!!! */
 404 };
 405
 406
 407 #define IAVF_TXD_DATA_QW1_DTYPE_SHIFT   (0)
 408 #define IAVF_TXD_DATA_QW1_DTYPE_MASK    (0xFUL << IAVF_TXD_QW1_DTYPE_SHIFT)
 409
 410 #define IAVF_TXD_DATA_QW1_CMD_SHIFT     (4)
 411 #define IAVF_TXD_DATA_QW1_CMD_MASK      (0x3FFUL << IAVF_TXD_DATA_QW1_CMD_SHIFT)
 412
 413 #define IAVF_TXD_DATA_QW1_OFFSET_SHIFT  (16)
 414 #define IAVF_TXD_DATA_QW1_OFFSET_MASK   (0x3FFFFULL << \
 415                                         IAVF_TXD_DATA_QW1_OFFSET_SHIFT)
 416
 417 #define IAVF_TXD_DATA_QW1_OFFSET_MACLEN_SHIFT   (IAVF_TXD_DATA_QW1_OFFSET_SHIFT)
 418 #define IAVF_TXD_DATA_QW1_OFFSET_MACLEN_MASK    \
 419         (0x7FUL << IAVF_TXD_DATA_QW1_OFFSET_MACLEN_SHIFT)
 420
 421 #define IAVF_TXD_DATA_QW1_OFFSET_IPLEN_SHIFT    \
 422         (IAVF_TXD_DATA_QW1_OFFSET_SHIFT + IAVF_TX_DESC_LENGTH_IPLEN_SHIFT)
 423 #define IAVF_TXD_DATA_QW1_OFFSET_IPLEN_MASK     \
 424         (0x7FUL << IAVF_TXD_DATA_QW1_OFFSET_IPLEN_SHIFT)
 425
 426 #define IAVF_TXD_DATA_QW1_OFFSET_L4LEN_SHIFT    \
 427         (IAVF_TXD_DATA_QW1_OFFSET_SHIFT + IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
 428 #define IAVF_TXD_DATA_QW1_OFFSET_L4LEN_MASK     \
 429         (0xFUL << IAVF_TXD_DATA_QW1_OFFSET_L4LEN_SHIFT)
 430
 431 #define IAVF_TXD_DATA_QW1_MACLEN_MASK   \
 432         (0x7FUL << IAVF_TX_DESC_LENGTH_MACLEN_SHIFT)
 433 #define IAVF_TXD_DATA_QW1_IPLEN_MASK    \
 434         (0x7FUL << IAVF_TX_DESC_LENGTH_IPLEN_SHIFT)
 435 #define IAVF_TXD_DATA_QW1_L4LEN_MASK    \
 436         (0xFUL << IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
 437 #define IAVF_TXD_DATA_QW1_FCLEN_MASK    \
 438         (0xFUL << IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
 439
 440 #define IAVF_TXD_DATA_QW1_TX_BUF_SZ_SHIFT       (34)
 441 #define IAVF_TXD_DATA_QW1_TX_BUF_SZ_MASK        \
 442         (0x3FFFULL << IAVF_TXD_DATA_QW1_TX_BUF_SZ_SHIFT)
 443
 444 #define IAVF_TXD_DATA_QW1_L2TAG1_SHIFT          (48)
 445 #define IAVF_TXD_DATA_QW1_L2TAG1_MASK           \
 446         (0xFFFFULL << IAVF_TXD_DATA_QW1_L2TAG1_SHIFT)
 447
 448 #define IAVF_TXD_CTX_QW1_IPSEC_PARAMS_CIPHERBLK_SHIFT   (11)
 449 #define IAVF_TXD_CTX_QW1_IPSEC_PARAMS_CIPHERBLK_MASK    \
 450         (0x7UL << IAVF_TXD_CTX_QW1_IPSEC_PARAMS_CIPHERBLK_SHIFT)
 451
 452 #define IAVF_TXD_CTX_QW1_IPSEC_PARAMS_ICVLEN_SHIFT      (14)
 453 #define IAVF_TXD_CTX_QW1_IPSEC_PARAMS_ICVLEN_MASK       \
 454         (0xFUL << IAVF_TXD_CTX_QW1_IPSEC_PARAMS_ICVLEN_SHIFT)
 455
 456 #define IAVF_TXD_CTX_QW1_SEG_PARAMS_TLEN_SHIFT          (30)
 457 #define IAVF_TXD_CTX_QW1_SEG_PARAMS_TLEN_MASK           \
 458         (0x3FFFFUL << IAVF_TXD_CTX_QW1_SEG_PARAMS_TLEN_SHIFT)
 459
 460 #define IAVF_TXD_CTX_QW1_TSYNC_PARAMS_TLEN_SHIFT        (30)
 461 #define IAVF_TXD_CTX_QW1_TSYNC_PARAMS_TLEN_MASK         \
 462         (0x3FUL << IAVF_TXD_CTX_QW1_SEG_PARAMS_TLEN_SHIFT)
 463
 464 #define IAVF_TXD_CTX_QW1_SEG_PARAMS_MSS_SHIFT           (50)
 465 #define IAVF_TXD_CTX_QW1_SEG_PARAMS_MSS_MASK            \
 466         (0x3FFFUL << IAVF_TXD_CTX_QW1_SEG_PARAMS_MSS_SHIFT)
 467
 468 #define IAVF_TXD_CTX_QW0_TUN_PARAMS_EIPT_SHIFT          (0)
 469 #define IAVF_TXD_CTX_QW0_TUN_PARAMS_EIPT_MASK           (0x3UL)
 470
 471 enum iavf_tx_ctx_desc_tunnel_external_ip_type {
 472         IAVF_TX_CTX_DESC_EIPT_NONE,
 473         IAVF_TX_CTX_DESC_EIPT_IPV6,
 474         IAVF_TX_CTX_DESC_EIPT_IPV4_NO_CHECKSUM_OFFLOAD,
 475         IAVF_TX_CTX_DESC_EIPT_IPV4_CHECKSUM_OFFLOAD
 476 };
 477
 478 #define IAVF_TXD_CTX_QW0_TUN_PARAMS_EIPLEN_SHIFT        (2)
 479 #define IAVF_TXD_CTX_QW0_TUN_PARAMS_EIPLEN_MASK         (0x7FUL)
 480
 481 #define IAVF_TXD_CTX_QW0_TUN_PARAMS_L4TUNT_SHIFT        (9)
 482 #define IAVF_TXD_CTX_QW0_TUN_PARAMS_L4TUNT_MASK         (0x3UL)
 483
 484 enum iavf_tx_ctx_desc_tunnel_l4_tunnel_type {
 485         IAVF_TX_CTX_DESC_L4_TUN_TYP_NO_UDP_GRE,
 486         IAVF_TX_CTX_DESC_L4_TUN_TYP_UDP,
 487         IAVF_TX_CTX_DESC_L4_TUN_TYP_GRE
 488 };
 489
 490 #define IAVF_TXD_CTX_QW0_TUN_PARAMS_EIP_NOINC_SHIFT     (11)
 491 #define IAVF_TXD_CTX_QW0_TUN_PARAMS_EIP_NOINC_MASK      (0x1UL)
 492
 493 #define IAVF_TXD_CTX_QW0_TUN_PARAMS_L4TUNLEN_SHIFT      (12)
 494 #define IAVF_TXD_CTX_QW0_TUN_PARAMS_L4TUNLEN_MASK       (0x7FUL)
 495
 496 #define IAVF_TXD_CTX_QW0_TUN_PARAMS_DECTTL_SHIFT        (19)
 497 #define IAVF_TXD_CTX_QW0_TUN_PARAMS_DECTTL_MASK         (0xFUL)
 498
 499 #define IAVF_TXD_CTX_QW0_TUN_PARAMS_L4T_CS_SHIFT        (23)
 500 #define IAVF_TXD_CTX_QW0_TUN_PARAMS_L4T_CS_MASK         (0x1UL)
 501
 502 #define IAVF_TXD_CTX_QW0_L2TAG2_PARAM                   (32)
 503 #define IAVF_TXD_CTX_QW0_L2TAG2_MASK                    (0xFFFFUL)
 504
 505
 506 #define IAVF_RX_FLEX_DESC_IPSEC_CRYPTO_SAID_MASK        (0xFFFFF)
 507
 508 /* for iavf_32b_rx_flex_desc.ptype_flex_flags0 member */
 509 #define IAVF_RX_FLEX_DESC_PTYPE_M       (0x3FF) /* 10-bits */
 510
 511
 512 /* for iavf_32b_rx_flex_desc.ptype_flex_flags0 member */
 513 #define IAVF_RX_FLEX_DESC_PTYPE_M       (0x3FF) /* 10-bits */
 514
 515 /* for iavf_32b_rx_flex_desc.pkt_len member */
 516 #define IAVF_RX_FLX_DESC_PKT_LEN_M      (0x3FFF) /* 14-bits */
 517
 518 int iavf_dev_rx_queue_setup(struct rte_eth_dev *dev,
 519                            uint16_t queue_idx,
 520                            uint16_t nb_desc,
 521                            unsigned int socket_id,
 522                            const struct rte_eth_rxconf *rx_conf,
 523                            struct rte_mempool *mp);
 524
 525 int iavf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
 526 int iavf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
 527 void iavf_dev_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid);
 528
 529 int iavf_dev_tx_queue_setup(struct rte_eth_dev *dev,
 530                            uint16_t queue_idx,
 531                            uint16_t nb_desc,
 532                            unsigned int socket_id,
 533                            const struct rte_eth_txconf *tx_conf);
 534 int iavf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
 535 int iavf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);
 536 int iavf_dev_tx_done_cleanup(void *txq, uint32_t free_cnt);
 537 void iavf_dev_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid);
 538 void iavf_stop_queues(struct rte_eth_dev *dev);
 539 uint16_t iavf_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
 540                        uint16_t nb_pkts);
 541 uint16_t iavf_recv_pkts_flex_rxd(void *rx_queue,
 542                                  struct rte_mbuf **rx_pkts,
 543                                  uint16_t nb_pkts);
 544 uint16_t iavf_recv_scattered_pkts(void *rx_queue,
 545                                  struct rte_mbuf **rx_pkts,
 546                                  uint16_t nb_pkts);
 547 uint16_t iavf_recv_scattered_pkts_flex_rxd(void *rx_queue,
 548                                            struct rte_mbuf **rx_pkts,
 549                                            uint16_t nb_pkts);
 550 uint16_t iavf_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 551                        uint16_t nb_pkts);
 552 uint16_t iavf_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 553                        uint16_t nb_pkts);
 554 void iavf_set_rx_function(struct rte_eth_dev *dev);
 555 void iavf_set_tx_function(struct rte_eth_dev *dev);
 556 void iavf_dev_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
 557                           struct rte_eth_rxq_info *qinfo);
 558 void iavf_dev_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
 559                           struct rte_eth_txq_info *qinfo);
 560 uint32_t iavf_dev_rxq_count(void *rx_queue);
 561 int iavf_dev_rx_desc_status(void *rx_queue, uint16_t offset);
 562 int iavf_dev_tx_desc_status(void *tx_queue, uint16_t offset);
 563
 564 uint16_t iavf_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
 565                            uint16_t nb_pkts);
 566 uint16_t iavf_recv_pkts_vec_flex_rxd(void *rx_queue, struct rte_mbuf **rx_pkts,
 567                                      uint16_t nb_pkts);
 568 uint16_t iavf_recv_scattered_pkts_vec(void *rx_queue,
 569                                      struct rte_mbuf **rx_pkts,
 570                                      uint16_t nb_pkts);
 571 uint16_t iavf_recv_scattered_pkts_vec_flex_rxd(void *rx_queue,
 572                                                struct rte_mbuf **rx_pkts,
 573                                                uint16_t nb_pkts);
 574 uint16_t iavf_xmit_fixed_burst_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
 575                                   uint16_t nb_pkts);
 576 uint16_t iavf_recv_pkts_vec_avx2(void *rx_queue, struct rte_mbuf **rx_pkts,
 577                                  uint16_t nb_pkts);
 578 uint16_t iavf_recv_pkts_vec_avx2_flex_rxd(void *rx_queue,
 579                                           struct rte_mbuf **rx_pkts,
 580                                           uint16_t nb_pkts);
 581 uint16_t iavf_recv_scattered_pkts_vec_avx2(void *rx_queue,
 582                                            struct rte_mbuf **rx_pkts,
 583                                            uint16_t nb_pkts);
 584 uint16_t iavf_recv_scattered_pkts_vec_avx2_flex_rxd(void *rx_queue,
 585                                                     struct rte_mbuf **rx_pkts,
 586                                                     uint16_t nb_pkts);
 587 uint16_t iavf_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
 588                             uint16_t nb_pkts);
 589 uint16_t iavf_xmit_pkts_vec_avx2(void *tx_queue, struct rte_mbuf **tx_pkts,
 590                                  uint16_t nb_pkts);
 591 int iavf_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc);
 592 int iavf_rx_vec_dev_check(struct rte_eth_dev *dev);
 593 int iavf_tx_vec_dev_check(struct rte_eth_dev *dev);
 594 int iavf_rxq_vec_setup(struct iavf_rx_queue *rxq);
 595 int iavf_txq_vec_setup(struct iavf_tx_queue *txq);
 596 uint16_t iavf_recv_pkts_vec_avx512(void *rx_queue, struct rte_mbuf **rx_pkts,
 597                                    uint16_t nb_pkts);
 598 uint16_t iavf_recv_pkts_vec_avx512_offload(void *rx_queue,
 599                                            struct rte_mbuf **rx_pkts,
 600                                            uint16_t nb_pkts);
 601 uint16_t iavf_recv_pkts_vec_avx512_flex_rxd(void *rx_queue,
 602                                             struct rte_mbuf **rx_pkts,
 603                                             uint16_t nb_pkts);
 604 uint16_t iavf_recv_pkts_vec_avx512_flex_rxd_offload(void *rx_queue,
 605                                                     struct rte_mbuf **rx_pkts,
 606                                                     uint16_t nb_pkts);
 607 uint16_t iavf_recv_scattered_pkts_vec_avx512(void *rx_queue,
 608                                              struct rte_mbuf **rx_pkts,
 609                                              uint16_t nb_pkts);
 610 uint16_t iavf_recv_scattered_pkts_vec_avx512_offload(void *rx_queue,
 611                                                      struct rte_mbuf **rx_pkts,
 612                                                      uint16_t nb_pkts);
 613 uint16_t iavf_recv_scattered_pkts_vec_avx512_flex_rxd(void *rx_queue,
 614                                                       struct rte_mbuf **rx_pkts,
 615                                                       uint16_t nb_pkts);
 616 uint16_t iavf_recv_scattered_pkts_vec_avx512_flex_rxd_offload(void *rx_queue,
 617                                                               struct rte_mbuf **rx_pkts,
 618                                                               uint16_t nb_pkts);
 619 uint16_t iavf_xmit_pkts_vec_avx512(void *tx_queue, struct rte_mbuf **tx_pkts,
 620                                    uint16_t nb_pkts);
 621 uint16_t iavf_xmit_pkts_vec_avx512_offload(void *tx_queue,
 622                                            struct rte_mbuf **tx_pkts,
 623                                            uint16_t nb_pkts);
 624 int iavf_txq_vec_setup_avx512(struct iavf_tx_queue *txq);
 625
 626 uint8_t iavf_proto_xtr_type_to_rxdid(uint8_t xtr_type);
 627
 628 void iavf_set_default_ptype_table(struct rte_eth_dev *dev);
 629
 630 static inline
 631 void iavf_dump_rx_descriptor(struct iavf_rx_queue *rxq,
 632                             const volatile void *desc,
 633                             uint16_t rx_id)
 634 {
 635 #ifdef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
 636         const volatile union iavf_16byte_rx_desc *rx_desc = desc;
 637
 638         printf("Queue %d Rx_desc %d: QW0: 0x%016"PRIx64" QW1: 0x%016"PRIx64"\n",
 639                rxq->queue_id, rx_id, rx_desc->read.pkt_addr,
 640                rx_desc->read.hdr_addr);
 641 #else
 642         const volatile union iavf_32byte_rx_desc *rx_desc = desc;
 643
 644         printf("Queue %d Rx_desc %d: QW0: 0x%016"PRIx64" QW1: 0x%016"PRIx64
 645                " QW2: 0x%016"PRIx64" QW3: 0x%016"PRIx64"\n", rxq->queue_id,
 646                rx_id, rx_desc->read.pkt_addr, rx_desc->read.hdr_addr,
 647                rx_desc->read.rsvd1, rx_desc->read.rsvd2);
 648 #endif
 649 }
 650
 651 /* All the descriptors are 16 bytes, so just use one of them
 652  * to print the qwords
 653  */
 654 static inline
 655 void iavf_dump_tx_descriptor(const struct iavf_tx_queue *txq,
 656                             const volatile void *desc, uint16_t tx_id)
 657 {
 658         const char *name;
 659         const volatile struct iavf_tx_desc *tx_desc = desc;
 660         enum iavf_tx_desc_dtype_value type;
 661
 662
 663         type = (enum iavf_tx_desc_dtype_value)
 664                 rte_le_to_cpu_64(tx_desc->cmd_type_offset_bsz &
 665                         rte_cpu_to_le_64(IAVF_TXD_DATA_QW1_DTYPE_MASK));
 666         switch (type) {
 667         case IAVF_TX_DESC_DTYPE_DATA:
 668                 name = "Tx_data_desc";
 669                 break;
 670         case IAVF_TX_DESC_DTYPE_CONTEXT:
 671                 name = "Tx_context_desc";
 672                 break;
 673         default:
 674                 name = "unknown_desc";
 675                 break;
 676         }
 677
 678         printf("Queue %d %s %d: QW0: 0x%016"PRIx64" QW1: 0x%016"PRIx64"\n",
 679                 txq->queue_id, name, tx_id, tx_desc->buffer_addr,
 680                 tx_desc->cmd_type_offset_bsz);
 681 }
 682
 683 #define FDIR_PROC_ENABLE_PER_QUEUE(ad, on) do { \
 684         int i; \
 685         for (i = 0; i < (ad)->dev_data->nb_rx_queues; i++) { \
 686                 struct iavf_rx_queue *rxq = (ad)->dev_data->rx_queues[i]; \
 687                 if (!rxq) \
 688                         continue; \
 689                 rxq->fdir_enabled = on; \
 690         } \
 691         PMD_DRV_LOG(DEBUG, "FDIR processing on RX set to %d", on); \
 692 } while (0)
 693
 694 /* Enable/disable flow director Rx processing in data path. */
 695 static inline
 696 void iavf_fdir_rx_proc_enable(struct iavf_adapter *ad, bool on)
 697 {
 698         if (on) {
 699                 /* enable flow director processing */
 700                 FDIR_PROC_ENABLE_PER_QUEUE(ad, on);
 701                 ad->fdir_ref_cnt++;
 702         } else {
 703                 if (ad->fdir_ref_cnt >= 1) {
 704                         ad->fdir_ref_cnt--;
 705
 706                         if (ad->fdir_ref_cnt == 0)
 707                                 FDIR_PROC_ENABLE_PER_QUEUE(ad, on);
 708                 }
 709         }
 710 }
 711
 712 #ifdef RTE_LIBRTE_IAVF_DEBUG_DUMP_DESC
 713 #define IAVF_DUMP_RX_DESC(rxq, desc, rx_id) \
 714         iavf_dump_rx_descriptor(rxq, desc, rx_id)
 715 #define IAVF_DUMP_TX_DESC(txq, desc, tx_id) \
 716         iavf_dump_tx_descriptor(txq, desc, tx_id)
 717 #else
 718 #define IAVF_DUMP_RX_DESC(rxq, desc, rx_id) do { } while (0)
 719 #define IAVF_DUMP_TX_DESC(txq, desc, tx_id) do { } while (0)
 720 #endif
 721
 722 #endif /* _IAVF_RXTX_H_ */