drivers/net/iavf/iavf_rxtx.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2017 Intel Corporation
   3  */
   4
   5 #ifndef _IAVF_RXTX_H_
   6 #define _IAVF_RXTX_H_
   7
   8 /* In QLEN must be whole number of 32 descriptors. */
   9 #define IAVF_ALIGN_RING_DESC      32
  10 #define IAVF_MIN_RING_DESC        64
  11 #define IAVF_MAX_RING_DESC        4096
  12 #define IAVF_DMA_MEM_ALIGN        4096
  13 /* Base address of the HW descriptor ring should be 128B aligned. */
  14 #define IAVF_RING_BASE_ALIGN      128
  15
  16 /* used for Rx Bulk Allocate */
  17 #define IAVF_RX_MAX_BURST         32
  18
  19 /* used for Vector PMD */
  20 #define IAVF_VPMD_RX_MAX_BURST    32
  21 #define IAVF_VPMD_TX_MAX_BURST    32
  22 #define IAVF_RXQ_REARM_THRESH     32
  23 #define IAVF_VPMD_DESCS_PER_LOOP  4
  24 #define IAVF_VPMD_TX_MAX_FREE_BUF 64
  25
  26 #define IAVF_TX_NO_VECTOR_FLAGS (                                \
  27                 RTE_ETH_TX_OFFLOAD_MULTI_SEGS |          \
  28                 RTE_ETH_TX_OFFLOAD_TCP_TSO |             \
  29                 RTE_ETH_TX_OFFLOAD_SECURITY)
  30
  31 #define IAVF_TX_VECTOR_OFFLOAD (                                 \
  32                 RTE_ETH_TX_OFFLOAD_VLAN_INSERT |                 \
  33                 RTE_ETH_TX_OFFLOAD_QINQ_INSERT |                 \
  34                 RTE_ETH_TX_OFFLOAD_IPV4_CKSUM |          \
  35                 RTE_ETH_TX_OFFLOAD_SCTP_CKSUM |          \
  36                 RTE_ETH_TX_OFFLOAD_UDP_CKSUM |           \
  37                 RTE_ETH_TX_OFFLOAD_TCP_CKSUM)
  38
  39 #define IAVF_RX_VECTOR_OFFLOAD (                                 \
  40                 RTE_ETH_RX_OFFLOAD_CHECKSUM |            \
  41                 RTE_ETH_RX_OFFLOAD_SCTP_CKSUM |          \
  42                 RTE_ETH_RX_OFFLOAD_VLAN |                \
  43                 RTE_ETH_RX_OFFLOAD_RSS_HASH)
  44
  45 #define IAVF_VECTOR_PATH 0
  46 #define IAVF_VECTOR_OFFLOAD_PATH 1
  47
  48 #define DEFAULT_TX_RS_THRESH     32
  49 #define DEFAULT_TX_FREE_THRESH   32
  50
  51 #define IAVF_MIN_TSO_MSS          256
  52 #define IAVF_MAX_TSO_MSS          9668
  53 #define IAVF_TSO_MAX_SEG          UINT8_MAX
  54 #define IAVF_TX_MAX_MTU_SEG       8
  55
  56 #define IAVF_TX_CKSUM_OFFLOAD_MASK (             \
  57                 RTE_MBUF_F_TX_IP_CKSUM |                 \
  58                 RTE_MBUF_F_TX_L4_MASK |          \
  59                 RTE_MBUF_F_TX_TCP_SEG)
  60
  61 #define IAVF_TX_OFFLOAD_MASK (  \
  62                 RTE_MBUF_F_TX_OUTER_IPV6 |               \
  63                 RTE_MBUF_F_TX_OUTER_IPV4 |               \
  64                 RTE_MBUF_F_TX_IPV6 |                     \
  65                 RTE_MBUF_F_TX_IPV4 |                     \
  66                 RTE_MBUF_F_TX_VLAN |             \
  67                 RTE_MBUF_F_TX_IP_CKSUM |                 \
  68                 RTE_MBUF_F_TX_L4_MASK |          \
  69                 RTE_MBUF_F_TX_TCP_SEG |          \
  70                 RTE_ETH_TX_OFFLOAD_SECURITY)
  71
  72 #define IAVF_TX_OFFLOAD_NOTSUP_MASK \
  73                 (RTE_MBUF_F_TX_OFFLOAD_MASK ^ IAVF_TX_OFFLOAD_MASK)
  74
  75 /**
  76  * Rx Flex Descriptors
  77  * These descriptors are used instead of the legacy version descriptors
  78  */
  79 union iavf_16b_rx_flex_desc {
  80         struct {
  81                 __le64 pkt_addr; /* Packet buffer address */
  82                 __le64 hdr_addr; /* Header buffer address */
  83                                  /* bit 0 of hdr_addr is DD bit */
  84         } read;
  85         struct {
  86                 /* Qword 0 */
  87                 u8 rxdid; /* descriptor builder profile ID */
  88                 u8 mir_id_umb_cast; /* mirror=[5:0], umb=[7:6] */
  89                 __le16 ptype_flex_flags0; /* ptype=[9:0], ff0=[15:10] */
  90                 __le16 pkt_len; /* [15:14] are reserved */
  91                 __le16 hdr_len_sph_flex_flags1; /* header=[10:0] */
  92                                                 /* sph=[11:11] */
  93                                                 /* ff1/ext=[15:12] */
  94
  95                 /* Qword 1 */
  96                 __le16 status_error0;
  97                 __le16 l2tag1;
  98                 __le16 flex_meta0;
  99                 __le16 flex_meta1;
 100         } wb; /* writeback */
 101 };
 102
 103 union iavf_32b_rx_flex_desc {
 104         struct {
 105                 __le64 pkt_addr; /* Packet buffer address */
 106                 __le64 hdr_addr; /* Header buffer address */
 107                                  /* bit 0 of hdr_addr is DD bit */
 108                 __le64 rsvd1;
 109                 __le64 rsvd2;
 110         } read;
 111         struct {
 112                 /* Qword 0 */
 113                 u8 rxdid; /* descriptor builder profile ID */
 114                 u8 mir_id_umb_cast; /* mirror=[5:0], umb=[7:6] */
 115                 __le16 ptype_flex_flags0; /* ptype=[9:0], ff0=[15:10] */
 116                 __le16 pkt_len; /* [15:14] are reserved */
 117                 __le16 hdr_len_sph_flex_flags1; /* header=[10:0] */
 118                                                 /* sph=[11:11] */
 119                                                 /* ff1/ext=[15:12] */
 120
 121                 /* Qword 1 */
 122                 __le16 status_error0;
 123                 __le16 l2tag1;
 124                 __le16 flex_meta0;
 125                 __le16 flex_meta1;
 126
 127                 /* Qword 2 */
 128                 __le16 status_error1;
 129                 u8 flex_flags2;
 130                 u8 time_stamp_low;
 131                 __le16 l2tag2_1st;
 132                 __le16 l2tag2_2nd;
 133
 134                 /* Qword 3 */
 135                 __le16 flex_meta2;
 136                 __le16 flex_meta3;
 137                 union {
 138                         struct {
 139                                 __le16 flex_meta4;
 140                                 __le16 flex_meta5;
 141                         } flex;
 142                         __le32 ts_high;
 143                 } flex_ts;
 144         } wb; /* writeback */
 145 };
 146
 147 /* HW desc structure, both 16-byte and 32-byte types are supported */
 148 #ifdef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
 149 #define iavf_rx_desc iavf_16byte_rx_desc
 150 #define iavf_rx_flex_desc iavf_16b_rx_flex_desc
 151 #else
 152 #define iavf_rx_desc iavf_32byte_rx_desc
 153 #define iavf_rx_flex_desc iavf_32b_rx_flex_desc
 154 #endif
 155
 156 typedef void (*iavf_rxd_to_pkt_fields_t)(struct iavf_rx_queue *rxq,
 157                                 struct rte_mbuf *mb,
 158                                 volatile union iavf_rx_flex_desc *rxdp);
 159
 160 struct iavf_rxq_ops {
 161         void (*release_mbufs)(struct iavf_rx_queue *rxq);
 162 };
 163
 164 struct iavf_txq_ops {
 165         void (*release_mbufs)(struct iavf_tx_queue *txq);
 166 };
 167
 168
 169 struct iavf_rx_queue_stats {
 170         uint64_t reserved;
 171         struct iavf_ipsec_crypto_stats ipsec_crypto;
 172 };
 173
 174 /* Structure associated with each Rx queue. */
 175 struct iavf_rx_queue {
 176         struct rte_mempool *mp;       /* mbuf pool to populate Rx ring */
 177         const struct rte_memzone *mz; /* memzone for Rx ring */
 178         volatile union iavf_rx_desc *rx_ring; /* Rx ring virtual address */
 179         uint64_t rx_ring_phys_addr;   /* Rx ring DMA address */
 180         struct rte_mbuf **sw_ring;     /* address of SW ring */
 181         uint16_t nb_rx_desc;          /* ring length */
 182         uint16_t rx_tail;             /* current value of tail */
 183         volatile uint8_t *qrx_tail;   /* register address of tail */
 184         uint16_t rx_free_thresh;      /* max free RX desc to hold */
 185         uint16_t nb_rx_hold;          /* number of held free RX desc */
 186         struct rte_mbuf *pkt_first_seg; /* first segment of current packet */
 187         struct rte_mbuf *pkt_last_seg;  /* last segment of current packet */
 188         struct rte_mbuf fake_mbuf;      /* dummy mbuf */
 189         uint8_t rxdid;
 190
 191         /* used for VPMD */
 192         uint16_t rxrearm_nb;       /* number of remaining to be re-armed */
 193         uint16_t rxrearm_start;    /* the idx we start the re-arming from */
 194         uint64_t mbuf_initializer; /* value to init mbufs */
 195
 196         /* for rx bulk */
 197         uint16_t rx_nb_avail;      /* number of staged packets ready */
 198         uint16_t rx_next_avail;    /* index of next staged packets */
 199         uint16_t rx_free_trigger;  /* triggers rx buffer allocation */
 200         struct rte_mbuf *rx_stage[IAVF_RX_MAX_BURST * 2]; /* store mbuf */
 201
 202         uint16_t port_id;        /* device port ID */
 203         uint8_t crc_len;        /* 0 if CRC stripped, 4 otherwise */
 204         uint8_t fdir_enabled;   /* 0 if FDIR disabled, 1 when enabled */
 205         uint16_t queue_id;      /* Rx queue index */
 206         uint16_t rx_buf_len;    /* The packet buffer size */
 207         uint16_t rx_hdr_len;    /* The header buffer size */
 208         uint16_t max_pkt_len;   /* Maximum packet length */
 209         struct iavf_vsi *vsi; /**< the VSI this queue belongs to */
 210
 211         bool q_set;             /* if rx queue has been configured */
 212         bool rx_deferred_start; /* don't start this queue in dev start */
 213         const struct iavf_rxq_ops *ops;
 214         uint8_t rx_flags;
 215 #define IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG1     BIT(0)
 216 #define IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG2_2   BIT(1)
 217         uint8_t proto_xtr; /* protocol extraction type */
 218         uint64_t xtr_ol_flag;
 219                 /* flexible descriptor metadata extraction offload flag */
 220         struct iavf_rx_queue_stats stats;
 221         uint64_t offloads;
 222 };
 223
 224 struct iavf_tx_entry {
 225         struct rte_mbuf *mbuf;
 226         uint16_t next_id;
 227         uint16_t last_id;
 228 };
 229
 230 struct iavf_tx_vec_entry {
 231         struct rte_mbuf *mbuf;
 232 };
 233
 234 /* Structure associated with each TX queue. */
 235 struct iavf_tx_queue {
 236         const struct rte_memzone *mz;  /* memzone for Tx ring */
 237         volatile struct iavf_tx_desc *tx_ring; /* Tx ring virtual address */
 238         uint64_t tx_ring_phys_addr;    /* Tx ring DMA address */
 239         struct iavf_tx_entry *sw_ring;  /* address array of SW ring */
 240         uint16_t nb_tx_desc;           /* ring length */
 241         uint16_t tx_tail;              /* current value of tail */
 242         volatile uint8_t *qtx_tail;    /* register address of tail */
 243         /* number of used desc since RS bit set */
 244         uint16_t nb_used;
 245         uint16_t nb_free;
 246         uint16_t last_desc_cleaned;    /* last desc have been cleaned*/
 247         uint16_t free_thresh;
 248         uint16_t rs_thresh;
 249
 250         uint16_t port_id;
 251         uint16_t queue_id;
 252         uint64_t offloads;
 253         uint16_t next_dd;              /* next to set RS, for VPMD */
 254         uint16_t next_rs;              /* next to check DD,  for VPMD */
 255         uint16_t ipsec_crypto_pkt_md_offset;
 256
 257         bool q_set;                    /* if rx queue has been configured */
 258         bool tx_deferred_start;        /* don't start this queue in dev start */
 259         const struct iavf_txq_ops *ops;
 260 #define IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG1       BIT(0)
 261 #define IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG2       BIT(1)
 262         uint8_t vlan_flag;
 263         uint8_t tc;
 264 };
 265
 266 /* Offload features */
 267 union iavf_tx_offload {
 268         uint64_t data;
 269         struct {
 270                 uint64_t l2_len:7; /* L2 (MAC) Header Length. */
 271                 uint64_t l3_len:9; /* L3 (IP) Header Length. */
 272                 uint64_t l4_len:8; /* L4 Header Length. */
 273                 uint64_t tso_segsz:16; /* TCP TSO segment size */
 274                 /* uint64_t unused : 24; */
 275         };
 276 };
 277
 278 /* Rx Flex Descriptor
 279  * RxDID Profile ID 16-21
 280  * Flex-field 0: RSS hash lower 16-bits
 281  * Flex-field 1: RSS hash upper 16-bits
 282  * Flex-field 2: Flow ID lower 16-bits
 283  * Flex-field 3: Flow ID upper 16-bits
 284  * Flex-field 4: AUX0
 285  * Flex-field 5: AUX1
 286  */
 287 struct iavf_32b_rx_flex_desc_comms {
 288         /* Qword 0 */
 289         u8 rxdid;
 290         u8 mir_id_umb_cast;
 291         __le16 ptype_flexi_flags0;
 292         __le16 pkt_len;
 293         __le16 hdr_len_sph_flex_flags1;
 294
 295         /* Qword 1 */
 296         __le16 status_error0;
 297         __le16 l2tag1;
 298         __le32 rss_hash;
 299
 300         /* Qword 2 */
 301         __le16 status_error1;
 302         u8 flexi_flags2;
 303         u8 ts_low;
 304         __le16 l2tag2_1st;
 305         __le16 l2tag2_2nd;
 306
 307         /* Qword 3 */
 308         __le32 flow_id;
 309         union {
 310                 struct {
 311                         __le16 aux0;
 312                         __le16 aux1;
 313                 } flex;
 314                 __le32 ts_high;
 315         } flex_ts;
 316 };
 317
 318 /* Rx Flex Descriptor
 319  * RxDID Profile ID 22-23 (swap Hash and FlowID)
 320  * Flex-field 0: Flow ID lower 16-bits
 321  * Flex-field 1: Flow ID upper 16-bits
 322  * Flex-field 2: RSS hash lower 16-bits
 323  * Flex-field 3: RSS hash upper 16-bits
 324  * Flex-field 4: AUX0
 325  * Flex-field 5: AUX1
 326  */
 327 struct iavf_32b_rx_flex_desc_comms_ovs {
 328         /* Qword 0 */
 329         u8 rxdid;
 330         u8 mir_id_umb_cast;
 331         __le16 ptype_flexi_flags0;
 332         __le16 pkt_len;
 333         __le16 hdr_len_sph_flex_flags1;
 334
 335         /* Qword 1 */
 336         __le16 status_error0;
 337         __le16 l2tag1;
 338         __le32 flow_id;
 339
 340         /* Qword 2 */
 341         __le16 status_error1;
 342         u8 flexi_flags2;
 343         u8 ts_low;
 344         __le16 l2tag2_1st;
 345         __le16 l2tag2_2nd;
 346
 347         /* Qword 3 */
 348         __le32 rss_hash;
 349         union {
 350                 struct {
 351                         __le16 aux0;
 352                         __le16 aux1;
 353                 } flex;
 354                 __le32 ts_high;
 355         } flex_ts;
 356 };
 357
 358 /* Rx Flex Descriptor
 359  * RxDID Profile ID 24 Inline IPsec
 360  * Flex-field 0: RSS hash lower 16-bits
 361  * Flex-field 1: RSS hash upper 16-bits
 362  * Flex-field 2: Flow ID lower 16-bits
 363  * Flex-field 3: Flow ID upper 16-bits
 364  * Flex-field 4: Inline IPsec SAID lower 16-bits
 365  * Flex-field 5: Inline IPsec SAID upper 16-bits
 366  */
 367 struct iavf_32b_rx_flex_desc_comms_ipsec {
 368         /* Qword 0 */
 369         u8 rxdid;
 370         u8 mir_id_umb_cast;
 371         __le16 ptype_flexi_flags0;
 372         __le16 pkt_len;
 373         __le16 hdr_len_sph_flex_flags1;
 374
 375         /* Qword 1 */
 376         __le16 status_error0;
 377         __le16 l2tag1;
 378         __le32 rss_hash;
 379
 380         /* Qword 2 */
 381         __le16 status_error1;
 382         u8 flexi_flags2;
 383         u8 ts_low;
 384         __le16 l2tag2_1st;
 385         __le16 l2tag2_2nd;
 386
 387         /* Qword 3 */
 388         __le32 flow_id;
 389         __le32 ipsec_said;
 390 };
 391
 392 /* Receive Flex Descriptor profile IDs: There are a total
 393  * of 64 profiles where profile IDs 0/1 are for legacy; and
 394  * profiles 2-63 are flex profiles that can be programmed
 395  * with a specific metadata (profile 7 reserved for HW)
 396  */
 397 enum iavf_rxdid {
 398         IAVF_RXDID_LEGACY_0             = 0,
 399         IAVF_RXDID_LEGACY_1             = 1,
 400         IAVF_RXDID_FLEX_NIC             = 2,
 401         IAVF_RXDID_FLEX_NIC_2           = 6,
 402         IAVF_RXDID_HW                   = 7,
 403         IAVF_RXDID_COMMS_GENERIC        = 16,
 404         IAVF_RXDID_COMMS_AUX_VLAN       = 17,
 405         IAVF_RXDID_COMMS_AUX_IPV4       = 18,
 406         IAVF_RXDID_COMMS_AUX_IPV6       = 19,
 407         IAVF_RXDID_COMMS_AUX_IPV6_FLOW  = 20,
 408         IAVF_RXDID_COMMS_AUX_TCP        = 21,
 409         IAVF_RXDID_COMMS_OVS_1          = 22,
 410         IAVF_RXDID_COMMS_OVS_2          = 23,
 411         IAVF_RXDID_COMMS_IPSEC_CRYPTO   = 24,
 412         IAVF_RXDID_COMMS_AUX_IP_OFFSET  = 25,
 413         IAVF_RXDID_LAST                 = 63,
 414 };
 415
 416 enum iavf_rx_flex_desc_status_error_0_bits {
 417         /* Note: These are predefined bit offsets */
 418         IAVF_RX_FLEX_DESC_STATUS0_DD_S = 0,
 419         IAVF_RX_FLEX_DESC_STATUS0_EOF_S,
 420         IAVF_RX_FLEX_DESC_STATUS0_HBO_S,
 421         IAVF_RX_FLEX_DESC_STATUS0_L3L4P_S,
 422         IAVF_RX_FLEX_DESC_STATUS0_XSUM_IPE_S,
 423         IAVF_RX_FLEX_DESC_STATUS0_XSUM_L4E_S,
 424         IAVF_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S,
 425         IAVF_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S,
 426         IAVF_RX_FLEX_DESC_STATUS0_LPBK_S,
 427         IAVF_RX_FLEX_DESC_STATUS0_IPV6EXADD_S,
 428         IAVF_RX_FLEX_DESC_STATUS0_RXE_S,
 429         IAVF_RX_FLEX_DESC_STATUS0_CRCP_S,
 430         IAVF_RX_FLEX_DESC_STATUS0_RSS_VALID_S,
 431         IAVF_RX_FLEX_DESC_STATUS0_L2TAG1P_S,
 432         IAVF_RX_FLEX_DESC_STATUS0_XTRMD0_VALID_S,
 433         IAVF_RX_FLEX_DESC_STATUS0_XTRMD1_VALID_S,
 434         IAVF_RX_FLEX_DESC_STATUS0_LAST /* this entry must be last!!! */
 435 };
 436
 437 enum iavf_rx_flex_desc_status_error_1_bits {
 438         /* Note: These are predefined bit offsets */
 439         /* Bits 3:0 are reserved for inline ipsec status */
 440         IAVF_RX_FLEX_DESC_STATUS1_IPSEC_CRYPTO_STATUS_0 = 0,
 441         IAVF_RX_FLEX_DESC_STATUS1_IPSEC_CRYPTO_STATUS_1,
 442         IAVF_RX_FLEX_DESC_STATUS1_IPSEC_CRYPTO_STATUS_2,
 443         IAVF_RX_FLEX_DESC_STATUS1_IPSEC_CRYPTO_STATUS_3,
 444         IAVF_RX_FLEX_DESC_STATUS1_NAT_S,
 445         IAVF_RX_FLEX_DESC_STATUS1_IPSEC_CRYPTO_PROCESSED,
 446         /* [10:6] reserved */
 447         IAVF_RX_FLEX_DESC_STATUS1_L2TAG2P_S = 11,
 448         IAVF_RX_FLEX_DESC_STATUS1_XTRMD2_VALID_S = 12,
 449         IAVF_RX_FLEX_DESC_STATUS1_XTRMD3_VALID_S = 13,
 450         IAVF_RX_FLEX_DESC_STATUS1_XTRMD4_VALID_S = 14,
 451         IAVF_RX_FLEX_DESC_STATUS1_XTRMD5_VALID_S = 15,
 452         IAVF_RX_FLEX_DESC_STATUS1_LAST /* this entry must be last!!! */
 453 };
 454
 455 #define IAVF_RX_FLEX_DESC_IPSEC_CRYPTO_STATUS_MASK  (           \
 456         BIT(IAVF_RX_FLEX_DESC_STATUS1_IPSEC_CRYPTO_STATUS_0) |  \
 457         BIT(IAVF_RX_FLEX_DESC_STATUS1_IPSEC_CRYPTO_STATUS_1) |  \
 458         BIT(IAVF_RX_FLEX_DESC_STATUS1_IPSEC_CRYPTO_STATUS_2) |  \
 459         BIT(IAVF_RX_FLEX_DESC_STATUS1_IPSEC_CRYPTO_STATUS_3))
 460
 461 enum iavf_rx_flex_desc_ipsec_crypto_status {
 462         IAVF_IPSEC_CRYPTO_STATUS_SUCCESS = 0,
 463         IAVF_IPSEC_CRYPTO_STATUS_SAD_MISS,
 464         IAVF_IPSEC_CRYPTO_STATUS_NOT_PROCESSED,
 465         IAVF_IPSEC_CRYPTO_STATUS_ICV_CHECK_FAIL,
 466         IAVF_IPSEC_CRYPTO_STATUS_LENGTH_ERR,
 467         /* Reserved */
 468         IAVF_IPSEC_CRYPTO_STATUS_MISC_ERR = 0xF
 469 };
 470
 471
 472
 473 #define IAVF_TXD_DATA_QW1_DTYPE_SHIFT   (0)
 474 #define IAVF_TXD_DATA_QW1_DTYPE_MASK    (0xFUL << IAVF_TXD_QW1_DTYPE_SHIFT)
 475
 476 #define IAVF_TXD_DATA_QW1_CMD_SHIFT     (4)
 477 #define IAVF_TXD_DATA_QW1_CMD_MASK      (0x3FFUL << IAVF_TXD_DATA_QW1_CMD_SHIFT)
 478
 479 #define IAVF_TXD_DATA_QW1_OFFSET_SHIFT  (16)
 480 #define IAVF_TXD_DATA_QW1_OFFSET_MASK   (0x3FFFFULL << \
 481                                         IAVF_TXD_DATA_QW1_OFFSET_SHIFT)
 482
 483 #define IAVF_TXD_DATA_QW1_OFFSET_MACLEN_SHIFT   (IAVF_TXD_DATA_QW1_OFFSET_SHIFT)
 484 #define IAVF_TXD_DATA_QW1_OFFSET_MACLEN_MASK    \
 485         (0x7FUL << IAVF_TXD_DATA_QW1_OFFSET_MACLEN_SHIFT)
 486
 487 #define IAVF_TXD_DATA_QW1_OFFSET_IPLEN_SHIFT    \
 488         (IAVF_TXD_DATA_QW1_OFFSET_SHIFT + IAVF_TX_DESC_LENGTH_IPLEN_SHIFT)
 489 #define IAVF_TXD_DATA_QW1_OFFSET_IPLEN_MASK     \
 490         (0x7FUL << IAVF_TXD_DATA_QW1_OFFSET_IPLEN_SHIFT)
 491
 492 #define IAVF_TXD_DATA_QW1_OFFSET_L4LEN_SHIFT    \
 493         (IAVF_TXD_DATA_QW1_OFFSET_SHIFT + IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
 494 #define IAVF_TXD_DATA_QW1_OFFSET_L4LEN_MASK     \
 495         (0xFUL << IAVF_TXD_DATA_QW1_OFFSET_L4LEN_SHIFT)
 496
 497 #define IAVF_TXD_DATA_QW1_MACLEN_MASK   \
 498         (0x7FUL << IAVF_TX_DESC_LENGTH_MACLEN_SHIFT)
 499 #define IAVF_TXD_DATA_QW1_IPLEN_MASK    \
 500         (0x7FUL << IAVF_TX_DESC_LENGTH_IPLEN_SHIFT)
 501 #define IAVF_TXD_DATA_QW1_L4LEN_MASK    \
 502         (0xFUL << IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
 503 #define IAVF_TXD_DATA_QW1_FCLEN_MASK    \
 504         (0xFUL << IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
 505
 506 #define IAVF_TXD_DATA_QW1_TX_BUF_SZ_SHIFT       (34)
 507 #define IAVF_TXD_DATA_QW1_TX_BUF_SZ_MASK        \
 508         (0x3FFFULL << IAVF_TXD_DATA_QW1_TX_BUF_SZ_SHIFT)
 509
 510 #define IAVF_TXD_DATA_QW1_L2TAG1_SHIFT          (48)
 511 #define IAVF_TXD_DATA_QW1_L2TAG1_MASK           \
 512         (0xFFFFULL << IAVF_TXD_DATA_QW1_L2TAG1_SHIFT)
 513
 514 #define IAVF_TXD_CTX_QW1_IPSEC_PARAMS_CIPHERBLK_SHIFT   (11)
 515 #define IAVF_TXD_CTX_QW1_IPSEC_PARAMS_CIPHERBLK_MASK    \
 516         (0x7UL << IAVF_TXD_CTX_QW1_IPSEC_PARAMS_CIPHERBLK_SHIFT)
 517
 518 #define IAVF_TXD_CTX_QW1_IPSEC_PARAMS_ICVLEN_SHIFT      (14)
 519 #define IAVF_TXD_CTX_QW1_IPSEC_PARAMS_ICVLEN_MASK       \
 520         (0xFUL << IAVF_TXD_CTX_QW1_IPSEC_PARAMS_ICVLEN_SHIFT)
 521
 522 #define IAVF_TXD_CTX_QW1_SEG_PARAMS_TLEN_SHIFT          (30)
 523 #define IAVF_TXD_CTX_QW1_SEG_PARAMS_TLEN_MASK           \
 524         (0x3FFFFUL << IAVF_TXD_CTX_QW1_SEG_PARAMS_TLEN_SHIFT)
 525
 526 #define IAVF_TXD_CTX_QW1_TSYNC_PARAMS_TLEN_SHIFT        (30)
 527 #define IAVF_TXD_CTX_QW1_TSYNC_PARAMS_TLEN_MASK         \
 528         (0x3FUL << IAVF_TXD_CTX_QW1_SEG_PARAMS_TLEN_SHIFT)
 529
 530 #define IAVF_TXD_CTX_QW1_SEG_PARAMS_MSS_SHIFT           (50)
 531 #define IAVF_TXD_CTX_QW1_SEG_PARAMS_MSS_MASK            \
 532         (0x3FFFUL << IAVF_TXD_CTX_QW1_SEG_PARAMS_MSS_SHIFT)
 533
 534 #define IAVF_TXD_CTX_QW0_TUN_PARAMS_EIPT_SHIFT          (0)
 535 #define IAVF_TXD_CTX_QW0_TUN_PARAMS_EIPT_MASK           (0x3UL)
 536
 537 enum iavf_tx_ctx_desc_tunnel_external_ip_type {
 538         IAVF_TX_CTX_DESC_EIPT_NONE,
 539         IAVF_TX_CTX_DESC_EIPT_IPV6,
 540         IAVF_TX_CTX_DESC_EIPT_IPV4_NO_CHECKSUM_OFFLOAD,
 541         IAVF_TX_CTX_DESC_EIPT_IPV4_CHECKSUM_OFFLOAD
 542 };
 543
 544 #define IAVF_TXD_CTX_QW0_TUN_PARAMS_EIPLEN_SHIFT        (2)
 545 #define IAVF_TXD_CTX_QW0_TUN_PARAMS_EIPLEN_MASK         (0x7FUL)
 546
 547 #define IAVF_TXD_CTX_QW0_TUN_PARAMS_L4TUNT_SHIFT        (9)
 548 #define IAVF_TXD_CTX_QW0_TUN_PARAMS_L4TUNT_MASK         (0x3UL)
 549
 550 enum iavf_tx_ctx_desc_tunnel_l4_tunnel_type {
 551         IAVF_TX_CTX_DESC_L4_TUN_TYP_NO_UDP_GRE,
 552         IAVF_TX_CTX_DESC_L4_TUN_TYP_UDP,
 553         IAVF_TX_CTX_DESC_L4_TUN_TYP_GRE
 554 };
 555
 556 #define IAVF_TXD_CTX_QW0_TUN_PARAMS_EIP_NOINC_SHIFT     (11)
 557 #define IAVF_TXD_CTX_QW0_TUN_PARAMS_EIP_NOINC_MASK      (0x1UL)
 558
 559 #define IAVF_TXD_CTX_QW0_TUN_PARAMS_L4TUNLEN_SHIFT      (12)
 560 #define IAVF_TXD_CTX_QW0_TUN_PARAMS_L4TUNLEN_MASK       (0x7FUL)
 561
 562 #define IAVF_TXD_CTX_QW0_TUN_PARAMS_DECTTL_SHIFT        (19)
 563 #define IAVF_TXD_CTX_QW0_TUN_PARAMS_DECTTL_MASK         (0xFUL)
 564
 565 #define IAVF_TXD_CTX_QW0_TUN_PARAMS_L4T_CS_SHIFT        (23)
 566 #define IAVF_TXD_CTX_QW0_TUN_PARAMS_L4T_CS_MASK         (0x1UL)
 567
 568 #define IAVF_TXD_CTX_QW0_L2TAG2_PARAM                   (32)
 569 #define IAVF_TXD_CTX_QW0_L2TAG2_MASK                    (0xFFFFUL)
 570
 571
 572 #define IAVF_RX_FLEX_DESC_IPSEC_CRYPTO_SAID_MASK        (0xFFFFF)
 573
 574 /* for iavf_32b_rx_flex_desc.ptype_flex_flags0 member */
 575 #define IAVF_RX_FLEX_DESC_PTYPE_M       (0x3FF) /* 10-bits */
 576
 577
 578 /* for iavf_32b_rx_flex_desc.ptype_flex_flags0 member */
 579 #define IAVF_RX_FLEX_DESC_PTYPE_M       (0x3FF) /* 10-bits */
 580
 581 /* for iavf_32b_rx_flex_desc.pkt_len member */
 582 #define IAVF_RX_FLX_DESC_PKT_LEN_M      (0x3FFF) /* 14-bits */
 583
 584 int iavf_dev_rx_queue_setup(struct rte_eth_dev *dev,
 585                            uint16_t queue_idx,
 586                            uint16_t nb_desc,
 587                            unsigned int socket_id,
 588                            const struct rte_eth_rxconf *rx_conf,
 589                            struct rte_mempool *mp);
 590
 591 int iavf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
 592 int iavf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
 593 void iavf_dev_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid);
 594
 595 int iavf_dev_tx_queue_setup(struct rte_eth_dev *dev,
 596                            uint16_t queue_idx,
 597                            uint16_t nb_desc,
 598                            unsigned int socket_id,
 599                            const struct rte_eth_txconf *tx_conf);
 600 int iavf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
 601 int iavf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);
 602 int iavf_dev_tx_done_cleanup(void *txq, uint32_t free_cnt);
 603 void iavf_dev_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid);
 604 void iavf_stop_queues(struct rte_eth_dev *dev);
 605 uint16_t iavf_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
 606                        uint16_t nb_pkts);
 607 uint16_t iavf_recv_pkts_flex_rxd(void *rx_queue,
 608                                  struct rte_mbuf **rx_pkts,
 609                                  uint16_t nb_pkts);
 610 uint16_t iavf_recv_scattered_pkts(void *rx_queue,
 611                                  struct rte_mbuf **rx_pkts,
 612                                  uint16_t nb_pkts);
 613 uint16_t iavf_recv_scattered_pkts_flex_rxd(void *rx_queue,
 614                                            struct rte_mbuf **rx_pkts,
 615                                            uint16_t nb_pkts);
 616 uint16_t iavf_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 617                        uint16_t nb_pkts);
 618 uint16_t iavf_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 619                        uint16_t nb_pkts);
 620 void iavf_set_rx_function(struct rte_eth_dev *dev);
 621 void iavf_set_tx_function(struct rte_eth_dev *dev);
 622 void iavf_dev_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
 623                           struct rte_eth_rxq_info *qinfo);
 624 void iavf_dev_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
 625                           struct rte_eth_txq_info *qinfo);
 626 uint32_t iavf_dev_rxq_count(void *rx_queue);
 627 int iavf_dev_rx_desc_status(void *rx_queue, uint16_t offset);
 628 int iavf_dev_tx_desc_status(void *tx_queue, uint16_t offset);
 629
 630 uint16_t iavf_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
 631                            uint16_t nb_pkts);
 632 uint16_t iavf_recv_pkts_vec_flex_rxd(void *rx_queue, struct rte_mbuf **rx_pkts,
 633                                      uint16_t nb_pkts);
 634 uint16_t iavf_recv_scattered_pkts_vec(void *rx_queue,
 635                                      struct rte_mbuf **rx_pkts,
 636                                      uint16_t nb_pkts);
 637 uint16_t iavf_recv_scattered_pkts_vec_flex_rxd(void *rx_queue,
 638                                                struct rte_mbuf **rx_pkts,
 639                                                uint16_t nb_pkts);
 640 uint16_t iavf_xmit_fixed_burst_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
 641                                   uint16_t nb_pkts);
 642 uint16_t iavf_recv_pkts_vec_avx2(void *rx_queue, struct rte_mbuf **rx_pkts,
 643                                  uint16_t nb_pkts);
 644 uint16_t iavf_recv_pkts_vec_avx2_flex_rxd(void *rx_queue,
 645                                           struct rte_mbuf **rx_pkts,
 646                                           uint16_t nb_pkts);
 647 uint16_t iavf_recv_scattered_pkts_vec_avx2(void *rx_queue,
 648                                            struct rte_mbuf **rx_pkts,
 649                                            uint16_t nb_pkts);
 650 uint16_t iavf_recv_scattered_pkts_vec_avx2_flex_rxd(void *rx_queue,
 651                                                     struct rte_mbuf **rx_pkts,
 652                                                     uint16_t nb_pkts);
 653 uint16_t iavf_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
 654                             uint16_t nb_pkts);
 655 uint16_t iavf_xmit_pkts_vec_avx2(void *tx_queue, struct rte_mbuf **tx_pkts,
 656                                  uint16_t nb_pkts);
 657 int iavf_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc);
 658 int iavf_rx_vec_dev_check(struct rte_eth_dev *dev);
 659 int iavf_tx_vec_dev_check(struct rte_eth_dev *dev);
 660 int iavf_rxq_vec_setup(struct iavf_rx_queue *rxq);
 661 int iavf_txq_vec_setup(struct iavf_tx_queue *txq);
 662 uint16_t iavf_recv_pkts_vec_avx512(void *rx_queue, struct rte_mbuf **rx_pkts,
 663                                    uint16_t nb_pkts);
 664 uint16_t iavf_recv_pkts_vec_avx512_offload(void *rx_queue,
 665                                            struct rte_mbuf **rx_pkts,
 666                                            uint16_t nb_pkts);
 667 uint16_t iavf_recv_pkts_vec_avx512_flex_rxd(void *rx_queue,
 668                                             struct rte_mbuf **rx_pkts,
 669                                             uint16_t nb_pkts);
 670 uint16_t iavf_recv_pkts_vec_avx512_flex_rxd_offload(void *rx_queue,
 671                                                     struct rte_mbuf **rx_pkts,
 672                                                     uint16_t nb_pkts);
 673 uint16_t iavf_recv_scattered_pkts_vec_avx512(void *rx_queue,
 674                                              struct rte_mbuf **rx_pkts,
 675                                              uint16_t nb_pkts);
 676 uint16_t iavf_recv_scattered_pkts_vec_avx512_offload(void *rx_queue,
 677                                                      struct rte_mbuf **rx_pkts,
 678                                                      uint16_t nb_pkts);
 679 uint16_t iavf_recv_scattered_pkts_vec_avx512_flex_rxd(void *rx_queue,
 680                                                       struct rte_mbuf **rx_pkts,
 681                                                       uint16_t nb_pkts);
 682 uint16_t iavf_recv_scattered_pkts_vec_avx512_flex_rxd_offload(void *rx_queue,
 683                                                               struct rte_mbuf **rx_pkts,
 684                                                               uint16_t nb_pkts);
 685 uint16_t iavf_xmit_pkts_vec_avx512(void *tx_queue, struct rte_mbuf **tx_pkts,
 686                                    uint16_t nb_pkts);
 687 uint16_t iavf_xmit_pkts_vec_avx512_offload(void *tx_queue,
 688                                            struct rte_mbuf **tx_pkts,
 689                                            uint16_t nb_pkts);
 690 int iavf_txq_vec_setup_avx512(struct iavf_tx_queue *txq);
 691
 692 uint8_t iavf_proto_xtr_type_to_rxdid(uint8_t xtr_type);
 693
 694 void iavf_set_default_ptype_table(struct rte_eth_dev *dev);
 695
 696 static inline
 697 void iavf_dump_rx_descriptor(struct iavf_rx_queue *rxq,
 698                             const volatile void *desc,
 699                             uint16_t rx_id)
 700 {
 701 #ifdef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
 702         const volatile union iavf_16byte_rx_desc *rx_desc = desc;
 703
 704         printf("Queue %d Rx_desc %d: QW0: 0x%016"PRIx64" QW1: 0x%016"PRIx64"\n",
 705                rxq->queue_id, rx_id, rx_desc->read.pkt_addr,
 706                rx_desc->read.hdr_addr);
 707 #else
 708         const volatile union iavf_32byte_rx_desc *rx_desc = desc;
 709
 710         printf("Queue %d Rx_desc %d: QW0: 0x%016"PRIx64" QW1: 0x%016"PRIx64
 711                " QW2: 0x%016"PRIx64" QW3: 0x%016"PRIx64"\n", rxq->queue_id,
 712                rx_id, rx_desc->read.pkt_addr, rx_desc->read.hdr_addr,
 713                rx_desc->read.rsvd1, rx_desc->read.rsvd2);
 714 #endif
 715 }
 716
 717 /* All the descriptors are 16 bytes, so just use one of them
 718  * to print the qwords
 719  */
 720 static inline
 721 void iavf_dump_tx_descriptor(const struct iavf_tx_queue *txq,
 722                             const volatile void *desc, uint16_t tx_id)
 723 {
 724         const char *name;
 725         const volatile struct iavf_tx_desc *tx_desc = desc;
 726         enum iavf_tx_desc_dtype_value type;
 727
 728
 729         type = (enum iavf_tx_desc_dtype_value)
 730                 rte_le_to_cpu_64(tx_desc->cmd_type_offset_bsz &
 731                         rte_cpu_to_le_64(IAVF_TXD_DATA_QW1_DTYPE_MASK));
 732         switch (type) {
 733         case IAVF_TX_DESC_DTYPE_DATA:
 734                 name = "Tx_data_desc";
 735                 break;
 736         case IAVF_TX_DESC_DTYPE_CONTEXT:
 737                 name = "Tx_context_desc";
 738                 break;
 739         case IAVF_TX_DESC_DTYPE_IPSEC:
 740                 name = "Tx_IPsec_desc";
 741                 break;
 742         default:
 743                 name = "unknown_desc";
 744                 break;
 745         }
 746
 747         printf("Queue %d %s %d: QW0: 0x%016"PRIx64" QW1: 0x%016"PRIx64"\n",
 748                 txq->queue_id, name, tx_id, tx_desc->buffer_addr,
 749                 tx_desc->cmd_type_offset_bsz);
 750 }
 751
 752 #define FDIR_PROC_ENABLE_PER_QUEUE(ad, on) do { \
 753         int i; \
 754         for (i = 0; i < (ad)->dev_data->nb_rx_queues; i++) { \
 755                 struct iavf_rx_queue *rxq = (ad)->dev_data->rx_queues[i]; \
 756                 if (!rxq) \
 757                         continue; \
 758                 rxq->fdir_enabled = on; \
 759         } \
 760         PMD_DRV_LOG(DEBUG, "FDIR processing on RX set to %d", on); \
 761 } while (0)
 762
 763 /* Enable/disable flow director Rx processing in data path. */
 764 static inline
 765 void iavf_fdir_rx_proc_enable(struct iavf_adapter *ad, bool on)
 766 {
 767         if (on) {
 768                 /* enable flow director processing */
 769                 FDIR_PROC_ENABLE_PER_QUEUE(ad, on);
 770                 ad->fdir_ref_cnt++;
 771         } else {
 772                 if (ad->fdir_ref_cnt >= 1) {
 773                         ad->fdir_ref_cnt--;
 774
 775                         if (ad->fdir_ref_cnt == 0)
 776                                 FDIR_PROC_ENABLE_PER_QUEUE(ad, on);
 777                 }
 778         }
 779 }
 780
 781 #ifdef RTE_LIBRTE_IAVF_DEBUG_DUMP_DESC
 782 #define IAVF_DUMP_RX_DESC(rxq, desc, rx_id) \
 783         iavf_dump_rx_descriptor(rxq, desc, rx_id)
 784 #define IAVF_DUMP_TX_DESC(txq, desc, tx_id) \
 785         iavf_dump_tx_descriptor(txq, desc, tx_id)
 786 #else
 787 #define IAVF_DUMP_RX_DESC(rxq, desc, rx_id) do { } while (0)
 788 #define IAVF_DUMP_TX_DESC(txq, desc, tx_id) do { } while (0)
 789 #endif
 790
 791 #endif /* _IAVF_RXTX_H_ */