drivers/net/iavf/iavf_rxtx.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2017 Intel Corporation
   3  */
   4
   5 #ifndef _IAVF_RXTX_H_
   6 #define _IAVF_RXTX_H_
   7
   8 /* In QLEN must be whole number of 32 descriptors. */
   9 #define IAVF_ALIGN_RING_DESC      32
  10 #define IAVF_MIN_RING_DESC        64
  11 #define IAVF_MAX_RING_DESC        4096
  12 #define IAVF_DMA_MEM_ALIGN        4096
  13 /* Base address of the HW descriptor ring should be 128B aligned. */
  14 #define IAVF_RING_BASE_ALIGN      128
  15
  16 /* used for Rx Bulk Allocate */
  17 #define IAVF_RX_MAX_BURST         32
  18
  19 /* used for Vector PMD */
  20 #define IAVF_VPMD_RX_MAX_BURST    32
  21 #define IAVF_VPMD_TX_MAX_BURST    32
  22 #define IAVF_RXQ_REARM_THRESH     32
  23 #define IAVF_VPMD_DESCS_PER_LOOP  4
  24 #define IAVF_VPMD_TX_MAX_FREE_BUF 64
  25
  26 #define IAVF_NO_VECTOR_FLAGS (                           \
  27                 DEV_TX_OFFLOAD_MULTI_SEGS |              \
  28                 DEV_TX_OFFLOAD_VLAN_INSERT |             \
  29                 DEV_TX_OFFLOAD_SCTP_CKSUM |              \
  30                 DEV_TX_OFFLOAD_UDP_CKSUM |               \
  31                 DEV_TX_OFFLOAD_TCP_TSO |                 \
  32                 DEV_TX_OFFLOAD_TCP_CKSUM)
  33
  34 #define DEFAULT_TX_RS_THRESH     32
  35 #define DEFAULT_TX_FREE_THRESH   32
  36
  37 #define IAVF_MIN_TSO_MSS          256
  38 #define IAVF_MAX_TSO_MSS          9668
  39 #define IAVF_TSO_MAX_SEG          UINT8_MAX
  40 #define IAVF_TX_MAX_MTU_SEG       8
  41
  42 #define IAVF_TX_CKSUM_OFFLOAD_MASK (             \
  43                 PKT_TX_IP_CKSUM |                \
  44                 PKT_TX_L4_MASK |                 \
  45                 PKT_TX_TCP_SEG)
  46
  47 #define IAVF_TX_OFFLOAD_MASK (  \
  48                 PKT_TX_OUTER_IPV6 |              \
  49                 PKT_TX_OUTER_IPV4 |              \
  50                 PKT_TX_IPV6 |                    \
  51                 PKT_TX_IPV4 |                    \
  52                 PKT_TX_VLAN_PKT |                \
  53                 PKT_TX_IP_CKSUM |                \
  54                 PKT_TX_L4_MASK |                 \
  55                 PKT_TX_TCP_SEG)
  56
  57 #define IAVF_TX_OFFLOAD_NOTSUP_MASK \
  58                 (PKT_TX_OFFLOAD_MASK ^ IAVF_TX_OFFLOAD_MASK)
  59
  60 /* HW desc structure, both 16-byte and 32-byte types are supported */
  61 #ifdef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
  62 #define iavf_rx_desc iavf_16byte_rx_desc
  63 #else
  64 #define iavf_rx_desc iavf_32byte_rx_desc
  65 #endif
  66
  67 struct iavf_rxq_ops {
  68         void (*release_mbufs)(struct iavf_rx_queue *rxq);
  69 };
  70
  71 struct iavf_txq_ops {
  72         void (*release_mbufs)(struct iavf_tx_queue *txq);
  73 };
  74
  75 /* Structure associated with each Rx queue. */
  76 struct iavf_rx_queue {
  77         struct rte_mempool *mp;       /* mbuf pool to populate Rx ring */
  78         const struct rte_memzone *mz; /* memzone for Rx ring */
  79         volatile union iavf_rx_desc *rx_ring; /* Rx ring virtual address */
  80         uint64_t rx_ring_phys_addr;   /* Rx ring DMA address */
  81         struct rte_mbuf **sw_ring;     /* address of SW ring */
  82         uint16_t nb_rx_desc;          /* ring length */
  83         uint16_t rx_tail;             /* current value of tail */
  84         volatile uint8_t *qrx_tail;   /* register address of tail */
  85         uint16_t rx_free_thresh;      /* max free RX desc to hold */
  86         uint16_t nb_rx_hold;          /* number of held free RX desc */
  87         struct rte_mbuf *pkt_first_seg; /* first segment of current packet */
  88         struct rte_mbuf *pkt_last_seg;  /* last segment of current packet */
  89         struct rte_mbuf fake_mbuf;      /* dummy mbuf */
  90
  91         /* used for VPMD */
  92         uint16_t rxrearm_nb;       /* number of remaining to be re-armed */
  93         uint16_t rxrearm_start;    /* the idx we start the re-arming from */
  94         uint64_t mbuf_initializer; /* value to init mbufs */
  95
  96         /* for rx bulk */
  97         uint16_t rx_nb_avail;      /* number of staged packets ready */
  98         uint16_t rx_next_avail;    /* index of next staged packets */
  99         uint16_t rx_free_trigger;  /* triggers rx buffer allocation */
 100         struct rte_mbuf *rx_stage[IAVF_RX_MAX_BURST * 2]; /* store mbuf */
 101
 102         uint16_t port_id;        /* device port ID */
 103         uint8_t crc_len;        /* 0 if CRC stripped, 4 otherwise */
 104         uint16_t queue_id;      /* Rx queue index */
 105         uint16_t rx_buf_len;    /* The packet buffer size */
 106         uint16_t rx_hdr_len;    /* The header buffer size */
 107         uint16_t max_pkt_len;   /* Maximum packet length */
 108         struct iavf_vsi *vsi; /**< the VSI this queue belongs to */
 109
 110         bool q_set;             /* if rx queue has been configured */
 111         bool rx_deferred_start; /* don't start this queue in dev start */
 112         const struct iavf_rxq_ops *ops;
 113 };
 114
 115 struct iavf_tx_entry {
 116         struct rte_mbuf *mbuf;
 117         uint16_t next_id;
 118         uint16_t last_id;
 119 };
 120
 121 /* Structure associated with each TX queue. */
 122 struct iavf_tx_queue {
 123         const struct rte_memzone *mz;  /* memzone for Tx ring */
 124         volatile struct iavf_tx_desc *tx_ring; /* Tx ring virtual address */
 125         uint64_t tx_ring_phys_addr;    /* Tx ring DMA address */
 126         struct iavf_tx_entry *sw_ring;  /* address array of SW ring */
 127         uint16_t nb_tx_desc;           /* ring length */
 128         uint16_t tx_tail;              /* current value of tail */
 129         volatile uint8_t *qtx_tail;    /* register address of tail */
 130         /* number of used desc since RS bit set */
 131         uint16_t nb_used;
 132         uint16_t nb_free;
 133         uint16_t last_desc_cleaned;    /* last desc have been cleaned*/
 134         uint16_t free_thresh;
 135         uint16_t rs_thresh;
 136
 137         uint16_t port_id;
 138         uint16_t queue_id;
 139         uint64_t offloads;
 140         uint16_t next_dd;              /* next to set RS, for VPMD */
 141         uint16_t next_rs;              /* next to check DD,  for VPMD */
 142
 143         bool q_set;                    /* if rx queue has been configured */
 144         bool tx_deferred_start;        /* don't start this queue in dev start */
 145         const struct iavf_txq_ops *ops;
 146 };
 147
 148 /* Offload features */
 149 union iavf_tx_offload {
 150         uint64_t data;
 151         struct {
 152                 uint64_t l2_len:7; /* L2 (MAC) Header Length. */
 153                 uint64_t l3_len:9; /* L3 (IP) Header Length. */
 154                 uint64_t l4_len:8; /* L4 Header Length. */
 155                 uint64_t tso_segsz:16; /* TCP TSO segment size */
 156                 /* uint64_t unused : 24; */
 157         };
 158 };
 159
 160 /* Rx Flex Descriptors
 161  * These descriptors are used instead of the legacy version descriptors
 162  */
 163 union iavf_16b_rx_flex_desc {
 164         struct {
 165                 __le64 pkt_addr; /* Packet buffer address */
 166                 __le64 hdr_addr; /* Header buffer address */
 167                                  /* bit 0 of hdr_addr is DD bit */
 168         } read;
 169         struct {
 170                 /* Qword 0 */
 171                 u8 rxdid; /* descriptor builder profile ID */
 172                 u8 mir_id_umb_cast; /* mirror=[5:0], umb=[7:6] */
 173                 __le16 ptype_flex_flags0; /* ptype=[9:0], ff0=[15:10] */
 174                 __le16 pkt_len; /* [15:14] are reserved */
 175                 __le16 hdr_len_sph_flex_flags1; /* header=[10:0] */
 176                                                 /* sph=[11:11] */
 177                                                 /* ff1/ext=[15:12] */
 178
 179                 /* Qword 1 */
 180                 __le16 status_error0;
 181                 __le16 l2tag1;
 182                 __le16 flex_meta0;
 183                 __le16 flex_meta1;
 184         } wb; /* writeback */
 185 };
 186
 187 union iavf_32b_rx_flex_desc {
 188         struct {
 189                 __le64 pkt_addr; /* Packet buffer address */
 190                 __le64 hdr_addr; /* Header buffer address */
 191                                  /* bit 0 of hdr_addr is DD bit */
 192                 __le64 rsvd1;
 193                 __le64 rsvd2;
 194         } read;
 195         struct {
 196                 /* Qword 0 */
 197                 u8 rxdid; /* descriptor builder profile ID */
 198                 u8 mir_id_umb_cast; /* mirror=[5:0], umb=[7:6] */
 199                 __le16 ptype_flex_flags0; /* ptype=[9:0], ff0=[15:10] */
 200                 __le16 pkt_len; /* [15:14] are reserved */
 201                 __le16 hdr_len_sph_flex_flags1; /* header=[10:0] */
 202                                                 /* sph=[11:11] */
 203                                                 /* ff1/ext=[15:12] */
 204
 205                 /* Qword 1 */
 206                 __le16 status_error0;
 207                 __le16 l2tag1;
 208                 __le16 flex_meta0;
 209                 __le16 flex_meta1;
 210
 211                 /* Qword 2 */
 212                 __le16 status_error1;
 213                 u8 flex_flags2;
 214                 u8 time_stamp_low;
 215                 __le16 l2tag2_1st;
 216                 __le16 l2tag2_2nd;
 217
 218                 /* Qword 3 */
 219                 __le16 flex_meta2;
 220                 __le16 flex_meta3;
 221                 union {
 222                         struct {
 223                                 __le16 flex_meta4;
 224                                 __le16 flex_meta5;
 225                         } flex;
 226                         __le32 ts_high;
 227                 } flex_ts;
 228         } wb; /* writeback */
 229 };
 230
 231 /* Rx Flex Descriptor
 232  * RxDID Profile ID 16-21
 233  * Flex-field 0: RSS hash lower 16-bits
 234  * Flex-field 1: RSS hash upper 16-bits
 235  * Flex-field 2: Flow ID lower 16-bits
 236  * Flex-field 3: Flow ID upper 16-bits
 237  * Flex-field 4: AUX0
 238  * Flex-field 5: AUX1
 239  */
 240 struct iavf_32b_rx_flex_desc_comms {
 241         /* Qword 0 */
 242         u8 rxdid;
 243         u8 mir_id_umb_cast;
 244         __le16 ptype_flexi_flags0;
 245         __le16 pkt_len;
 246         __le16 hdr_len_sph_flex_flags1;
 247
 248         /* Qword 1 */
 249         __le16 status_error0;
 250         __le16 l2tag1;
 251         __le32 rss_hash;
 252
 253         /* Qword 2 */
 254         __le16 status_error1;
 255         u8 flexi_flags2;
 256         u8 ts_low;
 257         __le16 l2tag2_1st;
 258         __le16 l2tag2_2nd;
 259
 260         /* Qword 3 */
 261         __le32 flow_id;
 262         union {
 263                 struct {
 264                         __le16 aux0;
 265                         __le16 aux1;
 266                 } flex;
 267                 __le32 ts_high;
 268         } flex_ts;
 269 };
 270
 271 /* Rx Flex Descriptor
 272  * RxDID Profile ID 22-23 (swap Hash and FlowID)
 273  * Flex-field 0: Flow ID lower 16-bits
 274  * Flex-field 1: Flow ID upper 16-bits
 275  * Flex-field 2: RSS hash lower 16-bits
 276  * Flex-field 3: RSS hash upper 16-bits
 277  * Flex-field 4: AUX0
 278  * Flex-field 5: AUX1
 279  */
 280 struct iavf_32b_rx_flex_desc_comms_ovs {
 281         /* Qword 0 */
 282         u8 rxdid;
 283         u8 mir_id_umb_cast;
 284         __le16 ptype_flexi_flags0;
 285         __le16 pkt_len;
 286         __le16 hdr_len_sph_flex_flags1;
 287
 288         /* Qword 1 */
 289         __le16 status_error0;
 290         __le16 l2tag1;
 291         __le32 flow_id;
 292
 293         /* Qword 2 */
 294         __le16 status_error1;
 295         u8 flexi_flags2;
 296         u8 ts_low;
 297         __le16 l2tag2_1st;
 298         __le16 l2tag2_2nd;
 299
 300         /* Qword 3 */
 301         __le32 rss_hash;
 302         union {
 303                 struct {
 304                         __le16 aux0;
 305                         __le16 aux1;
 306                 } flex;
 307                 __le32 ts_high;
 308         } flex_ts;
 309 };
 310
 311 /* Receive Flex Descriptor profile IDs: There are a total
 312  * of 64 profiles where profile IDs 0/1 are for legacy; and
 313  * profiles 2-63 are flex profiles that can be programmed
 314  * with a specific metadata (profile 7 reserved for HW)
 315  */
 316 enum iavf_rxdid {
 317         IAVF_RXDID_LEGACY_0             = 0,
 318         IAVF_RXDID_LEGACY_1             = 1,
 319         IAVF_RXDID_FLEX_NIC             = 2,
 320         IAVF_RXDID_FLEX_NIC_2           = 6,
 321         IAVF_RXDID_HW                   = 7,
 322         IAVF_RXDID_COMMS_GENERIC        = 16,
 323         IAVF_RXDID_COMMS_AUX_VLAN       = 17,
 324         IAVF_RXDID_COMMS_AUX_IPV4       = 18,
 325         IAVF_RXDID_COMMS_AUX_IPV6       = 19,
 326         IAVF_RXDID_COMMS_AUX_IPV6_FLOW  = 20,
 327         IAVF_RXDID_COMMS_AUX_TCP        = 21,
 328         IAVF_RXDID_COMMS_OVS_1          = 22,
 329         IAVF_RXDID_COMMS_OVS_2          = 23,
 330         IAVF_RXDID_LAST                 = 63,
 331 };
 332
 333 enum iavf_rx_flex_desc_status_error_0_bits {
 334         /* Note: These are predefined bit offsets */
 335         IAVF_RX_FLEX_DESC_STATUS0_DD_S = 0,
 336         IAVF_RX_FLEX_DESC_STATUS0_EOF_S,
 337         IAVF_RX_FLEX_DESC_STATUS0_HBO_S,
 338         IAVF_RX_FLEX_DESC_STATUS0_L3L4P_S,
 339         IAVF_RX_FLEX_DESC_STATUS0_XSUM_IPE_S,
 340         IAVF_RX_FLEX_DESC_STATUS0_XSUM_L4E_S,
 341         IAVF_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S,
 342         IAVF_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S,
 343         IAVF_RX_FLEX_DESC_STATUS0_LPBK_S,
 344         IAVF_RX_FLEX_DESC_STATUS0_IPV6EXADD_S,
 345         IAVF_RX_FLEX_DESC_STATUS0_RXE_S,
 346         IAVF_RX_FLEX_DESC_STATUS0_CRCP_S,
 347         IAVF_RX_FLEX_DESC_STATUS0_RSS_VALID_S,
 348         IAVF_RX_FLEX_DESC_STATUS0_L2TAG1P_S,
 349         IAVF_RX_FLEX_DESC_STATUS0_XTRMD0_VALID_S,
 350         IAVF_RX_FLEX_DESC_STATUS0_XTRMD1_VALID_S,
 351         IAVF_RX_FLEX_DESC_STATUS0_LAST /* this entry must be last!!! */
 352 };
 353
 354 /* for iavf_32b_rx_flex_desc.ptype_flex_flags0 member */
 355 #define IAVF_RX_FLEX_DESC_PTYPE_M       (0x3FF) /* 10-bits */
 356
 357 /* for iavf_32b_rx_flex_desc.pkt_len member */
 358 #define IAVF_RX_FLX_DESC_PKT_LEN_M      (0x3FFF) /* 14-bits */
 359
 360 int iavf_dev_rx_queue_setup(struct rte_eth_dev *dev,
 361                            uint16_t queue_idx,
 362                            uint16_t nb_desc,
 363                            unsigned int socket_id,
 364                            const struct rte_eth_rxconf *rx_conf,
 365                            struct rte_mempool *mp);
 366
 367 int iavf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
 368 int iavf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
 369 void iavf_dev_rx_queue_release(void *rxq);
 370
 371 int iavf_dev_tx_queue_setup(struct rte_eth_dev *dev,
 372                            uint16_t queue_idx,
 373                            uint16_t nb_desc,
 374                            unsigned int socket_id,
 375                            const struct rte_eth_txconf *tx_conf);
 376 int iavf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
 377 int iavf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);
 378 void iavf_dev_tx_queue_release(void *txq);
 379 void iavf_stop_queues(struct rte_eth_dev *dev);
 380 uint16_t iavf_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
 381                        uint16_t nb_pkts);
 382 uint16_t iavf_recv_scattered_pkts(void *rx_queue,
 383                                  struct rte_mbuf **rx_pkts,
 384                                  uint16_t nb_pkts);
 385 uint16_t iavf_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 386                        uint16_t nb_pkts);
 387 uint16_t iavf_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 388                        uint16_t nb_pkts);
 389 void iavf_set_rx_function(struct rte_eth_dev *dev);
 390 void iavf_set_tx_function(struct rte_eth_dev *dev);
 391 void iavf_dev_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
 392                           struct rte_eth_rxq_info *qinfo);
 393 void iavf_dev_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
 394                           struct rte_eth_txq_info *qinfo);
 395 uint32_t iavf_dev_rxq_count(struct rte_eth_dev *dev, uint16_t queue_id);
 396 int iavf_dev_rx_desc_status(void *rx_queue, uint16_t offset);
 397 int iavf_dev_tx_desc_status(void *tx_queue, uint16_t offset);
 398
 399 uint16_t iavf_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
 400                            uint16_t nb_pkts);
 401 uint16_t iavf_recv_scattered_pkts_vec(void *rx_queue,
 402                                      struct rte_mbuf **rx_pkts,
 403                                      uint16_t nb_pkts);
 404 uint16_t iavf_xmit_fixed_burst_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
 405                                   uint16_t nb_pkts);
 406 uint16_t iavf_recv_pkts_vec_avx2(void *rx_queue, struct rte_mbuf **rx_pkts,
 407                                  uint16_t nb_pkts);
 408 uint16_t iavf_recv_scattered_pkts_vec_avx2(void *rx_queue,
 409                                            struct rte_mbuf **rx_pkts,
 410                                            uint16_t nb_pkts);
 411 uint16_t iavf_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
 412                             uint16_t nb_pkts);
 413 uint16_t iavf_xmit_pkts_vec_avx2(void *tx_queue, struct rte_mbuf **tx_pkts,
 414                                  uint16_t nb_pkts);
 415 int iavf_rx_vec_dev_check(struct rte_eth_dev *dev);
 416 int iavf_tx_vec_dev_check(struct rte_eth_dev *dev);
 417 int iavf_rxq_vec_setup(struct iavf_rx_queue *rxq);
 418 int iavf_txq_vec_setup(struct iavf_tx_queue *txq);
 419
 420 const uint32_t *iavf_get_default_ptype_table(void);
 421
 422 static inline
 423 void iavf_dump_rx_descriptor(struct iavf_rx_queue *rxq,
 424                             const volatile void *desc,
 425                             uint16_t rx_id)
 426 {
 427 #ifdef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
 428         const volatile union iavf_16byte_rx_desc *rx_desc = desc;
 429
 430         printf("Queue %d Rx_desc %d: QW0: 0x%016"PRIx64" QW1: 0x%016"PRIx64"\n",
 431                rxq->queue_id, rx_id, rx_desc->read.pkt_addr,
 432                rx_desc->read.hdr_addr);
 433 #else
 434         const volatile union iavf_32byte_rx_desc *rx_desc = desc;
 435
 436         printf("Queue %d Rx_desc %d: QW0: 0x%016"PRIx64" QW1: 0x%016"PRIx64
 437                " QW2: 0x%016"PRIx64" QW3: 0x%016"PRIx64"\n", rxq->queue_id,
 438                rx_id, rx_desc->read.pkt_addr, rx_desc->read.hdr_addr,
 439                rx_desc->read.rsvd1, rx_desc->read.rsvd2);
 440 #endif
 441 }
 442
 443 /* All the descriptors are 16 bytes, so just use one of them
 444  * to print the qwords
 445  */
 446 static inline
 447 void iavf_dump_tx_descriptor(const struct iavf_tx_queue *txq,
 448                             const volatile void *desc, uint16_t tx_id)
 449 {
 450         const char *name;
 451         const volatile struct iavf_tx_desc *tx_desc = desc;
 452         enum iavf_tx_desc_dtype_value type;
 453
 454         type = (enum iavf_tx_desc_dtype_value)rte_le_to_cpu_64(
 455                 tx_desc->cmd_type_offset_bsz &
 456                 rte_cpu_to_le_64(IAVF_TXD_QW1_DTYPE_MASK));
 457         switch (type) {
 458         case IAVF_TX_DESC_DTYPE_DATA:
 459                 name = "Tx_data_desc";
 460                 break;
 461         case IAVF_TX_DESC_DTYPE_CONTEXT:
 462                 name = "Tx_context_desc";
 463                 break;
 464         default:
 465                 name = "unknown_desc";
 466                 break;
 467         }
 468
 469         printf("Queue %d %s %d: QW0: 0x%016"PRIx64" QW1: 0x%016"PRIx64"\n",
 470                txq->queue_id, name, tx_id, tx_desc->buffer_addr,
 471                tx_desc->cmd_type_offset_bsz);
 472 }
 473
 474 #ifdef RTE_LIBRTE_IAVF_DEBUG_DUMP_DESC
 475 #define IAVF_DUMP_RX_DESC(rxq, desc, rx_id) \
 476         iavf_dump_rx_descriptor(rxq, desc, rx_id)
 477 #define IAVF_DUMP_TX_DESC(txq, desc, tx_id) \
 478         iavf_dump_tx_descriptor(txq, desc, tx_id)
 479 #else
 480 #define IAVF_DUMP_RX_DESC(rxq, desc, rx_id) do { } while (0)
 481 #define IAVF_DUMP_TX_DESC(txq, desc, tx_id) do { } while (0)
 482 #endif
 483
 484 #endif /* _IAVF_RXTX_H_ */