drivers/net/iavf/iavf_rxtx.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2017 Intel Corporation
   3  */
   4
   5 #ifndef _IAVF_RXTX_H_
   6 #define _IAVF_RXTX_H_
   7
   8 /* In QLEN must be whole number of 32 descriptors. */
   9 #define IAVF_ALIGN_RING_DESC      32
  10 #define IAVF_MIN_RING_DESC        64
  11 #define IAVF_MAX_RING_DESC        4096
  12 #define IAVF_DMA_MEM_ALIGN        4096
  13 /* Base address of the HW descriptor ring should be 128B aligned. */
  14 #define IAVF_RING_BASE_ALIGN      128
  15
  16 /* used for Rx Bulk Allocate */
  17 #define IAVF_RX_MAX_BURST         32
  18
  19 /* used for Vector PMD */
  20 #define IAVF_VPMD_RX_MAX_BURST    32
  21 #define IAVF_VPMD_TX_MAX_BURST    32
  22 #define IAVF_RXQ_REARM_THRESH     32
  23 #define IAVF_VPMD_DESCS_PER_LOOP  4
  24 #define IAVF_VPMD_TX_MAX_FREE_BUF 64
  25
  26 #define IAVF_TX_NO_VECTOR_FLAGS (                                \
  27                 RTE_ETH_TX_OFFLOAD_MULTI_SEGS |          \
  28                 RTE_ETH_TX_OFFLOAD_TCP_TSO |             \
  29                 RTE_ETH_TX_OFFLOAD_SECURITY)
  30
  31 #define IAVF_TX_VECTOR_OFFLOAD (                                 \
  32                 RTE_ETH_TX_OFFLOAD_VLAN_INSERT |                 \
  33                 RTE_ETH_TX_OFFLOAD_QINQ_INSERT |                 \
  34                 RTE_ETH_TX_OFFLOAD_IPV4_CKSUM |          \
  35                 RTE_ETH_TX_OFFLOAD_SCTP_CKSUM |          \
  36                 RTE_ETH_TX_OFFLOAD_UDP_CKSUM |           \
  37                 RTE_ETH_TX_OFFLOAD_TCP_CKSUM)
  38
  39 #define IAVF_RX_VECTOR_OFFLOAD (                                 \
  40                 RTE_ETH_RX_OFFLOAD_CHECKSUM |            \
  41                 RTE_ETH_RX_OFFLOAD_SCTP_CKSUM |          \
  42                 RTE_ETH_RX_OFFLOAD_VLAN |                \
  43                 RTE_ETH_RX_OFFLOAD_RSS_HASH)
  44
  45 #define IAVF_VECTOR_PATH 0
  46 #define IAVF_VECTOR_OFFLOAD_PATH 1
  47
  48 #define DEFAULT_TX_RS_THRESH     32
  49 #define DEFAULT_TX_FREE_THRESH   32
  50
  51 #define IAVF_MIN_TSO_MSS          256
  52 #define IAVF_MAX_TSO_MSS          9668
  53 #define IAVF_TSO_MAX_SEG          UINT8_MAX
  54 #define IAVF_TX_MAX_MTU_SEG       8
  55
  56 #define IAVF_TX_CKSUM_OFFLOAD_MASK (             \
  57                 RTE_MBUF_F_TX_IP_CKSUM |                 \
  58                 RTE_MBUF_F_TX_L4_MASK |          \
  59                 RTE_MBUF_F_TX_TCP_SEG)
  60
  61 #define IAVF_TX_OFFLOAD_MASK (  \
  62                 RTE_MBUF_F_TX_OUTER_IPV6 |               \
  63                 RTE_MBUF_F_TX_OUTER_IPV4 |               \
  64                 RTE_MBUF_F_TX_IPV6 |                     \
  65                 RTE_MBUF_F_TX_IPV4 |                     \
  66                 RTE_MBUF_F_TX_VLAN |             \
  67                 RTE_MBUF_F_TX_IP_CKSUM |                 \
  68                 RTE_MBUF_F_TX_L4_MASK |          \
  69                 RTE_MBUF_F_TX_TCP_SEG |          \
  70                 RTE_ETH_TX_OFFLOAD_SECURITY)
  71
  72 #define IAVF_TX_OFFLOAD_NOTSUP_MASK \
  73                 (RTE_MBUF_F_TX_OFFLOAD_MASK ^ IAVF_TX_OFFLOAD_MASK)
  74
  75 /**
  76  * Rx Flex Descriptors
  77  * These descriptors are used instead of the legacy version descriptors
  78  */
  79 union iavf_16b_rx_flex_desc {
  80         struct {
  81                 __le64 pkt_addr; /* Packet buffer address */
  82                 __le64 hdr_addr; /* Header buffer address */
  83                                  /* bit 0 of hdr_addr is DD bit */
  84         } read;
  85         struct {
  86                 /* Qword 0 */
  87                 u8 rxdid; /* descriptor builder profile ID */
  88                 u8 mir_id_umb_cast; /* mirror=[5:0], umb=[7:6] */
  89                 __le16 ptype_flex_flags0; /* ptype=[9:0], ff0=[15:10] */
  90                 __le16 pkt_len; /* [15:14] are reserved */
  91                 __le16 hdr_len_sph_flex_flags1; /* header=[10:0] */
  92                                                 /* sph=[11:11] */
  93                                                 /* ff1/ext=[15:12] */
  94
  95                 /* Qword 1 */
  96                 __le16 status_error0;
  97                 __le16 l2tag1;
  98                 __le16 flex_meta0;
  99                 __le16 flex_meta1;
 100         } wb; /* writeback */
 101 };
 102
 103 union iavf_32b_rx_flex_desc {
 104         struct {
 105                 __le64 pkt_addr; /* Packet buffer address */
 106                 __le64 hdr_addr; /* Header buffer address */
 107                                  /* bit 0 of hdr_addr is DD bit */
 108                 __le64 rsvd1;
 109                 __le64 rsvd2;
 110         } read;
 111         struct {
 112                 /* Qword 0 */
 113                 u8 rxdid; /* descriptor builder profile ID */
 114                 u8 mir_id_umb_cast; /* mirror=[5:0], umb=[7:6] */
 115                 __le16 ptype_flex_flags0; /* ptype=[9:0], ff0=[15:10] */
 116                 __le16 pkt_len; /* [15:14] are reserved */
 117                 __le16 hdr_len_sph_flex_flags1; /* header=[10:0] */
 118                                                 /* sph=[11:11] */
 119                                                 /* ff1/ext=[15:12] */
 120
 121                 /* Qword 1 */
 122                 __le16 status_error0;
 123                 __le16 l2tag1;
 124                 __le16 flex_meta0;
 125                 __le16 flex_meta1;
 126
 127                 /* Qword 2 */
 128                 __le16 status_error1;
 129                 u8 flex_flags2;
 130                 u8 time_stamp_low;
 131                 __le16 l2tag2_1st;
 132                 __le16 l2tag2_2nd;
 133
 134                 /* Qword 3 */
 135                 __le16 flex_meta2;
 136                 __le16 flex_meta3;
 137                 union {
 138                         struct {
 139                                 __le16 flex_meta4;
 140                                 __le16 flex_meta5;
 141                         } flex;
 142                         __le32 ts_high;
 143                 } flex_ts;
 144         } wb; /* writeback */
 145 };
 146
 147 /* HW desc structure, both 16-byte and 32-byte types are supported */
 148 #ifdef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
 149 #define iavf_rx_desc iavf_16byte_rx_desc
 150 #define iavf_rx_flex_desc iavf_16b_rx_flex_desc
 151 #else
 152 #define iavf_rx_desc iavf_32byte_rx_desc
 153 #define iavf_rx_flex_desc iavf_32b_rx_flex_desc
 154 #endif
 155
 156 typedef void (*iavf_rxd_to_pkt_fields_t)(struct iavf_rx_queue *rxq,
 157                                 struct rte_mbuf *mb,
 158                                 volatile union iavf_rx_flex_desc *rxdp);
 159
 160 struct iavf_rxq_ops {
 161         void (*release_mbufs)(struct iavf_rx_queue *rxq);
 162 };
 163
 164 struct iavf_txq_ops {
 165         void (*release_mbufs)(struct iavf_tx_queue *txq);
 166 };
 167
 168 struct iavf_ipsec_crypto_stats {
 169         uint64_t icount;
 170         uint64_t ibytes;
 171         struct {
 172                 uint64_t count;
 173                 uint64_t sad_miss;
 174                 uint64_t not_processed;
 175                 uint64_t icv_check;
 176                 uint64_t ipsec_length;
 177                 uint64_t misc;
 178         } ierrors;
 179 };
 180
 181 struct iavf_rx_queue_stats {
 182         uint64_t reserved;
 183         struct iavf_ipsec_crypto_stats ipsec_crypto;
 184 };
 185
 186 /* Structure associated with each Rx queue. */
 187 struct iavf_rx_queue {
 188         struct rte_mempool *mp;       /* mbuf pool to populate Rx ring */
 189         const struct rte_memzone *mz; /* memzone for Rx ring */
 190         volatile union iavf_rx_desc *rx_ring; /* Rx ring virtual address */
 191         uint64_t rx_ring_phys_addr;   /* Rx ring DMA address */
 192         struct rte_mbuf **sw_ring;     /* address of SW ring */
 193         uint16_t nb_rx_desc;          /* ring length */
 194         uint16_t rx_tail;             /* current value of tail */
 195         volatile uint8_t *qrx_tail;   /* register address of tail */
 196         uint16_t rx_free_thresh;      /* max free RX desc to hold */
 197         uint16_t nb_rx_hold;          /* number of held free RX desc */
 198         struct rte_mbuf *pkt_first_seg; /* first segment of current packet */
 199         struct rte_mbuf *pkt_last_seg;  /* last segment of current packet */
 200         struct rte_mbuf fake_mbuf;      /* dummy mbuf */
 201         uint8_t rxdid;
 202
 203         /* used for VPMD */
 204         uint16_t rxrearm_nb;       /* number of remaining to be re-armed */
 205         uint16_t rxrearm_start;    /* the idx we start the re-arming from */
 206         uint64_t mbuf_initializer; /* value to init mbufs */
 207
 208         /* for rx bulk */
 209         uint16_t rx_nb_avail;      /* number of staged packets ready */
 210         uint16_t rx_next_avail;    /* index of next staged packets */
 211         uint16_t rx_free_trigger;  /* triggers rx buffer allocation */
 212         struct rte_mbuf *rx_stage[IAVF_RX_MAX_BURST * 2]; /* store mbuf */
 213
 214         uint16_t port_id;        /* device port ID */
 215         uint8_t crc_len;        /* 0 if CRC stripped, 4 otherwise */
 216         uint8_t fdir_enabled;   /* 0 if FDIR disabled, 1 when enabled */
 217         uint16_t queue_id;      /* Rx queue index */
 218         uint16_t rx_buf_len;    /* The packet buffer size */
 219         uint16_t rx_hdr_len;    /* The header buffer size */
 220         uint16_t max_pkt_len;   /* Maximum packet length */
 221         struct iavf_vsi *vsi; /**< the VSI this queue belongs to */
 222
 223         bool q_set;             /* if rx queue has been configured */
 224         bool rx_deferred_start; /* don't start this queue in dev start */
 225         const struct iavf_rxq_ops *ops;
 226         uint8_t rx_flags;
 227 #define IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG1     BIT(0)
 228 #define IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG2_2   BIT(1)
 229         uint8_t proto_xtr; /* protocol extraction type */
 230         uint64_t xtr_ol_flag;
 231                 /* flexible descriptor metadata extraction offload flag */
 232         iavf_rxd_to_pkt_fields_t rxd_to_pkt_fields;
 233                                 /* handle flexible descriptor by RXDID */
 234         struct iavf_rx_queue_stats stats;
 235         uint64_t offloads;
 236 };
 237
 238 struct iavf_tx_entry {
 239         struct rte_mbuf *mbuf;
 240         uint16_t next_id;
 241         uint16_t last_id;
 242 };
 243
 244 struct iavf_tx_vec_entry {
 245         struct rte_mbuf *mbuf;
 246 };
 247
 248 /* Structure associated with each TX queue. */
 249 struct iavf_tx_queue {
 250         const struct rte_memzone *mz;  /* memzone for Tx ring */
 251         volatile struct iavf_tx_desc *tx_ring; /* Tx ring virtual address */
 252         uint64_t tx_ring_phys_addr;    /* Tx ring DMA address */
 253         struct iavf_tx_entry *sw_ring;  /* address array of SW ring */
 254         uint16_t nb_tx_desc;           /* ring length */
 255         uint16_t tx_tail;              /* current value of tail */
 256         volatile uint8_t *qtx_tail;    /* register address of tail */
 257         /* number of used desc since RS bit set */
 258         uint16_t nb_used;
 259         uint16_t nb_free;
 260         uint16_t last_desc_cleaned;    /* last desc have been cleaned*/
 261         uint16_t free_thresh;
 262         uint16_t rs_thresh;
 263
 264         uint16_t port_id;
 265         uint16_t queue_id;
 266         uint64_t offloads;
 267         uint16_t next_dd;              /* next to set RS, for VPMD */
 268         uint16_t next_rs;              /* next to check DD,  for VPMD */
 269         uint16_t ipsec_crypto_pkt_md_offset;
 270
 271         bool q_set;                    /* if rx queue has been configured */
 272         bool tx_deferred_start;        /* don't start this queue in dev start */
 273         const struct iavf_txq_ops *ops;
 274 #define IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG1       BIT(0)
 275 #define IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG2       BIT(1)
 276         uint8_t vlan_flag;
 277         uint8_t tc;
 278 };
 279
 280 /* Offload features */
 281 union iavf_tx_offload {
 282         uint64_t data;
 283         struct {
 284                 uint64_t l2_len:7; /* L2 (MAC) Header Length. */
 285                 uint64_t l3_len:9; /* L3 (IP) Header Length. */
 286                 uint64_t l4_len:8; /* L4 Header Length. */
 287                 uint64_t tso_segsz:16; /* TCP TSO segment size */
 288                 /* uint64_t unused : 24; */
 289         };
 290 };
 291
 292 /* Rx Flex Descriptor
 293  * RxDID Profile ID 16-21
 294  * Flex-field 0: RSS hash lower 16-bits
 295  * Flex-field 1: RSS hash upper 16-bits
 296  * Flex-field 2: Flow ID lower 16-bits
 297  * Flex-field 3: Flow ID upper 16-bits
 298  * Flex-field 4: AUX0
 299  * Flex-field 5: AUX1
 300  */
 301 struct iavf_32b_rx_flex_desc_comms {
 302         /* Qword 0 */
 303         u8 rxdid;
 304         u8 mir_id_umb_cast;
 305         __le16 ptype_flexi_flags0;
 306         __le16 pkt_len;
 307         __le16 hdr_len_sph_flex_flags1;
 308
 309         /* Qword 1 */
 310         __le16 status_error0;
 311         __le16 l2tag1;
 312         __le32 rss_hash;
 313
 314         /* Qword 2 */
 315         __le16 status_error1;
 316         u8 flexi_flags2;
 317         u8 ts_low;
 318         __le16 l2tag2_1st;
 319         __le16 l2tag2_2nd;
 320
 321         /* Qword 3 */
 322         __le32 flow_id;
 323         union {
 324                 struct {
 325                         __le16 aux0;
 326                         __le16 aux1;
 327                 } flex;
 328                 __le32 ts_high;
 329         } flex_ts;
 330 };
 331
 332 /* Rx Flex Descriptor
 333  * RxDID Profile ID 22-23 (swap Hash and FlowID)
 334  * Flex-field 0: Flow ID lower 16-bits
 335  * Flex-field 1: Flow ID upper 16-bits
 336  * Flex-field 2: RSS hash lower 16-bits
 337  * Flex-field 3: RSS hash upper 16-bits
 338  * Flex-field 4: AUX0
 339  * Flex-field 5: AUX1
 340  */
 341 struct iavf_32b_rx_flex_desc_comms_ovs {
 342         /* Qword 0 */
 343         u8 rxdid;
 344         u8 mir_id_umb_cast;
 345         __le16 ptype_flexi_flags0;
 346         __le16 pkt_len;
 347         __le16 hdr_len_sph_flex_flags1;
 348
 349         /* Qword 1 */
 350         __le16 status_error0;
 351         __le16 l2tag1;
 352         __le32 flow_id;
 353
 354         /* Qword 2 */
 355         __le16 status_error1;
 356         u8 flexi_flags2;
 357         u8 ts_low;
 358         __le16 l2tag2_1st;
 359         __le16 l2tag2_2nd;
 360
 361         /* Qword 3 */
 362         __le32 rss_hash;
 363         union {
 364                 struct {
 365                         __le16 aux0;
 366                         __le16 aux1;
 367                 } flex;
 368                 __le32 ts_high;
 369         } flex_ts;
 370 };
 371
 372 /* Rx Flex Descriptor
 373  * RxDID Profile ID 24 Inline IPsec
 374  * Flex-field 0: RSS hash lower 16-bits
 375  * Flex-field 1: RSS hash upper 16-bits
 376  * Flex-field 2: Flow ID lower 16-bits
 377  * Flex-field 3: Flow ID upper 16-bits
 378  * Flex-field 4: Inline IPsec SAID lower 16-bits
 379  * Flex-field 5: Inline IPsec SAID upper 16-bits
 380  */
 381 struct iavf_32b_rx_flex_desc_comms_ipsec {
 382         /* Qword 0 */
 383         u8 rxdid;
 384         u8 mir_id_umb_cast;
 385         __le16 ptype_flexi_flags0;
 386         __le16 pkt_len;
 387         __le16 hdr_len_sph_flex_flags1;
 388
 389         /* Qword 1 */
 390         __le16 status_error0;
 391         __le16 l2tag1;
 392         __le32 rss_hash;
 393
 394         /* Qword 2 */
 395         __le16 status_error1;
 396         u8 flexi_flags2;
 397         u8 ts_low;
 398         __le16 l2tag2_1st;
 399         __le16 l2tag2_2nd;
 400
 401         /* Qword 3 */
 402         __le32 flow_id;
 403         __le32 ipsec_said;
 404 };
 405
 406 /* Receive Flex Descriptor profile IDs: There are a total
 407  * of 64 profiles where profile IDs 0/1 are for legacy; and
 408  * profiles 2-63 are flex profiles that can be programmed
 409  * with a specific metadata (profile 7 reserved for HW)
 410  */
 411 enum iavf_rxdid {
 412         IAVF_RXDID_LEGACY_0             = 0,
 413         IAVF_RXDID_LEGACY_1             = 1,
 414         IAVF_RXDID_FLEX_NIC             = 2,
 415         IAVF_RXDID_FLEX_NIC_2           = 6,
 416         IAVF_RXDID_HW                   = 7,
 417         IAVF_RXDID_COMMS_GENERIC        = 16,
 418         IAVF_RXDID_COMMS_AUX_VLAN       = 17,
 419         IAVF_RXDID_COMMS_AUX_IPV4       = 18,
 420         IAVF_RXDID_COMMS_AUX_IPV6       = 19,
 421         IAVF_RXDID_COMMS_AUX_IPV6_FLOW  = 20,
 422         IAVF_RXDID_COMMS_AUX_TCP        = 21,
 423         IAVF_RXDID_COMMS_OVS_1          = 22,
 424         IAVF_RXDID_COMMS_OVS_2          = 23,
 425         IAVF_RXDID_COMMS_IPSEC_CRYPTO   = 24,
 426         IAVF_RXDID_COMMS_AUX_IP_OFFSET  = 25,
 427         IAVF_RXDID_LAST                 = 63,
 428 };
 429
 430 enum iavf_rx_flex_desc_status_error_0_bits {
 431         /* Note: These are predefined bit offsets */
 432         IAVF_RX_FLEX_DESC_STATUS0_DD_S = 0,
 433         IAVF_RX_FLEX_DESC_STATUS0_EOF_S,
 434         IAVF_RX_FLEX_DESC_STATUS0_HBO_S,
 435         IAVF_RX_FLEX_DESC_STATUS0_L3L4P_S,
 436         IAVF_RX_FLEX_DESC_STATUS0_XSUM_IPE_S,
 437         IAVF_RX_FLEX_DESC_STATUS0_XSUM_L4E_S,
 438         IAVF_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S,
 439         IAVF_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S,
 440         IAVF_RX_FLEX_DESC_STATUS0_LPBK_S,
 441         IAVF_RX_FLEX_DESC_STATUS0_IPV6EXADD_S,
 442         IAVF_RX_FLEX_DESC_STATUS0_RXE_S,
 443         IAVF_RX_FLEX_DESC_STATUS0_CRCP_S,
 444         IAVF_RX_FLEX_DESC_STATUS0_RSS_VALID_S,
 445         IAVF_RX_FLEX_DESC_STATUS0_L2TAG1P_S,
 446         IAVF_RX_FLEX_DESC_STATUS0_XTRMD0_VALID_S,
 447         IAVF_RX_FLEX_DESC_STATUS0_XTRMD1_VALID_S,
 448         IAVF_RX_FLEX_DESC_STATUS0_LAST /* this entry must be last!!! */
 449 };
 450
 451 enum iavf_rx_flex_desc_status_error_1_bits {
 452         /* Note: These are predefined bit offsets */
 453         /* Bits 3:0 are reserved for inline ipsec status */
 454         IAVF_RX_FLEX_DESC_STATUS1_IPSEC_CRYPTO_STATUS_0 = 0,
 455         IAVF_RX_FLEX_DESC_STATUS1_IPSEC_CRYPTO_STATUS_1,
 456         IAVF_RX_FLEX_DESC_STATUS1_IPSEC_CRYPTO_STATUS_2,
 457         IAVF_RX_FLEX_DESC_STATUS1_IPSEC_CRYPTO_STATUS_3,
 458         IAVF_RX_FLEX_DESC_STATUS1_NAT_S,
 459         IAVF_RX_FLEX_DESC_STATUS1_IPSEC_CRYPTO_PROCESSED,
 460         /* [10:6] reserved */
 461         IAVF_RX_FLEX_DESC_STATUS1_L2TAG2P_S = 11,
 462         IAVF_RX_FLEX_DESC_STATUS1_XTRMD2_VALID_S = 12,
 463         IAVF_RX_FLEX_DESC_STATUS1_XTRMD3_VALID_S = 13,
 464         IAVF_RX_FLEX_DESC_STATUS1_XTRMD4_VALID_S = 14,
 465         IAVF_RX_FLEX_DESC_STATUS1_XTRMD5_VALID_S = 15,
 466         IAVF_RX_FLEX_DESC_STATUS1_LAST /* this entry must be last!!! */
 467 };
 468
 469 #define IAVF_RX_FLEX_DESC_IPSEC_CRYPTO_STATUS_MASK  (           \
 470         BIT(IAVF_RX_FLEX_DESC_STATUS1_IPSEC_CRYPTO_STATUS_0) |  \
 471         BIT(IAVF_RX_FLEX_DESC_STATUS1_IPSEC_CRYPTO_STATUS_1) |  \
 472         BIT(IAVF_RX_FLEX_DESC_STATUS1_IPSEC_CRYPTO_STATUS_2) |  \
 473         BIT(IAVF_RX_FLEX_DESC_STATUS1_IPSEC_CRYPTO_STATUS_3))
 474
 475 enum iavf_rx_flex_desc_ipsec_crypto_status {
 476         IAVF_IPSEC_CRYPTO_STATUS_SUCCESS = 0,
 477         IAVF_IPSEC_CRYPTO_STATUS_SAD_MISS,
 478         IAVF_IPSEC_CRYPTO_STATUS_NOT_PROCESSED,
 479         IAVF_IPSEC_CRYPTO_STATUS_ICV_CHECK_FAIL,
 480         IAVF_IPSEC_CRYPTO_STATUS_LENGTH_ERR,
 481         /* Reserved */
 482         IAVF_IPSEC_CRYPTO_STATUS_MISC_ERR = 0xF
 483 };
 484
 485
 486
 487 #define IAVF_TXD_DATA_QW1_DTYPE_SHIFT   (0)
 488 #define IAVF_TXD_DATA_QW1_DTYPE_MASK    (0xFUL << IAVF_TXD_QW1_DTYPE_SHIFT)
 489
 490 #define IAVF_TXD_DATA_QW1_CMD_SHIFT     (4)
 491 #define IAVF_TXD_DATA_QW1_CMD_MASK      (0x3FFUL << IAVF_TXD_DATA_QW1_CMD_SHIFT)
 492
 493 #define IAVF_TXD_DATA_QW1_OFFSET_SHIFT  (16)
 494 #define IAVF_TXD_DATA_QW1_OFFSET_MASK   (0x3FFFFULL << \
 495                                         IAVF_TXD_DATA_QW1_OFFSET_SHIFT)
 496
 497 #define IAVF_TXD_DATA_QW1_OFFSET_MACLEN_SHIFT   (IAVF_TXD_DATA_QW1_OFFSET_SHIFT)
 498 #define IAVF_TXD_DATA_QW1_OFFSET_MACLEN_MASK    \
 499         (0x7FUL << IAVF_TXD_DATA_QW1_OFFSET_MACLEN_SHIFT)
 500
 501 #define IAVF_TXD_DATA_QW1_OFFSET_IPLEN_SHIFT    \
 502         (IAVF_TXD_DATA_QW1_OFFSET_SHIFT + IAVF_TX_DESC_LENGTH_IPLEN_SHIFT)
 503 #define IAVF_TXD_DATA_QW1_OFFSET_IPLEN_MASK     \
 504         (0x7FUL << IAVF_TXD_DATA_QW1_OFFSET_IPLEN_SHIFT)
 505
 506 #define IAVF_TXD_DATA_QW1_OFFSET_L4LEN_SHIFT    \
 507         (IAVF_TXD_DATA_QW1_OFFSET_SHIFT + IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
 508 #define IAVF_TXD_DATA_QW1_OFFSET_L4LEN_MASK     \
 509         (0xFUL << IAVF_TXD_DATA_QW1_OFFSET_L4LEN_SHIFT)
 510
 511 #define IAVF_TXD_DATA_QW1_MACLEN_MASK   \
 512         (0x7FUL << IAVF_TX_DESC_LENGTH_MACLEN_SHIFT)
 513 #define IAVF_TXD_DATA_QW1_IPLEN_MASK    \
 514         (0x7FUL << IAVF_TX_DESC_LENGTH_IPLEN_SHIFT)
 515 #define IAVF_TXD_DATA_QW1_L4LEN_MASK    \
 516         (0xFUL << IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
 517 #define IAVF_TXD_DATA_QW1_FCLEN_MASK    \
 518         (0xFUL << IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
 519
 520 #define IAVF_TXD_DATA_QW1_TX_BUF_SZ_SHIFT       (34)
 521 #define IAVF_TXD_DATA_QW1_TX_BUF_SZ_MASK        \
 522         (0x3FFFULL << IAVF_TXD_DATA_QW1_TX_BUF_SZ_SHIFT)
 523
 524 #define IAVF_TXD_DATA_QW1_L2TAG1_SHIFT          (48)
 525 #define IAVF_TXD_DATA_QW1_L2TAG1_MASK           \
 526         (0xFFFFULL << IAVF_TXD_DATA_QW1_L2TAG1_SHIFT)
 527
 528 #define IAVF_TXD_CTX_QW1_IPSEC_PARAMS_CIPHERBLK_SHIFT   (11)
 529 #define IAVF_TXD_CTX_QW1_IPSEC_PARAMS_CIPHERBLK_MASK    \
 530         (0x7UL << IAVF_TXD_CTX_QW1_IPSEC_PARAMS_CIPHERBLK_SHIFT)
 531
 532 #define IAVF_TXD_CTX_QW1_IPSEC_PARAMS_ICVLEN_SHIFT      (14)
 533 #define IAVF_TXD_CTX_QW1_IPSEC_PARAMS_ICVLEN_MASK       \
 534         (0xFUL << IAVF_TXD_CTX_QW1_IPSEC_PARAMS_ICVLEN_SHIFT)
 535
 536 #define IAVF_TXD_CTX_QW1_SEG_PARAMS_TLEN_SHIFT          (30)
 537 #define IAVF_TXD_CTX_QW1_SEG_PARAMS_TLEN_MASK           \
 538         (0x3FFFFUL << IAVF_TXD_CTX_QW1_SEG_PARAMS_TLEN_SHIFT)
 539
 540 #define IAVF_TXD_CTX_QW1_TSYNC_PARAMS_TLEN_SHIFT        (30)
 541 #define IAVF_TXD_CTX_QW1_TSYNC_PARAMS_TLEN_MASK         \
 542         (0x3FUL << IAVF_TXD_CTX_QW1_SEG_PARAMS_TLEN_SHIFT)
 543
 544 #define IAVF_TXD_CTX_QW1_SEG_PARAMS_MSS_SHIFT           (50)
 545 #define IAVF_TXD_CTX_QW1_SEG_PARAMS_MSS_MASK            \
 546         (0x3FFFUL << IAVF_TXD_CTX_QW1_SEG_PARAMS_MSS_SHIFT)
 547
 548 #define IAVF_TXD_CTX_QW0_TUN_PARAMS_EIPT_SHIFT          (0)
 549 #define IAVF_TXD_CTX_QW0_TUN_PARAMS_EIPT_MASK           (0x3UL)
 550
 551 enum iavf_tx_ctx_desc_tunnel_external_ip_type {
 552         IAVF_TX_CTX_DESC_EIPT_NONE,
 553         IAVF_TX_CTX_DESC_EIPT_IPV6,
 554         IAVF_TX_CTX_DESC_EIPT_IPV4_NO_CHECKSUM_OFFLOAD,
 555         IAVF_TX_CTX_DESC_EIPT_IPV4_CHECKSUM_OFFLOAD
 556 };
 557
 558 #define IAVF_TXD_CTX_QW0_TUN_PARAMS_EIPLEN_SHIFT        (2)
 559 #define IAVF_TXD_CTX_QW0_TUN_PARAMS_EIPLEN_MASK         (0x7FUL)
 560
 561 #define IAVF_TXD_CTX_QW0_TUN_PARAMS_L4TUNT_SHIFT        (9)
 562 #define IAVF_TXD_CTX_QW0_TUN_PARAMS_L4TUNT_MASK         (0x3UL)
 563
 564 enum iavf_tx_ctx_desc_tunnel_l4_tunnel_type {
 565         IAVF_TX_CTX_DESC_L4_TUN_TYP_NO_UDP_GRE,
 566         IAVF_TX_CTX_DESC_L4_TUN_TYP_UDP,
 567         IAVF_TX_CTX_DESC_L4_TUN_TYP_GRE
 568 };
 569
 570 #define IAVF_TXD_CTX_QW0_TUN_PARAMS_EIP_NOINC_SHIFT     (11)
 571 #define IAVF_TXD_CTX_QW0_TUN_PARAMS_EIP_NOINC_MASK      (0x1UL)
 572
 573 #define IAVF_TXD_CTX_QW0_TUN_PARAMS_L4TUNLEN_SHIFT      (12)
 574 #define IAVF_TXD_CTX_QW0_TUN_PARAMS_L4TUNLEN_MASK       (0x7FUL)
 575
 576 #define IAVF_TXD_CTX_QW0_TUN_PARAMS_DECTTL_SHIFT        (19)
 577 #define IAVF_TXD_CTX_QW0_TUN_PARAMS_DECTTL_MASK         (0xFUL)
 578
 579 #define IAVF_TXD_CTX_QW0_TUN_PARAMS_L4T_CS_SHIFT        (23)
 580 #define IAVF_TXD_CTX_QW0_TUN_PARAMS_L4T_CS_MASK         (0x1UL)
 581
 582 #define IAVF_TXD_CTX_QW0_L2TAG2_PARAM                   (32)
 583 #define IAVF_TXD_CTX_QW0_L2TAG2_MASK                    (0xFFFFUL)
 584
 585
 586 #define IAVF_RX_FLEX_DESC_IPSEC_CRYPTO_SAID_MASK        (0xFFFFF)
 587
 588 /* for iavf_32b_rx_flex_desc.ptype_flex_flags0 member */
 589 #define IAVF_RX_FLEX_DESC_PTYPE_M       (0x3FF) /* 10-bits */
 590
 591
 592 /* for iavf_32b_rx_flex_desc.ptype_flex_flags0 member */
 593 #define IAVF_RX_FLEX_DESC_PTYPE_M       (0x3FF) /* 10-bits */
 594
 595 /* for iavf_32b_rx_flex_desc.pkt_len member */
 596 #define IAVF_RX_FLX_DESC_PKT_LEN_M      (0x3FFF) /* 14-bits */
 597
 598 int iavf_dev_rx_queue_setup(struct rte_eth_dev *dev,
 599                            uint16_t queue_idx,
 600                            uint16_t nb_desc,
 601                            unsigned int socket_id,
 602                            const struct rte_eth_rxconf *rx_conf,
 603                            struct rte_mempool *mp);
 604
 605 int iavf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
 606 int iavf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
 607 void iavf_dev_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid);
 608
 609 int iavf_dev_tx_queue_setup(struct rte_eth_dev *dev,
 610                            uint16_t queue_idx,
 611                            uint16_t nb_desc,
 612                            unsigned int socket_id,
 613                            const struct rte_eth_txconf *tx_conf);
 614 int iavf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
 615 int iavf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);
 616 int iavf_dev_tx_done_cleanup(void *txq, uint32_t free_cnt);
 617 void iavf_dev_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid);
 618 void iavf_stop_queues(struct rte_eth_dev *dev);
 619 uint16_t iavf_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
 620                        uint16_t nb_pkts);
 621 uint16_t iavf_recv_pkts_flex_rxd(void *rx_queue,
 622                                  struct rte_mbuf **rx_pkts,
 623                                  uint16_t nb_pkts);
 624 uint16_t iavf_recv_scattered_pkts(void *rx_queue,
 625                                  struct rte_mbuf **rx_pkts,
 626                                  uint16_t nb_pkts);
 627 uint16_t iavf_recv_scattered_pkts_flex_rxd(void *rx_queue,
 628                                            struct rte_mbuf **rx_pkts,
 629                                            uint16_t nb_pkts);
 630 uint16_t iavf_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 631                        uint16_t nb_pkts);
 632 uint16_t iavf_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 633                        uint16_t nb_pkts);
 634 void iavf_set_rx_function(struct rte_eth_dev *dev);
 635 void iavf_set_tx_function(struct rte_eth_dev *dev);
 636 void iavf_dev_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
 637                           struct rte_eth_rxq_info *qinfo);
 638 void iavf_dev_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
 639                           struct rte_eth_txq_info *qinfo);
 640 uint32_t iavf_dev_rxq_count(void *rx_queue);
 641 int iavf_dev_rx_desc_status(void *rx_queue, uint16_t offset);
 642 int iavf_dev_tx_desc_status(void *tx_queue, uint16_t offset);
 643
 644 uint16_t iavf_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
 645                            uint16_t nb_pkts);
 646 uint16_t iavf_recv_pkts_vec_flex_rxd(void *rx_queue, struct rte_mbuf **rx_pkts,
 647                                      uint16_t nb_pkts);
 648 uint16_t iavf_recv_scattered_pkts_vec(void *rx_queue,
 649                                      struct rte_mbuf **rx_pkts,
 650                                      uint16_t nb_pkts);
 651 uint16_t iavf_recv_scattered_pkts_vec_flex_rxd(void *rx_queue,
 652                                                struct rte_mbuf **rx_pkts,
 653                                                uint16_t nb_pkts);
 654 uint16_t iavf_xmit_fixed_burst_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
 655                                   uint16_t nb_pkts);
 656 uint16_t iavf_recv_pkts_vec_avx2(void *rx_queue, struct rte_mbuf **rx_pkts,
 657                                  uint16_t nb_pkts);
 658 uint16_t iavf_recv_pkts_vec_avx2_flex_rxd(void *rx_queue,
 659                                           struct rte_mbuf **rx_pkts,
 660                                           uint16_t nb_pkts);
 661 uint16_t iavf_recv_scattered_pkts_vec_avx2(void *rx_queue,
 662                                            struct rte_mbuf **rx_pkts,
 663                                            uint16_t nb_pkts);
 664 uint16_t iavf_recv_scattered_pkts_vec_avx2_flex_rxd(void *rx_queue,
 665                                                     struct rte_mbuf **rx_pkts,
 666                                                     uint16_t nb_pkts);
 667 uint16_t iavf_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
 668                             uint16_t nb_pkts);
 669 uint16_t iavf_xmit_pkts_vec_avx2(void *tx_queue, struct rte_mbuf **tx_pkts,
 670                                  uint16_t nb_pkts);
 671 int iavf_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc);
 672 int iavf_rx_vec_dev_check(struct rte_eth_dev *dev);
 673 int iavf_tx_vec_dev_check(struct rte_eth_dev *dev);
 674 int iavf_rxq_vec_setup(struct iavf_rx_queue *rxq);
 675 int iavf_txq_vec_setup(struct iavf_tx_queue *txq);
 676 uint16_t iavf_recv_pkts_vec_avx512(void *rx_queue, struct rte_mbuf **rx_pkts,
 677                                    uint16_t nb_pkts);
 678 uint16_t iavf_recv_pkts_vec_avx512_offload(void *rx_queue,
 679                                            struct rte_mbuf **rx_pkts,
 680                                            uint16_t nb_pkts);
 681 uint16_t iavf_recv_pkts_vec_avx512_flex_rxd(void *rx_queue,
 682                                             struct rte_mbuf **rx_pkts,
 683                                             uint16_t nb_pkts);
 684 uint16_t iavf_recv_pkts_vec_avx512_flex_rxd_offload(void *rx_queue,
 685                                                     struct rte_mbuf **rx_pkts,
 686                                                     uint16_t nb_pkts);
 687 uint16_t iavf_recv_scattered_pkts_vec_avx512(void *rx_queue,
 688                                              struct rte_mbuf **rx_pkts,
 689                                              uint16_t nb_pkts);
 690 uint16_t iavf_recv_scattered_pkts_vec_avx512_offload(void *rx_queue,
 691                                                      struct rte_mbuf **rx_pkts,
 692                                                      uint16_t nb_pkts);
 693 uint16_t iavf_recv_scattered_pkts_vec_avx512_flex_rxd(void *rx_queue,
 694                                                       struct rte_mbuf **rx_pkts,
 695                                                       uint16_t nb_pkts);
 696 uint16_t iavf_recv_scattered_pkts_vec_avx512_flex_rxd_offload(void *rx_queue,
 697                                                               struct rte_mbuf **rx_pkts,
 698                                                               uint16_t nb_pkts);
 699 uint16_t iavf_xmit_pkts_vec_avx512(void *tx_queue, struct rte_mbuf **tx_pkts,
 700                                    uint16_t nb_pkts);
 701 uint16_t iavf_xmit_pkts_vec_avx512_offload(void *tx_queue,
 702                                            struct rte_mbuf **tx_pkts,
 703                                            uint16_t nb_pkts);
 704 int iavf_txq_vec_setup_avx512(struct iavf_tx_queue *txq);
 705
 706 uint8_t iavf_proto_xtr_type_to_rxdid(uint8_t xtr_type);
 707
 708 void iavf_set_default_ptype_table(struct rte_eth_dev *dev);
 709
 710 static inline
 711 void iavf_dump_rx_descriptor(struct iavf_rx_queue *rxq,
 712                             const volatile void *desc,
 713                             uint16_t rx_id)
 714 {
 715 #ifdef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
 716         const volatile union iavf_16byte_rx_desc *rx_desc = desc;
 717
 718         printf("Queue %d Rx_desc %d: QW0: 0x%016"PRIx64" QW1: 0x%016"PRIx64"\n",
 719                rxq->queue_id, rx_id, rx_desc->read.pkt_addr,
 720                rx_desc->read.hdr_addr);
 721 #else
 722         const volatile union iavf_32byte_rx_desc *rx_desc = desc;
 723
 724         printf("Queue %d Rx_desc %d: QW0: 0x%016"PRIx64" QW1: 0x%016"PRIx64
 725                " QW2: 0x%016"PRIx64" QW3: 0x%016"PRIx64"\n", rxq->queue_id,
 726                rx_id, rx_desc->read.pkt_addr, rx_desc->read.hdr_addr,
 727                rx_desc->read.rsvd1, rx_desc->read.rsvd2);
 728 #endif
 729 }
 730
 731 /* All the descriptors are 16 bytes, so just use one of them
 732  * to print the qwords
 733  */
 734 static inline
 735 void iavf_dump_tx_descriptor(const struct iavf_tx_queue *txq,
 736                             const volatile void *desc, uint16_t tx_id)
 737 {
 738         const char *name;
 739         const volatile struct iavf_tx_desc *tx_desc = desc;
 740         enum iavf_tx_desc_dtype_value type;
 741
 742
 743         type = (enum iavf_tx_desc_dtype_value)
 744                 rte_le_to_cpu_64(tx_desc->cmd_type_offset_bsz &
 745                         rte_cpu_to_le_64(IAVF_TXD_DATA_QW1_DTYPE_MASK));
 746         switch (type) {
 747         case IAVF_TX_DESC_DTYPE_DATA:
 748                 name = "Tx_data_desc";
 749                 break;
 750         case IAVF_TX_DESC_DTYPE_CONTEXT:
 751                 name = "Tx_context_desc";
 752                 break;
 753         case IAVF_TX_DESC_DTYPE_IPSEC:
 754                 name = "Tx_IPsec_desc";
 755                 break;
 756         default:
 757                 name = "unknown_desc";
 758                 break;
 759         }
 760
 761         printf("Queue %d %s %d: QW0: 0x%016"PRIx64" QW1: 0x%016"PRIx64"\n",
 762                 txq->queue_id, name, tx_id, tx_desc->buffer_addr,
 763                 tx_desc->cmd_type_offset_bsz);
 764 }
 765
 766 #define FDIR_PROC_ENABLE_PER_QUEUE(ad, on) do { \
 767         int i; \
 768         for (i = 0; i < (ad)->dev_data->nb_rx_queues; i++) { \
 769                 struct iavf_rx_queue *rxq = (ad)->dev_data->rx_queues[i]; \
 770                 if (!rxq) \
 771                         continue; \
 772                 rxq->fdir_enabled = on; \
 773         } \
 774         PMD_DRV_LOG(DEBUG, "FDIR processing on RX set to %d", on); \
 775 } while (0)
 776
 777 /* Enable/disable flow director Rx processing in data path. */
 778 static inline
 779 void iavf_fdir_rx_proc_enable(struct iavf_adapter *ad, bool on)
 780 {
 781         if (on) {
 782                 /* enable flow director processing */
 783                 FDIR_PROC_ENABLE_PER_QUEUE(ad, on);
 784                 ad->fdir_ref_cnt++;
 785         } else {
 786                 if (ad->fdir_ref_cnt >= 1) {
 787                         ad->fdir_ref_cnt--;
 788
 789                         if (ad->fdir_ref_cnt == 0)
 790                                 FDIR_PROC_ENABLE_PER_QUEUE(ad, on);
 791                 }
 792         }
 793 }
 794
 795 #ifdef RTE_LIBRTE_IAVF_DEBUG_DUMP_DESC
 796 #define IAVF_DUMP_RX_DESC(rxq, desc, rx_id) \
 797         iavf_dump_rx_descriptor(rxq, desc, rx_id)
 798 #define IAVF_DUMP_TX_DESC(txq, desc, tx_id) \
 799         iavf_dump_tx_descriptor(txq, desc, tx_id)
 800 #else
 801 #define IAVF_DUMP_RX_DESC(rxq, desc, rx_id) do { } while (0)
 802 #define IAVF_DUMP_TX_DESC(txq, desc, tx_id) do { } while (0)
 803 #endif
 804
 805 #endif /* _IAVF_RXTX_H_ */