drivers/net/iavf/iavf_rxtx.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2017 Intel Corporation
   3  */
   4
   5 #ifndef _IAVF_RXTX_H_
   6 #define _IAVF_RXTX_H_
   7
   8 /* In QLEN must be whole number of 32 descriptors. */
   9 #define IAVF_ALIGN_RING_DESC      32
  10 #define IAVF_MIN_RING_DESC        64
  11 #define IAVF_MAX_RING_DESC        4096
  12 #define IAVF_DMA_MEM_ALIGN        4096
  13 /* Base address of the HW descriptor ring should be 128B aligned. */
  14 #define IAVF_RING_BASE_ALIGN      128
  15
  16 /* used for Rx Bulk Allocate */
  17 #define IAVF_RX_MAX_BURST         32
  18
  19 /* used for Vector PMD */
  20 #define IAVF_VPMD_RX_MAX_BURST    32
  21 #define IAVF_VPMD_TX_MAX_BURST    32
  22 #define IAVF_RXQ_REARM_THRESH     32
  23 #define IAVF_VPMD_DESCS_PER_LOOP  4
  24 #define IAVF_VPMD_TX_MAX_FREE_BUF 64
  25
  26 #define IAVF_TX_NO_VECTOR_FLAGS (                                \
  27                 RTE_ETH_TX_OFFLOAD_MULTI_SEGS |          \
  28                 RTE_ETH_TX_OFFLOAD_TCP_TSO |             \
  29                 RTE_ETH_TX_OFFLOAD_SECURITY)
  30
  31 #define IAVF_TX_VECTOR_OFFLOAD (                                 \
  32                 RTE_ETH_TX_OFFLOAD_VLAN_INSERT |                 \
  33                 RTE_ETH_TX_OFFLOAD_QINQ_INSERT |                 \
  34                 RTE_ETH_TX_OFFLOAD_IPV4_CKSUM |          \
  35                 RTE_ETH_TX_OFFLOAD_SCTP_CKSUM |          \
  36                 RTE_ETH_TX_OFFLOAD_UDP_CKSUM |           \
  37                 RTE_ETH_TX_OFFLOAD_TCP_CKSUM)
  38
  39 #define IAVF_RX_VECTOR_OFFLOAD (                                 \
  40                 RTE_ETH_RX_OFFLOAD_CHECKSUM |            \
  41                 RTE_ETH_RX_OFFLOAD_SCTP_CKSUM |          \
  42                 RTE_ETH_RX_OFFLOAD_VLAN |                \
  43                 RTE_ETH_RX_OFFLOAD_RSS_HASH)
  44
  45 #define IAVF_VECTOR_PATH 0
  46 #define IAVF_VECTOR_OFFLOAD_PATH 1
  47
  48 #define DEFAULT_TX_RS_THRESH     32
  49 #define DEFAULT_TX_FREE_THRESH   32
  50
  51 #define IAVF_MIN_TSO_MSS          256
  52 #define IAVF_MAX_TSO_MSS          9668
  53 #define IAVF_TSO_MAX_SEG          UINT8_MAX
  54 #define IAVF_TX_MAX_MTU_SEG       8
  55
  56 #define IAVF_TX_CKSUM_OFFLOAD_MASK (             \
  57                 RTE_MBUF_F_TX_IP_CKSUM |                 \
  58                 RTE_MBUF_F_TX_L4_MASK |          \
  59                 RTE_MBUF_F_TX_TCP_SEG)
  60
  61 #define IAVF_TX_OFFLOAD_MASK (  \
  62                 RTE_MBUF_F_TX_OUTER_IPV6 |               \
  63                 RTE_MBUF_F_TX_OUTER_IPV4 |               \
  64                 RTE_MBUF_F_TX_IPV6 |                     \
  65                 RTE_MBUF_F_TX_IPV4 |                     \
  66                 RTE_MBUF_F_TX_VLAN |             \
  67                 RTE_MBUF_F_TX_IP_CKSUM |                 \
  68                 RTE_MBUF_F_TX_L4_MASK |          \
  69                 RTE_MBUF_F_TX_TCP_SEG |          \
  70                 RTE_ETH_TX_OFFLOAD_SECURITY)
  71
  72 #define IAVF_TX_OFFLOAD_NOTSUP_MASK \
  73                 (RTE_MBUF_F_TX_OFFLOAD_MASK ^ IAVF_TX_OFFLOAD_MASK)
  74
  75 extern uint64_t iavf_timestamp_dynflag;
  76 extern int iavf_timestamp_dynfield_offset;
  77
  78 /**
  79  * Rx Flex Descriptors
  80  * These descriptors are used instead of the legacy version descriptors
  81  */
  82 union iavf_16b_rx_flex_desc {
  83         struct {
  84                 __le64 pkt_addr; /* Packet buffer address */
  85                 __le64 hdr_addr; /* Header buffer address */
  86                                  /* bit 0 of hdr_addr is DD bit */
  87         } read;
  88         struct {
  89                 /* Qword 0 */
  90                 u8 rxdid; /* descriptor builder profile ID */
  91                 u8 mir_id_umb_cast; /* mirror=[5:0], umb=[7:6] */
  92                 __le16 ptype_flex_flags0; /* ptype=[9:0], ff0=[15:10] */
  93                 __le16 pkt_len; /* [15:14] are reserved */
  94                 __le16 hdr_len_sph_flex_flags1; /* header=[10:0] */
  95                                                 /* sph=[11:11] */
  96                                                 /* ff1/ext=[15:12] */
  97
  98                 /* Qword 1 */
  99                 __le16 status_error0;
 100                 __le16 l2tag1;
 101                 __le16 flex_meta0;
 102                 __le16 flex_meta1;
 103         } wb; /* writeback */
 104 };
 105
 106 union iavf_32b_rx_flex_desc {
 107         struct {
 108                 __le64 pkt_addr; /* Packet buffer address */
 109                 __le64 hdr_addr; /* Header buffer address */
 110                                  /* bit 0 of hdr_addr is DD bit */
 111                 __le64 rsvd1;
 112                 __le64 rsvd2;
 113         } read;
 114         struct {
 115                 /* Qword 0 */
 116                 u8 rxdid; /* descriptor builder profile ID */
 117                 u8 mir_id_umb_cast; /* mirror=[5:0], umb=[7:6] */
 118                 __le16 ptype_flex_flags0; /* ptype=[9:0], ff0=[15:10] */
 119                 __le16 pkt_len; /* [15:14] are reserved */
 120                 __le16 hdr_len_sph_flex_flags1; /* header=[10:0] */
 121                                                 /* sph=[11:11] */
 122                                                 /* ff1/ext=[15:12] */
 123
 124                 /* Qword 1 */
 125                 __le16 status_error0;
 126                 __le16 l2tag1;
 127                 __le16 flex_meta0;
 128                 __le16 flex_meta1;
 129
 130                 /* Qword 2 */
 131                 __le16 status_error1;
 132                 u8 flex_flags2;
 133                 u8 time_stamp_low;
 134                 __le16 l2tag2_1st;
 135                 __le16 l2tag2_2nd;
 136
 137                 /* Qword 3 */
 138                 __le16 flex_meta2;
 139                 __le16 flex_meta3;
 140                 union {
 141                         struct {
 142                                 __le16 flex_meta4;
 143                                 __le16 flex_meta5;
 144                         } flex;
 145                         __le32 ts_high;
 146                 } flex_ts;
 147         } wb; /* writeback */
 148 };
 149
 150 /* HW desc structure, both 16-byte and 32-byte types are supported */
 151 #ifdef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
 152 #define iavf_rx_desc iavf_16byte_rx_desc
 153 #define iavf_rx_flex_desc iavf_16b_rx_flex_desc
 154 #else
 155 #define iavf_rx_desc iavf_32byte_rx_desc
 156 #define iavf_rx_flex_desc iavf_32b_rx_flex_desc
 157 #endif
 158
 159 typedef void (*iavf_rxd_to_pkt_fields_t)(struct iavf_rx_queue *rxq,
 160                                 struct rte_mbuf *mb,
 161                                 volatile union iavf_rx_flex_desc *rxdp);
 162
 163 struct iavf_rxq_ops {
 164         void (*release_mbufs)(struct iavf_rx_queue *rxq);
 165 };
 166
 167 struct iavf_txq_ops {
 168         void (*release_mbufs)(struct iavf_tx_queue *txq);
 169 };
 170
 171
 172 struct iavf_rx_queue_stats {
 173         uint64_t reserved;
 174         struct iavf_ipsec_crypto_stats ipsec_crypto;
 175 };
 176
 177 /* Structure associated with each Rx queue. */
 178 struct iavf_rx_queue {
 179         struct rte_mempool *mp;       /* mbuf pool to populate Rx ring */
 180         const struct rte_memzone *mz; /* memzone for Rx ring */
 181         volatile union iavf_rx_desc *rx_ring; /* Rx ring virtual address */
 182         uint64_t rx_ring_phys_addr;   /* Rx ring DMA address */
 183         struct rte_mbuf **sw_ring;     /* address of SW ring */
 184         uint16_t nb_rx_desc;          /* ring length */
 185         uint16_t rx_tail;             /* current value of tail */
 186         volatile uint8_t *qrx_tail;   /* register address of tail */
 187         uint16_t rx_free_thresh;      /* max free RX desc to hold */
 188         uint16_t nb_rx_hold;          /* number of held free RX desc */
 189         struct rte_mbuf *pkt_first_seg; /* first segment of current packet */
 190         struct rte_mbuf *pkt_last_seg;  /* last segment of current packet */
 191         struct rte_mbuf fake_mbuf;      /* dummy mbuf */
 192         uint8_t rxdid;
 193         uint8_t rel_mbufs_type;
 194
 195         /* used for VPMD */
 196         uint16_t rxrearm_nb;       /* number of remaining to be re-armed */
 197         uint16_t rxrearm_start;    /* the idx we start the re-arming from */
 198         uint64_t mbuf_initializer; /* value to init mbufs */
 199
 200         /* for rx bulk */
 201         uint16_t rx_nb_avail;      /* number of staged packets ready */
 202         uint16_t rx_next_avail;    /* index of next staged packets */
 203         uint16_t rx_free_trigger;  /* triggers rx buffer allocation */
 204         struct rte_mbuf *rx_stage[IAVF_RX_MAX_BURST * 2]; /* store mbuf */
 205
 206         uint16_t port_id;        /* device port ID */
 207         uint8_t crc_len;        /* 0 if CRC stripped, 4 otherwise */
 208         uint8_t fdir_enabled;   /* 0 if FDIR disabled, 1 when enabled */
 209         uint16_t queue_id;      /* Rx queue index */
 210         uint16_t rx_buf_len;    /* The packet buffer size */
 211         uint16_t rx_hdr_len;    /* The header buffer size */
 212         uint16_t max_pkt_len;   /* Maximum packet length */
 213         struct iavf_vsi *vsi; /**< the VSI this queue belongs to */
 214
 215         bool q_set;             /* if rx queue has been configured */
 216         bool rx_deferred_start; /* don't start this queue in dev start */
 217         const struct iavf_rxq_ops *ops;
 218         uint8_t rx_flags;
 219 #define IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG1     BIT(0)
 220 #define IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG2_2   BIT(1)
 221         uint8_t proto_xtr; /* protocol extraction type */
 222         uint64_t xtr_ol_flag;
 223                 /* flexible descriptor metadata extraction offload flag */
 224         struct iavf_rx_queue_stats stats;
 225         uint64_t offloads;
 226 };
 227
 228 struct iavf_tx_entry {
 229         struct rte_mbuf *mbuf;
 230         uint16_t next_id;
 231         uint16_t last_id;
 232 };
 233
 234 struct iavf_tx_vec_entry {
 235         struct rte_mbuf *mbuf;
 236 };
 237
 238 /* Structure associated with each TX queue. */
 239 struct iavf_tx_queue {
 240         const struct rte_memzone *mz;  /* memzone for Tx ring */
 241         volatile struct iavf_tx_desc *tx_ring; /* Tx ring virtual address */
 242         uint64_t tx_ring_phys_addr;    /* Tx ring DMA address */
 243         struct iavf_tx_entry *sw_ring;  /* address array of SW ring */
 244         uint16_t nb_tx_desc;           /* ring length */
 245         uint16_t tx_tail;              /* current value of tail */
 246         volatile uint8_t *qtx_tail;    /* register address of tail */
 247         /* number of used desc since RS bit set */
 248         uint16_t nb_used;
 249         uint16_t nb_free;
 250         uint16_t last_desc_cleaned;    /* last desc have been cleaned*/
 251         uint16_t free_thresh;
 252         uint16_t rs_thresh;
 253         uint8_t rel_mbufs_type;
 254
 255         uint16_t port_id;
 256         uint16_t queue_id;
 257         uint64_t offloads;
 258         uint16_t next_dd;              /* next to set RS, for VPMD */
 259         uint16_t next_rs;              /* next to check DD,  for VPMD */
 260         uint16_t ipsec_crypto_pkt_md_offset;
 261
 262         bool q_set;                    /* if rx queue has been configured */
 263         bool tx_deferred_start;        /* don't start this queue in dev start */
 264         const struct iavf_txq_ops *ops;
 265 #define IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG1       BIT(0)
 266 #define IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG2       BIT(1)
 267         uint8_t vlan_flag;
 268         uint8_t tc;
 269 };
 270
 271 /* Offload features */
 272 union iavf_tx_offload {
 273         uint64_t data;
 274         struct {
 275                 uint64_t l2_len:7; /* L2 (MAC) Header Length. */
 276                 uint64_t l3_len:9; /* L3 (IP) Header Length. */
 277                 uint64_t l4_len:8; /* L4 Header Length. */
 278                 uint64_t tso_segsz:16; /* TCP TSO segment size */
 279                 /* uint64_t unused : 24; */
 280         };
 281 };
 282
 283 /* Rx Flex Descriptor
 284  * RxDID Profile ID 16-21
 285  * Flex-field 0: RSS hash lower 16-bits
 286  * Flex-field 1: RSS hash upper 16-bits
 287  * Flex-field 2: Flow ID lower 16-bits
 288  * Flex-field 3: Flow ID upper 16-bits
 289  * Flex-field 4: AUX0
 290  * Flex-field 5: AUX1
 291  */
 292 struct iavf_32b_rx_flex_desc_comms {
 293         /* Qword 0 */
 294         u8 rxdid;
 295         u8 mir_id_umb_cast;
 296         __le16 ptype_flexi_flags0;
 297         __le16 pkt_len;
 298         __le16 hdr_len_sph_flex_flags1;
 299
 300         /* Qword 1 */
 301         __le16 status_error0;
 302         __le16 l2tag1;
 303         __le32 rss_hash;
 304
 305         /* Qword 2 */
 306         __le16 status_error1;
 307         u8 flexi_flags2;
 308         u8 ts_low;
 309         __le16 l2tag2_1st;
 310         __le16 l2tag2_2nd;
 311
 312         /* Qword 3 */
 313         __le32 flow_id;
 314         union {
 315                 struct {
 316                         __le16 aux0;
 317                         __le16 aux1;
 318                 } flex;
 319                 __le32 ts_high;
 320         } flex_ts;
 321 };
 322
 323 /* Rx Flex Descriptor
 324  * RxDID Profile ID 22-23 (swap Hash and FlowID)
 325  * Flex-field 0: Flow ID lower 16-bits
 326  * Flex-field 1: Flow ID upper 16-bits
 327  * Flex-field 2: RSS hash lower 16-bits
 328  * Flex-field 3: RSS hash upper 16-bits
 329  * Flex-field 4: AUX0
 330  * Flex-field 5: AUX1
 331  */
 332 struct iavf_32b_rx_flex_desc_comms_ovs {
 333         /* Qword 0 */
 334         u8 rxdid;
 335         u8 mir_id_umb_cast;
 336         __le16 ptype_flexi_flags0;
 337         __le16 pkt_len;
 338         __le16 hdr_len_sph_flex_flags1;
 339
 340         /* Qword 1 */
 341         __le16 status_error0;
 342         __le16 l2tag1;
 343         __le32 flow_id;
 344
 345         /* Qword 2 */
 346         __le16 status_error1;
 347         u8 flexi_flags2;
 348         u8 ts_low;
 349         __le16 l2tag2_1st;
 350         __le16 l2tag2_2nd;
 351
 352         /* Qword 3 */
 353         __le32 rss_hash;
 354         union {
 355                 struct {
 356                         __le16 aux0;
 357                         __le16 aux1;
 358                 } flex;
 359                 __le32 ts_high;
 360         } flex_ts;
 361 };
 362
 363 /* Rx Flex Descriptor
 364  * RxDID Profile ID 24 Inline IPsec
 365  * Flex-field 0: RSS hash lower 16-bits
 366  * Flex-field 1: RSS hash upper 16-bits
 367  * Flex-field 2: Flow ID lower 16-bits
 368  * Flex-field 3: Flow ID upper 16-bits
 369  * Flex-field 4: Inline IPsec SAID lower 16-bits
 370  * Flex-field 5: Inline IPsec SAID upper 16-bits
 371  */
 372 struct iavf_32b_rx_flex_desc_comms_ipsec {
 373         /* Qword 0 */
 374         u8 rxdid;
 375         u8 mir_id_umb_cast;
 376         __le16 ptype_flexi_flags0;
 377         __le16 pkt_len;
 378         __le16 hdr_len_sph_flex_flags1;
 379
 380         /* Qword 1 */
 381         __le16 status_error0;
 382         __le16 l2tag1;
 383         __le32 rss_hash;
 384
 385         /* Qword 2 */
 386         __le16 status_error1;
 387         u8 flexi_flags2;
 388         u8 ts_low;
 389         __le16 l2tag2_1st;
 390         __le16 l2tag2_2nd;
 391
 392         /* Qword 3 */
 393         __le32 flow_id;
 394         __le32 ipsec_said;
 395 };
 396
 397 enum iavf_rxtx_rel_mbufs_type {
 398         IAVF_REL_MBUFS_DEFAULT          = 0,
 399         IAVF_REL_MBUFS_SSE_VEC          = 1,
 400         IAVF_REL_MBUFS_AVX512_VEC       = 2,
 401 };
 402
 403 /* Receive Flex Descriptor profile IDs: There are a total
 404  * of 64 profiles where profile IDs 0/1 are for legacy; and
 405  * profiles 2-63 are flex profiles that can be programmed
 406  * with a specific metadata (profile 7 reserved for HW)
 407  */
 408 enum iavf_rxdid {
 409         IAVF_RXDID_LEGACY_0             = 0,
 410         IAVF_RXDID_LEGACY_1             = 1,
 411         IAVF_RXDID_FLEX_NIC             = 2,
 412         IAVF_RXDID_FLEX_NIC_2           = 6,
 413         IAVF_RXDID_HW                   = 7,
 414         IAVF_RXDID_COMMS_GENERIC        = 16,
 415         IAVF_RXDID_COMMS_AUX_VLAN       = 17,
 416         IAVF_RXDID_COMMS_AUX_IPV4       = 18,
 417         IAVF_RXDID_COMMS_AUX_IPV6       = 19,
 418         IAVF_RXDID_COMMS_AUX_IPV6_FLOW  = 20,
 419         IAVF_RXDID_COMMS_AUX_TCP        = 21,
 420         IAVF_RXDID_COMMS_OVS_1          = 22,
 421         IAVF_RXDID_COMMS_OVS_2          = 23,
 422         IAVF_RXDID_COMMS_IPSEC_CRYPTO   = 24,
 423         IAVF_RXDID_COMMS_AUX_IP_OFFSET  = 25,
 424         IAVF_RXDID_LAST                 = 63,
 425 };
 426
 427 enum iavf_rx_flex_desc_status_error_0_bits {
 428         /* Note: These are predefined bit offsets */
 429         IAVF_RX_FLEX_DESC_STATUS0_DD_S = 0,
 430         IAVF_RX_FLEX_DESC_STATUS0_EOF_S,
 431         IAVF_RX_FLEX_DESC_STATUS0_HBO_S,
 432         IAVF_RX_FLEX_DESC_STATUS0_L3L4P_S,
 433         IAVF_RX_FLEX_DESC_STATUS0_XSUM_IPE_S,
 434         IAVF_RX_FLEX_DESC_STATUS0_XSUM_L4E_S,
 435         IAVF_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S,
 436         IAVF_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S,
 437         IAVF_RX_FLEX_DESC_STATUS0_LPBK_S,
 438         IAVF_RX_FLEX_DESC_STATUS0_IPV6EXADD_S,
 439         IAVF_RX_FLEX_DESC_STATUS0_RXE_S,
 440         IAVF_RX_FLEX_DESC_STATUS0_CRCP_S,
 441         IAVF_RX_FLEX_DESC_STATUS0_RSS_VALID_S,
 442         IAVF_RX_FLEX_DESC_STATUS0_L2TAG1P_S,
 443         IAVF_RX_FLEX_DESC_STATUS0_XTRMD0_VALID_S,
 444         IAVF_RX_FLEX_DESC_STATUS0_XTRMD1_VALID_S,
 445         IAVF_RX_FLEX_DESC_STATUS0_LAST /* this entry must be last!!! */
 446 };
 447
 448 enum iavf_rx_flex_desc_status_error_1_bits {
 449         /* Note: These are predefined bit offsets */
 450         /* Bits 3:0 are reserved for inline ipsec status */
 451         IAVF_RX_FLEX_DESC_STATUS1_IPSEC_CRYPTO_STATUS_0 = 0,
 452         IAVF_RX_FLEX_DESC_STATUS1_IPSEC_CRYPTO_STATUS_1,
 453         IAVF_RX_FLEX_DESC_STATUS1_IPSEC_CRYPTO_STATUS_2,
 454         IAVF_RX_FLEX_DESC_STATUS1_IPSEC_CRYPTO_STATUS_3,
 455         IAVF_RX_FLEX_DESC_STATUS1_NAT_S,
 456         IAVF_RX_FLEX_DESC_STATUS1_IPSEC_CRYPTO_PROCESSED,
 457         /* [10:6] reserved */
 458         IAVF_RX_FLEX_DESC_STATUS1_L2TAG2P_S = 11,
 459         IAVF_RX_FLEX_DESC_STATUS1_XTRMD2_VALID_S = 12,
 460         IAVF_RX_FLEX_DESC_STATUS1_XTRMD3_VALID_S = 13,
 461         IAVF_RX_FLEX_DESC_STATUS1_XTRMD4_VALID_S = 14,
 462         IAVF_RX_FLEX_DESC_STATUS1_XTRMD5_VALID_S = 15,
 463         IAVF_RX_FLEX_DESC_STATUS1_LAST /* this entry must be last!!! */
 464 };
 465
 466 #define IAVF_RX_FLEX_DESC_IPSEC_CRYPTO_STATUS_MASK  (           \
 467         BIT(IAVF_RX_FLEX_DESC_STATUS1_IPSEC_CRYPTO_STATUS_0) |  \
 468         BIT(IAVF_RX_FLEX_DESC_STATUS1_IPSEC_CRYPTO_STATUS_1) |  \
 469         BIT(IAVF_RX_FLEX_DESC_STATUS1_IPSEC_CRYPTO_STATUS_2) |  \
 470         BIT(IAVF_RX_FLEX_DESC_STATUS1_IPSEC_CRYPTO_STATUS_3))
 471
 472 enum iavf_rx_flex_desc_ipsec_crypto_status {
 473         IAVF_IPSEC_CRYPTO_STATUS_SUCCESS = 0,
 474         IAVF_IPSEC_CRYPTO_STATUS_SAD_MISS,
 475         IAVF_IPSEC_CRYPTO_STATUS_NOT_PROCESSED,
 476         IAVF_IPSEC_CRYPTO_STATUS_ICV_CHECK_FAIL,
 477         IAVF_IPSEC_CRYPTO_STATUS_LENGTH_ERR,
 478         /* Reserved */
 479         IAVF_IPSEC_CRYPTO_STATUS_MISC_ERR = 0xF
 480 };
 481
 482
 483
 484 #define IAVF_TXD_DATA_QW1_DTYPE_SHIFT   (0)
 485 #define IAVF_TXD_DATA_QW1_DTYPE_MASK    (0xFUL << IAVF_TXD_QW1_DTYPE_SHIFT)
 486
 487 #define IAVF_TXD_DATA_QW1_CMD_SHIFT     (4)
 488 #define IAVF_TXD_DATA_QW1_CMD_MASK      (0x3FFUL << IAVF_TXD_DATA_QW1_CMD_SHIFT)
 489
 490 #define IAVF_TXD_DATA_QW1_OFFSET_SHIFT  (16)
 491 #define IAVF_TXD_DATA_QW1_OFFSET_MASK   (0x3FFFFULL << \
 492                                         IAVF_TXD_DATA_QW1_OFFSET_SHIFT)
 493
 494 #define IAVF_TXD_DATA_QW1_OFFSET_MACLEN_SHIFT   (IAVF_TXD_DATA_QW1_OFFSET_SHIFT)
 495 #define IAVF_TXD_DATA_QW1_OFFSET_MACLEN_MASK    \
 496         (0x7FUL << IAVF_TXD_DATA_QW1_OFFSET_MACLEN_SHIFT)
 497
 498 #define IAVF_TXD_DATA_QW1_OFFSET_IPLEN_SHIFT    \
 499         (IAVF_TXD_DATA_QW1_OFFSET_SHIFT + IAVF_TX_DESC_LENGTH_IPLEN_SHIFT)
 500 #define IAVF_TXD_DATA_QW1_OFFSET_IPLEN_MASK     \
 501         (0x7FUL << IAVF_TXD_DATA_QW1_OFFSET_IPLEN_SHIFT)
 502
 503 #define IAVF_TXD_DATA_QW1_OFFSET_L4LEN_SHIFT    \
 504         (IAVF_TXD_DATA_QW1_OFFSET_SHIFT + IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
 505 #define IAVF_TXD_DATA_QW1_OFFSET_L4LEN_MASK     \
 506         (0xFUL << IAVF_TXD_DATA_QW1_OFFSET_L4LEN_SHIFT)
 507
 508 #define IAVF_TXD_DATA_QW1_MACLEN_MASK   \
 509         (0x7FUL << IAVF_TX_DESC_LENGTH_MACLEN_SHIFT)
 510 #define IAVF_TXD_DATA_QW1_IPLEN_MASK    \
 511         (0x7FUL << IAVF_TX_DESC_LENGTH_IPLEN_SHIFT)
 512 #define IAVF_TXD_DATA_QW1_L4LEN_MASK    \
 513         (0xFUL << IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
 514 #define IAVF_TXD_DATA_QW1_FCLEN_MASK    \
 515         (0xFUL << IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
 516
 517 #define IAVF_TXD_DATA_QW1_TX_BUF_SZ_SHIFT       (34)
 518 #define IAVF_TXD_DATA_QW1_TX_BUF_SZ_MASK        \
 519         (0x3FFFULL << IAVF_TXD_DATA_QW1_TX_BUF_SZ_SHIFT)
 520
 521 #define IAVF_TXD_DATA_QW1_L2TAG1_SHIFT          (48)
 522 #define IAVF_TXD_DATA_QW1_L2TAG1_MASK           \
 523         (0xFFFFULL << IAVF_TXD_DATA_QW1_L2TAG1_SHIFT)
 524
 525 #define IAVF_TXD_CTX_QW1_IPSEC_PARAMS_CIPHERBLK_SHIFT   (11)
 526 #define IAVF_TXD_CTX_QW1_IPSEC_PARAMS_CIPHERBLK_MASK    \
 527         (0x7UL << IAVF_TXD_CTX_QW1_IPSEC_PARAMS_CIPHERBLK_SHIFT)
 528
 529 #define IAVF_TXD_CTX_QW1_IPSEC_PARAMS_ICVLEN_SHIFT      (14)
 530 #define IAVF_TXD_CTX_QW1_IPSEC_PARAMS_ICVLEN_MASK       \
 531         (0xFUL << IAVF_TXD_CTX_QW1_IPSEC_PARAMS_ICVLEN_SHIFT)
 532
 533 #define IAVF_TXD_CTX_QW1_SEG_PARAMS_TLEN_SHIFT          (30)
 534 #define IAVF_TXD_CTX_QW1_SEG_PARAMS_TLEN_MASK           \
 535         (0x3FFFFUL << IAVF_TXD_CTX_QW1_SEG_PARAMS_TLEN_SHIFT)
 536
 537 #define IAVF_TXD_CTX_QW1_TSYNC_PARAMS_TLEN_SHIFT        (30)
 538 #define IAVF_TXD_CTX_QW1_TSYNC_PARAMS_TLEN_MASK         \
 539         (0x3FUL << IAVF_TXD_CTX_QW1_SEG_PARAMS_TLEN_SHIFT)
 540
 541 #define IAVF_TXD_CTX_QW1_SEG_PARAMS_MSS_SHIFT           (50)
 542 #define IAVF_TXD_CTX_QW1_SEG_PARAMS_MSS_MASK            \
 543         (0x3FFFUL << IAVF_TXD_CTX_QW1_SEG_PARAMS_MSS_SHIFT)
 544
 545 #define IAVF_TXD_CTX_QW0_TUN_PARAMS_EIPT_SHIFT          (0)
 546 #define IAVF_TXD_CTX_QW0_TUN_PARAMS_EIPT_MASK           (0x3UL)
 547
 548 enum iavf_tx_ctx_desc_tunnel_external_ip_type {
 549         IAVF_TX_CTX_DESC_EIPT_NONE,
 550         IAVF_TX_CTX_DESC_EIPT_IPV6,
 551         IAVF_TX_CTX_DESC_EIPT_IPV4_NO_CHECKSUM_OFFLOAD,
 552         IAVF_TX_CTX_DESC_EIPT_IPV4_CHECKSUM_OFFLOAD
 553 };
 554
 555 #define IAVF_TXD_CTX_QW0_TUN_PARAMS_EIPLEN_SHIFT        (2)
 556 #define IAVF_TXD_CTX_QW0_TUN_PARAMS_EIPLEN_MASK         (0x7FUL)
 557
 558 #define IAVF_TXD_CTX_QW0_TUN_PARAMS_L4TUNT_SHIFT        (9)
 559 #define IAVF_TXD_CTX_QW0_TUN_PARAMS_L4TUNT_MASK         (0x3UL)
 560
 561 enum iavf_tx_ctx_desc_tunnel_l4_tunnel_type {
 562         IAVF_TX_CTX_DESC_L4_TUN_TYP_NO_UDP_GRE,
 563         IAVF_TX_CTX_DESC_L4_TUN_TYP_UDP,
 564         IAVF_TX_CTX_DESC_L4_TUN_TYP_GRE
 565 };
 566
 567 #define IAVF_TXD_CTX_QW0_TUN_PARAMS_EIP_NOINC_SHIFT     (11)
 568 #define IAVF_TXD_CTX_QW0_TUN_PARAMS_EIP_NOINC_MASK      (0x1UL)
 569
 570 #define IAVF_TXD_CTX_QW0_TUN_PARAMS_L4TUNLEN_SHIFT      (12)
 571 #define IAVF_TXD_CTX_QW0_TUN_PARAMS_L4TUNLEN_MASK       (0x7FUL)
 572
 573 #define IAVF_TXD_CTX_QW0_TUN_PARAMS_DECTTL_SHIFT        (19)
 574 #define IAVF_TXD_CTX_QW0_TUN_PARAMS_DECTTL_MASK         (0xFUL)
 575
 576 #define IAVF_TXD_CTX_QW0_TUN_PARAMS_L4T_CS_SHIFT        (23)
 577 #define IAVF_TXD_CTX_QW0_TUN_PARAMS_L4T_CS_MASK         (0x1UL)
 578
 579 #define IAVF_TXD_CTX_QW0_L2TAG2_PARAM                   (32)
 580 #define IAVF_TXD_CTX_QW0_L2TAG2_MASK                    (0xFFFFUL)
 581
 582
 583 #define IAVF_RX_FLEX_DESC_IPSEC_CRYPTO_SAID_MASK        (0xFFFFF)
 584
 585 /* for iavf_32b_rx_flex_desc.ptype_flex_flags0 member */
 586 #define IAVF_RX_FLEX_DESC_PTYPE_M       (0x3FF) /* 10-bits */
 587
 588
 589 /* for iavf_32b_rx_flex_desc.ptype_flex_flags0 member */
 590 #define IAVF_RX_FLEX_DESC_PTYPE_M       (0x3FF) /* 10-bits */
 591
 592 /* for iavf_32b_rx_flex_desc.pkt_len member */
 593 #define IAVF_RX_FLX_DESC_PKT_LEN_M      (0x3FFF) /* 14-bits */
 594
 595 int iavf_dev_rx_queue_setup(struct rte_eth_dev *dev,
 596                            uint16_t queue_idx,
 597                            uint16_t nb_desc,
 598                            unsigned int socket_id,
 599                            const struct rte_eth_rxconf *rx_conf,
 600                            struct rte_mempool *mp);
 601
 602 int iavf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
 603 int iavf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
 604 void iavf_dev_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid);
 605
 606 int iavf_dev_tx_queue_setup(struct rte_eth_dev *dev,
 607                            uint16_t queue_idx,
 608                            uint16_t nb_desc,
 609                            unsigned int socket_id,
 610                            const struct rte_eth_txconf *tx_conf);
 611 int iavf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
 612 int iavf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);
 613 int iavf_dev_tx_done_cleanup(void *txq, uint32_t free_cnt);
 614 void iavf_dev_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid);
 615 void iavf_stop_queues(struct rte_eth_dev *dev);
 616 uint16_t iavf_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
 617                        uint16_t nb_pkts);
 618 uint16_t iavf_recv_pkts_flex_rxd(void *rx_queue,
 619                                  struct rte_mbuf **rx_pkts,
 620                                  uint16_t nb_pkts);
 621 uint16_t iavf_recv_scattered_pkts(void *rx_queue,
 622                                  struct rte_mbuf **rx_pkts,
 623                                  uint16_t nb_pkts);
 624 uint16_t iavf_recv_scattered_pkts_flex_rxd(void *rx_queue,
 625                                            struct rte_mbuf **rx_pkts,
 626                                            uint16_t nb_pkts);
 627 uint16_t iavf_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 628                        uint16_t nb_pkts);
 629 uint16_t iavf_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 630                        uint16_t nb_pkts);
 631 void iavf_set_rx_function(struct rte_eth_dev *dev);
 632 void iavf_set_tx_function(struct rte_eth_dev *dev);
 633 void iavf_dev_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
 634                           struct rte_eth_rxq_info *qinfo);
 635 void iavf_dev_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
 636                           struct rte_eth_txq_info *qinfo);
 637 uint32_t iavf_dev_rxq_count(void *rx_queue);
 638 int iavf_dev_rx_desc_status(void *rx_queue, uint16_t offset);
 639 int iavf_dev_tx_desc_status(void *tx_queue, uint16_t offset);
 640
 641 uint16_t iavf_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
 642                            uint16_t nb_pkts);
 643 uint16_t iavf_recv_pkts_vec_flex_rxd(void *rx_queue, struct rte_mbuf **rx_pkts,
 644                                      uint16_t nb_pkts);
 645 uint16_t iavf_recv_scattered_pkts_vec(void *rx_queue,
 646                                      struct rte_mbuf **rx_pkts,
 647                                      uint16_t nb_pkts);
 648 uint16_t iavf_recv_scattered_pkts_vec_flex_rxd(void *rx_queue,
 649                                                struct rte_mbuf **rx_pkts,
 650                                                uint16_t nb_pkts);
 651 uint16_t iavf_xmit_fixed_burst_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
 652                                   uint16_t nb_pkts);
 653 uint16_t iavf_recv_pkts_vec_avx2(void *rx_queue, struct rte_mbuf **rx_pkts,
 654                                  uint16_t nb_pkts);
 655 uint16_t iavf_recv_pkts_vec_avx2_flex_rxd(void *rx_queue,
 656                                           struct rte_mbuf **rx_pkts,
 657                                           uint16_t nb_pkts);
 658 uint16_t iavf_recv_scattered_pkts_vec_avx2(void *rx_queue,
 659                                            struct rte_mbuf **rx_pkts,
 660                                            uint16_t nb_pkts);
 661 uint16_t iavf_recv_scattered_pkts_vec_avx2_flex_rxd(void *rx_queue,
 662                                                     struct rte_mbuf **rx_pkts,
 663                                                     uint16_t nb_pkts);
 664 uint16_t iavf_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
 665                             uint16_t nb_pkts);
 666 uint16_t iavf_xmit_pkts_vec_avx2(void *tx_queue, struct rte_mbuf **tx_pkts,
 667                                  uint16_t nb_pkts);
 668 int iavf_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc);
 669 int iavf_rx_vec_dev_check(struct rte_eth_dev *dev);
 670 int iavf_tx_vec_dev_check(struct rte_eth_dev *dev);
 671 int iavf_rxq_vec_setup(struct iavf_rx_queue *rxq);
 672 int iavf_txq_vec_setup(struct iavf_tx_queue *txq);
 673 uint16_t iavf_recv_pkts_vec_avx512(void *rx_queue, struct rte_mbuf **rx_pkts,
 674                                    uint16_t nb_pkts);
 675 uint16_t iavf_recv_pkts_vec_avx512_offload(void *rx_queue,
 676                                            struct rte_mbuf **rx_pkts,
 677                                            uint16_t nb_pkts);
 678 uint16_t iavf_recv_pkts_vec_avx512_flex_rxd(void *rx_queue,
 679                                             struct rte_mbuf **rx_pkts,
 680                                             uint16_t nb_pkts);
 681 uint16_t iavf_recv_pkts_vec_avx512_flex_rxd_offload(void *rx_queue,
 682                                                     struct rte_mbuf **rx_pkts,
 683                                                     uint16_t nb_pkts);
 684 uint16_t iavf_recv_scattered_pkts_vec_avx512(void *rx_queue,
 685                                              struct rte_mbuf **rx_pkts,
 686                                              uint16_t nb_pkts);
 687 uint16_t iavf_recv_scattered_pkts_vec_avx512_offload(void *rx_queue,
 688                                                      struct rte_mbuf **rx_pkts,
 689                                                      uint16_t nb_pkts);
 690 uint16_t iavf_recv_scattered_pkts_vec_avx512_flex_rxd(void *rx_queue,
 691                                                       struct rte_mbuf **rx_pkts,
 692                                                       uint16_t nb_pkts);
 693 uint16_t iavf_recv_scattered_pkts_vec_avx512_flex_rxd_offload(void *rx_queue,
 694                                                               struct rte_mbuf **rx_pkts,
 695                                                               uint16_t nb_pkts);
 696 uint16_t iavf_xmit_pkts_vec_avx512(void *tx_queue, struct rte_mbuf **tx_pkts,
 697                                    uint16_t nb_pkts);
 698 uint16_t iavf_xmit_pkts_vec_avx512_offload(void *tx_queue,
 699                                            struct rte_mbuf **tx_pkts,
 700                                            uint16_t nb_pkts);
 701 int iavf_txq_vec_setup_avx512(struct iavf_tx_queue *txq);
 702
 703 uint8_t iavf_proto_xtr_type_to_rxdid(uint8_t xtr_type);
 704
 705 void iavf_set_default_ptype_table(struct rte_eth_dev *dev);
 706 void iavf_tx_queue_release_mbufs_avx512(struct iavf_tx_queue *txq);
 707 void iavf_rx_queue_release_mbufs_sse(struct iavf_rx_queue *rxq);
 708 void iavf_tx_queue_release_mbufs_sse(struct iavf_tx_queue *txq);
 709
 710 static inline
 711 void iavf_dump_rx_descriptor(struct iavf_rx_queue *rxq,
 712                             const volatile void *desc,
 713                             uint16_t rx_id)
 714 {
 715 #ifdef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
 716         const volatile union iavf_16byte_rx_desc *rx_desc = desc;
 717
 718         printf("Queue %d Rx_desc %d: QW0: 0x%016"PRIx64" QW1: 0x%016"PRIx64"\n",
 719                rxq->queue_id, rx_id, rx_desc->read.pkt_addr,
 720                rx_desc->read.hdr_addr);
 721 #else
 722         const volatile union iavf_32byte_rx_desc *rx_desc = desc;
 723
 724         printf("Queue %d Rx_desc %d: QW0: 0x%016"PRIx64" QW1: 0x%016"PRIx64
 725                " QW2: 0x%016"PRIx64" QW3: 0x%016"PRIx64"\n", rxq->queue_id,
 726                rx_id, rx_desc->read.pkt_addr, rx_desc->read.hdr_addr,
 727                rx_desc->read.rsvd1, rx_desc->read.rsvd2);
 728 #endif
 729 }
 730
 731 /* All the descriptors are 16 bytes, so just use one of them
 732  * to print the qwords
 733  */
 734 static inline
 735 void iavf_dump_tx_descriptor(const struct iavf_tx_queue *txq,
 736                             const volatile void *desc, uint16_t tx_id)
 737 {
 738         const char *name;
 739         const volatile struct iavf_tx_desc *tx_desc = desc;
 740         enum iavf_tx_desc_dtype_value type;
 741
 742
 743         type = (enum iavf_tx_desc_dtype_value)
 744                 rte_le_to_cpu_64(tx_desc->cmd_type_offset_bsz &
 745                         rte_cpu_to_le_64(IAVF_TXD_DATA_QW1_DTYPE_MASK));
 746         switch (type) {
 747         case IAVF_TX_DESC_DTYPE_DATA:
 748                 name = "Tx_data_desc";
 749                 break;
 750         case IAVF_TX_DESC_DTYPE_CONTEXT:
 751                 name = "Tx_context_desc";
 752                 break;
 753         case IAVF_TX_DESC_DTYPE_IPSEC:
 754                 name = "Tx_IPsec_desc";
 755                 break;
 756         default:
 757                 name = "unknown_desc";
 758                 break;
 759         }
 760
 761         printf("Queue %d %s %d: QW0: 0x%016"PRIx64" QW1: 0x%016"PRIx64"\n",
 762                 txq->queue_id, name, tx_id, tx_desc->buffer_addr,
 763                 tx_desc->cmd_type_offset_bsz);
 764 }
 765
 766 #define FDIR_PROC_ENABLE_PER_QUEUE(ad, on) do { \
 767         int i; \
 768         for (i = 0; i < (ad)->dev_data->nb_rx_queues; i++) { \
 769                 struct iavf_rx_queue *rxq = (ad)->dev_data->rx_queues[i]; \
 770                 if (!rxq) \
 771                         continue; \
 772                 rxq->fdir_enabled = on; \
 773         } \
 774         PMD_DRV_LOG(DEBUG, "FDIR processing on RX set to %d", on); \
 775 } while (0)
 776
 777 /* Enable/disable flow director Rx processing in data path. */
 778 static inline
 779 void iavf_fdir_rx_proc_enable(struct iavf_adapter *ad, bool on)
 780 {
 781         if (on) {
 782                 /* enable flow director processing */
 783                 FDIR_PROC_ENABLE_PER_QUEUE(ad, on);
 784                 ad->fdir_ref_cnt++;
 785         } else {
 786                 if (ad->fdir_ref_cnt >= 1) {
 787                         ad->fdir_ref_cnt--;
 788
 789                         if (ad->fdir_ref_cnt == 0)
 790                                 FDIR_PROC_ENABLE_PER_QUEUE(ad, on);
 791                 }
 792         }
 793 }
 794
 795 static inline
 796 uint64_t iavf_tstamp_convert_32b_64b(uint64_t time, uint32_t in_timestamp)
 797 {
 798         const uint64_t mask = 0xFFFFFFFF;
 799         uint32_t delta;
 800         uint64_t ns;
 801
 802         delta = (in_timestamp - (uint32_t)(time & mask));
 803         if (delta > (mask / 2)) {
 804                 delta = ((uint32_t)(time & mask) - in_timestamp);
 805                 ns = time - delta;
 806         } else {
 807                 ns = time + delta;
 808         }
 809
 810         return ns;
 811 }
 812
 813 #ifdef RTE_LIBRTE_IAVF_DEBUG_DUMP_DESC
 814 #define IAVF_DUMP_RX_DESC(rxq, desc, rx_id) \
 815         iavf_dump_rx_descriptor(rxq, desc, rx_id)
 816 #define IAVF_DUMP_TX_DESC(txq, desc, tx_id) \
 817         iavf_dump_tx_descriptor(txq, desc, tx_id)
 818 #else
 819 #define IAVF_DUMP_RX_DESC(rxq, desc, rx_id) do { } while (0)
 820 #define IAVF_DUMP_TX_DESC(txq, desc, tx_id) do { } while (0)
 821 #endif
 822
 823 #endif /* _IAVF_RXTX_H_ */