1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2019 Intel Corporation
5 #include "iavf_rxtx_vec_common.h"
9 #ifndef __INTEL_COMPILER
10 #pragma GCC diagnostic ignored "-Wcast-qual"
14 iavf_rxq_rearm(struct iavf_rx_queue *rxq)
18 volatile union iavf_rx_desc *rxdp;
19 struct rte_mbuf **rxp = &rxq->sw_ring[rxq->rxrearm_start];
21 rxdp = rxq->rx_ring + rxq->rxrearm_start;
23 /* Pull 'n' more MBUFs into the software ring */
24 if (rte_mempool_get_bulk(rxq->mp,
26 IAVF_RXQ_REARM_THRESH) < 0) {
27 if (rxq->rxrearm_nb + IAVF_RXQ_REARM_THRESH >=
31 dma_addr0 = _mm_setzero_si128();
32 for (i = 0; i < IAVF_VPMD_DESCS_PER_LOOP; i++) {
33 rxp[i] = &rxq->fake_mbuf;
34 _mm_store_si128((__m128i *)&rxdp[i].read,
38 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
39 IAVF_RXQ_REARM_THRESH;
43 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
44 struct rte_mbuf *mb0, *mb1;
45 __m128i dma_addr0, dma_addr1;
46 __m128i hdr_room = _mm_set_epi64x(RTE_PKTMBUF_HEADROOM,
47 RTE_PKTMBUF_HEADROOM);
48 /* Initialize the mbufs in vector, process 2 mbufs in one loop */
49 for (i = 0; i < IAVF_RXQ_REARM_THRESH; i += 2, rxp += 2) {
50 __m128i vaddr0, vaddr1;
55 /* load buf_addr(lo 64bit) and buf_physaddr(hi 64bit) */
56 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, buf_physaddr) !=
57 offsetof(struct rte_mbuf, buf_addr) + 8);
58 vaddr0 = _mm_loadu_si128((__m128i *)&mb0->buf_addr);
59 vaddr1 = _mm_loadu_si128((__m128i *)&mb1->buf_addr);
61 /* convert pa to dma_addr hdr/data */
62 dma_addr0 = _mm_unpackhi_epi64(vaddr0, vaddr0);
63 dma_addr1 = _mm_unpackhi_epi64(vaddr1, vaddr1);
65 /* add headroom to pa values */
66 dma_addr0 = _mm_add_epi64(dma_addr0, hdr_room);
67 dma_addr1 = _mm_add_epi64(dma_addr1, hdr_room);
69 /* flush desc with pa dma_addr */
70 _mm_store_si128((__m128i *)&rxdp++->read, dma_addr0);
71 _mm_store_si128((__m128i *)&rxdp++->read, dma_addr1);
74 struct rte_mbuf *mb0, *mb1, *mb2, *mb3;
75 __m256i dma_addr0_1, dma_addr2_3;
76 __m256i hdr_room = _mm256_set1_epi64x(RTE_PKTMBUF_HEADROOM);
77 /* Initialize the mbufs in vector, process 4 mbufs in one loop */
78 for (i = 0; i < IAVF_RXQ_REARM_THRESH;
79 i += 4, rxp += 4, rxdp += 4) {
80 __m128i vaddr0, vaddr1, vaddr2, vaddr3;
81 __m256i vaddr0_1, vaddr2_3;
88 /* load buf_addr(lo 64bit) and buf_physaddr(hi 64bit) */
89 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, buf_physaddr) !=
90 offsetof(struct rte_mbuf, buf_addr) + 8);
91 vaddr0 = _mm_loadu_si128((__m128i *)&mb0->buf_addr);
92 vaddr1 = _mm_loadu_si128((__m128i *)&mb1->buf_addr);
93 vaddr2 = _mm_loadu_si128((__m128i *)&mb2->buf_addr);
94 vaddr3 = _mm_loadu_si128((__m128i *)&mb3->buf_addr);
97 * merge 0 & 1, by casting 0 to 256-bit and inserting 1
98 * into the high lanes. Similarly for 2 & 3
101 _mm256_inserti128_si256(_mm256_castsi128_si256(vaddr0),
104 _mm256_inserti128_si256(_mm256_castsi128_si256(vaddr2),
107 /* convert pa to dma_addr hdr/data */
108 dma_addr0_1 = _mm256_unpackhi_epi64(vaddr0_1, vaddr0_1);
109 dma_addr2_3 = _mm256_unpackhi_epi64(vaddr2_3, vaddr2_3);
111 /* add headroom to pa values */
112 dma_addr0_1 = _mm256_add_epi64(dma_addr0_1, hdr_room);
113 dma_addr2_3 = _mm256_add_epi64(dma_addr2_3, hdr_room);
115 /* flush desc with pa dma_addr */
116 _mm256_store_si256((__m256i *)&rxdp->read, dma_addr0_1);
117 _mm256_store_si256((__m256i *)&(rxdp + 2)->read, dma_addr2_3);
122 rxq->rxrearm_start += IAVF_RXQ_REARM_THRESH;
123 if (rxq->rxrearm_start >= rxq->nb_rx_desc)
124 rxq->rxrearm_start = 0;
126 rxq->rxrearm_nb -= IAVF_RXQ_REARM_THRESH;
128 rx_id = (uint16_t)((rxq->rxrearm_start == 0) ?
129 (rxq->nb_rx_desc - 1) : (rxq->rxrearm_start - 1));
131 /* Update the tail pointer on the NIC */
132 IAVF_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
135 #define PKTLEN_SHIFT 10
137 static inline uint16_t
138 _iavf_recv_raw_pkts_vec_avx2(struct iavf_rx_queue *rxq,
139 struct rte_mbuf **rx_pkts,
140 uint16_t nb_pkts, uint8_t *split_packet)
142 #define IAVF_DESCS_PER_LOOP_AVX 8
144 /* const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl; */
145 const uint32_t *type_table = rxq->vsi->adapter->ptype_tbl;
147 const __m256i mbuf_init = _mm256_set_epi64x(0, 0,
148 0, rxq->mbuf_initializer);
149 /* struct iavf_rx_entry *sw_ring = &rxq->sw_ring[rxq->rx_tail]; */
150 struct rte_mbuf **sw_ring = &rxq->sw_ring[rxq->rx_tail];
151 volatile union iavf_rx_desc *rxdp = rxq->rx_ring + rxq->rx_tail;
152 const int avx_aligned = ((rxq->rx_tail & 1) == 0);
156 /* nb_pkts has to be floor-aligned to IAVF_DESCS_PER_LOOP_AVX */
157 nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, IAVF_DESCS_PER_LOOP_AVX);
159 /* See if we need to rearm the RX queue - gives the prefetch a bit
162 if (rxq->rxrearm_nb > IAVF_RXQ_REARM_THRESH)
165 /* Before we start moving massive data around, check to see if
166 * there is actually a packet available
168 if (!(rxdp->wb.qword1.status_error_len &
169 rte_cpu_to_le_32(1 << IAVF_RX_DESC_STATUS_DD_SHIFT)))
172 /* constants used in processing loop */
173 const __m256i crc_adjust =
175 (/* first descriptor */
176 0, 0, 0, /* ignore non-length fields */
177 -rxq->crc_len, /* sub crc on data_len */
178 0, /* ignore high-16bits of pkt_len */
179 -rxq->crc_len, /* sub crc on pkt_len */
180 0, 0, /* ignore pkt_type field */
181 /* second descriptor */
182 0, 0, 0, /* ignore non-length fields */
183 -rxq->crc_len, /* sub crc on data_len */
184 0, /* ignore high-16bits of pkt_len */
185 -rxq->crc_len, /* sub crc on pkt_len */
186 0, 0 /* ignore pkt_type field */
189 /* 8 packets DD mask, LSB in each 32-bit value */
190 const __m256i dd_check = _mm256_set1_epi32(1);
192 /* 8 packets EOP mask, second-LSB in each 32-bit value */
193 const __m256i eop_check = _mm256_slli_epi32(dd_check,
194 IAVF_RX_DESC_STATUS_EOF_SHIFT);
196 /* mask to shuffle from desc. to mbuf (2 descriptors)*/
197 const __m256i shuf_msk =
199 (/* first descriptor */
200 7, 6, 5, 4, /* octet 4~7, 32bits rss */
201 3, 2, /* octet 2~3, low 16 bits vlan_macip */
202 15, 14, /* octet 15~14, 16 bits data_len */
203 0xFF, 0xFF, /* skip high 16 bits pkt_len, zero out */
204 15, 14, /* octet 15~14, low 16 bits pkt_len */
205 0xFF, 0xFF, /* pkt_type set as unknown */
206 0xFF, 0xFF, /*pkt_type set as unknown */
207 /* second descriptor */
208 7, 6, 5, 4, /* octet 4~7, 32bits rss */
209 3, 2, /* octet 2~3, low 16 bits vlan_macip */
210 15, 14, /* octet 15~14, 16 bits data_len */
211 0xFF, 0xFF, /* skip high 16 bits pkt_len, zero out */
212 15, 14, /* octet 15~14, low 16 bits pkt_len */
213 0xFF, 0xFF, /* pkt_type set as unknown */
214 0xFF, 0xFF /*pkt_type set as unknown */
217 * compile-time check the above crc and shuffle layout is correct.
218 * NOTE: the first field (lowest address) is given last in set_epi
221 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
222 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);
223 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=
224 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);
225 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, vlan_tci) !=
226 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 10);
227 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, hash) !=
228 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 12);
230 /* Status/Error flag masks */
232 * mask everything except RSS, flow director and VLAN flags
233 * bit2 is for VLAN tag, bit11 for flow director indication
234 * bit13:12 for RSS indication. Bits 3-5 of error
235 * field (bits 22-24) are for IP/L4 checksum errors
237 const __m256i flags_mask =
238 _mm256_set1_epi32((1 << 2) | (1 << 11) |
239 (3 << 12) | (7 << 22));
241 * data to be shuffled by result of flag mask. If VLAN bit is set,
242 * (bit 2), then position 4 in this array will be used in the
245 const __m256i vlan_flags_shuf =
246 _mm256_set_epi32(0, 0, PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED, 0,
247 0, 0, PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED, 0);
249 * data to be shuffled by result of flag mask, shifted down 11.
250 * If RSS/FDIR bits are set, shuffle moves appropriate flags in
253 const __m256i rss_flags_shuf =
254 _mm256_set_epi8(0, 0, 0, 0, 0, 0, 0, 0,
255 PKT_RX_RSS_HASH | PKT_RX_FDIR, PKT_RX_RSS_HASH,
256 0, 0, 0, 0, PKT_RX_FDIR, 0,/* end up 128-bits */
257 0, 0, 0, 0, 0, 0, 0, 0,
258 PKT_RX_RSS_HASH | PKT_RX_FDIR, PKT_RX_RSS_HASH,
259 0, 0, 0, 0, PKT_RX_FDIR, 0);
262 * data to be shuffled by the result of the flags mask shifted by 22
263 * bits. This gives use the l3_l4 flags.
265 const __m256i l3_l4_flags_shuf = _mm256_set_epi8(0, 0, 0, 0, 0, 0, 0, 0,
266 /* shift right 1 bit to make sure it not exceed 255 */
267 (PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD |
268 PKT_RX_IP_CKSUM_BAD) >> 1,
269 (PKT_RX_IP_CKSUM_GOOD | PKT_RX_EIP_CKSUM_BAD |
270 PKT_RX_L4_CKSUM_BAD) >> 1,
271 (PKT_RX_EIP_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,
272 (PKT_RX_IP_CKSUM_GOOD | PKT_RX_EIP_CKSUM_BAD) >> 1,
273 (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,
274 (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD) >> 1,
275 PKT_RX_IP_CKSUM_BAD >> 1,
276 (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD) >> 1,
277 /* second 128-bits */
278 0, 0, 0, 0, 0, 0, 0, 0,
279 (PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD |
280 PKT_RX_IP_CKSUM_BAD) >> 1,
281 (PKT_RX_IP_CKSUM_GOOD | PKT_RX_EIP_CKSUM_BAD |
282 PKT_RX_L4_CKSUM_BAD) >> 1,
283 (PKT_RX_EIP_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,
284 (PKT_RX_IP_CKSUM_GOOD | PKT_RX_EIP_CKSUM_BAD) >> 1,
285 (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,
286 (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD) >> 1,
287 PKT_RX_IP_CKSUM_BAD >> 1,
288 (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD) >> 1);
290 const __m256i cksum_mask =
291 _mm256_set1_epi32(PKT_RX_IP_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD |
292 PKT_RX_L4_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD |
293 PKT_RX_EIP_CKSUM_BAD);
295 RTE_SET_USED(avx_aligned); /* for 32B descriptors we don't use this */
297 uint16_t i, received;
299 for (i = 0, received = 0; i < nb_pkts;
300 i += IAVF_DESCS_PER_LOOP_AVX,
301 rxdp += IAVF_DESCS_PER_LOOP_AVX) {
302 /* step 1, copy over 8 mbuf pointers to rx_pkts array */
303 _mm256_storeu_si256((void *)&rx_pkts[i],
304 _mm256_loadu_si256((void *)&sw_ring[i]));
305 #ifdef RTE_ARCH_X86_64
307 ((void *)&rx_pkts[i + 4],
308 _mm256_loadu_si256((void *)&sw_ring[i + 4]));
311 __m256i raw_desc0_1, raw_desc2_3, raw_desc4_5, raw_desc6_7;
312 #ifdef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
313 /* for AVX we need alignment otherwise loads are not atomic */
315 /* load in descriptors, 2 at a time, in reverse order */
316 raw_desc6_7 = _mm256_load_si256((void *)(rxdp + 6));
317 rte_compiler_barrier();
318 raw_desc4_5 = _mm256_load_si256((void *)(rxdp + 4));
319 rte_compiler_barrier();
320 raw_desc2_3 = _mm256_load_si256((void *)(rxdp + 2));
321 rte_compiler_barrier();
322 raw_desc0_1 = _mm256_load_si256((void *)(rxdp + 0));
326 const __m128i raw_desc7 =
327 _mm_load_si128((void *)(rxdp + 7));
328 rte_compiler_barrier();
329 const __m128i raw_desc6 =
330 _mm_load_si128((void *)(rxdp + 6));
331 rte_compiler_barrier();
332 const __m128i raw_desc5 =
333 _mm_load_si128((void *)(rxdp + 5));
334 rte_compiler_barrier();
335 const __m128i raw_desc4 =
336 _mm_load_si128((void *)(rxdp + 4));
337 rte_compiler_barrier();
338 const __m128i raw_desc3 =
339 _mm_load_si128((void *)(rxdp + 3));
340 rte_compiler_barrier();
341 const __m128i raw_desc2 =
342 _mm_load_si128((void *)(rxdp + 2));
343 rte_compiler_barrier();
344 const __m128i raw_desc1 =
345 _mm_load_si128((void *)(rxdp + 1));
346 rte_compiler_barrier();
347 const __m128i raw_desc0 =
348 _mm_load_si128((void *)(rxdp + 0));
351 _mm256_inserti128_si256
352 (_mm256_castsi128_si256(raw_desc6),
355 _mm256_inserti128_si256
356 (_mm256_castsi128_si256(raw_desc4),
359 _mm256_inserti128_si256
360 (_mm256_castsi128_si256(raw_desc2),
363 _mm256_inserti128_si256
364 (_mm256_castsi128_si256(raw_desc0),
371 for (j = 0; j < IAVF_DESCS_PER_LOOP_AVX; j++)
372 rte_mbuf_prefetch_part2(rx_pkts[i + j]);
376 * convert descriptors 4-7 into mbufs, adjusting length and
377 * re-arranging fields. Then write into the mbuf
379 const __m256i len6_7 = _mm256_slli_epi32(raw_desc6_7,
381 const __m256i len4_5 = _mm256_slli_epi32(raw_desc4_5,
383 const __m256i desc6_7 = _mm256_blend_epi16(raw_desc6_7,
385 const __m256i desc4_5 = _mm256_blend_epi16(raw_desc4_5,
387 __m256i mb6_7 = _mm256_shuffle_epi8(desc6_7, shuf_msk);
388 __m256i mb4_5 = _mm256_shuffle_epi8(desc4_5, shuf_msk);
390 mb6_7 = _mm256_add_epi16(mb6_7, crc_adjust);
391 mb4_5 = _mm256_add_epi16(mb4_5, crc_adjust);
393 * to get packet types, shift 64-bit values down 30 bits
394 * and so ptype is in lower 8-bits in each
396 const __m256i ptypes6_7 = _mm256_srli_epi64(desc6_7, 30);
397 const __m256i ptypes4_5 = _mm256_srli_epi64(desc4_5, 30);
398 const uint8_t ptype7 = _mm256_extract_epi8(ptypes6_7, 24);
399 const uint8_t ptype6 = _mm256_extract_epi8(ptypes6_7, 8);
400 const uint8_t ptype5 = _mm256_extract_epi8(ptypes4_5, 24);
401 const uint8_t ptype4 = _mm256_extract_epi8(ptypes4_5, 8);
403 mb6_7 = _mm256_insert_epi32(mb6_7, type_table[ptype7], 4);
404 mb6_7 = _mm256_insert_epi32(mb6_7, type_table[ptype6], 0);
405 mb4_5 = _mm256_insert_epi32(mb4_5, type_table[ptype5], 4);
406 mb4_5 = _mm256_insert_epi32(mb4_5, type_table[ptype4], 0);
407 /* merge the status bits into one register */
408 const __m256i status4_7 = _mm256_unpackhi_epi32(desc6_7,
412 * convert descriptors 0-3 into mbufs, adjusting length and
413 * re-arranging fields. Then write into the mbuf
415 const __m256i len2_3 = _mm256_slli_epi32(raw_desc2_3,
417 const __m256i len0_1 = _mm256_slli_epi32(raw_desc0_1,
419 const __m256i desc2_3 = _mm256_blend_epi16(raw_desc2_3,
421 const __m256i desc0_1 = _mm256_blend_epi16(raw_desc0_1,
423 __m256i mb2_3 = _mm256_shuffle_epi8(desc2_3, shuf_msk);
424 __m256i mb0_1 = _mm256_shuffle_epi8(desc0_1, shuf_msk);
426 mb2_3 = _mm256_add_epi16(mb2_3, crc_adjust);
427 mb0_1 = _mm256_add_epi16(mb0_1, crc_adjust);
428 /* get the packet types */
429 const __m256i ptypes2_3 = _mm256_srli_epi64(desc2_3, 30);
430 const __m256i ptypes0_1 = _mm256_srli_epi64(desc0_1, 30);
431 const uint8_t ptype3 = _mm256_extract_epi8(ptypes2_3, 24);
432 const uint8_t ptype2 = _mm256_extract_epi8(ptypes2_3, 8);
433 const uint8_t ptype1 = _mm256_extract_epi8(ptypes0_1, 24);
434 const uint8_t ptype0 = _mm256_extract_epi8(ptypes0_1, 8);
436 mb2_3 = _mm256_insert_epi32(mb2_3, type_table[ptype3], 4);
437 mb2_3 = _mm256_insert_epi32(mb2_3, type_table[ptype2], 0);
438 mb0_1 = _mm256_insert_epi32(mb0_1, type_table[ptype1], 4);
439 mb0_1 = _mm256_insert_epi32(mb0_1, type_table[ptype0], 0);
440 /* merge the status bits into one register */
441 const __m256i status0_3 = _mm256_unpackhi_epi32(desc2_3,
445 * take the two sets of status bits and merge to one
446 * After merge, the packets status flags are in the
447 * order (hi->lo): [1, 3, 5, 7, 0, 2, 4, 6]
449 __m256i status0_7 = _mm256_unpacklo_epi64(status4_7,
452 /* now do flag manipulation */
454 /* get only flag/error bits we want */
455 const __m256i flag_bits =
456 _mm256_and_si256(status0_7, flags_mask);
457 /* set vlan and rss flags */
458 const __m256i vlan_flags =
459 _mm256_shuffle_epi8(vlan_flags_shuf, flag_bits);
460 const __m256i rss_flags =
461 _mm256_shuffle_epi8(rss_flags_shuf,
462 _mm256_srli_epi32(flag_bits, 11));
464 * l3_l4_error flags, shuffle, then shift to correct adjustment
465 * of flags in flags_shuf, and finally mask out extra bits
467 __m256i l3_l4_flags = _mm256_shuffle_epi8(l3_l4_flags_shuf,
468 _mm256_srli_epi32(flag_bits, 22));
469 l3_l4_flags = _mm256_slli_epi32(l3_l4_flags, 1);
470 l3_l4_flags = _mm256_and_si256(l3_l4_flags, cksum_mask);
473 const __m256i mbuf_flags = _mm256_or_si256(l3_l4_flags,
474 _mm256_or_si256(rss_flags, vlan_flags));
476 * At this point, we have the 8 sets of flags in the low 16-bits
477 * of each 32-bit value in vlan0.
478 * We want to extract these, and merge them with the mbuf init
479 * data so we can do a single write to the mbuf to set the flags
480 * and all the other initialization fields. Extracting the
481 * appropriate flags means that we have to do a shift and blend
482 * for each mbuf before we do the write. However, we can also
483 * add in the previously computed rx_descriptor fields to
484 * make a single 256-bit write per mbuf
486 /* check the structure matches expectations */
487 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, ol_flags) !=
488 offsetof(struct rte_mbuf, rearm_data) + 8);
489 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, rearm_data) !=
490 RTE_ALIGN(offsetof(struct rte_mbuf,
493 /* build up data and do writes */
494 __m256i rearm0, rearm1, rearm2, rearm3, rearm4, rearm5,
496 rearm6 = _mm256_blend_epi32(mbuf_init,
497 _mm256_slli_si256(mbuf_flags, 8),
499 rearm4 = _mm256_blend_epi32(mbuf_init,
500 _mm256_slli_si256(mbuf_flags, 4),
502 rearm2 = _mm256_blend_epi32(mbuf_init, mbuf_flags, 0x04);
503 rearm0 = _mm256_blend_epi32(mbuf_init,
504 _mm256_srli_si256(mbuf_flags, 4),
506 /* permute to add in the rx_descriptor e.g. rss fields */
507 rearm6 = _mm256_permute2f128_si256(rearm6, mb6_7, 0x20);
508 rearm4 = _mm256_permute2f128_si256(rearm4, mb4_5, 0x20);
509 rearm2 = _mm256_permute2f128_si256(rearm2, mb2_3, 0x20);
510 rearm0 = _mm256_permute2f128_si256(rearm0, mb0_1, 0x20);
512 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 6]->rearm_data,
514 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 4]->rearm_data,
516 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 2]->rearm_data,
518 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 0]->rearm_data,
521 /* repeat for the odd mbufs */
522 const __m256i odd_flags =
523 _mm256_castsi128_si256
524 (_mm256_extracti128_si256(mbuf_flags, 1));
525 rearm7 = _mm256_blend_epi32(mbuf_init,
526 _mm256_slli_si256(odd_flags, 8),
528 rearm5 = _mm256_blend_epi32(mbuf_init,
529 _mm256_slli_si256(odd_flags, 4),
531 rearm3 = _mm256_blend_epi32(mbuf_init, odd_flags, 0x04);
532 rearm1 = _mm256_blend_epi32(mbuf_init,
533 _mm256_srli_si256(odd_flags, 4),
535 /* since odd mbufs are already in hi 128-bits use blend */
536 rearm7 = _mm256_blend_epi32(rearm7, mb6_7, 0xF0);
537 rearm5 = _mm256_blend_epi32(rearm5, mb4_5, 0xF0);
538 rearm3 = _mm256_blend_epi32(rearm3, mb2_3, 0xF0);
539 rearm1 = _mm256_blend_epi32(rearm1, mb0_1, 0xF0);
540 /* again write to mbufs */
541 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 7]->rearm_data,
543 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 5]->rearm_data,
545 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 3]->rearm_data,
547 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 1]->rearm_data,
550 /* extract and record EOP bit */
552 const __m128i eop_mask =
553 _mm_set1_epi16(1 << IAVF_RX_DESC_STATUS_EOF_SHIFT);
554 const __m256i eop_bits256 = _mm256_and_si256(status0_7,
556 /* pack status bits into a single 128-bit register */
557 const __m128i eop_bits =
559 (_mm256_castsi256_si128(eop_bits256),
560 _mm256_extractf128_si256(eop_bits256,
563 * flip bits, and mask out the EOP bit, which is now
564 * a split-packet bit i.e. !EOP, rather than EOP one.
566 __m128i split_bits = _mm_andnot_si128(eop_bits,
569 * eop bits are out of order, so we need to shuffle them
570 * back into order again. In doing so, only use low 8
571 * bits, which acts like another pack instruction
572 * The original order is (hi->lo): 1,3,5,7,0,2,4,6
573 * [Since we use epi8, the 16-bit positions are
574 * multiplied by 2 in the eop_shuffle value.]
576 __m128i eop_shuffle =
577 _mm_set_epi8(/* zero hi 64b */
578 0xFF, 0xFF, 0xFF, 0xFF,
579 0xFF, 0xFF, 0xFF, 0xFF,
580 /* move values to lo 64b */
583 split_bits = _mm_shuffle_epi8(split_bits, eop_shuffle);
584 *(uint64_t *)split_packet =
585 _mm_cvtsi128_si64(split_bits);
586 split_packet += IAVF_DESCS_PER_LOOP_AVX;
589 /* perform dd_check */
590 status0_7 = _mm256_and_si256(status0_7, dd_check);
591 status0_7 = _mm256_packs_epi32(status0_7,
592 _mm256_setzero_si256());
594 uint64_t burst = __builtin_popcountll
596 (_mm256_extracti128_si256
598 burst += __builtin_popcountll
600 (_mm256_castsi256_si128(status0_7)));
602 if (burst != IAVF_DESCS_PER_LOOP_AVX)
606 /* update tail pointers */
607 rxq->rx_tail += received;
608 rxq->rx_tail &= (rxq->nb_rx_desc - 1);
609 if ((rxq->rx_tail & 1) == 1 && received > 1) { /* keep avx2 aligned */
613 rxq->rxrearm_nb += received;
619 * - nb_pkts < IAVF_DESCS_PER_LOOP, just return no packet
622 iavf_recv_pkts_vec_avx2(void *rx_queue, struct rte_mbuf **rx_pkts,
625 return _iavf_recv_raw_pkts_vec_avx2(rx_queue, rx_pkts, nb_pkts, NULL);
629 * vPMD receive routine that reassembles single burst of 32 scattered packets
631 * - nb_pkts < IAVF_DESCS_PER_LOOP, just return no packet
634 iavf_recv_scattered_burst_vec_avx2(void *rx_queue, struct rte_mbuf **rx_pkts,
637 struct iavf_rx_queue *rxq = rx_queue;
638 uint8_t split_flags[IAVF_VPMD_RX_MAX_BURST] = {0};
640 /* get some new buffers */
641 uint16_t nb_bufs = _iavf_recv_raw_pkts_vec_avx2(rxq, rx_pkts, nb_pkts,
646 /* happy day case, full burst + no packets to be joined */
647 const uint64_t *split_fl64 = (uint64_t *)split_flags;
649 if (!rxq->pkt_first_seg &&
650 split_fl64[0] == 0 && split_fl64[1] == 0 &&
651 split_fl64[2] == 0 && split_fl64[3] == 0)
654 /* reassemble any packets that need reassembly*/
657 if (!rxq->pkt_first_seg) {
658 /* find the first split flag, and only reassemble then*/
659 while (i < nb_bufs && !split_flags[i])
663 rxq->pkt_first_seg = rx_pkts[i];
665 return i + reassemble_packets(rxq, &rx_pkts[i], nb_bufs - i,
670 * vPMD receive routine that reassembles scattered packets.
671 * Main receive routine that can handle arbitrary burst sizes
673 * - nb_pkts < IAVF_DESCS_PER_LOOP, just return no packet
676 iavf_recv_scattered_pkts_vec_avx2(void *rx_queue, struct rte_mbuf **rx_pkts,
681 while (nb_pkts > IAVF_VPMD_RX_MAX_BURST) {
682 uint16_t burst = iavf_recv_scattered_burst_vec_avx2(rx_queue,
683 rx_pkts + retval, IAVF_VPMD_RX_MAX_BURST);
686 if (burst < IAVF_VPMD_RX_MAX_BURST)
689 return retval + iavf_recv_scattered_burst_vec_avx2(rx_queue,
690 rx_pkts + retval, nb_pkts);
694 iavf_vtx1(volatile struct iavf_tx_desc *txdp,
695 struct rte_mbuf *pkt, uint64_t flags)
698 (IAVF_TX_DESC_DTYPE_DATA |
699 ((uint64_t)flags << IAVF_TXD_QW1_CMD_SHIFT) |
700 ((uint64_t)pkt->data_len << IAVF_TXD_QW1_TX_BUF_SZ_SHIFT));
702 __m128i descriptor = _mm_set_epi64x(high_qw,
703 pkt->buf_physaddr + pkt->data_off);
704 _mm_store_si128((__m128i *)txdp, descriptor);
708 iavf_vtx(volatile struct iavf_tx_desc *txdp,
709 struct rte_mbuf **pkt, uint16_t nb_pkts, uint64_t flags)
711 const uint64_t hi_qw_tmpl = (IAVF_TX_DESC_DTYPE_DATA |
712 ((uint64_t)flags << IAVF_TXD_QW1_CMD_SHIFT));
714 /* if unaligned on 32-bit boundary, do one to align */
715 if (((uintptr_t)txdp & 0x1F) != 0 && nb_pkts != 0) {
716 iavf_vtx1(txdp, *pkt, flags);
717 nb_pkts--, txdp++, pkt++;
720 /* do two at a time while possible, in bursts */
721 for (; nb_pkts > 3; txdp += 4, pkt += 4, nb_pkts -= 4) {
724 ((uint64_t)pkt[3]->data_len <<
725 IAVF_TXD_QW1_TX_BUF_SZ_SHIFT);
728 ((uint64_t)pkt[2]->data_len <<
729 IAVF_TXD_QW1_TX_BUF_SZ_SHIFT);
732 ((uint64_t)pkt[1]->data_len <<
733 IAVF_TXD_QW1_TX_BUF_SZ_SHIFT);
736 ((uint64_t)pkt[0]->data_len <<
737 IAVF_TXD_QW1_TX_BUF_SZ_SHIFT);
742 pkt[3]->buf_physaddr + pkt[3]->data_off,
744 pkt[2]->buf_physaddr + pkt[2]->data_off);
748 pkt[1]->buf_physaddr + pkt[1]->data_off,
750 pkt[0]->buf_physaddr + pkt[0]->data_off);
751 _mm256_store_si256((void *)(txdp + 2), desc2_3);
752 _mm256_store_si256((void *)txdp, desc0_1);
755 /* do any last ones */
757 iavf_vtx1(txdp, *pkt, flags);
758 txdp++, pkt++, nb_pkts--;
762 static inline uint16_t
763 iavf_xmit_fixed_burst_vec_avx2(void *tx_queue, struct rte_mbuf **tx_pkts,
766 struct iavf_tx_queue *txq = (struct iavf_tx_queue *)tx_queue;
767 volatile struct iavf_tx_desc *txdp;
768 struct iavf_tx_entry *txep;
769 uint16_t n, nb_commit, tx_id;
770 /* bit2 is reserved and must be set to 1 according to Spec */
771 uint64_t flags = IAVF_TX_DESC_CMD_EOP | IAVF_TX_DESC_CMD_ICRC;
772 uint64_t rs = IAVF_TX_DESC_CMD_RS | flags;
774 /* cross rx_thresh boundary is not allowed */
775 nb_pkts = RTE_MIN(nb_pkts, txq->rs_thresh);
777 if (txq->nb_free < txq->free_thresh)
778 iavf_tx_free_bufs(txq);
780 nb_commit = nb_pkts = (uint16_t)RTE_MIN(txq->nb_free, nb_pkts);
781 if (unlikely(nb_pkts == 0))
784 tx_id = txq->tx_tail;
785 txdp = &txq->tx_ring[tx_id];
786 txep = &txq->sw_ring[tx_id];
788 txq->nb_free = (uint16_t)(txq->nb_free - nb_pkts);
790 n = (uint16_t)(txq->nb_tx_desc - tx_id);
791 if (nb_commit >= n) {
792 tx_backlog_entry(txep, tx_pkts, n);
794 iavf_vtx(txdp, tx_pkts, n - 1, flags);
798 iavf_vtx1(txdp, *tx_pkts++, rs);
800 nb_commit = (uint16_t)(nb_commit - n);
803 txq->next_rs = (uint16_t)(txq->rs_thresh - 1);
805 /* avoid reach the end of ring */
806 txdp = &txq->tx_ring[tx_id];
807 txep = &txq->sw_ring[tx_id];
810 tx_backlog_entry(txep, tx_pkts, nb_commit);
812 iavf_vtx(txdp, tx_pkts, nb_commit, flags);
814 tx_id = (uint16_t)(tx_id + nb_commit);
815 if (tx_id > txq->next_rs) {
816 txq->tx_ring[txq->next_rs].cmd_type_offset_bsz |=
817 rte_cpu_to_le_64(((uint64_t)IAVF_TX_DESC_CMD_RS) <<
818 IAVF_TXD_QW1_CMD_SHIFT);
820 (uint16_t)(txq->next_rs + txq->rs_thresh);
823 txq->tx_tail = tx_id;
825 IAVF_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
831 iavf_xmit_pkts_vec_avx2(void *tx_queue, struct rte_mbuf **tx_pkts,
835 struct iavf_tx_queue *txq = (struct iavf_tx_queue *)tx_queue;
840 num = (uint16_t)RTE_MIN(nb_pkts, txq->rs_thresh);
841 ret = iavf_xmit_fixed_burst_vec_avx2(tx_queue, &tx_pkts[nb_tx],